VM fault report. Driver vendor: X.Org Device vendor: AMD Device name: AMD TONGA (DRM 3.1.0, LLVM 3.9.0) Failing VM page: 0x002309be Buffer list (in units of pages = 4kB):  Size VM start page VM end page Usage 16 0x0000000100214 0x0000000100224 BORDER_COLORS 1 0x0000000100224 0x0000000100225 IB2 4 -- hole -- 32768 0x0000000100229 0x0000000108229 COMPUTE_GLOBAL 2 -- hole -- 32768 0x000000010822b 0x000000011022b COMPUTE_GLOBAL 2989 -- hole -- 1 0x0000000110dd8 0x0000000110dd9 QUERY 1 0x0000000110dd9 0x0000000110dda QUERY 5 -- hole -- 1 0x0000000110ddf 0x0000000110de0 QUERY 26 -- hole -- 1 0x0000000110dfa 0x0000000110dfb TRACE 23975 -- hole -- 2912 0x0000000116ba2 0x0000000117702 SCRATCH_BUFFER 76 0x0000000117702 0x000000011774e USER_SHADER 1 0x000000011774e 0x000000011774f CONST_BUFFER Note: The holes represent memory not used by the IB. Other buffers can still be allocated there. ------------------ IB2: Init config begin ------------------ CONTEXT_CONTROL: 0x80000000 0x80000000 SET_CONTEXT_REG: VGT_HOS_MAX_TESS_LEVEL <- 64.0f (0x42800000) VGT_HOS_MIN_TESS_LEVEL <- 0 SET_CONTEXT_REG: VGT_GS_PER_ES <- GS_PER_ES = 128 (0x80) VGT_ES_PER_GS <- ES_PER_GS = 64 (0x40) VGT_GS_PER_VS <- GS_PER_VS = 2 SET_CONTEXT_REG: VGT_PRIMITIVEID_RESET <- 0 SET_CONTEXT_REG: VGT_STRMOUT_DRAW_OPAQUE_OFFSET <- 0 SET_CONTEXT_REG: VGT_STRMOUT_BUFFER_CONFIG <- STREAM_0_BUFFER_EN = 0 STREAM_1_BUFFER_EN = 0 STREAM_2_BUFFER_EN = 0 STREAM_3_BUFFER_EN = 0 SET_CONTEXT_REG: VGT_VTX_CNT_EN <- VTX_CNT_EN = 0 SET_CONTEXT_REG: PA_SC_CENTROID_PRIORITY_0 <- DISTANCE_0 = 0 DISTANCE_1 = 1 DISTANCE_2 = 2 DISTANCE_3 = 3 DISTANCE_4 = 4 DISTANCE_5 = 5 DISTANCE_6 = 6 DISTANCE_7 = 7 PA_SC_CENTROID_PRIORITY_1 <- DISTANCE_8 = 8 DISTANCE_9 = 9 DISTANCE_10 = 10 (0xa) DISTANCE_11 = 11 (0xb) DISTANCE_12 = 12 (0xc) DISTANCE_13 = 13 (0xd) DISTANCE_14 = 14 (0xe) DISTANCE_15 = 15 (0xf) SET_CONTEXT_REG: PA_SU_PRIM_FILTER_CNTL <- TRIANGLE_FILTER_DISABLE = 0 LINE_FILTER_DISABLE = 0 POINT_FILTER_DISABLE = 0 RECTANGLE_FILTER_DISABLE = 0 TRIANGLE_EXPAND_ENA = 0 LINE_EXPAND_ENA = 0 POINT_EXPAND_ENA = 0 RECTANGLE_EXPAND_ENA = 0 PRIM_EXPAND_CONSTANT = 0 XMAX_RIGHT_EXCLUSION = 0 YMAX_BOTTOM_EXCLUSION = 0 SET_CONTEXT_REG: PA_SC_VPORT_ZMIN_0 <- 0 PA_SC_VPORT_ZMAX_0 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_1 <- 0 PA_SC_VPORT_ZMAX_1 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_2 <- 0 PA_SC_VPORT_ZMAX_2 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_3 <- 0 PA_SC_VPORT_ZMAX_3 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_4 <- 0 PA_SC_VPORT_ZMAX_4 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_5 <- 0 PA_SC_VPORT_ZMAX_5 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_6 <- 0 PA_SC_VPORT_ZMAX_6 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_7 <- 0 PA_SC_VPORT_ZMAX_7 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_8 <- 0 PA_SC_VPORT_ZMAX_8 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_9 <- 0 PA_SC_VPORT_ZMAX_9 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_10 <- 0 PA_SC_VPORT_ZMAX_10 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_11 <- 0 PA_SC_VPORT_ZMAX_11 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_12 <- 0 PA_SC_VPORT_ZMAX_12 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_13 <- 0 PA_SC_VPORT_ZMAX_13 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_14 <- 0 PA_SC_VPORT_ZMAX_14 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_15 <- 0 PA_SC_VPORT_ZMAX_15 <- 1.0f (0x3f800000) PA_SC_RASTER_CONFIG <- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2 RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_0 RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_1 RB_XSEL = 0 RB_YSEL = 0 PKR_MAP = RASTER_CONFIG_PKR_MAP_0 PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0 PKR_YSEL = RASTER_CONFIG_PKR_YSEL_0 PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0 SC_MAP = RASTER_CONFIG_SC_MAP_0 SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE SE_MAP = RASTER_CONFIG_SE_MAP_2 SE_XSEL = RASTER_CONFIG_SE_XSEL_16_WIDE_TILE SE_YSEL = RASTER_CONFIG_SE_YSEL_16_WIDE_TILE PA_SC_RASTER_CONFIG_1 <- SE_PAIR_MAP = RASTER_CONFIG_SE_PAIR_MAP_2 SE_PAIR_XSEL = RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE SE_PAIR_YSEL = RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 SET_CONTEXT_REG: PA_SC_GENERIC_SCISSOR_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 PA_SC_GENERIC_SCISSOR_BR <- BR_X = 16384 (0x4000) BR_Y = 16384 (0x4000) SET_CONTEXT_REG: PA_SC_SCREEN_SCISSOR_TL <- TL_X = 0 TL_Y = 0 PA_SC_SCREEN_SCISSOR_BR <- BR_X = 16384 (0x4000) BR_Y = 16384 (0x4000) SET_CONTEXT_REG: PA_SC_CLIPRECT_RULE <- CLIP_RULE = 0xffff SET_CONTEXT_REG: PA_SC_EDGERULE <- ER_TRI = 10 (0xa) ER_POINT = 10 (0xa) ER_RECT = 10 (0xa) ER_LINE_LR = 42 (0x2a) ER_LINE_RL = 42 (0x2a) ER_LINE_TB = 10 (0xa) ER_LINE_BT = 10 (0xa) PA_SU_HARDWARE_SCREEN_OFFSET <- HW_SCREEN_OFFSET_X = 0 HW_SCREEN_OFFSET_Y = 0 SET_CONTEXT_REG: PA_CL_NANINF_CNTL <- VTE_XY_INF_DISCARD = 0 VTE_Z_INF_DISCARD = 0 VTE_W_INF_DISCARD = 0 VTE_0XNANINF_IS_0 = 0 VTE_XY_NAN_RETAIN = 0 VTE_Z_NAN_RETAIN = 0 VTE_W_NAN_RETAIN = 0 VTE_W_RECIP_NAN_IS_0 = 0 VS_XY_NAN_TO_INF = 0 VS_XY_INF_RETAIN = 0 VS_Z_NAN_TO_INF = 0 VS_Z_INF_RETAIN = 0 VS_W_NAN_TO_INF = 0 VS_W_INF_RETAIN = 0 VS_CLIP_DIST_INF_DISCARD = 0 VTE_NO_OUTPUT_NEG_0 = 0 SET_CONTEXT_REG: PA_CL_GB_VERT_CLIP_ADJ <- 1.0f (0x3f800000) PA_CL_GB_VERT_DISC_ADJ <- 1.0f (0x3f800000) PA_CL_GB_HORZ_CLIP_ADJ <- 1.0f (0x3f800000) PA_CL_GB_HORZ_DISC_ADJ <- 1.0f (0x3f800000) SET_CONTEXT_REG: DB_SRESULTS_COMPARE_STATE0 <- COMPAREFUNC0 = REF_NEVER COMPAREVALUE0 = 0 COMPAREMASK0 = 0 ENABLE0 = 0 DB_SRESULTS_COMPARE_STATE1 <- COMPAREFUNC1 = REF_NEVER COMPAREVALUE1 = 0 COMPAREMASK1 = 0 ENABLE1 = 0 DB_PRELOAD_CONTROL <- START_X = 0 START_Y = 0 MAX_X = 0 MAX_Y = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE <- FORCE_HIZ_ENABLE = FORCE_OFF FORCE_HIS_ENABLE0 = FORCE_DISABLE FORCE_HIS_ENABLE1 = FORCE_DISABLE FORCE_SHADER_Z_ORDER = 0 FAST_Z_DISABLE = 0 FAST_STENCIL_DISABLE = 0 NOOP_CULL_DISABLE = 0 FORCE_COLOR_KILL = 0 FORCE_Z_READ = 0 FORCE_STENCIL_READ = 0 FORCE_FULL_Z_RANGE = FORCE_OFF FORCE_QC_SMASK_CONFLICT = 0 DISABLE_VIEWPORT_CLAMP = 0 IGNORE_SC_ZRANGE = 0 DISABLE_FULLY_COVERED = 0 FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF MAX_TILES_IN_DTT = 0 DISABLE_TILE_RATE_TILES = 0 FORCE_Z_DIRTY = 0 FORCE_STENCIL_DIRTY = 0 FORCE_Z_VALID = 0 FORCE_STENCIL_VALID = 0 PRESERVE_COMPRESSION = 0 SET_CONTEXT_REG: VGT_MAX_VTX_INDX <- 0xffffffff VGT_MIN_VTX_INDX <- 0 VGT_INDX_OFFSET <- 0 SET_SH_REG: SPI_SHADER_PGM_RSRC3_HS <- WAVE_LIMIT = 0 LOCK_LOW_THRESHOLD = 0 GROUP_FIFO_DEPTH = 0 SET_SH_REG: SPI_SHADER_PGM_RSRC3_ES <- CU_EN = 0xffff WAVE_LIMIT = 0 LOCK_LOW_THRESHOLD = 0 GROUP_FIFO_DEPTH = 0 SET_SH_REG: SPI_SHADER_PGM_RSRC3_GS <- CU_EN = 0xffff WAVE_LIMIT = 0 LOCK_LOW_THRESHOLD = 0 GROUP_FIFO_DEPTH = 0 SET_SH_REG: SPI_SHADER_PGM_RSRC3_LS <- CU_EN = 0xfffe WAVE_LIMIT = 0 LOCK_LOW_THRESHOLD = 0 GROUP_FIFO_DEPTH = 0 SET_SH_REG: SPI_SHADER_PGM_RSRC3_VS <- CU_EN = 0xfffe WAVE_LIMIT = 0 LOCK_LOW_THRESHOLD = 0 SPI_SHADER_LATE_ALLOC_VS <- LIMIT = 31 (0x1f) SET_SH_REG: SPI_SHADER_PGM_RSRC3_PS <- CU_EN = 0xffff WAVE_LIMIT = 0 LOCK_LOW_THRESHOLD = 0 SET_CONTEXT_REG: CB_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 OVERWRITE_COMBINER_MRT_SHARING_DISABLE = 1 OVERWRITE_COMBINER_WATERMARK = 4 SET_CONTEXT_REG: VGT_VERTEX_REUSE_BLOCK_CNTL <- VTX_REUSE_DEPTH = 30 (0x1e) VGT_OUT_DEALLOC_CNTL <- DEALLOC_DIST = 32 (0x20) SET_CONTEXT_REG: TA_BC_BASE_ADDR <- 0x01002140 TA_BC_BASE_ADDR_HI <- ADDRESS = 0 ------------------- IB2: Init config end ------------------- ------------------ IB begin ------------------ WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x10dfa000 DST_ADDR_HI <- 1 0x00000001 NOP: Trace point ID: 1 This trace point was reached by the CP. INDIRECT_BUFFER_CIK: 0x00224000 0x00000001 0x00000090 EVENT_WRITE_EOP: 0x00000514 0x10dd9000 0x60000001 0x00000000 0x00000000 CONTEXT_CONTROL: 0x80000000 0x80000000 EVENT_WRITE_EOP: 0x0000052d 0x00000000 0x00000000 0x00000000 0x00000000 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = CACHE_FLUSH EVENT_INDEX <- 7 INV_L2 <- 1 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 1 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 1 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 1 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_SH_REG: COMPUTE_USER_DATA_0 <- 0x1774e000 COMPUTE_USER_DATA_1 <- 1 COMPUTE_USER_DATA_2 <- 0x16ba2000 COMPUTE_USER_DATA_3 <- 0x00900001 SET_SH_REG: COMPUTE_START_X <- 0 COMPUTE_START_Y <- 0 COMPUTE_START_Z <- 0 COMPUTE_NUM_THREAD_X <- NUM_THREAD_FULL = 256 (0x0100) NUM_THREAD_PARTIAL = 0 COMPUTE_NUM_THREAD_Y <- NUM_THREAD_FULL = 1 NUM_THREAD_PARTIAL = 0 COMPUTE_NUM_THREAD_Z <- NUM_THREAD_FULL = 1 NUM_THREAD_PARTIAL = 0 SET_SH_REG: COMPUTE_PGM_LO <- 0x01177053 COMPUTE_PGM_HI <- DATA = 0 INST_ATC = 0 SET_SH_REG: COMPUTE_PGM_RSRC1 <- VGPRS = 63 (0x3f) SGPRS = 9 PRIORITY = 0 FLOAT_MODE = 192 (0xc0) PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 BULKY = 0 CDBG_USER = 0 COMPUTE_PGM_RSRC2 <- SCRATCH_EN = 1 USER_SGPR = 2 TRAP_PRESENT = 0 TGID_X_EN = 1 TGID_Y_EN = 0 TGID_Z_EN = 0 TG_SIZE_EN = 0 TIDIG_COMP_CNT = 0 EXCP_EN_MSB = 0 LDS_SIZE = 0 EXCP_EN = 0 SET_SH_REG: COMPUTE_RESOURCE_LIMITS <- WAVES_PER_SH = 0 WAVES_PER_SH_CIK = 0 TG_PER_CU = 0 LOCK_THRESHOLD = 0 SIMD_DEST_CNTL = 0 FORCE_SIMD_DIST = 0 CU_GROUP_COUNT = 0 COMPUTE_STATIC_THREAD_MGMT_SE0 <- SH0_CU_EN = 0xffff SH1_CU_EN = 0xffff COMPUTE_STATIC_THREAD_MGMT_SE1 <- SH0_CU_EN = 0xffff SH1_CU_EN = 0xffff COMPUTE_TMPRING_SIZE <- WAVES = 896 (0x380) WAVESIZE = 9 DISPATCH_DIRECT: 0x00000200 0x00000001 0x00000001 0x00000001 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = CS_PARTIAL_FLUSH EVENT_INDEX <- 4 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 0 CB1_DEST_BASE_ENA = 0 CB2_DEST_BASE_ENA = 0 CB3_DEST_BASE_ENA = 0 CB4_DEST_BASE_ENA = 0 CB5_DEST_BASE_ENA = 0 CB6_DEST_BASE_ENA = 0 CB7_DEST_BASE_ENA = 0 DB_DEST_BASE_ENA = 0 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 1 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 0 DB_ACTION_ENA = 0 SH_KCACHE_ACTION_ENA = 1 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 1 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) EVENT_WRITE_EOP: 0x00000514 0x10dd8000 0x60000001 0x00000000 0x00000000 EVENT_WRITE_EOP: 0x00000514 0x10ddf000 0x60000001 0x00000000 0x00000000 CONTEXT_CONTROL: 0x80000000 0x80000000 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = CACHE_FLUSH EVENT_INDEX <- 7 INV_L2 <- 1 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 0 CB1_DEST_BASE_ENA = 0 CB2_DEST_BASE_ENA = 0 CB3_DEST_BASE_ENA = 0 CB4_DEST_BASE_ENA = 0 CB5_DEST_BASE_ENA = 0 CB6_DEST_BASE_ENA = 0 CB7_DEST_BASE_ENA = 0 DB_DEST_BASE_ENA = 0 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 1 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 0 DB_ACTION_ENA = 0 SH_KCACHE_ACTION_ENA = 1 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 1 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) EVENT_WRITE_EOP: 0x0000052d 0x00000000 0x00000000 0x00000000 0x00000000 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = PS_PARTIAL_FLUSH EVENT_INDEX <- 4 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 1 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x10dfa000 DST_ADDR_HI <- 1 0x00000002 NOP: Trace point ID: 2 !!!!! This is the last trace point that was reached by the CP !!!!! ------------------- IB end -------------------