From cac1aae72cd6cd33b2f463e6bdec3d14bd7a2705 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 11 Mar 2016 14:52:47 +0100 Subject: [PATCH] drm/radeon: fix CU harvest programming MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marek Olšák --- drivers/gpu/drm/radeon/si.c | 36 +++++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 07037e3..273aa90 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -2991,27 +2991,36 @@ static void si_setup_spi(struct radeon_device *rdev, u32 se_num, u32 sh_per_se, u32 cu_per_sh) { - int i, j, k; - u32 data, mask, active_cu; + int i, j; + u32 active_cu, bit, compute_se[2] = {0,0}; for (i = 0; i < se_num; i++) { for (j = 0; j < sh_per_se; j++) { si_select_se_sh(rdev, i, j); - data = RREG32(SPI_STATIC_THREAD_MGMT_3); active_cu = si_get_cu_enabled(rdev, cu_per_sh); - mask = 1; - for (k = 0; k < 16; k++) { - mask <<= k; - if (active_cu & mask) { - data &= ~mask; - WREG32(SPI_STATIC_THREAD_MGMT_3, data); - break; - } - } + WREG32(SPI_STATIC_THREAD_MGMT_1, + (active_cu) | (active_cu << 16)); + WREG32(SPI_STATIC_THREAD_MGMT_2, + (active_cu) | (active_cu << 16)); + printk("(%i,%i)SPI_STATIC_THREAD_MGMT_1/2 = 0x%08x\n", + i, j, (active_cu) | (active_cu << 16)); + + compute_se[i] |= active_cu << (16 * j); + + /* Clear one bit for LS & HS to avoid a hw deadlock */ + bit = ffs(active_cu); + if (bit) + active_cu &= ~(1 << (bit - 1)); + WREG32(SPI_STATIC_THREAD_MGMT_3, active_cu); + printk("(%i,%i)SPI_STATIC_THREAD_MGMT_3 = 0x%04x\n", + i, j, active_cu); } } si_select_se_sh(rdev, 0xffffffff, 0xffffffff); + + /*WREG32(COMPUTE_STATIC_THREAD_MGMT_SE0, compute_se[0]); + WREG32(COMPUTE_STATIC_THREAD_MGMT_SE1, compute_se[1]);*/ } static u32 si_get_rb_disabled(struct radeon_device *rdev, @@ -4424,9 +4433,6 @@ static bool si_vm_reg_valid(u32 reg) case PA_SC_LINE_STIPPLE_STATE: case PA_SC_ENHANCE: case SQC_CACHES: - case SPI_STATIC_THREAD_MGMT_1: - case SPI_STATIC_THREAD_MGMT_2: - case SPI_STATIC_THREAD_MGMT_3: case SPI_PS_MAX_WAVE_ID: case SPI_CONFIG_CNTL: case SPI_CONFIG_CNTL_1: -- 2.5.0