Driver vendor: X.Org Device vendor: AMD Device name: AMD TAHITI (DRM 2.43.0, LLVM 3.7.1) draw_info: {indexed = 0, mode = quads, start = 0, count = 4, start_instance = 0, instance_count = 1, vertices_per_patch = 0, index_bias = 0, min_index = 0, max_index = 3, primitive_restart = 0, restart_index = 0, count_from_stream_output = NULL, indirect = NULL, indirect_offset = 0, } vertex_buffer 0: {stride = 32, buffer_offset = 0, buffer = 0x021c3b50, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 1048576, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 3, bind = 16, flags = 3, } num vertex elements = 2 vertex_element 0: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } vertex_element 1: {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } num stream output targets = 0 begin shader: VERTEX shader_state: {tokens = " VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ", } end shader: VERTEX viewport_state 0: {scale = {128, 128, 1, }, translate = {128, 128, 0, }, } rasterizer_state: {flatshade = 0, light_twoside = 0, clamp_vertex_color = 0, clamp_fragment_color = 0, front_ccw = 0, cull_face = 0, fill_front = 0, fill_back = 0, offset_point = 0, offset_line = 0, offset_tri = 0, scissor = 0, poly_smooth = 0, poly_stipple_enable = 0, point_smooth = 0, sprite_coord_enable = 0, sprite_coord_mode = 0, point_quad_rasterization = 0, point_tri_clip = 0, point_size_per_vertex = 0, multisample = 0, line_smooth = 0, line_stipple_enable = 0, line_stipple_factor = 0, line_stipple_pattern = 0, line_last_pixel = 0, flatshade_first = 0, half_pixel_center = 0, bottom_edge_rule = 0, rasterizer_discard = 1, depth_clip = 0, clip_halfz = 0, clip_plane_enable = 0, line_width = 0, point_size = 0, offset_units = 0, offset_scale = 0, offset_clamp = 0, } depth_stencil_alpha_state: {depth = {enabled = 0, }, stencil = {{enabled = 0, }, {enabled = 0, }, }, alpha = {enabled = 0, }, } stencil_ref: {ref_value = {0, 0, }, } blend_state: {dither = 0, alpha_to_coverage = 0, alpha_to_one = 0, logicop_enable = 0, independent_blend_enable = 0, rt = {{blend_enable = 0, colormask = 15, }, }, } blend_color: {color = {0, 0, 0, 0, }, } min_samples = 0 sample_mask = 0xffffffff framebuffer_state: {width = 256, height = 256, nr_cbufs = 1, cbufs = {0x021ae740, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, zsbuf = NULL, } cbufs[0]: surface: {format = PIPE_FORMAT_R8G8B8A8_UNORM, width = 256, height = 256, texture = 0x021bed00, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, } resource: {target = 2d, format = PIPE_FORMAT_R8G8B8A8_UNORM, width0 = 256, height0 = 256, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 10, flags = 0, } ***************************************************************************** Driver-specific state: Memory-mapped registers: GRBM_STATUS <- ME0PIPE0_CMDFIFO_AVAIL = 8 SRBM_RQ_PENDING = 1 ME0PIPE0_CF_RQ_PENDING = 0 ME0PIPE0_PF_RQ_PENDING = 0 GDS_DMA_RQ_PENDING = 0 DB_CLEAN = 1 CB_CLEAN = 1 TA_BUSY = 0 GDS_BUSY = 0 WD_BUSY_NO_DMA = 0 VGT_BUSY = 1 IA_BUSY_NO_DMA = 0 IA_BUSY = 0 SX_BUSY = 1 WD_BUSY = 0 SPI_BUSY = 1 BCI_BUSY = 0 SC_BUSY = 1 PA_BUSY = 1 DB_BUSY = 0 CP_COHERENCY_BUSY = 0 CP_BUSY = 1 CB_BUSY = 0 GUI_ACTIVE = 1 Color buffer 0: Info: npix_x=256, npix_y=256, npix_z=1, blk_w=1, blk_h=1, blk_d=1, array_size=1, last_level=0, bpe=4, nsamples=1, flags=0x100301, r8g8b8a8_unorm Layout: size=262144, alignment=32768, bankw=1, bankh=1, nbanks=0, mtilea=1, tilesplit=512, pipeconfig=0, scanout=0 CMask: offset=0, size=2048, alignment=2048, pitch=512, height=256, xalign=512, yalign=256, slice_tile_max=7 Level[0]: offset=0, slice_size=262144, npix_x=256, npix_y=256, npix_z=1, nblk_x=256, nblk_y=256, nblk_z=1, pitch_bytes=1024, mode=3 SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 Vertex Shader as VS: Shader main disassembly: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C0800900 s_load_dwordx4 s[4:7], s[8:9], 0x4 ; C0820904 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100 buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 32, 0, 0, 0, v5, v6, v7, v8 ; F800020F 08070605 exp 15, 12, 0, 1, 0, v1, v2, v3, v4 ; F80008CF 04030201 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 12 Code Size: 56 bytes LDS: 0 blocks Scratch: 0 bytes per wave Max Waves: 10 ******************** Buffer list (in units of pages = 4kB): Size VM start page VM end page Usage 16 0x0000000000810 0x0000000000820 BORDER_COLORS 2 -- hole -- 1 0x0000000000822 0x0000000000823 TRACE 1 0x0000000000823 0x0000000000824 CMASK 1 -- hole -- 1 0x0000000000825 0x0000000000826 QUERY 1 0x0000000000826 0x0000000000827 USER_SHADER 1 -- hole -- 64 0x0000000000828 0x0000000000868 COLOR_BUFFER 256 0x0000000000868 0x0000000000968 CONST_BUFFER, DESCRIPTORS 256 0x0000000000968 0x0000000000a68 VERTEX_BUFFER Note: The holes represent memory not used by the IB. Other buffers can still be allocated there. ------------------ IB2: Init config begin ------------------ CONTEXT_CONTROL: 0x80000000 0x80000000 SET_CONTEXT_REG: VGT_HOS_MAX_TESS_LEVEL <- 64.0f (0x42800000) VGT_HOS_MIN_TESS_LEVEL <- 0 SET_CONTEXT_REG: VGT_GS_PER_ES <- GS_PER_ES = 128 (0x80) VGT_ES_PER_GS <- ES_PER_GS = 64 (0x40) VGT_GS_PER_VS <- GS_PER_VS = 2 SET_CONTEXT_REG: VGT_PRIMITIVEID_RESET <- 0 SET_CONTEXT_REG: VGT_STRMOUT_DRAW_OPAQUE_OFFSET <- 0 SET_CONTEXT_REG: VGT_STRMOUT_BUFFER_CONFIG <- STREAM_0_BUFFER_EN = 0 STREAM_1_BUFFER_EN = 0 STREAM_2_BUFFER_EN = 0 STREAM_3_BUFFER_EN = 0 SET_CONTEXT_REG: VGT_VTX_CNT_EN <- VTX_CNT_EN = 0 SET_CONFIG_REG: PA_CL_ENHANCE <- CLIP_VTX_REORDER_ENA = 1 NUM_CLIP_SEQ = 3 CLIPPED_PRIM_SEQ_STALL = 0 VE_NAN_PROC_DISABLE = 0 SET_CONTEXT_REG: PA_SC_CENTROID_PRIORITY_0 <- DISTANCE_0 = 0 DISTANCE_1 = 1 DISTANCE_2 = 2 DISTANCE_3 = 3 DISTANCE_4 = 4 DISTANCE_5 = 5 DISTANCE_6 = 6 DISTANCE_7 = 7 PA_SC_CENTROID_PRIORITY_1 <- DISTANCE_8 = 8 DISTANCE_9 = 9 DISTANCE_10 = 10 (0xa) DISTANCE_11 = 11 (0xb) DISTANCE_12 = 12 (0xc) DISTANCE_13 = 13 (0xd) DISTANCE_14 = 14 (0xe) DISTANCE_15 = 15 (0xf) SET_CONTEXT_REG: PA_SU_PRIM_FILTER_CNTL <- TRIANGLE_FILTER_DISABLE = 0 LINE_FILTER_DISABLE = 0 POINT_FILTER_DISABLE = 0 RECTANGLE_FILTER_DISABLE = 0 TRIANGLE_EXPAND_ENA = 0 LINE_EXPAND_ENA = 0 POINT_EXPAND_ENA = 0 RECTANGLE_EXPAND_ENA = 0 PRIM_EXPAND_CONSTANT = 0 XMAX_RIGHT_EXCLUSION = 0 YMAX_BOTTOM_EXCLUSION = 0 SET_CONTEXT_REG: PA_SC_VPORT_ZMIN_0 <- 0 PA_SC_VPORT_ZMAX_0 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_1 <- 0 PA_SC_VPORT_ZMAX_1 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_2 <- 0 PA_SC_VPORT_ZMAX_2 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_3 <- 0 PA_SC_VPORT_ZMAX_3 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_4 <- 0 PA_SC_VPORT_ZMAX_4 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_5 <- 0 PA_SC_VPORT_ZMAX_5 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_6 <- 0 PA_SC_VPORT_ZMAX_6 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_7 <- 0 PA_SC_VPORT_ZMAX_7 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_8 <- 0 PA_SC_VPORT_ZMAX_8 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_9 <- 0 PA_SC_VPORT_ZMAX_9 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_10 <- 0 PA_SC_VPORT_ZMAX_10 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_11 <- 0 PA_SC_VPORT_ZMAX_11 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_12 <- 0 PA_SC_VPORT_ZMAX_12 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_13 <- 0 PA_SC_VPORT_ZMAX_13 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_14 <- 0 PA_SC_VPORT_ZMAX_14 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_15 <- 0 PA_SC_VPORT_ZMAX_15 <- 1.0f (0x3f800000) PA_SC_RASTER_CONFIG <- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2 RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_2 RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_2 RB_XSEL = 1 RB_YSEL = 0 PKR_MAP = RASTER_CONFIG_PKR_MAP_2 PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0 PKR_YSEL = RASTER_CONFIG_PKR_YSEL_1 PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0 SC_MAP = RASTER_CONFIG_SC_MAP_0 SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE SE_MAP = RASTER_CONFIG_SE_MAP_2 SE_XSEL = RASTER_CONFIG_SE_XSEL_32_WIDE_TILE SE_YSEL = RASTER_CONFIG_SE_YSEL_32_WIDE_TILE SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 SET_CONTEXT_REG: PA_SC_GENERIC_SCISSOR_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 PA_SC_GENERIC_SCISSOR_BR <- BR_X = 16384 (0x4000) BR_Y = 16384 (0x4000) SET_CONTEXT_REG: PA_SC_SCREEN_SCISSOR_TL <- TL_X = 0 TL_Y = 0 PA_SC_SCREEN_SCISSOR_BR <- BR_X = 16384 (0x4000) BR_Y = 16384 (0x4000) SET_CONTEXT_REG: PA_SC_CLIPRECT_RULE <- CLIP_RULE = 0xffff SET_CONTEXT_REG: PA_SC_EDGERULE <- ER_TRI = 10 (0xa) ER_POINT = 10 (0xa) ER_RECT = 10 (0xa) ER_LINE_LR = 42 (0x2a) ER_LINE_RL = 42 (0x2a) ER_LINE_TB = 10 (0xa) ER_LINE_BT = 10 (0xa) PA_SU_HARDWARE_SCREEN_OFFSET <- HW_SCREEN_OFFSET_X = 0 HW_SCREEN_OFFSET_Y = 0 SET_CONTEXT_REG: PA_CL_NANINF_CNTL <- VTE_XY_INF_DISCARD = 0 VTE_Z_INF_DISCARD = 0 VTE_W_INF_DISCARD = 0 VTE_0XNANINF_IS_0 = 0 VTE_XY_NAN_RETAIN = 0 VTE_Z_NAN_RETAIN = 0 VTE_W_NAN_RETAIN = 0 VTE_W_RECIP_NAN_IS_0 = 0 VS_XY_NAN_TO_INF = 0 VS_XY_INF_RETAIN = 0 VS_Z_NAN_TO_INF = 0 VS_Z_INF_RETAIN = 0 VS_W_NAN_TO_INF = 0 VS_W_INF_RETAIN = 0 VS_CLIP_DIST_INF_DISCARD = 0 VTE_NO_OUTPUT_NEG_0 = 0 SET_CONTEXT_REG: PA_CL_GB_VERT_CLIP_ADJ <- 1.0f (0x3f800000) PA_CL_GB_VERT_DISC_ADJ <- 1.0f (0x3f800000) PA_CL_GB_HORZ_CLIP_ADJ <- 1.0f (0x3f800000) PA_CL_GB_HORZ_DISC_ADJ <- 1.0f (0x3f800000) SET_CONTEXT_REG: DB_SRESULTS_COMPARE_STATE0 <- COMPAREFUNC0 = REF_NEVER COMPAREVALUE0 = 0 COMPAREMASK0 = 0 ENABLE0 = 0 DB_SRESULTS_COMPARE_STATE1 <- COMPAREFUNC1 = REF_NEVER COMPAREVALUE1 = 0 COMPAREMASK1 = 0 ENABLE1 = 0 DB_PRELOAD_CONTROL <- START_X = 0 START_Y = 0 MAX_X = 0 MAX_Y = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE <- FORCE_HIZ_ENABLE = FORCE_OFF FORCE_HIS_ENABLE0 = FORCE_DISABLE FORCE_HIS_ENABLE1 = FORCE_DISABLE FORCE_SHADER_Z_ORDER = 0 FAST_Z_DISABLE = 0 FAST_STENCIL_DISABLE = 0 NOOP_CULL_DISABLE = 0 FORCE_COLOR_KILL = 0 FORCE_Z_READ = 0 FORCE_STENCIL_READ = 0 FORCE_FULL_Z_RANGE = FORCE_OFF FORCE_QC_SMASK_CONFLICT = 0 DISABLE_VIEWPORT_CLAMP = 0 IGNORE_SC_ZRANGE = 0 DISABLE_FULLY_COVERED = 0 FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF MAX_TILES_IN_DTT = 0 DISABLE_TILE_RATE_TILES = 0 FORCE_Z_DIRTY = 0 FORCE_STENCIL_DIRTY = 0 FORCE_Z_VALID = 0 FORCE_STENCIL_VALID = 0 PRESERVE_COMPRESSION = 0 SET_CONTEXT_REG: VGT_MAX_VTX_INDX <- 0xffffffff VGT_MIN_VTX_INDX <- 0 VGT_INDX_OFFSET <- 0 SET_CONTEXT_REG: TA_BC_BASE_ADDR <- 0x00008100 ------------------- IB2: Init config end ------------------- ------------------ IB begin ------------------ WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x00822000 DST_ADDR_HI <- 0 0x00000001 NOP: Trace point ID: 1 This trace point was reached by the CP. CONTEXT_CONTROL: 0x80000000 0x80000000 SET_CONTEXT_REG: VGT_HOS_MAX_TESS_LEVEL <- 64.0f (0x42800000) VGT_HOS_MIN_TESS_LEVEL <- 0 SET_CONTEXT_REG: VGT_GS_PER_ES <- GS_PER_ES = 128 (0x80) VGT_ES_PER_GS <- ES_PER_GS = 64 (0x40) VGT_GS_PER_VS <- GS_PER_VS = 2 SET_CONTEXT_REG: VGT_PRIMITIVEID_RESET <- 0 SET_CONTEXT_REG: VGT_STRMOUT_DRAW_OPAQUE_OFFSET <- 0 SET_CONTEXT_REG: VGT_STRMOUT_BUFFER_CONFIG <- STREAM_0_BUFFER_EN = 0 STREAM_1_BUFFER_EN = 0 STREAM_2_BUFFER_EN = 0 STREAM_3_BUFFER_EN = 0 SET_CONTEXT_REG: VGT_VTX_CNT_EN <- VTX_CNT_EN = 0 SET_CONFIG_REG: PA_CL_ENHANCE <- CLIP_VTX_REORDER_ENA = 1 NUM_CLIP_SEQ = 3 CLIPPED_PRIM_SEQ_STALL = 0 VE_NAN_PROC_DISABLE = 0 SET_CONTEXT_REG: PA_SC_CENTROID_PRIORITY_0 <- DISTANCE_0 = 0 DISTANCE_1 = 1 DISTANCE_2 = 2 DISTANCE_3 = 3 DISTANCE_4 = 4 DISTANCE_5 = 5 DISTANCE_6 = 6 DISTANCE_7 = 7 PA_SC_CENTROID_PRIORITY_1 <- DISTANCE_8 = 8 DISTANCE_9 = 9 DISTANCE_10 = 10 (0xa) DISTANCE_11 = 11 (0xb) DISTANCE_12 = 12 (0xc) DISTANCE_13 = 13 (0xd) DISTANCE_14 = 14 (0xe) DISTANCE_15 = 15 (0xf) SET_CONTEXT_REG: PA_SU_PRIM_FILTER_CNTL <- TRIANGLE_FILTER_DISABLE = 0 LINE_FILTER_DISABLE = 0 POINT_FILTER_DISABLE = 0 RECTANGLE_FILTER_DISABLE = 0 TRIANGLE_EXPAND_ENA = 0 LINE_EXPAND_ENA = 0 POINT_EXPAND_ENA = 0 RECTANGLE_EXPAND_ENA = 0 PRIM_EXPAND_CONSTANT = 0 XMAX_RIGHT_EXCLUSION = 0 YMAX_BOTTOM_EXCLUSION = 0 SET_CONTEXT_REG: PA_SC_VPORT_ZMIN_0 <- 0 PA_SC_VPORT_ZMAX_0 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_1 <- 0 PA_SC_VPORT_ZMAX_1 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_2 <- 0 PA_SC_VPORT_ZMAX_2 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_3 <- 0 PA_SC_VPORT_ZMAX_3 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_4 <- 0 PA_SC_VPORT_ZMAX_4 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_5 <- 0 PA_SC_VPORT_ZMAX_5 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_6 <- 0 PA_SC_VPORT_ZMAX_6 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_7 <- 0 PA_SC_VPORT_ZMAX_7 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_8 <- 0 PA_SC_VPORT_ZMAX_8 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_9 <- 0 PA_SC_VPORT_ZMAX_9 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_10 <- 0 PA_SC_VPORT_ZMAX_10 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_11 <- 0 PA_SC_VPORT_ZMAX_11 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_12 <- 0 PA_SC_VPORT_ZMAX_12 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_13 <- 0 PA_SC_VPORT_ZMAX_13 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_14 <- 0 PA_SC_VPORT_ZMAX_14 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_15 <- 0 PA_SC_VPORT_ZMAX_15 <- 1.0f (0x3f800000) PA_SC_RASTER_CONFIG <- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2 RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_2 RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_2 RB_XSEL = 1 RB_YSEL = 0 PKR_MAP = RASTER_CONFIG_PKR_MAP_2 PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0 PKR_YSEL = RASTER_CONFIG_PKR_YSEL_1 PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0 SC_MAP = RASTER_CONFIG_SC_MAP_0 SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE SE_MAP = RASTER_CONFIG_SE_MAP_2 SE_XSEL = RASTER_CONFIG_SE_XSEL_32_WIDE_TILE SE_YSEL = RASTER_CONFIG_SE_YSEL_32_WIDE_TILE SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 SET_CONTEXT_REG: PA_SC_GENERIC_SCISSOR_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 PA_SC_GENERIC_SCISSOR_BR <- BR_X = 16384 (0x4000) BR_Y = 16384 (0x4000) SET_CONTEXT_REG: PA_SC_SCREEN_SCISSOR_TL <- TL_X = 0 TL_Y = 0 PA_SC_SCREEN_SCISSOR_BR <- BR_X = 16384 (0x4000) BR_Y = 16384 (0x4000) SET_CONTEXT_REG: PA_SC_CLIPRECT_RULE <- CLIP_RULE = 0xffff SET_CONTEXT_REG: PA_SC_EDGERULE <- ER_TRI = 10 (0xa) ER_POINT = 10 (0xa) ER_RECT = 10 (0xa) ER_LINE_LR = 42 (0x2a) ER_LINE_RL = 42 (0x2a) ER_LINE_TB = 10 (0xa) ER_LINE_BT = 10 (0xa) PA_SU_HARDWARE_SCREEN_OFFSET <- HW_SCREEN_OFFSET_X = 0 HW_SCREEN_OFFSET_Y = 0 SET_CONTEXT_REG: PA_CL_NANINF_CNTL <- VTE_XY_INF_DISCARD = 0 VTE_Z_INF_DISCARD = 0 VTE_W_INF_DISCARD = 0 VTE_0XNANINF_IS_0 = 0 VTE_XY_NAN_RETAIN = 0 VTE_Z_NAN_RETAIN = 0 VTE_W_NAN_RETAIN = 0 VTE_W_RECIP_NAN_IS_0 = 0 VS_XY_NAN_TO_INF = 0 VS_XY_INF_RETAIN = 0 VS_Z_NAN_TO_INF = 0 VS_Z_INF_RETAIN = 0 VS_W_NAN_TO_INF = 0 VS_W_INF_RETAIN = 0 VS_CLIP_DIST_INF_DISCARD = 0 VTE_NO_OUTPUT_NEG_0 = 0 SET_CONTEXT_REG: PA_CL_GB_VERT_CLIP_ADJ <- 1.0f (0x3f800000) PA_CL_GB_VERT_DISC_ADJ <- 1.0f (0x3f800000) PA_CL_GB_HORZ_CLIP_ADJ <- 1.0f (0x3f800000) PA_CL_GB_HORZ_DISC_ADJ <- 1.0f (0x3f800000) SET_CONTEXT_REG: DB_SRESULTS_COMPARE_STATE0 <- COMPAREFUNC0 = REF_NEVER COMPAREVALUE0 = 0 COMPAREMASK0 = 0 ENABLE0 = 0 DB_SRESULTS_COMPARE_STATE1 <- COMPAREFUNC1 = REF_NEVER COMPAREVALUE1 = 0 COMPAREMASK1 = 0 ENABLE1 = 0 DB_PRELOAD_CONTROL <- START_X = 0 START_Y = 0 MAX_X = 0 MAX_Y = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE <- FORCE_HIZ_ENABLE = FORCE_OFF FORCE_HIS_ENABLE0 = FORCE_DISABLE FORCE_HIS_ENABLE1 = FORCE_DISABLE FORCE_SHADER_Z_ORDER = 0 FAST_Z_DISABLE = 0 FAST_STENCIL_DISABLE = 0 NOOP_CULL_DISABLE = 0 FORCE_COLOR_KILL = 0 FORCE_Z_READ = 0 FORCE_STENCIL_READ = 0 FORCE_FULL_Z_RANGE = FORCE_OFF FORCE_QC_SMASK_CONFLICT = 0 DISABLE_VIEWPORT_CLAMP = 0 IGNORE_SC_ZRANGE = 0 DISABLE_FULLY_COVERED = 0 FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF MAX_TILES_IN_DTT = 0 DISABLE_TILE_RATE_TILES = 0 FORCE_Z_DIRTY = 0 FORCE_STENCIL_DIRTY = 0 FORCE_Z_VALID = 0 FORCE_STENCIL_VALID = 0 PRESERVE_COMPRESSION = 0 SET_CONTEXT_REG: VGT_MAX_VTX_INDX <- 0xffffffff VGT_MIN_VTX_INDX <- 0 VGT_INDX_OFFSET <- 0 SET_CONTEXT_REG: TA_BC_BASE_ADDR <- 0x00008100 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = SAMPLE_STREAMOUTSTATS EVENT_INDEX <- 3 INV_L2 <- 0 ADDRESS_LO <- 0x00825020 ADDRESS_HI <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 SURFACE_SYNC: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 1 SH_ICACHE_ACTION_ENA = 1 CP_COHER_SIZE <- 0xffffffff CP_COHER_BASE <- 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: VGT_STRMOUT_BUFFER_CONFIG <- STREAM_0_BUFFER_EN = 0 STREAM_1_BUFFER_EN = 0 STREAM_2_BUFFER_EN = 0 STREAM_3_BUFFER_EN = 0 SET_CONTEXT_REG: VGT_STRMOUT_CONFIG <- STREAMOUT_0_EN = 1 STREAMOUT_1_EN = 1 STREAMOUT_2_EN = 1 STREAMOUT_3_EN = 1 RAST_STREAM = 0 RAST_STREAM_MASK = 0 USE_RAST_STREAM_MASK = 0 SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x00008280 CB_COLOR0_PITCH <- TILE_MAX = 31 (0x1f) FMASK_TILE_MAX = 0 CB_COLOR0_SLICE <- TILE_MAX = 1023 (0x003ff) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_8_8_8_8 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 1 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 16 (0x10) FMASK_TILE_MODE_INDEX = 16 (0x10) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x00008230 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 7 CB_COLOR0_FMASK <- 0x00008280 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 1023 (0x003ff) CB_COLOR0_CLEAR_WORD0 <- 0x1a1a1a1a CB_COLOR0_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_8_8_8_8 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 1 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: CB_COLOR2_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: CB_COLOR3_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: CB_COLOR4_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: CB_COLOR5_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: CB_COLOR6_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: CB_COLOR7_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_Z_INFO <- FORMAT = Z_INVALID NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 0 READ_SIZE = 0 TILE_SURFACE_ENABLE = 0 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_INVALID TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 0 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 256 (0x100) BR_Y = 256 (0x100) SET_CONTEXT_REG: PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 <- S0_X = 14 (0xe) S0_Y = 11 (0xb) S1_X = 3 S1_Y = 12 (0xc) S2_X = 15 (0xf) S2_Y = 5 S3_X = 10 (0xa) S3_Y = 14 (0xe) PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 <- S4_X = 6 S4_Y = 0 S5_X = 0 S5_Y = 0 S6_X = 11 (0xb) S6_Y = 3 S7_X = 4 S7_Y = 4 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 <- S8_X = 0 S8_Y = 0 S9_X = 0 S9_Y = 0 S10_X = 0 S10_Y = 0 S11_X = 0 S11_Y = 0 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 <- S12_X = 0 S12_Y = 0 S13_X = 0 S13_Y = 0 S14_X = 0 S14_Y = 0 S15_X = 0 S15_Y = 0 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 <- S0_X = 14 (0xe) S0_Y = 11 (0xb) S1_X = 3 S1_Y = 12 (0xc) S2_X = 15 (0xf) S2_Y = 5 S3_X = 10 (0xa) S3_Y = 14 (0xe) PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 <- S4_X = 6 S4_Y = 0 S5_X = 0 S5_Y = 0 S6_X = 11 (0xb) S6_Y = 3 S7_X = 4 S7_Y = 4 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 <- S8_X = 0 S8_Y = 0 S9_X = 0 S9_Y = 0 S10_X = 0 S10_Y = 0 S11_X = 0 S11_Y = 0 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 <- S12_X = 0 S12_Y = 0 S13_X = 0 S13_Y = 0 S14_X = 0 S14_Y = 0 S15_X = 0 S15_Y = 0 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 <- S0_X = 14 (0xe) S0_Y = 11 (0xb) S1_X = 3 S1_Y = 12 (0xc) S2_X = 15 (0xf) S2_Y = 5 S3_X = 10 (0xa) S3_Y = 14 (0xe) PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 <- S4_X = 6 S4_Y = 0 S5_X = 0 S5_Y = 0 S6_X = 11 (0xb) S6_Y = 3 S7_X = 4 S7_Y = 4 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 <- S8_X = 0 S8_Y = 0 S9_X = 0 S9_Y = 0 S10_X = 0 S10_Y = 0 S11_X = 0 S11_Y = 0 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 <- S12_X = 0 S12_Y = 0 S13_X = 0 S13_Y = 0 S14_X = 0 S14_Y = 0 S15_X = 0 S15_Y = 0 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 <- S0_X = 14 (0xe) S0_Y = 11 (0xb) S1_X = 3 S1_Y = 12 (0xc) S2_X = 15 (0xf) S2_Y = 5 S3_X = 10 (0xa) S3_Y = 14 (0xe) PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 <- S4_X = 6 S4_Y = 0 S5_X = 0 S5_Y = 0 S6_X = 11 (0xb) S6_Y = 3 S7_X = 4 S7_Y = 4 SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 1 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: PA_SC_LINE_CNTL <- EXPAND_LINE_WIDTH = 0 LAST_PIXEL = 1 PERPENDICULAR_ENDCAP_ENA = 0 DX10_DIAMOND_TEST_ENA = 0 PA_SC_AA_CONFIG <- MSAA_NUM_SAMPLES = 0 AA_MASK_CENTROID_DTMN = 0 MAX_SAMPLE_DIST = 0 MSAA_EXPOSED_SAMPLES = 0 DETAIL_TO_EXPOSED_MODE = 0 SET_CONTEXT_REG: DB_EQAA <- MAX_ANCHOR_SAMPLES = 0 PS_ITER_SAMPLES = 0 MASK_EXPORT_NUM_SAMPLES = 0 ALPHA_TO_MASK_NUM_SAMPLES = 0 HIGH_QUALITY_INTERSECTIONS = 1 INCOHERENT_EQAA_READS = 0 INTERPOLATE_COMP_Z = 0 INTERPOLATE_SRC_Z = 0 STATIC_ANCHOR_ASSOCIATIONS = 1 ALPHA_TO_MASK_EQAA_DISABLE = 0 OVERRASTERIZATION_AMOUNT = 0 ENABLE_POSTZ_OVERRASTERIZATION = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_1 <- WALK_SIZE = 0 WALK_ALIGNMENT = 0 WALK_ALIGN8_PRIM_FITS_ST = 0 WALK_FENCE_ENABLE = 0 WALK_FENCE_SIZE = 0 SUPERTILE_WALK_ORDER_ENABLE = 0 TILE_WALK_ORDER_ENABLE = 0 TILE_COVER_DISABLE = 0 TILE_COVER_NO_SCISSOR = 0 ZMM_LINE_EXTENT = 0 ZMM_LINE_OFFSET = 0 ZMM_RECT_EXTENT = 0 KILL_PIX_POST_HI_Z = 0 KILL_PIX_POST_DETAIL_MASK = 0 PS_ITER_SAMPLE = 0 MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 0 MULTI_GPU_SUPERTILE_ENABLE = 0 GPU_ID_OVERRIDE_ENABLE = 0 GPU_ID_OVERRIDE = 0 MULTI_GPU_PRIM_DISCARD_ENABLE = 0 FORCE_EOV_CNTDWN_ENABLE = 1 FORCE_EOV_REZ_ENABLE = 1 OUT_OF_ORDER_PRIMITIVE_ENABLE = 0 OUT_OF_ORDER_WATER_MARK = 0 SET_CONTEXT_REG: PA_SC_AA_MASK_X0Y0_X1Y0 <- AA_MASK_X0Y0 = 0xffff AA_MASK_X1Y0 = 0xffff PA_SC_AA_MASK_X0Y1_X1Y1 <- AA_MASK_X0Y1 = 0xffff AA_MASK_X1Y1 = 0xffff SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: CB_BLEND_RED <- 0 CB_BLEND_GREEN <- 0 CB_BLEND_BLUE <- 0 CB_BLEND_ALPHA <- 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 1 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 1 ZCLIP_FAR_DISABLE = 1 SET_CONTEXT_REG: VGT_REUSE_OFF <- REUSE_OFF = 0 SET_CONTEXT_REG: PA_CL_UCP_0_X <- 0 PA_CL_UCP_0_Y <- 0 PA_CL_UCP_0_Z <- 0 PA_CL_UCP_0_W <- 0 PA_CL_UCP_1_X <- 0 PA_CL_UCP_1_Y <- 0 PA_CL_UCP_1_Z <- 0 PA_CL_UCP_1_W <- 0 PA_CL_UCP_2_X <- 0 PA_CL_UCP_2_Y <- 0 PA_CL_UCP_2_Z <- 0 PA_CL_UCP_2_W <- 0 PA_CL_UCP_3_X <- 0 PA_CL_UCP_3_Y <- 0 PA_CL_UCP_3_Z <- 0 PA_CL_UCP_3_W <- 0 PA_CL_UCP_4_X <- 0 PA_CL_UCP_4_Y <- 0 PA_CL_UCP_4_Z <- 0 PA_CL_UCP_4_W <- 0 PA_CL_UCP_5_X <- 0 PA_CL_UCP_5_Y <- 0 PA_CL_UCP_5_Z <- 0 PA_CL_UCP_5_W <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 0x00868300 SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 0x00868100 SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 0x00868400 SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_0 <- 0x00868b00 SPI_SHADER_USER_DATA_PS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 0x00868900 SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 0x00868c00 SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_0 <- 0x00869300 SPI_SHADER_USER_DATA_GS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 0x00869100 SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_4 <- 0x00869400 SPI_SHADER_USER_DATA_GS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_HS_0 <- 0x00869b00 SPI_SHADER_USER_DATA_HS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_HS_2 <- 0x00869900 SPI_SHADER_USER_DATA_HS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_HS_4 <- 0x00869c00 SPI_SHADER_USER_DATA_HS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 0x0086a900 SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_SC_VPORT_SCISSOR_0_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 PA_SC_VPORT_SCISSOR_0_BR <- BR_X = 0 BR_Y = 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 128.0f (0x43000000) PA_CL_VPORT_XOFFSET <- 128.0f (0x43000000) PA_CL_VPORT_YSCALE <- 128.0f (0x43000000) PA_CL_VPORT_YOFFSET <- 128.0f (0x43000000) PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: DB_STENCILREFMASK <- STENCILTESTVAL = 0 STENCILMASK = 0 STENCILWRITEMASK = 0 STENCILOPVAL = 1 DB_STENCILREFMASK_BF <- STENCILTESTVAL_BF = 0 STENCILMASK_BF = 0 STENCILWRITEMASK_BF = 0 STENCILOPVAL_BF = 1 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 0 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_SHADER_STAGES_EN <- LS_EN = LS_STAGE_OFF HS_EN = 0 ES_EN = ES_STAGE_OFF GS_EN = 0 VS_EN = VS_STAGE_REAL DYNAMIC_HS = 0 DISPATCH_DRAW_EN = 0 DIS_DEALLOC_ACCUM_0 = 0 DIS_DEALLOC_ACCUM_1 = 0 VS_WAVE_ID_EN = 0 SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x00008260 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 192 (0xc0) PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_TMPRING_SIZE <- WAVES = 768 (0x300) WAVESIZE = 0 SET_CONFIG_REG: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_QUADLIST SET_CONTEXT_REG: IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 0 MAX_PRIMGRP_IN_WAVE = 0 SET_CONTEXT_REG: VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 SET_CONTEXT_REG: VGT_GS_OUT_PRIM_TYPE <- OUTPRIM_TYPE = OUTPRIM_TYPE_TRISTRIP OUTPRIM_TYPE_1 = 0 OUTPRIM_TYPE_2 = 0 OUTPRIM_TYPE_3 = 0 UNIQUE_TYPE_PER_STREAM = 0 SET_CONTEXT_REG: VGT_MULTI_PRIM_IB_RESET_EN <- RESET_EN = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 SET_SH_REG: SPI_SHADER_USER_DATA_VS_10 <- 0 SPI_SHADER_USER_DATA_VS_11 <- 0 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 4 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x00822000 DST_ADDR_HI <- 0 0x00000002 NOP: Trace point ID: 2 !!!!! This is the last trace point that was reached by the CP !!!!! EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = SAMPLE_STREAMOUTSTATS EVENT_INDEX <- 3 INV_L2 <- 0 ADDRESS_LO <- 0x00825030 ADDRESS_HI <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = PS_PARTIAL_FLUSH EVENT_INDEX <- 4 INV_L2 <- 0 SURFACE_SYNC: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_BASE <- 0 POLL_INTERVAL <- 10 (0x000a) WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x00822000 DST_ADDR_HI <- 0 0x00000003 NOP: Trace point ID: 3 !!!!! This trace point was NOT reached by the CP !!!!! ------------------- IB end ------------------- Done.