[ 55.182048] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 55.182080] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 55.182106] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 55.182127] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 55.198047] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 55.198079] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 55.198118] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 55.198127] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 60.035453] [drm:drm_mode_getconnector] [CONNECTOR:47:?] [ 60.035465] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:eDP-1] [ 60.035469] [drm:intel_dp_detect] [CONNECTOR:47:eDP-1] [ 60.035484] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 60.035492] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 60.036040] [drm:intel_dp_probe_oui] Sink OUI: 001cf8 [ 60.036365] [drm:intel_dp_probe_oui] Branch OUI: 000000 [ 60.036831] [drm:drm_edid_to_eld] ELD: no CEA Extension found [ 60.036837] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:eDP-1] probed modes : [ 60.036842] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 60.036851] [drm:drm_mode_getconnector] [CONNECTOR:47:?] [ 60.037110] [drm:drm_mode_getconnector] [CONNECTOR:45:?] [ 60.037114] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] [ 60.037122] [drm:intel_dp_detect] [CONNECTOR:45:DP-1] [ 60.037572] [drm:intel_dp_get_dpcd] DPCD: 11 0a c4 01 01 00 01 00 02 02 06 00 00 00 00 [ 60.037576] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source no, sink no [ 60.037579] [drm:intel_dp_print_rates] source rates: 162000, 270000 [ 60.037581] [drm:intel_dp_print_rates] sink rates: 162000, 270000 [ 60.037583] [drm:intel_dp_print_rates] common rates: 162000, 270000 [ 60.044084] [drm:drm_detect_monitor_audio] Monitor has basic audio support [ 60.044662] [drm:drm_edid_to_eld] ELD monitor ASUS PB287Q [ 60.044667] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 600, latency present 0 0, video latency 0 0, audio latency 0 0 [ 60.044669] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 [ 60.044736] [drm:drm_mode_debug_printmodeline] Modeline 69:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 60.044738] [drm:drm_mode_prune_invalid] Not using 3840x2160 mode: CLOCK_HIGH [ 60.044745] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:45:DP-1] probed modes : [ 60.044749] [drm:drm_mode_debug_printmodeline] Modeline 71:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9 [ 60.044752] [drm:drm_mode_debug_printmodeline] Modeline 73:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x40 0x9 [ 60.044756] [drm:drm_mode_debug_printmodeline] Modeline 72:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x5 [ 60.044759] [drm:drm_mode_debug_printmodeline] Modeline 76:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa [ 60.044763] [drm:drm_mode_debug_printmodeline] Modeline 108:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 60.044766] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 60.044770] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 60.044774] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 60.044777] [drm:drm_mode_debug_printmodeline] Modeline 107:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 60.044781] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 60.044784] [drm:drm_mode_debug_printmodeline] Modeline 80:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 [ 60.044787] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 60.044791] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 60.044794] [drm:drm_mode_debug_printmodeline] Modeline 79:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 [ 60.044798] [drm:drm_mode_debug_printmodeline] Modeline 77:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 [ 60.044801] [drm:drm_mode_debug_printmodeline] Modeline 81:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 60.044805] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 60.044808] [drm:drm_mode_debug_printmodeline] Modeline 113:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 60.044812] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 60.044815] [drm:drm_mode_debug_printmodeline] Modeline 111:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa [ 60.044819] [drm:drm_mode_debug_printmodeline] Modeline 91:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 60.044822] [drm:drm_mode_debug_printmodeline] Modeline 92:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 60.044826] [drm:drm_mode_debug_printmodeline] Modeline 93:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 60.044829] [drm:drm_mode_debug_printmodeline] Modeline 121:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa [ 60.044833] [drm:drm_mode_debug_printmodeline] Modeline 109:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa [ 60.044836] [drm:drm_mode_debug_printmodeline] Modeline 94:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa [ 60.044840] [drm:drm_mode_debug_printmodeline] Modeline 96:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 60.044843] [drm:drm_mode_debug_printmodeline] Modeline 97:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 60.044847] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 60.044850] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 60.044854] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 60.044857] [drm:drm_mode_debug_printmodeline] Modeline 116:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 60.044861] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 60.044864] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 60.044868] [drm:drm_mode_debug_printmodeline] Modeline 86:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa [ 60.044871] [drm:drm_mode_debug_printmodeline] Modeline 87:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa [ 60.044875] [drm:drm_mode_debug_printmodeline] Modeline 88:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 60.044878] [drm:drm_mode_debug_printmodeline] Modeline 98:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 60.044881] [drm:drm_mode_debug_printmodeline] Modeline 89:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 60.045041] [drm:drm_mode_getconnector] [CONNECTOR:45:?] [ 60.045188] [drm:drm_mode_getconnector] [CONNECTOR:55:?] [ 60.045192] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] [ 60.045194] [drm:intel_dp_detect] [CONNECTOR:55:DP-2] [ 60.045198] [drm:intel_power_well_enable] enabling dpio-common-d [ 60.061545] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x1d0607ff) [ 60.070392] [drm:intel_power_well_disable] disabling dpio-common-d [ 60.078437] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x1d0607fd) [ 60.087267] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] disconnected [ 60.087692] [drm:drm_mode_getconnector] [CONNECTOR:40:?] [ 60.087697] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] [ 60.087700] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1] [ 60.088489] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 60.088505] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 60.088949] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 60.088961] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 60.088969] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] disconnected [ 60.089008] [drm:drm_mode_getconnector] [CONNECTOR:53:?] [ 60.089014] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] [ 60.089018] [drm:intel_hdmi_detect] [CONNECTOR:53:HDMI-A-2] [ 60.214448] [drm:intel_hdmi_detect] Live status not up! [ 60.214459] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] disconnected [ 60.225251] [drm:i915_gem_open] [ 60.248270] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 60.248281] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 60.248763] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 60.248772] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 60.249001] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 60.249009] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 60.249106] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3000/6000 [ 60.249110] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 60.249121] [drm:intel_edp_backlight_power] panel power control backlight disable [ 60.252571] [drm:i915_gem_context_create_ioctl] HW context 1 created [ 60.450805] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/6000 [ 60.450814] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 60.450917] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 60.450929] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 60.450965] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains [ 60.450971] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 60.450977] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148352KHz [ 60.450985] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 60.450988] [drm:intel_dp_compute_config] DP link bw required 356045 available 518400 [ 60.450995] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 60.451001] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff8800754fb000 for pipe A [ 60.451006] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 60.451009] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 60.451013] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 60.451018] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5761420, gmch_n: 8388608, link_m: 240059, link_n: 262144, tu: 64 [ 60.451022] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 60.451025] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 60.451027] [drm:intel_dump_pipe_config] requested mode: [ 60.451035] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5 [ 60.451038] [drm:intel_dump_pipe_config] adjusted mode: [ 60.451044] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5 [ 60.451048] [drm:intel_dump_crtc_timings] crtc timings: 148352 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x0 flags: 0x5 [ 60.451051] [drm:intel_dump_pipe_config] port clock: 162000 [ 60.451054] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 60.451059] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 60.451063] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 60.451066] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 60.451069] [drm:intel_dump_pipe_config] ips: 0 [ 60.451072] [drm:intel_dump_pipe_config] double wide: 0 [ 60.451075] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 60.451078] [drm:intel_dump_pipe_config] planes on this crtc [ 60.451082] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled [ 60.451086] [drm:intel_dump_pipe_config] FB:62, fb = 3840x1632 format = 0x34325258 [ 60.451091] [drm:intel_dump_pipe_config] scaler:0 src (0, 552) 1920x1080 dst (0, 0) 1920x1080 [ 60.451095] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 60.451101] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 60.451105] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0 [ 60.451112] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 60.451143] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 60.461310] [drm:intel_edp_backlight_off] [ 60.662441] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 60.662861] [drm:edp_panel_off] Turn eDP port C panel power off [ 60.662868] [drm:wait_panel_off] Wait for panel power off time [ 60.662875] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 60.703496] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 60.703506] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 60.703512] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 60.703567] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 60.703821] [drm:wait_panel_status] Wait complete [ 60.703841] [drm:intel_disable_pipe] disabling pipe A [ 60.712573] [drm:intel_dp_link_down] [ 60.783985] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x0d0007fd) [ 60.793263] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 60.801691] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe B [ 60.802736] [drm:intel_disable_pipe] disabling pipe B [ 60.818162] [drm:intel_dp_link_down] [ 60.847638] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x050007fd) [ 60.861298] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 60.861313] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 60.870611] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007fd) [ 61.012151] [drm:intel_dp_reset_link_train] flt enabled: true [ 61.092393] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 61.092402] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 61.093213] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 61.176756] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 61.176765] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 61.260641] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 61.260650] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 61.261702] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 61.262028] [drm:intel_enable_dp] Enabling DP audio on pipe A [ 61.262035] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44] [ 61.262041] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD [ 61.262132] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 61.262142] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 61.262149] [drm:intel_enable_pipe] enabling pipe A [ 61.262167] [drm:intel_psr_enable] PSR not supported by this panel [ 61.279206] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 61.279220] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 61.279226] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 61.279233] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 61.279236] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 61.279241] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 61.279244] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 61.279253] [drm:check_crtc_state] [CRTC:26] [ 61.289530] [drm:check_crtc_state] [CRTC:31] [ 61.289668] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 61.291030] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 61.291041] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 61.291045] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 61.292339] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 61.292349] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 61.292368] [drm:connected_sink_compute_bpp] [CONNECTOR:47:eDP-1] checking for sink bpp constrains [ 61.292371] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 61.292376] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz [ 61.292385] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 61.292387] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 61.292390] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 61.292394] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880178f9f000 for pipe B [ 61.292397] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 61.292399] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 61.292401] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 61.292404] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 61.292407] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 61.292409] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 61.292410] [drm:intel_dump_pipe_config] requested mode: [ 61.292414] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x0 0xa [ 61.292416] [drm:intel_dump_pipe_config] adjusted mode: [ 61.292420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 61.292423] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 61.292425] [drm:intel_dump_pipe_config] port clock: 270000 [ 61.292427] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 61.292429] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 61.292431] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 61.292433] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 61.292435] [drm:intel_dump_pipe_config] ips: 0 [ 61.292437] [drm:intel_dump_pipe_config] double wide: 0 [ 61.292439] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 61.292441] [drm:intel_dump_pipe_config] planes on this crtc [ 61.292444] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0 [ 61.292447] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0 [ 61.292449] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0 [ 61.292452] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0 [ 61.292456] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 61.292480] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x1d0607fd) [ 61.394905] [drm:vlv_detach_power_sequencer] detaching pipe A power sequencer from port C [ 61.394918] [drm:vlv_init_panel_power_sequencer] initializing pipe B power sequencer for port C [ 61.394929] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06 [ 61.394938] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 61.394946] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 61.394952] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 61.394956] [drm:wait_panel_status] Wait complete [ 61.394964] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 61.394968] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled [ 61.430308] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 61.430320] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 61.430324] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 1 [ 61.430446] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 61.598976] [drm:edp_panel_on] Turn eDP port C panel power on [ 61.599147] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 61.599154] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 61.599158] [drm:wait_panel_status] Wait complete [ 61.599164] [drm:wait_panel_on] Wait for panel power on [ 61.599170] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b [ 61.762444] [drm:wait_panel_status] Wait complete [ 61.762458] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 61.762470] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 61.762488] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 61.762495] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 61.763074] [drm:intel_dp_reset_link_train] flt enabled: true [ 61.805130] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 61.805139] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 61.805815] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 61.807149] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 61.817783] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 61.817796] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 61.817806] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 61.817813] [drm:intel_enable_pipe] enabling pipe B [ 61.817832] [drm:intel_edp_backlight_on] [ 61.817836] [drm:intel_panel_enable_backlight] pipe B [ 61.817841] [drm:intel_panel_actually_set_backlight] set backlight PWM = 6000 [ 61.817854] [drm:intel_psr_match_conditions] PSR disable by flag [ 61.835534] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 61.835548] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 61.835555] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 61.835559] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 61.835562] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 61.835565] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 61.835570] [drm:check_crtc_state] [CRTC:31] [ 61.847403] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3000/6000 [ 61.847411] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 61.847738] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 61.847750] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 61.866966] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 61.867000] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 61.867031] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 61.867052] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 61.867101] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 61.867121] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 61.867143] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 61.867162] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 61.869988] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 61.870010] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 61.870046] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 61.870054] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 61.887399] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 61.887408] [drm:i915_pages_create_for_stolen] offset=0x805000, size=16384 [ 61.888955] [drm:i915_gem_context_destroy_ioctl] HW context 1 destroyed [ 61.901876] [drm:i915_gem_context_create_ioctl] HW context 1 created [ 62.054015] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.054046] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.062004] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.062030] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.096528] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.096551] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.096631] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.096651] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.110089] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.110121] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.118059] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.118091] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.126107] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.126140] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.134116] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.134149] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.150092] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.150125] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.174084] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.174116] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.196860] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.196897] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.198035] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.198065] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.206121] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.206153] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.214081] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.214121] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.222086] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.222119] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.230008] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.230040] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.238071] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.238104] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.247069] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.247098] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.254037] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.254067] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.262126] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.262159] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.270024] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.270056] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.281787] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.281821] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.286081] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.286115] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.294126] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.294159] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.311103] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.311135] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.318096] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.318127] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.346772] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.346807] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.346925] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.346945] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.359173] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.359204] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.374259] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.374292] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.382292] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.382327] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.390032] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.390066] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.407041] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.407076] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.414193] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.414220] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.430168] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.430203] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.438375] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.438455] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.470376] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.470469] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.487013] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.487046] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.686669] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.686710] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.694853] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.694895] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.710778] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.710819] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.734646] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.735012] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.766651] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.766691] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.791636] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.791678] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.799761] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 62.799803] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 63.447624] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 63.448455] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 63.448543] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 63.448554] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 63.455928] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 63.455970] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 63.456009] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 63.456039] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 63.463629] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 63.463671] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 63.463709] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 63.463738] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 63.470337] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 63.470959] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 63.471007] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 63.471037] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 63.478666] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 63.478708] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 63.478747] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 63.478777] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 63.486687] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 63.486702] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 63.486747] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 63.486779] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 64.366675] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 64.366689] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 64.366754] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 64.366783] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 64.374841] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 64.374884] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 64.374942] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 64.374955] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 64.810476] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 64.810489] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007 [ 64.919723] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 64.919764] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 65.263779] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 65.263822] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 65.270838] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 65.270880] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 65.727839] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 65.727881] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 65.734804] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 65.734846] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 66.127740] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.127753] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 66.135539] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.135571] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.144203] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.144236] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.151556] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.151588] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.159787] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.159817] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.166563] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 66.166603] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 66.166642] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.166671] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.175563] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 66.175606] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 66.175633] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.175653] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.183470] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 66.183484] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 66.183530] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 66.183559] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.359665] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.359680] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 67.359744] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.359772] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.367927] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.367969] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.368009] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.368038] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.375556] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.375597] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.375635] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.375663] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.383683] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.383732] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.383785] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.383821] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.391323] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.391373] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.391427] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.391466] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.472206] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.472279] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.472367] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.472424] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.479794] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.479885] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.479996] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.480073] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.487897] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.487987] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.488102] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.488177] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.503901] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.503990] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.504104] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.504179] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.511840] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.511930] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.512047] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.512123] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.519894] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.519984] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.520097] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.520173] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.527870] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.527960] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.528073] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.528148] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.543951] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.544042] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.544156] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.544232] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.551886] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.551976] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.552091] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.552166] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.559576] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.559665] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.559776] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.559850] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.575437] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.575529] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.575645] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.575718] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.583682] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.583775] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.583888] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.583963] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.591776] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.591867] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.591981] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.592055] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.599848] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.599936] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.600053] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.600128] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.616071] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.616161] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.616279] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.616356] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.623658] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.623736] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.623835] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.623901] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.631882] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.631962] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.632060] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.632127] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.639581] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.639653] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.639739] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.639798] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.647815] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.647889] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.647976] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.648035] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.671893] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.671972] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 67.672069] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 67.672133] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.287795] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.287836] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.287875] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.287904] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.295813] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.295866] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.295922] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.295960] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.303869] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.303924] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.303979] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.304018] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.311827] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.311889] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.311959] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.312011] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.319949] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.320011] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.320084] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.320133] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.327755] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.327846] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.327965] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.328041] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.335854] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.335934] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.336032] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.336097] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.343686] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 68.343717] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 68.343823] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 68.343890] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 72.192797] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.192833] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 72.192998] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 72.193074] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 72.200062] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.200152] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.200300] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 72.200332] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 72.687978] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.688051] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.849031] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.849123] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.864329] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.864421] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.872147] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.872238] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.880195] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.880285] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.889363] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.889451] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.897144] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.897234] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.905384] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 72.905473] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 73.025144] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 73.025236] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 73.032895] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 73.032986] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.064153] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.064244] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.163277] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.163367] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.320245] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.320335] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.337536] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.337628] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.344886] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.344932] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.352788] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.352831] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.360438] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.360486] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.585187] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.585279] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.593005] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.593095] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.671666] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.671705] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.679835] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.679876] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.688883] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 74.688918] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 75.096977] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 75.097030] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 75.104921] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 75.105011] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 75.120918] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 75.121008] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 75.160643] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 75.160659] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 75.168495] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 75.168524] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 75.176997] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 75.177012] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 75.177059] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 75.177080] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 75.184827] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 75.184865] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 88.079210] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 88.079249] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 88.137275] [drm:internal_framebuffer_create] could not create framebuffer [ 88.138040] [drm:internal_framebuffer_create] could not create framebuffer [ 88.138049] [drm:internal_framebuffer_create] could not create framebuffer [ 88.146556] [drm:drm_mode_addfb2] [FB:68] [ 88.146721] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 88.146730] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 88.148997] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 88.149006] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 88.157075] [drm:internal_framebuffer_create] could not create framebuffer [ 88.157089] [drm:internal_framebuffer_create] could not create framebuffer [ 88.164331] [drm:drm_mode_addfb2] [FB:134] [ 88.164704] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 88.164713] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 88.168936] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 88.168949] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 88.169833] [drm:internal_framebuffer_create] could not create framebuffer [ 88.169843] [drm:internal_framebuffer_create] could not create framebuffer [ 88.177294] [drm:drm_mode_addfb2] [FB:142] [ 88.177621] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 88.177629] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 88.177666] [drm:connected_sink_compute_bpp] [CONNECTOR:47:eDP-1] checking for sink bpp constrains [ 88.177669] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 88.177676] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz [ 88.177686] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 88.177688] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 88.177692] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 88.177696] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff880178f9f000 for pipe A [ 88.177699] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 88.177701] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 88.177703] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 88.177706] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 88.177709] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 88.177711] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 88.177712] [drm:intel_dump_pipe_config] requested mode: [ 88.177717] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x0 0xa [ 88.177719] [drm:intel_dump_pipe_config] adjusted mode: [ 88.177722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 88.177725] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 88.177727] [drm:intel_dump_pipe_config] port clock: 270000 [ 88.177729] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 88.177732] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 88.177734] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 88.177736] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 88.177738] [drm:intel_dump_pipe_config] ips: 0 [ 88.177740] [drm:intel_dump_pipe_config] double wide: 0 [ 88.177742] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 88.177744] [drm:intel_dump_pipe_config] planes on this crtc [ 88.177747] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled [ 88.177750] [drm:intel_dump_pipe_config] FB:68, fb = 1920x1080 format = 0x34325258 [ 88.177753] [drm:intel_dump_pipe_config] scaler:0 src (0, 0) 1920x1080 dst (0, 0) 1920x1080 [ 88.177757] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 88.177760] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 88.177763] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0 [ 88.177768] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 88.179184] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 88.190421] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A [ 88.193993] [drm:intel_disable_pipe] disabling pipe A [ 88.208022] [drm:intel_dp_link_down] [ 88.237236] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x150607fd) [ 88.248415] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 88.251719] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 88.251749] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 88.251763] [drm:intel_edp_backlight_off] [ 88.454477] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 88.454753] [drm:edp_panel_off] Turn eDP port C panel power off [ 88.454773] [drm:wait_panel_off] Wait for panel power off time [ 88.454793] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 88.495144] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 88.495171] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 88.495186] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 88.495389] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 88.495440] [drm:wait_panel_status] Wait complete [ 88.495483] [drm:intel_disable_pipe] disabling pipe B [ 88.502876] [drm:intel_dp_link_down] [ 88.575995] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x050007fd) [ 88.588291] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 88.588330] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 88.600314] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x150607fd) [ 88.700531] [drm:vlv_detach_power_sequencer] detaching pipe B power sequencer from port C [ 88.700561] [drm:vlv_init_panel_power_sequencer] initializing pipe A power sequencer for port C [ 88.700589] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06 [ 88.700617] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 88.700631] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 89.058498] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 89.058522] [drm:wait_panel_status] Wait complete [ 89.058544] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 89.058556] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled [ 89.093425] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 89.093451] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 89.093468] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 1 [ 89.093614] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 89.262480] [drm:edp_panel_on] Turn eDP port C panel power on [ 89.262506] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 89.262527] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 89.262539] [drm:wait_panel_status] Wait complete [ 89.262554] [drm:wait_panel_on] Wait for panel power on [ 89.262570] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b [ 89.425676] [drm:wait_panel_status] Wait complete [ 89.425707] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 89.425734] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 89.425769] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 89.425789] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 89.427374] [drm:intel_dp_reset_link_train] flt enabled: true [ 89.470286] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 89.470309] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 89.471288] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 89.472628] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 89.472978] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 89.473008] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 89.473023] [drm:intel_enable_pipe] enabling pipe A [ 89.473062] [drm:intel_edp_backlight_on] [ 89.473075] [drm:intel_panel_enable_backlight] pipe A [ 89.473090] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 89.473116] [drm:intel_psr_match_conditions] PSR disable by flag [ 89.490310] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 89.490342] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 89.490361] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 89.490379] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 89.490392] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 89.490404] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 89.490415] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 89.490432] [drm:check_crtc_state] [CRTC:26] [ 89.502069] [drm:check_crtc_state] [CRTC:31] [ 89.503312] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 89.503744] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 89.503775] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 89.503788] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 89.507183] [drm:internal_framebuffer_create] could not create framebuffer [ 89.507216] [drm:internal_framebuffer_create] could not create framebuffer [ 89.553458] [drm:drm_mode_addfb2] [FB:141] [ 89.554341] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 89.554350] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 89.554379] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains [ 89.554381] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 89.554386] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz [ 89.554396] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24 [ 89.554398] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000 [ 89.554402] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 89.554406] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880178f99800 for pipe B [ 89.554408] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 89.554410] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 89.554413] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 89.554416] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64 [ 89.554418] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 89.554420] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 89.554422] [drm:intel_dump_pipe_config] requested mode: [ 89.554426] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x0 0x9 [ 89.554428] [drm:intel_dump_pipe_config] adjusted mode: [ 89.554432] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x0 0x9 [ 89.554435] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x0 flags: 0x9 [ 89.554437] [drm:intel_dump_pipe_config] port clock: 270000 [ 89.554439] [drm:intel_dump_pipe_config] pipe src size: 3840x2160 [ 89.554441] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 89.554443] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 89.554446] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 89.554448] [drm:intel_dump_pipe_config] ips: 0 [ 89.554449] [drm:intel_dump_pipe_config] double wide: 0 [ 89.554452] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 89.554454] [drm:intel_dump_pipe_config] planes on this crtc [ 89.554457] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0 [ 89.554460] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0 [ 89.554463] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0 [ 89.554466] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0 [ 89.554478] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000 [ 89.556142] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 89.556150] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 89.556170] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains [ 89.556173] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 89.556177] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz [ 89.556186] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24 [ 89.556188] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000 [ 89.556192] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 89.556195] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880178f9b000 for pipe B [ 89.556197] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 89.556199] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 89.556202] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 89.556205] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64 [ 89.556208] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 89.556210] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 89.556212] [drm:intel_dump_pipe_config] requested mode: [ 89.556215] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x0 0x9 [ 89.556225] [drm:intel_dump_pipe_config] adjusted mode: [ 89.556229] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x0 0x9 [ 89.556232] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x0 flags: 0x9 [ 89.556234] [drm:intel_dump_pipe_config] port clock: 270000 [ 89.556236] [drm:intel_dump_pipe_config] pipe src size: 3840x2160 [ 89.556239] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 89.556241] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 89.556243] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 89.556245] [drm:intel_dump_pipe_config] ips: 0 [ 89.556247] [drm:intel_dump_pipe_config] double wide: 0 [ 89.556249] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 89.556251] [drm:intel_dump_pipe_config] planes on this crtc [ 89.556254] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0 [ 89.556257] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0 [ 89.556260] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0 [ 89.556262] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0 [ 89.556270] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000 [ 89.560247] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 89.573574] [drm:intel_edp_backlight_off] [ 89.774472] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 89.774715] [drm:edp_panel_off] Turn eDP port C panel power off [ 89.774728] [drm:wait_panel_off] Wait for panel power off time [ 89.774741] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 89.815169] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 89.815186] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 89.815197] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 89.815288] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 89.816323] [drm:wait_panel_status] Wait complete [ 89.816357] [drm:intel_disable_pipe] disabling pipe A [ 89.825320] [drm:intel_dp_link_down] [ 89.896556] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x050007fd) [ 89.920325] [drm:intel_update_cdclk] Current CD clock rate: 320000 kHz [ 89.920386] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x150607fd) [ 90.020964] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 90.020989] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 90.378478] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 90.378505] [drm:wait_panel_status] Wait complete [ 90.378527] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 90.378539] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled [ 90.413405] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 90.413431] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 90.413446] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 1 [ 90.413590] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 90.582467] [drm:edp_panel_on] Turn eDP port C panel power on [ 90.582494] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 90.582516] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 90.582528] [drm:wait_panel_status] Wait complete [ 90.582542] [drm:wait_panel_on] Wait for panel power on [ 90.582557] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b [ 90.725118] [drm:wait_panel_status] Wait complete [ 90.725147] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 90.725171] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 90.725206] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 90.725226] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 90.725905] [drm:intel_dp_reset_link_train] flt enabled: true [ 90.767657] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 90.767682] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 90.768545] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 90.770781] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 90.771156] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 90.771189] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 90.771201] [drm:intel_enable_pipe] enabling pipe A [ 90.771238] [drm:intel_edp_backlight_on] [ 90.771251] [drm:intel_panel_enable_backlight] pipe A [ 90.771268] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 90.771291] [drm:intel_psr_match_conditions] PSR disable by flag [ 90.771389] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x1d0607fd) [ 90.910874] [drm:intel_dp_reset_link_train] flt enabled: false [ 90.995228] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 90.995253] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 90.996327] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 91.082672] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 91.082693] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 91.169940] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 91.169962] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 91.171959] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 91.172185] [drm:intel_enable_dp] Enabling DP audio on pipe B [ 91.172205] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44] [ 91.172221] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD [ 91.183792] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 91.183829] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 91.183843] [drm:intel_enable_pipe] enabling pipe B [ 91.183890] [drm:intel_psr_enable] PSR not supported by this panel [ 91.218189] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 91.218222] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 91.218241] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 91.218256] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 91.218267] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 91.218277] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 91.218290] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 91.218303] [drm:check_crtc_state] [CRTC:26] [ 91.231309] [drm:check_crtc_state] [CRTC:31] [ 91.428560] [drm:drm_mode_getconnector] [CONNECTOR:55:?] [ 91.428568] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] [ 91.428571] [drm:intel_dp_detect] [CONNECTOR:55:DP-2] [ 91.428577] [drm:intel_power_well_enable] enabling dpio-common-d [ 91.444598] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x1d0607ff) [ 91.453632] [drm:intel_power_well_disable] disabling dpio-common-d [ 91.462564] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x1d0607fd) [ 91.471342] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] disconnected [ 91.471410] [drm:drm_mode_getconnector] [CONNECTOR:40:?] [ 91.471419] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] [ 91.471425] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1] [ 91.471725] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 91.471732] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 91.471978] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 91.471987] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 91.471994] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] disconnected [ 91.472018] [drm:drm_mode_getconnector] [CONNECTOR:53:?] [ 91.472025] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] [ 91.472029] [drm:intel_hdmi_detect] [CONNECTOR:53:HDMI-A-2] [ 91.598496] [drm:intel_hdmi_detect] Live status not up! [ 91.598523] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] disconnected [ 91.893831] [drm:internal_framebuffer_create] could not create framebuffer [ 93.778255] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 93.778291] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007 [ 109.033380] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 109.033484] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 109.033567] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 109.038679] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 109.038704] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 109.038716] [drm:intel_edp_backlight_off] [ 109.242540] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 109.242869] [drm:edp_panel_off] Turn eDP port C panel power off [ 109.242892] [drm:wait_panel_off] Wait for panel power off time [ 109.242912] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 109.277007] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 109.277033] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 109.277048] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 109.277392] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 109.283510] [drm:wait_panel_status] Wait complete [ 109.283570] [drm:intel_disable_pipe] disabling pipe A [ 109.288059] [drm:intel_dp_link_down] [ 109.361004] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x0d0007fd) [ 109.372168] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 109.384705] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe B [ 109.385095] [drm:intel_disable_pipe] disabling pipe B [ 109.419955] [drm:intel_dp_link_down] [ 109.449307] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x050007fd) [ 109.461199] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 109.461239] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 109.484829] [drm:intel_update_cdclk] Current CD clock rate: 266667 kHz [ 109.484889] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x150607fd) [ 109.584313] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 109.584341] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 109.846460] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 109.846486] [drm:wait_panel_status] Wait complete [ 109.846506] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 109.846518] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled [ 109.881408] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 109.881434] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 109.881451] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 1 [ 109.882227] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 110.050372] [drm:edp_panel_on] Turn eDP port C panel power on [ 110.050399] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 110.050420] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 110.050431] [drm:wait_panel_status] Wait complete [ 110.050448] [drm:wait_panel_on] Wait for panel power on [ 110.050463] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b [ 110.211495] [drm:wait_panel_status] Wait complete [ 110.211523] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 110.211546] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 110.211579] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 110.211600] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 110.212293] [drm:intel_dp_reset_link_train] flt enabled: true [ 110.256279] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 110.256303] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 110.257168] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 110.259841] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 110.260203] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 110.260232] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 110.260244] [drm:intel_enable_pipe] enabling pipe A [ 110.260281] [drm:intel_edp_backlight_on] [ 110.260292] [drm:intel_panel_enable_backlight] pipe A [ 110.260308] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 110.260337] [drm:intel_psr_match_conditions] PSR disable by flag [ 110.277389] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 110.277421] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 110.277439] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 110.277457] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 110.277471] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 110.277481] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 110.277493] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 110.277506] [drm:check_crtc_state] [CRTC:26] [ 110.288716] [drm:check_crtc_state] [CRTC:31] [ 110.292507] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 110.292546] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 110.292561] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 110.295540] [drm:internal_framebuffer_create] could not create framebuffer [ 110.343103] [drm:internal_framebuffer_create] could not create framebuffer [ 110.343900] [drm:internal_framebuffer_create] could not create framebuffer [ 110.343907] [drm:internal_framebuffer_create] could not create framebuffer [ 110.348311] [drm:drm_mode_addfb2] [FB:61] [ 110.348361] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 110.348371] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 110.361667] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 110.361680] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 110.362889] [drm:internal_framebuffer_create] could not create framebuffer [ 110.362900] [drm:internal_framebuffer_create] could not create framebuffer [ 110.369191] [drm:drm_mode_addfb2] [FB:144] [ 110.369323] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 110.369332] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 110.369471] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3000/6000 [ 110.369476] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 110.369486] [drm:intel_edp_backlight_power] panel power control backlight disable [ 110.570443] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/6000 [ 110.570466] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 110.571308] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 110.571339] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 110.571416] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains [ 110.571429] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 110.571447] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 268500KHz [ 110.571481] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24 [ 110.571492] [drm:intel_dp_compute_config] DP link bw required 644400 available 864000 [ 110.571507] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 110.571525] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff8800754fd800 for pipe A [ 110.571535] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 110.571545] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 110.571559] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 110.571574] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6256503, gmch_n: 8388608, link_m: 521375, link_n: 524288, tu: 64 [ 110.571588] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 110.571598] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 110.571606] [drm:intel_dump_pipe_config] requested mode: [ 110.572061] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x0 0x9 [ 110.572072] [drm:intel_dump_pipe_config] adjusted mode: [ 110.572089] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x0 0x9 [ 110.572106] [drm:intel_dump_crtc_timings] crtc timings: 268500 2560 2608 2640 2720 1600 1603 1609 1646, type: 0x0 flags: 0x9 [ 110.572116] [drm:intel_dump_pipe_config] port clock: 270000 [ 110.572126] [drm:intel_dump_pipe_config] pipe src size: 2560x1600 [ 110.572137] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 110.572148] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 110.572160] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 110.572169] [drm:intel_dump_pipe_config] ips: 0 [ 110.572178] [drm:intel_dump_pipe_config] double wide: 0 [ 110.572191] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 110.572200] [drm:intel_dump_pipe_config] planes on this crtc [ 110.572218] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled [ 110.572233] [drm:intel_dump_pipe_config] FB:61, fb = 1920x1080 format = 0x34325258 [ 110.572248] [drm:intel_dump_pipe_config] scaler:0 src (0, 0) 1920x1080 dst (0, 0) 1920x1080 [ 110.572262] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 110.572276] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 110.572290] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0 [ 110.572321] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000 [ 110.572386] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 110.587628] [drm:intel_edp_backlight_off] [ 110.790252] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 110.790536] [drm:edp_panel_off] Turn eDP port C panel power off [ 110.790556] [drm:wait_panel_off] Wait for panel power off time [ 110.790575] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 110.830972] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 110.830998] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 110.831013] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 110.831752] [drm:wait_panel_status] Wait complete [ 110.831799] [drm:intel_disable_pipe] disabling pipe A [ 110.831854] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 110.845663] [drm:intel_dp_link_down] [ 110.916693] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x050007fd) [ 110.942259] [drm:intel_update_cdclk] Current CD clock rate: 320000 kHz [ 110.942317] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x0d0007fd) [ 111.084429] [drm:intel_dp_reset_link_train] flt enabled: true [ 111.169619] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 111.169640] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 111.171566] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 111.257924] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 111.257948] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 111.344238] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 111.344261] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 111.430088] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 111.430109] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 111.431442] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 111.431679] [drm:intel_enable_dp] Enabling DP audio on pipe A [ 111.431699] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44] [ 111.431713] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD [ 111.439794] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 111.439835] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=191, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=1 cxsr=0 [ 111.439851] [drm:intel_enable_pipe] enabling pipe A [ 111.439891] [drm:intel_psr_enable] PSR not supported by this panel [ 111.457130] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 111.457161] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 111.457180] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 111.457197] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 111.457208] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 111.457222] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 111.457234] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 111.457251] [drm:check_crtc_state] [CRTC:26] [ 111.469803] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 111.469840] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=191, cursor=0, sprite0=0, sprite1=0, SR: plane=1215, cursor=0 level=1 cxsr=1 [ 111.469855] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 111.473597] [drm:internal_framebuffer_create] could not create framebuffer [ 111.473631] [drm:internal_framebuffer_create] could not create framebuffer [ 111.473809] [drm:drm_mode_addfb2] [FB:149] [ 111.474670] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 111.474745] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 111.474926] [drm:connected_sink_compute_bpp] [CONNECTOR:47:eDP-1] checking for sink bpp constrains [ 111.474942] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 111.474963] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz [ 111.474997] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 111.475009] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 111.475023] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 111.475041] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff88017886a000 for pipe B [ 111.475051] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 111.475061] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 111.475074] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 111.475089] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 111.475103] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 111.475113] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 111.475122] [drm:intel_dump_pipe_config] requested mode: [ 111.475140] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x0 0xa [ 111.475150] [drm:intel_dump_pipe_config] adjusted mode: [ 111.475167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 111.475184] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 111.475195] [drm:intel_dump_pipe_config] port clock: 270000 [ 111.475205] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 111.475216] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 111.475235] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 111.475247] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 111.475256] [drm:intel_dump_pipe_config] ips: 0 [ 111.475265] [drm:intel_dump_pipe_config] double wide: 0 [ 111.475278] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 111.475322] [drm:intel_dump_pipe_config] planes on this crtc [ 111.475337] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0 [ 111.475350] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0 [ 111.475364] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0 [ 111.475377] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0 [ 111.475393] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000 [ 111.479509] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x1d0607fd) [ 111.579865] [drm:vlv_detach_power_sequencer] detaching pipe A power sequencer from port C [ 111.579886] [drm:vlv_init_panel_power_sequencer] initializing pipe B power sequencer for port C [ 111.579904] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06 [ 111.579921] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 111.579930] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 111.579944] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 111.579954] [drm:wait_panel_status] Wait complete [ 111.579968] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 111.579978] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled [ 111.615389] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 111.615414] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 111.615430] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 1 [ 111.615816] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 111.782247] [drm:edp_panel_on] Turn eDP port C panel power on [ 111.782269] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 111.782286] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 111.782295] [drm:wait_panel_status] Wait complete [ 111.782308] [drm:wait_panel_on] Wait for panel power on [ 111.782322] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b [ 111.921922] [drm:wait_panel_status] Wait complete [ 111.921949] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 111.921972] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 111.922002] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 111.922022] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 111.922694] [drm:intel_dp_reset_link_train] flt enabled: true [ 111.965768] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 111.965790] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 111.967466] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 111.968688] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 111.973478] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 111.973507] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 111.973536] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 111.973549] [drm:intel_enable_pipe] enabling pipe B [ 111.973589] [drm:intel_edp_backlight_on] [ 111.973602] [drm:intel_panel_enable_backlight] pipe B [ 111.973618] [drm:intel_panel_actually_set_backlight] set backlight PWM = 6000 [ 111.973648] [drm:intel_psr_match_conditions] PSR disable by flag [ 111.990787] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 111.990817] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 111.990837] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 111.990847] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 111.990858] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 111.990869] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 111.990883] [drm:check_crtc_state] [CRTC:31] [ 112.003677] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3000/6000 [ 112.003699] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 112.007293] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 112.007325] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 112.128489] [drm:drm_mode_getconnector] [CONNECTOR:55:?] [ 112.128498] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] [ 112.128502] [drm:intel_dp_detect] [CONNECTOR:55:DP-2] [ 112.128507] [drm:intel_power_well_enable] enabling dpio-common-d [ 112.145203] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x1d0607ff) [ 112.154056] [drm:intel_power_well_disable] disabling dpio-common-d [ 112.163206] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x1d0607fd) [ 112.172062] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] disconnected [ 112.172128] [drm:drm_mode_getconnector] [CONNECTOR:40:?] [ 112.172137] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] [ 112.172142] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1] [ 112.172436] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 112.172443] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 112.172799] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 112.172807] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 112.172813] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] disconnected [ 112.172835] [drm:drm_mode_getconnector] [CONNECTOR:53:?] [ 112.172842] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] [ 112.172846] [drm:intel_hdmi_detect] [CONNECTOR:53:HDMI-A-2] [ 112.298178] [drm:intel_hdmi_detect] Live status not up! [ 112.298205] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] disconnected [ 112.576451] [drm:internal_framebuffer_create] could not create framebuffer [ 114.502604] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 114.502645] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 114.502700] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 114.502711] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 114.970182] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 114.970214] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007 [ 117.447058] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 117.447098] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=351, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 117.447241] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 117.447271] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 117.551242] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 117.551334] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 117.767106] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 117.767198] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 117.775035] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 117.775126] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 125.675440] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 125.675477] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 125.676906] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 125.676936] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 125.679442] [drm:internal_framebuffer_create] could not create framebuffer [ 125.679477] [drm:internal_framebuffer_create] could not create framebuffer [ 125.697157] [drm:drm_mode_addfb2] [FB:159] [ 125.698048] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 125.698066] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 125.698132] [drm:connected_sink_compute_bpp] [CONNECTOR:47:eDP-1] checking for sink bpp constrains [ 125.698139] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 125.698151] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz [ 125.698170] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 125.698176] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 125.698186] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 125.698195] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff880178f9d000 for pipe A [ 125.698200] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 125.698205] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 125.698211] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 125.698219] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 125.698237] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 125.698242] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 125.698247] [drm:intel_dump_pipe_config] requested mode: [ 125.698257] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x0 0xa [ 125.698261] [drm:intel_dump_pipe_config] adjusted mode: [ 125.698270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 125.698279] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 125.698284] [drm:intel_dump_pipe_config] port clock: 270000 [ 125.698289] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 125.698294] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 125.698300] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 125.698306] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 125.698311] [drm:intel_dump_pipe_config] ips: 0 [ 125.698315] [drm:intel_dump_pipe_config] double wide: 0 [ 125.698322] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 125.698327] [drm:intel_dump_pipe_config] planes on this crtc [ 125.698333] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled [ 125.698340] [drm:intel_dump_pipe_config] FB:144, fb = 2560x1600 format = 0x34325258 [ 125.698348] [drm:intel_dump_pipe_config] scaler:0 src (0, 0) 2560x1600 dst (0, 0) 2560x1600 [ 125.698356] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 125.698363] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 125.698371] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0 [ 125.698385] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 125.701493] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 125.714419] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A [ 125.718751] [drm:intel_disable_pipe] disabling pipe A [ 125.732660] [drm:intel_dp_link_down] [ 125.762414] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x150607fd) [ 125.773636] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 125.790944] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 125.790980] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 125.790996] [drm:intel_edp_backlight_off] [ 125.994162] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 125.994437] [drm:edp_panel_off] Turn eDP port C panel power off [ 125.994458] [drm:wait_panel_off] Wait for panel power off time [ 125.994477] [drm:wait_panel_status] mask b0000000 value 00000000 status e0000003 control abcd0000 [ 126.028668] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 126.028693] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 126.028708] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 126.029133] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 126.035076] [drm:wait_panel_status] Wait complete [ 126.035126] [drm:intel_disable_pipe] disabling pipe B [ 126.042273] [drm:intel_dp_link_down] [ 126.116743] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x050007fd) [ 126.127938] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 126.127974] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 126.146949] [drm:intel_update_cdclk] Current CD clock rate: 266667 kHz [ 126.147009] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x150607fd) [ 126.246361] [drm:vlv_detach_power_sequencer] detaching pipe B power sequencer from port C [ 126.246389] [drm:vlv_init_panel_power_sequencer] initializing pipe A power sequencer for port C [ 126.246414] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06 [ 126.246441] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 126.246453] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 126.598097] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 126.598122] [drm:wait_panel_status] Wait complete [ 126.598144] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 126.598156] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled [ 126.633090] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 126.633116] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 126.633131] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 1 [ 126.633543] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 126.802085] [drm:edp_panel_on] Turn eDP port C panel power on [ 126.802112] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 126.802133] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 126.802145] [drm:wait_panel_status] Wait complete [ 126.802160] [drm:wait_panel_on] Wait for panel power on [ 126.802175] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b [ 126.965360] [drm:wait_panel_status] Wait complete [ 126.965389] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 126.965419] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 126.965453] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 126.965474] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 126.966938] [drm:intel_dp_reset_link_train] flt enabled: true [ 127.009441] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 127.009463] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 127.010877] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 127.012115] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 127.012467] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 127.012496] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 127.012508] [drm:intel_enable_pipe] enabling pipe A [ 127.012543] [drm:intel_edp_backlight_on] [ 127.012557] [drm:intel_panel_enable_backlight] pipe A [ 127.012574] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 127.012601] [drm:intel_psr_match_conditions] PSR disable by flag [ 127.029875] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 127.029906] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 127.029923] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 127.029940] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 127.029954] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 127.029964] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 127.029976] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 127.029995] [drm:check_crtc_state] [CRTC:26] [ 127.041158] [drm:check_crtc_state] [CRTC:31] [ 127.041600] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 127.041632] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 127.041646] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 127.045942] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 127.053083] [drm:internal_framebuffer_create] could not create framebuffer [ 127.053120] [drm:internal_framebuffer_create] could not create framebuffer [ 127.053324] [drm:drm_mode_addfb2] [FB:151] [ 127.054074] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 127.054103] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 127.054175] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains [ 127.054188] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 127.054211] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 241500KHz [ 127.054230] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24 [ 127.054235] [drm:intel_dp_compute_config] DP link bw required 579600 available 864000 [ 127.054243] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 127.054252] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880178869000 for pipe B [ 127.054257] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 127.054262] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 127.054269] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 127.054277] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5627357, gmch_n: 8388608, link_m: 468946, link_n: 524288, tu: 64 [ 127.054284] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 127.054306] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 127.054325] [drm:intel_dump_pipe_config] requested mode: [ 127.054358] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x0 0x5 [ 127.054387] [drm:intel_dump_pipe_config] adjusted mode: [ 127.054418] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x0 0x5 [ 127.054450] [drm:intel_dump_crtc_timings] crtc timings: 241500 2560 2608 2640 2720 1440 1443 1448 1481, type: 0x0 flags: 0x5 [ 127.054479] [drm:intel_dump_pipe_config] port clock: 270000 [ 127.054491] [drm:intel_dump_pipe_config] pipe src size: 2560x1440 [ 127.054497] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 127.054503] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 127.054509] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 127.054514] [drm:intel_dump_pipe_config] ips: 0 [ 127.054518] [drm:intel_dump_pipe_config] double wide: 0 [ 127.054525] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 127.054529] [drm:intel_dump_pipe_config] planes on this crtc [ 127.054536] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0 [ 127.054543] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0 [ 127.054550] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0 [ 127.054556] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0 [ 127.054564] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 127.057637] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x1d0607fd) [ 127.203147] [drm:intel_dp_reset_link_train] flt enabled: true [ 127.289096] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 127.289118] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 127.291426] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 127.376658] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 127.376680] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 127.378951] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 127.379202] [drm:intel_enable_dp] Enabling DP audio on pipe B [ 127.379224] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44] [ 127.379238] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD [ 127.389832] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 127.389866] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 127.389902] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=351, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 127.389934] [drm:intel_enable_pipe] enabling pipe B [ 127.389981] [drm:intel_psr_enable] PSR not supported by this panel [ 127.407895] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 127.407929] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 127.407948] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 127.407961] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 127.407972] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 127.407985] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 127.407998] [drm:check_crtc_state] [CRTC:31] [ 127.441685] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun [ 127.539125] [drm:drm_mode_getconnector] [CONNECTOR:55:?] [ 127.539134] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] [ 127.539137] [drm:intel_dp_detect] [CONNECTOR:55:DP-2] [ 127.539142] [drm:intel_power_well_enable] enabling dpio-common-d [ 127.557594] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x1d0607ff) [ 127.566740] [drm:intel_power_well_disable] disabling dpio-common-d [ 127.575778] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x1d0607fd) [ 127.585268] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] disconnected [ 127.585332] [drm:drm_mode_getconnector] [CONNECTOR:40:?] [ 127.585340] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] [ 127.585345] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1] [ 127.585533] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 127.585538] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 127.586961] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 127.586974] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 127.586984] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] disconnected [ 127.587019] [drm:drm_mode_getconnector] [CONNECTOR:53:?] [ 127.587030] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] [ 127.587037] [drm:intel_hdmi_detect] [CONNECTOR:53:HDMI-A-2] [ 127.714425] [drm:intel_hdmi_detect] Live status not up! [ 127.714452] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] disconnected [ 130.017960] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 130.017994] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007 [ 168.929632] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 168.929719] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 168.929773] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 168.942051] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe B [ 168.942320] [drm:intel_disable_pipe] disabling pipe B [ 168.958815] [drm:intel_dp_link_down] [ 168.989714] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x150607fd) [ 168.998436] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 168.998475] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 168.998489] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 169.010101] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 169.010133] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 169.010153] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 169.010169] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 169.010181] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 169.010193] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 169.010211] [drm:check_crtc_state] [CRTC:31] [ 169.012112] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 169.012143] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 169.054318] [drm:drm_mode_addfb2] [FB:145] [ 169.055242] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 169.055252] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 169.056981] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 169.056987] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 169.064554] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 169.064567] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 169.064967] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 169.064976] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 169.064998] [drm:connected_sink_compute_bpp] [CONNECTOR:47:eDP-1] checking for sink bpp constrains [ 169.065001] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 169.065007] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz [ 169.065016] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 169.065018] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 169.065022] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 169.065026] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880178f9a800 for pipe B [ 169.065028] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 169.065030] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 169.065033] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 169.065036] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 169.065039] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 169.065041] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 169.065043] [drm:intel_dump_pipe_config] requested mode: [ 169.065047] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x0 0xa [ 169.065049] [drm:intel_dump_pipe_config] adjusted mode: [ 169.065053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 169.065056] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 169.065058] [drm:intel_dump_pipe_config] port clock: 270000 [ 169.065060] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 169.065062] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 169.065065] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 169.065067] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 169.065069] [drm:intel_dump_pipe_config] ips: 0 [ 169.065071] [drm:intel_dump_pipe_config] double wide: 0 [ 169.065074] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 169.065075] [drm:intel_dump_pipe_config] planes on this crtc [ 169.065078] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0 [ 169.065081] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0 [ 169.065084] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0 [ 169.065086] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0 [ 169.065091] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 169.065107] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 169.080298] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 169.080322] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 169.080327] [drm:intel_edp_backlight_off] [ 169.281617] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 169.281877] [drm:edp_panel_off] Turn eDP port C panel power off [ 169.281885] [drm:wait_panel_off] Wait for panel power off time [ 169.281892] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 169.322330] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 169.322355] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 169.322367] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 169.322457] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 169.323128] [drm:wait_panel_status] Wait complete [ 169.323151] [drm:intel_disable_pipe] disabling pipe A [ 169.331090] [drm:intel_dp_link_down] [ 169.405348] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x050007fd) [ 169.417637] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 169.417677] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 169.417742] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x150607fd) [ 169.516781] [drm:vlv_detach_power_sequencer] detaching pipe A power sequencer from port C [ 169.516812] [drm:vlv_init_panel_power_sequencer] initializing pipe B power sequencer for port C [ 169.516837] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06 [ 169.516864] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 169.516876] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 169.885635] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 169.885658] [drm:wait_panel_status] Wait complete [ 169.885679] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 169.885692] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled [ 169.920554] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 169.920580] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 169.920594] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 1 [ 169.920740] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 170.089627] [drm:edp_panel_on] Turn eDP port C panel power on [ 170.089653] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 170.089677] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 170.089688] [drm:wait_panel_status] Wait complete [ 170.089703] [drm:wait_panel_on] Wait for panel power on [ 170.089718] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b [ 170.252680] [drm:wait_panel_status] Wait complete [ 170.252710] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 170.252735] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 170.252770] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 170.252789] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 170.253689] [drm:intel_dp_reset_link_train] flt enabled: true [ 170.295440] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 170.295462] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 170.296705] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 170.297829] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 170.298203] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 170.298245] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 170.298256] [drm:intel_enable_pipe] enabling pipe B [ 170.298294] [drm:intel_edp_backlight_on] [ 170.298306] [drm:intel_panel_enable_backlight] pipe B [ 170.298358] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 170.298385] [drm:intel_psr_match_conditions] PSR disable by flag [ 170.315501] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 170.315533] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 170.315554] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 170.315567] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 170.315579] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 170.315591] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 170.315609] [drm:check_crtc_state] [CRTC:26] [ 170.315626] [drm:check_crtc_state] [CRTC:31] [ 170.329242] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 170.329379] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 170.329395] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 170.335649] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 170.341152] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 170.341192] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 170.341666] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains [ 170.341676] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 170.341687] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148352KHz [ 170.341709] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 170.341715] [drm:intel_dp_compute_config] DP link bw required 356045 available 518400 [ 170.341723] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 170.341733] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff88017886e800 for pipe A [ 170.341739] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 170.341745] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 170.341752] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 170.341760] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5761420, gmch_n: 8388608, link_m: 240059, link_n: 262144, tu: 64 [ 170.341768] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 170.341773] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 170.341778] [drm:intel_dump_pipe_config] requested mode: [ 170.341788] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5 [ 170.341794] [drm:intel_dump_pipe_config] adjusted mode: [ 170.341803] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5 [ 170.341812] [drm:intel_dump_crtc_timings] crtc timings: 148352 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x0 flags: 0x5 [ 170.341819] [drm:intel_dump_pipe_config] port clock: 162000 [ 170.341824] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 170.341830] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 170.341837] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 170.341843] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 170.341848] [drm:intel_dump_pipe_config] ips: 0 [ 170.341853] [drm:intel_dump_pipe_config] double wide: 0 [ 170.341861] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 170.341866] [drm:intel_dump_pipe_config] planes on this crtc [ 170.341873] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 disabled, scaler_id = 0 [ 170.341880] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 170.341888] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 170.341895] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0 [ 170.341904] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 170.341961] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x1d0607fd) [ 170.484896] [drm:intel_dp_reset_link_train] flt enabled: false [ 170.569966] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 170.569987] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 170.570939] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 170.656693] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 170.656715] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 170.744153] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 170.744175] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 170.830240] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 170.830261] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 170.831571] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 170.831796] [drm:intel_enable_dp] Enabling DP audio on pipe A [ 170.831818] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44] [ 170.831832] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD [ 170.842665] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 170.842698] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 170.842749] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 170.842763] [drm:intel_enable_pipe] enabling pipe A [ 170.842812] [drm:intel_psr_enable] PSR not supported by this panel [ 170.860412] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 170.860443] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 170.860463] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 170.860475] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 170.860485] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 170.860500] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 170.860512] [drm:check_crtc_state] [CRTC:26] [ 170.992880] [drm:drm_mode_getconnector] [CONNECTOR:55:?] [ 170.992889] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] [ 170.992892] [drm:intel_dp_detect] [CONNECTOR:55:DP-2] [ 170.992898] [drm:intel_power_well_enable] enabling dpio-common-d [ 171.007312] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x1d0607ff) [ 171.015283] [drm:intel_power_well_disable] disabling dpio-common-d [ 171.023671] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x1d0607fd) [ 171.029264] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] disconnected [ 171.029316] [drm:drm_mode_getconnector] [CONNECTOR:40:?] [ 171.029321] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] [ 171.029324] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1] [ 171.029807] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 171.029810] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 171.029972] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 171.029976] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 171.029979] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] disconnected [ 171.029991] [drm:drm_mode_getconnector] [CONNECTOR:53:?] [ 171.029994] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] [ 171.029996] [drm:intel_hdmi_detect] [CONNECTOR:53:HDMI-A-2] [ 171.157554] [drm:intel_hdmi_detect] Live status not up! [ 171.157582] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] disconnected [ 171.418311] [drm:drm_mode_addfb2] [FB:161] [ 173.305558] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 173.305583] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007 [ 182.130816] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 182.130898] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 182.130952] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 182.138210] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A [ 182.138478] [drm:intel_disable_pipe] disabling pipe A [ 182.154601] [drm:intel_dp_link_down] [ 182.185398] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x150607fd) [ 182.197295] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 182.197335] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 182.197350] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 182.209714] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 182.209744] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 182.209762] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 182.209778] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 182.209789] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 182.209801] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 182.209821] [drm:check_crtc_state] [CRTC:26] [ 182.213471] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 182.213508] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 182.232226] [drm:drm_mode_addfb2] [FB:151] [ 182.232862] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 182.232878] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 182.233496] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 182.233509] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 182.249909] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 182.249932] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 182.251288] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 182.251307] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 182.251352] [drm:connected_sink_compute_bpp] [CONNECTOR:47:eDP-1] checking for sink bpp constrains [ 182.251360] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 182.251372] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz [ 182.251392] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 182.251398] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 182.251406] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 182.251417] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff88017886c000 for pipe A [ 182.251422] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 182.251428] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 182.251435] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 182.251443] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 182.251451] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 182.251456] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 182.251461] [drm:intel_dump_pipe_config] requested mode: [ 182.251471] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x0 0xa [ 182.251476] [drm:intel_dump_pipe_config] adjusted mode: [ 182.251486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 182.251495] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 182.251501] [drm:intel_dump_pipe_config] port clock: 270000 [ 182.251506] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 182.251512] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 182.251518] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 182.251525] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 182.251530] [drm:intel_dump_pipe_config] ips: 0 [ 182.251535] [drm:intel_dump_pipe_config] double wide: 0 [ 182.251542] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 182.251547] [drm:intel_dump_pipe_config] planes on this crtc [ 182.251554] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 disabled, scaler_id = 0 [ 182.251562] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 182.251569] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 182.251576] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0 [ 182.251585] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 182.251628] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 182.265845] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 182.265868] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 182.265879] [drm:intel_edp_backlight_off] [ 182.469651] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 182.469956] [drm:edp_panel_off] Turn eDP port C panel power off [ 182.469976] [drm:wait_panel_off] Wait for panel power off time [ 182.469995] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 182.510642] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 182.510668] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 182.510683] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 182.510822] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 182.510868] [drm:wait_panel_status] Wait complete [ 182.510909] [drm:intel_disable_pipe] disabling pipe B [ 182.515292] [drm:intel_dp_link_down] [ 182.589171] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x050007fd) [ 182.600659] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 182.600697] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 182.600745] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x150607fd) [ 182.699664] [drm:vlv_detach_power_sequencer] detaching pipe B power sequencer from port C [ 182.699692] [drm:vlv_init_panel_power_sequencer] initializing pipe A power sequencer for port C [ 182.699718] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06 [ 182.699742] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 182.699753] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 183.073704] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 183.073727] [drm:wait_panel_status] Wait complete [ 183.073747] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 183.073759] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled [ 183.108629] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 183.108655] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 183.108670] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 1 [ 183.108945] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 183.277635] [drm:edp_panel_on] Turn eDP port C panel power on [ 183.277661] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 183.277682] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 183.277695] [drm:wait_panel_status] Wait complete [ 183.277708] [drm:wait_panel_on] Wait for panel power on [ 183.277722] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b [ 183.441253] [drm:wait_panel_status] Wait complete [ 183.441281] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 183.441307] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 183.441338] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 183.441357] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 183.442026] [drm:intel_dp_reset_link_train] flt enabled: true [ 183.484091] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 183.484114] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 183.485030] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 183.486737] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 183.487219] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 183.487249] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 183.487262] [drm:intel_enable_pipe] enabling pipe A [ 183.487303] [drm:intel_edp_backlight_on] [ 183.487316] [drm:intel_panel_enable_backlight] pipe A [ 183.487331] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 183.487364] [drm:intel_psr_match_conditions] PSR disable by flag [ 183.504542] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 183.504572] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 183.504593] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 183.504606] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 183.504618] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 183.504630] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 183.504644] [drm:check_crtc_state] [CRTC:26] [ 183.517259] [drm:check_crtc_state] [CRTC:31] [ 183.517672] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 183.517704] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 183.517718] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 183.520021] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 183.523804] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 183.523837] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 183.523986] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains [ 183.524002] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 183.524022] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 119000KHz [ 183.524059] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 183.524070] [drm:intel_dp_compute_config] DP link bw required 285600 available 518400 [ 183.524085] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 183.524103] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880178868000 for pipe B [ 183.524113] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 183.524123] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 183.524136] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 183.524152] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4621501, gmch_n: 8388608, link_m: 192562, link_n: 262144, tu: 64 [ 183.524165] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 183.524176] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 183.524184] [drm:intel_dump_pipe_config] requested mode: [ 183.524203] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x0 0x9 [ 183.524212] [drm:intel_dump_pipe_config] adjusted mode: [ 183.524230] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x0 0x9 [ 183.524246] [drm:intel_dump_crtc_timings] crtc timings: 119000 1680 1728 1760 1840 1050 1053 1059 1080, type: 0x0 flags: 0x9 [ 183.524259] [drm:intel_dump_pipe_config] port clock: 162000 [ 183.524269] [drm:intel_dump_pipe_config] pipe src size: 1680x1050 [ 183.524288] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 183.524300] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 183.524312] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 183.524321] [drm:intel_dump_pipe_config] ips: 0 [ 183.524330] [drm:intel_dump_pipe_config] double wide: 0 [ 183.524345] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 183.524354] [drm:intel_dump_pipe_config] planes on this crtc [ 183.524367] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0 [ 183.524382] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0 [ 183.524395] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0 [ 183.524408] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0 [ 183.524424] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 183.524515] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x1d0607fd) [ 183.671196] [drm:intel_dp_reset_link_train] flt enabled: true [ 183.757706] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 183.757727] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 183.758558] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 183.843069] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 183.843093] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 183.928925] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 183.928948] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 183.931157] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 183.931401] [drm:intel_enable_dp] Enabling DP audio on pipe B [ 183.931424] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44] [ 183.931438] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD [ 183.941259] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 183.941291] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 183.941324] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=406, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 183.941337] [drm:intel_enable_pipe] enabling pipe B [ 183.941398] [drm:intel_psr_enable] PSR not supported by this panel [ 183.958342] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 183.958374] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 183.958393] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 183.958406] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 183.958416] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 183.958429] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 183.958442] [drm:check_crtc_state] [CRTC:31] [ 184.315266] [drm:drm_mode_addfb2] [FB:176] [ 186.489459] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 186.489490] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007 [ 197.317287] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 197.317373] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 197.317430] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 197.318314] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe B [ 197.322068] [drm:intel_disable_pipe] disabling pipe B [ 197.335698] [drm:intel_dp_link_down] [ 197.365201] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x150607fd) [ 197.376805] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 197.376844] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 197.376860] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 197.388102] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 197.388133] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 197.388153] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 197.388167] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 197.388177] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 197.388189] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 197.388210] [drm:check_crtc_state] [CRTC:31] [ 197.393183] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 197.393218] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 197.410697] [drm:drm_mode_addfb2] [FB:145] [ 197.411587] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 197.411604] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 197.412913] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 197.412925] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 197.422604] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 197.422621] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 197.423625] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 197.423639] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 197.423674] [drm:connected_sink_compute_bpp] [CONNECTOR:47:eDP-1] checking for sink bpp constrains [ 197.423679] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 197.423688] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz [ 197.423702] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 197.423706] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 197.423712] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 197.423718] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880178f9c000 for pipe B [ 197.423722] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 197.423725] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 197.423730] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 197.423736] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 197.423740] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 197.423744] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 197.423747] [drm:intel_dump_pipe_config] requested mode: [ 197.423754] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x0 0xa [ 197.423758] [drm:intel_dump_pipe_config] adjusted mode: [ 197.423764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 197.423770] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 197.423773] [drm:intel_dump_pipe_config] port clock: 270000 [ 197.423777] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 197.423781] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 197.423785] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 197.423789] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 197.423792] [drm:intel_dump_pipe_config] ips: 0 [ 197.423796] [drm:intel_dump_pipe_config] double wide: 0 [ 197.423800] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 197.423803] [drm:intel_dump_pipe_config] planes on this crtc [ 197.423808] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0 [ 197.423813] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0 [ 197.423818] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0 [ 197.423822] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0 [ 197.423829] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 197.423857] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 197.437904] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 197.437920] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 197.437928] [drm:intel_edp_backlight_off] [ 197.641381] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 197.641728] [drm:edp_panel_off] Turn eDP port C panel power off [ 197.641750] [drm:wait_panel_off] Wait for panel power off time [ 197.641770] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 197.682270] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 197.682296] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 197.682311] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 197.682449] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 197.683623] [drm:wait_panel_status] Wait complete [ 197.683672] [drm:intel_disable_pipe] disabling pipe A [ 197.688135] [drm:intel_dp_link_down] [ 197.760177] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x050007fd) [ 197.771405] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 197.771445] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 197.771512] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x150607fd) [ 197.870692] [drm:vlv_detach_power_sequencer] detaching pipe A power sequencer from port C [ 197.870722] [drm:vlv_init_panel_power_sequencer] initializing pipe B power sequencer for port C [ 197.870745] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06 [ 197.870771] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 197.870784] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 198.245576] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 198.245599] [drm:wait_panel_status] Wait complete [ 198.245619] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 198.245631] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled [ 198.280503] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 198.280529] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 198.280546] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 1 [ 198.280826] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 198.449436] [drm:edp_panel_on] Turn eDP port C panel power on [ 198.449464] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 198.449485] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 198.449497] [drm:wait_panel_status] Wait complete [ 198.449513] [drm:wait_panel_on] Wait for panel power on [ 198.449528] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control abcd000b [ 198.613073] [drm:wait_panel_status] Wait complete [ 198.613102] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 198.613128] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 198.613163] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 198.613183] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 198.613906] [drm:intel_dp_reset_link_train] flt enabled: true [ 198.656646] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 198.656669] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 198.658192] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 198.659377] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 198.659746] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 198.659778] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 198.659789] [drm:intel_enable_pipe] enabling pipe B [ 198.659830] [drm:intel_edp_backlight_on] [ 198.659845] [drm:intel_panel_enable_backlight] pipe B [ 198.659860] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 198.659888] [drm:intel_psr_match_conditions] PSR disable by flag [ 198.677280] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 198.677312] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 198.677332] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 198.677346] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 198.677358] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 198.677372] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 198.677390] [drm:check_crtc_state] [CRTC:26] [ 198.677406] [drm:check_crtc_state] [CRTC:31] [ 198.688837] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 198.688875] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 198.688891] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 198.691847] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 198.696753] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 198.696785] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 198.696848] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains [ 198.696862] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 198.696880] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 135000KHz [ 198.696915] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 198.696926] [drm:intel_dp_compute_config] DP link bw required 324000 available 518400 [ 198.697006] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 198.697027] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff88017886d800 for pipe A [ 198.697037] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 198.697047] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 198.697061] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 198.697076] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5242880, gmch_n: 8388608, link_m: 218453, link_n: 262144, tu: 64 [ 198.697089] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 198.697100] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 198.697108] [drm:intel_dump_pipe_config] requested mode: [ 198.697128] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x0 0x5 [ 198.697138] [drm:intel_dump_pipe_config] adjusted mode: [ 198.697155] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x0 0x5 [ 198.697185] [drm:intel_dump_crtc_timings] crtc timings: 135000 1280 1296 1440 1688 1024 1025 1028 1066, type: 0x0 flags: 0x5 [ 198.697195] [drm:intel_dump_pipe_config] port clock: 162000 [ 198.697205] [drm:intel_dump_pipe_config] pipe src size: 1280x1024 [ 198.697216] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 198.697228] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 198.697239] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 198.697249] [drm:intel_dump_pipe_config] ips: 0 [ 198.697258] [drm:intel_dump_pipe_config] double wide: 0 [ 198.697270] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 198.697279] [drm:intel_dump_pipe_config] planes on this crtc [ 198.697293] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 disabled, scaler_id = 0 [ 198.697306] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 198.697319] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 198.697332] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0 [ 198.697348] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 198.697430] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x1d0607fd) [ 198.842390] [drm:intel_dp_reset_link_train] flt enabled: true [ 198.928793] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 198.928814] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 198.930473] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 199.014914] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 199.014937] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 199.100375] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 199.100396] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 199.101912] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 199.102734] [drm:intel_enable_dp] Enabling DP audio on pipe A [ 199.102758] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44] [ 199.102773] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD [ 199.114247] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 199.114281] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 199.114315] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=431, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 199.114328] [drm:intel_enable_pipe] enabling pipe A [ 199.114394] [drm:intel_psr_enable] PSR not supported by this panel [ 199.128304] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 199.128336] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 199.128354] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 199.128366] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 199.128377] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 199.128389] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 199.128402] [drm:check_crtc_state] [CRTC:26] [ 199.253402] [drm:drm_mode_getconnector] [CONNECTOR:55:?] [ 199.253410] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] [ 199.253413] [drm:intel_dp_detect] [CONNECTOR:55:DP-2] [ 199.253419] [drm:intel_power_well_enable] enabling dpio-common-d [ 199.268966] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x1d0607ff) [ 199.276971] [drm:intel_power_well_disable] disabling dpio-common-d [ 199.285004] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x1d0607fd) [ 199.292966] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] disconnected [ 199.293016] [drm:drm_mode_getconnector] [CONNECTOR:40:?] [ 199.293020] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] [ 199.293023] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1] [ 199.293391] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 199.293394] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 199.293562] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 199.293565] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 199.293568] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] disconnected [ 199.293580] [drm:drm_mode_getconnector] [CONNECTOR:53:?] [ 199.293583] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] [ 199.293585] [drm:intel_hdmi_detect] [CONNECTOR:53:HDMI-A-2] [ 199.420948] [drm:intel_hdmi_detect] Live status not up! [ 199.420959] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] disconnected [ 199.593224] [drm:drm_mode_addfb2] [FB:178] [ 201.665337] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 201.665370] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007 [ 209.486800] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 209.486840] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 209.506233] [drm:drm_mode_addfb2] [FB:151] [ 209.506741] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 209.506759] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 209.512130] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 209.512151] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 209.528068] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 209.528084] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 209.528762] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 209.528774] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 209.529008] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3000/6000 [ 209.529014] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 209.529028] [drm:intel_edp_backlight_power] panel power control backlight disable [ 209.733370] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/6000 [ 209.733378] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 209.735201] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 209.735220] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 209.735274] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains [ 209.735280] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 209.735290] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 88750KHz [ 209.735308] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 209.735313] [drm:intel_dp_compute_config] DP link bw required 213000 available 259200 [ 209.735322] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 209.735331] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff88017886d000 for pipe B [ 209.735337] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 209.735342] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 209.735349] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 209.735357] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 3446708, gmch_n: 4194304, link_m: 143612, link_n: 262144, tu: 64 [ 209.735364] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 209.735369] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 209.735373] [drm:intel_dump_pipe_config] requested mode: [ 209.735383] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 88750 1440 1488 1520 1600 900 903 909 926 0x0 0x9 [ 209.735387] [drm:intel_dump_pipe_config] adjusted mode: [ 209.735396] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 88750 1440 1488 1520 1600 900 903 909 926 0x0 0x9 [ 209.735404] [drm:intel_dump_crtc_timings] crtc timings: 88750 1440 1488 1520 1600 900 903 909 926, type: 0x0 flags: 0x9 [ 209.735410] [drm:intel_dump_pipe_config] port clock: 162000 [ 209.735415] [drm:intel_dump_pipe_config] pipe src size: 1440x900 [ 209.735420] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 209.735426] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 209.735432] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 209.735437] [drm:intel_dump_pipe_config] ips: 0 [ 209.735441] [drm:intel_dump_pipe_config] double wide: 0 [ 209.735448] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 209.735453] [drm:intel_dump_pipe_config] planes on this crtc [ 209.735460] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 enabled [ 209.735467] [drm:intel_dump_pipe_config] FB:151, fb = 3360x1632 format = 0x34325258 [ 209.735475] [drm:intel_dump_pipe_config] scaler:0 src (0, 552) 1920x1080 dst (0, 0) 1920x1080 [ 209.735482] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0 [ 209.735489] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0 [ 209.735496] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0 [ 209.735506] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 209.735547] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 209.739191] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A [ 209.742922] [drm:intel_disable_pipe] disabling pipe A [ 209.753152] [drm:intel_dp_link_down] [ 209.783920] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x150607fd) [ 209.794989] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 209.795022] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 209.795034] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 209.808191] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 209.810021] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 209.810051] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 209.810065] [drm:intel_edp_backlight_off] [ 210.013146] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 210.013595] [drm:edp_panel_off] Turn eDP port C panel power off [ 210.013615] [drm:wait_panel_off] Wait for panel power off time [ 210.013632] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 210.053908] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 210.053933] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 210.053948] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 210.054328] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 210.054638] [drm:wait_panel_status] Wait complete [ 210.054682] [drm:intel_disable_pipe] disabling pipe B [ 210.061673] [drm:intel_dp_link_down] [ 210.135220] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x050007fd) [ 210.147553] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x150007fd) [ 210.156700] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0xc (PHY_CONTROL=0x1d0067fd) [ 210.257222] [drm:intel_dp_reset_link_train] flt enabled: false [ 210.298469] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 210.298491] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 210.299355] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 210.342536] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 210.342558] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 210.385485] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 210.385506] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 210.430371] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 210.430393] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 210.431630] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 210.431855] [drm:intel_enable_dp] Enabling DP audio on pipe B [ 210.431876] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44] [ 210.431890] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD [ 210.431917] [drm:chv_phy_powergate_ch] Power gating DPIO PHY0 CH1 (DPIO_PHY_CONTROL=0x0d0067fd) [ 210.443171] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 210.443209] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=331, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 210.443224] [drm:intel_enable_pipe] enabling pipe B [ 210.443265] [drm:intel_psr_enable] PSR not supported by this panel [ 210.460397] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 210.460428] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 210.460448] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 210.461172] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 210.461188] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 210.461204] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 210.461216] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 210.461236] [drm:check_crtc_state] [CRTC:26] [ 210.461255] [drm:check_crtc_state] [CRTC:31] [ 210.471801] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 210.473312] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 210.473346] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=331, cursor=0, sprite0=0, sprite1=0, SR: plane=1355, cursor=0 level=2 cxsr=1 [ 210.473361] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 210.494963] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 210.494983] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 210.495020] [drm:connected_sink_compute_bpp] [CONNECTOR:47:eDP-1] checking for sink bpp constrains [ 210.495029] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 210.495041] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz [ 210.495060] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 210.495065] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 210.495077] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 210.495086] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff8800754fd800 for pipe A [ 210.495093] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 210.495098] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 210.495105] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 210.495113] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 210.495120] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 210.495125] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 210.495129] [drm:intel_dump_pipe_config] requested mode: [ 210.495139] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x0 0xa [ 210.495143] [drm:intel_dump_pipe_config] adjusted mode: [ 210.495152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 210.495160] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 210.495166] [drm:intel_dump_pipe_config] port clock: 270000 [ 210.495171] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 210.495178] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 210.495184] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 210.495190] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 210.495195] [drm:intel_dump_pipe_config] ips: 0 [ 210.495199] [drm:intel_dump_pipe_config] double wide: 0 [ 210.495207] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 210.495212] [drm:intel_dump_pipe_config] planes on this crtc [ 210.495219] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 disabled, scaler_id = 0 [ 210.495225] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 210.495233] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 210.495242] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0 [ 210.495251] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 210.495306] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x1d0667fd) [ 210.594039] [drm:vlv_detach_power_sequencer] detaching pipe B power sequencer from port C [ 210.594069] [drm:vlv_init_panel_power_sequencer] initializing pipe A power sequencer for port C [ 210.594094] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06 [ 210.594119] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 210.594133] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 210.617374] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 210.617397] [drm:wait_panel_status] Wait complete [ 210.617419] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 210.617431] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled [ 210.652293] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 210.652319] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 210.652334] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 1 [ 210.652480] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 210.821476] [drm:edp_panel_on] Turn eDP port C panel power on [ 210.821501] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 210.821522] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 210.821533] [drm:wait_panel_status] Wait complete [ 210.821548] [drm:wait_panel_on] Wait for panel power on [ 210.821563] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b [ 210.981910] [drm:wait_panel_status] Wait complete [ 210.981939] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 210.981965] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 210.981999] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 210.982019] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 210.982708] [drm:intel_dp_reset_link_train] flt enabled: true [ 211.027138] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 211.027159] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 211.027990] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 211.030205] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 211.042552] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 211.042582] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 211.042611] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 211.042624] [drm:intel_enable_pipe] enabling pipe A [ 211.042664] [drm:intel_edp_backlight_on] [ 211.042677] [drm:intel_panel_enable_backlight] pipe A [ 211.042693] [drm:intel_panel_actually_set_backlight] set backlight PWM = 6000 [ 211.042723] [drm:intel_psr_match_conditions] PSR disable by flag [ 211.059898] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 211.059928] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 211.059946] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 211.059957] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 211.059967] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 211.059979] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 211.059991] [drm:check_crtc_state] [CRTC:26] [ 211.072709] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3000/6000 [ 211.072733] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 211.074717] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 211.074749] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 211.486027] [drm:drm_mode_addfb2] [FB:199] [ 212.139847] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 212.139891] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 212.139936] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 212.139967] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 212.172297] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 212.172338] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 212.172380] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 212.172412] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 212.188171] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 212.188216] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 212.188256] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 212.188288] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 212.195990] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 212.196033] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 212.196073] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 212.196102] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 212.204153] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 212.204170] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 212.204222] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 212.204252] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 212.900098] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 212.900142] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 212.908054] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 212.908115] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.036621] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.036713] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.044241] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.044331] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.052206] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.052297] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.060224] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.060314] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.068212] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.068301] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.076632] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.076723] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.082955] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.083047] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.092255] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.092346] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.100067] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.100159] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.107974] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.108066] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.116934] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.117131] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.129645] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.129735] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.131980] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.132070] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.139918] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.140009] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.148010] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 213.148100] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 214.033127] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 214.033160] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007 [ 215.467753] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 215.467793] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 215.475945] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 215.475987] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 215.868367] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.868403] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 215.892350] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.892440] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.900453] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.900542] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.916964] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.917053] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.924316] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.924408] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.932524] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.932614] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.940360] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.940449] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.956270] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.956361] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.972247] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 215.972338] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 216.004250] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 216.004340] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 216.204293] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 216.204386] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 216.204504] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 216.204580] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 216.212467] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 216.212558] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 216.212672] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 216.212747] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 216.220289] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 216.220379] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 216.220494] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 216.220569] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 216.228477] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 216.228515] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 216.228640] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 216.228718] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 216.709558] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 216.709651] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 216.860255] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 216.860346] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 216.868527] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 216.868618] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 217.341278] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 217.341369] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 217.413307] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.413343] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 217.420269] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.420363] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.429046] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.429137] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.788374] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.788465] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.796692] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.797338] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.804363] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.804456] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.821281] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.821372] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.829416] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.829507] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.836307] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.837884] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.844391] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.844485] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.852301] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.852393] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.877799] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.877889] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.885460] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.885549] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.900447] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 217.900485] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 218.028354] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 218.028443] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 218.036414] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 218.036506] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 218.685453] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.685491] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 218.685653] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 218.685729] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 218.693385] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.693474] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.693623] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 218.693654] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=421, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 218.757379] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.757471] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.780182] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.780272] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.924548] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.924583] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.932555] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.932586] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.940674] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.940703] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.948585] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 218.948626] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.260522] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.260547] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.268648] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.268683] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.276622] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.276656] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.509273] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.509467] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.516980] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.517028] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.524991] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.525019] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.533514] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.533556] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.541290] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 219.541339] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 227.738018] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 227.738097] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 227.738150] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 227.739485] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe B [ 227.742522] [drm:intel_disable_pipe] disabling pipe B [ 227.756720] [drm:intel_dp_link_down] [ 227.780556] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x150607fd) [ 227.792739] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 227.792775] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 227.792790] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 227.805257] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 227.805288] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 227.805309] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 227.805322] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 227.805335] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 227.805347] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 227.805365] [drm:check_crtc_state] [CRTC:31] [ 227.807777] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 227.807813] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 227.827037] [drm:drm_mode_addfb2] [FB:145] [ 227.827759] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 227.827778] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 227.843989] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 227.844010] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 227.845696] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 227.845715] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 227.845921] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3000/6000 [ 227.845931] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 227.845950] [drm:intel_edp_backlight_power] panel power control backlight disable [ 228.049159] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/6000 [ 228.049181] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 228.052606] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 228.053460] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 228.053545] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains [ 228.053559] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 228.053577] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 108000KHz [ 228.053611] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 228.053622] [drm:intel_dp_compute_config] DP link bw required 259200 available 259200 [ 228.053639] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 228.053657] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff8800754f8800 for pipe A [ 228.053668] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 228.053678] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 228.053691] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 228.053706] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 4194304, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64 [ 228.053720] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 228.053730] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 228.053739] [drm:intel_dump_pipe_config] requested mode: [ 228.053758] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 108000 1280 1376 1488 1800 960 961 964 1000 0x0 0x5 [ 228.053767] [drm:intel_dump_pipe_config] adjusted mode: [ 228.053784] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 108000 1280 1376 1488 1800 960 961 964 1000 0x0 0x5 [ 228.053801] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1376 1488 1800 960 961 964 1000, type: 0x0 flags: 0x5 [ 228.053811] [drm:intel_dump_pipe_config] port clock: 162000 [ 228.053821] [drm:intel_dump_pipe_config] pipe src size: 1280x960 [ 228.053833] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 228.053844] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 228.053856] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.053865] [drm:intel_dump_pipe_config] ips: 0 [ 228.053874] [drm:intel_dump_pipe_config] double wide: 0 [ 228.053887] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 228.053896] [drm:intel_dump_pipe_config] planes on this crtc [ 228.053912] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled [ 228.053925] [drm:intel_dump_pipe_config] FB:145, fb = 3200x1632 format = 0x34325258 [ 228.053941] [drm:intel_dump_pipe_config] scaler:0 src (0, 552) 1920x1080 dst (0, 0) 1920x1080 [ 228.053956] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 228.053971] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 228.053984] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0 [ 228.054001] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 228.054512] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 228.064185] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 228.064217] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 228.064232] [drm:intel_edp_backlight_off] [ 228.265027] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 228.265403] [drm:edp_panel_off] Turn eDP port C panel power off [ 228.265428] [drm:wait_panel_off] Wait for panel power off time [ 228.265446] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 228.305841] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 228.305866] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 228.305881] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 228.306020] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 228.306696] [drm:wait_panel_status] Wait complete [ 228.306739] [drm:intel_disable_pipe] disabling pipe A [ 228.311037] [drm:intel_dp_link_down] [ 228.384093] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x050007fd) [ 228.395687] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0xc (PHY_CONTROL=0x0d0067fd) [ 228.496563] [drm:intel_dp_reset_link_train] flt enabled: true [ 228.539028] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 228.539049] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 228.539969] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 228.585560] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 228.585583] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 228.629472] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 228.629494] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 228.630729] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 228.630955] [drm:intel_enable_dp] Enabling DP audio on pipe A [ 228.630976] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44] [ 228.630992] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD [ 228.631183] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 228.631210] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=351, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 228.631224] [drm:intel_enable_pipe] enabling pipe A [ 228.631262] [drm:intel_psr_enable] PSR not supported by this panel [ 228.648285] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 228.648318] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 228.648338] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 228.648354] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 228.648365] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 228.648380] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 228.648392] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 228.648413] [drm:check_crtc_state] [CRTC:26] [ 228.662491] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 228.662528] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=351, cursor=0, sprite0=0, sprite1=0, SR: plane=1375, cursor=0 level=2 cxsr=1 [ 228.662543] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 228.669222] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 228.669256] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 228.669324] [drm:connected_sink_compute_bpp] [CONNECTOR:47:eDP-1] checking for sink bpp constrains [ 228.669337] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 228.669358] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz [ 228.669392] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 228.669403] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 228.669418] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 228.669436] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880178f9e800 for pipe B [ 228.669448] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 228.669457] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 228.669471] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 228.669486] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 228.669500] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 228.669510] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 228.669519] [drm:intel_dump_pipe_config] requested mode: [ 228.669539] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x0 0xa [ 228.669549] [drm:intel_dump_pipe_config] adjusted mode: [ 228.669566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 228.669583] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 228.669595] [drm:intel_dump_pipe_config] port clock: 270000 [ 228.669605] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 228.669617] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 228.669629] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 228.669641] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.669650] [drm:intel_dump_pipe_config] ips: 0 [ 228.669659] [drm:intel_dump_pipe_config] double wide: 0 [ 228.669672] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 228.669681] [drm:intel_dump_pipe_config] planes on this crtc [ 228.669694] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0 [ 228.669709] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0 [ 228.669722] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0 [ 228.669737] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0 [ 228.669753] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 228.669844] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x1d0667fd) [ 228.770245] [drm:vlv_detach_power_sequencer] detaching pipe A power sequencer from port C [ 228.770275] [drm:vlv_init_panel_power_sequencer] initializing pipe B power sequencer for port C [ 228.770299] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06 [ 228.770324] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 228.770335] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 228.869106] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 228.869129] [drm:wait_panel_status] Wait complete [ 228.869151] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 228.869166] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled [ 228.904186] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 228.904213] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 228.904230] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 1 [ 228.904557] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 229.073021] [drm:edp_panel_on] Turn eDP port C panel power on [ 229.073049] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 229.073071] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 229.073081] [drm:wait_panel_status] Wait complete [ 229.073097] [drm:wait_panel_on] Wait for panel power on [ 229.073112] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b [ 229.235582] [drm:wait_panel_status] Wait complete [ 229.235611] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 229.235638] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 229.235670] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 229.235690] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 229.236374] [drm:intel_dp_reset_link_train] flt enabled: true [ 229.278309] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 229.278330] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 229.279573] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 229.282389] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 229.295296] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 229.295327] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 229.295356] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 229.295369] [drm:intel_enable_pipe] enabling pipe B [ 229.295409] [drm:intel_edp_backlight_on] [ 229.295422] [drm:intel_panel_enable_backlight] pipe B [ 229.295439] [drm:intel_panel_actually_set_backlight] set backlight PWM = 6000 [ 229.295468] [drm:intel_psr_match_conditions] PSR disable by flag [ 229.312922] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 229.312954] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 229.312973] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 229.312983] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 229.312993] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 229.313005] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 229.313018] [drm:check_crtc_state] [CRTC:31] [ 229.325512] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3000/6000 [ 229.325534] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 229.326190] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 229.326225] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 229.447142] [drm:drm_mode_getconnector] [CONNECTOR:55:?] [ 229.447150] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] [ 229.447153] [drm:intel_dp_detect] [CONNECTOR:55:DP-2] [ 229.447159] [drm:intel_power_well_enable] enabling dpio-common-d [ 229.462697] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x1d0667ff) [ 229.471871] [drm:intel_power_well_disable] disabling dpio-common-d [ 229.480659] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x1d0667fd) [ 229.490026] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] disconnected [ 229.490085] [drm:drm_mode_getconnector] [CONNECTOR:40:?] [ 229.490092] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] [ 229.490096] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1] [ 229.490392] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 229.490397] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 229.490632] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 229.490638] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 229.490643] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] disconnected [ 229.490660] [drm:drm_mode_getconnector] [CONNECTOR:53:?] [ 229.490665] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] [ 229.490669] [drm:intel_hdmi_detect] [CONNECTOR:53:HDMI-A-2] [ 229.616932] [drm:intel_hdmi_detect] Live status not up! [ 229.616960] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] disconnected [ 229.990812] [drm:drm_mode_addfb2] [FB:207] [ 230.518487] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.518528] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.518568] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.518598] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.526651] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.526689] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.526724] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.526751] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.534235] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.534281] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.534332] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.534365] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.542614] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.542661] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.542709] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.542743] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.550460] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.550547] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.550664] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.550739] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.558702] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.558791] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.558904] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.558979] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.566396] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.566485] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.566597] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.566671] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.574603] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.574691] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.574808] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.574881] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.582444] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.582533] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.582647] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.582721] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.590625] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 230.590659] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=431, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 230.590786] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 230.590865] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 232.288762] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 232.288794] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007 [ 233.678643] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.679343] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.687626] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.687715] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.822924] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.823016] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.830485] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.830576] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.839792] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.839884] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.846191] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.846273] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.862590] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.862670] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.870993] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.871084] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.887694] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.887787] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.894658] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.894746] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.910824] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.910914] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.919087] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.919177] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.926716] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.926806] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.935751] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.935840] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.942522] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.942613] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.950743] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.950833] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.962299] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.962384] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.966883] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.966971] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.974770] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.974861] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.982373] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 233.982465] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 234.390446] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 234.390537] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 234.398597] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 234.398688] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 234.471808] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 234.471846] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=431, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 234.472047] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 234.472075] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 234.479375] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 234.479416] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 234.486458] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 234.486512] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 234.494699] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 234.494751] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 234.502757] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 234.502817] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 236.391361] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 236.391401] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 236.391446] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 236.391458] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 236.439448] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 236.439482] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 236.455634] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 236.455686] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 236.463981] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 236.464062] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 236.470814] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 236.470848] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=431, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 236.470971] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 236.471045] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 237.423532] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 237.423623] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 237.623717] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 237.623809] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 237.630519] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 237.630565] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 237.638607] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 237.638668] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 258.211583] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 258.211621] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 258.274296] [drm:internal_framebuffer_create] could not create framebuffer [ 258.275064] [drm:internal_framebuffer_create] could not create framebuffer [ 258.275072] [drm:internal_framebuffer_create] could not create framebuffer [ 258.280793] [drm:drm_mode_addfb2] [FB:151] [ 258.280935] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 258.280945] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 258.281370] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 258.281375] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 258.299115] [drm:internal_framebuffer_create] could not create framebuffer [ 258.299130] [drm:internal_framebuffer_create] could not create framebuffer [ 258.306642] [drm:drm_mode_addfb2] [FB:175] [ 258.307046] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 258.307055] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 258.313405] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 258.313421] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 258.314595] [drm:internal_framebuffer_create] could not create framebuffer [ 258.314606] [drm:internal_framebuffer_create] could not create framebuffer [ 258.329685] [drm:drm_mode_addfb2] [FB:216] [ 258.330413] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 258.330444] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1] [ 258.330550] [drm:connected_sink_compute_bpp] [CONNECTOR:47:eDP-1] checking for sink bpp constrains [ 258.330565] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 258.330586] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz [ 258.330621] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 258.330632] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 258.330647] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 258.330664] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff880178f9c000 for pipe A [ 258.330674] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 258.330684] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 258.330698] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 258.330713] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 258.330727] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 258.330737] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 258.330745] [drm:intel_dump_pipe_config] requested mode: [ 258.330764] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x0 0xa [ 258.330773] [drm:intel_dump_pipe_config] adjusted mode: [ 258.330791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 258.330808] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 258.330818] [drm:intel_dump_pipe_config] port clock: 270000 [ 258.330828] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 258.330839] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 258.330850] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 258.330862] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 258.330872] [drm:intel_dump_pipe_config] ips: 0 [ 258.330881] [drm:intel_dump_pipe_config] double wide: 0 [ 258.330893] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 258.330902] [drm:intel_dump_pipe_config] planes on this crtc [ 258.330915] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled [ 258.330928] [drm:intel_dump_pipe_config] FB:151, fb = 1280x960 format = 0x34325258 [ 258.330944] [drm:intel_dump_pipe_config] scaler:0 src (0, 0) 1280x960 dst (0, 0) 1280x960 [ 258.330958] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 258.330972] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 258.330985] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0 [ 258.331003] [drm:intel_modeset_checks] New cdclk calculated to be atomic 266667, actual 266667 [ 258.331818] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 258.340119] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A [ 258.341472] [drm:intel_disable_pipe] disabling pipe A [ 258.350358] [drm:intel_dp_link_down] [ 258.373185] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x150607fd) [ 258.385072] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 258.396167] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 258.396202] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 258.396218] [drm:intel_edp_backlight_off] [ 258.596677] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 258.596949] [drm:edp_panel_off] Turn eDP port C panel power off [ 258.596971] [drm:wait_panel_off] Wait for panel power off time [ 258.596990] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 258.637460] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 258.637485] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 258.637498] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 258.637633] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 258.638245] [drm:wait_panel_status] Wait complete [ 258.638266] [drm:intel_disable_pipe] disabling pipe B [ 258.647611] [drm:intel_dp_link_down] [ 258.720013] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x050007fd) [ 258.731397] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 258.731434] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 258.742475] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x150607fd) [ 258.842587] [drm:vlv_detach_power_sequencer] detaching pipe B power sequencer from port C [ 258.842617] [drm:vlv_init_panel_power_sequencer] initializing pipe A power sequencer for port C [ 258.842641] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06 [ 258.842670] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 258.842683] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 259.200697] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 259.200721] [drm:wait_panel_status] Wait complete [ 259.200741] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 259.200757] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled [ 259.235616] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 259.235642] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 259.235657] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 1 [ 259.235945] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 259.404679] [drm:edp_panel_on] Turn eDP port C panel power on [ 259.404706] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 259.404726] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 259.404737] [drm:wait_panel_status] Wait complete [ 259.404752] [drm:wait_panel_on] Wait for panel power on [ 259.404767] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control abcd000b [ 259.567663] [drm:wait_panel_status] Wait complete [ 259.567693] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 259.567721] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 259.567753] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 259.567773] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 259.568475] [drm:intel_dp_reset_link_train] flt enabled: true [ 259.610531] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 259.610555] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 259.611507] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 259.613289] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 259.613656] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 259.613686] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 259.613698] [drm:intel_enable_pipe] enabling pipe A [ 259.613735] [drm:intel_edp_backlight_on] [ 259.613747] [drm:intel_panel_enable_backlight] pipe A [ 259.613760] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 259.613785] [drm:intel_psr_match_conditions] PSR disable by flag [ 259.631032] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 259.631066] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 259.631082] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 259.631100] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 259.631114] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 259.631124] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 259.631138] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 259.631155] [drm:check_crtc_state] [CRTC:26] [ 259.642301] [drm:check_crtc_state] [CRTC:31] [ 259.642720] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 259.642754] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1 [ 259.642769] [drm:intel_set_memory_cxsr] memory self-refresh is enabled [ 259.645341] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 259.649089] [drm:internal_framebuffer_create] could not create framebuffer [ 259.649124] [drm:internal_framebuffer_create] could not create framebuffer [ 259.692513] [drm:drm_mode_addfb2] [FB:199] [ 259.693209] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 259.693224] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 259.693250] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains [ 259.693253] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 259.693258] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz [ 259.693268] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24 [ 259.693270] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000 [ 259.693273] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 259.693278] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff88017886e000 for pipe B [ 259.693280] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 259.693282] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 259.693285] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 259.693288] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64 [ 259.693290] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 259.693292] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 259.693294] [drm:intel_dump_pipe_config] requested mode: [ 259.693298] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x0 0x9 [ 259.693300] [drm:intel_dump_pipe_config] adjusted mode: [ 259.693304] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x0 0x9 [ 259.693307] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x0 flags: 0x9 [ 259.693309] [drm:intel_dump_pipe_config] port clock: 270000 [ 259.693311] [drm:intel_dump_pipe_config] pipe src size: 3840x2160 [ 259.693313] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 259.693315] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 259.693318] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 259.693320] [drm:intel_dump_pipe_config] ips: 0 [ 259.693321] [drm:intel_dump_pipe_config] double wide: 0 [ 259.693324] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 259.693326] [drm:intel_dump_pipe_config] planes on this crtc [ 259.693329] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0 [ 259.693332] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0 [ 259.693335] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0 [ 259.693337] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0 [ 259.693349] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000 [ 259.693401] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 259.693406] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 259.693416] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains [ 259.693419] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 259.693422] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz [ 259.693428] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24 [ 259.693430] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000 [ 259.693433] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 259.693436] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880178868000 for pipe B [ 259.693438] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 259.693439] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 259.693442] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 259.693445] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64 [ 259.693447] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 259.693449] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 259.693451] [drm:intel_dump_pipe_config] requested mode: [ 259.693455] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x0 0x9 [ 259.693456] [drm:intel_dump_pipe_config] adjusted mode: [ 259.693460] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x0 0x9 [ 259.693463] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x0 flags: 0x9 [ 259.693465] [drm:intel_dump_pipe_config] port clock: 270000 [ 259.693467] [drm:intel_dump_pipe_config] pipe src size: 3840x2160 [ 259.693469] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 259.693471] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 259.693473] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 259.693475] [drm:intel_dump_pipe_config] ips: 0 [ 259.693477] [drm:intel_dump_pipe_config] double wide: 0 [ 259.693479] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 259.693481] [drm:intel_dump_pipe_config] planes on this crtc [ 259.693483] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0 [ 259.693486] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0 [ 259.693488] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0 [ 259.693491] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0 [ 259.693497] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000 [ 259.698353] [drm:drm_mode_setcrtc] [CRTC:31:crtc-1] [ 259.698362] [drm:drm_mode_setcrtc] [CONNECTOR:45:DP-1] [ 259.698380] [drm:connected_sink_compute_bpp] [CONNECTOR:45:DP-1] checking for sink bpp constrains [ 259.698384] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24 [ 259.698389] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 297000KHz [ 259.698399] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24 [ 259.698402] [drm:intel_dp_compute_config] DP link bw required 712800 available 864000 [ 259.698406] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0 [ 259.698411] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff880178868800 for pipe B [ 259.698414] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 259.698417] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 259.698421] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 259.698425] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64 [ 259.698430] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 259.698433] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 259.698435] [drm:intel_dump_pipe_config] requested mode: [ 259.698441] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x0 0x9 [ 259.698443] [drm:intel_dump_pipe_config] adjusted mode: [ 259.698449] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x0 0x9 [ 259.698454] [drm:intel_dump_crtc_timings] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x0 flags: 0x9 [ 259.698456] [drm:intel_dump_pipe_config] port clock: 270000 [ 259.698459] [drm:intel_dump_pipe_config] pipe src size: 3840x2160 [ 259.698463] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 259.698466] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 259.698470] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 259.698472] [drm:intel_dump_pipe_config] ips: 0 [ 259.698475] [drm:intel_dump_pipe_config] double wide: 0 [ 259.698479] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0 [ 259.698482] [drm:intel_dump_pipe_config] planes on this crtc [ 259.698492] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0 [ 259.698494] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0 [ 259.698497] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0 [ 259.698499] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0 [ 259.698506] [drm:intel_modeset_checks] New cdclk calculated to be atomic 320000, actual 320000 [ 259.698926] [drm:intel_set_memory_cxsr] memory self-refresh is disabled [ 259.714048] [drm:intel_edp_backlight_off] [ 259.916693] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 259.916984] [drm:edp_panel_off] Turn eDP port C panel power off [ 259.917006] [drm:wait_panel_off] Wait for panel power off time [ 259.917026] [drm:wait_panel_status] mask b0000000 value 00000000 status e0000003 control abcd0000 [ 259.957349] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 259.957375] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 259.957391] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 0 [ 259.957552] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 259.957599] [drm:wait_panel_status] Wait complete [ 259.957641] [drm:intel_disable_pipe] disabling pipe A [ 259.964293] [drm:intel_dp_link_down] [ 260.039580] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x050007fd) [ 260.063345] [drm:intel_update_cdclk] Current CD clock rate: 320000 kHz [ 260.063404] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x150607fd) [ 260.161783] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 260.161809] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 260.520678] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 260.520701] [drm:wait_panel_status] Wait complete [ 260.520722] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 260.520738] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled [ 260.555602] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00100000, dig 0x00100000, pins 0x00000040 [ 260.555628] [drm:intel_hpd_irq_handler] digital hpd port C - long [ 260.555643] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 6 - cnt: 1 [ 260.555783] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C [ 260.724663] [drm:edp_panel_on] Turn eDP port C panel power on [ 260.724689] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 260.724711] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 260.724723] [drm:wait_panel_status] Wait complete [ 260.724738] [drm:wait_panel_on] Wait for panel power on [ 260.724753] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b [ 260.861255] [drm:wait_panel_status] Wait complete [ 260.861285] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 260.861309] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 260.861342] [drm:edp_panel_vdd_on] Turning eDP port C VDD on [ 260.861362] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 260.862069] [drm:intel_dp_reset_link_train] flt enabled: true [ 260.904429] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 260.904451] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 260.905394] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 260.906621] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 260.906985] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 260.907015] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0 [ 260.907030] [drm:intel_enable_pipe] enabling pipe A [ 260.907069] [drm:intel_edp_backlight_on] [ 260.907082] [drm:intel_panel_enable_backlight] pipe A [ 260.907097] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3000 [ 260.907123] [drm:intel_psr_match_conditions] PSR disable by flag [ 260.907225] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x1d0607fd) [ 261.049368] [drm:intel_dp_reset_link_train] flt enabled: false [ 261.133449] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 261.133472] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 261.134409] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 261.220190] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 261.220213] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 261.307547] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 261.307572] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 261.308987] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 261.309236] [drm:intel_enable_dp] Enabling DP audio on pipe B [ 261.309257] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:45:DP-1], [ENCODER:44:TMDS-44] [ 261.309271] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD [ 261.320725] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 261.320789] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 261.320804] [drm:intel_enable_pipe] enabling pipe B [ 261.320851] [drm:intel_psr_enable] PSR not supported by this panel [ 261.354743] [drm:intel_connector_check_state] [CONNECTOR:45:DP-1] [ 261.354777] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1] [ 261.354794] [drm:check_encoder_state] [ENCODER:39:TMDS-39] [ 261.354810] [drm:check_encoder_state] [ENCODER:44:TMDS-44] [ 261.354820] [drm:check_encoder_state] [ENCODER:46:TMDS-46] [ 261.354831] [drm:check_encoder_state] [ENCODER:52:TMDS-52] [ 261.354842] [drm:check_encoder_state] [ENCODER:54:TMDS-54] [ 261.354856] [drm:check_crtc_state] [CRTC:26] [ 261.368446] [drm:check_crtc_state] [CRTC:31] [ 261.574226] [drm:drm_mode_getconnector] [CONNECTOR:55:?] [ 261.574235] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] [ 261.574238] [drm:intel_dp_detect] [CONNECTOR:55:DP-2] [ 261.574244] [drm:intel_power_well_enable] enabling dpio-common-d [ 261.590319] [drm:chv_dpio_cmn_power_well_enable] Enabled DPIO PHY1 (PHY_CONTROL=0x1d0607ff) [ 261.598329] [drm:intel_power_well_disable] disabling dpio-common-d [ 261.606364] [drm:chv_dpio_cmn_power_well_disable] Disabled DPIO PHY1 (PHY_CONTROL=0x1d0607fd) [ 261.614349] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] disconnected [ 261.614395] [drm:drm_mode_getconnector] [CONNECTOR:40:?] [ 261.614399] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] [ 261.614402] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1] [ 261.614833] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 261.614836] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 261.615076] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 261.615080] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 261.615082] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:HDMI-A-1] disconnected [ 261.615092] [drm:drm_mode_getconnector] [CONNECTOR:53:?] [ 261.615096] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] [ 261.615098] [drm:intel_hdmi_detect] [CONNECTOR:53:HDMI-A-2] [ 261.740314] [drm:intel_hdmi_detect] Live status not up! [ 261.740325] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:HDMI-A-2] disconnected [ 261.845199] [drm:internal_framebuffer_create] could not create framebuffer [ 262.714569] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 262.714599] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 262.714632] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 262.714641] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=271, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 262.721631] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 262.721642] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 262.721674] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 262.721694] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 263.912331] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off [ 263.912343] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007 [ 264.755905] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 264.755947] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0 [ 264.756126] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 264.756201] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 264.763190] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 264.763278] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [ 264.763432] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511 [ 264.763461] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=271, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0