From 7ca055a3491198a89dd6714ac6ab9195896a86b8 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Mon, 4 Apr 2016 10:59:40 -0700 Subject: [PATCH] Revert "drm/i915: PSR: Let's rely more on frontbuffer tracking." This reverts commit 921ec285a6589cf3beb7f56a70744f75b09349f8. Apparently it wasn't a good idea to duplicate and let both HW and SW handling psr Exits. This caused flickers in certain platforms in certain conditions. Reference: https://bugs.freedesktop.org/show_bug.cgi?id=94593 Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_psr.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 38e9518..72e51c2 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -754,9 +754,25 @@ void intel_psr_flush(struct drm_device *dev, frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; - /* By definition flush = invalidate + flush */ - if (frontbuffer_bits) - intel_psr_exit(dev); + if (HAS_DDI(dev)) { + /* + * By definition every flush should mean invalidate + flush, + * however on core platforms let's minimize the + * disable/re-enable so we can avoid the invalidate when flip + * originated the flush. + */ + if (frontbuffer_bits && origin != ORIGIN_FLIP) + intel_psr_exit(dev); + } else { + /* + * On Valleyview and Cherryview we don't use hardware tracking + * so any plane updates or cursor moves don't result in a PSR + * invalidating. Which means we need to manually fake this in + * software for all flushes. + */ + if (frontbuffer_bits) + intel_psr_exit(dev); + } if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) if (!work_busy(&dev_priv->psr.work.work)) -- 2.4.3