COMP PROPERTY CS_FIXED_BLOCK_WIDTH 1024 PROPERTY CS_FIXED_BLOCK_HEIGHT 1 PROPERTY CS_FIXED_BLOCK_DEPTH 1 DCL SV[0], THREAD_ID DCL SV[1], BLOCK_ID DCL BUFFER[16] DCL BUFFER[17] DCL BUFFER[18] DCL BUFFER[19] DCL CONST[0..5] DCL TEMP[0..260], LOCAL IMM[0] UINT32 {1024, 1, 16, 0} IMM[1] FLT32 { 0.0000, 0.0100, 1.0000, 0.2000} IMM[2] FLT32 { 1.5708, -0.0236, 0.0813, -0.2146} IMM[3] FLT32 { 0.0000, -0.2000, 10.0000, 2.0000} IMM[4] INT32 {1, 0, 4, 2} IMM[5] FLT32 { 0.3500, 0.0000, 0.0000, 0.0000} IMM[6] INT32 {-1, 0, 0, 0} 0: UMAD TEMP[0].xyz, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz 1: MOV TEMP[1].x, TEMP[0].xxxx 2: MOV TEMP[1].x, TEMP[0].xxxx 3: MOD TEMP[2].x, TEMP[0].xxxx, CONST[0].xxxx 4: IDIV TEMP[3].x, TEMP[0].xxxx, CONST[0].xxxx 5: MOV TEMP[4], IMM[1].xxxx 6: UMUL TEMP[5].x, TEMP[0].xxxx, IMM[0].zzzz 7: LOAD TEMP[5], BUFFER[18], TEMP[5].xxxx 8: ADD TEMP[5], TEMP[5], -CONST[4] 9: DP4 TEMP[6].x, TEMP[5], TEMP[5] 10: SQRT TEMP[6].x, TEMP[6].xxxx 11: ADD TEMP[7].x, CONST[5].xxxx, IMM[1].yyyy 12: FSGE TEMP[6].x, TEMP[7].xxxx, TEMP[6].xxxx 13: UIF TEMP[6].xxxx :0 14: MOV TEMP[6].xyz, IMM[1].xxxx 15: DP4 TEMP[7].x, TEMP[5], TEMP[5] 16: RSQ TEMP[7].x, TEMP[7].xxxx 17: MUL TEMP[5], TEMP[5], TEMP[7].xxxx 18: DP3 TEMP[7].x, TEMP[5].xyzz, IMM[1].xzxx 19: MAX TEMP[7].x, TEMP[7].xxxx, IMM[1].xxxx 20: FSNE TEMP[8].x, TEMP[7].xxxx, IMM[1].zzzz 21: UIF TEMP[8].xxxx :0 22: DP3 TEMP[8].x, TEMP[5].xyzz, TEMP[5].xyzz 23: FSEQ TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx 24: UIF TEMP[9].xxxx :0 25: MOV TEMP[9].xyz, IMM[1].xxxx 26: ELSE :0 27: DP3 TEMP[10].x, IMM[1].xzxx, TEMP[5].xyzz 28: RCP TEMP[8].x, TEMP[8].xxxx 29: MUL TEMP[8].x, TEMP[10].xxxx, TEMP[8].xxxx 30: MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[8].xxxx 31: ADD TEMP[9].xyz, IMM[1].xzxx, -TEMP[5].xyzz 32: ENDIF 33: DP3 TEMP[5].x, TEMP[9].xyzz, TEMP[9].xyzz 34: RSQ TEMP[5].x, TEMP[5].xxxx 35: MUL TEMP[6].xyz, TEMP[9].xyzz, TEMP[5].xxxx 36: ENDIF 37: MOV TEMP[5].w, IMM[1].xxxx 38: MOV TEMP[5].xyz, -TEMP[6].xyzx 39: MOV TEMP[8].w, IMM[1].xxxx 40: MOV TEMP[8].xyz, -TEMP[6].xyzx 41: SSG TEMP[6].x, TEMP[7].xxxx 42: ABS TEMP[9].x, TEMP[7].xxxx 43: ADD TEMP[9].x, IMM[1].zzzz, -TEMP[9].xxxx 44: SQRT TEMP[9].x, TEMP[9].xxxx 45: ABS TEMP[10].x, TEMP[7].xxxx 46: ABS TEMP[11].x, TEMP[7].xxxx 47: ABS TEMP[12].x, TEMP[7].xxxx 48: MAD TEMP[12].x, TEMP[12].xxxx, IMM[2].yyyy, IMM[2].zzzz 49: MAD TEMP[11].x, TEMP[11].xxxx, TEMP[12].xxxx, IMM[2].wwww 50: MAD TEMP[10].x, TEMP[10].xxxx, TEMP[11].xxxx, IMM[2].xxxx 51: MUL TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx 52: ADD TEMP[9].x, IMM[2].xxxx, -TEMP[9].xxxx 53: MUL TEMP[6].x, TEMP[6].xxxx, TEMP[9].xxxx 54: ADD TEMP[6].x, IMM[2].xxxx, -TEMP[6].xxxx 55: SIN TEMP[6].x, TEMP[6].xxxx 56: MUL TEMP[6].x, IMM[1].wwww, TEMP[6].xxxx 57: MUL TEMP[7].x, IMM[1].wwww, TEMP[7].xxxx 58: MUL TEMP[7], TEMP[7].xxxx, TEMP[8] 59: MAD TEMP[4], TEMP[6].xxxx, TEMP[5], -TEMP[7] 60: ELSE :0 61: ADD TEMP[4], TEMP[4], IMM[3].xyxx 62: ENDIF 63: UMUL TEMP[5].x, TEMP[0].xxxx, IMM[0].zzzz 64: UMUL TEMP[6].x, TEMP[0].xxxx, IMM[0].zzzz 65: LOAD TEMP[6], BUFFER[18], TEMP[6].xxxx 66: MOV TEMP[7], TEMP[6] 67: UMUL TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz 68: LOAD TEMP[0], BUFFER[16], TEMP[0].xxxx 69: MUL TEMP[4], TEMP[4], IMM[3].zzzz 70: MUL TEMP[7].x, CONST[1].xxxx, CONST[1].xxxx 71: MAD TEMP[0], IMM[3].wwww, TEMP[6], -TEMP[0] 72: MAD TEMP[0], TEMP[4], TEMP[7].xxxx, TEMP[0] 73: STORE BUFFER[19], TEMP[5].xxxx, TEMP[0] 74: MEMBAR IMM[4].xxxx 75: BARRIER 76: MOV TEMP[0].x, IMM[4].yyyy 77: BGNLOOP :0 78: ISGE TEMP[4].x, TEMP[0].xxxx, IMM[4].zzzz 79: UIF TEMP[4].xxxx :0 80: BRK 81: ENDIF 82: MOV TEMP[5].x, IMM[4].yyyy 83: BGNLOOP :0 84: ISGE TEMP[6].x, TEMP[5].xxxx, IMM[4].wwww 85: UIF TEMP[6].xxxx :0 86: BRK 87: ENDIF 88: MOD TEMP[7].x, TEMP[3].xxxx, IMM[4].wwww 89: USEQ TEMP[8].x, TEMP[7].xxxx, TEMP[5].xxxx 90: MOD TEMP[9].x, TEMP[2].xxxx, IMM[4].wwww 91: USEQ TEMP[10].x, TEMP[9].xxxx, TEMP[5].xxxx 92: AND TEMP[11].x, TEMP[8].xxxx, TEMP[10].xxxx 93: UIF TEMP[11].xxxx :0 94: UMUL TEMP[12].x, TEMP[1].xxxx, IMM[0].zzzz 95: LOAD TEMP[13], BUFFER[19], TEMP[12].xxxx 96: MOV TEMP[14], TEMP[13] 97: MOV TEMP[15], TEMP[13] 98: UADD TEMP[16].x, TEMP[1].xxxx, IMM[4].xxxx 99: MOD TEMP[17].x, TEMP[16].xxxx, CONST[0].xxxx 100: ISLT TEMP[18].x, TEMP[2].xxxx, TEMP[17].xxxx 101: UIF TEMP[18].xxxx :0 102: UMUL TEMP[19].x, TEMP[16].xxxx, IMM[0].zzzz 103: LOAD TEMP[20], BUFFER[19], TEMP[19].xxxx 104: MOV TEMP[21], TEMP[20] 105: ADD TEMP[22], TEMP[13], -TEMP[20] 106: DP4 TEMP[23].x, TEMP[22], TEMP[22] 107: SQRT TEMP[24].x, TEMP[23].xxxx 108: ADD TEMP[25].x, CONST[2].xxxx, -TEMP[24].xxxx 109: MUL TEMP[26].x, IMM[5].xxxx, TEMP[25].xxxx 110: RCP TEMP[27].x, TEMP[24].xxxx 111: MUL TEMP[28].x, TEMP[26].xxxx, TEMP[27].xxxx 112: MUL TEMP[29], TEMP[28].xxxx, TEMP[22] 113: UMUL TEMP[30].x, TEMP[1].xxxx, IMM[0].zzzz 114: UMUL TEMP[31].x, TEMP[1].xxxx, IMM[0].zzzz 115: LOAD TEMP[32], BUFFER[19], TEMP[31].xxxx 116: ADD TEMP[33], TEMP[32], TEMP[29] 117: STORE BUFFER[19], TEMP[30].xxxx, TEMP[33] 118: UMUL TEMP[34].x, TEMP[16].xxxx, IMM[0].zzzz 119: UMUL TEMP[35].x, TEMP[16].xxxx, IMM[0].zzzz 120: LOAD TEMP[36], BUFFER[19], TEMP[35].xxxx 121: ADD TEMP[37], TEMP[36], -TEMP[29] 122: STORE BUFFER[19], TEMP[34].xxxx, TEMP[37] 123: MEMBAR IMM[4].xxxx 124: ENDIF 125: UADD TEMP[38].x, TEMP[1].xxxx, CONST[0].xxxx 126: UMUL TEMP[39].x, CONST[0].xxxx, CONST[0].xxxx 127: ISLT TEMP[40].x, TEMP[38].xxxx, TEMP[39].xxxx 128: UIF TEMP[40].xxxx :0 129: UMUL TEMP[41].x, TEMP[38].xxxx, IMM[0].zzzz 130: LOAD TEMP[42], BUFFER[19], TEMP[41].xxxx 131: MOV TEMP[43], TEMP[42] 132: ADD TEMP[44], TEMP[13], -TEMP[42] 133: DP4 TEMP[45].x, TEMP[44], TEMP[44] 134: SQRT TEMP[46].x, TEMP[45].xxxx 135: ADD TEMP[47].x, CONST[2].xxxx, -TEMP[46].xxxx 136: MUL TEMP[48].x, IMM[5].xxxx, TEMP[47].xxxx 137: RCP TEMP[49].x, TEMP[46].xxxx 138: MUL TEMP[50].x, TEMP[48].xxxx, TEMP[49].xxxx 139: MUL TEMP[51], TEMP[50].xxxx, TEMP[44] 140: UMUL TEMP[52].x, TEMP[1].xxxx, IMM[0].zzzz 141: UMUL TEMP[53].x, TEMP[1].xxxx, IMM[0].zzzz 142: LOAD TEMP[54], BUFFER[19], TEMP[53].xxxx 143: ADD TEMP[55], TEMP[54], TEMP[51] 144: STORE BUFFER[19], TEMP[52].xxxx, TEMP[55] 145: UMUL TEMP[56].x, TEMP[38].xxxx, IMM[0].zzzz 146: UMUL TEMP[57].x, TEMP[38].xxxx, IMM[0].zzzz 147: LOAD TEMP[58], BUFFER[19], TEMP[57].xxxx 148: ADD TEMP[59], TEMP[58], -TEMP[51] 149: STORE BUFFER[19], TEMP[56].xxxx, TEMP[59] 150: MEMBAR IMM[4].xxxx 151: ENDIF 152: UADD TEMP[60].x, TEMP[1].xxxx, IMM[4].xxxx 153: UADD TEMP[61].x, TEMP[60].xxxx, CONST[0].xxxx 154: UMUL TEMP[62].x, CONST[0].xxxx, CONST[0].xxxx 155: ISLT TEMP[63].x, TEMP[61].xxxx, TEMP[62].xxxx 156: MOD TEMP[64].x, TEMP[61].xxxx, CONST[0].xxxx 157: ISLT TEMP[65].x, TEMP[2].xxxx, TEMP[64].xxxx 158: AND TEMP[66].x, TEMP[63].xxxx, TEMP[65].xxxx 159: UIF TEMP[66].xxxx :0 160: UMUL TEMP[67].x, TEMP[61].xxxx, IMM[0].zzzz 161: LOAD TEMP[68], BUFFER[19], TEMP[67].xxxx 162: MOV TEMP[69], TEMP[68] 163: ADD TEMP[70], TEMP[21], -TEMP[68] 164: DP4 TEMP[71].x, TEMP[70], TEMP[70] 165: SQRT TEMP[72].x, TEMP[71].xxxx 166: ADD TEMP[73].x, CONST[2].xxxx, -TEMP[72].xxxx 167: MUL TEMP[74].x, IMM[5].xxxx, TEMP[73].xxxx 168: RCP TEMP[75].x, TEMP[72].xxxx 169: MUL TEMP[76].x, TEMP[74].xxxx, TEMP[75].xxxx 170: MUL TEMP[77], TEMP[76].xxxx, TEMP[70] 171: UMUL TEMP[78].x, TEMP[16].xxxx, IMM[0].zzzz 172: UMUL TEMP[79].x, TEMP[16].xxxx, IMM[0].zzzz 173: LOAD TEMP[80], BUFFER[19], TEMP[79].xxxx 174: ADD TEMP[81], TEMP[80], TEMP[77] 175: STORE BUFFER[19], TEMP[78].xxxx, TEMP[81] 176: UMUL TEMP[82].x, TEMP[61].xxxx, IMM[0].zzzz 177: UMUL TEMP[83].x, TEMP[61].xxxx, IMM[0].zzzz 178: LOAD TEMP[84], BUFFER[19], TEMP[83].xxxx 179: ADD TEMP[85], TEMP[84], -TEMP[77] 180: STORE BUFFER[19], TEMP[82].xxxx, TEMP[85] 181: MEMBAR IMM[4].xxxx 182: ADD TEMP[86], TEMP[43], -TEMP[68] 183: DP4 TEMP[87].x, TEMP[86], TEMP[86] 184: SQRT TEMP[88].x, TEMP[87].xxxx 185: ADD TEMP[89].x, CONST[2].xxxx, -TEMP[88].xxxx 186: MUL TEMP[90].x, IMM[5].xxxx, TEMP[89].xxxx 187: RCP TEMP[91].x, TEMP[88].xxxx 188: MUL TEMP[92].x, TEMP[90].xxxx, TEMP[91].xxxx 189: MUL TEMP[93], TEMP[92].xxxx, TEMP[86] 190: UMUL TEMP[94].x, TEMP[38].xxxx, IMM[0].zzzz 191: UMUL TEMP[95].x, TEMP[38].xxxx, IMM[0].zzzz 192: LOAD TEMP[96], BUFFER[19], TEMP[95].xxxx 193: ADD TEMP[97], TEMP[96], TEMP[93] 194: STORE BUFFER[19], TEMP[94].xxxx, TEMP[97] 195: UMUL TEMP[98].x, TEMP[61].xxxx, IMM[0].zzzz 196: UMUL TEMP[99].x, TEMP[61].xxxx, IMM[0].zzzz 197: LOAD TEMP[100], BUFFER[19], TEMP[99].xxxx 198: ADD TEMP[14], TEMP[100], -TEMP[93] 199: STORE BUFFER[19], TEMP[98].xxxx, TEMP[14] 200: MEMBAR IMM[4].xxxx 201: ADD TEMP[15], TEMP[13], -TEMP[68] 202: DP4 TEMP[101].x, TEMP[15], TEMP[15] 203: SQRT TEMP[102].x, TEMP[101].xxxx 204: ADD TEMP[103].x, CONST[3].xxxx, -TEMP[102].xxxx 205: MUL TEMP[104].x, IMM[5].xxxx, TEMP[103].xxxx 206: RCP TEMP[105].x, TEMP[102].xxxx 207: MUL TEMP[106].x, TEMP[104].xxxx, TEMP[105].xxxx 208: MUL TEMP[107], TEMP[106].xxxx, TEMP[15] 209: UMUL TEMP[108].x, TEMP[1].xxxx, IMM[0].zzzz 210: UMUL TEMP[109].x, TEMP[1].xxxx, IMM[0].zzzz 211: LOAD TEMP[110], BUFFER[19], TEMP[109].xxxx 212: ADD TEMP[111], TEMP[110], TEMP[107] 213: STORE BUFFER[19], TEMP[108].xxxx, TEMP[111] 214: UMUL TEMP[112].x, TEMP[61].xxxx, IMM[0].zzzz 215: UMUL TEMP[113].x, TEMP[61].xxxx, IMM[0].zzzz 216: LOAD TEMP[114], BUFFER[19], TEMP[113].xxxx 217: ADD TEMP[115], TEMP[114], -TEMP[107] 218: STORE BUFFER[19], TEMP[112].xxxx, TEMP[115] 219: ADD TEMP[116], TEMP[21], -TEMP[43] 220: DP4 TEMP[117].x, TEMP[116], TEMP[116] 221: SQRT TEMP[118].x, TEMP[117].xxxx 222: ADD TEMP[119].x, CONST[3].xxxx, -TEMP[118].xxxx 223: MUL TEMP[120].x, IMM[5].xxxx, TEMP[119].xxxx 224: RCP TEMP[121].x, TEMP[118].xxxx 225: MUL TEMP[122].x, TEMP[120].xxxx, TEMP[121].xxxx 226: MUL TEMP[123], TEMP[122].xxxx, TEMP[116] 227: UMUL TEMP[124].x, TEMP[16].xxxx, IMM[0].zzzz 228: UMUL TEMP[125].x, TEMP[16].xxxx, IMM[0].zzzz 229: LOAD TEMP[126], BUFFER[19], TEMP[125].xxxx 230: ADD TEMP[127], TEMP[126], TEMP[123] 231: STORE BUFFER[19], TEMP[124].xxxx, TEMP[127] 232: UMUL TEMP[128].x, TEMP[38].xxxx, IMM[0].zzzz 233: UMUL TEMP[129].x, TEMP[38].xxxx, IMM[0].zzzz 234: LOAD TEMP[130], BUFFER[19], TEMP[129].xxxx 235: ADD TEMP[131], TEMP[130], -TEMP[123] 236: STORE BUFFER[19], TEMP[128].xxxx, TEMP[131] 237: MEMBAR IMM[4].xxxx 238: ENDIF 239: ELSE :0 240: USEQ TEMP[132].x, TEMP[5].xxxx, IMM[4].xxxx 241: MOD TEMP[133].x, TEMP[2].xxxx, IMM[4].wwww 242: USEQ TEMP[134].x, TEMP[133].xxxx, IMM[4].xxxx 243: AND TEMP[135].x, TEMP[132].xxxx, TEMP[134].xxxx 244: USEQ TEMP[136].x, TEMP[3].xxxx, IMM[4].yyyy 245: AND TEMP[137].x, TEMP[135].xxxx, TEMP[136].xxxx 246: UIF TEMP[137].xxxx :0 247: UADD TEMP[16].x, TEMP[1].xxxx, IMM[4].xxxx 248: ISLT TEMP[138].x, TEMP[16].xxxx, CONST[0].xxxx 249: UIF TEMP[138].xxxx :0 250: UMUL TEMP[139].x, TEMP[1].xxxx, IMM[0].zzzz 251: LOAD TEMP[140], BUFFER[19], TEMP[139].xxxx 252: MOV TEMP[141], TEMP[140] 253: UMUL TEMP[142].x, TEMP[16].xxxx, IMM[0].zzzz 254: LOAD TEMP[143], BUFFER[19], TEMP[142].xxxx 255: ADD TEMP[144], TEMP[140], -TEMP[143] 256: DP4 TEMP[145].x, TEMP[144], TEMP[144] 257: SQRT TEMP[146].x, TEMP[145].xxxx 258: ADD TEMP[147].x, CONST[2].xxxx, -TEMP[146].xxxx 259: MUL TEMP[148].x, IMM[5].xxxx, TEMP[147].xxxx 260: RCP TEMP[149].x, TEMP[146].xxxx 261: MUL TEMP[150].x, TEMP[148].xxxx, TEMP[149].xxxx 262: MUL TEMP[151], TEMP[150].xxxx, TEMP[144] 263: UMUL TEMP[152].x, TEMP[1].xxxx, IMM[0].zzzz 264: UMUL TEMP[153].x, TEMP[1].xxxx, IMM[0].zzzz 265: LOAD TEMP[154], BUFFER[19], TEMP[153].xxxx 266: ADD TEMP[155], TEMP[154], TEMP[151] 267: STORE BUFFER[19], TEMP[152].xxxx, TEMP[155] 268: UMUL TEMP[156].x, TEMP[16].xxxx, IMM[0].zzzz 269: UMUL TEMP[157].x, TEMP[16].xxxx, IMM[0].zzzz 270: LOAD TEMP[158], BUFFER[19], TEMP[157].xxxx 271: ADD TEMP[159], TEMP[158], -TEMP[151] 272: STORE BUFFER[19], TEMP[156].xxxx, TEMP[159] 273: MEMBAR IMM[4].xxxx 274: ENDIF 275: ELSE :0 276: USEQ TEMP[160].x, TEMP[5].xxxx, IMM[4].xxxx 277: MOD TEMP[161].x, TEMP[3].xxxx, IMM[4].wwww 278: USEQ TEMP[162].x, TEMP[161].xxxx, IMM[4].xxxx 279: AND TEMP[163].x, TEMP[160].xxxx, TEMP[162].xxxx 280: USEQ TEMP[164].x, TEMP[2].xxxx, IMM[4].yyyy 281: AND TEMP[165].x, TEMP[163].xxxx, TEMP[164].xxxx 282: UIF TEMP[165].xxxx :0 283: UADD TEMP[38].x, TEMP[1].xxxx, CONST[0].xxxx 284: UMUL TEMP[166].x, CONST[0].xxxx, CONST[0].xxxx 285: ISLT TEMP[167].x, TEMP[38].xxxx, TEMP[166].xxxx 286: UIF TEMP[167].xxxx :0 287: UMUL TEMP[168].x, TEMP[1].xxxx, IMM[0].zzzz 288: LOAD TEMP[169], BUFFER[19], TEMP[168].xxxx 289: MOV TEMP[170], TEMP[169] 290: UMUL TEMP[171].x, TEMP[38].xxxx, IMM[0].zzzz 291: LOAD TEMP[172], BUFFER[19], TEMP[171].xxxx 292: ADD TEMP[173], TEMP[169], -TEMP[172] 293: DP4 TEMP[174].x, TEMP[173], TEMP[173] 294: SQRT TEMP[175].x, TEMP[174].xxxx 295: ADD TEMP[176].x, CONST[2].xxxx, -TEMP[175].xxxx 296: MUL TEMP[177].x, IMM[5].xxxx, TEMP[176].xxxx 297: RCP TEMP[178].x, TEMP[175].xxxx 298: MUL TEMP[179].x, TEMP[177].xxxx, TEMP[178].xxxx 299: MUL TEMP[180], TEMP[179].xxxx, TEMP[173] 300: UMUL TEMP[181].x, TEMP[1].xxxx, IMM[0].zzzz 301: UMUL TEMP[182].x, TEMP[1].xxxx, IMM[0].zzzz 302: LOAD TEMP[183], BUFFER[19], TEMP[182].xxxx 303: ADD TEMP[184], TEMP[183], TEMP[180] 304: STORE BUFFER[19], TEMP[181].xxxx, TEMP[184] 305: UMUL TEMP[185].x, TEMP[38].xxxx, IMM[0].zzzz 306: UMUL TEMP[69].x, TEMP[38].xxxx, IMM[0].zzzz 307: LOAD TEMP[186], BUFFER[19], TEMP[69].xxxx 308: ADD TEMP[187], TEMP[186], -TEMP[180] 309: STORE BUFFER[19], TEMP[185].xxxx, TEMP[187] 310: MEMBAR IMM[4].xxxx 311: ENDIF 312: ENDIF 313: ENDIF 314: ENDIF 315: BARRIER 316: UADD TEMP[5].x, TEMP[5].xxxx, IMM[4].xxxx 317: ENDLOOP :0 318: MOV TEMP[188].x, IMM[4].yyyy 319: BGNLOOP :0 320: ISGE TEMP[189].x, TEMP[188].xxxx, IMM[4].wwww 321: UIF TEMP[189].xxxx :0 322: BRK 323: ENDIF 324: MOD TEMP[190].x, TEMP[3].xxxx, IMM[4].wwww 325: USEQ TEMP[191].x, TEMP[190].xxxx, TEMP[188].xxxx 326: UADD TEMP[192].x, TEMP[2].xxxx, IMM[4].xxxx 327: MOD TEMP[193].x, TEMP[192].xxxx, IMM[4].wwww 328: USEQ TEMP[194].x, TEMP[193].xxxx, TEMP[188].xxxx 329: AND TEMP[195].x, TEMP[191].xxxx, TEMP[194].xxxx 330: UIF TEMP[195].xxxx :0 331: UMUL TEMP[196].x, TEMP[1].xxxx, IMM[0].zzzz 332: LOAD TEMP[197], BUFFER[19], TEMP[196].xxxx 333: MOV TEMP[198], TEMP[197] 334: UADD TEMP[199].x, TEMP[1].xxxx, IMM[4].xxxx 335: UADD TEMP[200].x, TEMP[1].xxxx, CONST[0].xxxx 336: UADD TEMP[201].x, TEMP[1].xxxx, IMM[4].xxxx 337: UADD TEMP[202].x, TEMP[201].xxxx, CONST[0].xxxx 338: UMUL TEMP[203].x, CONST[0].xxxx, CONST[0].xxxx 339: ISLT TEMP[204].x, TEMP[202].xxxx, TEMP[203].xxxx 340: MOD TEMP[205].x, TEMP[202].xxxx, CONST[0].xxxx 341: ISLT TEMP[206].x, TEMP[2].xxxx, TEMP[205].xxxx 342: AND TEMP[207].x, TEMP[204].xxxx, TEMP[206].xxxx 343: UIF TEMP[207].xxxx :0 344: UMUL TEMP[208].x, TEMP[199].xxxx, IMM[0].zzzz 345: LOAD TEMP[209], BUFFER[19], TEMP[208].xxxx 346: MOV TEMP[210], TEMP[209] 347: UMUL TEMP[211].x, TEMP[200].xxxx, IMM[0].zzzz 348: LOAD TEMP[212], BUFFER[19], TEMP[211].xxxx 349: MOV TEMP[213], TEMP[212] 350: UMUL TEMP[214].x, TEMP[202].xxxx, IMM[0].zzzz 351: LOAD TEMP[215], BUFFER[19], TEMP[214].xxxx 352: ADD TEMP[216], TEMP[197], -TEMP[215] 353: DP4 TEMP[217].x, TEMP[216], TEMP[216] 354: SQRT TEMP[218].x, TEMP[217].xxxx 355: ADD TEMP[219].x, CONST[3].xxxx, -TEMP[218].xxxx 356: MUL TEMP[220].x, IMM[5].xxxx, TEMP[219].xxxx 357: RCP TEMP[221].x, TEMP[218].xxxx 358: MUL TEMP[222].x, TEMP[220].xxxx, TEMP[221].xxxx 359: MUL TEMP[223], TEMP[222].xxxx, TEMP[216] 360: UMUL TEMP[224].x, TEMP[1].xxxx, IMM[0].zzzz 361: UMUL TEMP[225].x, TEMP[1].xxxx, IMM[0].zzzz 362: LOAD TEMP[226], BUFFER[19], TEMP[225].xxxx 363: ADD TEMP[227], TEMP[226], TEMP[223] 364: STORE BUFFER[19], TEMP[224].xxxx, TEMP[227] 365: UMUL TEMP[228].x, TEMP[202].xxxx, IMM[0].zzzz 366: UMUL TEMP[229].x, TEMP[202].xxxx, IMM[0].zzzz 367: LOAD TEMP[230], BUFFER[19], TEMP[229].xxxx 368: ADD TEMP[231], TEMP[230], -TEMP[223] 369: STORE BUFFER[19], TEMP[228].xxxx, TEMP[231] 370: ADD TEMP[232], TEMP[209], -TEMP[212] 371: DP4 TEMP[233].x, TEMP[232], TEMP[232] 372: SQRT TEMP[234].x, TEMP[233].xxxx 373: ADD TEMP[235].x, CONST[3].xxxx, -TEMP[234].xxxx 374: MUL TEMP[236].x, IMM[5].xxxx, TEMP[235].xxxx 375: RCP TEMP[237].x, TEMP[234].xxxx 376: MUL TEMP[238].x, TEMP[236].xxxx, TEMP[237].xxxx 377: MUL TEMP[239], TEMP[238].xxxx, TEMP[232] 378: UMUL TEMP[240].x, TEMP[199].xxxx, IMM[0].zzzz 379: UMUL TEMP[241].x, TEMP[199].xxxx, IMM[0].zzzz 380: LOAD TEMP[242], BUFFER[19], TEMP[241].xxxx 381: ADD TEMP[243], TEMP[242], TEMP[239] 382: STORE BUFFER[19], TEMP[240].xxxx, TEMP[243] 383: UMUL TEMP[244].x, TEMP[200].xxxx, IMM[0].zzzz 384: UMUL TEMP[245].x, TEMP[200].xxxx, IMM[0].zzzz 385: LOAD TEMP[246], BUFFER[19], TEMP[245].xxxx 386: ADD TEMP[247], TEMP[246], -TEMP[239] 387: STORE BUFFER[19], TEMP[244].xxxx, TEMP[247] 388: MEMBAR IMM[4].xxxx 389: ENDIF 390: ENDIF 391: BARRIER 392: UADD TEMP[188].x, TEMP[188].xxxx, IMM[4].xxxx 393: ENDLOOP :0 394: UMUL TEMP[248].x, TEMP[1].xxxx, IMM[0].zzzz 395: LOAD TEMP[249], BUFFER[19], TEMP[248].xxxx 396: ADD TEMP[250], TEMP[249], -CONST[4] 397: DP4 TEMP[251].x, TEMP[250], TEMP[250] 398: SQRT TEMP[252].x, TEMP[251].xxxx 399: ADD TEMP[253].x, CONST[5].xxxx, IMM[1].yyyy 400: FSLT TEMP[254].x, TEMP[252].xxxx, TEMP[253].xxxx 401: UIF TEMP[254].xxxx :0 402: UMUL TEMP[255].x, TEMP[1].xxxx, IMM[0].zzzz 403: DP4 TEMP[256].x, TEMP[250], TEMP[250] 404: RSQ TEMP[257].x, TEMP[256].xxxx 405: MUL TEMP[258], TEMP[250], TEMP[257].xxxx 406: ADD TEMP[259].x, CONST[5].xxxx, IMM[1].yyyy 407: MAD TEMP[260], TEMP[258], TEMP[259].xxxx, CONST[4] 408: STORE BUFFER[19], TEMP[255].xxxx, TEMP[260] 409: MEMBAR IMM[4].xxxx 410: ENDIF 411: BARRIER 412: UADD TEMP[0].x, TEMP[0].xxxx, IMM[4].xxxx 413: ENDLOOP :0 414: MOV TEMP[0].xyz, IMM[1].xxxx 415: UADD TEMP[4].x, CONST[0].xxxx, IMM[6].xxxx 416: ISLT TEMP[4].x, TEMP[2].xxxx, TEMP[4].xxxx 417: UIF TEMP[4].xxxx :0 418: UADD TEMP[4].x, TEMP[1].xxxx, IMM[4].xxxx 419: UMUL TEMP[4].x, TEMP[4].xxxx, IMM[0].zzzz 420: LOAD TEMP[4], BUFFER[19], TEMP[4].xxxx 421: UMUL TEMP[5].x, TEMP[1].xxxx, IMM[0].zzzz 422: LOAD TEMP[5], BUFFER[19], TEMP[5].xxxx 423: ADD TEMP[4].xyz, TEMP[4], -TEMP[5] 424: DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz 425: RSQ TEMP[5].x, TEMP[5].xxxx 426: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xxxx 427: UADD TEMP[5].x, CONST[0].xxxx, IMM[6].xxxx 428: ISLT TEMP[5].x, TEMP[3].xxxx, TEMP[5].xxxx 429: UIF TEMP[5].xxxx :0 430: UADD TEMP[5].x, TEMP[1].xxxx, CONST[0].xxxx 431: UMUL TEMP[5].x, TEMP[5].xxxx, IMM[0].zzzz 432: LOAD TEMP[5], BUFFER[19], TEMP[5].xxxx 433: UMUL TEMP[6].x, TEMP[1].xxxx, IMM[0].zzzz 434: LOAD TEMP[6], BUFFER[19], TEMP[6].xxxx 435: ADD TEMP[5].xyz, TEMP[5], -TEMP[6] 436: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz 437: RSQ TEMP[6].x, TEMP[6].xxxx 438: MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xxxx 439: MUL TEMP[6].xyz, TEMP[5].zxyy, TEMP[4].yzxx 440: MAD TEMP[5].xyz, TEMP[5].yzxx, TEMP[4].zxyy, -TEMP[6].xyzz 441: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz 442: RSQ TEMP[6].x, TEMP[6].xxxx 443: MUL TEMP[0].xyz, TEMP[5].xyzz, TEMP[6].xxxx 444: ENDIF 445: ISLT TEMP[5].x, IMM[4].yyyy, TEMP[3].xxxx 446: UIF TEMP[5].xxxx :0 447: UMUL TEMP[5].x, TEMP[1].xxxx, IMM[0].zzzz 448: LOAD TEMP[5], BUFFER[19], TEMP[5].xxxx 449: INEG TEMP[6].x, CONST[0].xxxx 450: UADD TEMP[6].x, TEMP[1].xxxx, TEMP[6].xxxx 451: UMUL TEMP[6].x, TEMP[6].xxxx, IMM[0].zzzz 452: LOAD TEMP[6], BUFFER[19], TEMP[6].xxxx 453: ADD TEMP[5].xyz, TEMP[5], -TEMP[6] 454: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz 455: RSQ TEMP[6].x, TEMP[6].xxxx 456: MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xxxx 457: MUL TEMP[6].xyz, TEMP[5].zxyy, TEMP[4].yzxx 458: MAD TEMP[4].xyz, TEMP[5].yzxx, TEMP[4].zxyy, -TEMP[6].xyzz 459: DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz 460: RSQ TEMP[5].x, TEMP[5].xxxx 461: MAD TEMP[0].xyz, TEMP[4].xyzz, TEMP[5].xxxx, TEMP[0].xyzz 462: ENDIF 463: ENDIF 464: ISLT TEMP[2].x, IMM[4].yyyy, TEMP[2].xxxx 465: UIF TEMP[2].xxxx :0 466: UMUL TEMP[2].x, TEMP[1].xxxx, IMM[0].zzzz 467: LOAD TEMP[2], BUFFER[19], TEMP[2].xxxx 468: UADD TEMP[4].x, TEMP[1].xxxx, IMM[6].xxxx 469: UMUL TEMP[4].x, TEMP[4].xxxx, IMM[0].zzzz 470: LOAD TEMP[4], BUFFER[19], TEMP[4].xxxx 471: ADD TEMP[2].xyz, TEMP[2], -TEMP[4] 472: DP3 TEMP[4].x, TEMP[2].xyzz, TEMP[2].xyzz 473: RSQ TEMP[4].x, TEMP[4].xxxx 474: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[4].xxxx 475: UADD TEMP[4].x, CONST[0].xxxx, IMM[6].xxxx 476: ISLT TEMP[4].x, TEMP[3].xxxx, TEMP[4].xxxx 477: UIF TEMP[4].xxxx :0 478: UADD TEMP[4].x, TEMP[1].xxxx, CONST[0].xxxx 479: UMUL TEMP[4].x, TEMP[4].xxxx, IMM[0].zzzz 480: LOAD TEMP[4], BUFFER[19], TEMP[4].xxxx 481: UMUL TEMP[5].x, TEMP[1].xxxx, IMM[0].zzzz 482: LOAD TEMP[5], BUFFER[19], TEMP[5].xxxx 483: ADD TEMP[4].xyz, TEMP[4], -TEMP[5] 484: DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz 485: RSQ TEMP[5].x, TEMP[5].xxxx 486: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xxxx 487: MUL TEMP[5].xyz, TEMP[4].zxyy, TEMP[2].yzxx 488: MAD TEMP[4].xyz, TEMP[4].yzxx, TEMP[2].zxyy, -TEMP[5].xyzz 489: DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz 490: RSQ TEMP[5].x, TEMP[5].xxxx 491: MAD TEMP[0].xyz, TEMP[4].xyzz, TEMP[5].xxxx, TEMP[0].xyzz 492: ENDIF 493: ISLT TEMP[3].x, IMM[4].yyyy, TEMP[3].xxxx 494: UIF TEMP[3].xxxx :0 495: UMUL TEMP[3].x, TEMP[1].xxxx, IMM[0].zzzz 496: LOAD TEMP[3], BUFFER[19], TEMP[3].xxxx 497: INEG TEMP[4].x, CONST[0].xxxx 498: UADD TEMP[4].x, TEMP[1].xxxx, TEMP[4].xxxx 499: UMUL TEMP[4].x, TEMP[4].xxxx, IMM[0].zzzz 500: LOAD TEMP[4], BUFFER[19], TEMP[4].xxxx 501: ADD TEMP[3].xyz, TEMP[3], -TEMP[4] 502: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[3].xyzz 503: RSQ TEMP[4].x, TEMP[4].xxxx 504: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx 505: MUL TEMP[4].xyz, TEMP[3].zxyy, TEMP[2].yzxx 506: MAD TEMP[2].xyz, TEMP[3].yzxx, TEMP[2].zxyy, -TEMP[4].xyzz 507: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz 508: RSQ TEMP[3].x, TEMP[3].xxxx 509: MAD TEMP[0].xyz, TEMP[2].xyzz, TEMP[3].xxxx, TEMP[0].xyzz 510: ENDIF 511: ENDIF 512: UMUL TEMP[1].x, TEMP[1].xxxx, IMM[0].zzzz 513: DP3 TEMP[2].x, TEMP[0].xyzz, TEMP[0].xyzz 514: RSQ TEMP[2].x, TEMP[2].xxxx 515: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx 516: STORE BUFFER[17].xyz, TEMP[1].xxxx, TEMP[0].xyzz 517: MEMBAR IMM[4].xxxx 518: END MAIN:-1 () BB:0 (59 instructions) - df = { } -> BB:8 (tree) -> BB:2 (tree) 0: nop u32 %r3135 (0) 1: rdsv u32 %r2700 sv[CTAID:0] (0) 2: mov u32 %r2701 0x00000400 (0) 3: rdsv u32 %r2702 sv[TID:0] (0) 4: mad u32 %r2703 %r2700 %r2701 %r2702 (0) 5: ld u32 %r2714 c0[0x0] (0) 6: mov u32 $r0 %r2703 (0) 7: mov u32 $r1 %r2714 (0) 8: call abs BUILTIN:1 (0) 9: mov u32 %r2715 $r1 (0) 10: nop - { $r0 $r2d } (0) 11: nop - $p0q (0) 12: mov u32 $r0 %r2703 (0) 13: mov u32 $r1 %r2714 (0) 14: call abs BUILTIN:1 (0) 15: mov u32 %r2717 $r0 (0) 16: nop - { $r1 $r2d } (0) 17: nop - $p0q (0) 18: shl u32 %r2727 %r2703 0x00000004 (0) 19: add u64 %r2731d %r2727 c7[0x320] (0) 20: add u32 %r2732 %r2727 0x00000004 (0) 21: set u8 %p2733 gt u32 %r2732 c7[0x328] (0) 22: not %p2733 ld u32 %r2734 g[%r2731d+0x0] (0) 23: %p2733 mov u32 %r2735 0x00000000 (0) 24: union u32 %r2736 %r2734 %r2735 (0) 25: add u32 %r2741 %r2727 0x00000008 (0) 26: set u8 %p2742 gt u32 %r2741 c7[0x328] (0) 27: not %p2742 ld u32 %r2743 g[%r2731d+0x4] (0) 28: %p2742 mov u32 %r2744 0x00000000 (0) 29: union u32 %r2745 %r2743 %r2744 (0) 30: add u32 %r2750 %r2727 0x0000000c (0) 31: set u8 %p2751 gt u32 %r2750 c7[0x328] (0) 32: not %p2751 ld u32 %r2752 g[%r2731d+0x8] (0) 33: %p2751 mov u32 %r2753 0x00000000 (0) 34: union u32 %r2754 %r2752 %r2753 (0) 35: add u32 %r2759 %r2727 0x00000010 (0) 36: set u8 %p2760 gt u32 %r2759 c7[0x328] (0) 37: not %p2760 ld u32 %r2761 g[%r2731d+0xc] (0) 38: %p2760 mov u32 %r2762 0x00000000 (0) 39: union u32 %r2763 %r2761 %r2762 (0) 40: neg f32 %r2769 c0[0x40] (0) 41: add f32 %r2770 %r2736 %r2769 (0) 42: neg f32 %r2772 c0[0x44] (0) 43: add f32 %r2773 %r2745 %r2772 (0) 44: neg f32 %r2775 c0[0x48] (0) 45: add f32 %r2776 %r2754 %r2775 (0) 46: neg f32 %r2778 c0[0x4c] (0) 47: add f32 %r2779 %r2763 %r2778 (0) 48: mul f32 %r2784 %r2770 %r2770 (0) 49: mad f32 %r2785 %r2773 %r2773 %r2784 (0) 50: mad f32 %r2786 %r2776 %r2776 %r2785 (0) 51: mad f32 %r2787 %r2779 %r2779 %r2786 (0) 52: rsq f32 %r2789 %r2787 (0) 53: rcp f32 %r2790 %r2789 (0) 54: ld u32 %r2792 c0[0x50] (0) 55: add f32 %r2794 %r2792 0.010000 (0) 56: joinat BB:9 (0) 57: set u8 %p2797 ge f32 %r2794 %r2790 (0) 58: not %p2797 bra BB:8 (0) BB:2 (14 instructions) - idom = BB:0, df = { BB:9 } -> BB:7 (forward) -> BB:3 (tree) 59: mov u32 %r2798 0x00000000 (0) 60: mul f32 %r2804 %r2770 %r2770 (0) 61: mad f32 %r2805 %r2773 %r2773 %r2804 (0) 62: mad f32 %r2806 %r2776 %r2776 %r2805 (0) 63: mad f32 %r2807 %r2779 %r2779 %r2806 (0) 64: abs f32 %r2809 %r2807 (0) 65: rsq f32 %r2810 %r2809 (0) 66: mul f32 %r2813 %r2770 %r2810 (0) 67: mul f32 %r2814 %r2773 %r2810 (0) 68: mul f32 %r2815 %r2776 %r2810 (0) 69: max f32 %r2829 %r2814 0.000000 (0) 70: joinat BB:7 (0) 71: set u8 %p2833 neu f32 %r2829 1.000000 (0) 72: not %p2833 bra BB:7 (0) BB:3 (6 instructions) - idom = BB:2, df = { BB:7 } -> BB:5 (tree) -> BB:4 (tree) 73: mul f32 %r2834 %r2813 %r2813 (0) 74: mad f32 %r2835 %r2814 %r2814 %r2834 (0) 75: mad f32 %r2836 %r2815 %r2815 %r2835 (0) 76: joinat BB:6 (0) 77: set u8 %p2840 eq f32 %r2836 0.000000 (0) 78: not %p2840 bra BB:5 (0) BB:4 (2 instructions) - idom = BB:3, df = { BB:6 } -> BB:6 (forward) 79: mov u32 %r2841 0x00000000 (0) 80: bra BB:6 (0) BB:5 (12 instructions) - idom = BB:3, df = { BB:6 } -> BB:6 (forward) 81: rcp f32 %r2868 %r2836 (0) 82: mul f32 %r2870 %r2814 %r2868 (0) 83: mul f32 %r2872 %r2813 %r2870 (0) 84: mul f32 %r2873 %r2814 %r2870 (0) 85: mul f32 %r2874 %r2815 %r2870 (0) 86: neg f32 %r2879 %r2872 (0) 87: mov f32 %r2880 %r2879 (0) 88: neg f32 %r2882 %r2873 (0) 89: add f32 %r2883 %r2882 1.000000 (0) 90: neg f32 %r2885 %r2874 (0) 91: mov f32 %r2886 %r2885 (0) 92: bra BB:6 (0) BB:6 (13 instructions) - idom = BB:3, df = { BB:7 } -> BB:7 (forward) 93: phi u32 %r2847 %r2841 %r2880 (0) 94: phi u32 %r2848 %r2841 %r2883 (0) 95: phi u32 %r2849 %r2841 %r2886 (0) 96: join (0) 97: mul f32 %r2850 %r2847 %r2847 (0) 98: mad f32 %r2851 %r2848 %r2848 %r2850 (0) 99: mad f32 %r2852 %r2849 %r2849 %r2851 (0) 100: abs f32 %r2854 %r2852 (0) 101: rsq f32 %r2855 %r2854 (0) 102: mul f32 %r2858 %r2847 %r2855 (0) 103: mul f32 %r2859 %r2848 %r2855 (0) 104: mul f32 %r2860 %r2849 %r2855 (0) 105: bra BB:7 (0) BB:7 (44 instructions) - idom = BB:2, df = { BB:9 } -> BB:9 (forward) 106: phi u32 %r2887 %r2798 %r2858 (0) 107: phi u32 %r2888 %r2798 %r2859 (0) 108: phi u32 %r2889 %r2798 %r2860 (0) 109: join (0) 110: neg f32 %r2892 %r2887 (0) 111: neg f32 %r2894 %r2888 (0) 112: neg f32 %r2896 %r2889 (0) 113: set f32 %r2906 gt %r2829 0.000000 (0) 114: set f32 %r2907 lt %r2829 0.000000 (0) 115: sub f32 %r2908 %r2906 %r2907 (0) 116: abs f32 %r2909 %r2829 (0) 117: neg f32 %r2911 %r2909 (0) 118: add f32 %r2912 %r2911 1.000000 (0) 119: rsq f32 %r2914 %r2912 (0) 120: rcp f32 %r2915 %r2914 (0) 121: mov u32 %r2920 0xbcc19a5f (0) 122: mov u32 %r2921 0x3da68d87 (0) 123: mad f32 %r2922 %r2909 %r2920 %r2921 (0) 124: mov u32 %r2924 0xbe5bc094 (0) 125: mad f32 %r2925 %r2909 %r2922 %r2924 (0) 126: mov u32 %r2927 0x3fc90fdb (0) 127: mad f32 %r2928 %r2909 %r2925 %r2927 (0) 128: mul f32 %r2930 %r2915 %r2928 (0) 129: neg f32 %r2933 %r2930 (0) 130: add f32 %r2934 %r2933 1.570796 (0) 131: mul f32 %r2936 %r2908 %r2934 (0) 132: neg f32 %r2939 %r2936 (0) 133: add f32 %r2940 %r2939 1.570796 (0) 134: presin f32 %r2942 %r2940 (0) 135: sin f32 %r2943 %r2942 (0) 136: mul f32 %r2947 %r2943 0.200000 (0) 137: mul f32 %r2950 %r2829 0.200000 (0) 138: mul f32 %r2952 %r2950 %r2892 (0) 139: mul f32 %r2953 %r2950 %r2894 (0) 140: mul f32 %r2954 %r2950 %r2896 (0) 141: neg f32 %r2960 %r2952 (0) 142: mad f32 %r2961 %r2947 %r2892 %r2960 (0) 143: neg f32 %r2962 %r2953 (0) 144: mad f32 %r2963 %r2947 %r2894 %r2962 (0) 145: neg f32 %r2964 %r2954 (0) 146: mad f32 %r2965 %r2947 %r2896 %r2964 (0) 147: mov f32 %r2966 -0.000000 (0) 148: mov f32 %r2967 %r2966 (0) 149: bra BB:9 (0) BB:8 (3 instructions) - idom = BB:0, df = { BB:9 } -> BB:9 (forward) 150: mov f32 %r6409 0.000000 (0) 151: mov f32 %r6411 -0.200000 (0) 152: bra BB:9 (0) BB:9 (75 instructions) - idom = BB:0, df = { } -> BB:10 (tree) 153: phi u32 %r2968 %r2961 %r6409 (0) 154: phi u32 %r2969 %r2963 %r6411 (0) 155: phi u32 %r2970 %r2965 %r6409 (0) 156: phi u32 %r2971 %r2967 %r6409 (0) 157: join (0) 158: shl u32 %r2973 %r2703 0x00000004 (0) 159: add u64 %r2979d %r2973 c7[0x320] (0) 160: add u32 %r2980 %r2973 0x00000004 (0) 161: set u8 %p2981 gt u32 %r2980 c7[0x328] (0) 162: not %p2981 ld u32 %r2982 g[%r2979d+0x0] (0) 163: %p2981 mov u32 %r2983 0x00000000 (0) 164: union u32 %r2984 %r2982 %r2983 (0) 165: add u32 %r2989 %r2973 0x00000008 (0) 166: set u8 %p2990 gt u32 %r2989 c7[0x328] (0) 167: not %p2990 ld u32 %r2991 g[%r2979d+0x4] (0) 168: %p2990 mov u32 %r2992 0x00000000 (0) 169: union u32 %r2993 %r2991 %r2992 (0) 170: add u32 %r2998 %r2973 0x0000000c (0) 171: set u8 %p2999 gt u32 %r2998 c7[0x328] (0) 172: not %p2999 ld u32 %r3000 g[%r2979d+0x8] (0) 173: %p2999 mov u32 %r3001 0x00000000 (0) 174: union u32 %r3002 %r3000 %r3001 (0) 175: add u32 %r3007 %r2973 0x00000010 (0) 176: set u8 %p3008 gt u32 %r3007 c7[0x328] (0) 177: not %p3008 ld u32 %r3009 g[%r2979d+0xc] (0) 178: %p3008 mov u32 %r3010 0x00000000 (0) 179: union u32 %r3011 %r3009 %r3010 (0) 180: add u64 %r3026d %r2973 c7[0x300] (0) 181: set u8 %p3028 gt u32 %r2980 c7[0x308] (0) 182: not %p3028 ld u32 %r3029 g[%r3026d+0x0] (0) 183: %p3028 mov u32 %r3030 0x00000000 (0) 184: union u32 %r3031 %r3029 %r3030 (0) 185: set u8 %p3037 gt u32 %r2989 c7[0x308] (0) 186: not %p3037 ld u32 %r3038 g[%r3026d+0x4] (0) 187: %p3037 mov u32 %r3039 0x00000000 (0) 188: union u32 %r3040 %r3038 %r3039 (0) 189: set u8 %p3046 gt u32 %r2998 c7[0x308] (0) 190: not %p3046 ld u32 %r3047 g[%r3026d+0x8] (0) 191: %p3046 mov u32 %r3048 0x00000000 (0) 192: union u32 %r3049 %r3047 %r3048 (0) 193: set u8 %p3055 gt u32 %r3007 c7[0x308] (0) 194: not %p3055 ld u32 %r3056 g[%r3026d+0xc] (0) 195: %p3055 mov u32 %r3057 0x00000000 (0) 196: union u32 %r3058 %r3056 %r3057 (0) 197: mul f32 %r3064 %r2968 10.000000 (0) 198: mul f32 %r3066 %r2969 10.000000 (0) 199: mul f32 %r3068 %r2970 10.000000 (0) 200: mul f32 %r3070 %r2971 10.000000 (0) 201: ld u32 %r3075 c0[0x10] (0) 202: mul f32 %r3077 %r3075 c0[0x10] (0) 203: neg f32 %r3079 %r3031 (0) 204: mad f32 %r3080 %r2984 2.000000 %r3079 (0) 205: neg f32 %r3082 %r3040 (0) 206: mad f32 %r3083 %r2993 2.000000 %r3082 (0) 207: neg f32 %r3085 %r3049 (0) 208: mad f32 %r3086 %r3002 2.000000 %r3085 (0) 209: neg f32 %r3088 %r3058 (0) 210: mad f32 %r3089 %r3011 2.000000 %r3088 (0) 211: mad f32 %r3094 %r3064 %r3077 %r3080 (0) 212: mad f32 %r3095 %r3066 %r3077 %r3083 (0) 213: mad f32 %r3096 %r3068 %r3077 %r3086 (0) 214: mad f32 %r3097 %r3070 %r3077 %r3089 (0) 215: add u64 %r3105d %r2973 c7[0x330] (0) 216: set u8 %p3107 gt u32 %r2980 c7[0x338] (0) 217: not %p3107 st u32 # g[%r3105d+0x0] %r3094 (0) 218: set u8 %p3113 gt u32 %r2989 c7[0x338] (0) 219: not %p3113 st u32 # g[%r3105d+0x4] %r3095 (0) 220: set u8 %p3119 gt u32 %r2998 c7[0x338] (0) 221: not %p3119 st u32 # g[%r3105d+0x8] %r3096 (0) 222: set u8 %p3125 gt u32 %r3007 c7[0x338] (0) 223: not %p3125 st u32 # g[%r3105d+0xc] %r3097 (0) 224: membar (SUBOP:7) - # (0) 225: bar u32 # 0x00000000 0x00000000 (0) 226: mov u32 %r3126 0x00000000 (0) 227: prebreak BB:11 (0) BB:10 (12 instructions) - idom = BB:9, df = { BB:10 } -> BB:13 (forward) -> BB:12 (tree) 228: phi u32 %r3136 %r4133 %r3126 (0) 229: phi u32 %r3137 %r4004 %r3135 (0) 230: phi u32 %r3138 %r4005 %r3135 (0) 231: phi u32 %r3139 %r4006 %r3135 (0) 232: phi u32 %r3140 %r4007 %r3135 (0) 233: phi u32 %r3141 %r4008 %r3135 (0) 234: phi u32 %r3142 %r4009 %r3135 (0) 235: phi u32 %r3143 %r4010 %r3135 (0) 236: phi u32 %r3144 %r4011 %r3135 (0) 237: precont BB:10 (0) 238: set u8 %p3147 ge s32 %r3136 4 (0) 239: not %p3147 bra BB:13 (0) BB:12 (1 instructions) - idom = BB:10, df = { } -> BB:11 (cross) 240: break BB:11 (0) BB:13 (2 instructions) - idom = BB:10, df = { BB:10 } -> BB:14 (tree) 241: mov u32 %r4001 0x00000000 (0) 242: prebreak BB:15 (0) BB:14 (12 instructions) - idom = BB:13, df = { BB:10 BB:14 } -> BB:17 (forward) -> BB:16 (tree) 243: phi u32 %r4003 %r5880 %r4001 (0) 244: phi u32 %r4004 %r5871 %r3137 (0) 245: phi u32 %r4005 %r5872 %r3138 (0) 246: phi u32 %r4006 %r5873 %r3139 (0) 247: phi u32 %r4007 %r5874 %r3140 (0) 248: phi u32 %r4008 %r5875 %r3141 (0) 249: phi u32 %r4009 %r5876 %r3142 (0) 250: phi u32 %r4010 %r5877 %r3143 (0) 251: phi u32 %r4011 %r5878 %r3144 (0) 252: precont BB:14 (0) 253: set u8 %p4014 ge s32 %r4003 2 (0) 254: not %p4014 bra BB:17 (0) BB:16 (1 instructions) - idom = BB:14, df = { BB:10 } -> BB:15 (cross) 255: break BB:15 (0) BB:17 (19 instructions) - idom = BB:14, df = { BB:14 } -> BB:25 (tree) -> BB:18 (tree) 256: mov u32 %r4661 0x00000002 (0) 257: mov u32 $r0 %r2717 (0) 258: mov u32 $r1 %r4661 (0) 259: call abs BUILTIN:1 (0) 260: mov u32 %r4662 $r1 (0) 261: nop - { $r0 $r2d } (0) 262: nop - $p0q (0) 263: set u32 %r4663 eq %r4662 %r4003 (0) 264: mov u32 $r0 %r2715 (0) 265: mov u32 $r1 %r4661 (0) 266: call abs BUILTIN:1 (0) 267: mov u32 %r4665 $r1 (0) 268: nop - { $r0 $r2d } (0) 269: nop - $p0q (0) 270: set u32 %r4666 eq %r4665 %r4003 (0) 271: and u32 %r4667 %r4663 %r4666 (0) 272: joinat BB:35 (0) 273: set u8 %p4668 neu u32 0x00000000 %r4667 (0) 274: not %p4668 bra BB:25 (0) BB:18 (33 instructions) - idom = BB:17, df = { BB:35 } -> BB:20 (forward) -> BB:19 (tree) 275: shl u32 %r4670 %r2703 0x00000004 (0) 276: add u64 %r4674d %r4670 c7[0x330] (0) 277: add u32 %r4675 %r4670 0x00000004 (0) 278: set u8 %p4676 gt u32 %r4675 c7[0x338] (0) 279: not %p4676 ld u32 %r4677 g[%r4674d+0x0] (0) 280: %p4676 mov u32 %r4678 0x00000000 (0) 281: union u32 %r4679 %r4677 %r4678 (0) 282: add u32 %r4684 %r4670 0x00000008 (0) 283: set u8 %p4685 gt u32 %r4684 c7[0x338] (0) 284: not %p4685 ld u32 %r4686 g[%r4674d+0x4] (0) 285: %p4685 mov u32 %r4687 0x00000000 (0) 286: union u32 %r4688 %r4686 %r4687 (0) 287: add u32 %r4693 %r4670 0x0000000c (0) 288: set u8 %p4694 gt u32 %r4693 c7[0x338] (0) 289: not %p4694 ld u32 %r4695 g[%r4674d+0x8] (0) 290: %p4694 mov u32 %r4696 0x00000000 (0) 291: union u32 %r4697 %r4695 %r4696 (0) 292: add u32 %r4702 %r4670 0x00000010 (0) 293: set u8 %p4703 gt u32 %r4702 c7[0x338] (0) 294: not %p4703 ld u32 %r4704 g[%r4674d+0xc] (0) 295: %p4703 mov u32 %r4705 0x00000000 (0) 296: union u32 %r4706 %r4704 %r4705 (0) 297: add u32 %r4716 %r2703 0x00000001 (0) 298: ld u32 %r4717 c0[0x0] (0) 299: mov u32 $r0 %r4716 (0) 300: mov u32 $r1 %r4717 (0) 301: call abs BUILTIN:1 (0) 302: mov u32 %r4718 $r1 (0) 303: nop - { $r0 $r2d } (0) 304: nop - $p0q (0) 305: joinat BB:20 (0) 306: set u8 %p4720 lt s32 %r2715 %r4718 (0) 307: not %p4720 bra BB:20 (0) BB:19 (102 instructions) - idom = BB:18, df = { BB:20 } -> BB:20 (forward) 308: shl u32 %r6425 %r2703 0x00000004 (0) 309: add u32 %r4722 %r6425 0x00000010 (0) 310: add u64 %r4726d %r4722 c7[0x330] (0) 311: add u32 %r4727 %r4722 0x00000004 (0) 312: set u8 %p4728 gt u32 %r4727 c7[0x338] (0) 313: not %p4728 ld u32 %r4729 g[%r4726d+0x0] (0) 314: %p4728 mov u32 %r4730 0x00000000 (0) 315: union u32 %r4731 %r4729 %r4730 (0) 316: add u32 %r4736 %r4722 0x00000008 (0) 317: set u8 %p4737 gt u32 %r4736 c7[0x338] (0) 318: not %p4737 ld u32 %r4738 g[%r4726d+0x4] (0) 319: %p4737 mov u32 %r4739 0x00000000 (0) 320: union u32 %r4740 %r4738 %r4739 (0) 321: add u32 %r4745 %r4722 0x0000000c (0) 322: set u8 %p4746 gt u32 %r4745 c7[0x338] (0) 323: not %p4746 ld u32 %r4747 g[%r4726d+0x8] (0) 324: %p4746 mov u32 %r4748 0x00000000 (0) 325: union u32 %r4749 %r4747 %r4748 (0) 326: add u32 %r4754 %r4722 0x00000010 (0) 327: set u8 %p4755 gt u32 %r4754 c7[0x338] (0) 328: not %p4755 ld u32 %r4756 g[%r4726d+0xc] (0) 329: %p4755 mov u32 %r4757 0x00000000 (0) 330: union u32 %r4758 %r4756 %r4757 (0) 331: neg f32 %r4763 %r4731 (0) 332: add f32 %r4764 %r4679 %r4763 (0) 333: neg f32 %r4765 %r4740 (0) 334: add f32 %r4766 %r4688 %r4765 (0) 335: neg f32 %r4767 %r4749 (0) 336: add f32 %r4768 %r4697 %r4767 (0) 337: neg f32 %r4769 %r4758 (0) 338: add f32 %r4770 %r4706 %r4769 (0) 339: mul f32 %r4771 %r4764 %r4764 (0) 340: mad f32 %r4772 %r4766 %r4766 %r4771 (0) 341: mad f32 %r4773 %r4768 %r4768 %r4772 (0) 342: mad f32 %r4774 %r4770 %r4770 %r4773 (0) 343: rsq f32 %r4776 %r4774 (0) 344: rcp f32 %r4777 %r4776 (0) 345: neg f32 %r4779 %r4777 (0) 346: add f32 %r4780 %r4779 c0[0x20] (0) 347: mul f32 %r4782 %r4780 0.350000 (0) 348: rcp f32 %r4783 %r4777 (0) 349: mul f32 %r4784 %r4782 %r4783 (0) 350: mul f32 %r4785 %r4784 %r4764 (0) 351: mul f32 %r4786 %r4784 %r4766 (0) 352: mul f32 %r4787 %r4784 %r4768 (0) 353: mul f32 %r4788 %r4784 %r4770 (0) 354: shl u32 %r4790 %r2703 0x00000004 (0) 355: add u64 %r4796d %r4790 c7[0x330] (0) 356: add u32 %r4797 %r4790 0x00000004 (0) 357: set u8 %p4798 gt u32 %r4797 c7[0x338] (0) 358: not %p4798 ld u32 %r4799 g[%r4796d+0x0] (0) 359: %p4798 mov u32 %r4800 0x00000000 (0) 360: union u32 %r4801 %r4799 %r4800 (0) 361: add u32 %r4806 %r4790 0x00000008 (0) 362: set u8 %p4807 gt u32 %r4806 c7[0x338] (0) 363: not %p4807 ld u32 %r4808 g[%r4796d+0x4] (0) 364: %p4807 mov u32 %r4809 0x00000000 (0) 365: union u32 %r4810 %r4808 %r4809 (0) 366: add u32 %r4815 %r4790 0x0000000c (0) 367: set u8 %p4816 gt u32 %r4815 c7[0x338] (0) 368: not %p4816 ld u32 %r4817 g[%r4796d+0x8] (0) 369: %p4816 mov u32 %r4818 0x00000000 (0) 370: union u32 %r4819 %r4817 %r4818 (0) 371: add u32 %r4824 %r4790 0x00000010 (0) 372: set u8 %p4825 gt u32 %r4824 c7[0x338] (0) 373: not %p4825 ld u32 %r4826 g[%r4796d+0xc] (0) 374: %p4825 mov u32 %r4827 0x00000000 (0) 375: union u32 %r4828 %r4826 %r4827 (0) 376: add f32 %r4829 %r4801 %r4785 (0) 377: add f32 %r4830 %r4810 %r4786 (0) 378: add f32 %r4831 %r4819 %r4787 (0) 379: add f32 %r4832 %r4828 %r4788 (0) 380: not %p4798 st u32 # g[%r4796d+0x0] %r4829 (0) 381: not %p4807 st u32 # g[%r4796d+0x4] %r4830 (0) 382: not %p4816 st u32 # g[%r4796d+0x8] %r4831 (0) 383: not %p4825 st u32 # g[%r4796d+0xc] %r4832 (0) 384: not %p4728 ld u32 %r4867 g[%r4726d+0x0] (0) 385: %p4728 mov u32 %r4868 0x00000000 (0) 386: union u32 %r4869 %r4867 %r4868 (0) 387: not %p4737 ld u32 %r4876 g[%r4726d+0x4] (0) 388: %p4737 mov u32 %r4877 0x00000000 (0) 389: union u32 %r4878 %r4876 %r4877 (0) 390: not %p4746 ld u32 %r4885 g[%r4726d+0x8] (0) 391: %p4746 mov u32 %r4886 0x00000000 (0) 392: union u32 %r4887 %r4885 %r4886 (0) 393: not %p4755 ld u32 %r4894 g[%r4726d+0xc] (0) 394: %p4755 mov u32 %r4895 0x00000000 (0) 395: union u32 %r4896 %r4894 %r4895 (0) 396: neg f32 %r4897 %r4785 (0) 397: add f32 %r4898 %r4869 %r4897 (0) 398: neg f32 %r4899 %r4786 (0) 399: add f32 %r4900 %r4878 %r4899 (0) 400: neg f32 %r4901 %r4787 (0) 401: add f32 %r4902 %r4887 %r4901 (0) 402: neg f32 %r4903 %r4788 (0) 403: add f32 %r4904 %r4896 %r4903 (0) 404: not %p4728 st u32 # g[%r4726d+0x0] %r4898 (0) 405: not %p4737 st u32 # g[%r4726d+0x4] %r4900 (0) 406: not %p4746 st u32 # g[%r4726d+0x8] %r4902 (0) 407: not %p4755 st u32 # g[%r4726d+0xc] %r4904 (0) 408: membar (SUBOP:7) - # (0) 409: bra BB:20 (0) BB:20 (11 instructions) - idom = BB:18, df = { BB:35 } -> BB:22 (forward) -> BB:21 (tree) 410: phi u32 %r4929 %r4004 %r4731 (0) 411: phi u32 %r4930 %r4005 %r4740 (0) 412: phi u32 %r4931 %r4006 %r4749 (0) 413: phi u32 %r4932 %r4007 %r4758 (0) 414: join (0) 415: ld u32 %r4933 c0[0x0] (0) 416: add u32 %r4934 %r2703 c0[0x0] (0) 417: mul u32 %r4937 %r4933 c0[0x0] (0) 418: joinat BB:22 (0) 419: set u8 %p4939 lt s32 %r4934 %r4937 (0) 420: not %p4939 bra BB:22 (0) BB:21 (101 instructions) - idom = BB:20, df = { BB:22 } -> BB:22 (forward) 421: shl u32 %r4941 %r4934 0x00000004 (0) 422: add u64 %r4945d %r4941 c7[0x330] (0) 423: add u32 %r4946 %r4941 0x00000004 (0) 424: set u8 %p4947 gt u32 %r4946 c7[0x338] (0) 425: not %p4947 ld u32 %r4948 g[%r4945d+0x0] (0) 426: %p4947 mov u32 %r4949 0x00000000 (0) 427: union u32 %r4950 %r4948 %r4949 (0) 428: add u32 %r4955 %r4941 0x00000008 (0) 429: set u8 %p4956 gt u32 %r4955 c7[0x338] (0) 430: not %p4956 ld u32 %r4957 g[%r4945d+0x4] (0) 431: %p4956 mov u32 %r4958 0x00000000 (0) 432: union u32 %r4959 %r4957 %r4958 (0) 433: add u32 %r4964 %r4941 0x0000000c (0) 434: set u8 %p4965 gt u32 %r4964 c7[0x338] (0) 435: not %p4965 ld u32 %r4966 g[%r4945d+0x8] (0) 436: %p4965 mov u32 %r4967 0x00000000 (0) 437: union u32 %r4968 %r4966 %r4967 (0) 438: add u32 %r4973 %r4941 0x00000010 (0) 439: set u8 %p4974 gt u32 %r4973 c7[0x338] (0) 440: not %p4974 ld u32 %r4975 g[%r4945d+0xc] (0) 441: %p4974 mov u32 %r4976 0x00000000 (0) 442: union u32 %r4977 %r4975 %r4976 (0) 443: neg f32 %r4982 %r4950 (0) 444: add f32 %r4983 %r4679 %r4982 (0) 445: neg f32 %r4984 %r4959 (0) 446: add f32 %r4985 %r4688 %r4984 (0) 447: neg f32 %r4986 %r4968 (0) 448: add f32 %r4987 %r4697 %r4986 (0) 449: neg f32 %r4988 %r4977 (0) 450: add f32 %r4989 %r4706 %r4988 (0) 451: mul f32 %r4990 %r4983 %r4983 (0) 452: mad f32 %r4991 %r4985 %r4985 %r4990 (0) 453: mad f32 %r4992 %r4987 %r4987 %r4991 (0) 454: mad f32 %r4993 %r4989 %r4989 %r4992 (0) 455: rsq f32 %r4995 %r4993 (0) 456: rcp f32 %r4996 %r4995 (0) 457: neg f32 %r4998 %r4996 (0) 458: add f32 %r4999 %r4998 c0[0x20] (0) 459: mul f32 %r5001 %r4999 0.350000 (0) 460: rcp f32 %r5002 %r4996 (0) 461: mul f32 %r5003 %r5001 %r5002 (0) 462: mul f32 %r5004 %r5003 %r4983 (0) 463: mul f32 %r5005 %r5003 %r4985 (0) 464: mul f32 %r5006 %r5003 %r4987 (0) 465: mul f32 %r5007 %r5003 %r4989 (0) 466: shl u32 %r5009 %r2703 0x00000004 (0) 467: add u64 %r5015d %r5009 c7[0x330] (0) 468: add u32 %r5016 %r5009 0x00000004 (0) 469: set u8 %p5017 gt u32 %r5016 c7[0x338] (0) 470: not %p5017 ld u32 %r5018 g[%r5015d+0x0] (0) 471: %p5017 mov u32 %r5019 0x00000000 (0) 472: union u32 %r5020 %r5018 %r5019 (0) 473: add u32 %r5025 %r5009 0x00000008 (0) 474: set u8 %p5026 gt u32 %r5025 c7[0x338] (0) 475: not %p5026 ld u32 %r5027 g[%r5015d+0x4] (0) 476: %p5026 mov u32 %r5028 0x00000000 (0) 477: union u32 %r5029 %r5027 %r5028 (0) 478: add u32 %r5034 %r5009 0x0000000c (0) 479: set u8 %p5035 gt u32 %r5034 c7[0x338] (0) 480: not %p5035 ld u32 %r5036 g[%r5015d+0x8] (0) 481: %p5035 mov u32 %r5037 0x00000000 (0) 482: union u32 %r5038 %r5036 %r5037 (0) 483: add u32 %r5043 %r5009 0x00000010 (0) 484: set u8 %p5044 gt u32 %r5043 c7[0x338] (0) 485: not %p5044 ld u32 %r5045 g[%r5015d+0xc] (0) 486: %p5044 mov u32 %r5046 0x00000000 (0) 487: union u32 %r5047 %r5045 %r5046 (0) 488: add f32 %r5048 %r5020 %r5004 (0) 489: add f32 %r5049 %r5029 %r5005 (0) 490: add f32 %r5050 %r5038 %r5006 (0) 491: add f32 %r5051 %r5047 %r5007 (0) 492: not %p5017 st u32 # g[%r5015d+0x0] %r5048 (0) 493: not %p5026 st u32 # g[%r5015d+0x4] %r5049 (0) 494: not %p5035 st u32 # g[%r5015d+0x8] %r5050 (0) 495: not %p5044 st u32 # g[%r5015d+0xc] %r5051 (0) 496: not %p4947 ld u32 %r5086 g[%r4945d+0x0] (0) 497: %p4947 mov u32 %r5087 0x00000000 (0) 498: union u32 %r5088 %r5086 %r5087 (0) 499: not %p4956 ld u32 %r5095 g[%r4945d+0x4] (0) 500: %p4956 mov u32 %r5096 0x00000000 (0) 501: union u32 %r5097 %r5095 %r5096 (0) 502: not %p4965 ld u32 %r5104 g[%r4945d+0x8] (0) 503: %p4965 mov u32 %r5105 0x00000000 (0) 504: union u32 %r5106 %r5104 %r5105 (0) 505: not %p4974 ld u32 %r5113 g[%r4945d+0xc] (0) 506: %p4974 mov u32 %r5114 0x00000000 (0) 507: union u32 %r5115 %r5113 %r5114 (0) 508: neg f32 %r5116 %r5004 (0) 509: add f32 %r5117 %r5088 %r5116 (0) 510: neg f32 %r5118 %r5005 (0) 511: add f32 %r5119 %r5097 %r5118 (0) 512: neg f32 %r5120 %r5006 (0) 513: add f32 %r5121 %r5106 %r5120 (0) 514: neg f32 %r5122 %r5007 (0) 515: add f32 %r5123 %r5115 %r5122 (0) 516: not %p4947 st u32 # g[%r4945d+0x0] %r5117 (0) 517: not %p4956 st u32 # g[%r4945d+0x4] %r5119 (0) 518: not %p4965 st u32 # g[%r4945d+0x8] %r5121 (0) 519: not %p4974 st u32 # g[%r4945d+0xc] %r5123 (0) 520: membar (SUBOP:7) - # (0) 521: bra BB:22 (0) BB:22 (21 instructions) - idom = BB:20, df = { BB:35 } -> BB:24 (forward) -> BB:23 (tree) 522: phi u32 %r5148 %r4008 %r4950 (0) 523: phi u32 %r5149 %r4009 %r4959 (0) 524: phi u32 %r5150 %r4010 %r4968 (0) 525: phi u32 %r5151 %r4011 %r4977 (0) 526: join (0) 527: add u32 %r5153 %r2703 0x00000001 (0) 528: ld u32 %r5154 c0[0x0] (0) 529: add u32 %r5155 %r5153 c0[0x0] (0) 530: mul u32 %r5158 %r5154 c0[0x0] (0) 531: set s32 %r5159 lt %r5155 %r5158 (0) 532: mov u32 $r0 %r5155 (0) 533: mov u32 $r1 %r5154 (0) 534: call abs BUILTIN:1 (0) 535: mov u32 %r5161 $r1 (0) 536: nop - { $r0 $r2d } (0) 537: nop - $p0q (0) 538: set s32 %r5162 lt %r2715 %r5161 (0) 539: and u32 %r5163 %r5159 %r5162 (0) 540: joinat BB:24 (0) 541: set u8 %p5164 neu u32 0x00000000 %r5163 (0) 542: not %p5164 bra BB:24 (0) BB:23 (317 instructions) - idom = BB:22, df = { BB:24 } -> BB:24 (forward) 543: shl u32 %r5166 %r5155 0x00000004 (0) 544: add u64 %r5170d %r5166 c7[0x330] (0) 545: add u32 %r5171 %r5166 0x00000004 (0) 546: set u8 %p5172 gt u32 %r5171 c7[0x338] (0) 547: not %p5172 ld u32 %r5173 g[%r5170d+0x0] (0) 548: %p5172 mov u32 %r5174 0x00000000 (0) 549: union u32 %r5175 %r5173 %r5174 (0) 550: add u32 %r5180 %r5166 0x00000008 (0) 551: set u8 %p5181 gt u32 %r5180 c7[0x338] (0) 552: not %p5181 ld u32 %r5182 g[%r5170d+0x4] (0) 553: %p5181 mov u32 %r5183 0x00000000 (0) 554: union u32 %r5184 %r5182 %r5183 (0) 555: add u32 %r5189 %r5166 0x0000000c (0) 556: set u8 %p5190 gt u32 %r5189 c7[0x338] (0) 557: not %p5190 ld u32 %r5191 g[%r5170d+0x8] (0) 558: %p5190 mov u32 %r5192 0x00000000 (0) 559: union u32 %r5193 %r5191 %r5192 (0) 560: add u32 %r5198 %r5166 0x00000010 (0) 561: set u8 %p5199 gt u32 %r5198 c7[0x338] (0) 562: not %p5199 ld u32 %r5200 g[%r5170d+0xc] (0) 563: %p5199 mov u32 %r5201 0x00000000 (0) 564: union u32 %r5202 %r5200 %r5201 (0) 565: neg f32 %r5207 %r5175 (0) 566: add f32 %r5208 %r4929 %r5207 (0) 567: neg f32 %r5209 %r5184 (0) 568: add f32 %r5210 %r4930 %r5209 (0) 569: neg f32 %r5211 %r5193 (0) 570: add f32 %r5212 %r4931 %r5211 (0) 571: neg f32 %r5213 %r5202 (0) 572: add f32 %r5214 %r4932 %r5213 (0) 573: mul f32 %r5215 %r5208 %r5208 (0) 574: mad f32 %r5216 %r5210 %r5210 %r5215 (0) 575: mad f32 %r5217 %r5212 %r5212 %r5216 (0) 576: mad f32 %r5218 %r5214 %r5214 %r5217 (0) 577: rsq f32 %r5220 %r5218 (0) 578: rcp f32 %r5221 %r5220 (0) 579: neg f32 %r5223 %r5221 (0) 580: add f32 %r5224 %r5223 c0[0x20] (0) 581: mul f32 %r5226 %r5224 0.350000 (0) 582: rcp f32 %r5227 %r5221 (0) 583: mul f32 %r5228 %r5226 %r5227 (0) 584: mul f32 %r5229 %r5228 %r5208 (0) 585: mul f32 %r5230 %r5228 %r5210 (0) 586: mul f32 %r5231 %r5228 %r5212 (0) 587: mul f32 %r5232 %r5228 %r5214 (0) 588: shl u32 %r6423 %r2703 0x00000004 (0) 589: add u32 %r5234 %r6423 0x00000010 (0) 590: add u64 %r5240d %r5234 c7[0x330] (0) 591: add u32 %r5241 %r5234 0x00000004 (0) 592: set u8 %p5242 gt u32 %r5241 c7[0x338] (0) 593: not %p5242 ld u32 %r5243 g[%r5240d+0x0] (0) 594: %p5242 mov u32 %r5244 0x00000000 (0) 595: union u32 %r5245 %r5243 %r5244 (0) 596: add u32 %r5250 %r5234 0x00000008 (0) 597: set u8 %p5251 gt u32 %r5250 c7[0x338] (0) 598: not %p5251 ld u32 %r5252 g[%r5240d+0x4] (0) 599: %p5251 mov u32 %r5253 0x00000000 (0) 600: union u32 %r5254 %r5252 %r5253 (0) 601: add u32 %r5259 %r5234 0x0000000c (0) 602: set u8 %p5260 gt u32 %r5259 c7[0x338] (0) 603: not %p5260 ld u32 %r5261 g[%r5240d+0x8] (0) 604: %p5260 mov u32 %r5262 0x00000000 (0) 605: union u32 %r5263 %r5261 %r5262 (0) 606: add u32 %r5268 %r5234 0x00000010 (0) 607: set u8 %p5269 gt u32 %r5268 c7[0x338] (0) 608: not %p5269 ld u32 %r5270 g[%r5240d+0xc] (0) 609: %p5269 mov u32 %r5271 0x00000000 (0) 610: union u32 %r5272 %r5270 %r5271 (0) 611: add f32 %r5273 %r5245 %r5229 (0) 612: add f32 %r5274 %r5254 %r5230 (0) 613: add f32 %r5275 %r5263 %r5231 (0) 614: add f32 %r5276 %r5272 %r5232 (0) 615: not %p5242 st u32 # g[%r5240d+0x0] %r5273 (0) 616: not %p5251 st u32 # g[%r5240d+0x4] %r5274 (0) 617: not %p5260 st u32 # g[%r5240d+0x8] %r5275 (0) 618: not %p5269 st u32 # g[%r5240d+0xc] %r5276 (0) 619: not %p5172 ld u32 %r5311 g[%r5170d+0x0] (0) 620: %p5172 mov u32 %r5312 0x00000000 (0) 621: union u32 %r5313 %r5311 %r5312 (0) 622: not %p5181 ld u32 %r5320 g[%r5170d+0x4] (0) 623: %p5181 mov u32 %r5321 0x00000000 (0) 624: union u32 %r5322 %r5320 %r5321 (0) 625: not %p5190 ld u32 %r5329 g[%r5170d+0x8] (0) 626: %p5190 mov u32 %r5330 0x00000000 (0) 627: union u32 %r5331 %r5329 %r5330 (0) 628: not %p5199 ld u32 %r5338 g[%r5170d+0xc] (0) 629: %p5199 mov u32 %r5339 0x00000000 (0) 630: union u32 %r5340 %r5338 %r5339 (0) 631: neg f32 %r5341 %r5229 (0) 632: add f32 %r5342 %r5313 %r5341 (0) 633: neg f32 %r5343 %r5230 (0) 634: add f32 %r5344 %r5322 %r5343 (0) 635: neg f32 %r5345 %r5231 (0) 636: add f32 %r5346 %r5331 %r5345 (0) 637: neg f32 %r5347 %r5232 (0) 638: add f32 %r5348 %r5340 %r5347 (0) 639: not %p5172 st u32 # g[%r5170d+0x0] %r5342 (0) 640: not %p5181 st u32 # g[%r5170d+0x4] %r5344 (0) 641: not %p5190 st u32 # g[%r5170d+0x8] %r5346 (0) 642: not %p5199 st u32 # g[%r5170d+0xc] %r5348 (0) 643: membar (SUBOP:7) - # (0) 644: add f32 %r5374 %r5148 %r5207 (0) 645: add f32 %r5376 %r5149 %r5209 (0) 646: add f32 %r5378 %r5150 %r5211 (0) 647: add f32 %r5380 %r5151 %r5213 (0) 648: mul f32 %r5381 %r5374 %r5374 (0) 649: mad f32 %r5382 %r5376 %r5376 %r5381 (0) 650: mad f32 %r5383 %r5378 %r5378 %r5382 (0) 651: mad f32 %r5384 %r5380 %r5380 %r5383 (0) 652: rsq f32 %r5386 %r5384 (0) 653: rcp f32 %r5387 %r5386 (0) 654: neg f32 %r5389 %r5387 (0) 655: add f32 %r5390 %r5389 c0[0x20] (0) 656: mul f32 %r5392 %r5390 0.350000 (0) 657: rcp f32 %r5393 %r5387 (0) 658: mul f32 %r5394 %r5392 %r5393 (0) 659: mul f32 %r5395 %r5394 %r5374 (0) 660: mul f32 %r5396 %r5394 %r5376 (0) 661: mul f32 %r5397 %r5394 %r5378 (0) 662: mul f32 %r5398 %r5394 %r5380 (0) 663: shl u32 %r5400 %r4934 0x00000004 (0) 664: add u64 %r5406d %r5400 c7[0x330] (0) 665: add u32 %r5407 %r5400 0x00000004 (0) 666: set u8 %p5408 gt u32 %r5407 c7[0x338] (0) 667: not %p5408 ld u32 %r5409 g[%r5406d+0x0] (0) 668: %p5408 mov u32 %r5410 0x00000000 (0) 669: union u32 %r5411 %r5409 %r5410 (0) 670: add u32 %r5416 %r5400 0x00000008 (0) 671: set u8 %p5417 gt u32 %r5416 c7[0x338] (0) 672: not %p5417 ld u32 %r5418 g[%r5406d+0x4] (0) 673: %p5417 mov u32 %r5419 0x00000000 (0) 674: union u32 %r5420 %r5418 %r5419 (0) 675: add u32 %r5425 %r5400 0x0000000c (0) 676: set u8 %p5426 gt u32 %r5425 c7[0x338] (0) 677: not %p5426 ld u32 %r5427 g[%r5406d+0x8] (0) 678: %p5426 mov u32 %r5428 0x00000000 (0) 679: union u32 %r5429 %r5427 %r5428 (0) 680: add u32 %r5434 %r5400 0x00000010 (0) 681: set u8 %p5435 gt u32 %r5434 c7[0x338] (0) 682: not %p5435 ld u32 %r5436 g[%r5406d+0xc] (0) 683: %p5435 mov u32 %r5437 0x00000000 (0) 684: union u32 %r5438 %r5436 %r5437 (0) 685: add f32 %r5439 %r5411 %r5395 (0) 686: add f32 %r5440 %r5420 %r5396 (0) 687: add f32 %r5441 %r5429 %r5397 (0) 688: add f32 %r5442 %r5438 %r5398 (0) 689: not %p5408 st u32 # g[%r5406d+0x0] %r5439 (0) 690: not %p5417 st u32 # g[%r5406d+0x4] %r5440 (0) 691: not %p5426 st u32 # g[%r5406d+0x8] %r5441 (0) 692: not %p5435 st u32 # g[%r5406d+0xc] %r5442 (0) 693: not %p5172 ld u32 %r5477 g[%r5170d+0x0] (0) 694: %p5172 mov u32 %r5478 0x00000000 (0) 695: union u32 %r5479 %r5477 %r5478 (0) 696: not %p5181 ld u32 %r5486 g[%r5170d+0x4] (0) 697: %p5181 mov u32 %r5487 0x00000000 (0) 698: union u32 %r5488 %r5486 %r5487 (0) 699: not %p5190 ld u32 %r5495 g[%r5170d+0x8] (0) 700: %p5190 mov u32 %r5496 0x00000000 (0) 701: union u32 %r5497 %r5495 %r5496 (0) 702: not %p5199 ld u32 %r5504 g[%r5170d+0xc] (0) 703: %p5199 mov u32 %r5505 0x00000000 (0) 704: union u32 %r5506 %r5504 %r5505 (0) 705: neg f32 %r5507 %r5395 (0) 706: add f32 %r5508 %r5479 %r5507 (0) 707: neg f32 %r5509 %r5396 (0) 708: add f32 %r5510 %r5488 %r5509 (0) 709: neg f32 %r5511 %r5397 (0) 710: add f32 %r5512 %r5497 %r5511 (0) 711: neg f32 %r5513 %r5398 (0) 712: add f32 %r5514 %r5506 %r5513 (0) 713: not %p5172 st u32 # g[%r5170d+0x0] %r5508 (0) 714: not %p5181 st u32 # g[%r5170d+0x4] %r5510 (0) 715: not %p5190 st u32 # g[%r5170d+0x8] %r5512 (0) 716: not %p5199 st u32 # g[%r5170d+0xc] %r5514 (0) 717: membar (SUBOP:7) - # (0) 718: add f32 %r5540 %r4679 %r5207 (0) 719: add f32 %r5542 %r4688 %r5209 (0) 720: add f32 %r5544 %r4697 %r5211 (0) 721: add f32 %r5546 %r4706 %r5213 (0) 722: mul f32 %r5547 %r5540 %r5540 (0) 723: mad f32 %r5548 %r5542 %r5542 %r5547 (0) 724: mad f32 %r5549 %r5544 %r5544 %r5548 (0) 725: mad f32 %r5550 %r5546 %r5546 %r5549 (0) 726: rsq f32 %r5552 %r5550 (0) 727: rcp f32 %r5553 %r5552 (0) 728: neg f32 %r5555 %r5553 (0) 729: add f32 %r5556 %r5555 c0[0x30] (0) 730: mul f32 %r5558 %r5556 0.350000 (0) 731: rcp f32 %r5559 %r5553 (0) 732: mul f32 %r5560 %r5558 %r5559 (0) 733: mul f32 %r5561 %r5560 %r5540 (0) 734: mul f32 %r5562 %r5560 %r5542 (0) 735: mul f32 %r5563 %r5560 %r5544 (0) 736: mul f32 %r5564 %r5560 %r5546 (0) 737: shl u32 %r5566 %r2703 0x00000004 (0) 738: add u64 %r5572d %r5566 c7[0x330] (0) 739: add u32 %r5573 %r5566 0x00000004 (0) 740: set u8 %p5574 gt u32 %r5573 c7[0x338] (0) 741: not %p5574 ld u32 %r5575 g[%r5572d+0x0] (0) 742: %p5574 mov u32 %r5576 0x00000000 (0) 743: union u32 %r5577 %r5575 %r5576 (0) 744: add u32 %r5582 %r5566 0x00000008 (0) 745: set u8 %p5583 gt u32 %r5582 c7[0x338] (0) 746: not %p5583 ld u32 %r5584 g[%r5572d+0x4] (0) 747: %p5583 mov u32 %r5585 0x00000000 (0) 748: union u32 %r5586 %r5584 %r5585 (0) 749: add u32 %r5591 %r5566 0x0000000c (0) 750: set u8 %p5592 gt u32 %r5591 c7[0x338] (0) 751: not %p5592 ld u32 %r5593 g[%r5572d+0x8] (0) 752: %p5592 mov u32 %r5594 0x00000000 (0) 753: union u32 %r5595 %r5593 %r5594 (0) 754: add u32 %r5600 %r5566 0x00000010 (0) 755: set u8 %p5601 gt u32 %r5600 c7[0x338] (0) 756: not %p5601 ld u32 %r5602 g[%r5572d+0xc] (0) 757: %p5601 mov u32 %r5603 0x00000000 (0) 758: union u32 %r5604 %r5602 %r5603 (0) 759: add f32 %r5605 %r5577 %r5561 (0) 760: add f32 %r5606 %r5586 %r5562 (0) 761: add f32 %r5607 %r5595 %r5563 (0) 762: add f32 %r5608 %r5604 %r5564 (0) 763: not %p5574 st u32 # g[%r5572d+0x0] %r5605 (0) 764: not %p5583 st u32 # g[%r5572d+0x4] %r5606 (0) 765: not %p5592 st u32 # g[%r5572d+0x8] %r5607 (0) 766: not %p5601 st u32 # g[%r5572d+0xc] %r5608 (0) 767: not %p5172 ld u32 %r5643 g[%r5170d+0x0] (0) 768: %p5172 mov u32 %r5644 0x00000000 (0) 769: union u32 %r5645 %r5643 %r5644 (0) 770: not %p5181 ld u32 %r5652 g[%r5170d+0x4] (0) 771: %p5181 mov u32 %r5653 0x00000000 (0) 772: union u32 %r5654 %r5652 %r5653 (0) 773: not %p5190 ld u32 %r5661 g[%r5170d+0x8] (0) 774: %p5190 mov u32 %r5662 0x00000000 (0) 775: union u32 %r5663 %r5661 %r5662 (0) 776: not %p5199 ld u32 %r5670 g[%r5170d+0xc] (0) 777: %p5199 mov u32 %r5671 0x00000000 (0) 778: union u32 %r5672 %r5670 %r5671 (0) 779: neg f32 %r5673 %r5561 (0) 780: add f32 %r5674 %r5645 %r5673 (0) 781: neg f32 %r5675 %r5562 (0) 782: add f32 %r5676 %r5654 %r5675 (0) 783: neg f32 %r5677 %r5563 (0) 784: add f32 %r5678 %r5663 %r5677 (0) 785: neg f32 %r5679 %r5564 (0) 786: add f32 %r5680 %r5672 %r5679 (0) 787: not %p5172 st u32 # g[%r5170d+0x0] %r5674 (0) 788: not %p5181 st u32 # g[%r5170d+0x4] %r5676 (0) 789: not %p5190 st u32 # g[%r5170d+0x8] %r5678 (0) 790: not %p5199 st u32 # g[%r5170d+0xc] %r5680 (0) 791: neg f32 %r5705 %r5148 (0) 792: add f32 %r5706 %r4929 %r5705 (0) 793: neg f32 %r5707 %r5149 (0) 794: add f32 %r5708 %r4930 %r5707 (0) 795: neg f32 %r5709 %r5150 (0) 796: add f32 %r5710 %r4931 %r5709 (0) 797: neg f32 %r5711 %r5151 (0) 798: add f32 %r5712 %r4932 %r5711 (0) 799: mul f32 %r5713 %r5706 %r5706 (0) 800: mad f32 %r5714 %r5708 %r5708 %r5713 (0) 801: mad f32 %r5715 %r5710 %r5710 %r5714 (0) 802: mad f32 %r5716 %r5712 %r5712 %r5715 (0) 803: rsq f32 %r5718 %r5716 (0) 804: rcp f32 %r5719 %r5718 (0) 805: neg f32 %r5721 %r5719 (0) 806: add f32 %r5722 %r5721 c0[0x30] (0) 807: mul f32 %r5724 %r5722 0.350000 (0) 808: rcp f32 %r5725 %r5719 (0) 809: mul f32 %r5726 %r5724 %r5725 (0) 810: mul f32 %r5727 %r5726 %r5706 (0) 811: mul f32 %r5728 %r5726 %r5708 (0) 812: mul f32 %r5729 %r5726 %r5710 (0) 813: mul f32 %r5730 %r5726 %r5712 (0) 814: not %p5242 ld u32 %r5741 g[%r5240d+0x0] (0) 815: %p5242 mov u32 %r5742 0x00000000 (0) 816: union u32 %r5743 %r5741 %r5742 (0) 817: not %p5251 ld u32 %r5750 g[%r5240d+0x4] (0) 818: %p5251 mov u32 %r5751 0x00000000 (0) 819: union u32 %r5752 %r5750 %r5751 (0) 820: not %p5260 ld u32 %r5759 g[%r5240d+0x8] (0) 821: %p5260 mov u32 %r5760 0x00000000 (0) 822: union u32 %r5761 %r5759 %r5760 (0) 823: not %p5269 ld u32 %r5768 g[%r5240d+0xc] (0) 824: %p5269 mov u32 %r5769 0x00000000 (0) 825: union u32 %r5770 %r5768 %r5769 (0) 826: add f32 %r5771 %r5743 %r5727 (0) 827: add f32 %r5772 %r5752 %r5728 (0) 828: add f32 %r5773 %r5761 %r5729 (0) 829: add f32 %r5774 %r5770 %r5730 (0) 830: not %p5242 st u32 # g[%r5240d+0x0] %r5771 (0) 831: not %p5251 st u32 # g[%r5240d+0x4] %r5772 (0) 832: not %p5260 st u32 # g[%r5240d+0x8] %r5773 (0) 833: not %p5269 st u32 # g[%r5240d+0xc] %r5774 (0) 834: not %p5408 ld u32 %r5809 g[%r5406d+0x0] (0) 835: %p5408 mov u32 %r5810 0x00000000 (0) 836: union u32 %r5811 %r5809 %r5810 (0) 837: not %p5417 ld u32 %r5818 g[%r5406d+0x4] (0) 838: %p5417 mov u32 %r5819 0x00000000 (0) 839: union u32 %r5820 %r5818 %r5819 (0) 840: not %p5426 ld u32 %r5827 g[%r5406d+0x8] (0) 841: %p5426 mov u32 %r5828 0x00000000 (0) 842: union u32 %r5829 %r5827 %r5828 (0) 843: not %p5435 ld u32 %r5836 g[%r5406d+0xc] (0) 844: %p5435 mov u32 %r5837 0x00000000 (0) 845: union u32 %r5838 %r5836 %r5837 (0) 846: neg f32 %r5839 %r5727 (0) 847: add f32 %r5840 %r5811 %r5839 (0) 848: neg f32 %r5841 %r5728 (0) 849: add f32 %r5842 %r5820 %r5841 (0) 850: neg f32 %r5843 %r5729 (0) 851: add f32 %r5844 %r5829 %r5843 (0) 852: neg f32 %r5845 %r5730 (0) 853: add f32 %r5846 %r5838 %r5845 (0) 854: not %p5408 st u32 # g[%r5406d+0x0] %r5840 (0) 855: not %p5417 st u32 # g[%r5406d+0x4] %r5842 (0) 856: not %p5426 st u32 # g[%r5406d+0x8] %r5844 (0) 857: not %p5435 st u32 # g[%r5406d+0xc] %r5846 (0) 858: membar (SUBOP:7) - # (0) 859: bra BB:24 (0) BB:24 (2 instructions) - idom = BB:22, df = { BB:35 } -> BB:35 (forward) 860: join (0) 861: bra BB:35 (0) BB:25 (15 instructions) - idom = BB:17, df = { BB:35 } -> BB:29 (tree) -> BB:26 (tree) 862: set u32 %r5883 eq %r4003 0x00000001 (0) 863: mov u32 %r5884 0x00000002 (0) 864: mov u32 $r0 %r2715 (0) 865: mov u32 $r1 %r5884 (0) 866: call abs BUILTIN:1 (0) 867: mov u32 %r5885 $r1 (0) 868: nop - { $r0 $r2d } (0) 869: nop - $p0q (0) 870: set u32 %r5887 eq %r5885 0x00000001 (0) 871: and u32 %r5888 %r5883 %r5887 (0) 872: set u32 %r5890 eq %r2717 0x00000000 (0) 873: and u32 %r5891 %r5888 %r5890 (0) 874: joinat BB:34 (0) 875: set u8 %p5892 neu u32 0x00000000 %r5891 (0) 876: not %p5892 bra BB:29 (0) BB:26 (4 instructions) - idom = BB:25, df = { BB:34 } -> BB:28 (forward) -> BB:27 (tree) 877: add u32 %r5894 %r2703 0x00000001 (0) 878: joinat BB:28 (0) 879: set u8 %p5897 lt s32 %r5894 c0[0x0] (0) 880: not %p5897 bra BB:28 (0) BB:27 (114 instructions) - idom = BB:26, df = { BB:28 } -> BB:28 (forward) 881: shl u32 %r5899 %r2703 0x00000004 (0) 882: add u64 %r5903d %r5899 c7[0x330] (0) 883: add u32 %r5904 %r5899 0x00000004 (0) 884: set u8 %p5905 gt u32 %r5904 c7[0x338] (0) 885: not %p5905 ld u32 %r5906 g[%r5903d+0x0] (0) 886: %p5905 mov u32 %r5907 0x00000000 (0) 887: union u32 %r5908 %r5906 %r5907 (0) 888: add u32 %r5913 %r5899 0x00000008 (0) 889: set u8 %p5914 gt u32 %r5913 c7[0x338] (0) 890: not %p5914 ld u32 %r5915 g[%r5903d+0x4] (0) 891: %p5914 mov u32 %r5916 0x00000000 (0) 892: union u32 %r5917 %r5915 %r5916 (0) 893: add u32 %r5922 %r5899 0x0000000c (0) 894: set u8 %p5923 gt u32 %r5922 c7[0x338] (0) 895: not %p5923 ld u32 %r5924 g[%r5903d+0x8] (0) 896: %p5923 mov u32 %r5925 0x00000000 (0) 897: union u32 %r5926 %r5924 %r5925 (0) 898: add u32 %r5931 %r5899 0x00000010 (0) 899: set u8 %p5932 gt u32 %r5931 c7[0x338] (0) 900: not %p5932 ld u32 %r5933 g[%r5903d+0xc] (0) 901: %p5932 mov u32 %r5934 0x00000000 (0) 902: union u32 %r5935 %r5933 %r5934 (0) 903: shl u32 %r6421 %r2703 0x00000004 (0) 904: add u32 %r5941 %r6421 0x00000010 (0) 905: add u64 %r5945d %r5941 c7[0x330] (0) 906: add u32 %r5946 %r5941 0x00000004 (0) 907: set u8 %p5947 gt u32 %r5946 c7[0x338] (0) 908: not %p5947 ld u32 %r5948 g[%r5945d+0x0] (0) 909: %p5947 mov u32 %r5949 0x00000000 (0) 910: union u32 %r5950 %r5948 %r5949 (0) 911: add u32 %r5955 %r5941 0x00000008 (0) 912: set u8 %p5956 gt u32 %r5955 c7[0x338] (0) 913: not %p5956 ld u32 %r5957 g[%r5945d+0x4] (0) 914: %p5956 mov u32 %r5958 0x00000000 (0) 915: union u32 %r5959 %r5957 %r5958 (0) 916: add u32 %r5964 %r5941 0x0000000c (0) 917: set u8 %p5965 gt u32 %r5964 c7[0x338] (0) 918: not %p5965 ld u32 %r5966 g[%r5945d+0x8] (0) 919: %p5965 mov u32 %r5967 0x00000000 (0) 920: union u32 %r5968 %r5966 %r5967 (0) 921: add u32 %r5973 %r5941 0x00000010 (0) 922: set u8 %p5974 gt u32 %r5973 c7[0x338] (0) 923: not %p5974 ld u32 %r5975 g[%r5945d+0xc] (0) 924: %p5974 mov u32 %r5976 0x00000000 (0) 925: union u32 %r5977 %r5975 %r5976 (0) 926: neg f32 %r5978 %r5950 (0) 927: add f32 %r5979 %r5908 %r5978 (0) 928: neg f32 %r5980 %r5959 (0) 929: add f32 %r5981 %r5917 %r5980 (0) 930: neg f32 %r5982 %r5968 (0) 931: add f32 %r5983 %r5926 %r5982 (0) 932: neg f32 %r5984 %r5977 (0) 933: add f32 %r5985 %r5935 %r5984 (0) 934: mul f32 %r5986 %r5979 %r5979 (0) 935: mad f32 %r5987 %r5981 %r5981 %r5986 (0) 936: mad f32 %r5988 %r5983 %r5983 %r5987 (0) 937: mad f32 %r5989 %r5985 %r5985 %r5988 (0) 938: rsq f32 %r5991 %r5989 (0) 939: rcp f32 %r5992 %r5991 (0) 940: neg f32 %r5994 %r5992 (0) 941: add f32 %r5995 %r5994 c0[0x20] (0) 942: mul f32 %r5997 %r5995 0.350000 (0) 943: rcp f32 %r5998 %r5992 (0) 944: mul f32 %r5999 %r5997 %r5998 (0) 945: mul f32 %r6000 %r5999 %r5979 (0) 946: mul f32 %r6001 %r5999 %r5981 (0) 947: mul f32 %r6002 %r5999 %r5983 (0) 948: mul f32 %r6003 %r5999 %r5985 (0) 949: not %p5905 ld u32 %r6014 g[%r5903d+0x0] (0) 950: %p5905 mov u32 %r6015 0x00000000 (0) 951: union u32 %r6016 %r6014 %r6015 (0) 952: not %p5914 ld u32 %r6023 g[%r5903d+0x4] (0) 953: %p5914 mov u32 %r6024 0x00000000 (0) 954: union u32 %r6025 %r6023 %r6024 (0) 955: not %p5923 ld u32 %r6032 g[%r5903d+0x8] (0) 956: %p5923 mov u32 %r6033 0x00000000 (0) 957: union u32 %r6034 %r6032 %r6033 (0) 958: not %p5932 ld u32 %r6041 g[%r5903d+0xc] (0) 959: %p5932 mov u32 %r6042 0x00000000 (0) 960: union u32 %r6043 %r6041 %r6042 (0) 961: add f32 %r6044 %r6016 %r6000 (0) 962: add f32 %r6045 %r6025 %r6001 (0) 963: add f32 %r6046 %r6034 %r6002 (0) 964: add f32 %r6047 %r6043 %r6003 (0) 965: not %p5905 st u32 # g[%r5903d+0x0] %r6044 (0) 966: not %p5914 st u32 # g[%r5903d+0x4] %r6045 (0) 967: not %p5923 st u32 # g[%r5903d+0x8] %r6046 (0) 968: not %p5932 st u32 # g[%r5903d+0xc] %r6047 (0) 969: not %p5947 ld u32 %r6082 g[%r5945d+0x0] (0) 970: %p5947 mov u32 %r6083 0x00000000 (0) 971: union u32 %r6084 %r6082 %r6083 (0) 972: not %p5956 ld u32 %r6091 g[%r5945d+0x4] (0) 973: %p5956 mov u32 %r6092 0x00000000 (0) 974: union u32 %r6093 %r6091 %r6092 (0) 975: not %p5965 ld u32 %r6100 g[%r5945d+0x8] (0) 976: %p5965 mov u32 %r6101 0x00000000 (0) 977: union u32 %r6102 %r6100 %r6101 (0) 978: not %p5974 ld u32 %r6109 g[%r5945d+0xc] (0) 979: %p5974 mov u32 %r6110 0x00000000 (0) 980: union u32 %r6111 %r6109 %r6110 (0) 981: neg f32 %r6112 %r6000 (0) 982: add f32 %r6113 %r6084 %r6112 (0) 983: neg f32 %r6114 %r6001 (0) 984: add f32 %r6115 %r6093 %r6114 (0) 985: neg f32 %r6116 %r6002 (0) 986: add f32 %r6117 %r6102 %r6116 (0) 987: neg f32 %r6118 %r6003 (0) 988: add f32 %r6119 %r6111 %r6118 (0) 989: not %p5947 st u32 # g[%r5945d+0x0] %r6113 (0) 990: not %p5956 st u32 # g[%r5945d+0x4] %r6115 (0) 991: not %p5965 st u32 # g[%r5945d+0x8] %r6117 (0) 992: not %p5974 st u32 # g[%r5945d+0xc] %r6119 (0) 993: membar (SUBOP:7) - # (0) 994: bra BB:28 (0) BB:28 (2 instructions) - idom = BB:26, df = { BB:34 } -> BB:34 (forward) 995: join (0) 996: bra BB:34 (0) BB:29 (15 instructions) - idom = BB:25, df = { BB:34 } -> BB:33 (forward) -> BB:30 (tree) 997: set u32 %r6145 eq %r4003 0x00000001 (0) 998: mov u32 %r6146 0x00000002 (0) 999: mov u32 $r0 %r2717 (0) 1000: mov u32 $r1 %r6146 (0) 1001: call abs BUILTIN:1 (0) 1002: mov u32 %r6147 $r1 (0) 1003: nop - { $r0 $r2d } (0) 1004: nop - $p0q (0) 1005: set u32 %r6149 eq %r6147 0x00000001 (0) 1006: and u32 %r6150 %r6145 %r6149 (0) 1007: set u32 %r6152 eq %r2715 0x00000000 (0) 1008: and u32 %r6153 %r6150 %r6152 (0) 1009: joinat BB:33 (0) 1010: set u8 %p6154 neu u32 0x00000000 %r6153 (0) 1011: not %p6154 bra BB:33 (0) BB:30 (6 instructions) - idom = BB:29, df = { BB:33 } -> BB:32 (forward) -> BB:31 (tree) 1012: ld u32 %r6155 c0[0x0] (0) 1013: add u32 %r6156 %r2703 c0[0x0] (0) 1014: mul u32 %r6159 %r6155 c0[0x0] (0) 1015: joinat BB:32 (0) 1016: set u8 %p6161 lt s32 %r6156 %r6159 (0) 1017: not %p6161 bra BB:32 (0) BB:31 (113 instructions) - idom = BB:30, df = { BB:32 } -> BB:32 (forward) 1018: shl u32 %r6163 %r2703 0x00000004 (0) 1019: add u64 %r6167d %r6163 c7[0x330] (0) 1020: add u32 %r6168 %r6163 0x00000004 (0) 1021: set u8 %p6169 gt u32 %r6168 c7[0x338] (0) 1022: not %p6169 ld u32 %r6170 g[%r6167d+0x0] (0) 1023: %p6169 mov u32 %r6171 0x00000000 (0) 1024: union u32 %r6172 %r6170 %r6171 (0) 1025: add u32 %r6177 %r6163 0x00000008 (0) 1026: set u8 %p6178 gt u32 %r6177 c7[0x338] (0) 1027: not %p6178 ld u32 %r6179 g[%r6167d+0x4] (0) 1028: %p6178 mov u32 %r6180 0x00000000 (0) 1029: union u32 %r6181 %r6179 %r6180 (0) 1030: add u32 %r6186 %r6163 0x0000000c (0) 1031: set u8 %p6187 gt u32 %r6186 c7[0x338] (0) 1032: not %p6187 ld u32 %r6188 g[%r6167d+0x8] (0) 1033: %p6187 mov u32 %r6189 0x00000000 (0) 1034: union u32 %r6190 %r6188 %r6189 (0) 1035: add u32 %r6195 %r6163 0x00000010 (0) 1036: set u8 %p6196 gt u32 %r6195 c7[0x338] (0) 1037: not %p6196 ld u32 %r6197 g[%r6167d+0xc] (0) 1038: %p6196 mov u32 %r6198 0x00000000 (0) 1039: union u32 %r6199 %r6197 %r6198 (0) 1040: shl u32 %r6205 %r6156 0x00000004 (0) 1041: add u64 %r6209d %r6205 c7[0x330] (0) 1042: add u32 %r6210 %r6205 0x00000004 (0) 1043: set u8 %p6211 gt u32 %r6210 c7[0x338] (0) 1044: not %p6211 ld u32 %r6212 g[%r6209d+0x0] (0) 1045: %p6211 mov u32 %r6213 0x00000000 (0) 1046: union u32 %r6214 %r6212 %r6213 (0) 1047: add u32 %r6219 %r6205 0x00000008 (0) 1048: set u8 %p6220 gt u32 %r6219 c7[0x338] (0) 1049: not %p6220 ld u32 %r6221 g[%r6209d+0x4] (0) 1050: %p6220 mov u32 %r6222 0x00000000 (0) 1051: union u32 %r6223 %r6221 %r6222 (0) 1052: add u32 %r6228 %r6205 0x0000000c (0) 1053: set u8 %p6229 gt u32 %r6228 c7[0x338] (0) 1054: not %p6229 ld u32 %r6230 g[%r6209d+0x8] (0) 1055: %p6229 mov u32 %r6231 0x00000000 (0) 1056: union u32 %r6232 %r6230 %r6231 (0) 1057: add u32 %r6237 %r6205 0x00000010 (0) 1058: set u8 %p6238 gt u32 %r6237 c7[0x338] (0) 1059: not %p6238 ld u32 %r6239 g[%r6209d+0xc] (0) 1060: %p6238 mov u32 %r6240 0x00000000 (0) 1061: union u32 %r6241 %r6239 %r6240 (0) 1062: neg f32 %r6242 %r6214 (0) 1063: add f32 %r6243 %r6172 %r6242 (0) 1064: neg f32 %r6244 %r6223 (0) 1065: add f32 %r6245 %r6181 %r6244 (0) 1066: neg f32 %r6246 %r6232 (0) 1067: add f32 %r6247 %r6190 %r6246 (0) 1068: neg f32 %r6248 %r6241 (0) 1069: add f32 %r6249 %r6199 %r6248 (0) 1070: mul f32 %r6250 %r6243 %r6243 (0) 1071: mad f32 %r6251 %r6245 %r6245 %r6250 (0) 1072: mad f32 %r6252 %r6247 %r6247 %r6251 (0) 1073: mad f32 %r6253 %r6249 %r6249 %r6252 (0) 1074: rsq f32 %r6255 %r6253 (0) 1075: rcp f32 %r6256 %r6255 (0) 1076: neg f32 %r6258 %r6256 (0) 1077: add f32 %r6259 %r6258 c0[0x20] (0) 1078: mul f32 %r6261 %r6259 0.350000 (0) 1079: rcp f32 %r6262 %r6256 (0) 1080: mul f32 %r6263 %r6261 %r6262 (0) 1081: mul f32 %r6264 %r6263 %r6243 (0) 1082: mul f32 %r6265 %r6263 %r6245 (0) 1083: mul f32 %r6266 %r6263 %r6247 (0) 1084: mul f32 %r6267 %r6263 %r6249 (0) 1085: not %p6169 ld u32 %r6278 g[%r6167d+0x0] (0) 1086: %p6169 mov u32 %r6279 0x00000000 (0) 1087: union u32 %r6280 %r6278 %r6279 (0) 1088: not %p6178 ld u32 %r6287 g[%r6167d+0x4] (0) 1089: %p6178 mov u32 %r6288 0x00000000 (0) 1090: union u32 %r6289 %r6287 %r6288 (0) 1091: not %p6187 ld u32 %r6296 g[%r6167d+0x8] (0) 1092: %p6187 mov u32 %r6297 0x00000000 (0) 1093: union u32 %r6298 %r6296 %r6297 (0) 1094: not %p6196 ld u32 %r6305 g[%r6167d+0xc] (0) 1095: %p6196 mov u32 %r6306 0x00000000 (0) 1096: union u32 %r6307 %r6305 %r6306 (0) 1097: add f32 %r6308 %r6280 %r6264 (0) 1098: add f32 %r6309 %r6289 %r6265 (0) 1099: add f32 %r6310 %r6298 %r6266 (0) 1100: add f32 %r6311 %r6307 %r6267 (0) 1101: not %p6169 st u32 # g[%r6167d+0x0] %r6308 (0) 1102: not %p6178 st u32 # g[%r6167d+0x4] %r6309 (0) 1103: not %p6187 st u32 # g[%r6167d+0x8] %r6310 (0) 1104: not %p6196 st u32 # g[%r6167d+0xc] %r6311 (0) 1105: not %p6211 ld u32 %r6346 g[%r6209d+0x0] (0) 1106: %p6211 mov u32 %r6347 0x00000000 (0) 1107: union u32 %r6348 %r6346 %r6347 (0) 1108: not %p6220 ld u32 %r6355 g[%r6209d+0x4] (0) 1109: %p6220 mov u32 %r6356 0x00000000 (0) 1110: union u32 %r6357 %r6355 %r6356 (0) 1111: not %p6229 ld u32 %r6364 g[%r6209d+0x8] (0) 1112: %p6229 mov u32 %r6365 0x00000000 (0) 1113: union u32 %r6366 %r6364 %r6365 (0) 1114: not %p6238 ld u32 %r6373 g[%r6209d+0xc] (0) 1115: %p6238 mov u32 %r6374 0x00000000 (0) 1116: union u32 %r6375 %r6373 %r6374 (0) 1117: neg f32 %r6376 %r6264 (0) 1118: add f32 %r6377 %r6348 %r6376 (0) 1119: neg f32 %r6378 %r6265 (0) 1120: add f32 %r6379 %r6357 %r6378 (0) 1121: neg f32 %r6380 %r6266 (0) 1122: add f32 %r6381 %r6366 %r6380 (0) 1123: neg f32 %r6382 %r6267 (0) 1124: add f32 %r6383 %r6375 %r6382 (0) 1125: not %p6211 st u32 # g[%r6209d+0x0] %r6377 (0) 1126: not %p6220 st u32 # g[%r6209d+0x4] %r6379 (0) 1127: not %p6229 st u32 # g[%r6209d+0x8] %r6381 (0) 1128: not %p6238 st u32 # g[%r6209d+0xc] %r6383 (0) 1129: membar (SUBOP:7) - # (0) 1130: bra BB:32 (0) BB:32 (2 instructions) - idom = BB:30, df = { BB:33 } -> BB:33 (forward) 1131: join (0) 1132: bra BB:33 (0) BB:33 (2 instructions) - idom = BB:29, df = { BB:34 } -> BB:34 (forward) 1133: join (0) 1134: bra BB:34 (0) BB:34 (2 instructions) - idom = BB:25, df = { BB:35 } -> BB:35 (forward) 1135: join (0) 1136: bra BB:35 (0) BB:35 (12 instructions) - idom = BB:17, df = { BB:14 } -> BB:14 (back) 1137: phi u32 %r5871 %r4929 %r4004 (0) 1138: phi u32 %r5872 %r4930 %r4005 (0) 1139: phi u32 %r5873 %r4931 %r4006 (0) 1140: phi u32 %r5874 %r4932 %r4007 (0) 1141: phi u32 %r5875 %r5148 %r4008 (0) 1142: phi u32 %r5876 %r5149 %r4009 (0) 1143: phi u32 %r5877 %r5150 %r4010 (0) 1144: phi u32 %r5878 %r5151 %r4011 (0) 1145: join (0) 1146: bar u32 # 0x00000000 0x00000000 (0) 1147: add u32 %r5880 %r4003 0x00000001 (0) 1148: cont BB:14 (0) BB:15 (2 instructions) - idom = BB:16, df = { BB:10 } -> BB:36 (tree) 1149: mov u32 %r4015 0x00000000 (0) 1150: prebreak BB:37 (0) BB:36 (4 instructions) - idom = BB:15, df = { BB:10 BB:36 } -> BB:39 (forward) -> BB:38 (tree) 1151: phi u32 %r4017 %r4659 %r4015 (0) 1152: precont BB:36 (0) 1153: set u8 %p4020 ge s32 %r4017 2 (0) 1154: not %p4020 bra BB:39 (0) BB:38 (1 instructions) - idom = BB:36, df = { BB:10 } -> BB:37 (cross) 1155: break BB:37 (0) BB:39 (20 instructions) - idom = BB:36, df = { BB:36 } -> BB:43 (forward) -> BB:40 (tree) 1156: mov u32 %r4135 0x00000002 (0) 1157: mov u32 $r0 %r2717 (0) 1158: mov u32 $r1 %r4135 (0) 1159: call abs BUILTIN:1 (0) 1160: mov u32 %r4136 $r1 (0) 1161: nop - { $r0 $r2d } (0) 1162: nop - $p0q (0) 1163: set u32 %r4137 eq %r4136 %r4017 (0) 1164: add u32 %r4139 %r2715 0x00000001 (0) 1165: mov u32 $r0 %r4139 (0) 1166: mov u32 $r1 %r4135 (0) 1167: call abs BUILTIN:1 (0) 1168: mov u32 %r4141 $r1 (0) 1169: nop - { $r0 $r2d } (0) 1170: nop - $p0q (0) 1171: set u32 %r4142 eq %r4141 %r4017 (0) 1172: and u32 %r4143 %r4137 %r4142 (0) 1173: joinat BB:43 (0) 1174: set u8 %p4144 neu u32 0x00000000 %r4143 (0) 1175: not %p4144 bra BB:43 (0) BB:40 (39 instructions) - idom = BB:39, df = { BB:43 } -> BB:42 (forward) -> BB:41 (tree) 1176: shl u32 %r4146 %r2703 0x00000004 (0) 1177: add u64 %r4150d %r4146 c7[0x330] (0) 1178: add u32 %r4151 %r4146 0x00000004 (0) 1179: set u8 %p4152 gt u32 %r4151 c7[0x338] (0) 1180: not %p4152 ld u32 %r4153 g[%r4150d+0x0] (0) 1181: %p4152 mov u32 %r4154 0x00000000 (0) 1182: union u32 %r4155 %r4153 %r4154 (0) 1183: add u32 %r4160 %r4146 0x00000008 (0) 1184: set u8 %p4161 gt u32 %r4160 c7[0x338] (0) 1185: not %p4161 ld u32 %r4162 g[%r4150d+0x4] (0) 1186: %p4161 mov u32 %r4163 0x00000000 (0) 1187: union u32 %r4164 %r4162 %r4163 (0) 1188: add u32 %r4169 %r4146 0x0000000c (0) 1189: set u8 %p4170 gt u32 %r4169 c7[0x338] (0) 1190: not %p4170 ld u32 %r4171 g[%r4150d+0x8] (0) 1191: %p4170 mov u32 %r4172 0x00000000 (0) 1192: union u32 %r4173 %r4171 %r4172 (0) 1193: add u32 %r4178 %r4146 0x00000010 (0) 1194: set u8 %p4179 gt u32 %r4178 c7[0x338] (0) 1195: not %p4179 ld u32 %r4180 g[%r4150d+0xc] (0) 1196: %p4179 mov u32 %r4181 0x00000000 (0) 1197: union u32 %r4182 %r4180 %r4181 (0) 1198: add u32 %r4188 %r2703 0x00000001 (0) 1199: ld u32 %r4189 c0[0x0] (0) 1200: add u32 %r4190 %r2703 c0[0x0] (0) 1201: add u32 %r4194 %r4188 c0[0x0] (0) 1202: mul u32 %r4197 %r4189 c0[0x0] (0) 1203: set s32 %r4198 lt %r4194 %r4197 (0) 1204: mov u32 $r0 %r4194 (0) 1205: mov u32 $r1 %r4189 (0) 1206: call abs BUILTIN:1 (0) 1207: mov u32 %r4200 $r1 (0) 1208: nop - { $r0 $r2d } (0) 1209: nop - $p0q (0) 1210: set s32 %r4201 lt %r2715 %r4200 (0) 1211: and u32 %r4202 %r4198 %r4201 (0) 1212: joinat BB:42 (0) 1213: set u8 %p4203 neu u32 0x00000000 %r4202 (0) 1214: not %p4203 bra BB:42 (0) BB:41 (213 instructions) - idom = BB:40, df = { BB:42 } -> BB:42 (forward) 1215: shl u32 %r6427 %r2703 0x00000004 (0) 1216: add u32 %r4205 %r6427 0x00000010 (0) 1217: add u64 %r4209d %r4205 c7[0x330] (0) 1218: add u32 %r4210 %r4205 0x00000004 (0) 1219: set u8 %p4211 gt u32 %r4210 c7[0x338] (0) 1220: not %p4211 ld u32 %r4212 g[%r4209d+0x0] (0) 1221: %p4211 mov u32 %r4213 0x00000000 (0) 1222: union u32 %r4214 %r4212 %r4213 (0) 1223: add u32 %r4219 %r4205 0x00000008 (0) 1224: set u8 %p4220 gt u32 %r4219 c7[0x338] (0) 1225: not %p4220 ld u32 %r4221 g[%r4209d+0x4] (0) 1226: %p4220 mov u32 %r4222 0x00000000 (0) 1227: union u32 %r4223 %r4221 %r4222 (0) 1228: add u32 %r4228 %r4205 0x0000000c (0) 1229: set u8 %p4229 gt u32 %r4228 c7[0x338] (0) 1230: not %p4229 ld u32 %r4230 g[%r4209d+0x8] (0) 1231: %p4229 mov u32 %r4231 0x00000000 (0) 1232: union u32 %r4232 %r4230 %r4231 (0) 1233: add u32 %r4237 %r4205 0x00000010 (0) 1234: set u8 %p4238 gt u32 %r4237 c7[0x338] (0) 1235: not %p4238 ld u32 %r4239 g[%r4209d+0xc] (0) 1236: %p4238 mov u32 %r4240 0x00000000 (0) 1237: union u32 %r4241 %r4239 %r4240 (0) 1238: shl u32 %r4247 %r4190 0x00000004 (0) 1239: add u64 %r4251d %r4247 c7[0x330] (0) 1240: add u32 %r4252 %r4247 0x00000004 (0) 1241: set u8 %p4253 gt u32 %r4252 c7[0x338] (0) 1242: not %p4253 ld u32 %r4254 g[%r4251d+0x0] (0) 1243: %p4253 mov u32 %r4255 0x00000000 (0) 1244: union u32 %r4256 %r4254 %r4255 (0) 1245: add u32 %r4261 %r4247 0x00000008 (0) 1246: set u8 %p4262 gt u32 %r4261 c7[0x338] (0) 1247: not %p4262 ld u32 %r4263 g[%r4251d+0x4] (0) 1248: %p4262 mov u32 %r4264 0x00000000 (0) 1249: union u32 %r4265 %r4263 %r4264 (0) 1250: add u32 %r4270 %r4247 0x0000000c (0) 1251: set u8 %p4271 gt u32 %r4270 c7[0x338] (0) 1252: not %p4271 ld u32 %r4272 g[%r4251d+0x8] (0) 1253: %p4271 mov u32 %r4273 0x00000000 (0) 1254: union u32 %r4274 %r4272 %r4273 (0) 1255: add u32 %r4279 %r4247 0x00000010 (0) 1256: set u8 %p4280 gt u32 %r4279 c7[0x338] (0) 1257: not %p4280 ld u32 %r4281 g[%r4251d+0xc] (0) 1258: %p4280 mov u32 %r4282 0x00000000 (0) 1259: union u32 %r4283 %r4281 %r4282 (0) 1260: shl u32 %r4289 %r4194 0x00000004 (0) 1261: add u64 %r4293d %r4289 c7[0x330] (0) 1262: add u32 %r4294 %r4289 0x00000004 (0) 1263: set u8 %p4295 gt u32 %r4294 c7[0x338] (0) 1264: not %p4295 ld u32 %r4296 g[%r4293d+0x0] (0) 1265: %p4295 mov u32 %r4297 0x00000000 (0) 1266: union u32 %r4298 %r4296 %r4297 (0) 1267: add u32 %r4303 %r4289 0x00000008 (0) 1268: set u8 %p4304 gt u32 %r4303 c7[0x338] (0) 1269: not %p4304 ld u32 %r4305 g[%r4293d+0x4] (0) 1270: %p4304 mov u32 %r4306 0x00000000 (0) 1271: union u32 %r4307 %r4305 %r4306 (0) 1272: add u32 %r4312 %r4289 0x0000000c (0) 1273: set u8 %p4313 gt u32 %r4312 c7[0x338] (0) 1274: not %p4313 ld u32 %r4314 g[%r4293d+0x8] (0) 1275: %p4313 mov u32 %r4315 0x00000000 (0) 1276: union u32 %r4316 %r4314 %r4315 (0) 1277: add u32 %r4321 %r4289 0x00000010 (0) 1278: set u8 %p4322 gt u32 %r4321 c7[0x338] (0) 1279: not %p4322 ld u32 %r4323 g[%r4293d+0xc] (0) 1280: %p4322 mov u32 %r4324 0x00000000 (0) 1281: union u32 %r4325 %r4323 %r4324 (0) 1282: neg f32 %r4326 %r4298 (0) 1283: add f32 %r4327 %r4155 %r4326 (0) 1284: neg f32 %r4328 %r4307 (0) 1285: add f32 %r4329 %r4164 %r4328 (0) 1286: neg f32 %r4330 %r4316 (0) 1287: add f32 %r4331 %r4173 %r4330 (0) 1288: neg f32 %r4332 %r4325 (0) 1289: add f32 %r4333 %r4182 %r4332 (0) 1290: mul f32 %r4334 %r4327 %r4327 (0) 1291: mad f32 %r4335 %r4329 %r4329 %r4334 (0) 1292: mad f32 %r4336 %r4331 %r4331 %r4335 (0) 1293: mad f32 %r4337 %r4333 %r4333 %r4336 (0) 1294: rsq f32 %r4339 %r4337 (0) 1295: rcp f32 %r4340 %r4339 (0) 1296: neg f32 %r4342 %r4340 (0) 1297: add f32 %r4343 %r4342 c0[0x30] (0) 1298: mul f32 %r4345 %r4343 0.350000 (0) 1299: rcp f32 %r4346 %r4340 (0) 1300: mul f32 %r4347 %r4345 %r4346 (0) 1301: mul f32 %r4348 %r4347 %r4327 (0) 1302: mul f32 %r4349 %r4347 %r4329 (0) 1303: mul f32 %r4350 %r4347 %r4331 (0) 1304: mul f32 %r4351 %r4347 %r4333 (0) 1305: shl u32 %r4353 %r2703 0x00000004 (0) 1306: add u64 %r4359d %r4353 c7[0x330] (0) 1307: add u32 %r4360 %r4353 0x00000004 (0) 1308: set u8 %p4361 gt u32 %r4360 c7[0x338] (0) 1309: not %p4361 ld u32 %r4362 g[%r4359d+0x0] (0) 1310: %p4361 mov u32 %r4363 0x00000000 (0) 1311: union u32 %r4364 %r4362 %r4363 (0) 1312: add u32 %r4369 %r4353 0x00000008 (0) 1313: set u8 %p4370 gt u32 %r4369 c7[0x338] (0) 1314: not %p4370 ld u32 %r4371 g[%r4359d+0x4] (0) 1315: %p4370 mov u32 %r4372 0x00000000 (0) 1316: union u32 %r4373 %r4371 %r4372 (0) 1317: add u32 %r4378 %r4353 0x0000000c (0) 1318: set u8 %p4379 gt u32 %r4378 c7[0x338] (0) 1319: not %p4379 ld u32 %r4380 g[%r4359d+0x8] (0) 1320: %p4379 mov u32 %r4381 0x00000000 (0) 1321: union u32 %r4382 %r4380 %r4381 (0) 1322: add u32 %r4387 %r4353 0x00000010 (0) 1323: set u8 %p4388 gt u32 %r4387 c7[0x338] (0) 1324: not %p4388 ld u32 %r4389 g[%r4359d+0xc] (0) 1325: %p4388 mov u32 %r4390 0x00000000 (0) 1326: union u32 %r4391 %r4389 %r4390 (0) 1327: add f32 %r4392 %r4364 %r4348 (0) 1328: add f32 %r4393 %r4373 %r4349 (0) 1329: add f32 %r4394 %r4382 %r4350 (0) 1330: add f32 %r4395 %r4391 %r4351 (0) 1331: not %p4361 st u32 # g[%r4359d+0x0] %r4392 (0) 1332: not %p4370 st u32 # g[%r4359d+0x4] %r4393 (0) 1333: not %p4379 st u32 # g[%r4359d+0x8] %r4394 (0) 1334: not %p4388 st u32 # g[%r4359d+0xc] %r4395 (0) 1335: not %p4295 ld u32 %r4430 g[%r4293d+0x0] (0) 1336: %p4295 mov u32 %r4431 0x00000000 (0) 1337: union u32 %r4432 %r4430 %r4431 (0) 1338: not %p4304 ld u32 %r4439 g[%r4293d+0x4] (0) 1339: %p4304 mov u32 %r4440 0x00000000 (0) 1340: union u32 %r4441 %r4439 %r4440 (0) 1341: not %p4313 ld u32 %r4448 g[%r4293d+0x8] (0) 1342: %p4313 mov u32 %r4449 0x00000000 (0) 1343: union u32 %r4450 %r4448 %r4449 (0) 1344: not %p4322 ld u32 %r4457 g[%r4293d+0xc] (0) 1345: %p4322 mov u32 %r4458 0x00000000 (0) 1346: union u32 %r4459 %r4457 %r4458 (0) 1347: neg f32 %r4460 %r4348 (0) 1348: add f32 %r4461 %r4432 %r4460 (0) 1349: neg f32 %r4462 %r4349 (0) 1350: add f32 %r4463 %r4441 %r4462 (0) 1351: neg f32 %r4464 %r4350 (0) 1352: add f32 %r4465 %r4450 %r4464 (0) 1353: neg f32 %r4466 %r4351 (0) 1354: add f32 %r4467 %r4459 %r4466 (0) 1355: not %p4295 st u32 # g[%r4293d+0x0] %r4461 (0) 1356: not %p4304 st u32 # g[%r4293d+0x4] %r4463 (0) 1357: not %p4313 st u32 # g[%r4293d+0x8] %r4465 (0) 1358: not %p4322 st u32 # g[%r4293d+0xc] %r4467 (0) 1359: neg f32 %r4492 %r4256 (0) 1360: add f32 %r4493 %r4214 %r4492 (0) 1361: neg f32 %r4494 %r4265 (0) 1362: add f32 %r4495 %r4223 %r4494 (0) 1363: neg f32 %r4496 %r4274 (0) 1364: add f32 %r4497 %r4232 %r4496 (0) 1365: neg f32 %r4498 %r4283 (0) 1366: add f32 %r4499 %r4241 %r4498 (0) 1367: mul f32 %r4500 %r4493 %r4493 (0) 1368: mad f32 %r4501 %r4495 %r4495 %r4500 (0) 1369: mad f32 %r4502 %r4497 %r4497 %r4501 (0) 1370: mad f32 %r4503 %r4499 %r4499 %r4502 (0) 1371: rsq f32 %r4505 %r4503 (0) 1372: rcp f32 %r4506 %r4505 (0) 1373: neg f32 %r4508 %r4506 (0) 1374: add f32 %r4509 %r4508 c0[0x30] (0) 1375: mul f32 %r4511 %r4509 0.350000 (0) 1376: rcp f32 %r4512 %r4506 (0) 1377: mul f32 %r4513 %r4511 %r4512 (0) 1378: mul f32 %r4514 %r4513 %r4493 (0) 1379: mul f32 %r4515 %r4513 %r4495 (0) 1380: mul f32 %r4516 %r4513 %r4497 (0) 1381: mul f32 %r4517 %r4513 %r4499 (0) 1382: not %p4211 ld u32 %r4528 g[%r4209d+0x0] (0) 1383: %p4211 mov u32 %r4529 0x00000000 (0) 1384: union u32 %r4530 %r4528 %r4529 (0) 1385: not %p4220 ld u32 %r4537 g[%r4209d+0x4] (0) 1386: %p4220 mov u32 %r4538 0x00000000 (0) 1387: union u32 %r4539 %r4537 %r4538 (0) 1388: not %p4229 ld u32 %r4546 g[%r4209d+0x8] (0) 1389: %p4229 mov u32 %r4547 0x00000000 (0) 1390: union u32 %r4548 %r4546 %r4547 (0) 1391: not %p4238 ld u32 %r4555 g[%r4209d+0xc] (0) 1392: %p4238 mov u32 %r4556 0x00000000 (0) 1393: union u32 %r4557 %r4555 %r4556 (0) 1394: add f32 %r4558 %r4530 %r4514 (0) 1395: add f32 %r4559 %r4539 %r4515 (0) 1396: add f32 %r4560 %r4548 %r4516 (0) 1397: add f32 %r4561 %r4557 %r4517 (0) 1398: not %p4211 st u32 # g[%r4209d+0x0] %r4558 (0) 1399: not %p4220 st u32 # g[%r4209d+0x4] %r4559 (0) 1400: not %p4229 st u32 # g[%r4209d+0x8] %r4560 (0) 1401: not %p4238 st u32 # g[%r4209d+0xc] %r4561 (0) 1402: not %p4253 ld u32 %r4596 g[%r4251d+0x0] (0) 1403: %p4253 mov u32 %r4597 0x00000000 (0) 1404: union u32 %r4598 %r4596 %r4597 (0) 1405: not %p4262 ld u32 %r4605 g[%r4251d+0x4] (0) 1406: %p4262 mov u32 %r4606 0x00000000 (0) 1407: union u32 %r4607 %r4605 %r4606 (0) 1408: not %p4271 ld u32 %r4614 g[%r4251d+0x8] (0) 1409: %p4271 mov u32 %r4615 0x00000000 (0) 1410: union u32 %r4616 %r4614 %r4615 (0) 1411: not %p4280 ld u32 %r4623 g[%r4251d+0xc] (0) 1412: %p4280 mov u32 %r4624 0x00000000 (0) 1413: union u32 %r4625 %r4623 %r4624 (0) 1414: neg f32 %r4626 %r4514 (0) 1415: add f32 %r4627 %r4598 %r4626 (0) 1416: neg f32 %r4628 %r4515 (0) 1417: add f32 %r4629 %r4607 %r4628 (0) 1418: neg f32 %r4630 %r4516 (0) 1419: add f32 %r4631 %r4616 %r4630 (0) 1420: neg f32 %r4632 %r4517 (0) 1421: add f32 %r4633 %r4625 %r4632 (0) 1422: not %p4253 st u32 # g[%r4251d+0x0] %r4627 (0) 1423: not %p4262 st u32 # g[%r4251d+0x4] %r4629 (0) 1424: not %p4271 st u32 # g[%r4251d+0x8] %r4631 (0) 1425: not %p4280 st u32 # g[%r4251d+0xc] %r4633 (0) 1426: membar (SUBOP:7) - # (0) 1427: bra BB:42 (0) BB:42 (2 instructions) - idom = BB:40, df = { BB:43 } -> BB:43 (forward) 1428: join (0) 1429: bra BB:43 (0) BB:43 (4 instructions) - idom = BB:39, df = { BB:36 } -> BB:36 (back) 1430: join (0) 1431: bar u32 # 0x00000000 0x00000000 (0) 1432: add u32 %r4659 %r4017 0x00000001 (0) 1433: cont BB:36 (0) BB:11 (6 instructions) - idom = BB:12, df = { } -> BB:51 (forward) -> BB:46 (tree) 1434: mov u32 %r3148 0x00000000 (0) 1435: ld u32 %r3154 c0[0x0] (0) 1436: add u32 %r3156 %r3154 0xffffffff (0) 1437: joinat BB:51 (0) 1438: set u8 %p3159 lt s32 %r2715 %r3156 (0) 1439: not %p3159 bra BB:51 (0) BB:46 (54 instructions) - idom = BB:11, df = { BB:51 } -> BB:48 (forward) -> BB:47 (tree) 1440: shl u32 %r6431 %r2703 0x00000004 (0) 1441: add u32 %r3163 %r6431 0x00000010 (0) 1442: add u64 %r3168d %r3163 c7[0x330] (0) 1443: add u32 %r3169 %r3163 0x00000004 (0) 1444: set u8 %p3170 gt u32 %r3169 c7[0x338] (0) 1445: not %p3170 ld u32 %r3171 g[%r3168d+0x0] (0) 1446: %p3170 mov u32 %r3172 0x00000000 (0) 1447: union u32 %r3173 %r3171 %r3172 (0) 1448: add u32 %r3178 %r3163 0x00000008 (0) 1449: set u8 %p3179 gt u32 %r3178 c7[0x338] (0) 1450: not %p3179 ld u32 %r3180 g[%r3168d+0x4] (0) 1451: %p3179 mov u32 %r3181 0x00000000 (0) 1452: union u32 %r3182 %r3180 %r3181 (0) 1453: add u32 %r3187 %r3163 0x0000000c (0) 1454: set u8 %p3188 gt u32 %r3187 c7[0x338] (0) 1455: not %p3188 ld u32 %r3189 g[%r3168d+0x8] (0) 1456: %p3188 mov u32 %r3190 0x00000000 (0) 1457: union u32 %r3191 %r3189 %r3190 (0) 1458: shl u32 %r3206 %r2703 0x00000004 (0) 1459: add u64 %r3210d %r3206 c7[0x330] (0) 1460: add u32 %r3211 %r3206 0x00000004 (0) 1461: set u8 %p3212 gt u32 %r3211 c7[0x338] (0) 1462: not %p3212 ld u32 %r3213 g[%r3210d+0x0] (0) 1463: %p3212 mov u32 %r3214 0x00000000 (0) 1464: union u32 %r3215 %r3213 %r3214 (0) 1465: add u32 %r3220 %r3206 0x00000008 (0) 1466: set u8 %p3221 gt u32 %r3220 c7[0x338] (0) 1467: not %p3221 ld u32 %r3222 g[%r3210d+0x4] (0) 1468: %p3221 mov u32 %r3223 0x00000000 (0) 1469: union u32 %r3224 %r3222 %r3223 (0) 1470: add u32 %r3229 %r3206 0x0000000c (0) 1471: set u8 %p3230 gt u32 %r3229 c7[0x338] (0) 1472: not %p3230 ld u32 %r3231 g[%r3210d+0x8] (0) 1473: %p3230 mov u32 %r3232 0x00000000 (0) 1474: union u32 %r3233 %r3231 %r3232 (0) 1475: neg f32 %r3247 %r3215 (0) 1476: add f32 %r3248 %r3173 %r3247 (0) 1477: neg f32 %r3249 %r3224 (0) 1478: add f32 %r3250 %r3182 %r3249 (0) 1479: neg f32 %r3251 %r3233 (0) 1480: add f32 %r3252 %r3191 %r3251 (0) 1481: mul f32 %r3256 %r3248 %r3248 (0) 1482: mad f32 %r3257 %r3250 %r3250 %r3256 (0) 1483: mad f32 %r3258 %r3252 %r3252 %r3257 (0) 1484: abs f32 %r3260 %r3258 (0) 1485: rsq f32 %r3261 %r3260 (0) 1486: mul f32 %r3264 %r3248 %r3261 (0) 1487: mul f32 %r3265 %r3250 %r3261 (0) 1488: mul f32 %r3266 %r3252 %r3261 (0) 1489: ld u32 %r3270 c0[0x0] (0) 1490: add u32 %r3272 %r3270 0xffffffff (0) 1491: joinat BB:48 (0) 1492: set u8 %p3275 lt s32 %r2717 %r3272 (0) 1493: not %p3275 bra BB:48 (0) BB:47 (67 instructions) - idom = BB:46, df = { BB:48 } -> BB:48 (forward) 1494: add u32 %r3277 %r2703 c0[0x0] (0) 1495: shl u32 %r3279 %r3277 0x00000004 (0) 1496: add u64 %r3284d %r3279 c7[0x330] (0) 1497: add u32 %r3285 %r3279 0x00000004 (0) 1498: set u8 %p3286 gt u32 %r3285 c7[0x338] (0) 1499: not %p3286 ld u32 %r3287 g[%r3284d+0x0] (0) 1500: %p3286 mov u32 %r3288 0x00000000 (0) 1501: union u32 %r3289 %r3287 %r3288 (0) 1502: add u32 %r3294 %r3279 0x00000008 (0) 1503: set u8 %p3295 gt u32 %r3294 c7[0x338] (0) 1504: not %p3295 ld u32 %r3296 g[%r3284d+0x4] (0) 1505: %p3295 mov u32 %r3297 0x00000000 (0) 1506: union u32 %r3298 %r3296 %r3297 (0) 1507: add u32 %r3303 %r3279 0x0000000c (0) 1508: set u8 %p3304 gt u32 %r3303 c7[0x338] (0) 1509: not %p3304 ld u32 %r3305 g[%r3284d+0x8] (0) 1510: %p3304 mov u32 %r3306 0x00000000 (0) 1511: union u32 %r3307 %r3305 %r3306 (0) 1512: shl u32 %r3322 %r2703 0x00000004 (0) 1513: add u64 %r3326d %r3322 c7[0x330] (0) 1514: add u32 %r3327 %r3322 0x00000004 (0) 1515: set u8 %p3328 gt u32 %r3327 c7[0x338] (0) 1516: not %p3328 ld u32 %r3329 g[%r3326d+0x0] (0) 1517: %p3328 mov u32 %r3330 0x00000000 (0) 1518: union u32 %r3331 %r3329 %r3330 (0) 1519: add u32 %r3336 %r3322 0x00000008 (0) 1520: set u8 %p3337 gt u32 %r3336 c7[0x338] (0) 1521: not %p3337 ld u32 %r3338 g[%r3326d+0x4] (0) 1522: %p3337 mov u32 %r3339 0x00000000 (0) 1523: union u32 %r3340 %r3338 %r3339 (0) 1524: add u32 %r3345 %r3322 0x0000000c (0) 1525: set u8 %p3346 gt u32 %r3345 c7[0x338] (0) 1526: not %p3346 ld u32 %r3347 g[%r3326d+0x8] (0) 1527: %p3346 mov u32 %r3348 0x00000000 (0) 1528: union u32 %r3349 %r3347 %r3348 (0) 1529: neg f32 %r3363 %r3331 (0) 1530: add f32 %r3364 %r3289 %r3363 (0) 1531: neg f32 %r3365 %r3340 (0) 1532: add f32 %r3366 %r3298 %r3365 (0) 1533: neg f32 %r3367 %r3349 (0) 1534: add f32 %r3368 %r3307 %r3367 (0) 1535: mul f32 %r3372 %r3364 %r3364 (0) 1536: mad f32 %r3373 %r3366 %r3366 %r3372 (0) 1537: mad f32 %r3374 %r3368 %r3368 %r3373 (0) 1538: abs f32 %r3376 %r3374 (0) 1539: rsq f32 %r3377 %r3376 (0) 1540: mul f32 %r3380 %r3364 %r3377 (0) 1541: mul f32 %r3381 %r3366 %r3377 (0) 1542: mul f32 %r3382 %r3368 %r3377 (0) 1543: mul f32 %r3386 %r3382 %r3265 (0) 1544: mul f32 %r3387 %r3380 %r3266 (0) 1545: mul f32 %r3388 %r3381 %r3264 (0) 1546: neg f32 %r3389 %r3386 (0) 1547: mad f32 %r3390 %r3381 %r3266 %r3389 (0) 1548: neg f32 %r3391 %r3387 (0) 1549: mad f32 %r3392 %r3382 %r3264 %r3391 (0) 1550: neg f32 %r3393 %r3388 (0) 1551: mad f32 %r3394 %r3380 %r3265 %r3393 (0) 1552: mul f32 %r3398 %r3390 %r3390 (0) 1553: mad f32 %r3399 %r3392 %r3392 %r3398 (0) 1554: mad f32 %r3400 %r3394 %r3394 %r3399 (0) 1555: abs f32 %r3402 %r3400 (0) 1556: rsq f32 %r3403 %r3402 (0) 1557: mul f32 %r3406 %r3390 %r3403 (0) 1558: mul f32 %r3407 %r3392 %r3403 (0) 1559: mul f32 %r3408 %r3394 %r3403 (0) 1560: bra BB:48 (0) BB:48 (7 instructions) - idom = BB:46, df = { BB:51 } -> BB:50 (forward) -> BB:49 (tree) 1561: phi u32 %r3409 %r3148 %r3406 (0) 1562: phi u32 %r3410 %r3148 %r3407 (0) 1563: phi u32 %r3411 %r3148 %r3408 (0) 1564: join (0) 1565: joinat BB:50 (0) 1566: set u8 %p3414 lt s32 0 %r2717 (0) 1567: not %p3414 bra BB:50 (0) BB:49 (68 instructions) - idom = BB:48, df = { BB:50 } -> BB:50 (forward) 1568: shl u32 %r3416 %r2703 0x00000004 (0) 1569: add u64 %r3420d %r3416 c7[0x330] (0) 1570: add u32 %r3421 %r3416 0x00000004 (0) 1571: set u8 %p3422 gt u32 %r3421 c7[0x338] (0) 1572: not %p3422 ld u32 %r3423 g[%r3420d+0x0] (0) 1573: %p3422 mov u32 %r3424 0x00000000 (0) 1574: union u32 %r3425 %r3423 %r3424 (0) 1575: add u32 %r3430 %r3416 0x00000008 (0) 1576: set u8 %p3431 gt u32 %r3430 c7[0x338] (0) 1577: not %p3431 ld u32 %r3432 g[%r3420d+0x4] (0) 1578: %p3431 mov u32 %r3433 0x00000000 (0) 1579: union u32 %r3434 %r3432 %r3433 (0) 1580: add u32 %r3439 %r3416 0x0000000c (0) 1581: set u8 %p3440 gt u32 %r3439 c7[0x338] (0) 1582: not %p3440 ld u32 %r3441 g[%r3420d+0x8] (0) 1583: %p3440 mov u32 %r3442 0x00000000 (0) 1584: union u32 %r3443 %r3441 %r3442 (0) 1585: neg s32 %r3458 c0[0x0] (0) 1586: add u32 %r3459 %r2703 %r3458 (0) 1587: shl u32 %r3462 %r3459 0x00000004 (0) 1588: add u64 %r3467d %r3462 c7[0x330] (0) 1589: add u32 %r3468 %r3462 0x00000004 (0) 1590: set u8 %p3469 gt u32 %r3468 c7[0x338] (0) 1591: not %p3469 ld u32 %r3470 g[%r3467d+0x0] (0) 1592: %p3469 mov u32 %r3471 0x00000000 (0) 1593: union u32 %r3472 %r3470 %r3471 (0) 1594: add u32 %r3477 %r3462 0x00000008 (0) 1595: set u8 %p3478 gt u32 %r3477 c7[0x338] (0) 1596: not %p3478 ld u32 %r3479 g[%r3467d+0x4] (0) 1597: %p3478 mov u32 %r3480 0x00000000 (0) 1598: union u32 %r3481 %r3479 %r3480 (0) 1599: add u32 %r3486 %r3462 0x0000000c (0) 1600: set u8 %p3487 gt u32 %r3486 c7[0x338] (0) 1601: not %p3487 ld u32 %r3488 g[%r3467d+0x8] (0) 1602: %p3487 mov u32 %r3489 0x00000000 (0) 1603: union u32 %r3490 %r3488 %r3489 (0) 1604: neg f32 %r3504 %r3472 (0) 1605: add f32 %r3505 %r3425 %r3504 (0) 1606: neg f32 %r3506 %r3481 (0) 1607: add f32 %r3507 %r3434 %r3506 (0) 1608: neg f32 %r3508 %r3490 (0) 1609: add f32 %r3509 %r3443 %r3508 (0) 1610: mul f32 %r3513 %r3505 %r3505 (0) 1611: mad f32 %r3514 %r3507 %r3507 %r3513 (0) 1612: mad f32 %r3515 %r3509 %r3509 %r3514 (0) 1613: abs f32 %r3517 %r3515 (0) 1614: rsq f32 %r3518 %r3517 (0) 1615: mul f32 %r3521 %r3505 %r3518 (0) 1616: mul f32 %r3522 %r3507 %r3518 (0) 1617: mul f32 %r3523 %r3509 %r3518 (0) 1618: mul f32 %r3527 %r3523 %r3265 (0) 1619: mul f32 %r3528 %r3521 %r3266 (0) 1620: mul f32 %r3529 %r3522 %r3264 (0) 1621: neg f32 %r3530 %r3527 (0) 1622: mad f32 %r3531 %r3522 %r3266 %r3530 (0) 1623: neg f32 %r3532 %r3528 (0) 1624: mad f32 %r3533 %r3523 %r3264 %r3532 (0) 1625: neg f32 %r3534 %r3529 (0) 1626: mad f32 %r3535 %r3521 %r3265 %r3534 (0) 1627: mul f32 %r3539 %r3531 %r3531 (0) 1628: mad f32 %r3540 %r3533 %r3533 %r3539 (0) 1629: mad f32 %r3541 %r3535 %r3535 %r3540 (0) 1630: abs f32 %r3543 %r3541 (0) 1631: rsq f32 %r3544 %r3543 (0) 1632: mad f32 %r3547 %r3531 %r3544 %r3409 (0) 1633: mad f32 %r3548 %r3533 %r3544 %r3410 (0) 1634: mad f32 %r3549 %r3535 %r3544 %r3411 (0) 1635: bra BB:50 (0) BB:50 (5 instructions) - idom = BB:48, df = { BB:51 } -> BB:51 (forward) 1636: phi u32 %r3553 %r3409 %r3547 (0) 1637: phi u32 %r3554 %r3410 %r3548 (0) 1638: phi u32 %r3555 %r3411 %r3549 (0) 1639: join (0) 1640: bra BB:51 (0) BB:51 (7 instructions) - idom = BB:11, df = { } -> BB:57 (forward) -> BB:52 (tree) 1641: phi u32 %r3556 %r3148 %r3553 (0) 1642: phi u32 %r3557 %r3148 %r3554 (0) 1643: phi u32 %r3558 %r3148 %r3555 (0) 1644: join (0) 1645: joinat BB:57 (0) 1646: set u8 %p3562 lt s32 0 %r2715 (0) 1647: not %p3562 bra BB:57 (0) BB:52 (54 instructions) - idom = BB:51, df = { BB:57 } -> BB:54 (forward) -> BB:53 (tree) 1648: shl u32 %r3564 %r2703 0x00000004 (0) 1649: add u64 %r3568d %r3564 c7[0x330] (0) 1650: add u32 %r3569 %r3564 0x00000004 (0) 1651: set u8 %p3570 gt u32 %r3569 c7[0x338] (0) 1652: not %p3570 ld u32 %r3571 g[%r3568d+0x0] (0) 1653: %p3570 mov u32 %r3572 0x00000000 (0) 1654: union u32 %r3573 %r3571 %r3572 (0) 1655: add u32 %r3578 %r3564 0x00000008 (0) 1656: set u8 %p3579 gt u32 %r3578 c7[0x338] (0) 1657: not %p3579 ld u32 %r3580 g[%r3568d+0x4] (0) 1658: %p3579 mov u32 %r3581 0x00000000 (0) 1659: union u32 %r3582 %r3580 %r3581 (0) 1660: add u32 %r3587 %r3564 0x0000000c (0) 1661: set u8 %p3588 gt u32 %r3587 c7[0x338] (0) 1662: not %p3588 ld u32 %r3589 g[%r3568d+0x8] (0) 1663: %p3588 mov u32 %r3590 0x00000000 (0) 1664: union u32 %r3591 %r3589 %r3590 (0) 1665: shl u32 %r6429 %r2703 0x00000004 (0) 1666: add u32 %r3608 %r6429 0xfffffff0 (0) 1667: add u64 %r3613d %r3608 c7[0x330] (0) 1668: add u32 %r3614 %r3608 0x00000004 (0) 1669: set u8 %p3615 gt u32 %r3614 c7[0x338] (0) 1670: not %p3615 ld u32 %r3616 g[%r3613d+0x0] (0) 1671: %p3615 mov u32 %r3617 0x00000000 (0) 1672: union u32 %r3618 %r3616 %r3617 (0) 1673: add u32 %r3623 %r3608 0x00000008 (0) 1674: set u8 %p3624 gt u32 %r3623 c7[0x338] (0) 1675: not %p3624 ld u32 %r3625 g[%r3613d+0x4] (0) 1676: %p3624 mov u32 %r3626 0x00000000 (0) 1677: union u32 %r3627 %r3625 %r3626 (0) 1678: add u32 %r3632 %r3608 0x0000000c (0) 1679: set u8 %p3633 gt u32 %r3632 c7[0x338] (0) 1680: not %p3633 ld u32 %r3634 g[%r3613d+0x8] (0) 1681: %p3633 mov u32 %r3635 0x00000000 (0) 1682: union u32 %r3636 %r3634 %r3635 (0) 1683: neg f32 %r3650 %r3618 (0) 1684: add f32 %r3651 %r3573 %r3650 (0) 1685: neg f32 %r3652 %r3627 (0) 1686: add f32 %r3653 %r3582 %r3652 (0) 1687: neg f32 %r3654 %r3636 (0) 1688: add f32 %r3655 %r3591 %r3654 (0) 1689: mul f32 %r3659 %r3651 %r3651 (0) 1690: mad f32 %r3660 %r3653 %r3653 %r3659 (0) 1691: mad f32 %r3661 %r3655 %r3655 %r3660 (0) 1692: abs f32 %r3663 %r3661 (0) 1693: rsq f32 %r3664 %r3663 (0) 1694: mul f32 %r3667 %r3651 %r3664 (0) 1695: mul f32 %r3668 %r3653 %r3664 (0) 1696: mul f32 %r3669 %r3655 %r3664 (0) 1697: ld u32 %r3673 c0[0x0] (0) 1698: add u32 %r3675 %r3673 0xffffffff (0) 1699: joinat BB:54 (0) 1700: set u8 %p3678 lt s32 %r2717 %r3675 (0) 1701: not %p3678 bra BB:54 (0) BB:53 (67 instructions) - idom = BB:52, df = { BB:54 } -> BB:54 (forward) 1702: add u32 %r3680 %r2703 c0[0x0] (0) 1703: shl u32 %r3682 %r3680 0x00000004 (0) 1704: add u64 %r3687d %r3682 c7[0x330] (0) 1705: add u32 %r3688 %r3682 0x00000004 (0) 1706: set u8 %p3689 gt u32 %r3688 c7[0x338] (0) 1707: not %p3689 ld u32 %r3690 g[%r3687d+0x0] (0) 1708: %p3689 mov u32 %r3691 0x00000000 (0) 1709: union u32 %r3692 %r3690 %r3691 (0) 1710: add u32 %r3697 %r3682 0x00000008 (0) 1711: set u8 %p3698 gt u32 %r3697 c7[0x338] (0) 1712: not %p3698 ld u32 %r3699 g[%r3687d+0x4] (0) 1713: %p3698 mov u32 %r3700 0x00000000 (0) 1714: union u32 %r3701 %r3699 %r3700 (0) 1715: add u32 %r3706 %r3682 0x0000000c (0) 1716: set u8 %p3707 gt u32 %r3706 c7[0x338] (0) 1717: not %p3707 ld u32 %r3708 g[%r3687d+0x8] (0) 1718: %p3707 mov u32 %r3709 0x00000000 (0) 1719: union u32 %r3710 %r3708 %r3709 (0) 1720: shl u32 %r3725 %r2703 0x00000004 (0) 1721: add u64 %r3729d %r3725 c7[0x330] (0) 1722: add u32 %r3730 %r3725 0x00000004 (0) 1723: set u8 %p3731 gt u32 %r3730 c7[0x338] (0) 1724: not %p3731 ld u32 %r3732 g[%r3729d+0x0] (0) 1725: %p3731 mov u32 %r3733 0x00000000 (0) 1726: union u32 %r3734 %r3732 %r3733 (0) 1727: add u32 %r3739 %r3725 0x00000008 (0) 1728: set u8 %p3740 gt u32 %r3739 c7[0x338] (0) 1729: not %p3740 ld u32 %r3741 g[%r3729d+0x4] (0) 1730: %p3740 mov u32 %r3742 0x00000000 (0) 1731: union u32 %r3743 %r3741 %r3742 (0) 1732: add u32 %r3748 %r3725 0x0000000c (0) 1733: set u8 %p3749 gt u32 %r3748 c7[0x338] (0) 1734: not %p3749 ld u32 %r3750 g[%r3729d+0x8] (0) 1735: %p3749 mov u32 %r3751 0x00000000 (0) 1736: union u32 %r3752 %r3750 %r3751 (0) 1737: neg f32 %r3766 %r3734 (0) 1738: add f32 %r3767 %r3692 %r3766 (0) 1739: neg f32 %r3768 %r3743 (0) 1740: add f32 %r3769 %r3701 %r3768 (0) 1741: neg f32 %r3770 %r3752 (0) 1742: add f32 %r3771 %r3710 %r3770 (0) 1743: mul f32 %r3775 %r3767 %r3767 (0) 1744: mad f32 %r3776 %r3769 %r3769 %r3775 (0) 1745: mad f32 %r3777 %r3771 %r3771 %r3776 (0) 1746: abs f32 %r3779 %r3777 (0) 1747: rsq f32 %r3780 %r3779 (0) 1748: mul f32 %r3783 %r3767 %r3780 (0) 1749: mul f32 %r3784 %r3769 %r3780 (0) 1750: mul f32 %r3785 %r3771 %r3780 (0) 1751: mul f32 %r3789 %r3785 %r3668 (0) 1752: mul f32 %r3790 %r3783 %r3669 (0) 1753: mul f32 %r3791 %r3784 %r3667 (0) 1754: neg f32 %r3792 %r3789 (0) 1755: mad f32 %r3793 %r3784 %r3669 %r3792 (0) 1756: neg f32 %r3794 %r3790 (0) 1757: mad f32 %r3795 %r3785 %r3667 %r3794 (0) 1758: neg f32 %r3796 %r3791 (0) 1759: mad f32 %r3797 %r3783 %r3668 %r3796 (0) 1760: mul f32 %r3801 %r3793 %r3793 (0) 1761: mad f32 %r3802 %r3795 %r3795 %r3801 (0) 1762: mad f32 %r3803 %r3797 %r3797 %r3802 (0) 1763: abs f32 %r3805 %r3803 (0) 1764: rsq f32 %r3806 %r3805 (0) 1765: mad f32 %r3809 %r3793 %r3806 %r3556 (0) 1766: mad f32 %r3810 %r3795 %r3806 %r3557 (0) 1767: mad f32 %r3811 %r3797 %r3806 %r3558 (0) 1768: bra BB:54 (0) BB:54 (7 instructions) - idom = BB:52, df = { BB:57 } -> BB:56 (forward) -> BB:55 (tree) 1769: phi u32 %r3815 %r3556 %r3809 (0) 1770: phi u32 %r3816 %r3557 %r3810 (0) 1771: phi u32 %r3817 %r3558 %r3811 (0) 1772: join (0) 1773: joinat BB:56 (0) 1774: set u8 %p3821 lt s32 0 %r2717 (0) 1775: not %p3821 bra BB:56 (0) BB:55 (68 instructions) - idom = BB:54, df = { BB:56 } -> BB:56 (forward) 1776: shl u32 %r3823 %r2703 0x00000004 (0) 1777: add u64 %r3827d %r3823 c7[0x330] (0) 1778: add u32 %r3828 %r3823 0x00000004 (0) 1779: set u8 %p3829 gt u32 %r3828 c7[0x338] (0) 1780: not %p3829 ld u32 %r3830 g[%r3827d+0x0] (0) 1781: %p3829 mov u32 %r3831 0x00000000 (0) 1782: union u32 %r3832 %r3830 %r3831 (0) 1783: add u32 %r3837 %r3823 0x00000008 (0) 1784: set u8 %p3838 gt u32 %r3837 c7[0x338] (0) 1785: not %p3838 ld u32 %r3839 g[%r3827d+0x4] (0) 1786: %p3838 mov u32 %r3840 0x00000000 (0) 1787: union u32 %r3841 %r3839 %r3840 (0) 1788: add u32 %r3846 %r3823 0x0000000c (0) 1789: set u8 %p3847 gt u32 %r3846 c7[0x338] (0) 1790: not %p3847 ld u32 %r3848 g[%r3827d+0x8] (0) 1791: %p3847 mov u32 %r3849 0x00000000 (0) 1792: union u32 %r3850 %r3848 %r3849 (0) 1793: neg s32 %r3865 c0[0x0] (0) 1794: add u32 %r3866 %r2703 %r3865 (0) 1795: shl u32 %r3869 %r3866 0x00000004 (0) 1796: add u64 %r3874d %r3869 c7[0x330] (0) 1797: add u32 %r3875 %r3869 0x00000004 (0) 1798: set u8 %p3876 gt u32 %r3875 c7[0x338] (0) 1799: not %p3876 ld u32 %r3877 g[%r3874d+0x0] (0) 1800: %p3876 mov u32 %r3878 0x00000000 (0) 1801: union u32 %r3879 %r3877 %r3878 (0) 1802: add u32 %r3884 %r3869 0x00000008 (0) 1803: set u8 %p3885 gt u32 %r3884 c7[0x338] (0) 1804: not %p3885 ld u32 %r3886 g[%r3874d+0x4] (0) 1805: %p3885 mov u32 %r3887 0x00000000 (0) 1806: union u32 %r3888 %r3886 %r3887 (0) 1807: add u32 %r3893 %r3869 0x0000000c (0) 1808: set u8 %p3894 gt u32 %r3893 c7[0x338] (0) 1809: not %p3894 ld u32 %r3895 g[%r3874d+0x8] (0) 1810: %p3894 mov u32 %r3896 0x00000000 (0) 1811: union u32 %r3897 %r3895 %r3896 (0) 1812: neg f32 %r3911 %r3879 (0) 1813: add f32 %r3912 %r3832 %r3911 (0) 1814: neg f32 %r3913 %r3888 (0) 1815: add f32 %r3914 %r3841 %r3913 (0) 1816: neg f32 %r3915 %r3897 (0) 1817: add f32 %r3916 %r3850 %r3915 (0) 1818: mul f32 %r3920 %r3912 %r3912 (0) 1819: mad f32 %r3921 %r3914 %r3914 %r3920 (0) 1820: mad f32 %r3922 %r3916 %r3916 %r3921 (0) 1821: abs f32 %r3924 %r3922 (0) 1822: rsq f32 %r3925 %r3924 (0) 1823: mul f32 %r3928 %r3912 %r3925 (0) 1824: mul f32 %r3929 %r3914 %r3925 (0) 1825: mul f32 %r3930 %r3916 %r3925 (0) 1826: mul f32 %r3934 %r3930 %r3668 (0) 1827: mul f32 %r3935 %r3928 %r3669 (0) 1828: mul f32 %r3936 %r3929 %r3667 (0) 1829: neg f32 %r3937 %r3934 (0) 1830: mad f32 %r3938 %r3929 %r3669 %r3937 (0) 1831: neg f32 %r3939 %r3935 (0) 1832: mad f32 %r3940 %r3930 %r3667 %r3939 (0) 1833: neg f32 %r3941 %r3936 (0) 1834: mad f32 %r3942 %r3928 %r3668 %r3941 (0) 1835: mul f32 %r3946 %r3938 %r3938 (0) 1836: mad f32 %r3947 %r3940 %r3940 %r3946 (0) 1837: mad f32 %r3948 %r3942 %r3942 %r3947 (0) 1838: abs f32 %r3950 %r3948 (0) 1839: rsq f32 %r3951 %r3950 (0) 1840: mad f32 %r3954 %r3938 %r3951 %r3815 (0) 1841: mad f32 %r3955 %r3940 %r3951 %r3816 (0) 1842: mad f32 %r3956 %r3942 %r3951 %r3817 (0) 1843: bra BB:56 (0) BB:56 (5 instructions) - idom = BB:54, df = { BB:57 } -> BB:57 (forward) 1844: phi u32 %r3960 %r3815 %r3954 (0) 1845: phi u32 %r3961 %r3816 %r3955 (0) 1846: phi u32 %r3962 %r3817 %r3956 (0) 1847: join (0) 1848: bra BB:57 (0) BB:57 (24 instructions) - idom = BB:51, df = { } -> BB:1 (tree) 1849: phi u32 %r3963 %r3556 %r3960 (0) 1850: phi u32 %r3964 %r3557 %r3961 (0) 1851: phi u32 %r3965 %r3558 %r3962 (0) 1852: join (0) 1853: shl u32 %r3967 %r2703 0x00000004 (0) 1854: mul f32 %r3969 %r3963 %r3963 (0) 1855: mad f32 %r3970 %r3964 %r3964 %r3969 (0) 1856: mad f32 %r3971 %r3965 %r3965 %r3970 (0) 1857: abs f32 %r3973 %r3971 (0) 1858: rsq f32 %r3974 %r3973 (0) 1859: mul f32 %r3977 %r3963 %r3974 (0) 1860: mul f32 %r3978 %r3964 %r3974 (0) 1861: mul f32 %r3979 %r3965 %r3974 (0) 1862: add u64 %r3986d %r3967 c7[0x310] (0) 1863: add u32 %r3987 %r3967 0x00000004 (0) 1864: set u8 %p3988 gt u32 %r3987 c7[0x318] (0) 1865: not %p3988 st u32 # g[%r3986d+0x0] %r3977 (0) 1866: add u32 %r3993 %r3967 0x00000008 (0) 1867: set u8 %p3994 gt u32 %r3993 c7[0x318] (0) 1868: not %p3994 st u32 # g[%r3986d+0x4] %r3978 (0) 1869: add u32 %r3999 %r3967 0x0000000c (0) 1870: set u8 %p4000 gt u32 %r3999 c7[0x318] (0) 1871: not %p4000 st u32 # g[%r3986d+0x8] %r3979 (0) 1872: membar (SUBOP:7) - # (0) BB:1 (1 instructions) - idom = BB:57, df = { } 1873: exit - # (0) BB:37 (41 instructions) - idom = BB:38, df = { BB:10 } -> BB:45 (forward) -> BB:44 (tree) 1874: shl u32 %r4022 %r2703 0x00000004 (0) 1875: add u64 %r4026d %r4022 c7[0x330] (0) 1876: add u32 %r4027 %r4022 0x00000004 (0) 1877: set u8 %p4028 gt u32 %r4027 c7[0x338] (0) 1878: not %p4028 ld u32 %r4029 g[%r4026d+0x0] (0) 1879: %p4028 mov u32 %r4030 0x00000000 (0) 1880: union u32 %r4031 %r4029 %r4030 (0) 1881: add u32 %r4036 %r4022 0x00000008 (0) 1882: set u8 %p4037 gt u32 %r4036 c7[0x338] (0) 1883: not %p4037 ld u32 %r4038 g[%r4026d+0x4] (0) 1884: %p4037 mov u32 %r4039 0x00000000 (0) 1885: union u32 %r4040 %r4038 %r4039 (0) 1886: add u32 %r4045 %r4022 0x0000000c (0) 1887: set u8 %p4046 gt u32 %r4045 c7[0x338] (0) 1888: not %p4046 ld u32 %r4047 g[%r4026d+0x8] (0) 1889: %p4046 mov u32 %r4048 0x00000000 (0) 1890: union u32 %r4049 %r4047 %r4048 (0) 1891: add u32 %r4054 %r4022 0x00000010 (0) 1892: set u8 %p4055 gt u32 %r4054 c7[0x338] (0) 1893: not %p4055 ld u32 %r4056 g[%r4026d+0xc] (0) 1894: %p4055 mov u32 %r4057 0x00000000 (0) 1895: union u32 %r4058 %r4056 %r4057 (0) 1896: neg f32 %r4060 c0[0x40] (0) 1897: add f32 %r4061 %r4031 %r4060 (0) 1898: neg f32 %r4063 c0[0x44] (0) 1899: add f32 %r4064 %r4040 %r4063 (0) 1900: neg f32 %r4066 c0[0x48] (0) 1901: add f32 %r4067 %r4049 %r4066 (0) 1902: neg f32 %r4069 c0[0x4c] (0) 1903: add f32 %r4070 %r4058 %r4069 (0) 1904: mul f32 %r4071 %r4061 %r4061 (0) 1905: mad f32 %r4072 %r4064 %r4064 %r4071 (0) 1906: mad f32 %r4073 %r4067 %r4067 %r4072 (0) 1907: mad f32 %r4074 %r4070 %r4070 %r4073 (0) 1908: rsq f32 %r4076 %r4074 (0) 1909: rcp f32 %r4077 %r4076 (0) 1910: ld u32 %r4078 c0[0x50] (0) 1911: add f32 %r4080 %r4078 0.010000 (0) 1912: joinat BB:45 (0) 1913: set u8 %p4082 lt f32 %r4077 %r4080 (0) 1914: not %p4082 bra BB:45 (0) BB:44 (32 instructions) - idom = BB:37, df = { BB:45 } -> BB:45 (forward) 1915: shl u32 %r4084 %r2703 0x00000004 (0) 1916: mul f32 %r4085 %r4061 %r4061 (0) 1917: mad f32 %r4086 %r4064 %r4064 %r4085 (0) 1918: mad f32 %r4087 %r4067 %r4067 %r4086 (0) 1919: mad f32 %r4088 %r4070 %r4070 %r4087 (0) 1920: abs f32 %r4090 %r4088 (0) 1921: rsq f32 %r4091 %r4090 (0) 1922: mul f32 %r4093 %r4061 %r4091 (0) 1923: mul f32 %r4094 %r4064 %r4091 (0) 1924: mul f32 %r4095 %r4067 %r4091 (0) 1925: mul f32 %r4096 %r4070 %r4091 (0) 1926: ld u32 %r4097 c0[0x50] (0) 1927: add f32 %r4099 %r4097 0.010000 (0) 1928: mad f32 %r4101 %r4093 %r4099 c0[0x40] (0) 1929: mad f32 %r4103 %r4094 %r4099 c0[0x44] (0) 1930: mad f32 %r4105 %r4095 %r4099 c0[0x48] (0) 1931: mad f32 %r4107 %r4096 %r4099 c0[0x4c] (0) 1932: add u64 %r4111d %r4084 c7[0x330] (0) 1933: add u32 %r4112 %r4084 0x00000004 (0) 1934: set u8 %p4113 gt u32 %r4112 c7[0x338] (0) 1935: not %p4113 st u32 # g[%r4111d+0x0] %r4101 (0) 1936: add u32 %r4118 %r4084 0x00000008 (0) 1937: set u8 %p4119 gt u32 %r4118 c7[0x338] (0) 1938: not %p4119 st u32 # g[%r4111d+0x4] %r4103 (0) 1939: add u32 %r4124 %r4084 0x0000000c (0) 1940: set u8 %p4125 gt u32 %r4124 c7[0x338] (0) 1941: not %p4125 st u32 # g[%r4111d+0x8] %r4105 (0) 1942: add u32 %r4130 %r4084 0x00000010 (0) 1943: set u8 %p4131 gt u32 %r4130 c7[0x338] (0) 1944: not %p4131 st u32 # g[%r4111d+0xc] %r4107 (0) 1945: membar (SUBOP:7) - # (0) 1946: bra BB:45 (0) BB:45 (4 instructions) - idom = BB:37, df = { BB:10 } -> BB:10 (back) 1947: join (0) 1948: bar u32 # 0x00000000 0x00000000 (0) 1949: add u32 %r4133 %r3136 0x00000001 (0) 1950: cont BB:10 (0) MAIN:-1 () BB:0 (51 instructions) - df = { } -> BB:8 (tree) -> BB:2 (tree) 0: rdsv u32 $r0 sv[CTAID:0] (8) 1: mov u32 $r1 0x00000400 (8) 2: rdsv u32 $r2 sv[TID:0] (8) 3: mad u32 $r8 $r0 $r1 $r2 (8) 4: ld u32 $r4 c0[0x0] (8) 5: mov u32 $r0 $r8 (8) 6: mov u32 $r1 $r4 (8) 7: call abs BUILTIN:1 (8) 8: mov u32 $r10 $r1 (8) 9: mov u32 $r0 $r8 (8) 10: mov u32 $r1 $r4 (8) 11: call abs BUILTIN:1 (8) 12: mov u32 $r9 $r0 (8) 13: shl u32 $r2 $r8 0x00000004 (8) 14: add u32 { $r0 $c0 } $r2 c7[0x320] (8) 15: add u32 $r1 $r255 c7[0x324] $c0 (8) 16: add u32 $r3 $r2 0x00000004 (8) 17: set u8 $p0 gt u32 $r3 c7[0x328] (8) 18: not $p0 ld u32 $r3 g[$r0d+0x0] (8) 19: $p0 mov u32 $r3 0x00000000 (8) 20: add u32 $r4 $r2 0x00000008 (8) 21: set u8 $p0 gt u32 $r4 c7[0x328] (8) 22: not $p0 ld u32 $r4 g[$r0d+0x4] (8) 23: $p0 mov u32 $r4 0x00000000 (8) 24: add u32 $r5 $r2 0x0000000c (8) 25: set u8 $p0 gt u32 $r5 c7[0x328] (8) 26: not $p0 ld u32 $r5 g[$r0d+0x8] (8) 27: $p0 mov u32 $r5 0x00000000 (8) 28: add u32 $r2 $r2 0x00000010 (8) 29: set u8 $p0 gt u32 $r2 c7[0x328] (8) 30: not $p0 ld u32 $r0 g[$r0d+0xc] (8) 31: $p0 mov u32 $r0 0x00000000 (8) 32: neg f32 $r1 c0[0x40] (8) 33: add f32 $r1 $r3 $r1 (8) 34: neg f32 $r2 c0[0x44] (8) 35: add f32 $r2 $r4 $r2 (8) 36: neg f32 $r3 c0[0x48] (8) 37: add f32 $r3 $r5 $r3 (8) 38: neg f32 $r4 c0[0x4c] (8) 39: add f32 $r0 $r0 $r4 (8) 40: mul f32 $r4 $r1 $r1 (8) 41: mad f32 $r4 $r2 $r2 $r4 (8) 42: mad f32 $r4 $r3 $r3 $r4 (8) 43: mad f32 $r4 $r0 $r0 $r4 (8) 44: rsq f32 $r4 $r4 (8) 45: rcp f32 $r4 $r4 (8) 46: ld u32 $r5 c0[0x50] (8) 47: add f32 $r5 $r5 0.010000 (8) 48: joinat BB:9 (8) 49: set u8 $p0 ge f32 $r5 $r4 (8) 50: not $p0 bra BB:8 (8) BB:2 (14 instructions) - idom = BB:0, df = { BB:9 } -> BB:73 (tree) -> BB:3 (tree) 51: mov u32 $r5 0x00000000 (8) 52: mul f32 $r4 $r1 $r1 (8) 53: mad f32 $r4 $r2 $r2 $r4 (8) 54: mad f32 $r4 $r3 $r3 $r4 (8) 55: mad f32 $r0 $r0 $r0 $r4 (8) 56: abs f32 $r0 $r0 (8) 57: rsq f32 $r0 $r0 (8) 58: mul f32 $r1 $r1 $r0 (8) 59: mul f32 $r2 $r2 $r0 (8) 60: mul f32 $r0 $r3 $r0 (8) 61: max f32 $r3 $r2 $r255 (8) 62: joinat BB:7 (8) 63: set u8 $p0 neu f32 $r3 1.000000 (8) 64: not $p0 bra BB:73 (8) BB:3 (6 instructions) - idom = BB:2, df = { BB:7 } -> BB:5 (tree) -> BB:4 (tree) 65: mul f32 $r4 $r1 $r1 (8) 66: mad f32 $r4 $r2 $r2 $r4 (8) 67: mad f32 $r4 $r0 $r0 $r4 (8) 68: joinat BB:6 (8) 69: set u8 $p0 eq f32 $r4 $r255 (8) 70: not $p0 bra BB:5 (8) BB:4 (4 instructions) - idom = BB:3, df = { BB:6 } -> BB:6 (forward) 71: mov u32 $r2 0x00000000 (8) 72: mov u32 $r0 $r2 (8) 73: mov u32 $r1 $r2 (8) 74: join BB:6 (8) BB:5 (10 instructions) - idom = BB:3, df = { BB:6 } -> BB:6 (forward) 75: rcp f32 $r4 $r4 (8) 76: mul f32 $r4 $r2 $r4 (8) 77: mul f32 $r1 $r1 $r4 (8) 78: mul f32 $r2 $r2 $r4 (8) 79: mul f32 $r4 $r0 $r4 (8) 80: neg f32 $r0 $r1 (8) 81: neg f32 $r1 $r2 (8) 82: add f32 $r1 $r1 1.000000 (8) 83: neg f32 $r2 $r4 (8) 84: join BB:6 (8) BB:6 (9 instructions) - idom = BB:3, df = { BB:7 } -> BB:7 (forward) 85: mul f32 $r4 $r0 $r0 (8) 86: mad f32 $r4 $r1 $r1 $r4 (8) 87: mad f32 $r4 $r2 $r2 $r4 (8) 88: abs f32 $r4 $r4 (8) 89: rsq f32 $r4 $r4 (8) 90: mul f32 $r0 $r0 $r4 (8) 91: mul f32 $r1 $r1 $r4 (8) 92: mul f32 $r5 $r2 $r4 (8) 93: join BB:7 (8) BB:73 (3 instructions) - df = { } -> BB:7 (forward) 94: mov u32 $r0 $r5 (8) 95: mov u32 $r1 $r5 (8) 96: join BB:7 (8) BB:7 (39 instructions) - idom = BB:2, df = { BB:9 } -> BB:9 (forward) 97: neg f32 $r0 $r0 (8) 98: neg f32 $r1 $r1 (8) 99: neg f32 $r2 $r5 (8) 100: set f32 $r4 gt $r3 $r255 (8) 101: set f32 $r5 lt $r3 $r255 (8) 102: sub f32 $r4 $r4 $r5 (8) 103: abs f32 $r5 $r3 (8) 104: neg f32 $r6 $r5 (8) 105: add f32 $r6 $r6 1.000000 (8) 106: rsq f32 $r6 $r6 (8) 107: rcp f32 $r6 $r6 (8) 108: mov u32 $r7 0xbcc19a5f (8) 109: mov u32 $r12 0x3da68d87 (8) 110: mad f32 $r7 $r5 $r7 $r12 (8) 111: mov u32 $r12 0xbe5bc094 (8) 112: mad f32 $r7 $r5 $r7 $r12 (8) 113: mov u32 $r12 0x3fc90fdb (8) 114: mad f32 $r5 $r5 $r7 $r12 (8) 115: mul f32 $r5 $r6 $r5 (8) 116: neg f32 $r5 $r5 (8) 117: add f32 $r5 $r5 1.570796 (8) 118: mul f32 $r4 $r4 $r5 (8) 119: neg f32 $r4 $r4 (8) 120: add f32 $r4 $r4 1.570796 (8) 121: presin f32 $r4 $r4 (8) 122: sin f32 $r4 $r4 (8) 123: mul f32 $r4 $r4 0.200000 (8) 124: mul f32 $r3 $r3 0.200000 (8) 125: mul f32 $r5 $r3 $r0 (8) 126: mul f32 $r6 $r3 $r1 (8) 127: mul f32 $r3 $r3 $r2 (8) 128: neg f32 $r5 $r5 (8) 129: mad f32 $r5 $r4 $r0 $r5 (8) 130: neg f32 $r0 $r6 (8) 131: mad f32 $r6 $r4 $r1 $r0 (8) 132: neg f32 $r0 $r3 (8) 133: mad f32 $r2 $r4 $r2 $r0 (8) 134: mov f32 $r3 -0.000000 (8) 135: join BB:9 (8) BB:8 (5 instructions) - idom = BB:0, df = { BB:9 } -> BB:9 (forward) 136: mov f32 $r3 0.000000 (8) 137: mov f32 $r6 -0.200000 (8) 138: mov u32 $r5 $r3 (8) 139: mov u32 $r2 $r3 (8) 140: join BB:9 (8) BB:9 (72 instructions) - idom = BB:0, df = { } -> BB:10 (tree) 141: shl u32 $r4 $r8 0x00000004 (8) 142: add u32 { $r0 $c0 } $r4 c7[0x320] (8) 143: add u32 $r1 $r255 c7[0x324] $c0 (8) 144: add u32 $r7 $r4 0x00000004 (8) 145: set u8 $p0 gt u32 $r7 c7[0x328] (8) 146: not $p0 ld u32 $r12 g[$r0d+0x0] (8) 147: $p0 mov u32 $r12 0x00000000 (8) 148: add u32 $r13 $r4 0x00000008 (8) 149: set u8 $p0 gt u32 $r13 c7[0x328] (8) 150: not $p0 ld u32 $r14 g[$r0d+0x4] (8) 151: $p0 mov u32 $r14 0x00000000 (8) 152: add u32 $r15 $r4 0x0000000c (8) 153: set u8 $p0 gt u32 $r15 c7[0x328] (8) 154: not $p0 ld u32 $r16 g[$r0d+0x8] (8) 155: $p0 mov u32 $r16 0x00000000 (8) 156: add u32 $r17 $r4 0x00000010 (8) 157: set u8 $p0 gt u32 $r17 c7[0x328] (8) 158: not $p0 ld u32 $r18 g[$r0d+0xc] (8) 159: $p0 mov u32 $r18 0x00000000 (8) 160: add u32 { $r0 $c0 } $r4 c7[0x300] (8) 161: add u32 $r1 $r255 c7[0x304] $c0 (8) 162: set u8 $p0 gt u32 $r7 c7[0x308] (8) 163: not $p0 ld u32 $r19 g[$r0d+0x0] (8) 164: $p0 mov u32 $r19 0x00000000 (8) 165: set u8 $p0 gt u32 $r13 c7[0x308] (8) 166: not $p0 ld u32 $r20 g[$r0d+0x4] (8) 167: $p0 mov u32 $r20 0x00000000 (8) 168: set u8 $p0 gt u32 $r15 c7[0x308] (8) 169: not $p0 ld u32 $r21 g[$r0d+0x8] (8) 170: $p0 mov u32 $r21 0x00000000 (8) 171: set u8 $p0 gt u32 $r17 c7[0x308] (8) 172: not $p0 ld u32 $r0 g[$r0d+0xc] (8) 173: $p0 mov u32 $r0 0x00000000 (8) 174: mul f32 $r1 $r5 10.000000 (8) 175: mul f32 $r5 $r6 10.000000 (8) 176: mul f32 $r2 $r2 10.000000 (8) 177: mul f32 $r3 $r3 10.000000 (8) 178: ld u32 $r6 c0[0x10] (8) 179: mul f32 $r6 $r6 c0[0x10] (8) 180: neg f32 $r19 $r19 (8) 181: mad f32 $r12 $r12 2.000000 $r19 (8) 182: neg f32 $r19 $r20 (8) 183: mad f32 $r14 $r14 2.000000 $r19 (8) 184: neg f32 $r19 $r21 (8) 185: mad f32 $r16 $r16 2.000000 $r19 (8) 186: neg f32 $r0 $r0 (8) 187: mad f32 $r0 $r18 2.000000 $r0 (8) 188: mad f32 $r12 $r1 $r6 $r12 (8) 189: mad f32 $r5 $r5 $r6 $r14 (8) 190: mad f32 $r2 $r2 $r6 $r16 (8) 191: mad f32 $r3 $r3 $r6 $r0 (8) 192: add u32 { $r0 $c0 } $r4 c7[0x330] (8) 193: add u32 $r1 $r255 c7[0x334] $c0 (8) 194: set u8 $p0 gt u32 $r7 c7[0x338] (8) 195: not $p0 st u32 # g[$r0d+0x0] $r12 (8) 196: set u8 $p0 gt u32 $r13 c7[0x338] (8) 197: not $p0 st u32 # g[$r0d+0x4] $r5 (8) 198: set u8 $p0 gt u32 $r15 c7[0x338] (8) 199: not $p0 st u32 # g[$r0d+0x8] $r2 (8) 200: set u8 $p0 gt u32 $r17 c7[0x338] (8) 201: not $p0 st u32 # g[$r0d+0xc] $r3 (8) 202: membar (SUBOP:7) - # (8) 203: bar u32 # $r255 $r255 (8) 204: mov u32 $r12 0x00000000 (8) 205: prebreak BB:11 (8) 206: mov u32 $r13 $r11 (8) 207: mov u32 $r14 $r11 (8) 208: mov u32 $r15 $r11 (8) 209: mov u32 $r16 $r11 (8) 210: mov u32 $r17 $r11 (8) 211: mov u32 $r18 $r11 (8) 212: mov u32 $r19 $r11 (8) BB:10 (2 instructions) - idom = BB:9, df = { BB:10 } -> BB:13 (forward) -> BB:12 (tree) 213: set u8 $p0 ge s32 $r12 4 (8) 214: not $p0 bra BB:13 (8) BB:12 (1 instructions) - idom = BB:10, df = { } -> BB:11 (cross) 215: break BB:11 (8) BB:13 (2 instructions) - idom = BB:10, df = { BB:10 } -> BB:14 (tree) 216: mov u32 $r20 0x00000000 (8) 217: prebreak BB:15 (8) BB:14 (2 instructions) - idom = BB:13, df = { BB:10 BB:14 } -> BB:17 (forward) -> BB:16 (tree) 218: set u8 $p0 ge s32 $r20 2 (8) 219: not $p0 bra BB:17 (8) BB:16 (1 instructions) - idom = BB:14, df = { BB:10 } -> BB:15 (cross) 220: break BB:15 (8) BB:17 (13 instructions) - idom = BB:14, df = { BB:14 } -> BB:25 (tree) -> BB:18 (tree) 221: mov u32 $r4 0x00000002 (8) 222: mov u32 $r0 $r9 (8) 223: mov u32 $r1 $r4 (8) 224: call abs BUILTIN:1 (8) 225: set u32 $r5 eq $r1 $r20 (8) 226: mov u32 $r0 $r10 (8) 227: mov u32 $r1 $r4 (8) 228: call abs BUILTIN:1 (8) 229: set u32 $r0 eq $r1 $r20 (8) 230: and u32 $r0 $r5 $r0 (8) 231: joinat BB:35 (8) 232: set u8 $p0 neu u32 $r255 $r0 (8) 233: not $p0 bra BB:25 (8) BB:18 (25 instructions) - idom = BB:17, df = { BB:35 } -> BB:61 (tree) -> BB:19 (tree) 234: shl u32 $r2 $r8 0x00000004 (8) 235: add u32 { $r0 $c0 } $r2 c7[0x330] (8) 236: add u32 $r1 $r255 c7[0x334] $c0 (8) 237: add u32 $r3 $r2 0x00000004 (8) 238: set u8 $p0 gt u32 $r3 c7[0x338] (8) 239: not $p0 ld u32 $r6 g[$r0d+0x0] (8) 240: $p0 mov u32 $r6 0x00000000 (8) 241: add u32 $r3 $r2 0x00000008 (8) 242: set u8 $p0 gt u32 $r3 c7[0x338] (8) 243: not $p0 ld u32 $r7 g[$r0d+0x4] (8) 244: $p0 mov u32 $r7 0x00000000 (8) 245: add u32 $r3 $r2 0x0000000c (8) 246: set u8 $p0 gt u32 $r3 c7[0x338] (8) 247: not $p0 ld u32 $r21 g[$r0d+0x8] (8) 248: $p0 mov u32 $r21 0x00000000 (8) 249: add u32 $r2 $r2 0x00000010 (8) 250: set u8 $p0 gt u32 $r2 c7[0x338] (8) 251: not $p0 ld u32 $r22 g[$r0d+0xc] (8) 252: $p0 mov u32 $r22 0x00000000 (8) 253: add u32 $r0 $r8 0x00000001 (8) 254: ld u32 $r1 c0[0x0] (8) 255: call abs BUILTIN:1 (8) 256: joinat BB:20 (8) 257: set u8 $p0 lt s32 $r10 $r1 (8) 258: not $p0 bra BB:61 (8) BB:19 (98 instructions) - idom = BB:18, df = { BB:20 } -> BB:20 (forward) 259: shl u32 $r0 $r8 0x00000004 (8) 260: add u32 $r2 $r0 0x00000010 (8) 261: add u32 { $r0 $c0 } $r2 c7[0x330] (8) 262: add u32 $r1 $r255 c7[0x334] $c0 (8) 263: add u32 $r3 $r2 0x00000004 (8) 264: set u8 $p0 gt u32 $r3 c7[0x338] (8) 265: cvt u8 $r29 $p0 (8) 266: cvt u8 $p0 $r29 (8) 267: not $p0 ld u32 $r4 g[$r0d+0x0] (8) 268: $p0 mov u32 $r4 0x00000000 (8) 269: add u32 $r3 $r2 0x00000008 (8) 270: set u8 $p0 gt u32 $r3 c7[0x338] (8) 271: not $p0 ld u32 $r5 g[$r0d+0x4] (8) 272: $p0 mov u32 $r5 0x00000000 (8) 273: add u32 $r3 $r2 0x0000000c (8) 274: set u8 $p1 gt u32 $r3 c7[0x338] (8) 275: not $p1 ld u32 $r15 g[$r0d+0x8] (8) 276: $p1 mov u32 $r15 0x00000000 (8) 277: add u32 $r2 $r2 0x00000010 (8) 278: set u8 $p2 gt u32 $r2 c7[0x338] (8) 279: not $p2 ld u32 $r16 g[$r0d+0xc] (8) 280: $p2 mov u32 $r16 0x00000000 (8) 281: neg f32 $r2 $r4 (8) 282: add f32 $r2 $r6 $r2 (8) 283: neg f32 $r3 $r5 (8) 284: add f32 $r3 $r7 $r3 (8) 285: neg f32 $r13 $r15 (8) 286: add f32 $r13 $r21 $r13 (8) 287: neg f32 $r14 $r16 (8) 288: add f32 $r14 $r22 $r14 (8) 289: mul f32 $r23 $r2 $r2 (8) 290: mad f32 $r23 $r3 $r3 $r23 (8) 291: mad f32 $r23 $r13 $r13 $r23 (8) 292: mad f32 $r23 $r14 $r14 $r23 (8) 293: rsq f32 $r23 $r23 (8) 294: rcp f32 $r23 $r23 (8) 295: neg f32 $r24 $r23 (8) 296: add f32 $r24 $r24 c0[0x20] (8) 297: mul f32 $r24 $r24 0.350000 (8) 298: rcp f32 $r23 $r23 (8) 299: mul f32 $r23 $r24 $r23 (8) 300: mul f32 $r24 $r23 $r2 (8) 301: mul f32 $r25 $r23 $r3 (8) 302: mul f32 $r13 $r23 $r13 (8) 303: mul f32 $r14 $r23 $r14 (8) 304: shl u32 $r23 $r8 0x00000004 (8) 305: add u32 { $r2 $c0 } $r23 c7[0x330] (8) 306: add u32 $r3 $r255 c7[0x334] $c0 (8) 307: add u32 $r26 $r23 0x00000004 (8) 308: set u8 $p3 gt u32 $r26 c7[0x338] (8) 309: not $p3 ld u32 $r26 g[$r2d+0x0] (8) 310: $p3 mov u32 $r26 0x00000000 (8) 311: add u32 $r27 $r23 0x00000008 (8) 312: set u8 $p4 gt u32 $r27 c7[0x338] (8) 313: not $p4 ld u32 $r27 g[$r2d+0x4] (8) 314: $p4 mov u32 $r27 0x00000000 (8) 315: add u32 $r28 $r23 0x0000000c (8) 316: set u8 $p5 gt u32 $r28 c7[0x338] (8) 317: not $p5 ld u32 $r28 g[$r2d+0x8] (8) 318: $p5 mov u32 $r28 0x00000000 (8) 319: add u32 $r23 $r23 0x00000010 (8) 320: set u8 $p6 gt u32 $r23 c7[0x338] (8) 321: not $p6 ld u32 $r23 g[$r2d+0xc] (8) 322: $p6 mov u32 $r23 0x00000000 (8) 323: add f32 $r26 $r26 $r24 (8) 324: add f32 $r27 $r27 $r25 (8) 325: add f32 $r28 $r28 $r13 (8) 326: add f32 $r23 $r23 $r14 (8) 327: not $p3 st u32 # g[$r2d+0x0] $r26 (8) 328: not $p4 st u32 # g[$r2d+0x4] $r27 (8) 329: not $p5 st u32 # g[$r2d+0x8] $r28 (8) 330: not $p6 st u32 # g[$r2d+0xc] $r23 (8) 331: cvt u8 $p3 $r29 (8) 332: not $p3 ld u32 $r2 g[$r0d+0x0] (8) 333: $p3 mov u32 $r2 0x00000000 (8) 334: not $p0 ld u32 $r3 g[$r0d+0x4] (8) 335: $p0 mov u32 $r3 0x00000000 (8) 336: not $p1 ld u32 $r23 g[$r0d+0x8] (8) 337: $p1 mov u32 $r23 0x00000000 (8) 338: not $p2 ld u32 $r26 g[$r0d+0xc] (8) 339: $p2 mov u32 $r26 0x00000000 (8) 340: neg f32 $r24 $r24 (8) 341: add f32 $r2 $r2 $r24 (8) 342: neg f32 $r24 $r25 (8) 343: add f32 $r3 $r3 $r24 (8) 344: neg f32 $r13 $r13 (8) 345: add f32 $r13 $r23 $r13 (8) 346: neg f32 $r14 $r14 (8) 347: add f32 $r14 $r26 $r14 (8) 348: cvt u8 $p3 $r29 (8) 349: not $p3 st u32 # g[$r0d+0x0] $r2 (8) 350: not $p0 st u32 # g[$r0d+0x4] $r3 (8) 351: not $p1 st u32 # g[$r0d+0x8] $r13 (8) 352: not $p2 st u32 # g[$r0d+0xc] $r14 (8) 353: membar (SUBOP:7) - # (8) 354: mov u32 $r13 $r4 (8) 355: mov u32 $r14 $r5 (8) 356: join BB:20 (8) BB:61 (1 instructions) - df = { } -> BB:20 (forward) 357: join BB:20 (8) BB:20 (6 instructions) - idom = BB:18, df = { BB:35 } -> BB:62 (tree) -> BB:21 (tree) 358: ld u32 $r0 c0[0x0] (8) 359: add u32 $r4 $r8 c0[0x0] (8) 360: mul u32 $r0 $r0 c0[0x0] (8) 361: joinat BB:22 (8) 362: set u8 $p0 lt s32 $r4 $r0 (8) 363: not $p0 bra BB:62 (8) BB:21 (98 instructions) - idom = BB:20, df = { BB:22 } -> BB:22 (forward) 364: shl u32 $r2 $r4 0x00000004 (8) 365: add u32 { $r0 $c0 } $r2 c7[0x330] (8) 366: add u32 $r1 $r255 c7[0x334] $c0 (8) 367: add u32 $r3 $r2 0x00000004 (8) 368: set u8 $p0 gt u32 $r3 c7[0x338] (8) 369: cvt u8 $r30 $p0 (8) 370: cvt u8 $p0 $r30 (8) 371: not $p0 ld u32 $r5 g[$r0d+0x0] (8) 372: $p0 mov u32 $r5 0x00000000 (8) 373: add u32 $r3 $r2 0x00000008 (8) 374: set u8 $p0 gt u32 $r3 c7[0x338] (8) 375: not $p0 ld u32 $r11 g[$r0d+0x4] (8) 376: $p0 mov u32 $r11 0x00000000 (8) 377: add u32 $r3 $r2 0x0000000c (8) 378: set u8 $p1 gt u32 $r3 c7[0x338] (8) 379: not $p1 ld u32 $r19 g[$r0d+0x8] (8) 380: $p1 mov u32 $r19 0x00000000 (8) 381: add u32 $r2 $r2 0x00000010 (8) 382: set u8 $p2 gt u32 $r2 c7[0x338] (8) 383: not $p2 ld u32 $r23 g[$r0d+0xc] (8) 384: $p2 mov u32 $r23 0x00000000 (8) 385: neg f32 $r2 $r5 (8) 386: add f32 $r2 $r6 $r2 (8) 387: neg f32 $r3 $r11 (8) 388: add f32 $r3 $r7 $r3 (8) 389: neg f32 $r17 $r19 (8) 390: add f32 $r17 $r21 $r17 (8) 391: neg f32 $r18 $r23 (8) 392: add f32 $r18 $r22 $r18 (8) 393: mul f32 $r24 $r2 $r2 (8) 394: mad f32 $r24 $r3 $r3 $r24 (8) 395: mad f32 $r24 $r17 $r17 $r24 (8) 396: mad f32 $r24 $r18 $r18 $r24 (8) 397: rsq f32 $r24 $r24 (8) 398: rcp f32 $r24 $r24 (8) 399: neg f32 $r25 $r24 (8) 400: add f32 $r25 $r25 c0[0x20] (8) 401: mul f32 $r25 $r25 0.350000 (8) 402: rcp f32 $r24 $r24 (8) 403: mul f32 $r24 $r25 $r24 (8) 404: mul f32 $r25 $r24 $r2 (8) 405: mul f32 $r26 $r24 $r3 (8) 406: mul f32 $r17 $r24 $r17 (8) 407: mul f32 $r18 $r24 $r18 (8) 408: shl u32 $r24 $r8 0x00000004 (8) 409: add u32 { $r2 $c0 } $r24 c7[0x330] (8) 410: add u32 $r3 $r255 c7[0x334] $c0 (8) 411: add u32 $r27 $r24 0x00000004 (8) 412: set u8 $p3 gt u32 $r27 c7[0x338] (8) 413: not $p3 ld u32 $r27 g[$r2d+0x0] (8) 414: $p3 mov u32 $r27 0x00000000 (8) 415: add u32 $r28 $r24 0x00000008 (8) 416: set u8 $p4 gt u32 $r28 c7[0x338] (8) 417: not $p4 ld u32 $r28 g[$r2d+0x4] (8) 418: $p4 mov u32 $r28 0x00000000 (8) 419: add u32 $r29 $r24 0x0000000c (8) 420: set u8 $p5 gt u32 $r29 c7[0x338] (8) 421: not $p5 ld u32 $r29 g[$r2d+0x8] (8) 422: $p5 mov u32 $r29 0x00000000 (8) 423: add u32 $r24 $r24 0x00000010 (8) 424: set u8 $p6 gt u32 $r24 c7[0x338] (8) 425: not $p6 ld u32 $r24 g[$r2d+0xc] (8) 426: $p6 mov u32 $r24 0x00000000 (8) 427: add f32 $r27 $r27 $r25 (8) 428: add f32 $r28 $r28 $r26 (8) 429: add f32 $r29 $r29 $r17 (8) 430: add f32 $r24 $r24 $r18 (8) 431: not $p3 st u32 # g[$r2d+0x0] $r27 (8) 432: not $p4 st u32 # g[$r2d+0x4] $r28 (8) 433: not $p5 st u32 # g[$r2d+0x8] $r29 (8) 434: not $p6 st u32 # g[$r2d+0xc] $r24 (8) 435: cvt u8 $p3 $r30 (8) 436: not $p3 ld u32 $r2 g[$r0d+0x0] (8) 437: $p3 mov u32 $r2 0x00000000 (8) 438: not $p0 ld u32 $r3 g[$r0d+0x4] (8) 439: $p0 mov u32 $r3 0x00000000 (8) 440: not $p1 ld u32 $r24 g[$r0d+0x8] (8) 441: $p1 mov u32 $r24 0x00000000 (8) 442: not $p2 ld u32 $r27 g[$r0d+0xc] (8) 443: $p2 mov u32 $r27 0x00000000 (8) 444: neg f32 $r25 $r25 (8) 445: add f32 $r2 $r2 $r25 (8) 446: neg f32 $r25 $r26 (8) 447: add f32 $r3 $r3 $r25 (8) 448: neg f32 $r17 $r17 (8) 449: add f32 $r17 $r24 $r17 (8) 450: neg f32 $r18 $r18 (8) 451: add f32 $r18 $r27 $r18 (8) 452: cvt u8 $p3 $r30 (8) 453: not $p3 st u32 # g[$r0d+0x0] $r2 (8) 454: not $p0 st u32 # g[$r0d+0x4] $r3 (8) 455: not $p1 st u32 # g[$r0d+0x8] $r17 (8) 456: not $p2 st u32 # g[$r0d+0xc] $r18 (8) 457: membar (SUBOP:7) - # (8) 458: mov u32 $r17 $r5 (8) 459: mov u32 $r18 $r11 (8) 460: mov u32 $r11 $r23 (8) 461: join BB:22 (8) BB:62 (1 instructions) - df = { } -> BB:22 (forward) 462: join BB:22 (8) BB:22 (12 instructions) - idom = BB:20, df = { BB:35 } -> BB:63 (tree) -> BB:23 (tree) 463: add u32 $r0 $r8 0x00000001 (8) 464: ld u32 $r1 c0[0x0] (8) 465: add u32 $r5 $r0 c0[0x0] (8) 466: mul u32 $r0 $r1 c0[0x0] (8) 467: set s32 $r23 lt $r5 $r0 (8) 468: mov u32 $r0 $r5 (8) 469: call abs BUILTIN:1 (8) 470: set s32 $r0 lt $r10 $r1 (8) 471: and u32 $r0 $r23 $r0 (8) 472: joinat BB:24 (8) 473: set u8 $p0 neu u32 $r255 $r0 (8) 474: not $p0 bra BB:63 (8) BB:23 (331 instructions) - idom = BB:22, df = { BB:24 } -> BB:24 (forward) 475: shl u32 $r2 $r5 0x00000004 (8) 476: add u32 { $r0 $c0 } $r2 c7[0x330] (8) 477: add u32 $r1 $r255 c7[0x334] $c0 (8) 478: add u32 $r3 $r2 0x00000004 (8) 479: set u8 $p0 gt u32 $r3 c7[0x338] (8) 480: not $p0 ld u32 $r3 g[$r0d+0x0] (8) 481: $p0 mov u32 $r3 0x00000000 (8) 482: add u32 $r5 $r2 0x00000008 (8) 483: set u8 $p1 gt u32 $r5 c7[0x338] (8) 484: not $p1 ld u32 $r5 g[$r0d+0x4] (8) 485: $p1 mov u32 $r5 0x00000000 (8) 486: add u32 $r23 $r2 0x0000000c (8) 487: set u8 $p2 gt u32 $r23 c7[0x338] (8) 488: not $p2 ld u32 $r23 g[$r0d+0x8] (8) 489: $p2 mov u32 $r23 0x00000000 (8) 490: add u32 $r2 $r2 0x00000010 (8) 491: set u8 $p3 gt u32 $r2 c7[0x338] (8) 492: not $p3 ld u32 $r2 g[$r0d+0xc] (8) 493: $p3 mov u32 $r2 0x00000000 (8) 494: neg f32 $r24 $r3 (8) 495: add f32 $r3 $r13 $r24 (8) 496: neg f32 $r25 $r5 (8) 497: add f32 $r5 $r14 $r25 (8) 498: neg f32 $r23 $r23 (8) 499: add f32 $r26 $r15 $r23 (8) 500: neg f32 $r27 $r2 (8) 501: add f32 $r2 $r16 $r27 (8) 502: mul f32 $r28 $r3 $r3 (8) 503: mad f32 $r28 $r5 $r5 $r28 (8) 504: mad f32 $r28 $r26 $r26 $r28 (8) 505: mad f32 $r28 $r2 $r2 $r28 (8) 506: rsq f32 $r28 $r28 (8) 507: rcp f32 $r28 $r28 (8) 508: neg f32 $r29 $r28 (8) 509: add f32 $r29 $r29 c0[0x20] (8) 510: mul f32 $r29 $r29 0.350000 (8) 511: rcp f32 $r28 $r28 (8) 512: mul f32 $r28 $r29 $r28 (8) 513: mul f32 $r29 $r28 $r3 (8) 514: mul f32 $r5 $r28 $r5 (8) 515: mul f32 $r26 $r28 $r26 (8) 516: mul f32 $r28 $r28 $r2 (8) 517: shl u32 $r2 $r8 0x00000004 (8) 518: add u32 $r30 $r2 0x00000010 (8) 519: add u32 { $r2 $c0 } $r30 c7[0x330] (8) 520: add u32 $r3 $r255 c7[0x334] $c0 (8) 521: add u32 $r31 $r30 0x00000004 (8) 522: set u8 $p4 gt u32 $r31 c7[0x338] (8) 523: cvt u8 $r42 $p4 (8) 524: cvt u8 $p4 $r42 (8) 525: not $p4 ld u32 $r31 g[$r2d+0x0] (8) 526: $p4 mov u32 $r31 0x00000000 (8) 527: add u32 $r32 $r30 0x00000008 (8) 528: set u8 $p4 gt u32 $r32 c7[0x338] (8) 529: cvt u8 $r41 $p4 (8) 530: cvt u8 $p4 $r41 (8) 531: not $p4 ld u32 $r32 g[$r2d+0x4] (8) 532: $p4 mov u32 $r32 0x00000000 (8) 533: add u32 $r33 $r30 0x0000000c (8) 534: set u8 $p4 gt u32 $r33 c7[0x338] (8) 535: cvt u8 $r40 $p4 (8) 536: cvt u8 $p4 $r40 (8) 537: not $p4 ld u32 $r33 g[$r2d+0x8] (8) 538: $p4 mov u32 $r33 0x00000000 (8) 539: add u32 $r30 $r30 0x00000010 (8) 540: set u8 $p4 gt u32 $r30 c7[0x338] (8) 541: cvt u8 $r39 $p4 (8) 542: cvt u8 $p4 $r39 (8) 543: not $p4 ld u32 $r30 g[$r2d+0xc] (8) 544: $p4 mov u32 $r30 0x00000000 (8) 545: add f32 $r31 $r31 $r29 (8) 546: add f32 $r32 $r32 $r5 (8) 547: add f32 $r33 $r33 $r26 (8) 548: add f32 $r30 $r30 $r28 (8) 549: cvt u8 $p4 $r42 (8) 550: not $p4 st u32 # g[$r2d+0x0] $r31 (8) 551: cvt u8 $p4 $r41 (8) 552: not $p4 st u32 # g[$r2d+0x4] $r32 (8) 553: cvt u8 $p4 $r40 (8) 554: not $p4 st u32 # g[$r2d+0x8] $r33 (8) 555: cvt u8 $p4 $r39 (8) 556: not $p4 st u32 # g[$r2d+0xc] $r30 (8) 557: not $p0 ld u32 $r30 g[$r0d+0x0] (8) 558: $p0 mov u32 $r30 0x00000000 (8) 559: not $p1 ld u32 $r31 g[$r0d+0x4] (8) 560: $p1 mov u32 $r31 0x00000000 (8) 561: not $p2 ld u32 $r32 g[$r0d+0x8] (8) 562: $p2 mov u32 $r32 0x00000000 (8) 563: not $p3 ld u32 $r33 g[$r0d+0xc] (8) 564: $p3 mov u32 $r33 0x00000000 (8) 565: neg f32 $r29 $r29 (8) 566: add f32 $r29 $r30 $r29 (8) 567: neg f32 $r5 $r5 (8) 568: add f32 $r5 $r31 $r5 (8) 569: neg f32 $r26 $r26 (8) 570: add f32 $r26 $r32 $r26 (8) 571: neg f32 $r28 $r28 (8) 572: add f32 $r28 $r33 $r28 (8) 573: not $p0 st u32 # g[$r0d+0x0] $r29 (8) 574: not $p1 st u32 # g[$r0d+0x4] $r5 (8) 575: not $p2 st u32 # g[$r0d+0x8] $r26 (8) 576: not $p3 st u32 # g[$r0d+0xc] $r28 (8) 577: membar (SUBOP:7) - # (8) 578: add f32 $r5 $r17 $r24 (8) 579: add f32 $r26 $r18 $r25 (8) 580: add f32 $r28 $r19 $r23 (8) 581: add f32 $r29 $r11 $r27 (8) 582: mul f32 $r30 $r5 $r5 (8) 583: mad f32 $r30 $r26 $r26 $r30 (8) 584: mad f32 $r30 $r28 $r28 $r30 (8) 585: mad f32 $r30 $r29 $r29 $r30 (8) 586: rsq f32 $r30 $r30 (8) 587: rcp f32 $r30 $r30 (8) 588: neg f32 $r31 $r30 (8) 589: add f32 $r31 $r31 c0[0x20] (8) 590: mul f32 $r31 $r31 0.350000 (8) 591: rcp f32 $r30 $r30 (8) 592: mul f32 $r30 $r31 $r30 (8) 593: mul f32 $r31 $r30 $r5 (8) 594: mul f32 $r26 $r30 $r26 (8) 595: mul f32 $r28 $r30 $r28 (8) 596: mul f32 $r29 $r30 $r29 (8) 597: shl u32 $r30 $r4 0x00000004 (8) 598: add u32 { $r4 $c0 } $r30 c7[0x330] (8) 599: add u32 $r5 $r255 c7[0x334] $c0 (8) 600: add u32 $r32 $r30 0x00000004 (8) 601: set u8 $p4 gt u32 $r32 c7[0x338] (8) 602: cvt u8 $r38 $p4 (8) 603: cvt u8 $p4 $r38 (8) 604: not $p4 ld u32 $r32 g[$r4d+0x0] (8) 605: $p4 mov u32 $r32 0x00000000 (8) 606: add u32 $r33 $r30 0x00000008 (8) 607: set u8 $p4 gt u32 $r33 c7[0x338] (8) 608: cvt u8 $r37 $p4 (8) 609: cvt u8 $p4 $r37 (8) 610: not $p4 ld u32 $r33 g[$r4d+0x4] (8) 611: $p4 mov u32 $r33 0x00000000 (8) 612: add u32 $r34 $r30 0x0000000c (8) 613: set u8 $p4 gt u32 $r34 c7[0x338] (8) 614: cvt u8 $r36 $p4 (8) 615: cvt u8 $p4 $r36 (8) 616: not $p4 ld u32 $r34 g[$r4d+0x8] (8) 617: $p4 mov u32 $r34 0x00000000 (8) 618: add u32 $r30 $r30 0x00000010 (8) 619: set u8 $p4 gt u32 $r30 c7[0x338] (8) 620: cvt u8 $r35 $p4 (8) 621: cvt u8 $p4 $r35 (8) 622: not $p4 ld u32 $r30 g[$r4d+0xc] (8) 623: $p4 mov u32 $r30 0x00000000 (8) 624: add f32 $r32 $r32 $r31 (8) 625: add f32 $r33 $r33 $r26 (8) 626: add f32 $r34 $r34 $r28 (8) 627: add f32 $r30 $r30 $r29 (8) 628: cvt u8 $p4 $r38 (8) 629: not $p4 st u32 # g[$r4d+0x0] $r32 (8) 630: cvt u8 $p4 $r37 (8) 631: not $p4 st u32 # g[$r4d+0x4] $r33 (8) 632: cvt u8 $p4 $r36 (8) 633: not $p4 st u32 # g[$r4d+0x8] $r34 (8) 634: cvt u8 $p4 $r35 (8) 635: not $p4 st u32 # g[$r4d+0xc] $r30 (8) 636: not $p0 ld u32 $r30 g[$r0d+0x0] (8) 637: $p0 mov u32 $r30 0x00000000 (8) 638: not $p1 ld u32 $r32 g[$r0d+0x4] (8) 639: $p1 mov u32 $r32 0x00000000 (8) 640: not $p2 ld u32 $r33 g[$r0d+0x8] (8) 641: $p2 mov u32 $r33 0x00000000 (8) 642: not $p3 ld u32 $r34 g[$r0d+0xc] (8) 643: $p3 mov u32 $r34 0x00000000 (8) 644: neg f32 $r31 $r31 (8) 645: add f32 $r30 $r30 $r31 (8) 646: neg f32 $r26 $r26 (8) 647: add f32 $r26 $r32 $r26 (8) 648: neg f32 $r28 $r28 (8) 649: add f32 $r28 $r33 $r28 (8) 650: neg f32 $r29 $r29 (8) 651: add f32 $r29 $r34 $r29 (8) 652: not $p0 st u32 # g[$r0d+0x0] $r30 (8) 653: not $p1 st u32 # g[$r0d+0x4] $r26 (8) 654: not $p2 st u32 # g[$r0d+0x8] $r28 (8) 655: not $p3 st u32 # g[$r0d+0xc] $r29 (8) 656: membar (SUBOP:7) - # (8) 657: add f32 $r6 $r6 $r24 (8) 658: add f32 $r7 $r7 $r25 (8) 659: add f32 $r21 $r21 $r23 (8) 660: add f32 $r22 $r22 $r27 (8) 661: mul f32 $r23 $r6 $r6 (8) 662: mad f32 $r23 $r7 $r7 $r23 (8) 663: mad f32 $r23 $r21 $r21 $r23 (8) 664: mad f32 $r23 $r22 $r22 $r23 (8) 665: rsq f32 $r23 $r23 (8) 666: rcp f32 $r23 $r23 (8) 667: neg f32 $r24 $r23 (8) 668: add f32 $r24 $r24 c0[0x30] (8) 669: mul f32 $r24 $r24 0.350000 (8) 670: rcp f32 $r23 $r23 (8) 671: mul f32 $r23 $r24 $r23 (8) 672: mul f32 $r24 $r23 $r6 (8) 673: mul f32 $r25 $r23 $r7 (8) 674: mul f32 $r21 $r23 $r21 (8) 675: mul f32 $r22 $r23 $r22 (8) 676: shl u32 $r23 $r8 0x00000004 (8) 677: add u32 { $r6 $c0 } $r23 c7[0x330] (8) 678: add u32 $r7 $r255 c7[0x334] $c0 (8) 679: add u32 $r26 $r23 0x00000004 (8) 680: set u8 $p4 gt u32 $r26 c7[0x338] (8) 681: cvt u8 $r29 $p4 (8) 682: cvt u8 $p4 $r29 (8) 683: not $p4 ld u32 $r26 g[$r6d+0x0] (8) 684: $p4 mov u32 $r26 0x00000000 (8) 685: add u32 $r27 $r23 0x00000008 (8) 686: set u8 $p4 gt u32 $r27 c7[0x338] (8) 687: cvt u8 $r30 $p4 (8) 688: cvt u8 $p4 $r30 (8) 689: not $p4 ld u32 $r27 g[$r6d+0x4] (8) 690: $p4 mov u32 $r27 0x00000000 (8) 691: add u32 $r28 $r23 0x0000000c (8) 692: set u8 $p4 gt u32 $r28 c7[0x338] (8) 693: not $p4 ld u32 $r28 g[$r6d+0x8] (8) 694: $p4 mov u32 $r28 0x00000000 (8) 695: add u32 $r23 $r23 0x00000010 (8) 696: set u8 $p5 gt u32 $r23 c7[0x338] (8) 697: not $p5 ld u32 $r23 g[$r6d+0xc] (8) 698: $p5 mov u32 $r23 0x00000000 (8) 699: add f32 $r26 $r26 $r24 (8) 700: add f32 $r27 $r27 $r25 (8) 701: add f32 $r28 $r28 $r21 (8) 702: add f32 $r23 $r23 $r22 (8) 703: cvt u8 $p6 $r29 (8) 704: not $p6 st u32 # g[$r6d+0x0] $r26 (8) 705: cvt u8 $p6 $r30 (8) 706: not $p6 st u32 # g[$r6d+0x4] $r27 (8) 707: not $p4 st u32 # g[$r6d+0x8] $r28 (8) 708: not $p5 st u32 # g[$r6d+0xc] $r23 (8) 709: not $p0 ld u32 $r6 g[$r0d+0x0] (8) 710: $p0 mov u32 $r6 0x00000000 (8) 711: not $p1 ld u32 $r7 g[$r0d+0x4] (8) 712: $p1 mov u32 $r7 0x00000000 (8) 713: not $p2 ld u32 $r23 g[$r0d+0x8] (8) 714: $p2 mov u32 $r23 0x00000000 (8) 715: not $p3 ld u32 $r26 g[$r0d+0xc] (8) 716: $p3 mov u32 $r26 0x00000000 (8) 717: neg f32 $r24 $r24 (8) 718: add f32 $r6 $r6 $r24 (8) 719: neg f32 $r24 $r25 (8) 720: add f32 $r7 $r7 $r24 (8) 721: neg f32 $r21 $r21 (8) 722: add f32 $r21 $r23 $r21 (8) 723: neg f32 $r22 $r22 (8) 724: add f32 $r22 $r26 $r22 (8) 725: not $p0 st u32 # g[$r0d+0x0] $r6 (8) 726: not $p1 st u32 # g[$r0d+0x4] $r7 (8) 727: not $p2 st u32 # g[$r0d+0x8] $r21 (8) 728: not $p3 st u32 # g[$r0d+0xc] $r22 (8) 729: neg f32 $r0 $r17 (8) 730: add f32 $r0 $r13 $r0 (8) 731: neg f32 $r1 $r18 (8) 732: add f32 $r1 $r14 $r1 (8) 733: neg f32 $r6 $r19 (8) 734: add f32 $r6 $r15 $r6 (8) 735: neg f32 $r7 $r11 (8) 736: add f32 $r7 $r16 $r7 (8) 737: mul f32 $r21 $r0 $r0 (8) 738: mad f32 $r21 $r1 $r1 $r21 (8) 739: mad f32 $r21 $r6 $r6 $r21 (8) 740: mad f32 $r21 $r7 $r7 $r21 (8) 741: rsq f32 $r21 $r21 (8) 742: rcp f32 $r21 $r21 (8) 743: neg f32 $r22 $r21 (8) 744: add f32 $r22 $r22 c0[0x30] (8) 745: mul f32 $r22 $r22 0.350000 (8) 746: rcp f32 $r21 $r21 (8) 747: mul f32 $r21 $r22 $r21 (8) 748: mul f32 $r0 $r21 $r0 (8) 749: mul f32 $r1 $r21 $r1 (8) 750: mul f32 $r6 $r21 $r6 (8) 751: mul f32 $r7 $r21 $r7 (8) 752: cvt u8 $p0 $r42 (8) 753: not $p0 ld u32 $r21 g[$r2d+0x0] (8) 754: $p0 mov u32 $r21 0x00000000 (8) 755: cvt u8 $p0 $r41 (8) 756: not $p0 ld u32 $r22 g[$r2d+0x4] (8) 757: $p0 mov u32 $r22 0x00000000 (8) 758: cvt u8 $p0 $r40 (8) 759: not $p0 ld u32 $r23 g[$r2d+0x8] (8) 760: $p0 mov u32 $r23 0x00000000 (8) 761: cvt u8 $p0 $r39 (8) 762: not $p0 ld u32 $r24 g[$r2d+0xc] (8) 763: $p0 mov u32 $r24 0x00000000 (8) 764: add f32 $r21 $r21 $r0 (8) 765: add f32 $r22 $r22 $r1 (8) 766: add f32 $r23 $r23 $r6 (8) 767: add f32 $r24 $r24 $r7 (8) 768: cvt u8 $p0 $r42 (8) 769: not $p0 st u32 # g[$r2d+0x0] $r21 (8) 770: cvt u8 $p0 $r41 (8) 771: not $p0 st u32 # g[$r2d+0x4] $r22 (8) 772: cvt u8 $p0 $r40 (8) 773: not $p0 st u32 # g[$r2d+0x8] $r23 (8) 774: cvt u8 $p0 $r39 (8) 775: not $p0 st u32 # g[$r2d+0xc] $r24 (8) 776: cvt u8 $p0 $r38 (8) 777: not $p0 ld u32 $r2 g[$r4d+0x0] (8) 778: $p0 mov u32 $r2 0x00000000 (8) 779: cvt u8 $p0 $r37 (8) 780: not $p0 ld u32 $r3 g[$r4d+0x4] (8) 781: $p0 mov u32 $r3 0x00000000 (8) 782: cvt u8 $p0 $r36 (8) 783: not $p0 ld u32 $r21 g[$r4d+0x8] (8) 784: $p0 mov u32 $r21 0x00000000 (8) 785: cvt u8 $p0 $r35 (8) 786: not $p0 ld u32 $r22 g[$r4d+0xc] (8) 787: $p0 mov u32 $r22 0x00000000 (8) 788: neg f32 $r0 $r0 (8) 789: add f32 $r0 $r2 $r0 (8) 790: neg f32 $r1 $r1 (8) 791: add f32 $r1 $r3 $r1 (8) 792: neg f32 $r2 $r6 (8) 793: add f32 $r2 $r21 $r2 (8) 794: neg f32 $r3 $r7 (8) 795: add f32 $r3 $r22 $r3 (8) 796: cvt u8 $p0 $r38 (8) 797: not $p0 st u32 # g[$r4d+0x0] $r0 (8) 798: cvt u8 $p0 $r37 (8) 799: not $p0 st u32 # g[$r4d+0x4] $r1 (8) 800: cvt u8 $p0 $r36 (8) 801: not $p0 st u32 # g[$r4d+0x8] $r2 (8) 802: cvt u8 $p0 $r35 (8) 803: not $p0 st u32 # g[$r4d+0xc] $r3 (8) 804: membar (SUBOP:7) - # (8) 805: join BB:24 (8) BB:63 (1 instructions) - df = { } -> BB:24 (forward) 806: join BB:24 (8) BB:24 (1 instructions) - idom = BB:22, df = { BB:35 } -> BB:35 (forward) 807: join BB:35 (8) BB:25 (11 instructions) - idom = BB:17, df = { BB:35 } -> BB:29 (tree) -> BB:26 (tree) 808: set u32 $r4 eq $r20 0x00000001 (8) 809: mov u32 $r1 0x00000002 (8) 810: mov u32 $r0 $r10 (8) 811: call abs BUILTIN:1 (8) 812: set u32 $r0 eq $r1 0x00000001 (8) 813: and u32 $r0 $r4 $r0 (8) 814: set u32 $r1 eq $r9 $r255 (8) 815: and u32 $r0 $r0 $r1 (8) 816: joinat BB:34 (8) 817: set u8 $p0 neu u32 $r255 $r0 (8) 818: not $p0 bra BB:29 (8) BB:26 (4 instructions) - idom = BB:25, df = { BB:34 } -> BB:60 (tree) -> BB:27 (tree) 819: add u32 $r0 $r8 0x00000001 (8) 820: joinat BB:28 (8) 821: set u8 $p0 lt s32 $r0 c0[0x0] (8) 822: not $p0 bra BB:60 (8) BB:27 (104 instructions) - idom = BB:26, df = { BB:28 } -> BB:28 (forward) 823: shl u32 $r2 $r8 0x00000004 (8) 824: add u32 { $r0 $c0 } $r2 c7[0x330] (8) 825: add u32 $r1 $r255 c7[0x334] $c0 (8) 826: add u32 $r3 $r2 0x00000004 (8) 827: set u8 $p0 gt u32 $r3 c7[0x338] (8) 828: not $p0 ld u32 $r4 g[$r0d+0x0] (8) 829: $p0 mov u32 $r4 0x00000000 (8) 830: add u32 $r3 $r2 0x00000008 (8) 831: set u8 $p1 gt u32 $r3 c7[0x338] (8) 832: not $p1 ld u32 $r5 g[$r0d+0x4] (8) 833: $p1 mov u32 $r5 0x00000000 (8) 834: add u32 $r3 $r2 0x0000000c (8) 835: set u8 $p2 gt u32 $r3 c7[0x338] (8) 836: not $p2 ld u32 $r6 g[$r0d+0x8] (8) 837: $p2 mov u32 $r6 0x00000000 (8) 838: add u32 $r2 $r2 0x00000010 (8) 839: set u8 $p3 gt u32 $r2 c7[0x338] (8) 840: not $p3 ld u32 $r7 g[$r0d+0xc] (8) 841: $p3 mov u32 $r7 0x00000000 (8) 842: shl u32 $r2 $r8 0x00000004 (8) 843: add u32 $r21 $r2 0x00000010 (8) 844: add u32 { $r2 $c0 } $r21 c7[0x330] (8) 845: add u32 $r3 $r255 c7[0x334] $c0 (8) 846: add u32 $r22 $r21 0x00000004 (8) 847: set u8 $p4 gt u32 $r22 c7[0x338] (8) 848: cvt u8 $r25 $p4 (8) 849: cvt u8 $p4 $r25 (8) 850: not $p4 ld u32 $r22 g[$r2d+0x0] (8) 851: $p4 mov u32 $r22 0x00000000 (8) 852: add u32 $r23 $r21 0x00000008 (8) 853: set u8 $p4 gt u32 $r23 c7[0x338] (8) 854: not $p4 ld u32 $r23 g[$r2d+0x4] (8) 855: $p4 mov u32 $r23 0x00000000 (8) 856: add u32 $r24 $r21 0x0000000c (8) 857: set u8 $p5 gt u32 $r24 c7[0x338] (8) 858: not $p5 ld u32 $r24 g[$r2d+0x8] (8) 859: $p5 mov u32 $r24 0x00000000 (8) 860: add u32 $r21 $r21 0x00000010 (8) 861: set u8 $p6 gt u32 $r21 c7[0x338] (8) 862: not $p6 ld u32 $r21 g[$r2d+0xc] (8) 863: $p6 mov u32 $r21 0x00000000 (8) 864: neg f32 $r22 $r22 (8) 865: add f32 $r4 $r4 $r22 (8) 866: neg f32 $r22 $r23 (8) 867: add f32 $r5 $r5 $r22 (8) 868: neg f32 $r22 $r24 (8) 869: add f32 $r6 $r6 $r22 (8) 870: neg f32 $r21 $r21 (8) 871: add f32 $r7 $r7 $r21 (8) 872: mul f32 $r21 $r4 $r4 (8) 873: mad f32 $r21 $r5 $r5 $r21 (8) 874: mad f32 $r21 $r6 $r6 $r21 (8) 875: mad f32 $r21 $r7 $r7 $r21 (8) 876: rsq f32 $r21 $r21 (8) 877: rcp f32 $r21 $r21 (8) 878: neg f32 $r22 $r21 (8) 879: add f32 $r22 $r22 c0[0x20] (8) 880: mul f32 $r22 $r22 0.350000 (8) 881: rcp f32 $r21 $r21 (8) 882: mul f32 $r21 $r22 $r21 (8) 883: mul f32 $r4 $r21 $r4 (8) 884: mul f32 $r5 $r21 $r5 (8) 885: mul f32 $r6 $r21 $r6 (8) 886: mul f32 $r7 $r21 $r7 (8) 887: not $p0 ld u32 $r21 g[$r0d+0x0] (8) 888: $p0 mov u32 $r21 0x00000000 (8) 889: not $p1 ld u32 $r22 g[$r0d+0x4] (8) 890: $p1 mov u32 $r22 0x00000000 (8) 891: not $p2 ld u32 $r23 g[$r0d+0x8] (8) 892: $p2 mov u32 $r23 0x00000000 (8) 893: not $p3 ld u32 $r24 g[$r0d+0xc] (8) 894: $p3 mov u32 $r24 0x00000000 (8) 895: add f32 $r21 $r21 $r4 (8) 896: add f32 $r22 $r22 $r5 (8) 897: add f32 $r23 $r23 $r6 (8) 898: add f32 $r24 $r24 $r7 (8) 899: not $p0 st u32 # g[$r0d+0x0] $r21 (8) 900: not $p1 st u32 # g[$r0d+0x4] $r22 (8) 901: not $p2 st u32 # g[$r0d+0x8] $r23 (8) 902: not $p3 st u32 # g[$r0d+0xc] $r24 (8) 903: cvt u8 $p0 $r25 (8) 904: not $p0 ld u32 $r0 g[$r2d+0x0] (8) 905: $p0 mov u32 $r0 0x00000000 (8) 906: not $p4 ld u32 $r1 g[$r2d+0x4] (8) 907: $p4 mov u32 $r1 0x00000000 (8) 908: not $p5 ld u32 $r21 g[$r2d+0x8] (8) 909: $p5 mov u32 $r21 0x00000000 (8) 910: not $p6 ld u32 $r22 g[$r2d+0xc] (8) 911: $p6 mov u32 $r22 0x00000000 (8) 912: neg f32 $r4 $r4 (8) 913: add f32 $r0 $r0 $r4 (8) 914: neg f32 $r4 $r5 (8) 915: add f32 $r1 $r1 $r4 (8) 916: neg f32 $r4 $r6 (8) 917: add f32 $r4 $r21 $r4 (8) 918: neg f32 $r5 $r7 (8) 919: add f32 $r5 $r22 $r5 (8) 920: cvt u8 $p0 $r25 (8) 921: not $p0 st u32 # g[$r2d+0x0] $r0 (8) 922: not $p4 st u32 # g[$r2d+0x4] $r1 (8) 923: not $p5 st u32 # g[$r2d+0x8] $r4 (8) 924: not $p6 st u32 # g[$r2d+0xc] $r5 (8) 925: membar (SUBOP:7) - # (8) 926: join BB:28 (8) BB:60 (1 instructions) - df = { } -> BB:28 (forward) 927: join BB:28 (8) BB:28 (1 instructions) - idom = BB:26, df = { BB:34 } -> BB:34 (forward) 928: join BB:34 (8) BB:29 (11 instructions) - idom = BB:25, df = { BB:34 } -> BB:58 (tree) -> BB:30 (tree) 929: set u32 $r4 eq $r20 0x00000001 (8) 930: mov u32 $r1 0x00000002 (8) 931: mov u32 $r0 $r9 (8) 932: call abs BUILTIN:1 (8) 933: set u32 $r0 eq $r1 0x00000001 (8) 934: and u32 $r0 $r4 $r0 (8) 935: set u32 $r1 eq $r10 $r255 (8) 936: and u32 $r0 $r0 $r1 (8) 937: joinat BB:33 (8) 938: set u8 $p0 neu u32 $r255 $r0 (8) 939: not $p0 bra BB:58 (8) BB:30 (6 instructions) - idom = BB:29, df = { BB:33 } -> BB:59 (tree) -> BB:31 (tree) 940: ld u32 $r0 c0[0x0] (8) 941: add u32 $r2 $r8 c0[0x0] (8) 942: mul u32 $r0 $r0 c0[0x0] (8) 943: joinat BB:32 (8) 944: set u8 $p0 lt s32 $r2 $r0 (8) 945: not $p0 bra BB:59 (8) BB:31 (103 instructions) - idom = BB:30, df = { BB:32 } -> BB:32 (forward) 946: shl u32 $r3 $r8 0x00000004 (8) 947: add u32 { $r0 $c0 } $r3 c7[0x330] (8) 948: add u32 $r1 $r255 c7[0x334] $c0 (8) 949: add u32 $r4 $r3 0x00000004 (8) 950: set u8 $p0 gt u32 $r4 c7[0x338] (8) 951: not $p0 ld u32 $r4 g[$r0d+0x0] (8) 952: $p0 mov u32 $r4 0x00000000 (8) 953: add u32 $r5 $r3 0x00000008 (8) 954: set u8 $p1 gt u32 $r5 c7[0x338] (8) 955: not $p1 ld u32 $r5 g[$r0d+0x4] (8) 956: $p1 mov u32 $r5 0x00000000 (8) 957: add u32 $r6 $r3 0x0000000c (8) 958: set u8 $p2 gt u32 $r6 c7[0x338] (8) 959: not $p2 ld u32 $r6 g[$r0d+0x8] (8) 960: $p2 mov u32 $r6 0x00000000 (8) 961: add u32 $r3 $r3 0x00000010 (8) 962: set u8 $p3 gt u32 $r3 c7[0x338] (8) 963: not $p3 ld u32 $r7 g[$r0d+0xc] (8) 964: $p3 mov u32 $r7 0x00000000 (8) 965: shl u32 $r21 $r2 0x00000004 (8) 966: add u32 { $r2 $c0 } $r21 c7[0x330] (8) 967: add u32 $r3 $r255 c7[0x334] $c0 (8) 968: add u32 $r22 $r21 0x00000004 (8) 969: set u8 $p4 gt u32 $r22 c7[0x338] (8) 970: cvt u8 $r25 $p4 (8) 971: cvt u8 $p4 $r25 (8) 972: not $p4 ld u32 $r22 g[$r2d+0x0] (8) 973: $p4 mov u32 $r22 0x00000000 (8) 974: add u32 $r23 $r21 0x00000008 (8) 975: set u8 $p4 gt u32 $r23 c7[0x338] (8) 976: not $p4 ld u32 $r23 g[$r2d+0x4] (8) 977: $p4 mov u32 $r23 0x00000000 (8) 978: add u32 $r24 $r21 0x0000000c (8) 979: set u8 $p5 gt u32 $r24 c7[0x338] (8) 980: not $p5 ld u32 $r24 g[$r2d+0x8] (8) 981: $p5 mov u32 $r24 0x00000000 (8) 982: add u32 $r21 $r21 0x00000010 (8) 983: set u8 $p6 gt u32 $r21 c7[0x338] (8) 984: not $p6 ld u32 $r21 g[$r2d+0xc] (8) 985: $p6 mov u32 $r21 0x00000000 (8) 986: neg f32 $r22 $r22 (8) 987: add f32 $r4 $r4 $r22 (8) 988: neg f32 $r22 $r23 (8) 989: add f32 $r5 $r5 $r22 (8) 990: neg f32 $r22 $r24 (8) 991: add f32 $r6 $r6 $r22 (8) 992: neg f32 $r21 $r21 (8) 993: add f32 $r7 $r7 $r21 (8) 994: mul f32 $r21 $r4 $r4 (8) 995: mad f32 $r21 $r5 $r5 $r21 (8) 996: mad f32 $r21 $r6 $r6 $r21 (8) 997: mad f32 $r21 $r7 $r7 $r21 (8) 998: rsq f32 $r21 $r21 (8) 999: rcp f32 $r21 $r21 (8) 1000: neg f32 $r22 $r21 (8) 1001: add f32 $r22 $r22 c0[0x20] (8) 1002: mul f32 $r22 $r22 0.350000 (8) 1003: rcp f32 $r21 $r21 (8) 1004: mul f32 $r21 $r22 $r21 (8) 1005: mul f32 $r4 $r21 $r4 (8) 1006: mul f32 $r5 $r21 $r5 (8) 1007: mul f32 $r6 $r21 $r6 (8) 1008: mul f32 $r7 $r21 $r7 (8) 1009: not $p0 ld u32 $r21 g[$r0d+0x0] (8) 1010: $p0 mov u32 $r21 0x00000000 (8) 1011: not $p1 ld u32 $r22 g[$r0d+0x4] (8) 1012: $p1 mov u32 $r22 0x00000000 (8) 1013: not $p2 ld u32 $r23 g[$r0d+0x8] (8) 1014: $p2 mov u32 $r23 0x00000000 (8) 1015: not $p3 ld u32 $r24 g[$r0d+0xc] (8) 1016: $p3 mov u32 $r24 0x00000000 (8) 1017: add f32 $r21 $r21 $r4 (8) 1018: add f32 $r22 $r22 $r5 (8) 1019: add f32 $r23 $r23 $r6 (8) 1020: add f32 $r24 $r24 $r7 (8) 1021: not $p0 st u32 # g[$r0d+0x0] $r21 (8) 1022: not $p1 st u32 # g[$r0d+0x4] $r22 (8) 1023: not $p2 st u32 # g[$r0d+0x8] $r23 (8) 1024: not $p3 st u32 # g[$r0d+0xc] $r24 (8) 1025: cvt u8 $p0 $r25 (8) 1026: not $p0 ld u32 $r0 g[$r2d+0x0] (8) 1027: $p0 mov u32 $r0 0x00000000 (8) 1028: not $p4 ld u32 $r1 g[$r2d+0x4] (8) 1029: $p4 mov u32 $r1 0x00000000 (8) 1030: not $p5 ld u32 $r21 g[$r2d+0x8] (8) 1031: $p5 mov u32 $r21 0x00000000 (8) 1032: not $p6 ld u32 $r22 g[$r2d+0xc] (8) 1033: $p6 mov u32 $r22 0x00000000 (8) 1034: neg f32 $r4 $r4 (8) 1035: add f32 $r0 $r0 $r4 (8) 1036: neg f32 $r4 $r5 (8) 1037: add f32 $r1 $r1 $r4 (8) 1038: neg f32 $r4 $r6 (8) 1039: add f32 $r4 $r21 $r4 (8) 1040: neg f32 $r5 $r7 (8) 1041: add f32 $r5 $r22 $r5 (8) 1042: cvt u8 $p0 $r25 (8) 1043: not $p0 st u32 # g[$r2d+0x0] $r0 (8) 1044: not $p4 st u32 # g[$r2d+0x4] $r1 (8) 1045: not $p5 st u32 # g[$r2d+0x8] $r4 (8) 1046: not $p6 st u32 # g[$r2d+0xc] $r5 (8) 1047: membar (SUBOP:7) - # (8) 1048: join BB:32 (8) BB:59 (1 instructions) - df = { } -> BB:32 (forward) 1049: join BB:32 (8) BB:32 (1 instructions) - idom = BB:30, df = { BB:33 } -> BB:33 (forward) 1050: join BB:33 (8) BB:58 (1 instructions) - df = { } -> BB:33 (forward) 1051: join BB:33 (8) BB:33 (1 instructions) - idom = BB:29, df = { BB:34 } -> BB:34 (forward) 1052: join BB:34 (8) BB:34 (1 instructions) - idom = BB:25, df = { BB:35 } -> BB:35 (forward) 1053: join BB:35 (8) BB:35 (3 instructions) - idom = BB:17, df = { BB:14 } -> BB:14 (back) 1054: bar u32 # $r255 $r255 (8) 1055: add u32 $r20 $r20 0x00000001 (8) 1056: bra BB:14 (8) BB:15 (2 instructions) - idom = BB:16, df = { BB:10 } -> BB:36 (tree) 1057: mov u32 $r20 0x00000000 (8) 1058: prebreak BB:37 (8) BB:36 (2 instructions) - idom = BB:15, df = { BB:10 BB:36 } -> BB:39 (forward) -> BB:38 (tree) 1059: set u8 $p0 ge s32 $r20 2 (8) 1060: not $p0 bra BB:39 (8) BB:38 (1 instructions) - idom = BB:36, df = { BB:10 } -> BB:37 (cross) 1061: break BB:37 (8) BB:39 (13 instructions) - idom = BB:36, df = { BB:36 } -> BB:64 (tree) -> BB:40 (tree) 1062: mov u32 $r4 0x00000002 (8) 1063: mov u32 $r0 $r9 (8) 1064: mov u32 $r1 $r4 (8) 1065: call abs BUILTIN:1 (8) 1066: set u32 $r5 eq $r1 $r20 (8) 1067: add u32 $r0 $r10 0x00000001 (8) 1068: mov u32 $r1 $r4 (8) 1069: call abs BUILTIN:1 (8) 1070: set u32 $r0 eq $r1 $r20 (8) 1071: and u32 $r0 $r5 $r0 (8) 1072: joinat BB:43 (8) 1073: set u8 $p0 neu u32 $r255 $r0 (8) 1074: not $p0 bra BB:64 (8) BB:40 (32 instructions) - idom = BB:39, df = { BB:43 } -> BB:65 (tree) -> BB:41 (tree) 1075: shl u32 $r2 $r8 0x00000004 (8) 1076: add u32 { $r0 $c0 } $r2 c7[0x330] (8) 1077: add u32 $r1 $r255 c7[0x334] $c0 (8) 1078: add u32 $r3 $r2 0x00000004 (8) 1079: set u8 $p0 gt u32 $r3 c7[0x338] (8) 1080: not $p0 ld u32 $r6 g[$r0d+0x0] (8) 1081: $p0 mov u32 $r6 0x00000000 (8) 1082: add u32 $r3 $r2 0x00000008 (8) 1083: set u8 $p0 gt u32 $r3 c7[0x338] (8) 1084: not $p0 ld u32 $r7 g[$r0d+0x4] (8) 1085: $p0 mov u32 $r7 0x00000000 (8) 1086: add u32 $r3 $r2 0x0000000c (8) 1087: set u8 $p0 gt u32 $r3 c7[0x338] (8) 1088: not $p0 ld u32 $r21 g[$r0d+0x8] (8) 1089: $p0 mov u32 $r21 0x00000000 (8) 1090: add u32 $r2 $r2 0x00000010 (8) 1091: set u8 $p0 gt u32 $r2 c7[0x338] (8) 1092: not $p0 ld u32 $r22 g[$r0d+0xc] (8) 1093: $p0 mov u32 $r22 0x00000000 (8) 1094: add u32 $r0 $r8 0x00000001 (8) 1095: ld u32 $r1 c0[0x0] (8) 1096: add u32 $r4 $r8 c0[0x0] (8) 1097: add u32 $r5 $r0 c0[0x0] (8) 1098: mul u32 $r0 $r1 c0[0x0] (8) 1099: set s32 $r23 lt $r5 $r0 (8) 1100: mov u32 $r0 $r5 (8) 1101: call abs BUILTIN:1 (8) 1102: set s32 $r0 lt $r10 $r1 (8) 1103: and u32 $r0 $r23 $r0 (8) 1104: joinat BB:42 (8) 1105: set u8 $p0 neu u32 $r255 $r0 (8) 1106: not $p0 bra BB:65 (8) BB:41 (225 instructions) - idom = BB:40, df = { BB:42 } -> BB:42 (forward) 1107: shl u32 $r0 $r8 0x00000004 (8) 1108: add u32 $r2 $r0 0x00000010 (8) 1109: add u32 { $r0 $c0 } $r2 c7[0x330] (8) 1110: add u32 $r1 $r255 c7[0x334] $c0 (8) 1111: add u32 $r3 $r2 0x00000004 (8) 1112: set u8 $p0 gt u32 $r3 c7[0x338] (8) 1113: cvt u8 $r44 $p0 (8) 1114: cvt u8 $p0 $r44 (8) 1115: not $p0 ld u32 $r23 g[$r0d+0x0] (8) 1116: $p0 mov u32 $r23 0x00000000 (8) 1117: add u32 $r3 $r2 0x00000008 (8) 1118: set u8 $p0 gt u32 $r3 c7[0x338] (8) 1119: cvt u8 $r42 $p0 (8) 1120: cvt u8 $p0 $r42 (8) 1121: not $p0 ld u32 $r24 g[$r0d+0x4] (8) 1122: $p0 mov u32 $r24 0x00000000 (8) 1123: add u32 $r3 $r2 0x0000000c (8) 1124: set u8 $p0 gt u32 $r3 c7[0x338] (8) 1125: cvt u8 $r40 $p0 (8) 1126: cvt u8 $p0 $r40 (8) 1127: not $p0 ld u32 $r25 g[$r0d+0x8] (8) 1128: $p0 mov u32 $r25 0x00000000 (8) 1129: add u32 $r2 $r2 0x00000010 (8) 1130: set u8 $p0 gt u32 $r2 c7[0x338] (8) 1131: cvt u8 $r38 $p0 (8) 1132: cvt u8 $p0 $r38 (8) 1133: not $p0 ld u32 $r26 g[$r0d+0xc] (8) 1134: $p0 mov u32 $r26 0x00000000 (8) 1135: shl u32 $r4 $r4 0x00000004 (8) 1136: add u32 { $r2 $c0 } $r4 c7[0x330] (8) 1137: add u32 $r3 $r255 c7[0x334] $c0 (8) 1138: add u32 $r27 $r4 0x00000004 (8) 1139: set u8 $p0 gt u32 $r27 c7[0x338] (8) 1140: cvt u8 $r45 $p0 (8) 1141: cvt u8 $p0 $r45 (8) 1142: not $p0 ld u32 $r27 g[$r2d+0x0] (8) 1143: $p0 mov u32 $r27 0x00000000 (8) 1144: add u32 $r28 $r4 0x00000008 (8) 1145: set u8 $p0 gt u32 $r28 c7[0x338] (8) 1146: cvt u8 $r43 $p0 (8) 1147: cvt u8 $p0 $r43 (8) 1148: not $p0 ld u32 $r28 g[$r2d+0x4] (8) 1149: $p0 mov u32 $r28 0x00000000 (8) 1150: add u32 $r29 $r4 0x0000000c (8) 1151: set u8 $p0 gt u32 $r29 c7[0x338] (8) 1152: cvt u8 $r41 $p0 (8) 1153: cvt u8 $p0 $r41 (8) 1154: not $p0 ld u32 $r29 g[$r2d+0x8] (8) 1155: $p0 mov u32 $r29 0x00000000 (8) 1156: add u32 $r4 $r4 0x00000010 (8) 1157: set u8 $p0 gt u32 $r4 c7[0x338] (8) 1158: cvt u8 $r39 $p0 (8) 1159: cvt u8 $p0 $r39 (8) 1160: not $p0 ld u32 $r30 g[$r2d+0xc] (8) 1161: $p0 mov u32 $r30 0x00000000 (8) 1162: shl u32 $r31 $r5 0x00000004 (8) 1163: add u32 { $r4 $c0 } $r31 c7[0x330] (8) 1164: add u32 $r5 $r255 c7[0x334] $c0 (8) 1165: add u32 $r32 $r31 0x00000004 (8) 1166: set u8 $p0 gt u32 $r32 c7[0x338] (8) 1167: cvt u8 $r37 $p0 (8) 1168: cvt u8 $p0 $r37 (8) 1169: not $p0 ld u32 $r32 g[$r4d+0x0] (8) 1170: $p0 mov u32 $r32 0x00000000 (8) 1171: add u32 $r33 $r31 0x00000008 (8) 1172: set u8 $p0 gt u32 $r33 c7[0x338] (8) 1173: not $p0 ld u32 $r33 g[$r4d+0x4] (8) 1174: $p0 mov u32 $r33 0x00000000 (8) 1175: add u32 $r34 $r31 0x0000000c (8) 1176: set u8 $p1 gt u32 $r34 c7[0x338] (8) 1177: not $p1 ld u32 $r34 g[$r4d+0x8] (8) 1178: $p1 mov u32 $r34 0x00000000 (8) 1179: add u32 $r31 $r31 0x00000010 (8) 1180: set u8 $p2 gt u32 $r31 c7[0x338] (8) 1181: not $p2 ld u32 $r31 g[$r4d+0xc] (8) 1182: $p2 mov u32 $r31 0x00000000 (8) 1183: neg f32 $r32 $r32 (8) 1184: add f32 $r6 $r6 $r32 (8) 1185: neg f32 $r32 $r33 (8) 1186: add f32 $r7 $r7 $r32 (8) 1187: neg f32 $r32 $r34 (8) 1188: add f32 $r21 $r21 $r32 (8) 1189: neg f32 $r31 $r31 (8) 1190: add f32 $r22 $r22 $r31 (8) 1191: mul f32 $r31 $r6 $r6 (8) 1192: mad f32 $r31 $r7 $r7 $r31 (8) 1193: mad f32 $r31 $r21 $r21 $r31 (8) 1194: mad f32 $r31 $r22 $r22 $r31 (8) 1195: rsq f32 $r31 $r31 (8) 1196: rcp f32 $r31 $r31 (8) 1197: neg f32 $r32 $r31 (8) 1198: add f32 $r32 $r32 c0[0x30] (8) 1199: mul f32 $r32 $r32 0.350000 (8) 1200: rcp f32 $r31 $r31 (8) 1201: mul f32 $r31 $r32 $r31 (8) 1202: mul f32 $r32 $r31 $r6 (8) 1203: mul f32 $r33 $r31 $r7 (8) 1204: mul f32 $r21 $r31 $r21 (8) 1205: mul f32 $r22 $r31 $r22 (8) 1206: shl u32 $r31 $r8 0x00000004 (8) 1207: add u32 { $r6 $c0 } $r31 c7[0x330] (8) 1208: add u32 $r7 $r255 c7[0x334] $c0 (8) 1209: add u32 $r34 $r31 0x00000004 (8) 1210: set u8 $p3 gt u32 $r34 c7[0x338] (8) 1211: not $p3 ld u32 $r34 g[$r6d+0x0] (8) 1212: $p3 mov u32 $r34 0x00000000 (8) 1213: add u32 $r35 $r31 0x00000008 (8) 1214: set u8 $p4 gt u32 $r35 c7[0x338] (8) 1215: not $p4 ld u32 $r35 g[$r6d+0x4] (8) 1216: $p4 mov u32 $r35 0x00000000 (8) 1217: add u32 $r36 $r31 0x0000000c (8) 1218: set u8 $p5 gt u32 $r36 c7[0x338] (8) 1219: not $p5 ld u32 $r36 g[$r6d+0x8] (8) 1220: $p5 mov u32 $r36 0x00000000 (8) 1221: add u32 $r31 $r31 0x00000010 (8) 1222: set u8 $p6 gt u32 $r31 c7[0x338] (8) 1223: not $p6 ld u32 $r31 g[$r6d+0xc] (8) 1224: $p6 mov u32 $r31 0x00000000 (8) 1225: add f32 $r34 $r34 $r32 (8) 1226: add f32 $r35 $r35 $r33 (8) 1227: add f32 $r36 $r36 $r21 (8) 1228: add f32 $r31 $r31 $r22 (8) 1229: not $p3 st u32 # g[$r6d+0x0] $r34 (8) 1230: not $p4 st u32 # g[$r6d+0x4] $r35 (8) 1231: not $p5 st u32 # g[$r6d+0x8] $r36 (8) 1232: not $p6 st u32 # g[$r6d+0xc] $r31 (8) 1233: cvt u8 $p3 $r37 (8) 1234: not $p3 ld u32 $r6 g[$r4d+0x0] (8) 1235: $p3 mov u32 $r6 0x00000000 (8) 1236: not $p0 ld u32 $r7 g[$r4d+0x4] (8) 1237: $p0 mov u32 $r7 0x00000000 (8) 1238: not $p1 ld u32 $r31 g[$r4d+0x8] (8) 1239: $p1 mov u32 $r31 0x00000000 (8) 1240: not $p2 ld u32 $r34 g[$r4d+0xc] (8) 1241: $p2 mov u32 $r34 0x00000000 (8) 1242: neg f32 $r32 $r32 (8) 1243: add f32 $r6 $r6 $r32 (8) 1244: neg f32 $r32 $r33 (8) 1245: add f32 $r7 $r7 $r32 (8) 1246: neg f32 $r21 $r21 (8) 1247: add f32 $r21 $r31 $r21 (8) 1248: neg f32 $r22 $r22 (8) 1249: add f32 $r22 $r34 $r22 (8) 1250: cvt u8 $p3 $r37 (8) 1251: not $p3 st u32 # g[$r4d+0x0] $r6 (8) 1252: not $p0 st u32 # g[$r4d+0x4] $r7 (8) 1253: not $p1 st u32 # g[$r4d+0x8] $r21 (8) 1254: not $p2 st u32 # g[$r4d+0xc] $r22 (8) 1255: neg f32 $r4 $r27 (8) 1256: add f32 $r4 $r23 $r4 (8) 1257: neg f32 $r5 $r28 (8) 1258: add f32 $r5 $r24 $r5 (8) 1259: neg f32 $r6 $r29 (8) 1260: add f32 $r6 $r25 $r6 (8) 1261: neg f32 $r7 $r30 (8) 1262: add f32 $r7 $r26 $r7 (8) 1263: mul f32 $r21 $r4 $r4 (8) 1264: mad f32 $r21 $r5 $r5 $r21 (8) 1265: mad f32 $r21 $r6 $r6 $r21 (8) 1266: mad f32 $r21 $r7 $r7 $r21 (8) 1267: rsq f32 $r21 $r21 (8) 1268: rcp f32 $r21 $r21 (8) 1269: neg f32 $r22 $r21 (8) 1270: add f32 $r22 $r22 c0[0x30] (8) 1271: mul f32 $r22 $r22 0.350000 (8) 1272: rcp f32 $r21 $r21 (8) 1273: mul f32 $r21 $r22 $r21 (8) 1274: mul f32 $r4 $r21 $r4 (8) 1275: mul f32 $r5 $r21 $r5 (8) 1276: mul f32 $r6 $r21 $r6 (8) 1277: mul f32 $r7 $r21 $r7 (8) 1278: cvt u8 $p0 $r44 (8) 1279: not $p0 ld u32 $r21 g[$r0d+0x0] (8) 1280: $p0 mov u32 $r21 0x00000000 (8) 1281: cvt u8 $p0 $r42 (8) 1282: not $p0 ld u32 $r22 g[$r0d+0x4] (8) 1283: $p0 mov u32 $r22 0x00000000 (8) 1284: cvt u8 $p0 $r40 (8) 1285: not $p0 ld u32 $r23 g[$r0d+0x8] (8) 1286: $p0 mov u32 $r23 0x00000000 (8) 1287: cvt u8 $p0 $r38 (8) 1288: not $p0 ld u32 $r24 g[$r0d+0xc] (8) 1289: $p0 mov u32 $r24 0x00000000 (8) 1290: add f32 $r21 $r21 $r4 (8) 1291: add f32 $r22 $r22 $r5 (8) 1292: add f32 $r23 $r23 $r6 (8) 1293: add f32 $r24 $r24 $r7 (8) 1294: cvt u8 $p0 $r44 (8) 1295: not $p0 st u32 # g[$r0d+0x0] $r21 (8) 1296: cvt u8 $p0 $r42 (8) 1297: not $p0 st u32 # g[$r0d+0x4] $r22 (8) 1298: cvt u8 $p0 $r40 (8) 1299: not $p0 st u32 # g[$r0d+0x8] $r23 (8) 1300: cvt u8 $p0 $r38 (8) 1301: not $p0 st u32 # g[$r0d+0xc] $r24 (8) 1302: cvt u8 $p0 $r45 (8) 1303: not $p0 ld u32 $r0 g[$r2d+0x0] (8) 1304: $p0 mov u32 $r0 0x00000000 (8) 1305: cvt u8 $p0 $r43 (8) 1306: not $p0 ld u32 $r1 g[$r2d+0x4] (8) 1307: $p0 mov u32 $r1 0x00000000 (8) 1308: cvt u8 $p0 $r41 (8) 1309: not $p0 ld u32 $r21 g[$r2d+0x8] (8) 1310: $p0 mov u32 $r21 0x00000000 (8) 1311: cvt u8 $p0 $r39 (8) 1312: not $p0 ld u32 $r22 g[$r2d+0xc] (8) 1313: $p0 mov u32 $r22 0x00000000 (8) 1314: neg f32 $r4 $r4 (8) 1315: add f32 $r0 $r0 $r4 (8) 1316: neg f32 $r4 $r5 (8) 1317: add f32 $r1 $r1 $r4 (8) 1318: neg f32 $r4 $r6 (8) 1319: add f32 $r4 $r21 $r4 (8) 1320: neg f32 $r5 $r7 (8) 1321: add f32 $r5 $r22 $r5 (8) 1322: cvt u8 $p0 $r45 (8) 1323: not $p0 st u32 # g[$r2d+0x0] $r0 (8) 1324: cvt u8 $p0 $r43 (8) 1325: not $p0 st u32 # g[$r2d+0x4] $r1 (8) 1326: cvt u8 $p0 $r41 (8) 1327: not $p0 st u32 # g[$r2d+0x8] $r4 (8) 1328: cvt u8 $p0 $r39 (8) 1329: not $p0 st u32 # g[$r2d+0xc] $r5 (8) 1330: membar (SUBOP:7) - # (8) 1331: join BB:42 (8) BB:65 (1 instructions) - df = { } -> BB:42 (forward) 1332: join BB:42 (8) BB:42 (1 instructions) - idom = BB:40, df = { BB:43 } -> BB:43 (forward) 1333: join BB:43 (8) BB:64 (1 instructions) - df = { } -> BB:43 (forward) 1334: join BB:43 (8) BB:43 (3 instructions) - idom = BB:39, df = { BB:36 } -> BB:36 (back) 1335: bar u32 # $r255 $r255 (8) 1336: add u32 $r20 $r20 0x00000001 (8) 1337: bra BB:36 (8) BB:11 (6 instructions) - idom = BB:12, df = { } -> BB:67 (tree) -> BB:46 (tree) 1338: mov u32 $r16 0x00000000 (8) 1339: ld u32 $r0 c0[0x0] (8) 1340: add u32 $r0 $r0 0xffffffff (8) 1341: joinat BB:51 (8) 1342: set u8 $p0 lt s32 $r10 $r0 (8) 1343: not $p0 bra BB:67 (8) BB:46 (50 instructions) - idom = BB:11, df = { BB:51 } -> BB:71 (tree) -> BB:47 (tree) 1344: shl u32 $r0 $r8 0x00000004 (8) 1345: add u32 $r2 $r0 0x00000010 (8) 1346: add u32 { $r0 $c0 } $r2 c7[0x330] (8) 1347: add u32 $r1 $r255 c7[0x334] $c0 (8) 1348: add u32 $r3 $r2 0x00000004 (8) 1349: set u8 $p0 gt u32 $r3 c7[0x338] (8) 1350: not $p0 ld u32 $r3 g[$r0d+0x0] (8) 1351: $p0 mov u32 $r3 0x00000000 (8) 1352: add u32 $r4 $r2 0x00000008 (8) 1353: set u8 $p0 gt u32 $r4 c7[0x338] (8) 1354: not $p0 ld u32 $r4 g[$r0d+0x4] (8) 1355: $p0 mov u32 $r4 0x00000000 (8) 1356: add u32 $r2 $r2 0x0000000c (8) 1357: set u8 $p0 gt u32 $r2 c7[0x338] (8) 1358: not $p0 ld u32 $r2 g[$r0d+0x8] (8) 1359: $p0 mov u32 $r2 0x00000000 (8) 1360: shl u32 $r5 $r8 0x00000004 (8) 1361: add u32 { $r0 $c0 } $r5 c7[0x330] (8) 1362: add u32 $r1 $r255 c7[0x334] $c0 (8) 1363: add u32 $r6 $r5 0x00000004 (8) 1364: set u8 $p0 gt u32 $r6 c7[0x338] (8) 1365: not $p0 ld u32 $r6 g[$r0d+0x0] (8) 1366: $p0 mov u32 $r6 0x00000000 (8) 1367: add u32 $r7 $r5 0x00000008 (8) 1368: set u8 $p0 gt u32 $r7 c7[0x338] (8) 1369: not $p0 ld u32 $r7 g[$r0d+0x4] (8) 1370: $p0 mov u32 $r7 0x00000000 (8) 1371: add u32 $r5 $r5 0x0000000c (8) 1372: set u8 $p0 gt u32 $r5 c7[0x338] (8) 1373: not $p0 ld u32 $r0 g[$r0d+0x8] (8) 1374: $p0 mov u32 $r0 0x00000000 (8) 1375: neg f32 $r1 $r6 (8) 1376: add f32 $r1 $r3 $r1 (8) 1377: neg f32 $r3 $r7 (8) 1378: add f32 $r3 $r4 $r3 (8) 1379: neg f32 $r0 $r0 (8) 1380: add f32 $r0 $r2 $r0 (8) 1381: mul f32 $r2 $r1 $r1 (8) 1382: mad f32 $r2 $r3 $r3 $r2 (8) 1383: mad f32 $r2 $r0 $r0 $r2 (8) 1384: abs f32 $r2 $r2 (8) 1385: rsq f32 $r2 $r2 (8) 1386: mul f32 $r4 $r1 $r2 (8) 1387: mul f32 $r3 $r3 $r2 (8) 1388: mul f32 $r2 $r0 $r2 (8) 1389: ld u32 $r0 c0[0x0] (8) 1390: add u32 $r0 $r0 0xffffffff (8) 1391: joinat BB:48 (8) 1392: set u8 $p0 lt s32 $r9 $r0 (8) 1393: not $p0 bra BB:71 (8) BB:47 (63 instructions) - idom = BB:46, df = { BB:48 } -> BB:48 (forward) 1394: add u32 $r0 $r8 c0[0x0] (8) 1395: shl u32 $r5 $r0 0x00000004 (8) 1396: add u32 { $r0 $c0 } $r5 c7[0x330] (8) 1397: add u32 $r1 $r255 c7[0x334] $c0 (8) 1398: add u32 $r6 $r5 0x00000004 (8) 1399: set u8 $p0 gt u32 $r6 c7[0x338] (8) 1400: not $p0 ld u32 $r6 g[$r0d+0x0] (8) 1401: $p0 mov u32 $r6 0x00000000 (8) 1402: add u32 $r7 $r5 0x00000008 (8) 1403: set u8 $p0 gt u32 $r7 c7[0x338] (8) 1404: not $p0 ld u32 $r7 g[$r0d+0x4] (8) 1405: $p0 mov u32 $r7 0x00000000 (8) 1406: add u32 $r5 $r5 0x0000000c (8) 1407: set u8 $p0 gt u32 $r5 c7[0x338] (8) 1408: not $p0 ld u32 $r5 g[$r0d+0x8] (8) 1409: $p0 mov u32 $r5 0x00000000 (8) 1410: shl u32 $r11 $r8 0x00000004 (8) 1411: add u32 { $r0 $c0 } $r11 c7[0x330] (8) 1412: add u32 $r1 $r255 c7[0x334] $c0 (8) 1413: add u32 $r12 $r11 0x00000004 (8) 1414: set u8 $p0 gt u32 $r12 c7[0x338] (8) 1415: not $p0 ld u32 $r12 g[$r0d+0x0] (8) 1416: $p0 mov u32 $r12 0x00000000 (8) 1417: add u32 $r13 $r11 0x00000008 (8) 1418: set u8 $p0 gt u32 $r13 c7[0x338] (8) 1419: not $p0 ld u32 $r13 g[$r0d+0x4] (8) 1420: $p0 mov u32 $r13 0x00000000 (8) 1421: add u32 $r11 $r11 0x0000000c (8) 1422: set u8 $p0 gt u32 $r11 c7[0x338] (8) 1423: not $p0 ld u32 $r0 g[$r0d+0x8] (8) 1424: $p0 mov u32 $r0 0x00000000 (8) 1425: neg f32 $r1 $r12 (8) 1426: add f32 $r1 $r6 $r1 (8) 1427: neg f32 $r6 $r13 (8) 1428: add f32 $r6 $r7 $r6 (8) 1429: neg f32 $r0 $r0 (8) 1430: add f32 $r0 $r5 $r0 (8) 1431: mul f32 $r5 $r1 $r1 (8) 1432: mad f32 $r5 $r6 $r6 $r5 (8) 1433: mad f32 $r5 $r0 $r0 $r5 (8) 1434: abs f32 $r5 $r5 (8) 1435: rsq f32 $r5 $r5 (8) 1436: mul f32 $r1 $r1 $r5 (8) 1437: mul f32 $r6 $r6 $r5 (8) 1438: mul f32 $r0 $r0 $r5 (8) 1439: mul f32 $r5 $r0 $r3 (8) 1440: mul f32 $r7 $r1 $r2 (8) 1441: mul f32 $r11 $r6 $r4 (8) 1442: neg f32 $r5 $r5 (8) 1443: mad f32 $r5 $r6 $r2 $r5 (8) 1444: neg f32 $r6 $r7 (8) 1445: mad f32 $r0 $r0 $r4 $r6 (8) 1446: neg f32 $r6 $r11 (8) 1447: mad f32 $r1 $r1 $r3 $r6 (8) 1448: mul f32 $r6 $r5 $r5 (8) 1449: mad f32 $r6 $r0 $r0 $r6 (8) 1450: mad f32 $r6 $r1 $r1 $r6 (8) 1451: abs f32 $r6 $r6 (8) 1452: rsq f32 $r6 $r6 (8) 1453: mul f32 $r14 $r5 $r6 (8) 1454: mul f32 $r15 $r0 $r6 (8) 1455: mul f32 $r16 $r1 $r6 (8) 1456: join BB:48 (8) BB:71 (3 instructions) - df = { } -> BB:48 (forward) 1457: mov u32 $r14 $r16 (8) 1458: mov u32 $r15 $r16 (8) 1459: join BB:48 (8) BB:48 (3 instructions) - idom = BB:46, df = { BB:51 } -> BB:72 (tree) -> BB:49 (tree) 1460: joinat BB:50 (8) 1461: set u8 $p0 lt s32 $r255 $r9 (8) 1462: not $p0 bra BB:72 (8) BB:49 (64 instructions) - idom = BB:48, df = { BB:50 } -> BB:50 (forward) 1463: shl u32 $r5 $r8 0x00000004 (8) 1464: add u32 { $r0 $c0 } $r5 c7[0x330] (8) 1465: add u32 $r1 $r255 c7[0x334] $c0 (8) 1466: add u32 $r6 $r5 0x00000004 (8) 1467: set u8 $p0 gt u32 $r6 c7[0x338] (8) 1468: not $p0 ld u32 $r6 g[$r0d+0x0] (8) 1469: $p0 mov u32 $r6 0x00000000 (8) 1470: add u32 $r7 $r5 0x00000008 (8) 1471: set u8 $p0 gt u32 $r7 c7[0x338] (8) 1472: not $p0 ld u32 $r7 g[$r0d+0x4] (8) 1473: $p0 mov u32 $r7 0x00000000 (8) 1474: add u32 $r5 $r5 0x0000000c (8) 1475: set u8 $p0 gt u32 $r5 c7[0x338] (8) 1476: not $p0 ld u32 $r5 g[$r0d+0x8] (8) 1477: $p0 mov u32 $r5 0x00000000 (8) 1478: neg s32 $r0 c0[0x0] (8) 1479: add u32 $r0 $r8 $r0 (8) 1480: shl u32 $r11 $r0 0x00000004 (8) 1481: add u32 { $r0 $c0 } $r11 c7[0x330] (8) 1482: add u32 $r1 $r255 c7[0x334] $c0 (8) 1483: add u32 $r12 $r11 0x00000004 (8) 1484: set u8 $p0 gt u32 $r12 c7[0x338] (8) 1485: not $p0 ld u32 $r12 g[$r0d+0x0] (8) 1486: $p0 mov u32 $r12 0x00000000 (8) 1487: add u32 $r13 $r11 0x00000008 (8) 1488: set u8 $p0 gt u32 $r13 c7[0x338] (8) 1489: not $p0 ld u32 $r13 g[$r0d+0x4] (8) 1490: $p0 mov u32 $r13 0x00000000 (8) 1491: add u32 $r11 $r11 0x0000000c (8) 1492: set u8 $p0 gt u32 $r11 c7[0x338] (8) 1493: not $p0 ld u32 $r0 g[$r0d+0x8] (8) 1494: $p0 mov u32 $r0 0x00000000 (8) 1495: neg f32 $r1 $r12 (8) 1496: add f32 $r1 $r6 $r1 (8) 1497: neg f32 $r6 $r13 (8) 1498: add f32 $r6 $r7 $r6 (8) 1499: neg f32 $r0 $r0 (8) 1500: add f32 $r0 $r5 $r0 (8) 1501: mul f32 $r5 $r1 $r1 (8) 1502: mad f32 $r5 $r6 $r6 $r5 (8) 1503: mad f32 $r5 $r0 $r0 $r5 (8) 1504: abs f32 $r5 $r5 (8) 1505: rsq f32 $r5 $r5 (8) 1506: mul f32 $r1 $r1 $r5 (8) 1507: mul f32 $r6 $r6 $r5 (8) 1508: mul f32 $r0 $r0 $r5 (8) 1509: mul f32 $r5 $r0 $r3 (8) 1510: mul f32 $r7 $r1 $r2 (8) 1511: mul f32 $r11 $r6 $r4 (8) 1512: neg f32 $r5 $r5 (8) 1513: mad f32 $r2 $r6 $r2 $r5 (8) 1514: neg f32 $r5 $r7 (8) 1515: mad f32 $r0 $r0 $r4 $r5 (8) 1516: neg f32 $r4 $r11 (8) 1517: mad f32 $r1 $r1 $r3 $r4 (8) 1518: mul f32 $r3 $r2 $r2 (8) 1519: mad f32 $r3 $r0 $r0 $r3 (8) 1520: mad f32 $r3 $r1 $r1 $r3 (8) 1521: abs f32 $r3 $r3 (8) 1522: rsq f32 $r3 $r3 (8) 1523: mad f32 $r14 $r2 $r3 $r14 (8) 1524: mad f32 $r15 $r0 $r3 $r15 (8) 1525: mad f32 $r16 $r1 $r3 $r16 (8) 1526: join BB:50 (8) BB:72 (1 instructions) - df = { } -> BB:50 (forward) 1527: join BB:50 (8) BB:50 (1 instructions) - idom = BB:48, df = { BB:51 } -> BB:51 (forward) 1528: join BB:51 (8) BB:67 (3 instructions) - df = { } -> BB:51 (forward) 1529: mov u32 $r14 $r16 (8) 1530: mov u32 $r15 $r16 (8) 1531: join BB:51 (8) BB:51 (3 instructions) - idom = BB:11, df = { } -> BB:68 (tree) -> BB:52 (tree) 1532: joinat BB:57 (8) 1533: set u8 $p0 lt s32 $r255 $r10 (8) 1534: not $p0 bra BB:68 (8) BB:52 (50 instructions) - idom = BB:51, df = { BB:57 } -> BB:69 (tree) -> BB:53 (tree) 1535: shl u32 $r2 $r8 0x00000004 (8) 1536: add u32 { $r0 $c0 } $r2 c7[0x330] (8) 1537: add u32 $r1 $r255 c7[0x334] $c0 (8) 1538: add u32 $r3 $r2 0x00000004 (8) 1539: set u8 $p0 gt u32 $r3 c7[0x338] (8) 1540: not $p0 ld u32 $r3 g[$r0d+0x0] (8) 1541: $p0 mov u32 $r3 0x00000000 (8) 1542: add u32 $r4 $r2 0x00000008 (8) 1543: set u8 $p0 gt u32 $r4 c7[0x338] (8) 1544: not $p0 ld u32 $r4 g[$r0d+0x4] (8) 1545: $p0 mov u32 $r4 0x00000000 (8) 1546: add u32 $r2 $r2 0x0000000c (8) 1547: set u8 $p0 gt u32 $r2 c7[0x338] (8) 1548: not $p0 ld u32 $r2 g[$r0d+0x8] (8) 1549: $p0 mov u32 $r2 0x00000000 (8) 1550: shl u32 $r0 $r8 0x00000004 (8) 1551: add u32 $r5 $r0 0xfffffff0 (8) 1552: add u32 { $r0 $c0 } $r5 c7[0x330] (8) 1553: add u32 $r1 $r255 c7[0x334] $c0 (8) 1554: add u32 $r6 $r5 0x00000004 (8) 1555: set u8 $p0 gt u32 $r6 c7[0x338] (8) 1556: not $p0 ld u32 $r6 g[$r0d+0x0] (8) 1557: $p0 mov u32 $r6 0x00000000 (8) 1558: add u32 $r7 $r5 0x00000008 (8) 1559: set u8 $p0 gt u32 $r7 c7[0x338] (8) 1560: not $p0 ld u32 $r7 g[$r0d+0x4] (8) 1561: $p0 mov u32 $r7 0x00000000 (8) 1562: add u32 $r5 $r5 0x0000000c (8) 1563: set u8 $p0 gt u32 $r5 c7[0x338] (8) 1564: not $p0 ld u32 $r0 g[$r0d+0x8] (8) 1565: $p0 mov u32 $r0 0x00000000 (8) 1566: neg f32 $r1 $r6 (8) 1567: add f32 $r1 $r3 $r1 (8) 1568: neg f32 $r3 $r7 (8) 1569: add f32 $r3 $r4 $r3 (8) 1570: neg f32 $r0 $r0 (8) 1571: add f32 $r0 $r2 $r0 (8) 1572: mul f32 $r2 $r1 $r1 (8) 1573: mad f32 $r2 $r3 $r3 $r2 (8) 1574: mad f32 $r2 $r0 $r0 $r2 (8) 1575: abs f32 $r2 $r2 (8) 1576: rsq f32 $r2 $r2 (8) 1577: mul f32 $r4 $r1 $r2 (8) 1578: mul f32 $r3 $r3 $r2 (8) 1579: mul f32 $r2 $r0 $r2 (8) 1580: ld u32 $r0 c0[0x0] (8) 1581: add u32 $r0 $r0 0xffffffff (8) 1582: joinat BB:54 (8) 1583: set u8 $p0 lt s32 $r9 $r0 (8) 1584: not $p0 bra BB:69 (8) BB:53 (63 instructions) - idom = BB:52, df = { BB:54 } -> BB:54 (forward) 1585: add u32 $r0 $r8 c0[0x0] (8) 1586: shl u32 $r5 $r0 0x00000004 (8) 1587: add u32 { $r0 $c0 } $r5 c7[0x330] (8) 1588: add u32 $r1 $r255 c7[0x334] $c0 (8) 1589: add u32 $r6 $r5 0x00000004 (8) 1590: set u8 $p0 gt u32 $r6 c7[0x338] (8) 1591: not $p0 ld u32 $r6 g[$r0d+0x0] (8) 1592: $p0 mov u32 $r6 0x00000000 (8) 1593: add u32 $r7 $r5 0x00000008 (8) 1594: set u8 $p0 gt u32 $r7 c7[0x338] (8) 1595: not $p0 ld u32 $r7 g[$r0d+0x4] (8) 1596: $p0 mov u32 $r7 0x00000000 (8) 1597: add u32 $r5 $r5 0x0000000c (8) 1598: set u8 $p0 gt u32 $r5 c7[0x338] (8) 1599: not $p0 ld u32 $r5 g[$r0d+0x8] (8) 1600: $p0 mov u32 $r5 0x00000000 (8) 1601: shl u32 $r10 $r8 0x00000004 (8) 1602: add u32 { $r0 $c0 } $r10 c7[0x330] (8) 1603: add u32 $r1 $r255 c7[0x334] $c0 (8) 1604: add u32 $r11 $r10 0x00000004 (8) 1605: set u8 $p0 gt u32 $r11 c7[0x338] (8) 1606: not $p0 ld u32 $r11 g[$r0d+0x0] (8) 1607: $p0 mov u32 $r11 0x00000000 (8) 1608: add u32 $r12 $r10 0x00000008 (8) 1609: set u8 $p0 gt u32 $r12 c7[0x338] (8) 1610: not $p0 ld u32 $r12 g[$r0d+0x4] (8) 1611: $p0 mov u32 $r12 0x00000000 (8) 1612: add u32 $r10 $r10 0x0000000c (8) 1613: set u8 $p0 gt u32 $r10 c7[0x338] (8) 1614: not $p0 ld u32 $r0 g[$r0d+0x8] (8) 1615: $p0 mov u32 $r0 0x00000000 (8) 1616: neg f32 $r1 $r11 (8) 1617: add f32 $r1 $r6 $r1 (8) 1618: neg f32 $r6 $r12 (8) 1619: add f32 $r6 $r7 $r6 (8) 1620: neg f32 $r0 $r0 (8) 1621: add f32 $r0 $r5 $r0 (8) 1622: mul f32 $r5 $r1 $r1 (8) 1623: mad f32 $r5 $r6 $r6 $r5 (8) 1624: mad f32 $r5 $r0 $r0 $r5 (8) 1625: abs f32 $r5 $r5 (8) 1626: rsq f32 $r5 $r5 (8) 1627: mul f32 $r1 $r1 $r5 (8) 1628: mul f32 $r6 $r6 $r5 (8) 1629: mul f32 $r0 $r0 $r5 (8) 1630: mul f32 $r5 $r0 $r3 (8) 1631: mul f32 $r7 $r1 $r2 (8) 1632: mul f32 $r10 $r6 $r4 (8) 1633: neg f32 $r5 $r5 (8) 1634: mad f32 $r5 $r6 $r2 $r5 (8) 1635: neg f32 $r6 $r7 (8) 1636: mad f32 $r0 $r0 $r4 $r6 (8) 1637: neg f32 $r6 $r10 (8) 1638: mad f32 $r1 $r1 $r3 $r6 (8) 1639: mul f32 $r6 $r5 $r5 (8) 1640: mad f32 $r6 $r0 $r0 $r6 (8) 1641: mad f32 $r6 $r1 $r1 $r6 (8) 1642: abs f32 $r6 $r6 (8) 1643: rsq f32 $r6 $r6 (8) 1644: mad f32 $r14 $r5 $r6 $r14 (8) 1645: mad f32 $r15 $r0 $r6 $r15 (8) 1646: mad f32 $r16 $r1 $r6 $r16 (8) 1647: join BB:54 (8) BB:69 (1 instructions) - df = { } -> BB:54 (forward) 1648: join BB:54 (8) BB:54 (3 instructions) - idom = BB:52, df = { BB:57 } -> BB:70 (tree) -> BB:55 (tree) 1649: joinat BB:56 (8) 1650: set u8 $p0 lt s32 $r255 $r9 (8) 1651: not $p0 bra BB:70 (8) BB:55 (64 instructions) - idom = BB:54, df = { BB:56 } -> BB:56 (forward) 1652: shl u32 $r5 $r8 0x00000004 (8) 1653: add u32 { $r0 $c0 } $r5 c7[0x330] (8) 1654: add u32 $r1 $r255 c7[0x334] $c0 (8) 1655: add u32 $r6 $r5 0x00000004 (8) 1656: set u8 $p0 gt u32 $r6 c7[0x338] (8) 1657: not $p0 ld u32 $r6 g[$r0d+0x0] (8) 1658: $p0 mov u32 $r6 0x00000000 (8) 1659: add u32 $r7 $r5 0x00000008 (8) 1660: set u8 $p0 gt u32 $r7 c7[0x338] (8) 1661: not $p0 ld u32 $r7 g[$r0d+0x4] (8) 1662: $p0 mov u32 $r7 0x00000000 (8) 1663: add u32 $r5 $r5 0x0000000c (8) 1664: set u8 $p0 gt u32 $r5 c7[0x338] (8) 1665: not $p0 ld u32 $r5 g[$r0d+0x8] (8) 1666: $p0 mov u32 $r5 0x00000000 (8) 1667: neg s32 $r0 c0[0x0] (8) 1668: add u32 $r0 $r8 $r0 (8) 1669: shl u32 $r9 $r0 0x00000004 (8) 1670: add u32 { $r0 $c0 } $r9 c7[0x330] (8) 1671: add u32 $r1 $r255 c7[0x334] $c0 (8) 1672: add u32 $r10 $r9 0x00000004 (8) 1673: set u8 $p0 gt u32 $r10 c7[0x338] (8) 1674: not $p0 ld u32 $r10 g[$r0d+0x0] (8) 1675: $p0 mov u32 $r10 0x00000000 (8) 1676: add u32 $r11 $r9 0x00000008 (8) 1677: set u8 $p0 gt u32 $r11 c7[0x338] (8) 1678: not $p0 ld u32 $r11 g[$r0d+0x4] (8) 1679: $p0 mov u32 $r11 0x00000000 (8) 1680: add u32 $r9 $r9 0x0000000c (8) 1681: set u8 $p0 gt u32 $r9 c7[0x338] (8) 1682: not $p0 ld u32 $r0 g[$r0d+0x8] (8) 1683: $p0 mov u32 $r0 0x00000000 (8) 1684: neg f32 $r1 $r10 (8) 1685: add f32 $r1 $r6 $r1 (8) 1686: neg f32 $r6 $r11 (8) 1687: add f32 $r6 $r7 $r6 (8) 1688: neg f32 $r0 $r0 (8) 1689: add f32 $r0 $r5 $r0 (8) 1690: mul f32 $r5 $r1 $r1 (8) 1691: mad f32 $r5 $r6 $r6 $r5 (8) 1692: mad f32 $r5 $r0 $r0 $r5 (8) 1693: abs f32 $r5 $r5 (8) 1694: rsq f32 $r5 $r5 (8) 1695: mul f32 $r1 $r1 $r5 (8) 1696: mul f32 $r6 $r6 $r5 (8) 1697: mul f32 $r0 $r0 $r5 (8) 1698: mul f32 $r5 $r0 $r3 (8) 1699: mul f32 $r7 $r1 $r2 (8) 1700: mul f32 $r9 $r6 $r4 (8) 1701: neg f32 $r5 $r5 (8) 1702: mad f32 $r2 $r6 $r2 $r5 (8) 1703: neg f32 $r5 $r7 (8) 1704: mad f32 $r0 $r0 $r4 $r5 (8) 1705: neg f32 $r4 $r9 (8) 1706: mad f32 $r1 $r1 $r3 $r4 (8) 1707: mul f32 $r3 $r2 $r2 (8) 1708: mad f32 $r3 $r0 $r0 $r3 (8) 1709: mad f32 $r3 $r1 $r1 $r3 (8) 1710: abs f32 $r3 $r3 (8) 1711: rsq f32 $r3 $r3 (8) 1712: mad f32 $r14 $r2 $r3 $r14 (8) 1713: mad f32 $r15 $r0 $r3 $r15 (8) 1714: mad f32 $r16 $r1 $r3 $r16 (8) 1715: join BB:56 (8) BB:70 (1 instructions) - df = { } -> BB:56 (forward) 1716: join BB:56 (8) BB:56 (1 instructions) - idom = BB:54, df = { BB:57 } -> BB:57 (forward) 1717: join BB:57 (8) BB:68 (1 instructions) - df = { } -> BB:57 (forward) 1718: join BB:57 (8) BB:57 (21 instructions) - idom = BB:51, df = { } -> BB:1 (tree) 1719: shl u32 $r2 $r8 0x00000004 (8) 1720: mul f32 $r0 $r14 $r14 (8) 1721: mad f32 $r0 $r15 $r15 $r0 (8) 1722: mad f32 $r0 $r16 $r16 $r0 (8) 1723: abs f32 $r0 $r0 (8) 1724: rsq f32 $r0 $r0 (8) 1725: mul f32 $r3 $r14 $r0 (8) 1726: mul f32 $r4 $r15 $r0 (8) 1727: mul f32 $r5 $r16 $r0 (8) 1728: add u32 { $r0 $c0 } $r2 c7[0x310] (8) 1729: add u32 $r1 $r255 c7[0x314] $c0 (8) 1730: add u32 $r6 $r2 0x00000004 (8) 1731: set u8 $p0 gt u32 $r6 c7[0x318] (8) 1732: not $p0 st u32 # g[$r0d+0x0] $r3 (8) 1733: add u32 $r3 $r2 0x00000008 (8) 1734: set u8 $p0 gt u32 $r3 c7[0x318] (8) 1735: not $p0 st u32 # g[$r0d+0x4] $r4 (8) 1736: add u32 $r2 $r2 0x0000000c (8) 1737: set u8 $p0 gt u32 $r2 c7[0x318] (8) 1738: not $p0 st u32 # g[$r0d+0x8] $r5 (8) 1739: membar (SUBOP:7) - # (8) BB:1 (1 instructions) - idom = BB:57, df = { } 1740: exit - # (8) BB:37 (38 instructions) - idom = BB:38, df = { BB:10 } -> BB:66 (tree) -> BB:44 (tree) 1741: shl u32 $r2 $r8 0x00000004 (8) 1742: add u32 { $r0 $c0 } $r2 c7[0x330] (8) 1743: add u32 $r1 $r255 c7[0x334] $c0 (8) 1744: add u32 $r3 $r2 0x00000004 (8) 1745: set u8 $p0 gt u32 $r3 c7[0x338] (8) 1746: not $p0 ld u32 $r3 g[$r0d+0x0] (8) 1747: $p0 mov u32 $r3 0x00000000 (8) 1748: add u32 $r4 $r2 0x00000008 (8) 1749: set u8 $p0 gt u32 $r4 c7[0x338] (8) 1750: not $p0 ld u32 $r4 g[$r0d+0x4] (8) 1751: $p0 mov u32 $r4 0x00000000 (8) 1752: add u32 $r5 $r2 0x0000000c (8) 1753: set u8 $p0 gt u32 $r5 c7[0x338] (8) 1754: not $p0 ld u32 $r5 g[$r0d+0x8] (8) 1755: $p0 mov u32 $r5 0x00000000 (8) 1756: add u32 $r2 $r2 0x00000010 (8) 1757: set u8 $p0 gt u32 $r2 c7[0x338] (8) 1758: not $p0 ld u32 $r0 g[$r0d+0xc] (8) 1759: $p0 mov u32 $r0 0x00000000 (8) 1760: neg f32 $r1 c0[0x40] (8) 1761: add f32 $r1 $r3 $r1 (8) 1762: neg f32 $r2 c0[0x44] (8) 1763: add f32 $r2 $r4 $r2 (8) 1764: neg f32 $r3 c0[0x48] (8) 1765: add f32 $r3 $r5 $r3 (8) 1766: neg f32 $r4 c0[0x4c] (8) 1767: add f32 $r0 $r0 $r4 (8) 1768: mul f32 $r4 $r1 $r1 (8) 1769: mad f32 $r4 $r2 $r2 $r4 (8) 1770: mad f32 $r4 $r3 $r3 $r4 (8) 1771: mad f32 $r4 $r0 $r0 $r4 (8) 1772: rsq f32 $r4 $r4 (8) 1773: rcp f32 $r4 $r4 (8) 1774: ld u32 $r5 c0[0x50] (8) 1775: add f32 $r5 $r5 0.010000 (8) 1776: joinat BB:45 (8) 1777: set u8 $p0 lt f32 $r4 $r5 (8) 1778: not $p0 bra BB:66 (8) BB:44 (33 instructions) - idom = BB:37, df = { BB:45 } -> BB:45 (forward) 1779: shl u32 $r4 $r8 0x00000004 (8) 1780: mul f32 $r5 $r1 $r1 (8) 1781: mad f32 $r5 $r2 $r2 $r5 (8) 1782: mad f32 $r5 $r3 $r3 $r5 (8) 1783: mad f32 $r5 $r0 $r0 $r5 (8) 1784: abs f32 $r5 $r5 (8) 1785: rsq f32 $r5 $r5 (8) 1786: mul f32 $r1 $r1 $r5 (8) 1787: mul f32 $r2 $r2 $r5 (8) 1788: mul f32 $r3 $r3 $r5 (8) 1789: mul f32 $r0 $r0 $r5 (8) 1790: ld u32 $r5 c0[0x50] (8) 1791: add f32 $r5 $r5 0.010000 (8) 1792: mad f32 $r6 $r1 $r5 c0[0x40] (8) 1793: mad f32 $r2 $r2 $r5 c0[0x44] (8) 1794: mad f32 $r3 $r3 $r5 c0[0x48] (8) 1795: mad f32 $r5 $r0 $r5 c0[0x4c] (8) 1796: add u32 { $r0 $c0 } $r4 c7[0x330] (8) 1797: add u32 $r1 $r255 c7[0x334] $c0 (8) 1798: add u32 $r7 $r4 0x00000004 (8) 1799: set u8 $p0 gt u32 $r7 c7[0x338] (8) 1800: not $p0 st u32 # g[$r0d+0x0] $r6 (8) 1801: add u32 $r6 $r4 0x00000008 (8) 1802: set u8 $p0 gt u32 $r6 c7[0x338] (8) 1803: not $p0 st u32 # g[$r0d+0x4] $r2 (8) 1804: add u32 $r2 $r4 0x0000000c (8) 1805: set u8 $p0 gt u32 $r2 c7[0x338] (8) 1806: not $p0 st u32 # g[$r0d+0x8] $r3 (8) 1807: add u32 $r2 $r4 0x00000010 (8) 1808: set u8 $p0 gt u32 $r2 c7[0x338] (8) 1809: not $p0 st u32 # g[$r0d+0xc] $r5 (8) 1810: membar (SUBOP:7) - # (8) 1811: join BB:45 (8) BB:66 (1 instructions) - df = { } -> BB:45 (forward) 1812: join BB:45 (8) BB:45 (3 instructions) - idom = BB:37, df = { BB:10 } -> BB:10 (back) 1813: bar u32 # $r255 $r255 (8) 1814: add u32 $r12 $r12 0x00000001 (8) 1815: bra BB:10 (8) 3708: message: shader compiler issue 1: type: 5, local: 0, gpr: 46, inst: 1816, bytes: 16608 shader binary code (0x40e0 bytes): 10a08010 088010a0 129c0002 86400000 001fc006 74000002 109c000a 86400000 009c0022 d0000800 001c0012 64c03c00 041c0002 e4c03c00 021c0006 e4c03c00 1080109c 08a0109c 78000000 110007fe 009c002a e4c03c00 041c0002 e4c03c00 021c0006 e4c03c00 78000000 110007fe 001c0026 e4c03c00 021c2009 c2400000 b0a010b0 08a08010 641c0802 608400e0 649ffc06 608040e0 021c080d c0800000 651c0c1e 5b401ce0 0020000c c4800000 0003c00e 74000000 041c0811 c0800000 a08010b0 088010b0 651c101e 5b401ce0 02200010 c4800000 0003c012 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cc001000 029c1012 84000000 021c1012 84000000 0a1c0016 64c03c00 851c1414 401e11eb a8000000 14800000 029c101e dd881c00 a0a01080 08a0a0a0 9420003c 12000000 021c2011 c2400000 009c0416 e3400000 011c0816 cc001400 019c0c16 cc001400 001c0016 cc001400 029c2816 e5500000 108010a0 08a0a080 029c1416 84000000 029c0406 e3400000 029c080a e3400000 029c0c0e e3400000 029c0002 e3400000 0a1c0016 64c03c00 851c1414 401e11eb 80108010 08a010b0 081c041a 8c001400 089c080a 8c001400 091c0c0e 8c001400 099c0016 8c001400 661c1002 608400e0 669ffc06 608040e0 021c101d c0800000 b0a010b0 08b0a010 671c1c1e 5b401ce0 00200018 e4800000 041c1019 c0800000 671c181e 5b401ce0 02200008 e4800000 061c1009 c0800000 671c081e 5b401ce0 10b0a010 08000080 0420000c e4800000 081c1009 c0800000 671c081e 5b401ce0 06200014 e4800000 001c0402 7cc00000 005c3c02 85800000 005c3c02 85800000 009c8010 08000000 7f9ffc02 85401c00 009c3031 c0800000 601c003c 12007fe3 COMPUTE LAUNCH DESCRIPTOR: ... [1c]: 0xbc000000 [20]: 0x000fb600 ... [2c]: 0x44014000 [30]: 0x00000001 [34]: 0x00010001 ... [48]: 0x04000000 [4c]: 0x00010001 [50]: 0x20000081 ... [74]: 0x003d0000 [78]: 0x80000000 ... [ac]: 0x003e2800 [b0]: 0x04000000 [b4]: 0x08000000 [b8]: 0x2e000000 [bc]: 0x30000800 ... entry = 0xfb600 grid dimensions = 1x1x1 block dimensions = 1024x1x1 s[] size: 0x0 l[] size: -0x0 / +0x0 stack size: 0x800 barrier count: 1 $r count: 46 cache split: 16K_SHARED_48K_L1 CB[0]: address = 0x3d0000, size 0x10000 CB[7]: address = 0x3e2800, size 0x800 HDR[00] = 0x00020461 HDR[04] = 0x00000000 HDR[08] = 0x00000000 HDR[0c] = 0x00000000 HDR[10] = 0x000ff000 HDR[14] = 0x00000000 HDR[18] = 0x0000007f HDR[1c] = 0x00000000 HDR[20] = 0x00000000 HDR[24] = 0x00000000 HDR[28] = 0x00000000 HDR[2c] = 0x00000000 HDR[30] = 0x00000000 HDR[34] = 0x000ff000 HDR[38] = 0x00000000 HDR[3c] = 0x00000000 HDR[40] = 0x00000000 HDR[44] = 0x00000000 HDR[48] = 0x00000000 HDR[4c] = 0x00000000 shader binary code (0x178 bytes): 108010dc 0810dc80 401ffc02 7ec3fc00 001c0006 63408000 009c000a 63408000 011c000e 63408000 019c0002 63408000 421ffc12 7ec3fc00 021c1006 4d000400 dc801080 08108010 029c100a 4d000800 031c100e 4d000c00 039c1002 4d000000 441ffc12 7ec3fc00 041c1006 4d000400 049c100a 4d000800 051c100e 4d000c00 8010dc80 08dc8010 059c1002 4d000000 461ffc12 7ec3fc00 061c1006 4d000400 069c100a 4d000800 071c100e 4d000c00 079c1002 4d000000 481ffc12 7ec3fc00 dc108010 08108010 081c1016 63408000 089c101a 63408000 091c1012 63408000 4a1ffc1e 7ec3fc00 0a1c1c16 4d001400 0a9c1c1a 4d001800 0b1c1c12 4d001000 9c8010dc 090d0c8c 4c1ffc1e 7ec3fc00 0c1c1c16 4d001400 0c9c1c1a 4d001800 0d1c1c12 4d001000 401ffc16 7f03fc00 421ffc1a 7f03fc00 441ffc12 7f03fc00 0d0d0d0c 08013811 461ffc22 7f03fc00 381ffc06 7f03fc00 3a1ffc0a 7f03fc00 3c1ffc0e 7f03fc00 3e1ffc02 7f03fc00 001c003c 18000000 HDR[00] = 0x00021462 HDR[04] = 0x00000000 HDR[08] = 0x00000000 HDR[0c] = 0x00000000 HDR[10] = 0x00000000 HDR[14] = 0x80000000 HDR[18] = 0x0000002a HDR[1c] = 0x00000000 HDR[20] = 0x00000000 HDR[24] = 0x00000000 HDR[28] = 0x00000000 HDR[2c] = 0x00000000 HDR[30] = 0x00000000 HDR[34] = 0x00000000 HDR[38] = 0x00000000 HDR[3c] = 0x00000000 HDR[40] = 0x00000000 HDR[44] = 0x00000000 HDR[48] = 0x0000000f HDR[4c] = 0x00000000 shader binary code (0xd0 bytes): 10b8a0b8 08b810b8 7f9ffc02 7483fc3e 021c0002 84000000 001ffc06 74a3fc40 009c040a e3408000 001ffc0e 74a3fc42 019c0c0a cd000800 001ffc02 74a3fc44 10a0a0a0 08a09c80 001c000a cd000800 011c280a e5508000 029c080a 84000000 011c0406 e3408000 011c0c0e e3408000 011c0002 e3408000 001c0406 63408000 10a0a0a0 08801080 009c0c06 4d000400 011c0002 4d000400 001c280e e5508000 021c0c02 63408000 029c0c06 63408000 031c0c0a 63408000 039c0c0e 63408000 000000b8 08000000 001c003c 18000000 COMPUTE LAUNCH DESCRIPTOR: ... [1c]: 0xbc000000 [20]: 0x000fb600 ... [2c]: 0x44014000 [30]: 0x00000001 [34]: 0x00010001 ... [48]: 0x04000000 [4c]: 0x00010001 [50]: 0x20000081 ... [74]: 0x003d0000 [78]: 0x80000000 ... [ac]: 0x003e2800 [b0]: 0x04000000 [b4]: 0x08000000 [b8]: 0x2e000000 [bc]: 0x30000800 ... entry = 0xfb600 grid dimensions = 1x1x1 block dimensions = 1024x1x1 s[] size: 0x0 l[] size: -0x0 / +0x0 stack size: 0x800 barrier count: 1 $r count: 46 cache split: 16K_SHARED_48K_L1 CB[0]: address = 0x3d0000, size 0x10000 CB[7]: address = 0x3e2800, size 0x800