[ 0.000000] Linux version 4.7.0-rc4-nightly+ (jenkins@vanaheimr) (gcc version 4.8.4 (Ubuntu 4.8.4-2ubuntu1~14.04.3) ) #2 SMP Fri Jun 24 02:05:40 CEST 2016 [ 0.000000] Command line: vmlinuz root=UUID=45362519-b952-45da-b977-424d472f4281 initrd=/initrd initcall_debug drm.debug=0xe log_buf_len=10M [ 0.000000] KERNEL supported cpus: [ 0.000000] Intel GenuineIntel [ 0.000000] AMD AuthenticAMD [ 0.000000] Centaur CentaurHauls [ 0.000000] x86/fpu: xstate_offset[3]: 960, xstate_sizes[3]: 64 [ 0.000000] x86/fpu: xstate_offset[4]: 1024, xstate_sizes[4]: 64 [ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR' [ 0.000000] x86/fpu: Enabled xstate features 0x1b, context size is 1088 bytes, using 'standard' format. [ 0.000000] x86/fpu: Using 'eager' FPU context switches. [ 0.000000] e820: BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable [ 0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000000059000-0x000000000009dfff] usable [ 0.000000] BIOS-e820: [mem 0x000000000009e000-0x00000000000fffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000000effffff] usable [ 0.000000] BIOS-e820: [mem 0x000000000f000000-0x0000000012151fff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000012152000-0x0000000077ff8fff] usable [ 0.000000] BIOS-e820: [mem 0x0000000077ff9000-0x0000000079da8fff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000079da9000-0x0000000079e08fff] ACPI NVS [ 0.000000] BIOS-e820: [mem 0x0000000079e09000-0x0000000079e38fff] ACPI data [ 0.000000] BIOS-e820: [mem 0x0000000079e39000-0x000000007ac2bfff] usable [ 0.000000] BIOS-e820: [mem 0x000000007ac2c000-0x000000007ac2cfff] ACPI NVS [ 0.000000] BIOS-e820: [mem 0x000000007ac2d000-0x000000007ac56fff] reserved [ 0.000000] BIOS-e820: [mem 0x000000007ac57000-0x000000007affffff] usable [ 0.000000] BIOS-e820: [mem 0x000000007b000000-0x000000007fffffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000e3ffffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000fed01000-0x00000000fed01fff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000027fffffff] usable [ 0.000000] NX (Execute Disable) protection: active [ 0.000000] efi: EFI v2.50 by EDK II [ 0.000000] efi: ACPI=0x79e38000 ACPI 2.0=0x79e38014 ESRT=0x79d74000 SMBIOS=0x7815a000 SMBIOS 3.0=0x78158000 PROP=0x7a06c920 [ 0.000000] efi: requested map not found. [ 0.000000] esrt: ESRT header is not in the memory map. [ 0.000000] SMBIOS 3.0.0 present. [ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved [ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable [ 0.000000] e820: last_pfn = 0x280000 max_arch_pfn = 0x400000000 [ 0.000000] MTRR default type: uncachable [ 0.000000] MTRR fixed ranges enabled: [ 0.000000] 00000-9FFFF write-back [ 0.000000] A0000-BFFFF uncachable [ 0.000000] C0000-FFFFF write-protect [ 0.000000] MTRR variable ranges enabled: [ 0.000000] 0 base 0000000000 mask 7F80000000 write-back [ 0.000000] 1 base 007C000000 mask 7FFC000000 uncachable [ 0.000000] 2 base 007B000000 mask 7FFF000000 uncachable [ 0.000000] 3 base 0100000000 mask 7F00000000 write-back [ 0.000000] 4 base 0200000000 mask 7F80000000 write-back [ 0.000000] 5 base 00FF800000 mask 70FF800000 write-combining [ 0.000000] 6 disabled [ 0.000000] 7 disabled [ 0.000000] 8 disabled [ 0.000000] 9 disabled [ 0.000000] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WC UC- WT [ 0.000000] e820: last_pfn = 0x7b000 max_arch_pfn = 0x400000000 [ 0.000000] Scanning 1 areas for low memory corruption [ 0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576 [ 0.000000] Using GB pages for direct mapping [ 0.000000] BRK [0x02013000, 0x02013fff] PGTABLE [ 0.000000] BRK [0x02014000, 0x02014fff] PGTABLE [ 0.000000] BRK [0x02015000, 0x02015fff] PGTABLE [ 0.000000] BRK [0x02016000, 0x02016fff] PGTABLE [ 0.000000] BRK [0x02017000, 0x02017fff] PGTABLE [ 0.000000] BRK [0x02018000, 0x02018fff] PGTABLE [ 0.000000] log_buf_len: 16777216 bytes [ 0.000000] early log buf free: 257568(98%) [ 0.000000] RAMDISK: [mem 0x72928000-0x74d97fff] [ 0.000000] ACPI: Early table checksum verification disabled [ 0.000000] ACPI: RSDP 0x0000000079E38014 000024 (v02 INTEL ) [ 0.000000] ACPI: XSDT 0x0000000079E10188 0000E4 (v01 INTEL EDK2 00000003 BRXT 01000013) [ 0.000000] ACPI: FACP 0x0000000079E30000 00010C (v05 INTEL EDK2 00000003 BRXT 0100000D) [ 0.000000] ACPI BIOS Warning (bug): 32/64X length mismatch in FADT/Pm1aEventBlock: 32/16 (20160422/tbfadt-624) [ 0.000000] ACPI BIOS Warning (bug): Invalid length for FADT/Pm1aEventBlock: 16, using default 32 (20160422/tbfadt-708) [ 0.000000] ACPI: DSDT 0x0000000079E22000 008C82 (v02 INTEL EDK2 00000003 BRXT 0100000D) [ 0.000000] ACPI: FACS 0x0000000079DF7000 000040 [ 0.000000] ACPI: SSDT 0x0000000079E36000 0003C6 (v02 INTEL Tpm2Tabl 00001000 INTL 20150818) [ 0.000000] ACPI: TPM2 0x0000000079E35000 000034 (v03 00000000 00000000) [ 0.000000] ACPI: UEFI 0x0000000079DFF000 000042 (v01 INTEL EDK2 00000002 BRXT 01000013) [ 0.000000] ACPI: BDAT 0x0000000079E34000 000030 (v02 00000000 00000000) [ 0.000000] ACPI: DBG2 0x0000000079E33000 000072 (v00 INTEL EDK2 00000003 BRXT 0100000D) [ 0.000000] ACPI: DBGP 0x0000000079E32000 000034 (v01 INTEL EDK2 00000003 BRXT 0100000D) [ 0.000000] ACPI: HPET 0x0000000079E2F000 000038 (v01 INTEL EDK2 00000003 BRXT 0100000D) [ 0.000000] ACPI: LPIT 0x0000000079E2E000 00005C (v01 INTEL EDK2 00000003 BRXT 0100000D) [ 0.000000] ACPI: APIC 0x0000000079E2D000 000084 (v03 INTEL EDK2 00000003 BRXT 0100000D) [ 0.000000] ACPI: MCFG 0x0000000079E2C000 00003C (v01 INTEL EDK2 00000003 BRXT 0100000D) [ 0.000000] ACPI: NPKT 0x0000000079E2B000 000065 (v01 INTEL EDK2 00000003 BRXT 0100000D) [ 0.000000] ACPI: SSDT 0x0000000079E18000 004549 (v02 INTEL RVPRtd3 00000003 BRXT 0100000D) [ 0.000000] ACPI: SSDT 0x0000000079E17000 000B53 (v02 INTEL UsbCTabl 00000003 BRXT 0100000D) [ 0.000000] ACPI: SSDT 0x0000000079E16000 000079 (v02 Intel_ IrmtTabl 00001000 INTL 20150818) [ 0.000000] ACPI: SSDT 0x0000000079E14000 001659 (v01 Intel_ Platform 00001000 INTL 20150818) [ 0.000000] ACPI: SSDT 0x0000000079E13000 000400 (v02 PmRef Cpu0Ist 00003000 INTL 20150818) [ 0.000000] ACPI: SSDT 0x0000000079E12000 00072B (v02 CpuRef CpuSsdt 00003000 INTL 20150818) [ 0.000000] ACPI: SSDT 0x0000000079E11000 000356 (v02 PmRef Cpu0Tst 00003000 INTL 20150818) [ 0.000000] ACPI: SSDT 0x0000000079E37000 00017C (v02 PmRef ApTst 00003000 INTL 20150818) [ 0.000000] ACPI: SSDT 0x0000000079E0D000 0027E6 (v02 SaSsdt SaSsdt 00003000 INTL 20150818) [ 0.000000] ACPI: FPDT 0x0000000079E0C000 000044 (v01 INTEL EDK2 00000002 BRXT 01000013) [ 0.000000] ACPI: WDAT 0x0000000079E31000 000104 (v01 00000000 00000000) [ 0.000000] ACPI: NHLT 0x0000000079E20000 001A50 (v00 INTEL EDK2 00000002 BRXT 01000013) [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] No NUMA configuration found [ 0.000000] Faking a node at [mem 0x0000000000000000-0x000000027fffffff] [ 0.000000] NODE_DATA(0) allocated [mem 0x27effa000-0x27effdfff] [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000000001000-0x0000000000ffffff] [ 0.000000] DMA32 [mem 0x0000000001000000-0x00000000ffffffff] [ 0.000000] Normal [mem 0x0000000100000000-0x000000027fffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000000001000-0x0000000000057fff] [ 0.000000] node 0: [mem 0x0000000000059000-0x000000000009dfff] [ 0.000000] node 0: [mem 0x0000000000100000-0x000000000effffff] [ 0.000000] node 0: [mem 0x0000000012152000-0x0000000077ff8fff] [ 0.000000] node 0: [mem 0x0000000079e39000-0x000000007ac2bfff] [ 0.000000] node 0: [mem 0x000000007ac57000-0x000000007affffff] [ 0.000000] node 0: [mem 0x0000000100000000-0x000000027fffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000027fffffff] [ 0.000000] On node 0 totalpages: 2056159 [ 0.000000] DMA zone: 64 pages used for memmap [ 0.000000] DMA zone: 21 pages reserved [ 0.000000] DMA zone: 3996 pages, LIFO batch:0 [ 0.000000] DMA32 zone: 7490 pages used for memmap [ 0.000000] DMA32 zone: 479299 pages, LIFO batch:31 [ 0.000000] Normal zone: 24576 pages used for memmap [ 0.000000] Normal zone: 1572864 pages, LIFO batch:31 [ 0.000000] Reserving Intel graphics memory at 0x000000007c000000-0x000000007fffffff [ 0.000000] ACPI: PM-Timer IO Port: 0x408 [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high level lint[0x1]) [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high level lint[0x1]) [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high level lint[0x1]) [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high level lint[0x1]) [ 0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-119 [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) [ 0.000000] ACPI: IRQ0 used by override. [ 0.000000] ACPI: IRQ9 used by override. [ 0.000000] Using ACPI (MADT) for SMP configuration information [ 0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000 [ 0.000000] smpboot: Allowing 4 CPUs, 0 hotplug CPUs [ 0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff] [ 0.000000] PM: Registered nosave memory: [mem 0x00058000-0x00058fff] [ 0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x000fffff] [ 0.000000] PM: Registered nosave memory: [mem 0x0f000000-0x12151fff] [ 0.000000] PM: Registered nosave memory: [mem 0x77ff9000-0x79da8fff] [ 0.000000] PM: Registered nosave memory: [mem 0x79da9000-0x79e08fff] [ 0.000000] PM: Registered nosave memory: [mem 0x79e09000-0x79e38fff] [ 0.000000] PM: Registered nosave memory: [mem 0x7ac2c000-0x7ac2cfff] [ 0.000000] PM: Registered nosave memory: [mem 0x7ac2d000-0x7ac56fff] [ 0.000000] PM: Registered nosave memory: [mem 0x7b000000-0x7fffffff] [ 0.000000] PM: Registered nosave memory: [mem 0x80000000-0xdfffffff] [ 0.000000] PM: Registered nosave memory: [mem 0xe0000000-0xe3ffffff] [ 0.000000] PM: Registered nosave memory: [mem 0xe4000000-0xfed00fff] [ 0.000000] PM: Registered nosave memory: [mem 0xfed01000-0xfed01fff] [ 0.000000] PM: Registered nosave memory: [mem 0xfed02000-0xffffffff] [ 0.000000] e820: [mem 0x80000000-0xdfffffff] available for PCI devices [ 0.000000] Booting paravirtualized kernel on bare hardware [ 0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns [ 0.000000] setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:4 nr_node_ids:1 [ 0.000000] percpu: Embedded 35 pages/cpu @ffff88027ec00000 s102744 r8192 d32424 u524288 [ 0.000000] pcpu-alloc: s102744 r8192 d32424 u524288 alloc=1*2097152 [ 0.000000] pcpu-alloc: [0] 0 1 2 3 [ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 2024008 [ 0.000000] Policy zone: Normal [ 0.000000] Kernel command line: vmlinuz root=UUID=45362519-b952-45da-b977-424d472f4281 initrd=/initrd initcall_debug drm.debug=0xe log_buf_len=10M [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) [ 0.000000] Calgary: detecting Calgary via BIOS EBDA area [ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing! [ 0.000000] Memory: 7913588K/8224636K available (7829K kernel code, 1311K rwdata, 3620K rodata, 1508K init, 1308K bss, 311048K reserved, 0K cma-reserved) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 [ 0.000000] Hierarchical RCU implementation. [ 0.000000] Build-time adjustment of leaf fanout to 64. [ 0.000000] RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=4. [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=4 [ 0.000000] NR_IRQS:16640 nr_irqs:1024 16 [ 0.000000] Offload RCU callbacks from all CPUs [ 0.000000] Offload RCU callbacks from CPUs: 0-3. [ 0.000000] WARNING: Persistent clock returned invalid value! Check your CMOS/BIOS settings. [ 0.000000] Console: colour dummy device 80x25 [ 0.000000] console [tty0] enabled [ 0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 99544814920 ns [ 0.000000] hpet clockevent registered [ 0.000000] tsc: Fast TSC calibration using PIT [ 0.000000] tsc: Detected 4438.004 MHz processor [ 0.000024] Calibrating delay loop (skipped), value calculated using timer frequency.. 8876.00 BogoMIPS (lpj=17752016) [ 0.000028] pid_max: default: 32768 minimum: 301 [ 0.000034] ACPI: Core revision 20160422 [ 0.000272] Security Framework initialized [ 0.000275] Yama: becoming mindful. [ 0.000280] AppArmor: AppArmor initialized [ 0.000573] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes) [ 0.001769] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes) [ 0.002298] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes) [ 0.002306] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes) [ 0.002463] CPU: Physical Processor ID: 0 [ 0.002467] CPU: Processor Core ID: 0 [ 0.002475] mce: CPU supports 7 MCE banks [ 0.002486] CPU0: Thermal monitoring enabled (TM1) [ 0.002510] Last level iTLB entries: 4KB 48, 2MB 0, 4MB 0 [ 0.002512] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0 [ 0.003300] Freeing SMP alternatives memory: 32K (ffffffff81ec2000 - ffffffff81eca000) [ 0.007538] ftrace: allocating 31359 entries in 123 pages [ 0.026319] smpboot: Max logical packages: 1 [ 0.026323] smpboot: APIC(0) Converting physical 0 to logical package 0 [ 0.026655] x2apic: IRQ remapping doesn't support X2APIC mode [ 0.027970] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 [ 0.067658] TSC deadline timer enabled [ 0.067662] smpboot: CPU0: Intel 06/5c (family: 0x6, model: 0x5c, stepping: 0x9) [ 0.067669] calling trace_init_flags_sys_exit+0x0/0xf @ 1 [ 0.067671] initcall trace_init_flags_sys_exit+0x0/0xf returned 0 after 0 usecs [ 0.067672] calling trace_init_flags_sys_enter+0x0/0xf @ 1 [ 0.067673] initcall trace_init_flags_sys_enter+0x0/0xf returned 0 after 0 usecs [ 0.067674] calling init_hw_perf_events+0x0/0x50e @ 1 [ 0.067675] Performance Events: PEBS fmt3+, 32-deep LBR, Goldmont events, full-width counters, Intel PMU driver. [ 0.067686] ... version: 4 [ 0.067687] ... bit width: 48 [ 0.067689] ... generic registers: 4 [ 0.067691] ... value mask: 0000ffffffffffff [ 0.067693] ... max period: 0000ffffffffffff [ 0.067695] ... fixed-purpose events: 3 [ 0.067696] ... event mask: 000000070000000f [ 0.067706] initcall init_hw_perf_events+0x0/0x50e returned 0 after 0 usecs [ 0.067708] calling xen_init_spinlocks_jump+0x0/0x29 @ 1 [ 0.067710] initcall xen_init_spinlocks_jump+0x0/0x29 returned 0 after 0 usecs [ 0.067711] calling set_real_mode_permissions+0x0/0x9a @ 1 [ 0.067715] initcall set_real_mode_permissions+0x0/0x9a returned 0 after 0 usecs [ 0.067717] calling trace_init_perf_perm_irq_work_exit+0x0/0x13 @ 1 [ 0.067718] initcall trace_init_perf_perm_irq_work_exit+0x0/0x13 returned 0 after 0 usecs [ 0.067720] calling register_trigger_all_cpu_backtrace+0x0/0x16 @ 1 [ 0.067721] initcall register_trigger_all_cpu_backtrace+0x0/0x16 returned 0 after 0 usecs [ 0.067722] calling numachip_system_init+0x0/0x67 @ 1 [ 0.067723] initcall numachip_system_init+0x0/0x67 returned 0 after 0 usecs [ 0.067724] calling kvm_spinlock_init_jump+0x0/0x34 @ 1 [ 0.067725] initcall kvm_spinlock_init_jump+0x0/0x34 returned 0 after 0 usecs [ 0.067727] calling early_efi_map_fb+0x0/0x32 @ 1 [ 0.067728] initcall early_efi_map_fb+0x0/0x32 returned 0 after 0 usecs [ 0.067729] calling spawn_ksoftirqd+0x0/0x2d @ 1 [ 0.067742] initcall spawn_ksoftirqd+0x0/0x2d returned 0 after 0 usecs [ 0.067744] calling init_workqueues+0x0/0x547 @ 1 [ 0.067789] initcall init_workqueues+0x0/0x547 returned 0 after 0 usecs [ 0.067791] calling migration_init+0x0/0x3e @ 1 [ 0.067792] initcall migration_init+0x0/0x3e returned 0 after 0 usecs [ 0.067793] calling check_cpu_stall_init+0x0/0x1b @ 1 [ 0.067794] initcall check_cpu_stall_init+0x0/0x1b returned 0 after 0 usecs [ 0.067795] calling rcu_spawn_gp_kthread+0x0/0x137 @ 1 [ 0.067824] initcall rcu_spawn_gp_kthread+0x0/0x137 returned 0 after 0 usecs [ 0.067826] calling cpu_stop_init+0x0/0x9b @ 1 [ 0.067836] initcall cpu_stop_init+0x0/0x9b returned 0 after 0 usecs [ 0.067838] calling relay_init+0x0/0x14 @ 1 [ 0.067840] initcall relay_init+0x0/0x14 returned 0 after 0 usecs [ 0.067841] calling init_events+0x0/0x60 @ 1 [ 0.067845] initcall init_events+0x0/0x60 returned 0 after 0 usecs [ 0.067846] calling init_trace_printk+0x0/0x12 @ 1 [ 0.067848] initcall init_trace_printk+0x0/0x12 returned 0 after 0 usecs [ 0.067849] calling event_trace_enable_again+0x0/0x24 @ 1 [ 0.067850] initcall event_trace_enable_again+0x0/0x24 returned 0 after 0 usecs [ 0.067852] calling jump_label_init_module+0x0/0x12 @ 1 [ 0.067853] initcall jump_label_init_module+0x0/0x12 returned 0 after 0 usecs [ 0.067854] calling lru_init+0x0/0x4e @ 1 [ 0.067866] initcall lru_init+0x0/0x4e returned 0 after 0 usecs [ 0.067868] calling dynamic_debug_init+0x0/0x272 @ 1 [ 0.068080] initcall dynamic_debug_init+0x0/0x272 returned 0 after 0 usecs [ 0.068082] calling rand_initialize+0x0/0x40 @ 1 [ 0.068130] initcall rand_initialize+0x0/0x40 returned 0 after 0 usecs [ 0.068199] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter. [ 0.068292] x86: Booting SMP configuration: [ 0.068295] .... node #0, CPUs: #1 #2 #3 [ 0.309761] x86: Booted up 1 node, 4 CPUs [ 0.309765] smpboot: Total of 4 processors activated (35511.41 BogoMIPS) [ 0.310663] devtmpfs: initialized [ 0.310704] x86/mm: Memory block size: 128MB [ 0.313861] calling ipc_ns_init+0x0/0x48 @ 1 [ 0.313862] initcall ipc_ns_init+0x0/0x48 returned 0 after 0 usecs [ 0.313864] calling init_mmap_min_addr+0x0/0x16 @ 1 [ 0.313865] initcall init_mmap_min_addr+0x0/0x16 returned 0 after 0 usecs [ 0.313866] calling evm_display_config+0x0/0x2d @ 1 [ 0.313867] evm: security.selinux [ 0.313869] evm: security.SMACK64 [ 0.313871] evm: security.ima [ 0.313873] evm: security.capability [ 0.313875] initcall evm_display_config+0x0/0x2d returned 0 after 0 usecs [ 0.313876] calling init_cpufreq_transition_notifier_list+0x0/0x1b @ 1 [ 0.313879] initcall init_cpufreq_transition_notifier_list+0x0/0x1b returned 0 after 0 usecs [ 0.313880] calling net_ns_init+0x0/0x139 @ 1 [ 0.313901] initcall net_ns_init+0x0/0x139 returned 0 after 0 usecs [ 0.313917] calling e820_mark_nvs_memory+0x0/0x3b @ 1 [ 0.313918] PM: Registering ACPI NVS region [mem 0x79da9000-0x79e08fff] (393216 bytes) [ 0.313925] PM: Registering ACPI NVS region [mem 0x7ac2c000-0x7ac2cfff] (4096 bytes) [ 0.313929] initcall e820_mark_nvs_memory+0x0/0x3b returned 0 after 0 usecs [ 0.313930] calling cpufreq_register_tsc_scaling+0x0/0x33 @ 1 [ 0.313931] initcall cpufreq_register_tsc_scaling+0x0/0x33 returned 0 after 0 usecs [ 0.313932] calling init_cpu_syscore+0x0/0x14 @ 1 [ 0.313934] initcall init_cpu_syscore+0x0/0x14 returned 0 after 0 usecs [ 0.313935] calling reboot_init+0x0/0x37 @ 1 [ 0.313938] initcall reboot_init+0x0/0x37 returned 0 after 0 usecs [ 0.313939] calling init_lapic_sysfs+0x0/0x23 @ 1 [ 0.313940] initcall init_lapic_sysfs+0x0/0x23 returned 0 after 0 usecs [ 0.313942] calling cpu_hotplug_pm_sync_init+0x0/0x14 @ 1 [ 0.313943] initcall cpu_hotplug_pm_sync_init+0x0/0x14 returned 0 after 0 usecs [ 0.313944] calling alloc_frozen_cpus+0x0/0x8 @ 1 [ 0.313945] initcall alloc_frozen_cpus+0x0/0x8 returned 0 after 0 usecs [ 0.313947] calling wq_sysfs_init+0x0/0x2b @ 1 [ 0.313960] initcall wq_sysfs_init+0x0/0x2b returned 0 after 0 usecs [ 0.313961] calling ksysfs_init+0x0/0x93 @ 1 [ 0.313967] initcall ksysfs_init+0x0/0x93 returned 0 after 0 usecs [ 0.313968] calling pm_init+0x0/0x76 @ 1 [ 0.313979] initcall pm_init+0x0/0x76 returned 0 after 0 usecs [ 0.313981] calling pm_disk_init+0x0/0x19 @ 1 [ 0.313984] initcall pm_disk_init+0x0/0x19 returned 0 after 0 usecs [ 0.313986] calling swsusp_header_init+0x0/0x40 @ 1 [ 0.313988] initcall swsusp_header_init+0x0/0x40 returned 0 after 0 usecs [ 0.313989] calling init_jiffies_clocksource+0x0/0x19 @ 1 [ 0.313991] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns [ 0.313995] initcall init_jiffies_clocksource+0x0/0x19 returned 0 after 0 usecs [ 0.313996] calling cgroup_wq_init+0x0/0x58 @ 1 [ 0.314005] initcall cgroup_wq_init+0x0/0x58 returned 0 after 0 usecs [ 0.314006] calling ftrace_mod_cmd_init+0x0/0x12 @ 1 [ 0.314007] initcall ftrace_mod_cmd_init+0x0/0x12 returned 0 after 0 usecs [ 0.314009] calling init_function_trace+0x0/0x92 @ 1 [ 0.314011] initcall init_function_trace+0x0/0x92 returned 0 after 0 usecs [ 0.314012] calling init_wakeup_tracer+0x0/0x32 @ 1 [ 0.314013] initcall init_wakeup_tracer+0x0/0x32 returned 0 after 0 usecs [ 0.314015] calling init_graph_trace+0x0/0x68 @ 1 [ 0.314017] initcall init_graph_trace+0x0/0x68 returned 0 after 0 usecs [ 0.314018] calling init_per_zone_wmark_min+0x0/0x6a @ 1 [ 0.314021] initcall init_per_zone_wmark_min+0x0/0x6a returned 0 after 0 usecs [ 0.314022] calling init_zero_pfn+0x0/0x39 @ 1 [ 0.314023] initcall init_zero_pfn+0x0/0x39 returned 0 after 0 usecs [ 0.314024] calling memory_failure_init+0x0/0xa4 @ 1 [ 0.314026] initcall memory_failure_init+0x0/0xa4 returned 0 after 0 usecs [ 0.314027] calling cma_init_reserved_areas+0x0/0x1d4 @ 1 [ 0.314028] initcall cma_init_reserved_areas+0x0/0x1d4 returned 0 after 0 usecs [ 0.314029] calling fsnotify_init+0x0/0x26 @ 1 [ 0.314031] initcall fsnotify_init+0x0/0x26 returned 0 after 0 usecs [ 0.314032] calling filelock_init+0x0/0x9f @ 1 [ 0.314036] initcall filelock_init+0x0/0x9f returned 0 after 0 usecs [ 0.314037] calling init_script_binfmt+0x0/0x16 @ 1 [ 0.314038] initcall init_script_binfmt+0x0/0x16 returned 0 after 0 usecs [ 0.314040] calling init_elf_binfmt+0x0/0x16 @ 1 [ 0.314041] initcall init_elf_binfmt+0x0/0x16 returned 0 after 0 usecs [ 0.314042] calling init_compat_elf_binfmt+0x0/0x16 @ 1 [ 0.314043] initcall init_compat_elf_binfmt+0x0/0x16 returned 0 after 0 usecs [ 0.314045] calling debugfs_init+0x0/0x50 @ 1 [ 0.314047] initcall debugfs_init+0x0/0x50 returned 0 after 0 usecs [ 0.314048] calling tracefs_init+0x0/0x3b @ 1 [ 0.314051] initcall tracefs_init+0x0/0x3b returned 0 after 0 usecs [ 0.314052] calling securityfs_init+0x0/0x47 @ 1 [ 0.314054] initcall securityfs_init+0x0/0x47 returned 0 after 0 usecs [ 0.314055] calling prandom_init+0x0/0xe4 @ 1 [ 0.314062] initcall prandom_init+0x0/0xe4 returned 0 after 0 usecs [ 0.314063] calling pinctrl_init+0x0/0xb2 @ 1 [ 0.314063] pinctrl core: initialized pinctrl subsystem [ 0.314074] initcall pinctrl_init+0x0/0xb2 returned 0 after 0 usecs [ 0.314076] calling gpiolib_dev_init+0x0/0xd4 @ 1 [ 0.314081] initcall gpiolib_dev_init+0x0/0xd4 returned 0 after 0 usecs [ 0.314082] calling sfi_sysfs_init+0x0/0xd9 @ 1 [ 0.314084] initcall sfi_sysfs_init+0x0/0xd9 returned 0 after 0 usecs [ 0.314085] calling virtio_init+0x0/0x30 @ 1 [ 0.314090] initcall virtio_init+0x0/0x30 returned 0 after 0 usecs [ 0.314091] calling regulator_init+0x0/0x8c @ 1 [ 0.314128] initcall regulator_init+0x0/0x8c returned 0 after 0 usecs [ 0.314130] calling iommu_init+0x0/0x56 @ 1 [ 0.314132] initcall iommu_init+0x0/0x56 returned 0 after 0 usecs [ 0.314133] calling early_resume_init+0x0/0x230 @ 1 [ 0.314160] RTC time: 23:01:21, date: 01/07/98 [ 0.314163] initcall early_resume_init+0x0/0x230 returned 0 after 0 usecs [ 0.314164] calling cpufreq_core_init+0x0/0x4c @ 1 [ 0.314166] initcall cpufreq_core_init+0x0/0x4c returned 0 after 0 usecs [ 0.314167] calling cpuidle_init+0x0/0x3d @ 1 [ 0.314169] initcall cpuidle_init+0x0/0x3d returned 0 after 0 usecs [ 0.314170] calling capsule_reboot_register+0x0/0x12 @ 1 [ 0.314172] initcall capsule_reboot_register+0x0/0x12 returned 0 after 0 usecs [ 0.314173] calling bsp_pm_check_init+0x0/0x14 @ 1 [ 0.314175] initcall bsp_pm_check_init+0x0/0x14 returned 0 after 0 usecs [ 0.314176] calling sock_init+0x0/0x8f @ 1 [ 0.314800] initcall sock_init+0x0/0x8f returned 0 after 0 usecs [ 0.314802] calling net_inuse_init+0x0/0x26 @ 1 [ 0.314804] initcall net_inuse_init+0x0/0x26 returned 0 after 0 usecs [ 0.314805] calling netpoll_init+0x0/0x31 @ 1 [ 0.314806] initcall netpoll_init+0x0/0x31 returned 0 after 0 usecs [ 0.314807] calling netlink_proto_init+0x0/0x15b @ 1 [ 0.314876] NET: Registered protocol family 16 [ 0.314884] initcall netlink_proto_init+0x0/0x15b returned 0 after 0 usecs [ 0.314885] calling __gnttab_init+0x0/0x30 @ 1 [ 0.314887] initcall __gnttab_init+0x0/0x30 returned -19 after 0 usecs [ 0.314902] calling bdi_class_init+0x0/0x49 @ 1 [ 0.314906] initcall bdi_class_init+0x0/0x49 returned 0 after 0 usecs [ 0.314907] calling mm_sysfs_init+0x0/0x29 @ 1 [ 0.314909] initcall mm_sysfs_init+0x0/0x29 returned 0 after 0 usecs [ 0.314910] calling kobject_uevent_init+0x0/0x12 @ 1 [ 0.314912] initcall kobject_uevent_init+0x0/0x12 returned 0 after 0 usecs [ 0.314914] calling pcibus_class_init+0x0/0x19 @ 1 [ 0.314917] initcall pcibus_class_init+0x0/0x19 returned 0 after 0 usecs [ 0.314918] calling pci_driver_init+0x0/0x12 @ 1 [ 0.314924] initcall pci_driver_init+0x0/0x12 returned 0 after 0 usecs [ 0.314925] calling rio_bus_init+0x0/0x40 @ 1 [ 0.314932] initcall rio_bus_init+0x0/0x40 returned 0 after 0 usecs [ 0.314933] calling backlight_class_init+0x0/0xaa @ 1 [ 0.314936] initcall backlight_class_init+0x0/0xaa returned 0 after 0 usecs [ 0.314937] calling xenbus_init+0x0/0x29c @ 1 [ 0.314939] initcall xenbus_init+0x0/0x29c returned -19 after 0 usecs [ 0.314940] calling tty_class_init+0x0/0x34 @ 1 [ 0.314942] initcall tty_class_init+0x0/0x34 returned 0 after 0 usecs [ 0.314943] calling vtconsole_class_init+0x0/0xc3 @ 1 [ 0.314955] initcall vtconsole_class_init+0x0/0xc3 returned 0 after 0 usecs [ 0.314956] calling iommu_dev_init+0x0/0x19 @ 1 [ 0.314960] initcall iommu_dev_init+0x0/0x19 returned 0 after 0 usecs [ 0.314961] calling mipi_dsi_bus_init+0x0/0x12 @ 1 [ 0.314966] initcall mipi_dsi_bus_init+0x0/0x12 returned 0 after 0 usecs [ 0.314967] calling wakeup_sources_debugfs_init+0x0/0x2b @ 1 [ 0.314970] initcall wakeup_sources_debugfs_init+0x0/0x2b returned 0 after 0 usecs [ 0.314971] calling register_node_type+0x0/0x2f @ 1 [ 0.314984] initcall register_node_type+0x0/0x2f returned 0 after 0 usecs [ 0.314985] calling regmap_initcall+0x0/0xd @ 1 [ 0.314987] initcall regmap_initcall+0x0/0xd returned 0 after 0 usecs [ 0.314988] calling sram_init+0x0/0x14 @ 1 [ 0.314993] initcall sram_init+0x0/0x14 returned 0 after 0 usecs [ 0.314994] calling syscon_init+0x0/0x14 @ 1 [ 0.314999] initcall syscon_init+0x0/0x14 returned 0 after 0 usecs [ 0.315001] calling spi_init+0x0/0x84 @ 1 [ 0.315007] initcall spi_init+0x0/0x84 returned 0 after 0 usecs [ 0.315008] calling i2c_init+0x0/0xaa @ 1 [ 0.315015] initcall i2c_init+0x0/0xaa returned 0 after 0 usecs [ 0.315016] calling init_ladder+0x0/0x25 @ 1 [ 0.321765] cpuidle: using governor ladder [ 0.321769] initcall init_ladder+0x0/0x25 returned 0 after 7812 usecs [ 0.321771] calling init_menu+0x0/0x12 @ 1 [ 0.325768] cpuidle: using governor menu [ 0.325772] initcall init_menu+0x0/0x12 returned 0 after 3906 usecs [ 0.325774] calling amd_postcore_init+0x0/0x141 @ 1 [ 0.325775] initcall amd_postcore_init+0x0/0x141 returned 0 after 0 usecs [ 0.325790] calling bts_init+0x0/0xaa @ 1 [ 0.325792] initcall bts_init+0x0/0xaa returned 0 after 0 usecs [ 0.325793] calling pt_init+0x0/0x367 @ 1 [ 0.325800] initcall pt_init+0x0/0x367 returned 0 after 0 usecs [ 0.325801] calling boot_params_ksysfs_init+0x0/0x226 @ 1 [ 0.325805] initcall boot_params_ksysfs_init+0x0/0x226 returned 0 after 0 usecs [ 0.325806] calling sbf_init+0x0/0xf5 @ 1 [ 0.325808] initcall sbf_init+0x0/0xf5 returned 0 after 0 usecs [ 0.325809] calling arch_kdebugfs_init+0x0/0x24 @ 1 [ 0.325811] initcall arch_kdebugfs_init+0x0/0x24 returned 0 after 0 usecs [ 0.325812] calling mtrr_if_init+0x0/0x65 @ 1 [ 0.325814] initcall mtrr_if_init+0x0/0x65 returned 0 after 0 usecs [ 0.325815] calling ffh_cstate_init+0x0/0x2b @ 1 [ 0.325817] initcall ffh_cstate_init+0x0/0x2b returned 0 after 0 usecs [ 0.325818] calling activate_jump_labels+0x0/0x35 @ 1 [ 0.325819] initcall activate_jump_labels+0x0/0x35 returned 0 after 0 usecs [ 0.325820] calling gigantic_pages_init+0x0/0x33 @ 1 [ 0.325822] initcall gigantic_pages_init+0x0/0x33 returned 0 after 0 usecs [ 0.325823] calling kcmp_cookies_init+0x0/0x36 @ 1 [ 0.325846] initcall kcmp_cookies_init+0x0/0x36 returned 0 after 0 usecs [ 0.325847] calling acpi_pci_init+0x0/0x66 @ 1 [ 0.325848] ACPI: bus type PCI registered [ 0.325850] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 [ 0.325853] initcall acpi_pci_init+0x0/0x66 returned 0 after 0 usecs [ 0.325854] calling dma_bus_init+0x0/0xc2 @ 1 [ 0.325864] initcall dma_bus_init+0x0/0xc2 returned 0 after 0 usecs [ 0.325865] calling dma_channel_table_init+0x0/0xcf @ 1 [ 0.325869] initcall dma_channel_table_init+0x0/0xcf returned 0 after 0 usecs [ 0.325870] calling setup_vcpu_hotplug_event+0x0/0x22 @ 1 [ 0.325871] initcall setup_vcpu_hotplug_event+0x0/0x22 returned -19 after 0 usecs [ 0.325873] calling register_xen_pci_notifier+0x0/0x36 @ 1 [ 0.325874] initcall register_xen_pci_notifier+0x0/0x36 returned 0 after 0 usecs [ 0.325875] calling xen_pcpu_init+0x0/0xc9 @ 1 [ 0.325877] initcall xen_pcpu_init+0x0/0xc9 returned -19 after 0 usecs [ 0.325878] calling dmi_id_init+0x0/0x30f @ 1 [ 0.325899] initcall dmi_id_init+0x0/0x30f returned 0 after 0 usecs [ 0.325901] calling numachip_timer_init+0x0/0x52 @ 1 [ 0.325902] initcall numachip_timer_init+0x0/0x52 returned -19 after 0 usecs [ 0.325903] calling pci_arch_init+0x0/0x68 @ 1 [ 0.325914] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) [ 0.325918] PCI: MMCONFIG at [mem 0xe0000000-0xe3ffffff] reserved in E820 [ 0.325922] PCI: Using configuration type 1 for base access [ 0.325926] initcall pci_arch_init+0x0/0x68 returned 0 after 0 usecs [ 0.325941] calling init_vdso+0x0/0x49 @ 1 [ 0.325956] initcall init_vdso+0x0/0x49 returned 0 after 0 usecs [ 0.325957] calling sysenter_setup+0x0/0x14 @ 1 [ 0.325960] initcall sysenter_setup+0x0/0x14 returned 0 after 0 usecs [ 0.325961] calling fixup_ht_bug+0x0/0xf2 @ 1 [ 0.325963] initcall fixup_ht_bug+0x0/0xf2 returned 0 after 0 usecs [ 0.325964] calling topology_init+0x0/0x89 @ 1 [ 0.326114] initcall topology_init+0x0/0x89 returned 0 after 0 usecs [ 0.326115] calling mtrr_init_finialize+0x0/0x3f @ 1 [ 0.326117] initcall mtrr_init_finialize+0x0/0x3f returned 0 after 0 usecs [ 0.326118] calling uid_cache_init+0x0/0x95 @ 1 [ 0.326120] initcall uid_cache_init+0x0/0x95 returned 0 after 0 usecs [ 0.326121] calling param_sysfs_init+0x0/0x1b2 @ 1 [ 0.326752] initcall param_sysfs_init+0x0/0x1b2 returned 0 after 0 usecs [ 0.326754] calling proc_schedstat_init+0x0/0x22 @ 1 [ 0.326756] initcall proc_schedstat_init+0x0/0x22 returned 0 after 0 usecs [ 0.326757] calling pm_sysrq_init+0x0/0x19 @ 1 [ 0.327753] initcall pm_sysrq_init+0x0/0x19 returned 0 after 3906 usecs [ 0.327755] calling create_proc_profile+0x0/0x2a0 @ 1 [ 0.327757] initcall create_proc_profile+0x0/0x2a0 returned 0 after 0 usecs [ 0.327758] calling crash_save_vmcoreinfo_init+0x0/0x5d3 @ 1 [ 0.327772] initcall crash_save_vmcoreinfo_init+0x0/0x5d3 returned 0 after 0 usecs [ 0.327773] calling crash_notes_memory_init+0x0/0x37 @ 1 [ 0.327775] initcall crash_notes_memory_init+0x0/0x37 returned 0 after 0 usecs [ 0.327776] calling cgroup_namespaces_init+0x0/0x8 @ 1 [ 0.327777] initcall cgroup_namespaces_init+0x0/0x8 returned 0 after 0 usecs [ 0.327778] calling user_namespaces_init+0x0/0x2d @ 1 [ 0.327783] initcall user_namespaces_init+0x0/0x2d returned 0 after 0 usecs [ 0.327784] calling hung_task_init+0x0/0x51 @ 1 [ 0.327800] initcall hung_task_init+0x0/0x51 returned 0 after 0 usecs [ 0.327802] calling oom_init+0x0/0x6a @ 1 [ 0.327813] initcall oom_init+0x0/0x6a returned 0 after 0 usecs [ 0.327815] calling default_bdi_init+0x0/0x3f @ 1 [ 0.327851] initcall default_bdi_init+0x0/0x3f returned 0 after 0 usecs [ 0.327853] calling percpu_enable_async+0x0/0xf @ 1 [ 0.327854] initcall percpu_enable_async+0x0/0xf returned 0 after 0 usecs [ 0.327855] calling kcompactd_init+0x0/0x69 @ 1 [ 0.327870] initcall kcompactd_init+0x0/0x69 returned 0 after 0 usecs [ 0.327871] calling init_reserve_notifier+0x0/0x26 @ 1 [ 0.327872] initcall init_reserve_notifier+0x0/0x26 returned 0 after 0 usecs [ 0.327874] calling init_admin_reserve+0x0/0x40 @ 1 [ 0.327875] initcall init_admin_reserve+0x0/0x40 returned 0 after 0 usecs [ 0.327876] calling init_user_reserve+0x0/0x40 @ 1 [ 0.327878] initcall init_user_reserve+0x0/0x40 returned 0 after 0 usecs [ 0.327879] calling hugetlb_init+0x0/0x499 @ 1 [ 0.327880] HugeTLB registered 1 GB page size, pre-allocated 0 pages [ 0.327883] HugeTLB registered 2 MB page size, pre-allocated 0 pages [ 0.327899] initcall hugetlb_init+0x0/0x499 returned 0 after 0 usecs [ 0.327900] calling mmu_notifier_init+0x0/0x12 @ 1 [ 0.327902] initcall mmu_notifier_init+0x0/0x12 returned 0 after 0 usecs [ 0.327903] calling ksm_init+0x0/0x15b @ 1 [ 0.327923] initcall ksm_init+0x0/0x15b returned 0 after 0 usecs [ 0.327925] calling hugepage_init+0x0/0x18f @ 1 [ 0.327945] initcall hugepage_init+0x0/0x18f returned 0 after 0 usecs [ 0.327947] calling mem_cgroup_swap_init+0x0/0x73 @ 1 [ 0.327948] initcall mem_cgroup_swap_init+0x0/0x73 returned 0 after 0 usecs [ 0.327949] calling mem_cgroup_init+0x0/0x148 @ 1 [ 0.327951] initcall mem_cgroup_init+0x0/0x148 returned 0 after 0 usecs [ 0.327952] calling crypto_wq_init+0x0/0x33 @ 1 [ 0.327969] initcall crypto_wq_init+0x0/0x33 returned 0 after 0 usecs [ 0.327970] calling cryptomgr_init+0x0/0x12 @ 1 [ 0.327972] initcall cryptomgr_init+0x0/0x12 returned 0 after 0 usecs [ 0.327973] calling init_bio+0x0/0xd1 @ 1 [ 0.328012] initcall init_bio+0x0/0xd1 returned 0 after 0 usecs [ 0.328014] calling blk_settings_init+0x0/0x2a @ 1 [ 0.328015] initcall blk_settings_init+0x0/0x2a returned 0 after 0 usecs [ 0.328016] calling blk_ioc_init+0x0/0x2a @ 1 [ 0.328020] initcall blk_ioc_init+0x0/0x2a returned 0 after 0 usecs [ 0.328021] calling blk_softirq_init+0x0/0x6a @ 1 [ 0.328022] initcall blk_softirq_init+0x0/0x6a returned 0 after 0 usecs [ 0.328024] calling blk_mq_init+0x0/0x19 @ 1 [ 0.328025] initcall blk_mq_init+0x0/0x19 returned 0 after 0 usecs [ 0.328026] calling genhd_device_init+0x0/0x76 @ 1 [ 0.328050] initcall genhd_device_init+0x0/0x76 returned 0 after 0 usecs [ 0.328052] calling irq_poll_setup+0x0/0x6a @ 1 [ 0.328053] initcall irq_poll_setup+0x0/0x6a returned 0 after 0 usecs [ 0.328054] calling byt_gpio_init+0x0/0x14 @ 1 [ 0.328060] initcall byt_gpio_init+0x0/0x14 returned 0 after 0 usecs [ 0.328061] calling gpiolib_debugfs_init+0x0/0x24 @ 1 [ 0.328065] initcall gpiolib_debugfs_init+0x0/0x24 returned 0 after 0 usecs [ 0.328066] calling lp_gpio_init+0x0/0x14 @ 1 [ 0.328070] initcall lp_gpio_init+0x0/0x14 returned 0 after 0 usecs [ 0.328071] calling rc5t583_gpio_init+0x0/0x14 @ 1 [ 0.328075] initcall rc5t583_gpio_init+0x0/0x14 returned 0 after 0 usecs [ 0.328076] calling sx150x_init+0x0/0x14 @ 1 [ 0.328081] initcall sx150x_init+0x0/0x14 returned 0 after 0 usecs [ 0.328082] calling palmas_gpio_init+0x0/0x14 @ 1 [ 0.328086] initcall palmas_gpio_init+0x0/0x14 returned 0 after 0 usecs [ 0.328087] calling tps6586x_gpio_init+0x0/0x14 @ 1 [ 0.328091] initcall tps6586x_gpio_init+0x0/0x14 returned 0 after 0 usecs [ 0.328092] calling tps65910_gpio_init+0x0/0x14 @ 1 [ 0.328096] initcall tps65910_gpio_init+0x0/0x14 returned 0 after 0 usecs [ 0.328097] calling pwm_debugfs_init+0x0/0x24 @ 1 [ 0.328099] initcall pwm_debugfs_init+0x0/0x24 returned 0 after 0 usecs [ 0.328100] calling pwm_sysfs_init+0x0/0x19 @ 1 [ 0.328103] initcall pwm_sysfs_init+0x0/0x19 returned 0 after 0 usecs [ 0.328104] calling pci_slot_init+0x0/0x50 @ 1 [ 0.328107] initcall pci_slot_init+0x0/0x50 returned 0 after 0 usecs [ 0.328108] calling fbmem_init+0x0/0xd7 @ 1 [ 0.328113] initcall fbmem_init+0x0/0xd7 returned 0 after 0 usecs [ 0.328114] calling acpi_init+0x0/0x2a3 @ 1 [ 0.328126] ACPI: Added _OSI(Module Device) [ 0.328128] ACPI: Added _OSI(Processor Device) [ 0.328130] ACPI: Added _OSI(3.0 _SCP Extensions) [ 0.328132] ACPI: Added _OSI(Processor Aggregator Device) [ 0.331405] ACPI: Executed 3 blocks of module-level executable AML code [ 0.332931] ACPI: Executed 2 blocks of module-level executable AML code [ 0.334083] ACPI: Executed 1 blocks of module-level executable AML code [ 0.336300] ACPI: 11 ACPI AML tables successfully acquired and loaded [ 0.340265] ACPI: Dynamic OEM Table Load: [ 0.340273] ACPI: SSDT 0xFFFF880274D2BA00 000102 (v02 PmRef Cpu0Cst 00003001 INTL 20150818) [ 0.340795] ACPI: Dynamic OEM Table Load: [ 0.340801] ACPI: SSDT 0xFFFF880274D2BC00 00015F (v02 PmRef ApIst 00003000 INTL 20150818) [ 0.341239] ACPI: Dynamic OEM Table Load: [ 0.341245] ACPI: SSDT 0xFFFF880274D17480 00008D (v02 PmRef ApCst 00003000 INTL 20150818) [ 0.342097] ACPI : EC: EC started [ 0.571924] ACPI: Interpreter enabled [ 0.571941] ACPI: (supports S0 S3 S4 S5) [ 0.571943] ACPI: Using IOAPIC for interrupt routing [ 0.571963] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.573111] ACPI: Power Resource [PXP] (off) [ 0.573460] ACPI: Power Resource [PXP] (on) [ 0.592161] ACPI: Power Resource [PXP] (on) [ 0.612105] ACPI: Power Resource [PXP] (off) [ 0.612411] ACPI: Power Resource [PXP] (off) [ 0.612714] ACPI: Power Resource [PXP] (off) [ 0.613120] ACPI: Power Resource [SPPR] (on) [ 0.631969] ACPI: Power Resource [ODPR] (on) [ 0.632063] ACPI: Power Resource [SPPR] (off) [ 0.632243] ACPI: Power Resource [ODPR] (on) [ 0.632447] ACPI: Power Resource [UPPR] (on) [ 0.632606] ACPI: Power Resource [UPPR] (on) [ 0.632742] ACPI: Power Resource [UPPR] (on) [ 0.632985] ACPI: Power Resource [UPPR] (on) [ 0.633141] ACPI: Power Resource [UPPR] (on) [ 0.633274] ACPI: Power Resource [UPPR] (on) [ 0.633426] ACPI: Power Resource [USBC] (on) [ 0.633501] ACPI: Power Resource [SDPR] (on) [ 0.648132] ACPI: Power Resource [LSPR] (on) [ 0.650061] ACPI: Power Resource [PAUD] (on) [ 0.651943] ACPI: Power Resource [FN00] (on) [ 0.740192] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.740198] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] [ 0.740636] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] [ 0.740647] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge [ 0.740973] PCI host bridge to bus 0000:00 [ 0.740977] pci_bus 0000:00: root bus resource [io 0x0070-0x0077] [ 0.740980] pci_bus 0000:00: root bus resource [io 0x0000-0x006f window] [ 0.740982] pci_bus 0000:00: root bus resource [io 0x0078-0x0cf7 window] [ 0.740984] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] [ 0.740987] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] [ 0.740990] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff window] [ 0.740994] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000fffff window] [ 0.740997] pci_bus 0000:00: root bus resource [mem 0x7c000001-0x7fffffff window] [ 0.741000] pci_bus 0000:00: root bus resource [mem 0x80000000-0xbfffffff window] [ 0.741004] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xefffffff window] [ 0.741007] pci_bus 0000:00: root bus resource [mem 0xfea00000-0xfeafffff window] [ 0.741010] pci_bus 0000:00: root bus resource [mem 0xfed00000-0xfed003ff window] [ 0.741014] pci_bus 0000:00: root bus resource [mem 0xfed01000-0xfed01fff window] [ 0.741017] pci_bus 0000:00: root bus resource [mem 0xfed03000-0xfed03fff window] [ 0.741022] pci_bus 0000:00: root bus resource [mem 0xfed06000-0xfed06fff window] [ 0.741025] pci_bus 0000:00: root bus resource [mem 0xfed08000-0xfed09fff window] [ 0.741029] pci_bus 0000:00: root bus resource [mem 0xfed80000-0xfedbffff window] [ 0.741032] pci_bus 0000:00: root bus resource [mem 0xfed1c000-0xfed1cfff window] [ 0.741035] pci_bus 0000:00: root bus resource [mem 0xfee00000-0xfeefffff window] [ 0.741039] pci_bus 0000:00: root bus resource [bus 00-ff] [ 0.741046] pci 0000:00:00.0: [8086:5af0] type 00 class 0x060000 [ 0.741202] pci 0000:00:02.0: [8086:5a84] type 00 class 0x030000 [ 0.741208] pci 0000:00:02.0: reg 0x10: [mem 0x90000000-0x90ffffff 64bit] [ 0.741212] pci 0000:00:02.0: reg 0x18: [mem 0x80000000-0x8fffffff 64bit pref] [ 0.741215] pci 0000:00:02.0: reg 0x20: [io 0x1000-0x103f] [ 0.741360] pci 0000:00:03.0: [8086:5a88] type 00 class 0x048000 [ 0.741366] pci 0000:00:03.0: reg 0x10: [mem 0x91000000-0x91ffffff 64bit] [ 0.741513] pci 0000:00:0e.0: [8086:5a98] type 00 class 0x040300 [ 0.741522] pci 0000:00:0e.0: reg 0x10: [mem 0x92210000-0x92213fff 64bit] [ 0.741535] pci 0000:00:0e.0: reg 0x20: [mem 0x92000000-0x920fffff 64bit] [ 0.741561] pci 0000:00:0e.0: PME# supported from D0 D3hot D3cold [ 0.741694] pci 0000:00:0e.0: System wakeup disabled by ACPI [ 0.741723] pci 0000:00:0f.0: [8086:5a9a] type 00 class 0x078000 [ 0.741735] pci 0000:00:0f.0: reg 0x10: [mem 0x92218000-0x92218fff 64bit] [ 0.741776] pci 0000:00:0f.0: PME# supported from D3hot [ 0.741902] pci 0000:00:11.0: [8086:5aa2] type 00 class 0x005007 [ 0.741912] pci 0000:00:11.0: reg 0x10: [mem 0x92214000-0x92215fff 64bit] [ 0.741918] pci 0000:00:11.0: reg 0x18: [mem 0x9221b000-0x9221bfff 64bit] [ 0.742067] pci 0000:00:12.0: [8086:5ae3] type 00 class 0x010601 [ 0.742074] pci 0000:00:12.0: reg 0x10: [mem 0x92216000-0x92217fff] [ 0.742077] pci 0000:00:12.0: reg 0x14: [mem 0x92242000-0x922420ff] [ 0.742081] pci 0000:00:12.0: reg 0x18: [io 0x1080-0x1087] [ 0.742084] pci 0000:00:12.0: reg 0x1c: [io 0x1088-0x108b] [ 0.742088] pci 0000:00:12.0: reg 0x20: [io 0x1060-0x107f] [ 0.742092] pci 0000:00:12.0: reg 0x24: [mem 0x92240000-0x922407ff] [ 0.742109] pci 0000:00:12.0: PME# supported from D3hot [ 0.742242] pci 0000:00:13.0: [8086:5ada] type 01 class 0x060400 [ 0.742273] pci 0000:00:13.0: PME# supported from D0 D3hot D3cold [ 0.742406] pci 0000:00:13.0: System wakeup disabled by ACPI [ 0.742436] pci 0000:00:13.3: [8086:5adb] type 01 class 0x060400 [ 0.742466] pci 0000:00:13.3: PME# supported from D0 D3hot D3cold [ 0.742599] pci 0000:00:13.3: System wakeup disabled by ACPI [ 0.742635] pci 0000:00:14.0: [8086:5ad7] type 01 class 0x060400 [ 0.742674] pci 0000:00:14.0: PME# supported from D0 D3hot D3cold [ 0.742811] pci 0000:00:14.0: System wakeup disabled by ACPI [ 0.742847] pci 0000:00:15.0: [8086:5aa8] type 00 class 0x0c0330 [ 0.742856] pci 0000:00:15.0: reg 0x10: [mem 0x92200000-0x9220ffff 64bit] [ 0.742888] pci 0000:00:15.0: PME# supported from D3hot D3cold [ 0.742994] pci 0000:00:15.0: System wakeup disabled by ACPI [ 0.743029] pci 0000:00:16.0: [8086:5aac] type 00 class 0x118000 [ 0.743040] pci 0000:00:16.0: reg 0x10: [mem 0x9221c000-0x9221cfff 64bit] [ 0.743048] pci 0000:00:16.0: reg 0x18: [mem 0x9221d000-0x9221dfff 64bit] [ 0.743193] pci 0000:00:16.1: [8086:5aae] type 00 class 0x118000 [ 0.743203] pci 0000:00:16.1: reg 0x10: [mem 0x9221e000-0x9221efff 64bit] [ 0.743210] pci 0000:00:16.1: reg 0x18: [mem 0x9221f000-0x9221ffff 64bit] [ 0.743360] pci 0000:00:16.2: [8086:5ab0] type 00 class 0x118000 [ 0.743371] pci 0000:00:16.2: reg 0x10: [mem 0x92220000-0x92220fff 64bit] [ 0.743378] pci 0000:00:16.2: reg 0x18: [mem 0x92221000-0x92221fff 64bit] [ 0.743524] pci 0000:00:16.3: [8086:5ab2] type 00 class 0x118000 [ 0.743534] pci 0000:00:16.3: reg 0x10: [mem 0x92222000-0x92222fff 64bit] [ 0.743543] pci 0000:00:16.3: reg 0x18: [mem 0x92223000-0x92223fff 64bit] [ 0.743692] pci 0000:00:17.0: [8086:5ab4] type 00 class 0x118000 [ 0.743703] pci 0000:00:17.0: reg 0x10: [mem 0x92224000-0x92224fff 64bit] [ 0.743710] pci 0000:00:17.0: reg 0x18: [mem 0x92225000-0x92225fff 64bit] [ 0.743855] pci 0000:00:17.1: [8086:5ab6] type 00 class 0x118000 [ 0.743866] pci 0000:00:17.1: reg 0x10: [mem 0x92226000-0x92226fff 64bit] [ 0.743873] pci 0000:00:17.1: reg 0x18: [mem 0x92227000-0x92227fff 64bit] [ 0.744023] pci 0000:00:17.2: [8086:5ab8] type 00 class 0x118000 [ 0.744034] pci 0000:00:17.2: reg 0x10: [mem 0x92228000-0x92228fff 64bit] [ 0.744041] pci 0000:00:17.2: reg 0x18: [mem 0x92229000-0x92229fff 64bit] [ 0.744186] pci 0000:00:17.3: [8086:5aba] type 00 class 0x118000 [ 0.744197] pci 0000:00:17.3: reg 0x10: [mem 0x9222a000-0x9222afff 64bit] [ 0.744204] pci 0000:00:17.3: reg 0x18: [mem 0x9222b000-0x9222bfff 64bit] [ 0.744354] pci 0000:00:18.0: [8086:5abc] type 00 class 0x118000 [ 0.744364] pci 0000:00:18.0: reg 0x10: [mem 0x9222c000-0x9222cfff 64bit] [ 0.744371] pci 0000:00:18.0: reg 0x18: [mem 0x9222d000-0x9222dfff 64bit] [ 0.744516] pci 0000:00:18.1: [8086:5abe] type 00 class 0x118000 [ 0.744527] pci 0000:00:18.1: reg 0x10: [mem 0x9222e000-0x9222efff 64bit] [ 0.744535] pci 0000:00:18.1: reg 0x18: [mem 0x9222f000-0x9222ffff 64bit] [ 0.744679] pci 0000:00:18.2: [8086:5ac0] type 00 class 0x118000 [ 0.744690] pci 0000:00:18.2: reg 0x10: [mem 0x92230000-0x92230fff 64bit] [ 0.744697] pci 0000:00:18.2: reg 0x18: [mem 0x92231000-0x92231fff 64bit] [ 0.744842] pci 0000:00:18.3: [8086:5aee] type 00 class 0x118000 [ 0.744852] pci 0000:00:18.3: reg 0x10: [mem 0x92232000-0x92232fff 64bit] [ 0.744859] pci 0000:00:18.3: reg 0x18: [mem 0x92233000-0x92233fff 64bit] [ 0.745009] pci 0000:00:19.0: [8086:5ac2] type 00 class 0x118000 [ 0.745019] pci 0000:00:19.0: reg 0x10: [mem 0x92234000-0x92234fff 64bit] [ 0.745026] pci 0000:00:19.0: reg 0x18: [mem 0x92235000-0x92235fff 64bit] [ 0.745172] pci 0000:00:19.1: [8086:5ac4] type 00 class 0x118000 [ 0.745184] pci 0000:00:19.1: reg 0x10: [mem 0x92236000-0x92236fff 64bit] [ 0.745191] pci 0000:00:19.1: reg 0x18: [mem 0x92237000-0x92237fff 64bit] [ 0.745336] pci 0000:00:19.2: [8086:5ac6] type 00 class 0x118000 [ 0.745347] pci 0000:00:19.2: reg 0x10: [mem 0x92238000-0x92238fff 64bit] [ 0.745354] pci 0000:00:19.2: reg 0x18: [mem 0x92239000-0x92239fff 64bit] [ 0.745505] pci 0000:00:1b.0: [8086:5aca] type 00 class 0x080501 [ 0.745514] pci 0000:00:1b.0: reg 0x10: [mem 0x9223a000-0x9223afff 64bit] [ 0.745519] pci 0000:00:1b.0: reg 0x18: [mem 0x9223b000-0x9223bfff 64bit] [ 0.745668] pci 0000:00:1c.0: [8086:5acc] type 00 class 0x080501 [ 0.745679] pci 0000:00:1c.0: reg 0x10: [mem 0x9223c000-0x9223cfff 64bit] [ 0.745684] pci 0000:00:1c.0: reg 0x18: [mem 0x9223d000-0x9223dfff 64bit] [ 0.745832] pci 0000:00:1e.0: [8086:5ad0] type 00 class 0x080501 [ 0.745841] pci 0000:00:1e.0: reg 0x10: [mem 0x9223e000-0x9223efff 64bit] [ 0.745846] pci 0000:00:1e.0: reg 0x18: [mem 0x9223f000-0x9223ffff 64bit] [ 0.745989] pci 0000:00:1f.0: [8086:5ae8] type 00 class 0x060100 [ 0.746175] pci 0000:00:1f.1: [8086:5ad4] type 00 class 0x0c0500 [ 0.746190] pci 0000:00:1f.1: reg 0x10: [mem 0x92241000-0x922410ff 64bit] [ 0.746211] pci 0000:00:1f.1: reg 0x20: [io 0x1040-0x105f] [ 0.746390] pci 0000:00:13.0: PCI bridge to [bus 01] [ 0.746430] pci 0000:00:13.3: PCI bridge to [bus 02] [ 0.746548] pci 0000:03:00.0: [8086:095a] type 00 class 0x028000 [ 0.746644] pci 0000:03:00.0: reg 0x10: [mem 0x92100000-0x92101fff 64bit] [ 0.746798] pci 0000:03:00.0: can't set Max Payload Size to 256; if necessary, use "pci=pcie_bus_safe" and report a bug [ 0.746992] pci 0000:03:00.0: PME# supported from D0 D3hot D3cold [ 0.747077] pci 0000:03:00.0: System wakeup disabled by ACPI [ 0.752036] pci 0000:00:14.0: PCI bridge to [bus 03] [ 0.752045] pci 0000:00:14.0: bridge window [mem 0x92100000-0x921fffff] [ 0.753473] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. [ 0.753514] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. [ 0.753555] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. [ 0.753595] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. [ 0.753634] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. [ 0.753674] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. [ 0.753715] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. [ 0.753755] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. [ 0.754243] ACPI: Enabled 2 GPEs in block 00 to 7F [ 0.754255] ACPI : EC: EC stopped [ 0.754309] ACPI : EC: GPE = 0x2b, I/O: command/status = 0x66, data = 0x62 [ 0.754312] ACPI : EC: EC started [ 0.984162] initcall acpi_init+0x0/0x2a3 returned 0 after 640625 usecs [ 0.984164] calling pnp_init+0x0/0x12 @ 1 [ 0.984170] initcall pnp_init+0x0/0x12 returned 0 after 0 usecs [ 0.984172] calling balloon_init+0x0/0x1ad @ 1 [ 0.984173] initcall balloon_init+0x0/0x1ad returned -19 after 0 usecs [ 0.984175] calling xen_setup_shutdown_event+0x0/0x40 @ 1 [ 0.984176] initcall xen_setup_shutdown_event+0x0/0x40 returned -19 after 0 usecs [ 0.984177] calling xenbus_probe_backend_init+0x0/0x52 @ 1 [ 0.984183] initcall xenbus_probe_backend_init+0x0/0x52 returned 0 after 0 usecs [ 0.984184] calling xenbus_probe_frontend_init+0x0/0x9b @ 1 [ 0.984189] initcall xenbus_probe_frontend_init+0x0/0x9b returned 0 after 0 usecs [ 0.984190] calling xen_acpi_pad_init+0x0/0x4d @ 1 [ 0.984191] initcall xen_acpi_pad_init+0x0/0x4d returned -19 after 0 usecs [ 0.984192] calling balloon_init+0x0/0x8a @ 1 [ 0.984194] initcall balloon_init+0x0/0x8a returned -19 after 0 usecs [ 0.984195] calling pm8607_regulator_init+0x0/0x14 @ 1 [ 0.984201] initcall pm8607_regulator_init+0x0/0x14 returned 0 after 0 usecs [ 0.984202] calling lp8788_buck_init+0x0/0x14 @ 1 [ 0.984208] initcall lp8788_buck_init+0x0/0x14 returned 0 after 0 usecs [ 0.984209] calling lp8788_ldo_init+0x0/0x19 @ 1 [ 0.984217] initcall lp8788_ldo_init+0x0/0x19 returned 0 after 0 usecs [ 0.984218] calling misc_init+0x0/0xc4 @ 1 [ 0.984223] initcall misc_init+0x0/0xc4 returned 0 after 0 usecs [ 0.984224] calling tpm_init+0x0/0x7e @ 1 [ 0.984227] initcall tpm_init+0x0/0x7e returned 0 after 0 usecs [ 0.984228] calling vga_arb_device_init+0x0/0x1b7 @ 1 [ 0.984258] vgaarb: setting as boot device: PCI:0000:00:02.0 [ 0.984262] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none [ 0.984268] vgaarb: loaded [ 0.984270] vgaarb: bridge control possible 0000:00:02.0 [ 0.984274] initcall vga_arb_device_init+0x0/0x1b7 returned 0 after 0 usecs [ 0.984276] calling cn_init+0x0/0xc0 @ 1 [ 0.984285] initcall cn_init+0x0/0xc0 returned 0 after 0 usecs [ 0.984287] calling pm860x_i2c_init+0x0/0x2e @ 1 [ 0.984294] initcall pm860x_i2c_init+0x0/0x2e returned 0 after 0 usecs [ 0.984296] calling wm8400_module_init+0x0/0x2e @ 1 [ 0.984300] initcall wm8400_module_init+0x0/0x2e returned 0 after 0 usecs [ 0.984301] calling wm831x_i2c_init+0x0/0x2e @ 1 [ 0.984304] initcall wm831x_i2c_init+0x0/0x2e returned 0 after 0 usecs [ 0.984306] calling wm831x_spi_init+0x0/0x2a @ 1 [ 0.984309] initcall wm831x_spi_init+0x0/0x2a returned 0 after 0 usecs [ 0.984311] calling wm8350_i2c_init+0x0/0x14 @ 1 [ 0.984314] initcall wm8350_i2c_init+0x0/0x14 returned 0 after 0 usecs [ 0.984315] calling tps65910_i2c_init+0x0/0x14 @ 1 [ 0.984319] initcall tps65910_i2c_init+0x0/0x14 returned 0 after 0 usecs [ 0.984320] calling tps80031_init+0x0/0x14 @ 1 [ 0.984324] initcall tps80031_init+0x0/0x14 returned 0 after 0 usecs [ 0.984325] calling ezx_pcap_init+0x0/0x14 @ 1 [ 0.984328] initcall ezx_pcap_init+0x0/0x14 returned 0 after 0 usecs [ 0.984330] calling da903x_init+0x0/0x14 @ 1 [ 0.984334] initcall da903x_init+0x0/0x14 returned 0 after 0 usecs [ 0.984335] calling da9052_spi_init+0x0/0x2e @ 1 [ 0.984339] initcall da9052_spi_init+0x0/0x2e returned 0 after 0 usecs [ 0.984340] calling da9052_i2c_init+0x0/0x2e @ 1 [ 0.984344] initcall da9052_i2c_init+0x0/0x2e returned 0 after 0 usecs [ 0.984345] calling lp8788_init+0x0/0x14 @ 1 [ 0.984349] initcall lp8788_init+0x0/0x14 returned 0 after 0 usecs [ 0.984350] calling da9055_i2c_init+0x0/0x2e @ 1 [ 0.984354] initcall da9055_i2c_init+0x0/0x2e returned 0 after 0 usecs [ 0.984355] calling max8925_i2c_init+0x0/0x2e @ 1 [ 0.984359] initcall max8925_i2c_init+0x0/0x2e returned 0 after 0 usecs [ 0.984360] calling max8997_i2c_init+0x0/0x14 @ 1 [ 0.984364] initcall max8997_i2c_init+0x0/0x14 returned 0 after 0 usecs [ 0.984365] calling max8998_i2c_init+0x0/0x14 @ 1 [ 0.984368] initcall max8998_i2c_init+0x0/0x14 returned 0 after 0 usecs [ 0.984370] calling ab3100_i2c_init+0x0/0x14 @ 1 [ 0.984373] initcall ab3100_i2c_init+0x0/0x14 returned 0 after 0 usecs [ 0.984375] calling tps6586x_init+0x0/0x14 @ 1 [ 0.984379] initcall tps6586x_init+0x0/0x14 returned 0 after 0 usecs [ 0.984380] calling tps65090_init+0x0/0x14 @ 1 [ 0.984384] initcall tps65090_init+0x0/0x14 returned 0 after 0 usecs [ 0.984385] calling aat2870_init+0x0/0x14 @ 1 [ 0.984389] initcall aat2870_init+0x0/0x14 returned 0 after 0 usecs [ 0.984390] calling palmas_i2c_init+0x0/0x14 @ 1 [ 0.984395] initcall palmas_i2c_init+0x0/0x14 returned 0 after 0 usecs [ 0.984396] calling rc5t583_i2c_init+0x0/0x14 @ 1 [ 0.984400] initcall rc5t583_i2c_init+0x0/0x14 returned 0 after 0 usecs [ 0.984401] calling sec_pmic_init+0x0/0x14 @ 1 [ 0.984405] initcall sec_pmic_init+0x0/0x14 returned 0 after 0 usecs [ 0.984406] calling as3711_i2c_init+0x0/0x14 @ 1 [ 0.984410] initcall as3711_i2c_init+0x0/0x14 returned 0 after 0 usecs [ 0.984411] calling dma_buf_init+0x0/0xaf @ 1 [ 0.984418] initcall dma_buf_init+0x0/0xaf returned 0 after 0 usecs [ 0.984420] calling init_scsi+0x0/0x9d @ 1 [ 0.984451] SCSI subsystem initialized [ 0.984454] initcall init_scsi+0x0/0x9d returned 0 after 0 usecs [ 0.984456] calling ata_init+0x0/0x409 @ 1 [ 0.984484] libata version 3.00 loaded. [ 0.984485] initcall ata_init+0x0/0x409 returned 0 after 0 usecs [ 0.984487] calling phy_init+0x0/0x32 @ 1 [ 0.984498] initcall phy_init+0x0/0x32 returned 0 after 0 usecs [ 0.984499] calling usb_init+0x0/0x166 @ 1 [ 0.984501] ACPI: bus type USB registered [ 0.984515] usbcore: registered new interface driver usbfs [ 0.984524] usbcore: registered new interface driver hub [ 0.984536] usbcore: registered new device driver usb [ 0.984539] initcall usb_init+0x0/0x166 returned 0 after 0 usecs [ 0.984540] calling usb_phy_generic_init+0x0/0x14 @ 1 [ 0.984549] initcall usb_phy_generic_init+0x0/0x14 returned 0 after 0 usecs [ 0.984550] calling serio_init+0x0/0x2c @ 1 [ 0.984554] initcall serio_init+0x0/0x2c returned 0 after 0 usecs [ 0.984555] calling input_init+0x0/0x10a @ 1 [ 0.984559] initcall input_init+0x0/0x10a returned 0 after 0 usecs [ 0.984560] calling rtc_init+0x0/0x4f @ 1 [ 0.984563] initcall rtc_init+0x0/0x4f returned 0 after 0 usecs [ 0.984564] calling power_supply_class_init+0x0/0x40 @ 1 [ 0.984566] initcall power_supply_class_init+0x0/0x40 returned 0 after 0 usecs [ 0.984567] calling hwmon_init+0x0/0xdd @ 1 [ 0.984571] initcall hwmon_init+0x0/0xdd returned 0 after 0 usecs [ 0.984572] calling md_init+0x0/0x165 @ 1 [ 0.984596] initcall md_init+0x0/0x165 returned 0 after 0 usecs [ 0.984597] calling mmc_init+0x0/0x3f @ 1 [ 0.984607] initcall mmc_init+0x0/0x3f returned 0 after 0 usecs [ 0.984609] calling leds_init+0x0/0x3c @ 1 [ 0.984611] initcall leds_init+0x0/0x3c returned 0 after 0 usecs [ 0.984612] calling dmi_init+0x0/0x11c @ 1 [ 0.984619] initcall dmi_init+0x0/0x11c returned 0 after 0 usecs [ 0.984621] calling efisubsys_init+0x0/0x14d @ 1 [ 0.984638] initcall efisubsys_init+0x0/0x14d returned 0 after 0 usecs [ 0.984639] calling devfreq_init+0x0/0xa9 @ 1 [ 0.984659] initcall devfreq_init+0x0/0xa9 returned 0 after 0 usecs [ 0.984660] calling devfreq_simple_ondemand_init+0x0/0x12 @ 1 [ 0.984662] initcall devfreq_simple_ondemand_init+0x0/0x12 returned 0 after 0 usecs [ 0.984663] calling devfreq_performance_init+0x0/0x12 @ 1 [ 0.984664] initcall devfreq_performance_init+0x0/0x12 returned 0 after 0 usecs [ 0.984665] calling devfreq_powersave_init+0x0/0x12 @ 1 [ 0.984666] initcall devfreq_powersave_init+0x0/0x12 returned 0 after 0 usecs [ 0.984667] calling devfreq_userspace_init+0x0/0x12 @ 1 [ 0.984669] initcall devfreq_userspace_init+0x0/0x12 returned 0 after 0 usecs [ 0.984670] calling ras_init+0x0/0x10 @ 1 [ 0.984673] initcall ras_init+0x0/0x10 returned 0 after 0 usecs [ 0.984674] calling pci_subsys_init+0x0/0x48 @ 1 [ 0.984675] PCI: Using ACPI for IRQ routing [ 0.986400] PCI: pci_cache_line_size set to 64 bytes [ 0.986538] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff] [ 0.986539] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff] [ 0.986540] e820: reserve RAM buffer [mem 0x0f000000-0x0fffffff] [ 0.986540] e820: reserve RAM buffer [mem 0x77ff9000-0x77ffffff] [ 0.986541] e820: reserve RAM buffer [mem 0x7ac2c000-0x7bffffff] [ 0.986542] e820: reserve RAM buffer [mem 0x7b000000-0x7bffffff] [ 0.986544] initcall pci_subsys_init+0x0/0x48 returned 0 after 0 usecs [ 0.986545] calling proto_init+0x0/0x12 @ 1 [ 0.986548] initcall proto_init+0x0/0x12 returned 0 after 0 usecs [ 0.986550] calling net_dev_init+0x0/0x1bd @ 1 [ 0.986603] initcall net_dev_init+0x0/0x1bd returned 0 after 0 usecs [ 0.986605] calling neigh_init+0x0/0x80 @ 1 [ 0.986606] initcall neigh_init+0x0/0x80 returned 0 after 0 usecs [ 0.986608] calling fib_rules_init+0x0/0xa8 @ 1 [ 0.986609] initcall fib_rules_init+0x0/0xa8 returned 0 after 0 usecs [ 0.986610] calling pktsched_init+0x0/0x113 @ 1 [ 0.986613] initcall pktsched_init+0x0/0x113 returned 0 after 0 usecs [ 0.986614] calling tc_filter_init+0x0/0x55 @ 1 [ 0.986615] initcall tc_filter_init+0x0/0x55 returned 0 after 0 usecs [ 0.986616] calling tc_action_init+0x0/0x55 @ 1 [ 0.986617] initcall tc_action_init+0x0/0x55 returned 0 after 0 usecs [ 0.986618] calling genl_init+0x0/0x87 @ 1 [ 0.986621] initcall genl_init+0x0/0x87 returned 0 after 0 usecs [ 0.986622] calling ipv4_netfilter_init+0x0/0x12 @ 1 [ 0.986623] initcall ipv4_netfilter_init+0x0/0x12 returned 0 after 0 usecs [ 0.986624] calling cipso_v4_init+0x0/0x6a @ 1 [ 0.986626] initcall cipso_v4_init+0x0/0x6a returned 0 after 0 usecs [ 0.986627] calling wireless_nlevent_init+0x0/0x39 @ 1 [ 0.986628] initcall wireless_nlevent_init+0x0/0x39 returned 0 after 0 usecs [ 0.986629] calling netlbl_init+0x0/0x83 @ 1 [ 0.986630] NetLabel: Initializing [ 0.986632] NetLabel: domain hash size = 128 [ 0.986634] NetLabel: protocols = UNLABELED CIPSOv4 [ 0.986642] NetLabel: unlabeled traffic allowed by default [ 0.986644] initcall netlbl_init+0x0/0x83 returned 0 after 0 usecs [ 0.986645] calling rfkill_init+0x0/0x85 @ 1 [ 0.986669] initcall rfkill_init+0x0/0x85 returned 0 after 0 usecs [ 0.986670] calling xen_mcfg_late+0x0/0xd1 @ 1 [ 0.986672] initcall xen_mcfg_late+0x0/0xd1 returned 0 after 0 usecs [ 0.986673] calling watchdog_init+0x0/0x77 @ 1 [ 0.986697] initcall watchdog_init+0x0/0x77 returned 0 after 0 usecs [ 0.986715] calling nmi_warning_debugfs+0x0/0x27 @ 1 [ 0.986721] initcall nmi_warning_debugfs+0x0/0x27 returned 0 after 0 usecs [ 0.986722] calling hpet_late_init+0x0/0xee @ 1 [ 0.986735] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 [ 0.986741] hpet0: 8 comparators, 64-bit 19.200000 MHz counter [ 0.987244] initcall hpet_late_init+0x0/0xee returned 0 after 0 usecs [ 0.987245] calling init_amd_nbs+0x0/0xc4 @ 1 [ 0.987250] initcall init_amd_nbs+0x0/0xc4 returned 0 after 0 usecs [ 0.987251] calling clocksource_done_booting+0x0/0x42 @ 1 [ 0.987260] clocksource: Switched to clocksource hpet [ 0.987266] initcall clocksource_done_booting+0x0/0x42 returned 0 after 28 usecs [ 0.987267] calling ftrace_init_tracefs+0x0/0x1d0 @ 1 [ 0.987284] initcall ftrace_init_tracefs+0x0/0x1d0 returned 0 after 56 usecs [ 0.987286] calling tracer_init_tracefs+0x0/0x1a4 @ 1 [ 0.987967] initcall tracer_init_tracefs+0x0/0x1a4 returned 0 after 2684 usecs [ 0.987968] calling init_trace_printk_function_export+0x0/0x32 @ 1 [ 0.987973] initcall init_trace_printk_function_export+0x0/0x32 returned 0 after 6 usecs [ 0.987974] calling init_graph_tracefs+0x0/0x32 @ 1 [ 0.987980] initcall init_graph_tracefs+0x0/0x32 returned 0 after 12 usecs [ 0.987981] calling event_trace_init+0x0/0x2df @ 1 [ 0.990910] initcall event_trace_init+0x0/0x2df returned 0 after 11579 usecs [ 0.990913] calling init_kprobe_trace+0x0/0x96 @ 1 [ 0.990918] initcall init_kprobe_trace+0x0/0x96 returned 0 after 11 usecs [ 0.990920] calling init_uprobe_trace+0x0/0x54 @ 1 [ 0.990926] initcall init_uprobe_trace+0x0/0x54 returned 0 after 13 usecs [ 0.990927] calling init_pipe_fs+0x0/0x47 @ 1 [ 0.990938] initcall init_pipe_fs+0x0/0x47 returned 0 after 32 usecs [ 0.990940] calling cgroup_writeback_init+0x0/0x2d @ 1 [ 0.990955] initcall cgroup_writeback_init+0x0/0x2d returned 0 after 47 usecs [ 0.990956] calling inotify_user_setup+0x0/0x4b @ 1 [ 0.990966] initcall inotify_user_setup+0x0/0x4b returned 0 after 18 usecs [ 0.990967] calling eventpoll_init+0x0/0xda @ 1 [ 0.990972] initcall eventpoll_init+0x0/0xda returned 0 after 8 usecs [ 0.990973] calling anon_inode_init+0x0/0x5f @ 1 [ 0.990981] initcall anon_inode_init+0x0/0x5f returned 0 after 18 usecs [ 0.990982] calling proc_locks_init+0x0/0x22 @ 1 [ 0.990987] initcall proc_locks_init+0x0/0x22 returned 0 after 10 usecs [ 0.990988] calling dquot_init+0x0/0x120 @ 1 [ 0.990990] VFS: Disk quotas dquot_6.6.0 [ 0.991004] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) [ 0.991008] initcall dquot_init+0x0/0x120 returned 0 after 67 usecs [ 0.991009] calling quota_init+0x0/0x31 @ 1 [ 0.991017] initcall quota_init+0x0/0x31 returned 0 after 21 usecs [ 0.991019] calling proc_cmdline_init+0x0/0x22 @ 1 [ 0.991023] initcall proc_cmdline_init+0x0/0x22 returned 0 after 8 usecs [ 0.991025] calling proc_consoles_init+0x0/0x22 @ 1 [ 0.991029] initcall proc_consoles_init+0x0/0x22 returned 0 after 6 usecs [ 0.991030] calling proc_cpuinfo_init+0x0/0x22 @ 1 [ 0.991034] initcall proc_cpuinfo_init+0x0/0x22 returned 0 after 6 usecs [ 0.991036] calling proc_devices_init+0x0/0x22 @ 1 [ 0.991049] initcall proc_devices_init+0x0/0x22 returned 0 after 41 usecs [ 0.991051] calling proc_interrupts_init+0x0/0x22 @ 1 [ 0.991055] initcall proc_interrupts_init+0x0/0x22 returned 0 after 6 usecs [ 0.991056] calling proc_loadavg_init+0x0/0x22 @ 1 [ 0.991060] initcall proc_loadavg_init+0x0/0x22 returned 0 after 6 usecs [ 0.991061] calling proc_meminfo_init+0x0/0x22 @ 1 [ 0.991065] initcall proc_meminfo_init+0x0/0x22 returned 0 after 6 usecs [ 0.991067] calling proc_stat_init+0x0/0x22 @ 1 [ 0.991071] initcall proc_stat_init+0x0/0x22 returned 0 after 6 usecs [ 0.991072] calling proc_uptime_init+0x0/0x22 @ 1 [ 0.991076] initcall proc_uptime_init+0x0/0x22 returned 0 after 6 usecs [ 0.991078] calling proc_version_init+0x0/0x22 @ 1 [ 0.991082] initcall proc_version_init+0x0/0x22 returned 0 after 6 usecs [ 0.991083] calling proc_softirqs_init+0x0/0x22 @ 1 [ 0.991087] initcall proc_softirqs_init+0x0/0x22 returned 0 after 6 usecs [ 0.991088] calling proc_kcore_init+0x0/0x182 @ 1 [ 0.991095] initcall proc_kcore_init+0x0/0x182 returned 0 after 14 usecs [ 0.991096] calling vmcore_init+0x0/0x56a @ 1 [ 0.991100] initcall vmcore_init+0x0/0x56a returned 0 after 6 usecs [ 0.991101] calling proc_kmsg_init+0x0/0x25 @ 1 [ 0.991105] initcall proc_kmsg_init+0x0/0x25 returned 0 after 6 usecs [ 0.991107] calling proc_page_init+0x0/0x5f @ 1 [ 0.991111] initcall proc_page_init+0x0/0x5f returned 0 after 8 usecs [ 0.991113] calling init_ramfs_fs+0x0/0x20 @ 1 [ 0.991116] initcall init_ramfs_fs+0x0/0x20 returned 0 after 4 usecs [ 0.991117] calling init_hugetlbfs_fs+0x0/0x160 @ 1 [ 0.991134] initcall init_hugetlbfs_fs+0x0/0x160 returned 0 after 55 usecs [ 0.991136] calling tomoyo_initerface_init+0x0/0x17b @ 1 [ 0.991139] initcall tomoyo_initerface_init+0x0/0x17b returned 0 after 4 usecs [ 0.991140] calling aa_create_aafs+0x0/0xc1 @ 1 [ 0.991157] AppArmor: AppArmor Filesystem Enabled [ 0.991162] initcall aa_create_aafs+0x0/0xc1 returned 0 after 72 usecs [ 0.991163] calling blk_scsi_ioctl_init+0x0/0x2c5 @ 1 [ 0.991167] initcall blk_scsi_ioctl_init+0x0/0x2c5 returned 0 after 6 usecs [ 0.991168] calling dynamic_debug_init_debugfs+0x0/0x69 @ 1 [ 0.991175] initcall dynamic_debug_init_debugfs+0x0/0x69 returned 0 after 17 usecs [ 0.991176] calling fb_console_init+0x0/0x116 @ 1 [ 0.991195] initcall fb_console_init+0x0/0x116 returned 0 after 65 usecs [ 0.991197] calling simplefb_init+0x0/0x14 @ 1 [ 0.991208] initcall simplefb_init+0x0/0x14 returned 0 after 34 usecs [ 0.991209] calling acpi_event_init+0x0/0x3d @ 1 [ 0.991215] initcall acpi_event_init+0x0/0x3d returned 0 after 13 usecs [ 0.991217] calling pnp_system_init+0x0/0x12 @ 1 [ 0.991224] initcall pnp_system_init+0x0/0x12 returned 0 after 18 usecs [ 0.991225] calling pnpacpi_init+0x0/0x74 @ 1 [ 0.991227] pnp: PnP ACPI init [ 0.991324] system 00:00: [io 0x06a4] has been reserved [ 0.991328] system 00:00: [io 0x06a0] has been reserved [ 0.991331] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.991414] system 00:01: [io 0x0680-0x069f] has been reserved [ 0.991417] system 00:01: [io 0x0400-0x047f] has been reserved [ 0.991420] system 00:01: [io 0x0500-0x05fe] has been reserved [ 0.991422] system 00:01: [io 0x0600-0x061f] has been reserved [ 0.991425] system 00:01: [io 0x164e-0x164f] has been reserved [ 0.991428] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.991469] pnp 00:02: Plug and Play ACPI device, IDs PNP0303 (active) [ 0.991742] system 00:03: [mem 0xe0000000-0xefffffff] could not be reserved [ 0.991746] system 00:03: [mem 0xfea00000-0xfeafffff] has been reserved [ 0.991748] system 00:03: [mem 0xfed01000-0xfed01fff] has been reserved [ 0.991751] system 00:03: [mem 0xfed03000-0xfed03fff] has been reserved [ 0.991753] system 00:03: [mem 0xfed06000-0xfed06fff] has been reserved [ 0.991756] system 00:03: [mem 0xfed08000-0xfed09fff] has been reserved [ 0.991758] system 00:03: [mem 0xfed80000-0xfedbffff] has been reserved [ 0.991761] system 00:03: [mem 0xfed1c000-0xfed1cfff] has been reserved [ 0.991763] system 00:03: [mem 0xfee00000-0xfeefffff] has been reserved [ 0.991767] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.991894] pnp 00:04: Plug and Play ACPI device, IDs PNP0b00 (active) [ 0.991984] pnp: PnP ACPI: found 5 devices [ 0.991989] initcall pnpacpi_init+0x0/0x74 returned 0 after 3013 usecs [ 0.991991] calling chr_dev_init+0x0/0xad @ 1 [ 0.993897] initcall chr_dev_init+0x0/0xad returned 0 after 7534 usecs [ 0.993899] calling firmware_class_init+0x0/0xec @ 1 [ 0.993907] initcall firmware_class_init+0x0/0xec returned 0 after 19 usecs [ 0.993908] calling thermal_init+0x0/0xd2 @ 1 [ 0.993919] initcall thermal_init+0x0/0xd2 returned 0 after 35 usecs [ 0.993921] calling cpufreq_gov_performance_init+0x0/0x12 @ 1 [ 0.993925] initcall cpufreq_gov_performance_init+0x0/0x12 returned 0 after 5 usecs [ 0.993926] calling init_acpi_pm_clocksource+0x0/0xd7 @ 1 [ 0.998396] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns [ 0.998402] initcall init_acpi_pm_clocksource+0x0/0xd7 returned 0 after 17716 usecs [ 0.998404] calling pcibios_assign_resources+0x0/0xb4 @ 1 [ 0.998424] pci 0000:00:13.0: PCI bridge to [bus 01] [ 0.998430] pci 0000:00:13.3: PCI bridge to [bus 02] [ 0.998435] pci 0000:00:14.0: PCI bridge to [bus 03] [ 0.998442] pci 0000:00:14.0: bridge window [mem 0x92100000-0x921fffff] [ 0.998452] pci_bus 0000:00: resource 4 [io 0x0070-0x0077] [ 0.998453] pci_bus 0000:00: resource 5 [io 0x0000-0x006f window] [ 0.998454] pci_bus 0000:00: resource 6 [io 0x0078-0x0cf7 window] [ 0.998455] pci_bus 0000:00: resource 7 [io 0x0d00-0xffff window] [ 0.998456] pci_bus 0000:00: resource 8 [mem 0x000a0000-0x000bffff window] [ 0.998457] pci_bus 0000:00: resource 9 [mem 0x000c0000-0x000dffff window] [ 0.998459] pci_bus 0000:00: resource 10 [mem 0x000e0000-0x000fffff window] [ 0.998460] pci_bus 0000:00: resource 11 [mem 0x7c000001-0x7fffffff window] [ 0.998461] pci_bus 0000:00: resource 12 [mem 0x80000000-0xbfffffff window] [ 0.998462] pci_bus 0000:00: resource 13 [mem 0xe0000000-0xefffffff window] [ 0.998463] pci_bus 0000:00: resource 14 [mem 0xfea00000-0xfeafffff window] [ 0.998464] pci_bus 0000:00: resource 15 [mem 0xfed00000-0xfed003ff window] [ 0.998465] pci_bus 0000:00: resource 16 [mem 0xfed01000-0xfed01fff window] [ 0.998467] pci_bus 0000:00: resource 17 [mem 0xfed03000-0xfed03fff window] [ 0.998468] pci_bus 0000:00: resource 18 [mem 0xfed06000-0xfed06fff window] [ 0.998469] pci_bus 0000:00: resource 19 [mem 0xfed08000-0xfed09fff window] [ 0.998470] pci_bus 0000:00: resource 20 [mem 0xfed80000-0xfedbffff window] [ 0.998471] pci_bus 0000:00: resource 21 [mem 0xfed1c000-0xfed1cfff window] [ 0.998472] pci_bus 0000:00: resource 22 [mem 0xfee00000-0xfeefffff window] [ 0.998473] pci_bus 0000:03: resource 1 [mem 0x92100000-0x921fffff] [ 0.998476] initcall pcibios_assign_resources+0x0/0xb4 returned 0 after 277 usecs [ 0.998478] calling sysctl_core_init+0x0/0x2c @ 1 [ 0.998488] initcall sysctl_core_init+0x0/0x2c returned 0 after 30 usecs [ 0.998489] calling eth_offload_init+0x0/0x14 @ 1 [ 0.998493] initcall eth_offload_init+0x0/0x14 returned 0 after 4 usecs [ 0.998494] calling inet_init+0x0/0x28a @ 1 [ 0.998504] NET: Registered protocol family 2 [ 0.998610] TCP established hash table entries: 65536 (order: 7, 524288 bytes) [ 0.998744] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes) [ 0.998920] TCP: Hash tables configured (established 65536 bind 65536) [ 0.998944] UDP hash table entries: 4096 (order: 5, 131072 bytes) [ 0.998982] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes) [ 0.999045] initcall inet_init+0x0/0x28a returned 0 after 2164 usecs [ 0.999047] calling ipv4_offload_init+0x0/0x61 @ 1 [ 0.999051] initcall ipv4_offload_init+0x0/0x61 returned 0 after 6 usecs [ 0.999052] calling af_unix_init+0x0/0x50 @ 1 [ 0.999054] NET: Registered protocol family 1 [ 0.999061] initcall af_unix_init+0x0/0x50 returned 0 after 25 usecs [ 0.999062] calling ipv6_offload_init+0x0/0x83 @ 1 [ 0.999066] initcall ipv6_offload_init+0x0/0x83 returned 0 after 6 usecs [ 0.999067] calling pci_apply_final_quirks+0x0/0x103 @ 1 [ 0.999076] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff] [ 0.999278] PCI: CLS 0 bytes, default 64 [ 0.999281] initcall pci_apply_final_quirks+0x0/0x103 returned 0 after 835 usecs [ 0.999282] calling acpi_reserve_resources+0x0/0xeb @ 1 [ 0.999287] initcall acpi_reserve_resources+0x0/0xeb returned 0 after 9 usecs [ 0.999288] calling populate_rootfs+0x0/0x104 @ 1 [ 0.999317] Trying to unpack rootfs image as initramfs... [ 1.385747] Freeing initrd memory: 37312K (ffff880072928000 - ffff880074d98000) [ 1.385756] initcall populate_rootfs+0x0/0x104 returned 0 after 1530456 usecs [ 1.385758] calling pci_iommu_init+0x0/0x3c @ 1 [ 1.385760] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 1.385763] software IO TLB [mem 0x6e928000-0x72928000] (64MB) mapped at [ffff88006e928000-ffff880072927fff] [ 1.385767] initcall pci_iommu_init+0x0/0x3c returned 0 after 28 usecs [ 1.385769] calling calgary_fixup_tce_spaces+0x0/0xf2 @ 1 [ 1.385772] initcall calgary_fixup_tce_spaces+0x0/0xf2 returned -19 after 4 usecs [ 1.385774] calling ir_dev_scope_init+0x0/0x34 @ 1 [ 1.385777] initcall ir_dev_scope_init+0x0/0x34 returned 0 after 4 usecs [ 1.385794] calling ia32_binfmt_init+0x0/0x14 @ 1 [ 1.385801] initcall ia32_binfmt_init+0x0/0x14 returned 0 after 15 usecs [ 1.385802] calling amd_uncore_init+0x0/0x239 @ 1 [ 1.385805] initcall amd_uncore_init+0x0/0x239 returned -19 after 4 usecs [ 1.385806] calling amd_ibs_init+0x0/0x1bc @ 1 [ 1.385810] initcall amd_ibs_init+0x0/0x1bc returned -19 after 4 usecs [ 1.385811] calling msr_init+0x0/0xc4 @ 1 [ 1.385816] initcall msr_init+0x0/0xc4 returned 0 after 13 usecs [ 1.385817] calling amd_iommu_pc_init+0x0/0x151 @ 1 [ 1.385822] initcall amd_iommu_pc_init+0x0/0x151 returned -19 after 9 usecs [ 1.385823] calling intel_cqm_init+0x0/0x4ba @ 1 [ 1.385827] initcall intel_cqm_init+0x0/0x4ba returned -19 after 4 usecs [ 1.385828] calling rapl_pmu_init+0x0/0x285 @ 1 [ 1.385831] initcall rapl_pmu_init+0x0/0x285 returned -19 after 5 usecs [ 1.385832] calling intel_uncore_init+0x0/0x2db @ 1 [ 1.385836] initcall intel_uncore_init+0x0/0x2db returned -19 after 4 usecs [ 1.385837] calling cstate_pmu_init+0x0/0x167 @ 1 [ 1.385840] initcall cstate_pmu_init+0x0/0x167 returned -19 after 4 usecs [ 1.385842] calling register_kernel_offset_dumper+0x0/0x1b @ 1 [ 1.385846] initcall register_kernel_offset_dumper+0x0/0x1b returned 0 after 6 usecs [ 1.385847] calling i8259A_init_ops+0x0/0x24 @ 1 [ 1.385851] initcall i8259A_init_ops+0x0/0x24 returned 0 after 4 usecs [ 1.385852] calling init_tsc_clocksource+0x0/0xb7 @ 1 [ 1.385859] initcall init_tsc_clocksource+0x0/0xb7 returned 0 after 16 usecs [ 1.385860] calling add_rtc_cmos+0x0/0xaa @ 1 [ 1.385864] initcall add_rtc_cmos+0x0/0xaa returned 0 after 7 usecs [ 1.385865] calling i8237A_init_ops+0x0/0x14 @ 1 [ 1.385874] initcall i8237A_init_ops+0x0/0x14 returned 0 after 27 usecs [ 1.385876] calling thermal_throttle_init_device+0x0/0x82 @ 1 [ 1.385888] initcall thermal_throttle_init_device+0x0/0x82 returned 0 after 38 usecs [ 1.385890] calling ioapic_init_ops+0x0/0x14 @ 1 [ 1.385893] initcall ioapic_init_ops+0x0/0x14 returned 0 after 4 usecs [ 1.385894] calling add_pcspkr+0x0/0x40 @ 1 [ 1.385915] initcall add_pcspkr+0x0/0x40 returned 0 after 70 usecs [ 1.385917] calling start_periodic_check_for_corruption+0x0/0x60 @ 1 [ 1.385919] Scanning for low memory corruption every 60 seconds [ 1.385924] initcall start_periodic_check_for_corruption+0x0/0x60 returned 0 after 17 usecs [ 1.385925] calling sysfb_init+0x0/0x6f @ 1 [ 1.385950] initcall sysfb_init+0x0/0x6f returned 0 after 85 usecs [ 1.385951] calling audit_classes_init+0x0/0xaf @ 1 [ 1.385956] initcall audit_classes_init+0x0/0xaf returned 0 after 11 usecs [ 1.385957] calling crc32c_intel_mod_init+0x0/0x69 @ 1 [ 1.386015] initcall crc32c_intel_mod_init+0x0/0x69 returned 0 after 217 usecs [ 1.386017] calling pmc_atom_init+0x0/0x1c3 @ 1 [ 1.386025] initcall pmc_atom_init+0x0/0x1c3 returned -19 after 22 usecs [ 1.386026] calling iosf_mbi_init+0x0/0x1b @ 1 [ 1.386039] initcall iosf_mbi_init+0x0/0x1b returned 0 after 37 usecs [ 1.386040] calling proc_execdomains_init+0x0/0x22 @ 1 [ 1.386045] initcall proc_execdomains_init+0x0/0x22 returned 0 after 9 usecs [ 1.386046] calling cpuhp_sysfs_init+0x0/0x6a @ 1 [ 1.386055] initcall cpuhp_sysfs_init+0x0/0x6a returned 0 after 25 usecs [ 1.386057] calling ioresources_init+0x0/0x3c @ 1 [ 1.386061] initcall ioresources_init+0x0/0x3c returned 0 after 8 usecs [ 1.386063] calling init_sched_debug_procfs+0x0/0x2c @ 1 [ 1.386067] initcall init_sched_debug_procfs+0x0/0x2c returned 0 after 6 usecs [ 1.386068] calling snapshot_device_init+0x0/0x12 @ 1 [ 1.386104] initcall snapshot_device_init+0x0/0x12 returned 0 after 134 usecs [ 1.386106] calling irq_gc_init_ops+0x0/0x14 @ 1 [ 1.386109] initcall irq_gc_init_ops+0x0/0x14 returned 0 after 4 usecs [ 1.386110] calling irq_pm_init_ops+0x0/0x14 @ 1 [ 1.386113] initcall irq_pm_init_ops+0x0/0x14 returned 0 after 4 usecs [ 1.386115] calling init_posix_timers+0x0/0x243 @ 1 [ 1.386122] initcall init_posix_timers+0x0/0x243 returned 0 after 20 usecs [ 1.386123] calling init_posix_cpu_timers+0x0/0x96 @ 1 [ 1.386127] initcall init_posix_cpu_timers+0x0/0x96 returned 0 after 4 usecs [ 1.386128] calling timekeeping_init_ops+0x0/0x14 @ 1 [ 1.386131] initcall timekeeping_init_ops+0x0/0x14 returned 0 after 4 usecs [ 1.386132] calling init_clocksource_sysfs+0x0/0x69 @ 1 [ 1.386155] initcall init_clocksource_sysfs+0x0/0x69 returned 0 after 78 usecs [ 1.386156] calling init_timer_list_procfs+0x0/0x2c @ 1 [ 1.386160] initcall init_timer_list_procfs+0x0/0x2c returned 0 after 7 usecs [ 1.386161] calling alarmtimer_init+0x0/0x168 @ 1 [ 1.386187] initcall alarmtimer_init+0x0/0x168 returned 0 after 90 usecs [ 1.386188] calling clockevents_init_sysfs+0x0/0xcb @ 1 [ 1.386239] initcall clockevents_init_sysfs+0x0/0xcb returned 0 after 189 usecs [ 1.386240] calling init_tstats_procfs+0x0/0x2c @ 1 [ 1.386245] initcall init_tstats_procfs+0x0/0x2c returned 0 after 7 usecs [ 1.386246] calling futex_init+0x0/0xee @ 1 [ 1.386251] futex hash table entries: 1024 (order: 4, 65536 bytes) [ 1.386260] initcall futex_init+0x0/0xee returned 0 after 49 usecs [ 1.386261] calling proc_dma_init+0x0/0x22 @ 1 [ 1.386266] initcall proc_dma_init+0x0/0x22 returned 0 after 7 usecs [ 1.386267] calling proc_modules_init+0x0/0x22 @ 1 [ 1.386271] initcall proc_modules_init+0x0/0x22 returned 0 after 6 usecs [ 1.386272] calling kallsyms_init+0x0/0x25 @ 1 [ 1.386277] initcall kallsyms_init+0x0/0x25 returned 0 after 6 usecs [ 1.386278] calling pid_namespaces_init+0x0/0x40 @ 1 [ 1.386285] initcall pid_namespaces_init+0x0/0x40 returned 0 after 17 usecs [ 1.386286] calling audit_init+0x0/0xf7 @ 1 [ 1.386288] audit: initializing netlink subsys (disabled) [ 1.386297] audit: type=2000 audit(2.751:1): initialized [ 1.386302] initcall audit_init+0x0/0xf7 returned 0 after 50 usecs [ 1.386303] calling audit_watch_init+0x0/0x3a @ 1 [ 1.386306] initcall audit_watch_init+0x0/0x3a returned 0 after 4 usecs [ 1.386307] calling audit_fsnotify_init+0x0/0x3a @ 1 [ 1.386311] initcall audit_fsnotify_init+0x0/0x3a returned 0 after 4 usecs [ 1.386312] calling audit_tree_init+0x0/0x49 @ 1 [ 1.386316] initcall audit_tree_init+0x0/0x49 returned 0 after 5 usecs [ 1.386317] calling init_kprobes+0x0/0x1b5 @ 1 [ 1.386429] initcall init_kprobes+0x0/0x1b5 returned 0 after 435 usecs [ 1.386430] calling utsname_sysctl_init+0x0/0x14 @ 1 [ 1.386437] initcall utsname_sysctl_init+0x0/0x14 returned 0 after 14 usecs [ 1.386438] calling init_tracepoints+0x0/0x2a @ 1 [ 1.386441] initcall init_tracepoints+0x0/0x2a returned 0 after 4 usecs [ 1.386442] calling init_lstats_procfs+0x0/0x25 @ 1 [ 1.386447] initcall init_lstats_procfs+0x0/0x25 returned 0 after 7 usecs [ 1.386448] calling stack_trace_init+0x0/0xb0 @ 1 [ 1.386455] initcall stack_trace_init+0x0/0xb0 returned 0 after 16 usecs [ 1.386456] calling init_mmio_trace+0x0/0x12 @ 1 [ 1.386461] initcall init_mmio_trace+0x0/0x12 returned 0 after 8 usecs [ 1.386463] calling init_blk_tracer+0x0/0x58 @ 1 [ 1.386468] initcall init_blk_tracer+0x0/0x58 returned 0 after 10 usecs [ 1.386469] calling perf_event_sysfs_init+0x0/0x93 @ 1 [ 1.386551] initcall perf_event_sysfs_init+0x0/0x93 returned 0 after 311 usecs [ 1.386552] calling init_uprobes+0x0/0x63 @ 1 [ 1.386557] initcall init_uprobes+0x0/0x63 returned 0 after 8 usecs [ 1.386558] calling system_trusted_keyring_init+0x0/0x74 @ 1 [ 1.386560] Initialise system trusted keyrings [ 1.386568] initcall system_trusted_keyring_init+0x0/0x74 returned 0 after 28 usecs [ 1.386569] calling kswapd_init+0x0/0x6e @ 1 [ 1.386601] initcall kswapd_init+0x0/0x6e returned 0 after 115 usecs [ 1.386602] calling extfrag_debug_init+0x0/0x7a @ 1 [ 1.386608] initcall extfrag_debug_init+0x0/0x7a returned 0 after 13 usecs [ 1.386609] calling setup_vmstat+0x0/0x19a @ 1 [ 1.386660] initcall setup_vmstat+0x0/0x19a returned 0 after 188 usecs [ 1.386662] calling mm_compute_batch_init+0x0/0x19 @ 1 [ 1.386667] initcall mm_compute_batch_init+0x0/0x19 returned 0 after 9 usecs [ 1.386668] calling slab_proc_init+0x0/0x25 @ 1 [ 1.386674] initcall slab_proc_init+0x0/0x25 returned 0 after 6 usecs [ 1.386675] calling workingset_init+0x0/0x87 @ 1 [ 1.386677] workingset: timestamp_bits=38 max_order=21 bucket_order=0 [ 1.386682] initcall workingset_init+0x0/0x87 returned 0 after 18 usecs [ 1.386683] calling proc_vmalloc_init+0x0/0x25 @ 1 [ 1.386687] initcall proc_vmalloc_init+0x0/0x25 returned 0 after 6 usecs [ 1.386688] calling procswaps_init+0x0/0x22 @ 1 [ 1.386692] initcall procswaps_init+0x0/0x22 returned 0 after 7 usecs [ 1.386693] calling init_frontswap+0x0/0x93 @ 1 [ 1.386700] initcall init_frontswap+0x0/0x93 returned 0 after 15 usecs [ 1.386701] calling slab_sysfs_init+0x0/0xf6 @ 1 [ 1.387793] initcall slab_sysfs_init+0x0/0xf6 returned 0 after 4312 usecs [ 1.387795] calling init_cleancache+0x0/0x93 @ 1 [ 1.387801] initcall init_cleancache+0x0/0x93 returned 0 after 15 usecs [ 1.387803] calling zs_init+0x0/0x88 @ 1 [ 1.387807] initcall zs_init+0x0/0x88 returned 0 after 7 usecs [ 1.387808] calling fcntl_init+0x0/0x2a @ 1 [ 1.387814] initcall fcntl_init+0x0/0x2a returned 0 after 12 usecs [ 1.387815] calling proc_filesystems_init+0x0/0x22 @ 1 [ 1.387820] initcall proc_filesystems_init+0x0/0x22 returned 0 after 7 usecs [ 1.387821] calling start_dirtytime_writeback+0x0/0x2a @ 1 [ 1.387825] initcall start_dirtytime_writeback+0x0/0x2a returned 0 after 6 usecs [ 1.387826] calling dio_init+0x0/0x2d @ 1 [ 1.387831] initcall dio_init+0x0/0x2d returned 0 after 9 usecs [ 1.387832] calling dnotify_init+0x0/0x7b @ 1 [ 1.387838] initcall dnotify_init+0x0/0x7b returned 0 after 11 usecs [ 1.387839] calling fanotify_user_setup+0x0/0x77 @ 1 [ 1.387846] initcall fanotify_user_setup+0x0/0x77 returned 0 after 14 usecs [ 1.387847] calling aio_setup+0x0/0xa7 @ 1 [ 1.387859] initcall aio_setup+0x0/0xa7 returned 0 after 34 usecs [ 1.387860] calling init_sys32_ioctl+0x0/0x28 @ 1 [ 1.387904] initcall init_sys32_ioctl+0x0/0x28 returned 0 after 164 usecs [ 1.387905] calling mbcache_init+0x0/0x31 @ 1 [ 1.387929] initcall mbcache_init+0x0/0x31 returned 0 after 79 usecs [ 1.387930] calling init_devpts_fs+0x0/0x28 @ 1 [ 1.387939] initcall init_devpts_fs+0x0/0x28 returned 0 after 23 usecs [ 1.387940] calling ext4_init_fs+0x0/0x19f @ 1 [ 1.388011] initcall ext4_init_fs+0x0/0x19f returned 0 after 268 usecs [ 1.388012] calling journal_init+0x0/0x104 @ 1 [ 1.388077] initcall journal_init+0x0/0x104 returned 0 after 247 usecs [ 1.388078] calling init_fat_fs+0x0/0x4a @ 1 [ 1.388110] initcall init_fat_fs+0x0/0x4a returned 0 after 115 usecs [ 1.388112] calling init_vfat_fs+0x0/0x12 @ 1 [ 1.388116] initcall init_vfat_fs+0x0/0x12 returned 0 after 6 usecs [ 1.388117] calling ecryptfs_init+0x0/0x1ba @ 1 [ 1.388261] initcall ecryptfs_init+0x0/0x1ba returned 0 after 560 usecs [ 1.388263] calling init_nls_cp437+0x0/0x14 @ 1 [ 1.388266] initcall init_nls_cp437+0x0/0x14 returned 0 after 4 usecs [ 1.388267] calling fuse_init+0x0/0x1ad @ 1 [ 1.388269] fuse init (API version 7.24) [ 1.388335] initcall fuse_init+0x0/0x1ad returned 0 after 257 usecs [ 1.388337] calling init_pstore_fs+0x0/0x47 @ 1 [ 1.388341] initcall init_pstore_fs+0x0/0x47 returned 0 after 7 usecs [ 1.388342] calling efivarfs_init+0x0/0x34 @ 1 [ 1.388346] initcall efivarfs_init+0x0/0x34 returned 0 after 6 usecs [ 1.388347] calling ipc_init+0x0/0x17 @ 1 [ 1.388352] initcall ipc_init+0x0/0x17 returned 0 after 10 usecs [ 1.388353] calling ipc_sysctl_init+0x0/0x14 @ 1 [ 1.388361] initcall ipc_sysctl_init+0x0/0x14 returned 0 after 20 usecs [ 1.388362] calling init_mqueue_fs+0x0/0xa1 @ 1 [ 1.388390] initcall init_mqueue_fs+0x0/0xa1 returned 0 after 96 usecs [ 1.388391] calling key_proc_init+0x0/0x5e @ 1 [ 1.388396] initcall key_proc_init+0x0/0x5e returned 0 after 10 usecs [ 1.388397] calling big_key_init+0x0/0x12 @ 1 [ 1.388400] Key type big_key registered [ 1.388403] initcall big_key_init+0x0/0x12 returned 0 after 14 usecs [ 1.388405] calling selinux_nf_ip_init+0x0/0x47 @ 1 [ 1.388408] initcall selinux_nf_ip_init+0x0/0x47 returned 0 after 4 usecs [ 1.388409] calling init_sel_fs+0x0/0x9a @ 1 [ 1.388413] initcall init_sel_fs+0x0/0x9a returned 0 after 4 usecs [ 1.388414] calling selnl_init+0x0/0x56 @ 1 [ 1.388420] initcall selnl_init+0x0/0x56 returned 0 after 14 usecs [ 1.388421] calling sel_netif_init+0x0/0x3a @ 1 [ 1.388425] initcall sel_netif_init+0x0/0x3a returned 0 after 4 usecs [ 1.388426] calling sel_netnode_init+0x0/0x32 @ 1 [ 1.388430] initcall sel_netnode_init+0x0/0x32 returned 0 after 5 usecs [ 1.388431] calling sel_netport_init+0x0/0x32 @ 1 [ 1.388434] initcall sel_netport_init+0x0/0x32 returned 0 after 4 usecs [ 1.388435] calling aurule_init+0x0/0x2d @ 1 [ 1.388439] initcall aurule_init+0x0/0x2d returned 0 after 4 usecs [ 1.388440] calling init_smk_fs+0x0/0x128 @ 1 [ 1.388444] initcall init_smk_fs+0x0/0x128 returned 0 after 4 usecs [ 1.388445] calling crypto_algapi_init+0x0/0xd @ 1 [ 1.388449] initcall crypto_algapi_init+0x0/0xd returned 0 after 7 usecs [ 1.388451] calling chainiv_module_init+0x0/0x12 @ 1 [ 1.388455] initcall chainiv_module_init+0x0/0x12 returned 0 after 6 usecs [ 1.388456] calling eseqiv_module_init+0x0/0x12 @ 1 [ 1.388459] initcall eseqiv_module_init+0x0/0x12 returned 0 after 4 usecs [ 1.388461] calling rsa_init+0x0/0x50 @ 1 [ 1.388509] initcall rsa_init+0x0/0x50 returned 0 after 177 usecs [ 1.388511] calling hmac_module_init+0x0/0x12 @ 1 [ 1.388514] initcall hmac_module_init+0x0/0x12 returned 0 after 4 usecs [ 1.388515] calling crypto_null_mod_init+0x0/0x44 @ 1 [ 1.388702] initcall crypto_null_mod_init+0x0/0x44 returned 0 after 725 usecs [ 1.388703] calling md5_mod_init+0x0/0x12 @ 1 [ 1.388763] initcall md5_mod_init+0x0/0x12 returned 0 after 222 usecs [ 1.388764] calling sha1_generic_mod_init+0x0/0x12 @ 1 [ 1.388820] initcall sha1_generic_mod_init+0x0/0x12 returned 0 after 208 usecs [ 1.388821] calling sha256_generic_mod_init+0x0/0x17 @ 1 [ 1.388919] initcall sha256_generic_mod_init+0x0/0x17 returned 0 after 373 usecs [ 1.388921] calling sha512_generic_mod_init+0x0/0x17 @ 1 [ 1.389020] initcall sha512_generic_mod_init+0x0/0x17 returned 0 after 378 usecs [ 1.389021] calling crypto_ecb_module_init+0x0/0x12 @ 1 [ 1.389025] initcall crypto_ecb_module_init+0x0/0x12 returned 0 after 5 usecs [ 1.389026] calling crypto_cbc_module_init+0x0/0x12 @ 1 [ 1.389030] initcall crypto_cbc_module_init+0x0/0x12 returned 0 after 4 usecs [ 1.389031] calling aes_init+0x0/0x12 @ 1 [ 1.389086] initcall aes_init+0x0/0x12 returned 0 after 203 usecs [ 1.389087] calling crc32c_mod_init+0x0/0x12 @ 1 [ 1.389133] initcall crc32c_mod_init+0x0/0x12 returned 0 after 171 usecs [ 1.389135] calling crct10dif_mod_init+0x0/0x12 @ 1 [ 1.389188] initcall crct10dif_mod_init+0x0/0x12 returned 0 after 200 usecs [ 1.389190] calling lzo_mod_init+0x0/0x12 @ 1 [ 1.389245] initcall lzo_mod_init+0x0/0x12 returned 0 after 207 usecs [ 1.389247] calling asymmetric_key_init+0x0/0x12 @ 1 [ 1.389249] Key type asymmetric registered [ 1.389253] initcall asymmetric_key_init+0x0/0x12 returned 0 after 13 usecs [ 1.389254] calling x509_key_init+0x0/0x12 @ 1 [ 1.389256] Asymmetric key parser 'x509' registered [ 1.389260] initcall x509_key_init+0x0/0x12 returned 0 after 13 usecs [ 1.389261] calling proc_genhd_init+0x0/0x3c @ 1 [ 1.389267] initcall proc_genhd_init+0x0/0x3c returned 0 after 12 usecs [ 1.389268] calling bsg_init+0x0/0x12a @ 1 [ 1.389292] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250) [ 1.389297] initcall bsg_init+0x0/0x12a returned 0 after 104 usecs [ 1.389299] calling throtl_init+0x0/0x44 @ 1 [ 1.389340] initcall throtl_init+0x0/0x44 returned 0 after 151 usecs [ 1.389341] calling noop_init+0x0/0x12 @ 1 [ 1.389344] io scheduler noop registered [ 1.389347] initcall noop_init+0x0/0x12 returned 0 after 13 usecs [ 1.389349] calling deadline_init+0x0/0x12 @ 1 [ 1.389352] io scheduler deadline registered (default) [ 1.389356] initcall deadline_init+0x0/0x12 returned 0 after 12 usecs [ 1.389357] calling cfq_init+0x0/0xb7 @ 1 [ 1.389378] io scheduler cfq registered [ 1.389383] initcall cfq_init+0x0/0xb7 returned 0 after 91 usecs [ 1.389384] calling btree_module_init+0x0/0x2a @ 1 [ 1.389389] initcall btree_module_init+0x0/0x2a returned 0 after 9 usecs [ 1.389390] calling crc_t10dif_mod_init+0x0/0x3e @ 1 [ 1.389394] initcall crc_t10dif_mod_init+0x0/0x3e returned 0 after 8 usecs [ 1.389395] calling percpu_counter_startup+0x0/0x19 @ 1 [ 1.389400] initcall percpu_counter_startup+0x0/0x19 returned 0 after 7 usecs [ 1.389401] calling digsig_init+0x0/0x3d @ 1 [ 1.389405] initcall digsig_init+0x0/0x3d returned 0 after 6 usecs [ 1.389406] calling sg_pool_init+0x0/0xcc @ 1 [ 1.389414] initcall sg_pool_init+0x0/0xcc returned 0 after 24 usecs [ 1.389415] calling phy_core_init+0x0/0x4d @ 1 [ 1.389421] initcall phy_core_init+0x0/0x4d returned 0 after 12 usecs [ 1.389422] calling intel_gpio_init+0x0/0x1b @ 1 [ 1.389435] initcall intel_gpio_init+0x0/0x1b returned 0 after 41 usecs [ 1.389436] calling pci_proc_init+0x0/0x65 @ 1 [ 1.389458] initcall pci_proc_init+0x0/0x65 returned 0 after 75 usecs [ 1.389459] calling pcie_portdrv_init+0x0/0x77 @ 1 [ 1.389527] pcieport 0000:00:13.0: can't derive routing for PCI INT C [ 1.389530] pcieport 0000:00:13.0: PCI INT C: not connected [ 1.389621] pcieport 0000:00:13.3: can't derive routing for PCI INT D [ 1.389624] pcieport 0000:00:13.3: PCI INT D: not connected [ 1.389709] pcieport 0000:00:14.0: can't derive routing for PCI INT B [ 1.389712] pcieport 0000:00:14.0: PCI INT B: not connected [ 1.389767] initcall pcie_portdrv_init+0x0/0x77 returned 0 after 1208 usecs [ 1.389769] calling aer_service_init+0x0/0x3e @ 1 [ 1.389775] initcall aer_service_init+0x0/0x3e returned 0 after 17 usecs [ 1.389777] calling pcie_pme_service_init+0x0/0x12 @ 1 [ 1.389793] pcieport 0000:00:13.0: Signaling PME through PCIe PME interrupt [ 1.389797] pcie_pme 0000:00:13.0:pcie001: service driver pcie_pme loaded [ 1.389808] pcieport 0000:00:13.3: Signaling PME through PCIe PME interrupt [ 1.389811] pcie_pme 0000:00:13.3:pcie001: service driver pcie_pme loaded [ 1.389826] pcieport 0000:00:14.0: Signaling PME through PCIe PME interrupt [ 1.389829] pci 0000:03:00.0: Signaling PME through PCIe PME interrupt [ 1.389836] pcie_pme 0000:00:14.0:pcie001: service driver pcie_pme loaded [ 1.389842] initcall pcie_pme_service_init+0x0/0x12 returned 0 after 247 usecs [ 1.389843] calling pci_hotplug_init+0x0/0x4a @ 1 [ 1.389845] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 [ 1.389849] initcall pci_hotplug_init+0x0/0x4a returned 0 after 12 usecs [ 1.389850] calling pcied_init+0x0/0x6f @ 1 [ 1.389854] pciehp: PCI Express Hot Plug Controller Driver version: 0.4 [ 1.389858] initcall pcied_init+0x0/0x6f returned 0 after 25 usecs [ 1.389859] calling imsttfb_init+0x0/0xf6 @ 1 [ 1.389869] initcall imsttfb_init+0x0/0xf6 returned 0 after 29 usecs [ 1.389871] calling asiliantfb_init+0x0/0x34 @ 1 [ 1.389879] initcall asiliantfb_init+0x0/0x34 returned 0 after 23 usecs [ 1.389880] calling vesafb_driver_init+0x0/0x14 @ 1 [ 1.389890] initcall vesafb_driver_init+0x0/0x14 returned 0 after 30 usecs [ 1.389892] calling efifb_driver_init+0x0/0x14 @ 1 [ 1.389898] efifb: probing for efifb [ 1.389909] efifb: framebuffer at 0x80000000, using 8100k, total 8100k [ 1.389912] efifb: mode is 1920x1080x32, linelength=7680, pages=1 [ 1.389914] efifb: scrolling: redraw [ 1.389916] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0 [ 1.393985] Console: switching to colour frame buffer device 240x67 [ 1.397971] fb0: EFI VGA frame buffer device [ 1.397991] initcall efifb_driver_init+0x0/0x14 returned 0 after 32062 usecs [ 1.397992] calling intel_idle_init+0x0/0x66e @ 1 [ 1.397996] intel_idle: does not run on family 6 model 92 [ 1.397998] initcall intel_idle_init+0x0/0x66e returned -19 after 10 usecs [ 1.397999] calling ipmi_init_msghandler_mod+0x0/0xd @ 1 [ 1.398007] ipmi message handler version 39.2 [ 1.398024] initcall ipmi_init_msghandler_mod+0x0/0xd returned 0 after 87 usecs [ 1.398026] calling acpi_ac_init+0x0/0x2e @ 1 [ 1.398074] ACPI: AC Adapter [ADP1] (on-line) [ 1.398098] initcall acpi_ac_init+0x0/0x2e returned 0 after 273 usecs [ 1.398099] calling acpi_button_driver_init+0x0/0x12 @ 1 [ 1.398131] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:01/PNP0C09:00/PNP0C0D:00/input/input0 [ 1.398294] ACPI: Lid Switch [LID0] [ 1.398338] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1 [ 1.398367] ACPI: Power Button [PWRB] [ 1.398403] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 [ 1.398428] ACPI: Power Button [PWRF] [ 1.398448] initcall acpi_button_driver_init+0x0/0x12 returned 0 after 1367 usecs [ 1.398449] calling acpi_fan_driver_init+0x0/0x14 @ 1 [ 1.398486] initcall acpi_fan_driver_init+0x0/0x14 returned 0 after 132 usecs [ 1.398487] calling acpi_processor_driver_init+0x0/0x44 @ 1 [ 1.399352] initcall acpi_processor_driver_init+0x0/0x44 returned 0 after 3411 usecs [ 1.399354] calling acpi_thermal_init+0x0/0x80 @ 1 [ 1.402922] thermal LNXTHERM:00: registered as thermal_zone0 [ 1.402942] ACPI: Thermal Zone [TZ01] (34 C) [ 1.402963] initcall acpi_thermal_init+0x0/0x80 returned 0 after 14278 usecs [ 1.402965] calling acpi_battery_init+0x0/0x2c @ 1 [ 1.402970] initcall acpi_battery_init+0x0/0x2c returned 0 after 10 usecs [ 1.402971] calling acpi_hed_driver_init+0x0/0x12 @ 1 [ 1.402992] initcall acpi_hed_driver_init+0x0/0x12 returned 0 after 65 usecs [ 1.402993] calling bgrt_init+0x0/0x7a @ 1 [ 1.402996] initcall bgrt_init+0x0/0x7a returned -19 after 4 usecs [ 1.402998] calling erst_init+0x0/0x2d9 @ 1 [ 1.403002] initcall erst_init+0x0/0x2d9 returned 0 after 6 usecs [ 1.403003] calling ghes_init+0x0/0x194 @ 1 [ 1.403005] GHES: HEST is not enabled! [ 1.403019] initcall ghes_init+0x0/0x194 returned -22 after 52 usecs [ 1.403020] calling virtio_mmio_init+0x0/0x14 @ 1 [ 1.403033] initcall virtio_mmio_init+0x0/0x14 returned 0 after 39 usecs [ 1.403035] calling virtio_pci_driver_init+0x0/0x1b @ 1 [ 1.403048] initcall virtio_pci_driver_init+0x0/0x1b returned 0 after 40 usecs [ 1.403049] calling virtio_balloon_driver_init+0x0/0x12 @ 1 [ 1.403056] initcall virtio_balloon_driver_init+0x0/0x12 returned 0 after 15 usecs [ 1.403057] calling xenbus_probe_initcall+0x0/0x50 @ 1 [ 1.403061] initcall xenbus_probe_initcall+0x0/0x50 returned -19 after 4 usecs [ 1.403062] calling xenbus_init+0x0/0x3b @ 1 [ 1.403066] initcall xenbus_init+0x0/0x3b returned -19 after 4 usecs [ 1.403067] calling xenbus_backend_init+0x0/0x4d @ 1 [ 1.403071] initcall xenbus_backend_init+0x0/0x4d returned -19 after 4 usecs [ 1.403072] calling hypervisor_subsys_init+0x0/0x27 @ 1 [ 1.403074] ACPI: Battery Slot [BAT0] (battery present) [ 1.403076] initcall hypervisor_subsys_init+0x0/0x27 returned -19 after 4 usecs [ 1.403077] calling hyper_sysfs_init+0x0/0x158 @ 1 [ 1.403080] initcall hyper_sysfs_init+0x0/0x158 returned -19 after 4 usecs [ 1.403081] calling platform_pci_init+0x0/0x1b @ 1 [ 1.403093] initcall platform_pci_init+0x0/0x1b returned 0 after 31 usecs [ 1.403094] calling xen_late_init_mcelog+0x0/0x54 @ 1 [ 1.403098] initcall xen_late_init_mcelog+0x0/0x54 returned -19 after 4 usecs [ 1.403099] calling xen_acpi_processor_init+0x0/0x26e @ 1 [ 1.403102] initcall xen_acpi_processor_init+0x0/0x26e returned -19 after 4 usecs [ 1.403103] calling lp872x_driver_init+0x0/0x14 @ 1 [ 1.403112] initcall lp872x_driver_init+0x0/0x14 returned 0 after 23 usecs [ 1.403113] calling pty_init+0x0/0x3a2 @ 1 [ 1.403119] ACPI: Battery Slot [BAT1] (battery absent) [ 1.403152] initcall pty_init+0x0/0x3a2 returned 0 after 144 usecs [ 1.403154] calling sysrq_init+0x0/0x78 @ 1 [ 1.403159] initcall sysrq_init+0x0/0x78 returned 0 after 12 usecs [ 1.403160] calling xen_hvc_init+0x0/0x23f @ 1 [ 1.403164] initcall xen_hvc_init+0x0/0x23f returned -19 after 4 usecs [ 1.403165] calling serial8250_init+0x0/0x157 @ 1 [ 1.403167] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled [ 1.423259] serial8250: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A [ 1.424340] initcall serial8250_init+0x0/0x157 returned 0 after 83842 usecs [ 1.424342] calling serial_pci_driver_init+0x0/0x1b @ 1 [ 1.424368] initcall serial_pci_driver_init+0x0/0x1b returned 0 after 91 usecs [ 1.424369] calling max310x_uart_driver_init+0x0/0x14 @ 1 [ 1.424377] initcall max310x_uart_driver_init+0x0/0x14 returned 0 after 17 usecs [ 1.424379] calling sccnxp_uart_driver_init+0x0/0x14 @ 1 [ 1.424387] initcall sccnxp_uart_driver_init+0x0/0x14 returned 0 after 22 usecs [ 1.424388] calling init_kgdboc+0x0/0x16 @ 1 [ 1.424392] initcall init_kgdboc+0x0/0x16 returned 0 after 7 usecs [ 1.424393] calling ttyprintk_init+0x0/0xff @ 1 [ 1.424419] initcall ttyprintk_init+0x0/0xff returned 0 after 92 usecs [ 1.424421] calling init+0x0/0x104 @ 1 [ 1.424436] initcall init+0x0/0x104 returned 0 after 50 usecs [ 1.424437] calling hpet_init+0x0/0x65 @ 1 [ 1.424508] initcall hpet_init+0x0/0x65 returned 0 after 270 usecs [ 1.424510] calling hwrng_modinit+0x0/0x12 @ 1 [ 1.424536] initcall hwrng_modinit+0x0/0x12 returned 0 after 95 usecs [ 1.424538] calling agp_init+0x0/0x29 @ 1 [ 1.424540] Linux agpgart interface v0.103 [ 1.424558] initcall agp_init+0x0/0x29 returned 0 after 69 usecs [ 1.424559] calling agp_amd64_mod_init+0x0/0x21 @ 1 [ 1.424578] initcall agp_amd64_mod_init+0x0/0x21 returned -19 after 65 usecs [ 1.424579] calling agp_intel_init+0x0/0x2a @ 1 [ 1.424591] initcall agp_intel_init+0x0/0x2a returned 0 after 35 usecs [ 1.424592] calling agp_via_init+0x0/0x2a @ 1 [ 1.424602] initcall agp_via_init+0x0/0x2a returned 0 after 29 usecs [ 1.424603] calling init_tis+0x0/0xcf @ 1 [ 1.424630] initcall init_tis+0x0/0xcf returned 0 after 95 usecs [ 1.424631] calling cn_proc_init+0x0/0x38 @ 1 [ 1.424636] initcall cn_proc_init+0x0/0x38 returned 0 after 6 usecs [ 1.424637] calling topology_sysfs_init+0x0/0x80 @ 1 [ 1.424654] initcall topology_sysfs_init+0x0/0x80 returned 0 after 57 usecs [ 1.424656] calling cacheinfo_sysfs_init+0x0/0x8a @ 1 [ 1.424811] initcall cacheinfo_sysfs_init+0x0/0x8a returned 0 after 602 usecs [ 1.424812] calling devcoredump_init+0x0/0x19 @ 1 [ 1.424818] initcall devcoredump_init+0x0/0x19 returned 0 after 14 usecs [ 1.424820] calling brd_init+0x0/0x15a @ 1 [ 1.426946] brd: module loaded [ 1.426962] initcall brd_init+0x0/0x15a returned 0 after 8469 usecs [ 1.426964] calling loop_init+0x0/0x14d @ 1 [ 1.428052] loop: module loaded [ 1.428068] initcall loop_init+0x0/0x14d returned 0 after 4358 usecs [ 1.428070] calling init+0x0/0x80 @ 1 [ 1.428082] initcall init+0x0/0x80 returned 0 after 37 usecs [ 1.428083] calling xlblk_init+0x0/0xdf @ 1 [ 1.428089] initcall xlblk_init+0x0/0xdf returned -19 after 9 usecs [ 1.428090] calling htcpld_core_init+0x0/0x2d @ 1 [ 1.428108] initcall htcpld_core_init+0x0/0x2d returned -19 after 61 usecs [ 1.428110] calling wm8994_i2c_driver_init+0x0/0x14 @ 1 [ 1.428117] initcall wm8994_i2c_driver_init+0x0/0x14 returned 0 after 16 usecs [ 1.428119] calling tps65912_i2c_driver_init+0x0/0x14 @ 1 [ 1.428125] initcall tps65912_i2c_driver_init+0x0/0x14 returned 0 after 15 usecs [ 1.428127] calling tps65912_spi_driver_init+0x0/0x14 @ 1 [ 1.428133] initcall tps65912_spi_driver_init+0x0/0x14 returned 0 after 16 usecs [ 1.428135] calling twl6040_driver_init+0x0/0x14 @ 1 [ 1.428141] initcall twl6040_driver_init+0x0/0x14 returned 0 after 15 usecs [ 1.428142] calling smsc_i2c_driver_init+0x0/0x14 @ 1 [ 1.428150] initcall smsc_i2c_driver_init+0x0/0x14 returned 0 after 18 usecs [ 1.428151] calling da9063_i2c_driver_init+0x0/0x14 @ 1 [ 1.428158] initcall da9063_i2c_driver_init+0x0/0x14 returned 0 after 15 usecs [ 1.428159] calling max77693_i2c_driver_init+0x0/0x14 @ 1 [ 1.428165] initcall max77693_i2c_driver_init+0x0/0x14 returned 0 after 15 usecs [ 1.428167] calling adp5520_driver_init+0x0/0x14 @ 1 [ 1.428175] initcall adp5520_driver_init+0x0/0x14 returned 0 after 21 usecs [ 1.428176] calling intel_soc_pmic_i2c_driver_init+0x0/0x14 @ 1 [ 1.428183] initcall intel_soc_pmic_i2c_driver_init+0x0/0x14 returned 0 after 16 usecs [ 1.428184] calling spi_transport_init+0x0/0x76 @ 1 [ 1.428192] initcall spi_transport_init+0x0/0x76 returned 0 after 21 usecs [ 1.428193] calling init_sd+0x0/0x173 @ 1 [ 1.428206] initcall init_sd+0x0/0x173 returned 0 after 38 usecs [ 1.428207] calling init_sr+0x0/0x43 @ 1 [ 1.428213] initcall init_sr+0x0/0x43 returned 0 after 14 usecs [ 1.428215] calling init_sg+0x0/0x122 @ 1 [ 1.428224] initcall init_sg+0x0/0x122 returned 0 after 27 usecs [ 1.428225] calling piix_init+0x0/0x29 @ 1 [ 1.428243] initcall piix_init+0x0/0x29 returned 0 after 57 usecs [ 1.428244] calling sis_pci_driver_init+0x0/0x1b @ 1 [ 1.428255] initcall sis_pci_driver_init+0x0/0x1b returned 0 after 31 usecs [ 1.428256] calling ata_generic_pci_driver_init+0x0/0x1b @ 1 [ 1.428267] initcall ata_generic_pci_driver_init+0x0/0x1b returned 0 after 31 usecs [ 1.428268] calling net_olddevs_init+0x0/0x5b @ 1 [ 1.428274] initcall net_olddevs_init+0x0/0x5b returned 0 after 10 usecs [ 1.428275] calling phy_module_init+0x0/0x19 @ 1 [ 1.428310] initcall phy_module_init+0x0/0x19 returned 0 after 127 usecs [ 1.428311] calling phy_module_init+0x0/0x19 @ 1 [ 1.428326] initcall phy_module_init+0x0/0x19 returned 0 after 46 usecs [ 1.428327] calling phy_module_init+0x0/0x19 @ 1 [ 1.428336] initcall phy_module_init+0x0/0x19 returned 0 after 23 usecs [ 1.428337] calling phy_module_init+0x0/0x19 @ 1 [ 1.428351] initcall phy_module_init+0x0/0x19 returned 0 after 42 usecs [ 1.428352] calling phy_module_init+0x0/0x19 @ 1 [ 1.428359] initcall phy_module_init+0x0/0x19 returned 0 after 16 usecs [ 1.428360] calling phy_module_init+0x0/0x19 @ 1 [ 1.428379] initcall phy_module_init+0x0/0x19 returned 0 after 63 usecs [ 1.428380] calling phy_module_init+0x0/0x19 @ 1 [ 1.428404] initcall phy_module_init+0x0/0x19 returned 0 after 80 usecs [ 1.428405] calling phy_module_init+0x0/0x19 @ 1 [ 1.428440] initcall phy_module_init+0x0/0x19 returned 0 after 127 usecs [ 1.428441] calling phy_module_init+0x0/0x19 @ 1 [ 1.428451] initcall phy_module_init+0x0/0x19 returned 0 after 25 usecs [ 1.428452] calling phy_module_init+0x0/0x19 @ 1 [ 1.428463] initcall phy_module_init+0x0/0x19 returned 0 after 33 usecs [ 1.428465] calling phy_module_init+0x0/0x19 @ 1 [ 1.428482] initcall phy_module_init+0x0/0x19 returned 0 after 58 usecs [ 1.428483] calling phy_module_init+0x0/0x19 @ 1 [ 1.428490] initcall phy_module_init+0x0/0x19 returned 0 after 15 usecs [ 1.428491] calling fixed_mdio_bus_init+0x0/0xc4 @ 1 [ 1.428517] libphy: Fixed MDIO Bus: probed [ 1.428534] initcall fixed_mdio_bus_init+0x0/0xc4 returned 0 after 154 usecs [ 1.428535] calling mdio_gpio_driver_init+0x0/0x14 @ 1 [ 1.428544] initcall mdio_gpio_driver_init+0x0/0x14 returned 0 after 23 usecs [ 1.428545] calling phy_module_init+0x0/0x19 @ 1 [ 1.428552] initcall phy_module_init+0x0/0x19 returned 0 after 16 usecs [ 1.428553] calling phy_module_init+0x0/0x19 @ 1 [ 1.428563] initcall phy_module_init+0x0/0x19 returned 0 after 28 usecs [ 1.428565] calling phy_module_init+0x0/0x19 @ 1 [ 1.428605] initcall phy_module_init+0x0/0x19 returned 0 after 146 usecs [ 1.428606] calling phy_module_init+0x0/0x19 @ 1 [ 1.428618] initcall phy_module_init+0x0/0x19 returned 0 after 37 usecs [ 1.428620] calling phy_module_init+0x0/0x19 @ 1 [ 1.428626] initcall phy_module_init+0x0/0x19 returned 0 after 16 usecs [ 1.428628] calling tun_init+0x0/0x90 @ 1 [ 1.428630] tun: Universal TUN/TAP device driver, 1.6 [ 1.428657] tun: (C) 1999-2004 Max Krasnyansky [ 1.428709] initcall tun_init+0x0/0x90 returned 0 after 309 usecs [ 1.428711] calling virtio_net_driver_init+0x0/0x12 @ 1 [ 1.428718] initcall virtio_net_driver_init+0x0/0x12 returned 0 after 18 usecs [ 1.428719] calling ppp_init+0x0/0x115 @ 1 [ 1.428721] PPP generic driver version 2.4.2 [ 1.428767] initcall ppp_init+0x0/0x115 returned 0 after 178 usecs [ 1.428769] calling netif_init+0x0/0x68 @ 1 [ 1.428773] initcall netif_init+0x0/0x68 returned -19 after 4 usecs [ 1.428774] calling cdrom_init+0x0/0x19 @ 1 [ 1.428780] initcall cdrom_init+0x0/0x19 returned 0 after 15 usecs [ 1.428781] calling dwc2_platform_driver_init+0x0/0x14 @ 1 [ 1.428790] initcall dwc2_platform_driver_init+0x0/0x14 returned 0 after 25 usecs [ 1.428791] calling dwc2_pci_driver_init+0x0/0x1b @ 1 [ 1.428801] initcall dwc2_pci_driver_init+0x0/0x1b returned 0 after 27 usecs [ 1.428802] calling ohci_hcd_mod_init+0x0/0x95 @ 1 [ 1.428804] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver [ 1.428827] initcall ohci_hcd_mod_init+0x0/0x95 returned 0 after 88 usecs [ 1.428828] calling ohci_pci_init+0x0/0x69 @ 1 [ 1.428830] ohci-pci: OHCI PCI platform driver [ 1.428851] initcall ohci_pci_init+0x0/0x69 returned 0 after 81 usecs [ 1.428852] calling ohci_platform_init+0x0/0x4c @ 1 [ 1.428854] ohci-platform: OHCI generic platform driver [ 1.428876] initcall ohci_platform_init+0x0/0x4c returned 0 after 86 usecs [ 1.428877] calling uhci_hcd_init+0x0/0x11d @ 1 [ 1.428879] uhci_hcd: USB Universal Host Controller Interface driver [ 1.428912] initcall uhci_hcd_init+0x0/0x11d returned 0 after 125 usecs [ 1.428913] calling kgdbdbgp_start_thread+0x0/0x52 @ 1 [ 1.428916] initcall kgdbdbgp_start_thread+0x0/0x52 returned 0 after 4 usecs [ 1.428917] calling i8042_init+0x0/0x413 @ 1 [ 1.428935] i8042: PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1 [ 1.428956] i8042: PNP: PS/2 appears to have AUX port disabled, if this is incorrect please boot with i8042.nopnp [ 1.429290] i8042: Warning: Keylock active [ 1.429429] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 1.429452] initcall i8042_init+0x0/0x413 returned 0 after 2107 usecs [ 1.429453] calling input_leds_init+0x0/0x12 @ 1 [ 1.429457] initcall input_leds_init+0x0/0x12 returned 0 after 6 usecs [ 1.429458] calling mousedev_init+0x0/0x85 @ 1 [ 1.429520] mousedev: PS/2 mouse device common for all mice [ 1.429541] initcall mousedev_init+0x0/0x85 returned 0 after 317 usecs [ 1.429542] calling evdev_init+0x0/0x12 @ 1 [ 1.429620] initcall evdev_init+0x0/0x12 returned 0 after 297 usecs [ 1.429621] calling atkbd_init+0x0/0x27 @ 1 [ 1.429632] initcall atkbd_init+0x0/0x27 returned 0 after 30 usecs [ 1.429633] calling uinput_init+0x0/0x12 @ 1 [ 1.429658] initcall uinput_init+0x0/0x12 returned 0 after 90 usecs [ 1.429660] calling cmos_init+0x0/0x73 @ 1 [ 1.429672] rtc_cmos 00:04: RTC can wake from S4 [ 1.429763] rtc rtc0: invalid alarm value: 16606-1--2913 127655972:-930576223:4 [ 1.429815] rtc_cmos 00:04: rtc core: registered rtc_cmos as rtc0 [ 1.429862] rtc_cmos 00:04: alarms up to one month, y3k, 242 bytes nvram, hpet irqs [ 1.429891] initcall cmos_init+0x0/0x73 returned 0 after 903 usecs [ 1.429892] calling dm_init+0x0/0x46 @ 1 [ 1.429918] device-mapper: uevent: version 1.0.3 [ 1.429976] device-mapper: ioctl: 4.34.0-ioctl (2015-10-28) initialised: dm-devel@redhat.com [ 1.430004] initcall dm_init+0x0/0x46 returned 0 after 432 usecs [ 1.430005] calling cpufreq_stats_init+0x0/0xcb @ 1 [ 1.430009] initcall cpufreq_stats_init+0x0/0xcb returned 0 after 7 usecs [ 1.430010] calling cpufreq_gov_powersave_init+0x0/0x12 @ 1 [ 1.430014] initcall cpufreq_gov_powersave_init+0x0/0x12 returned 0 after 4 usecs [ 1.430015] calling cpufreq_gov_userspace_init+0x0/0x12 @ 1 [ 1.430018] initcall cpufreq_gov_userspace_init+0x0/0x12 returned 0 after 4 usecs [ 1.430019] calling cpufreq_gov_dbs_init+0x0/0x12 @ 1 [ 1.430023] initcall cpufreq_gov_dbs_init+0x0/0x12 returned 0 after 4 usecs [ 1.430024] calling cpufreq_gov_dbs_init+0x0/0x12 @ 1 [ 1.430028] initcall cpufreq_gov_dbs_init+0x0/0x12 returned 0 after 4 usecs [ 1.430029] calling intel_pstate_init+0x0/0x4d6 @ 1 [ 1.430033] initcall intel_pstate_init+0x0/0x4d6 returned -19 after 6 usecs [ 1.430034] calling ledtrig_cpu_init+0x0/0x99 @ 1 [ 1.430039] ledtrig-cpu: registered to indicate activity on CPUs [ 1.430059] initcall ledtrig_cpu_init+0x0/0x99 returned 0 after 88 usecs [ 1.430060] calling efivars_sysfs_init+0x0/0x230 @ 1 [ 1.430062] EFI Variables Facility v0.08 2004-May-17 [ 1.433097] initcall efivars_sysfs_init+0x0/0x230 returned 0 after 12016 usecs [ 1.433100] calling esrt_sysfs_init+0x0/0x343 @ 1 [ 1.433103] initcall esrt_sysfs_init+0x0/0x343 returned -38 after 4 usecs [ 1.433104] calling gpio_clk_driver_init+0x0/0x14 @ 1 [ 1.433115] initcall gpio_clk_driver_init+0x0/0x14 returned 0 after 33 usecs [ 1.433117] calling extcon_class_init+0x0/0x17 @ 1 [ 1.433123] initcall extcon_class_init+0x0/0x17 returned 0 after 13 usecs [ 1.433124] calling powercap_init+0x0/0x289 @ 1 [ 1.433147] initcall powercap_init+0x0/0x289 returned 0 after 80 usecs [ 1.433148] calling pm_check_save_msr+0x0/0x20 @ 1 [ 1.433152] initcall pm_check_save_msr+0x0/0x20 returned 0 after 5 usecs [ 1.433154] calling sock_diag_init+0x0/0x37 @ 1 [ 1.433170] initcall sock_diag_init+0x0/0x37 returned 0 after 51 usecs [ 1.433171] calling blackhole_init+0x0/0x12 @ 1 [ 1.433177] initcall blackhole_init+0x0/0x12 returned 0 after 13 usecs [ 1.433178] calling gre_offload_init+0x0/0x47 @ 1 [ 1.433182] initcall gre_offload_init+0x0/0x47 returned 0 after 5 usecs [ 1.433183] calling sysctl_ipv4_init+0x0/0x4e @ 1 [ 1.433210] initcall sysctl_ipv4_init+0x0/0x4e returned 0 after 99 usecs [ 1.433212] calling cubictcp_register+0x0/0x59 @ 1 [ 1.433217] initcall cubictcp_register+0x0/0x59 returned 0 after 5 usecs [ 1.433218] calling inet6_init+0x0/0x323 @ 1 [ 1.433298] NET: Registered protocol family 10 [ 1.433468] initcall inet6_init+0x0/0x323 returned 0 after 975 usecs [ 1.433470] calling packet_init+0x0/0x42 @ 1 [ 1.433472] NET: Registered protocol family 17 [ 1.434414] initcall packet_init+0x0/0x42 returned 0 after 3725 usecs [ 1.434415] calling dcbnl_init+0x0/0x4d @ 1 [ 1.434419] initcall dcbnl_init+0x0/0x4d returned 0 after 5 usecs [ 1.434420] calling init_dns_resolver+0x0/0xe7 @ 1 [ 1.434427] Key type dns_resolver registered [ 1.435355] initcall init_dns_resolver+0x0/0xe7 returned 0 after 3692 usecs [ 1.435357] calling mcheck_init_device+0x0/0x17b @ 1 [ 1.435467] initcall mcheck_init_device+0x0/0x17b returned 0 after 421 usecs [ 1.435484] calling tboot_late_init+0x0/0x29b @ 1 [ 1.435488] initcall tboot_late_init+0x0/0x29b returned 0 after 4 usecs [ 1.435489] calling mcheck_late_init+0x0/0x34 @ 1 [ 1.435496] initcall mcheck_late_init+0x0/0x34 returned 0 after 15 usecs [ 1.435497] calling severities_debugfs_init+0x0/0x3d @ 1 [ 1.435501] initcall severities_debugfs_init+0x0/0x3d returned 0 after 6 usecs [ 1.435502] calling threshold_init_device+0x0/0x45 @ 1 [ 1.435506] initcall threshold_init_device+0x0/0x45 returned 0 after 6 usecs [ 1.435507] calling microcode_init+0x0/0x1b8 @ 1 [ 1.435547] microcode: CPU0 sig=0x506c9, pf=0x1, revision=0xc [ 1.436499] microcode: CPU1 sig=0x506c9, pf=0x1, revision=0xc [ 1.437432] microcode: CPU2 sig=0x506c9, pf=0x1, revision=0xc [ 1.438341] microcode: CPU3 sig=0x506c9, pf=0x1, revision=0xc [ 1.439289] microcode: Microcode Update Driver: v2.01 , Peter Oruba [ 1.440209] initcall microcode_init+0x0/0x1b8 returned 0 after 18605 usecs [ 1.440210] calling hpet_insert_resource+0x0/0x24 @ 1 [ 1.440214] initcall hpet_insert_resource+0x0/0x24 returned 0 after 7 usecs [ 1.440216] calling update_mp_table+0x0/0x43d @ 1 [ 1.440220] initcall update_mp_table+0x0/0x43d returned 0 after 4 usecs [ 1.440221] calling lapic_insert_resource+0x0/0x3f @ 1 [ 1.440225] initcall lapic_insert_resource+0x0/0x3f returned 0 after 6 usecs [ 1.440226] calling print_ICs+0x0/0x1b4 @ 1 [ 1.440230] initcall print_ICs+0x0/0x1b4 returned 0 after 5 usecs [ 1.440231] calling pat_memtype_list_init+0x0/0x35 @ 1 [ 1.440237] initcall pat_memtype_list_init+0x0/0x35 returned 0 after 11 usecs [ 1.440238] calling create_tlb_single_page_flush_ceiling+0x0/0x29 @ 1 [ 1.440242] initcall create_tlb_single_page_flush_ceiling+0x0/0x29 returned 0 after 6 usecs [ 1.440244] calling init_oops_id+0x0/0x40 @ 1 [ 1.440250] initcall init_oops_id+0x0/0x40 returned 0 after 16 usecs [ 1.440252] calling sched_init_debug+0x0/0x24 @ 1 [ 1.440258] initcall sched_init_debug+0x0/0x24 returned 0 after 14 usecs [ 1.440259] calling pm_qos_power_init+0x0/0xb7 @ 1 [ 1.440421] initcall pm_qos_power_init+0x0/0xb7 returned 0 after 630 usecs [ 1.440424] calling pm_debugfs_init+0x0/0x24 @ 1 [ 1.440428] initcall pm_debugfs_init+0x0/0x24 returned 0 after 8 usecs [ 1.440429] calling printk_late_init+0x0/0x75 @ 1 [ 1.440433] initcall printk_late_init+0x0/0x75 returned 0 after 6 usecs [ 1.440434] calling tk_debug_sleep_time_init+0x0/0x3c @ 1 [ 1.440438] initcall tk_debug_sleep_time_init+0x0/0x3c returned 0 after 6 usecs [ 1.440440] calling debugfs_kprobe_init+0x0/0xa7 @ 1 [ 1.440446] initcall debugfs_kprobe_init+0x0/0xa7 returned 0 after 10 usecs [ 1.440447] calling taskstats_init+0x0/0x6e @ 1 [ 1.440452] registered taskstats version 1 [ 1.441367] initcall taskstats_init+0x0/0x6e returned 0 after 3633 usecs [ 1.441368] calling clear_boot_tracer+0x0/0x30 @ 1 [ 1.441372] initcall clear_boot_tracer+0x0/0x30 returned 0 after 4 usecs [ 1.441373] calling kdb_ftrace_register+0x0/0x32 @ 1 [ 1.441378] initcall kdb_ftrace_register+0x0/0x32 returned 0 after 8 usecs [ 1.441379] calling load_system_certificate_list+0x0/0x101 @ 1 [ 1.441381] Loading compiled-in X.509 certificates [ 1.444257] Loaded X.509 cert 'Build time autogenerated kernel key: 38c547059ee152ccf45d61f11075146fd9508032' [ 1.445209] initcall load_system_certificate_list+0x0/0x101 returned 0 after 15149 usecs [ 1.445211] calling fault_around_debugfs+0x0/0x35 @ 1 [ 1.445217] initcall fault_around_debugfs+0x0/0x35 returned 0 after 14 usecs [ 1.445218] calling max_swapfiles_check+0x0/0x8 @ 1 [ 1.445222] initcall max_swapfiles_check+0x0/0x8 returned 0 after 4 usecs [ 1.445223] calling split_huge_pages_debugfs+0x0/0x35 @ 1 [ 1.445227] initcall split_huge_pages_debugfs+0x0/0x35 returned 0 after 6 usecs [ 1.445228] calling check_early_ioremap_leak+0x0/0x42 @ 1 [ 1.445233] initcall check_early_ioremap_leak+0x0/0x42 returned 0 after 8 usecs [ 1.445234] calling init_root_keyring+0x0/0xb @ 1 [ 1.445244] initcall init_root_keyring+0x0/0xb returned 0 after 27 usecs [ 1.445245] calling big_key_crypto_init+0x0/0xa1 @ 1 [ 1.446493] initcall big_key_crypto_init+0x0/0xa1 returned -14 after 4925 usecs [ 1.446496] calling init_trusted+0x0/0xba @ 1 [ 1.447919] Key type trusted registered [ 1.448879] initcall init_trusted+0x0/0xba returned 0 after 9420 usecs [ 1.448881] calling init_encrypted+0x0/0x11b @ 1 [ 1.451533] Key type encrypted registered [ 1.452478] initcall init_encrypted+0x0/0x11b returned 0 after 14227 usecs [ 1.452480] calling init_profile_hash+0x0/0x7d @ 1 [ 1.452482] AppArmor: AppArmor sha1 policy hashing enabled [ 1.453444] initcall init_profile_hash+0x0/0x7d returned 0 after 3808 usecs [ 1.453446] calling init_ima+0x0/0x31 @ 1 [ 1.453448] ima: No TPM chip found, activating TPM-bypass! [ 1.454414] initcall init_ima+0x0/0x31 returned 0 after 3822 usecs [ 1.454415] calling init_evm+0x0/0x55 @ 1 [ 1.454417] evm: HMAC attrs: 0x1 [ 1.455383] initcall init_evm+0x0/0x55 returned 0 after 3819 usecs [ 1.455384] calling prandom_reseed+0x0/0x40 @ 1 [ 1.455402] initcall prandom_reseed+0x0/0x40 returned 0 after 61 usecs [ 1.455403] calling pci_resource_alignment_sysfs_init+0x0/0x22 @ 1 [ 1.455410] initcall pci_resource_alignment_sysfs_init+0x0/0x22 returned 0 after 15 usecs [ 1.455411] calling pci_sysfs_init+0x0/0x49 @ 1 [ 1.455721] initcall pci_sysfs_init+0x0/0x49 returned 0 after 1215 usecs [ 1.455723] calling boot_wait_for_devices+0x0/0x29 @ 1 [ 1.455727] initcall boot_wait_for_devices+0x0/0x29 returned -19 after 4 usecs [ 1.455728] calling dmar_free_unused_resources+0x0/0xb5 @ 1 [ 1.455732] initcall dmar_free_unused_resources+0x0/0xb5 returned 0 after 5 usecs [ 1.455734] calling deferred_probe_initcall+0x0/0x70 @ 1 [ 1.455819] initcall deferred_probe_initcall+0x0/0x70 returned 0 after 323 usecs [ 1.455821] calling late_resume_init+0x0/0x1a0 @ 1 [ 1.455823] Magic number: 6:809:49 [ 1.456822] initcall late_resume_init+0x0/0x1a0 returned 0 after 3952 usecs [ 1.456823] calling rtc_hctosys+0x0/0xe7 @ 1 [ 1.456853] rtc_cmos 00:04: setting system clock to 16598-01-07 23:01:25 UTC (461615756485) [ 1.457834] initcall rtc_hctosys+0x0/0xe7 returned -22 after 3993 usecs [ 1.457836] calling charger_manager_init+0x0/0x9b @ 1 [ 1.457903] initcall charger_manager_init+0x0/0x9b returned 0 after 251 usecs [ 1.457905] calling acpi_cpufreq_init+0x0/0x27d @ 1 [ 1.458291] initcall acpi_cpufreq_init+0x0/0x27d returned 0 after 1519 usecs [ 1.458294] calling powernowk8_init+0x0/0x180 @ 1 [ 1.458308] initcall powernowk8_init+0x0/0x180 returned -19 after 5 usecs [ 1.458309] calling pcc_cpufreq_init+0x0/0x4b3 @ 1 [ 1.458315] initcall pcc_cpufreq_init+0x0/0x4b3 returned -19 after 13 usecs [ 1.458316] calling centrino_init+0x0/0x2a @ 1 [ 1.458319] initcall centrino_init+0x0/0x2a returned -19 after 4 usecs [ 1.458320] calling edd_init+0x0/0x2e5 @ 1 [ 1.458322] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found [ 1.459303] EDD information not available. [ 1.460280] initcall edd_init+0x0/0x2e5 returned -19 after 7748 usecs [ 1.460281] calling firmware_memmap_init+0x0/0x33 @ 1 [ 1.460315] initcall firmware_memmap_init+0x0/0x33 returned 0 after 122 usecs [ 1.460316] calling efi_shutdown_init+0x0/0x33 @ 1 [ 1.460320] initcall efi_shutdown_init+0x0/0x33 returned 0 after 5 usecs [ 1.460321] calling clk_debug_init+0x0/0x137 @ 1 [ 1.460330] initcall clk_debug_init+0x0/0x137 returned 0 after 25 usecs [ 1.460331] calling pci_mmcfg_late_insert_resources+0x0/0x4b @ 1 [ 1.460336] initcall pci_mmcfg_late_insert_resources+0x0/0x4b returned 0 after 7 usecs [ 1.460337] calling register_sk_filter_ops+0x0/0x8 @ 1 [ 1.460341] initcall register_sk_filter_ops+0x0/0x8 returned 0 after 4 usecs [ 1.460342] calling tcp_congestion_default+0x0/0x12 @ 1 [ 1.460346] initcall tcp_congestion_default+0x0/0x12 returned 0 after 6 usecs [ 1.460347] calling ip_auto_config+0x0/0xee4 @ 1 [ 1.460352] initcall ip_auto_config+0x0/0xee4 returned 0 after 10 usecs [ 1.460354] calling software_resume+0x0/0x370 @ 1 [ 1.460356] PM: Hibernation image not present or could not be loaded. [ 1.460359] initcall software_resume+0x0/0x370 returned -2 after 9 usecs [ 1.460360] calling regulator_init_complete+0x0/0x1f @ 1 [ 1.460364] initcall regulator_init_complete+0x0/0x1f returned 0 after 7 usecs [ 1.460366] calling clk_disable_unused+0x0/0x100 @ 1 [ 1.460370] initcall clk_disable_unused+0x0/0x100 returned 0 after 6 usecs [ 1.460371] calling init_default_flow_dissectors+0x0/0x38 @ 1 [ 1.460375] initcall init_default_flow_dissectors+0x0/0x38 returned 0 after 6 usecs [ 1.461055] Freeing unused kernel memory: 1508K (ffffffff81d49000 - ffffffff81ec2000) [ 1.462049] Write protecting the kernel read-only data: 12288k [ 1.463225] Freeing unused kernel memory: 348K (ffff8800017a9000 - ffff880001800000) [ 1.464972] Freeing unused kernel memory: 476K (ffff880001b89000 - ffff880001c00000) [ 1.476854] random: systemd-udevd urandom read with 5 bits of entropy available [ 1.486116] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0 [ 1.509205] calling acpi_video_init+0x0/0x1000 [video] @ 154 [ 1.509215] initcall acpi_video_init+0x0/0x1000 [video] returned 0 after 22 usecs [ 1.519674] calling hid_init+0x0/0x65 [hid] @ 163 [ 1.519686] hidraw: raw HID events driver (C) Jiri Kosina [ 1.520717] initcall hid_init+0x0/0x65 [hid] returned 0 after 4103 usecs [ 1.521613] calling i2c_hid_driver_init+0x0/0x1000 [i2c_hid] @ 163 [ 1.521627] initcall i2c_hid_driver_init+0x0/0x1000 [i2c_hid] returned 0 after 38 usecs [ 1.526636] calling ahci_pci_driver_init+0x0/0x1000 [ahci] @ 165 [ 1.526651] ahci 0000:00:12.0: version 3.0 [ 1.529103] calling xhci_hcd_init+0x0/0x15 [xhci_hcd] @ 153 [ 1.529111] initcall xhci_hcd_init+0x0/0x15 [xhci_hcd] returned 0 after 5 usecs [ 1.529495] calling sdhci_drv_init+0x0/0x1000 [sdhci] @ 150 [ 1.529497] sdhci: Secure Digital Host Controller Interface driver [ 1.530515] sdhci: Copyright(c) Pierre Ossman [ 1.531501] initcall sdhci_drv_init+0x0/0x1000 [sdhci] returned 0 after 7926 usecs [ 1.531532] calling xhci_pci_init+0x0/0x1000 [xhci_pci] @ 153 [ 1.531989] calling drm_core_init+0x0/0xf3 [drm] @ 160 [ 1.532156] ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl SATA mode [ 1.532179] [drm] Initialized drm 1.1.0 20060810 [ 1.532193] initcall drm_core_init+0x0/0xf3 [drm] returned 0 after 749 usecs [ 1.534132] ahci 0000:00:12.0: flags: 64bit ncq sntf pm clo only pmp pio slum part deso sadm sds apst [ 1.535263] calling sdhci_driver_init+0x0/0x1000 [sdhci_pci] @ 159 [ 1.535695] scsi host0: ahci [ 1.537083] ata1: SATA max UDMA/133 abar m2048@0x92240000 port 0x92240100 irq 123 [ 1.538379] initcall ahci_pci_driver_init+0x0/0x1000 [ahci] returned 0 after 46478 usecs [ 1.538810] xhci_hcd 0000:00:15.0: xHCI Host Controller [ 1.539816] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 1 [ 1.541866] xhci_hcd 0000:00:15.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00009810 [ 1.542880] xhci_hcd 0000:00:15.0: cache line size of 64 is not supported [ 1.542935] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 [ 1.543972] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 1.545014] usb usb1: Product: xHCI Host Controller [ 1.545066] calling drm_kms_helper_init+0x0/0x14 [drm_kms_helper] @ 160 [ 1.545074] initcall drm_kms_helper_init+0x0/0x14 [drm_kms_helper] returned 0 after 4 usecs [ 1.546034] usb usb1: Manufacturer: Linux 4.7.0-rc4-nightly+ xhci-hcd [ 1.547039] usb usb1: SerialNumber: 0000:00:15.0 [ 1.548174] hub 1-0:1.0: USB hub found [ 1.549232] hub 1-0:1.0: 8 ports detected [ 1.550256] atkbd serio0: Failed to enable keyboard on isa0060/serio0 [ 1.551314] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3 [ 1.552912] xhci_hcd 0000:00:15.0: xHCI Host Controller [ 1.553951] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 2 [ 1.555012] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003 [ 1.556063] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 1.557105] usb usb2: Product: xHCI Host Controller [ 1.558185] usb usb2: Manufacturer: Linux 4.7.0-rc4-nightly+ xhci-hcd [ 1.559254] usb usb2: SerialNumber: 0000:00:15.0 [ 1.560408] hub 2-0:1.0: USB hub found [ 1.561490] hub 2-0:1.0: 7 ports detected [ 1.561728] calling i915_init+0x0/0x9b [i915] @ 160 [ 1.562945] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev a) [ 1.564039] sdhci-pci 0000:00:1b.0: failed to setup card detect gpio [ 1.565097] initcall xhci_pci_init+0x0/0x1000 [xhci_pci] returned 0 after 132901 usecs [ 1.569156] mmc0: SDHCI controller on PCI [0000:00:1b.0] using ADMA 64-bit [ 1.570186] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev a) [ 1.575348] mmc1: SDHCI controller on PCI [0000:00:1c.0] using ADMA 64-bit [ 1.576371] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev a) [ 1.581518] mmc2: SDHCI controller on PCI [0000:00:1e.0] using ADMA 64-bit [ 1.582684] initcall sdhci_driver_init+0x0/0x1000 [sdhci_pci] returned 0 after 187769 usecs [ 1.582927] [drm:intel_detect_pch] No PCH found. [ 1.582930] [drm:get_allowed_dc_mask] Allowed DC state mask 09 [ 1.582939] [drm:i915_dump_device_info] i915 device info: gen=9, pciid=0x5a84 rev=0x0a flags=need_gfx_hws,is_broxton,is_preliminary,has_fbc,has_hotplug,has_ddi,has_fpga_dbg, [ 1.583016] [drm:intel_device_info_runtime_init] slice total: 1 [ 1.583017] [drm:intel_device_info_runtime_init] subslice total: 3 [ 1.583017] [drm:intel_device_info_runtime_init] subslice per slice: 3 [ 1.583018] [drm:intel_device_info_runtime_init] EU total: 18 [ 1.583019] [drm:intel_device_info_runtime_init] EU per subslice: 6 [ 1.583020] [drm:intel_device_info_runtime_init] Has Pooled EU: y [ 1.583020] [drm:intel_device_info_runtime_init] Min EU in pool: 9 [ 1.583021] [drm:intel_device_info_runtime_init] has slice power gating: n [ 1.583022] [drm:intel_device_info_runtime_init] has subslice power gating: y [ 1.583022] [drm:intel_device_info_runtime_init] has EU power gating: y [ 1.583023] [drm:intel_device_info_runtime_init] ppgtt mode: 3 [ 1.583044] [drm:i915_gem_init_stolen] Memory reserved for graphics device: 65536K, usable: 64512K [ 1.583045] [drm] Memory usable by graphics device = 4096M [ 1.584067] [drm:i915_ggtt_init_hw] GMADR size = 256M [ 1.584067] [drm:i915_ggtt_init_hw] GTT stolen size = 64M [ 1.584099] checking generic (80000000 7e9000) vs hw (80000000 10000000) [ 1.584100] fb: switching to inteldrmfb from EFI VGA [ 1.585123] Console: switching to colour dummy device 80x25 [ 1.585162] [drm] Replacing VGA console driver [ 1.585250] [drm:intel_opregion_setup] graphic opregion physical addr: 0x79df2018 [ 1.585254] [drm:intel_opregion_setup] Public ACPI methods supported [ 1.585254] [drm:intel_opregion_setup] ASLE supported [ 1.585257] [drm:intel_opregion_setup] Found valid VBT in ACPI OpRegion (RVDA) [ 1.585279] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 1.585281] [drm] Driver supports precise vblank timestamp query. [ 1.585284] [drm:init_vbt_defaults] Set default to SSC at 100000 kHz [ 1.585285] [drm:intel_bios_init] VBT signature "$VBT BROXTON ", BDB version 207 [ 1.585286] [drm:parse_general_features] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0 [ 1.585287] [drm:parse_general_definitions] crt_ddc_bus_pin: 2 [ 1.585288] [drm:intel_opregion_get_panel_type] Failed to get panel details from OpRegion (-19) [ 1.585289] [drm:parse_lfp_panel_data] Panel type: 2 (VBT) [ 1.585290] [drm:parse_lfp_panel_data] DRRS supported mode is seamless [ 1.585291] [drm:parse_lfp_panel_data] Found panel mode in BIOS VBT tables: [ 1.585293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa [ 1.585294] [drm:parse_lfp_panel_data] VBT initial LVDS value 300 [ 1.585295] [drm:parse_lfp_backlight] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 180 [ 1.585296] [drm:parse_sdvo_device_mapping] Unsupported child device size for SDVO mapping. [ 1.585297] [drm:parse_device_mapping] Expected child device config size for VBT version 207 not known; assuming 38 [ 1.585298] [drm:parse_driver_features] DRRS State Enabled:1 [ 1.585300] [drm:parse_ddi_port] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0 [ 1.585301] [drm:parse_ddi_port] VBT HDMI level shift for port A: 0 [ 1.585302] [drm:parse_ddi_port] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0 [ 1.585303] [drm:parse_ddi_port] VBT HDMI level shift for port B: 8 [ 1.585304] [drm:parse_ddi_port] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0 [ 1.585304] [drm:parse_ddi_port] VBT HDMI level shift for port C: 8 [ 1.585327] [drm:intel_dsm_pci_probe] no _DSM method for intel device [ 1.585331] [drm:gen9_set_dc_state] Setting DC state from 00 to 00 [ 1.585334] [drm:intel_power_well_enable] enabling power well 1 [ 1.585337] [drm:intel_update_cdclk] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz [ 1.585348] [drm:intel_power_well_enable] enabling always-on [ 1.585349] [drm:intel_power_well_enable] enabling DC off [ 1.585350] [drm:gen9_set_dc_state] Setting DC state from 00 to 00 [ 1.585352] [drm:intel_power_well_enable] enabling power well 2 [ 1.585353] [drm:intel_power_well_enable] enabling dpio-common-a [ 1.586587] [drm:intel_power_well_enable] enabling dpio-common-bc [ 1.586597] [drm:bxt_ddi_phy_init] DDI PHY 0 already enabled, won't reprogram it [ 1.586599] [drm:gen9_set_dc_state] Setting DC state from 00 to 00 [ 1.586615] [drm:bxt_ddi_phy_init] DDI PHY 1 already enabled, won't reprogram it [ 1.586625] [drm:bxt_ddi_phy_init] DDI PHY 0 already enabled, won't reprogram it [ 1.586628] [drm:intel_csr_ucode_init] Loading i915/bxt_dmc_ver1.bin [ 1.586782] [drm:intel_fbc_init] Sanitized enable_fbc value: 0 [ 1.586892] [drm] Finished loading i915/bxt_dmc_ver1.bin (v1.7) [ 1.590434] [drm:intel_print_wm_latency] Gen9 Plane WM0 latency 9 (9.0 usec) [ 1.590436] [drm:intel_print_wm_latency] Gen9 Plane WM1 latency 9 (9.0 usec) [ 1.590437] [drm:intel_print_wm_latency] Gen9 Plane WM2 latency 10 (10.0 usec) [ 1.590438] [drm:intel_print_wm_latency] Gen9 Plane WM3 latency 24 (24.0 usec) [ 1.590439] [drm:intel_print_wm_latency] Gen9 Plane WM4 latency 24 (24.0 usec) [ 1.590440] [drm:intel_print_wm_latency] Gen9 Plane WM5 latency 24 (24.0 usec) [ 1.590441] [drm:intel_print_wm_latency] Gen9 Plane WM6 latency 24 (24.0 usec) [ 1.590442] [drm:intel_print_wm_latency] Gen9 Plane WM7 latency 24 (24.0 usec) [ 1.590443] [drm:intel_modeset_init] 3 display pipes available. [ 1.590460] [drm:intel_update_cdclk] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz [ 1.590461] [drm:intel_update_max_cdclk] Max CD clock rate: 624000 kHz [ 1.590462] [drm:intel_update_max_cdclk] Max dotclock rate: 624000 kHz [ 1.590464] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem [ 1.590770] [drm:intel_ddi_init] BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing [ 1.590772] [drm:intel_dp_init_connector] Adding eDP connector on port A [ 1.590811] [drm:intel_dp_aux_init] registering DPDDC-A bus for card0-eDP-1 [ 1.590835] [drm:intel_pps_dump_state] cur t1_t3 0 t8 0 t9 0 t10 500 t11_t12 5000 [ 1.590836] [drm:intel_pps_dump_state] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000 [ 1.590837] [drm:intel_dp_init_panel_power_sequencer] panel power up delay 200, power down delay 50, power cycle delay 500 [ 1.590838] [drm:intel_dp_init_panel_power_sequencer] backlight on delay 1, off delay 200 [ 1.590839] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60 [ 1.590840] [drm:intel_edp_panel_vdd_sanitize] VDD left on by BIOS, adjusting state tracking [ 1.592591] [drm:intel_dp_get_dpcd] DPCD: 11 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00 [ 1.594710] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel. [ 1.594787] [drm:intel_dp_get_dpcd] EDP DPCD : 02 fb c7 [ 1.594788] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no [ 1.594790] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 [ 1.594791] [drm:intel_dp_print_rates] sink rates: 162000, 270000 [ 1.594792] [drm:intel_dp_print_rates] common rates: 162000, 270000 [ 1.595621] [drm:drm_edid_to_eld] ELD: no CEA Extension found [ 1.595623] [drm:intel_dp_drrs_init] Downclock mode is not found. DRRS not supported [ 1.595624] [drm:get_backlight_max_vbt] VBT defined backlight frequency 200 Hz [ 1.595626] [drm:intel_panel_setup_backlight] Connector eDP-1 backlight initialized, disabled, brightness 0/96000 [ 1.595639] [drm:intel_dp_init_connector] Adding DP connector on port B [ 1.595673] [drm:intel_dp_aux_init] registering DPDDC-B bus for card0-DP-1 [ 1.595696] [drm:intel_hdmi_init_connector] Adding HDMI connector on port B [ 1.595719] [drm:intel_dp_init_connector] Adding DP connector on port C [ 1.595737] [drm:intel_dp_aux_init] registering DPDDC-C bus for card0-DP-2 [ 1.595755] [drm:intel_hdmi_init_connector] Adding HDMI connector on port C [ 1.595772] [drm:intel_dsi_init] [ 1.595784] [drm:intel_modeset_readout_hw_state] [CRTC:26:pipe A] hw state readout: enabled [ 1.595786] [drm:intel_modeset_readout_hw_state] [CRTC:31:pipe B] hw state readout: disabled [ 1.595788] [drm:intel_modeset_readout_hw_state] [CRTC:36:pipe C] hw state readout: disabled [ 1.595789] [drm:intel_modeset_readout_hw_state] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0 [ 1.595794] [drm:intel_modeset_readout_hw_state] PORT PLL B hw state readout: crtc_mask 0x00000001, on 1 [ 1.595796] [drm:intel_modeset_readout_hw_state] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0 [ 1.595797] [drm:intel_modeset_readout_hw_state] [ENCODER:38:DDI A] hw state readout: disabled, pipe A [ 1.595802] [drm:intel_modeset_readout_hw_state] [ENCODER:46:DDI B] hw state readout: enabled, pipe A [ 1.595803] [drm:intel_modeset_readout_hw_state] [ENCODER:48:DP-MST A] hw state readout: disabled, pipe A [ 1.595804] [drm:intel_modeset_readout_hw_state] [ENCODER:49:DP-MST B] hw state readout: disabled, pipe B [ 1.595805] [drm:intel_modeset_readout_hw_state] [ENCODER:50:DP-MST C] hw state readout: disabled, pipe C [ 1.595806] [drm:intel_modeset_readout_hw_state] [ENCODER:53:DDI C] hw state readout: disabled, pipe A [ 1.595807] [drm:intel_modeset_readout_hw_state] [ENCODER:55:DP-MST A] hw state readout: disabled, pipe A [ 1.595808] [drm:intel_modeset_readout_hw_state] [ENCODER:56:DP-MST B] hw state readout: disabled, pipe B [ 1.595809] [drm:intel_modeset_readout_hw_state] [ENCODER:57:DP-MST C] hw state readout: disabled, pipe C [ 1.595810] [drm:intel_modeset_readout_hw_state] [CONNECTOR:39:eDP-1] hw state readout: disabled [ 1.595812] [drm:intel_modeset_readout_hw_state] [CONNECTOR:47:DP-1] hw state readout: enabled [ 1.595813] [drm:intel_modeset_readout_hw_state] [CONNECTOR:51:HDMI-A-1] hw state readout: disabled [ 1.595814] [drm:intel_modeset_readout_hw_state] [CONNECTOR:54:DP-2] hw state readout: disabled [ 1.595816] [drm:intel_modeset_readout_hw_state] [CONNECTOR:58:HDMI-A-2] hw state readout: disabled [ 1.595826] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][setup_hw_state] config ffff88026f60f000 for pipe A [ 1.595827] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 1.595828] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 1.595829] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 1.595830] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 1730150, gmch_n: 8388608, link_m: 144179, link_n: 524288, tu: 64 [ 1.595831] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 1.595832] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 1.595833] [drm:intel_dump_pipe_config] requested mode: [ 1.595834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148499 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 1.595835] [drm:intel_dump_pipe_config] adjusted mode: [ 1.595837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148499 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 1.595838] [drm:intel_dump_crtc_timings] crtc timings: 148499 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5 [ 1.595839] [drm:intel_dump_pipe_config] port clock: 540000 [ 1.595839] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 1.595840] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0 [ 1.595841] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 1.595842] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x07800438, enabled [ 1.595843] [drm:intel_dump_pipe_config] ips: 0 [ 1.595844] [drm:intel_dump_pipe_config] double wide: 0 [ 1.595845] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58 [ 1.595846] [drm:intel_dump_pipe_config] planes on this crtc [ 1.595847] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 1.595848] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 1.595849] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 1.595850] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 1.595851] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][setup_hw_state] config ffff88026f60c000 for pipe B [ 1.595852] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 1.595852] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0 [ 1.595853] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 1.595854] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 1.595856] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 1.595856] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 1.595857] [drm:intel_dump_pipe_config] requested mode: [ 1.595858] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [ 1.595859] [drm:intel_dump_pipe_config] adjusted mode: [ 1.595860] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [ 1.595861] [drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 [ 1.595862] [drm:intel_dump_pipe_config] port clock: 0 [ 1.595863] [drm:intel_dump_pipe_config] pipe src size: 0x0 [ 1.595864] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 [ 1.595865] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 1.595865] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 1.595866] [drm:intel_dump_pipe_config] ips: 0 [ 1.595867] [drm:intel_dump_pipe_config] double wide: 0 [ 1.595868] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 [ 1.595869] [drm:intel_dump_pipe_config] planes on this crtc [ 1.595870] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 1.595871] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 1.595871] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 1.595872] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 1.595874] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][setup_hw_state] config ffff88026f007800 for pipe C [ 1.595874] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 1.595875] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0 [ 1.595876] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 1.595877] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 1.595878] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 1.595879] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 1.595880] [drm:intel_dump_pipe_config] requested mode: [ 1.595881] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [ 1.595882] [drm:intel_dump_pipe_config] adjusted mode: [ 1.595883] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [ 1.595884] [drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 [ 1.595885] [drm:intel_dump_pipe_config] port clock: 0 [ 1.595885] [drm:intel_dump_pipe_config] pipe src size: 0x0 [ 1.595886] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: 0 [ 1.595887] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 1.595888] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 1.595889] [drm:intel_dump_pipe_config] ips: 0 [ 1.595889] [drm:intel_dump_pipe_config] double wide: 0 [ 1.595891] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 [ 1.595891] [drm:intel_dump_pipe_config] planes on this crtc [ 1.595892] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 1.595893] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 1.595894] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 1.595910] [drm:skylake_get_initial_plane_config] pipe A with fb: size=1920x1080@32, offset=0, pitch 7680, size 0x7e9000 [ 1.595911] [drm:i915_gem_object_create_stolen_for_preallocated] creating preallocated stolen object: stolen_offset=0, gtt_offset=0, size=7e9000 [ 1.595914] [drm:i915_pages_create_for_stolen] offset=0x0, size=8294400 [ 1.595916] [drm:intel_alloc_initial_plane_obj] initial plane fb obj ffff88026f59c000 [ 1.595917] [drm:intel_guc_init] GuC firmware pending, path i915/bxt_guc_ver8_7.bin [ 1.595918] [drm:guc_fw_fetch] before requesting firmware: GuC fw fetch status PENDING [ 1.595951] [drm:guc_fw_fetch] fetch GuC fw from i915/bxt_guc_ver8_7.bin succeeded, fw ffff880275243aa0 [ 1.595953] [drm:guc_fw_fetch] firmware version 8.7 OK (minimum 8.7) [ 1.595989] [drm:guc_fw_fetch] GuC fw fetch status SUCCESS, obj ffff88026f59c240 [ 1.596062] [drm:i915_gem_setup_global_gtt] reserving preallocated space: 0 + 7e9000 [ 1.596063] [drm:i915_gem_setup_global_gtt] clearing unused GTT space: [7e9000, fffff000] [ 1.596085] [drm:i915_gem_context_init] LR context support initialized [ 1.596092] [drm:intel_init_pipe_control] render ring pipe control offset: 0x007ea000 [ 1.596097] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 1.596098] [drm:i915_pages_create_for_stolen] offset=0x7e9000, size=16384 [ 1.596120] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 1.596121] [drm:i915_pages_create_for_stolen] offset=0x7ed000, size=16384 [ 1.596130] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 1.596131] [drm:i915_pages_create_for_stolen] offset=0x7f1000, size=16384 [ 1.596138] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 1.596139] [drm:i915_pages_create_for_stolen] offset=0x7f5000, size=16384 [ 1.596147] [drm:gen8_init_common_ring] Execlists enabled for render ring [ 1.596168] [drm:gen8_init_common_ring] Execlists enabled for blitter ring [ 1.596186] [drm:gen8_init_common_ring] Execlists enabled for bsd ring [ 1.596205] [drm:gen8_init_common_ring] Execlists enabled for video enhancement ring [ 1.596223] [drm:intel_guc_setup] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch SUCCESS, load NONE [ 1.596224] [drm:intel_guc_setup] GuC fw status: fetch SUCCESS, load PENDING [ 1.598206] [drm:guc_ucode_xfer_dma] DMA status 0x10, GuC status 0x8002f0ec [ 1.598208] [drm:guc_ucode_xfer_dma] returning 0 [ 1.598209] [drm:intel_guc_setup] GuC fw status: fetch SUCCESS, load SUCCESS [ 1.598219] [drm:select_doorbell_register] assigned normal priority doorbell id 0x0 [ 1.598220] [drm:select_doorbell_cacheline] selected doorbell cacheline 0x0, next 0x40, linesize 64 [ 1.598231] [drm:guc_client_alloc] new priority 2 client ffff880275346b80: ctx_index 0 [ 1.598231] [drm:guc_client_alloc] doorbell id 0, cacheline offset 0x0 [ 1.601201] [drm:intel_update_cdclk] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz [ 1.601229] [drm:intel_backlight_device_register] Connector eDP-1 backlight sysfs interface registered [ 1.601231] [drm:intel_fbdev_init_bios] found possible fb from plane A [ 1.601232] [drm:intel_fbdev_init_bios] pipe B not active or no fb, skipping [ 1.601233] [drm:intel_fbdev_init_bios] pipe C not active or no fb, skipping [ 1.601233] [drm:intel_fbdev_init_bios] checking plane A for BIOS fb [ 1.601235] [drm:intel_fbdev_init_bios] pipe A area: 1920x1080, bpp: 32, size: 8294400 [ 1.601236] [drm:intel_fbdev_init_bios] fb big enough for plane A (8294400 >= 8294400) [ 1.601237] [drm:intel_fbdev_init_bios] pipe B not active, skipping [ 1.601237] [drm:intel_fbdev_init_bios] pipe C not active, skipping [ 1.601238] [drm:intel_fbdev_init_bios] using BIOS fb for initial console [ 1.601241] [drm:bxt_hpd_irq_setup] Invert bit setting: hp_ctl:18001818 hp_port:38 [ 1.601481] [drm:intel_didl_outputs] More than 15 outputs detected via ACPI [ 1.610686] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) [ 1.610856] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input4 [ 1.610937] [drm] Initialized i915 1.6.0 20160620 for 0000:00:02.0 on minor 0 [ 1.610942] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1] [ 1.610944] [drm:intel_dp_detect] [CONNECTOR:39:eDP-1] [ 1.610982] initcall i915_init+0x0/0x9b [i915] returned 0 after 194964 usecs [ 1.613681] [drm:intel_dp_probe_oui] Sink OUI: 001cf8 [ 1.617663] [drm:intel_dp_probe_oui] Branch OUI: 000000 [ 1.623641] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1] status updated from unknown to connected [ 1.623650] [drm:drm_edid_to_eld] ELD: no CEA Extension found [ 1.623652] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1] probed modes : [ 1.623654] [drm:drm_mode_debug_printmodeline] Modeline 40:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 1.623655] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] [ 1.623656] [drm:intel_dp_detect] [CONNECTOR:47:DP-1] [ 1.627624] [drm:intel_dp_get_dpcd] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00 [ 1.631609] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink yes [ 1.631611] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 [ 1.631612] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000 [ 1.631613] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000 [ 1.632743] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x3ff8a2d9011, max_idle_ns: 440795372089 ns [ 1.635747] [drm:intel_dp_probe_mst] Sink is not MST capable [ 1.636591] usb 1-2: new high-speed USB device number 2 using xhci_hcd [ 1.637764] [drm:drm_dp_i2c_do_msg] native defer [ 1.638548] [drm:drm_dp_i2c_do_msg] native defer [ 1.641013] [drm:drm_dp_i2c_do_msg] native defer [ 1.641802] [drm:drm_dp_i2c_do_msg] native defer [ 1.642588] [drm:drm_dp_i2c_do_msg] native defer [ 1.643385] [drm:drm_dp_i2c_do_msg] native defer [ 1.644160] [drm:drm_dp_i2c_do_msg] native defer [ 1.644924] [drm:drm_dp_i2c_do_msg] native defer [ 1.645694] [drm:drm_dp_i2c_do_msg] native defer [ 1.646489] [drm:drm_dp_i2c_do_msg] native defer [ 1.647287] [drm:drm_dp_i2c_do_msg] native defer [ 1.648085] [drm:drm_dp_i2c_do_msg] native defer [ 1.648864] [drm:drm_dp_i2c_do_msg] native defer [ 1.649650] [drm:drm_dp_i2c_do_msg] native defer [ 1.650432] [drm:drm_dp_i2c_do_msg] native defer [ 1.651223] [drm:drm_dp_i2c_do_msg] native defer [ 1.652006] [drm:drm_dp_i2c_do_msg] native defer [ 1.652754] [drm:drm_dp_i2c_do_msg] native defer [ 1.653526] [drm:drm_dp_i2c_do_msg] native defer [ 1.654294] [drm:drm_dp_i2c_do_msg] native defer [ 1.655064] [drm:drm_dp_i2c_do_msg] native defer [ 1.655857] [drm:drm_dp_i2c_do_msg] native defer [ 1.656656] [drm:drm_dp_i2c_do_msg] native defer [ 1.657447] [drm:drm_dp_i2c_do_msg] native defer [ 1.658066] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) [ 1.658240] [drm:drm_dp_i2c_do_msg] native defer [ 1.659026] [drm:drm_dp_i2c_do_msg] native defer [ 1.661168] [drm:drm_dp_i2c_do_msg] native defer [ 1.663221] mmc1: new HS400 MMC card at address 0001 [ 1.663268] [drm:drm_dp_i2c_do_msg] native defer [ 1.663556] ata1.00: ATA-9: INTEL SSDSC2BW080A4, LAFi, max UDMA/133 [ 1.663561] ata1.00: 156301488 sectors, multi 16: LBA48 NCQ (depth 31/32), AA [ 1.664581] calling mmc_blk_init+0x0/0x1000 [mmc_block] @ 151 [ 1.664707] mmcblk1: mmc1:0001 CGND3R 58.2 GiB [ 1.664772] mmcblk1boot0: mmc1:0001 CGND3R partition 1 4.00 MiB [ 1.664817] mmcblk1boot1: mmc1:0001 CGND3R partition 2 4.00 MiB [ 1.664870] [drm:drm_dp_i2c_do_msg] native defer [ 1.664872] mmcblk1rpmb: mmc1:0001 CGND3R partition 3 4.00 MiB [ 1.665471] mmcblk1: p1 p2 p3 p4 [ 1.665840] initcall mmc_blk_init+0x0/0x1000 [mmc_block] returned 0 after 4964 usecs [ 1.666524] [drm:drm_detect_monitor_audio] Monitor has basic audio support [ 1.666653] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] status updated from unknown to connected [ 1.666692] [drm:drm_edid_to_eld] ELD monitor ASUS PB238 [ 1.666693] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0 [ 1.666694] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 [ 1.666708] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] probed modes : [ 1.666710] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 1.666711] [drm:drm_mode_debug_printmodeline] Modeline 100:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 1.666713] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.666714] [drm:drm_mode_debug_printmodeline] Modeline 108:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.666716] [drm:drm_mode_debug_printmodeline] Modeline 98:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 1.666717] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 1.666719] [drm:drm_mode_debug_printmodeline] Modeline 67:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 [ 1.666720] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.666722] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.666723] [drm:drm_mode_debug_printmodeline] Modeline 68:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 [ 1.666725] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 [ 1.666726] [drm:drm_mode_debug_printmodeline] Modeline 71:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 1.666728] [drm:drm_mode_debug_printmodeline] Modeline 64:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.666729] [drm:drm_mode_debug_printmodeline] Modeline 102:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.666731] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 1.666732] [drm:drm_mode_debug_printmodeline] Modeline 96:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa [ 1.666734] [drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 1.666735] [drm:drm_mode_debug_printmodeline] Modeline 80:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 1.666736] [drm:drm_mode_debug_printmodeline] Modeline 81:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 1.666738] [drm:drm_mode_debug_printmodeline] Modeline 109:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa [ 1.666739] [drm:drm_mode_debug_printmodeline] Modeline 94:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa [ 1.666741] [drm:drm_mode_debug_printmodeline] Modeline 82:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa [ 1.666742] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 1.666744] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 1.666745] [drm:drm_mode_debug_printmodeline] Modeline 72:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 1.666747] [drm:drm_mode_debug_printmodeline] Modeline 73:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 1.666748] [drm:drm_mode_debug_printmodeline] Modeline 66:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 1.666749] [drm:drm_mode_debug_printmodeline] Modeline 101:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 1.666751] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 1.666752] [drm:drm_mode_debug_printmodeline] Modeline 74:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 1.666754] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa [ 1.666755] [drm:drm_mode_debug_printmodeline] Modeline 103:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 1.666756] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.666758] [drm:drm_mode_debug_printmodeline] Modeline 77:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 1.666759] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1] [ 1.666760] [drm:intel_hdmi_detect] [CONNECTOR:51:HDMI-A-1] [ 1.666801] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 1.666804] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 1.666843] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 1.666845] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 1.666884] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 1.666885] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 1.666924] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 1.666926] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1] status updated from unknown to disconnected [ 1.666927] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1] disconnected [ 1.666928] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2] [ 1.666929] [drm:intel_dp_detect] [CONNECTOR:54:DP-2] [ 1.667037] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 01 01 00 01 01 02 00 00 00 00 00 00 [ 1.667118] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no [ 1.667120] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 [ 1.667121] [drm:intel_dp_print_rates] sink rates: 162000, 270000 [ 1.667122] [drm:intel_dp_print_rates] common rates: 162000, 270000 [ 1.672443] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2] status updated from unknown to connected [ 1.672452] [drm:drm_edid_to_eld] ELD: no CEA Extension found [ 1.672455] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2] probed modes : [ 1.672457] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 1.672458] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.672460] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.672461] [drm:drm_mode_debug_printmodeline] Modeline 87:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 1.672463] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 1.672464] [drm:drm_mode_debug_printmodeline] Modeline 104:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 1.672465] [drm:drm_mode_debug_printmodeline] Modeline 105:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 1.672467] [drm:drm_mode_debug_printmodeline] Modeline 89:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 1.672468] [drm:drm_mode_debug_printmodeline] Modeline 90:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 1.672470] [drm:drm_mode_debug_printmodeline] Modeline 91:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.672471] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 1.672473] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2] [ 1.672474] [drm:intel_hdmi_detect] [CONNECTOR:58:HDMI-A-2] [ 1.672515] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 1.672516] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 1.674518] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 1.674520] ata1.00: configured for UDMA/133 [ 1.674523] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [ 1.674587] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 1.674588] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 1.674629] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 1.674632] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2] status updated from unknown to disconnected [ 1.674633] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2] disconnected [ 1.674635] [drm:drm_setup_crtcs] [ 1.674636] [drm:drm_enable_connectors] connector 39 enabled? yes [ 1.674637] [drm:drm_enable_connectors] connector 47 enabled? yes [ 1.674638] [drm:drm_enable_connectors] connector 51 enabled? no [ 1.674638] [drm:drm_enable_connectors] connector 54 enabled? yes [ 1.674639] [drm:drm_enable_connectors] connector 58 enabled? no [ 1.674641] [drm:intel_fb_initial_config] connector eDP-1 has no encoder or crtc, skipping [ 1.674642] [drm:intel_fb_initial_config] looking for cmdline mode on connector DP-1 [ 1.674643] [drm:intel_fb_initial_config] looking for preferred mode on connector DP-1 0 [ 1.674644] [drm:intel_fb_initial_config] connector DP-1 on [CRTC:26:pipe A]: 1920x1080 [ 1.674645] [drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping [ 1.674646] [drm:intel_fb_initial_config] connector DP-2 has no encoder or crtc, skipping [ 1.674646] [drm:intel_fb_initial_config] connector HDMI-A-2 not enabled, skipping [ 1.674647] [drm:intel_fb_initial_config] fallback: Not all outputs enabled [ 1.674648] [drm:intel_fb_initial_config] Enabled: 1, detected: 3 [ 1.674649] [drm:intel_fb_initial_config] Not using firmware configuration [ 1.674650] [drm:drm_target_preferred] looking for cmdline mode on connector 39 [ 1.674651] [drm:drm_target_preferred] looking for preferred mode on connector 39 0 [ 1.674651] [drm:drm_target_preferred] found mode 1920x1080 [ 1.674652] [drm:drm_target_preferred] looking for cmdline mode on connector 47 [ 1.674653] [drm:drm_target_preferred] looking for preferred mode on connector 47 0 [ 1.674654] [drm:drm_target_preferred] found mode 1920x1080 [ 1.674654] [drm:drm_target_preferred] looking for cmdline mode on connector 54 [ 1.674655] [drm:drm_target_preferred] looking for preferred mode on connector 54 0 [ 1.674656] [drm:drm_target_preferred] found mode 1920x1080 [ 1.674657] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config [ 1.674661] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 26 (0,0) [ 1.674662] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 31 (0,0) [ 1.674664] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 36 (0,0) [ 1.674665] [drm:intelfb_create] re-using BIOS fb [ 1.674668] [drm:intelfb_create] allocated 1920x1080 fb: 0x00000000, bo ffff88026f59c000 [ 1.674677] [drm:drm_fb_helper_hotplug_event] [ 1.674679] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1] [ 1.674680] [drm:intel_dp_detect] [CONNECTOR:39:eDP-1] [ 1.674691] scsi 0:0:0:0: Direct-Access ATA INTEL SSDSC2BW08 LAFi PQ: 0 ANSI: 5 [ 1.676662] fbcon: inteldrmfb (fb0) is primary device [ 1.676681] [drm:intel_dp_probe_oui] Sink OUI: 001cf8 [ 1.678743] [drm:intel_dp_probe_oui] Branch OUI: 000000 [ 1.678837] [drm:drm_edid_to_eld] ELD: no CEA Extension found [ 1.678839] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1] probed modes : [ 1.678840] [drm:drm_mode_debug_printmodeline] Modeline 40:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 1.678841] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] [ 1.678843] [drm:intel_dp_detect] [CONNECTOR:47:DP-1] [ 1.680917] [drm:intel_dp_get_dpcd] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00 [ 1.682950] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink yes [ 1.682952] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 [ 1.682952] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000 [ 1.682953] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000 [ 1.685100] [drm:intel_dp_probe_mst] Sink is not MST capable [ 1.687189] [drm:drm_edid_to_eld] ELD monitor ASUS PB238 [ 1.687190] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0 [ 1.687191] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 [ 1.687206] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] probed modes : [ 1.687207] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 1.687208] [drm:drm_mode_debug_printmodeline] Modeline 100:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 1.687209] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.687210] [drm:drm_mode_debug_printmodeline] Modeline 108:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.687211] [drm:drm_mode_debug_printmodeline] Modeline 98:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 1.687212] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 1.687213] [drm:drm_mode_debug_printmodeline] Modeline 67:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 [ 1.687215] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.687216] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.687217] [drm:drm_mode_debug_printmodeline] Modeline 68:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 [ 1.687218] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 [ 1.687219] [drm:drm_mode_debug_printmodeline] Modeline 71:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 1.687220] [drm:drm_mode_debug_printmodeline] Modeline 64:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.687221] [drm:drm_mode_debug_printmodeline] Modeline 102:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.687222] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 1.687223] [drm:drm_mode_debug_printmodeline] Modeline 96:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa [ 1.687224] [drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 1.687225] [drm:drm_mode_debug_printmodeline] Modeline 80:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 1.687226] [drm:drm_mode_debug_printmodeline] Modeline 81:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 1.687227] [drm:drm_mode_debug_printmodeline] Modeline 109:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa [ 1.687228] [drm:drm_mode_debug_printmodeline] Modeline 94:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa [ 1.687229] [drm:drm_mode_debug_printmodeline] Modeline 82:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa [ 1.687230] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 1.687231] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 1.687232] [drm:drm_mode_debug_printmodeline] Modeline 72:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 1.687233] [drm:drm_mode_debug_printmodeline] Modeline 73:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 1.687234] [drm:drm_mode_debug_printmodeline] Modeline 66:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 1.687235] [drm:drm_mode_debug_printmodeline] Modeline 101:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 1.687236] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 1.687237] [drm:drm_mode_debug_printmodeline] Modeline 74:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 1.687238] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa [ 1.687239] [drm:drm_mode_debug_printmodeline] Modeline 103:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 1.687240] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.687241] [drm:drm_mode_debug_printmodeline] Modeline 77:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 1.687242] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1] [ 1.687242] [drm:intel_hdmi_detect] [CONNECTOR:51:HDMI-A-1] [ 1.687519] usb 1-2: New USB device found, idVendor=0b95, idProduct=7720 [ 1.687520] usb 1-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 1.687521] usb 1-2: Product: AX88x72A [ 1.687521] usb 1-2: Manufacturer: ASIX Elec. Corp. [ 1.687522] usb 1-2: SerialNumber: DADBD3 [ 1.688679] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 1.688679] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 1.690373] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 1.690375] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 1.691566] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 1.691567] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 1.692669] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 1.692671] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1] disconnected [ 1.692672] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2] [ 1.692673] [drm:intel_dp_detect] [CONNECTOR:54:DP-2] [ 1.692788] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 01 01 00 01 01 02 00 00 00 00 00 00 [ 1.692870] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no [ 1.692871] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 [ 1.692872] [drm:intel_dp_print_rates] sink rates: 162000, 270000 [ 1.692872] [drm:intel_dp_print_rates] common rates: 162000, 270000 [ 1.692971] [drm:drm_edid_to_eld] ELD: no CEA Extension found [ 1.692974] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2] probed modes : [ 1.692976] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 1.692977] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.692978] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.692979] [drm:drm_mode_debug_printmodeline] Modeline 87:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 1.692980] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 1.692981] [drm:drm_mode_debug_printmodeline] Modeline 104:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 1.692982] [drm:drm_mode_debug_printmodeline] Modeline 105:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 1.692983] [drm:drm_mode_debug_printmodeline] Modeline 89:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 1.692984] [drm:drm_mode_debug_printmodeline] Modeline 90:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 1.692985] [drm:drm_mode_debug_printmodeline] Modeline 91:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.692986] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 1.692987] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2] [ 1.692987] [drm:intel_hdmi_detect] [CONNECTOR:58:HDMI-A-2] [ 1.693029] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 1.693030] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 1.693069] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 1.693070] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [ 1.693110] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 1.693110] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 1.693148] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 1.693149] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2] disconnected [ 1.693151] [drm:drm_setup_crtcs] [ 1.693152] [drm:drm_enable_connectors] connector 39 enabled? yes [ 1.693152] [drm:drm_enable_connectors] connector 47 enabled? yes [ 1.693153] [drm:drm_enable_connectors] connector 51 enabled? no [ 1.693153] [drm:drm_enable_connectors] connector 54 enabled? yes [ 1.693154] [drm:drm_enable_connectors] connector 58 enabled? no [ 1.693154] [drm:intel_fb_initial_config] connector eDP-1 has no encoder or crtc, skipping [ 1.693155] [drm:intel_fb_initial_config] looking for cmdline mode on connector DP-1 [ 1.693156] [drm:intel_fb_initial_config] looking for preferred mode on connector DP-1 0 [ 1.693157] [drm:intel_fb_initial_config] connector DP-1 on [CRTC:26:pipe A]: 1920x1080 [ 1.693157] [drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping [ 1.693157] [drm:intel_fb_initial_config] connector DP-2 has no encoder or crtc, skipping [ 1.693158] [drm:intel_fb_initial_config] connector HDMI-A-2 not enabled, skipping [ 1.693158] [drm:intel_fb_initial_config] fallback: Not all outputs enabled [ 1.693159] [drm:intel_fb_initial_config] Enabled: 1, detected: 3 [ 1.693159] [drm:intel_fb_initial_config] Not using firmware configuration [ 1.693160] [drm:drm_target_preferred] looking for cmdline mode on connector 39 [ 1.693160] [drm:drm_target_preferred] looking for preferred mode on connector 39 0 [ 1.693160] [drm:drm_target_preferred] found mode 1920x1080 [ 1.693161] [drm:drm_target_preferred] looking for cmdline mode on connector 47 [ 1.693161] [drm:drm_target_preferred] looking for preferred mode on connector 47 0 [ 1.693162] [drm:drm_target_preferred] found mode 1920x1080 [ 1.693162] [drm:drm_target_preferred] looking for cmdline mode on connector 54 [ 1.693162] [drm:drm_target_preferred] looking for preferred mode on connector 54 0 [ 1.693163] [drm:drm_target_preferred] found mode 1920x1080 [ 1.693163] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config [ 1.693167] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 26 (0,0) [ 1.693168] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 31 (0,0) [ 1.693169] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 36 (0,0) [ 1.693179] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 1.693180] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 1.693181] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 1.693182] [drm:skl_update_scaler] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0 [ 1.693183] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 1.693185] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 1.693185] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 1.693186] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 1.693187] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88026efc9800 for pipe A [ 1.693187] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 1.693188] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 1.693188] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 1.693189] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 1.693190] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 1.693190] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 1.693191] [drm:intel_dump_pipe_config] requested mode: [ 1.693192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 1.693192] [drm:intel_dump_pipe_config] adjusted mode: [ 1.693193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 1.693194] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 1.693194] [drm:intel_dump_pipe_config] port clock: 270000 [ 1.693195] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 1.693195] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 1.693196] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 1.693196] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 1.693197] [drm:intel_dump_pipe_config] ips: 0 [ 1.693197] [drm:intel_dump_pipe_config] double wide: 0 [ 1.693198] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x4100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x58 [ 1.693199] [drm:intel_dump_pipe_config] planes on this crtc [ 1.693200] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 1.693201] [drm:intel_dump_pipe_config] FB:60, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 1.693201] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 [ 1.693202] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 1.693202] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 1.693203] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 1.693203] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 1.693204] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 1.693205] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 1.693205] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 1.693206] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 1.693206] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 1.693207] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88026efca000 for pipe B [ 1.693207] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 1.693208] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 1.693209] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 1.693209] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 1.693210] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 1.693210] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 1.693211] [drm:intel_dump_pipe_config] requested mode: [ 1.693212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 1.693212] [drm:intel_dump_pipe_config] adjusted mode: [ 1.693213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 1.693214] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 1.693214] [drm:intel_dump_pipe_config] port clock: 162000 [ 1.693215] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 1.693215] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 [ 1.693216] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 1.693216] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 1.693216] [drm:intel_dump_pipe_config] ips: 0 [ 1.693217] [drm:intel_dump_pipe_config] double wide: 0 [ 1.693218] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 [ 1.693218] [drm:intel_dump_pipe_config] planes on this crtc [ 1.693218] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 1.693219] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 1.693219] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 1.693220] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 1.693221] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 1.693221] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 1.693222] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 1.693222] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 1.693223] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 1.693223] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 1.693224] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88026efca800 for pipe C [ 1.693224] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 1.693225] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 1.693225] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 1.693226] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 1.693227] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 1.693227] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 1.693228] [drm:intel_dump_pipe_config] requested mode: [ 1.693229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 1.693229] [drm:intel_dump_pipe_config] adjusted mode: [ 1.693230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 1.693231] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 1.693231] [drm:intel_dump_pipe_config] port clock: 162000 [ 1.693232] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 1.693232] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: 0 [ 1.693233] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 1.693233] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 1.693233] [drm:intel_dump_pipe_config] ips: 0 [ 1.693234] [drm:intel_dump_pipe_config] double wide: 0 [ 1.693235] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 [ 1.693235] [drm:intel_dump_pipe_config] planes on this crtc [ 1.693236] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 1.693236] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 1.693236] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 1.693238] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 1.693240] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 1.693240] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 1.693241] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 1.693243] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A [ 1.693243] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A [ 1.693244] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 1.693244] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 1.693245] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 1.693245] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 1.693246] [drm:skl_update_scaler] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0 [ 1.693246] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C [ 1.693247] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C [ 1.693247] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 1.693248] [drm:skl_update_scaler] scaler_user index 2.31: Staged freeing scaler id 0 scaler_users = 0x0 [ 1.693266] [drm:intel_disable_pipe] disabling pipe A [ 1.695309] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26 [ 1.695314] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 1.695317] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 1.702694] sd 0:0:0:0: [sda] 156301488 512-byte logical blocks: (80.0 GB/74.5 GiB) [ 1.702703] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 1.702737] sd 0:0:0:0: [sda] Write Protect is off [ 1.702738] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 1.702750] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 1.702917] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 1.702918] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 1.702918] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 1.702919] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 1.702919] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 1.702920] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 1.702920] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 1.702921] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 1.702921] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 1.702921] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 1.702922] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 1.702924] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 1.702925] [drm:verify_single_dpll_state] PORT PLL A [ 1.702926] [drm:verify_single_dpll_state] PORT PLL B [ 1.702927] [drm:verify_single_dpll_state] PORT PLL C [ 1.702932] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26 [ 1.702932] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 1.702954] [drm:edp_panel_on] Turn eDP port A panel power on [ 1.702955] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 1.703494] sda: sda1 sda2 sda3 [ 1.703741] sd 0:0:0:0: [sda] Attached SCSI disk [ 1.719539] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 0000006a [ 1.719540] [drm:wait_panel_status] Wait complete [ 1.719541] [drm:wait_panel_on] Wait for panel power on [ 1.719542] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 0000006b [ 1.759834] usb 1-4: new full-speed USB device number 3 using xhci_hcd [ 1.771456] [drm:wait_panel_status] Wait complete [ 1.773800] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 1.773801] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 1.774040] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 1.776543] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 1.776585] [drm:skylake_pfit_enable] for crtc_state = ffff88026efc9800 [ 1.776633] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 1.776635] [drm:intel_enable_pipe] enabling pipe A [ 1.776645] [drm:intel_edp_backlight_on] [ 1.776646] [drm:intel_panel_enable_backlight] pipe A [ 1.776647] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 1.776648] [drm:intel_psr_enable] PSR not supported on this platform [ 1.776649] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 1.776670] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 1.776670] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 1.778795] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 1.778796] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 1.781243] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 1.787181] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 1.787232] [drm:skylake_pfit_enable] for crtc_state = ffff88026efca000 [ 1.787283] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 1.787284] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 1.787285] [drm:intel_enable_pipe] enabling pipe B [ 1.787308] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 1.787309] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 1.787329] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36 [ 1.787330] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 1.790489] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 1.790490] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 1.791690] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 1.792241] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 1.792241] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 1.794783] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 1.794831] [drm:skylake_pfit_enable] for crtc_state = ffff88026efca800 [ 1.794884] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 1.794885] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 1.794886] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 1.794887] [drm:intel_enable_pipe] enabling pipe C [ 1.799050] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 1.799053] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 1.799063] [drm:intel_ddi_get_config] pipe has 24 bpp for eDP panel, overriding BIOS-provided max 18 bpp [ 1.799067] [drm:verify_single_dpll_state] PORT PLL A [ 1.799074] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 1.799076] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 1.799087] [drm:verify_single_dpll_state] PORT PLL B [ 1.799092] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 1.799094] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 1.799103] [drm:verify_single_dpll_state] PORT PLL C [ 1.799130] [drm:drm_fb_helper_hotplug_event] [ 1.799131] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1] [ 1.799132] [drm:intel_dp_detect] [CONNECTOR:39:eDP-1] [ 1.799221] [drm:intel_dp_probe_oui] Sink OUI: 001cf8 [ 1.799308] [drm:intel_dp_probe_oui] Branch OUI: 000000 [ 1.799406] [drm:drm_edid_to_eld] ELD: no CEA Extension found [ 1.799407] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:39:eDP-1] probed modes : [ 1.799408] [drm:drm_mode_debug_printmodeline] Modeline 40:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 1.799409] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] [ 1.799410] [drm:intel_dp_detect] [CONNECTOR:47:DP-1] [ 1.799523] [drm:intel_dp_get_dpcd] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00 [ 1.799608] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink yes [ 1.799609] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 [ 1.799610] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000 [ 1.799611] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000 [ 1.799808] [drm:intel_dp_probe_mst] Sink is not MST capable [ 1.799935] [drm:drm_edid_to_eld] ELD monitor ASUS PB238 [ 1.799935] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0 [ 1.799936] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 [ 1.799951] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] probed modes : [ 1.799952] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 1.799953] [drm:drm_mode_debug_printmodeline] Modeline 100:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 1.799954] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.799955] [drm:drm_mode_debug_printmodeline] Modeline 108:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.799956] [drm:drm_mode_debug_printmodeline] Modeline 98:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 1.799957] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 1.799958] [drm:drm_mode_debug_printmodeline] Modeline 67:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 [ 1.799959] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.799961] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.799962] [drm:drm_mode_debug_printmodeline] Modeline 68:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 [ 1.799963] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 [ 1.799964] [drm:drm_mode_debug_printmodeline] Modeline 71:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 1.799965] [drm:drm_mode_debug_printmodeline] Modeline 64:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.799966] [drm:drm_mode_debug_printmodeline] Modeline 102:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.799967] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 1.799968] [drm:drm_mode_debug_printmodeline] Modeline 96:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa [ 1.799969] [drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 1.799970] [drm:drm_mode_debug_printmodeline] Modeline 80:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 1.799971] [drm:drm_mode_debug_printmodeline] Modeline 81:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 1.799972] [drm:drm_mode_debug_printmodeline] Modeline 109:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa [ 1.799973] [drm:drm_mode_debug_printmodeline] Modeline 94:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa [ 1.799974] [drm:drm_mode_debug_printmodeline] Modeline 82:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa [ 1.799975] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 1.799976] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 1.799977] [drm:drm_mode_debug_printmodeline] Modeline 72:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 1.799978] [drm:drm_mode_debug_printmodeline] Modeline 73:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 1.799979] [drm:drm_mode_debug_printmodeline] Modeline 66:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 1.799980] [drm:drm_mode_debug_printmodeline] Modeline 101:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 1.799981] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 1.799982] [drm:drm_mode_debug_printmodeline] Modeline 74:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 1.799983] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa [ 1.799984] [drm:drm_mode_debug_printmodeline] Modeline 103:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 1.799985] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.799986] [drm:drm_mode_debug_printmodeline] Modeline 77:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 1.799987] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1] [ 1.799987] [drm:intel_hdmi_detect] [CONNECTOR:51:HDMI-A-1] [ 1.800030] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 1.800030] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 1.800072] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 1.800073] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 1.800113] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 1.800114] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 1.800154] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 1.800155] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:HDMI-A-1] disconnected [ 1.800156] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2] [ 1.800157] [drm:intel_dp_detect] [CONNECTOR:54:DP-2] [ 1.800272] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 01 01 00 01 01 02 00 00 00 00 00 00 [ 1.800359] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no [ 1.800360] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 [ 1.800361] [drm:intel_dp_print_rates] sink rates: 162000, 270000 [ 1.800361] [drm:intel_dp_print_rates] common rates: 162000, 270000 [ 1.800459] [drm:drm_edid_to_eld] ELD: no CEA Extension found [ 1.800462] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:DP-2] probed modes : [ 1.800463] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 1.800464] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.800465] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.800466] [drm:drm_mode_debug_printmodeline] Modeline 87:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 1.800467] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 1.800468] [drm:drm_mode_debug_printmodeline] Modeline 104:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 1.800469] [drm:drm_mode_debug_printmodeline] Modeline 105:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 1.800470] [drm:drm_mode_debug_printmodeline] Modeline 89:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 1.800471] [drm:drm_mode_debug_printmodeline] Modeline 90:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 1.800472] [drm:drm_mode_debug_printmodeline] Modeline 91:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.800473] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 1.800474] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2] [ 1.800474] [drm:intel_hdmi_detect] [CONNECTOR:58:HDMI-A-2] [ 1.800515] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 1.800516] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 1.800557] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 1.800557] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [ 1.800597] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 1.800598] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 1.800637] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 1.800638] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:58:HDMI-A-2] disconnected [ 1.800640] [drm:drm_setup_crtcs] [ 1.800641] [drm:drm_enable_connectors] connector 39 enabled? yes [ 1.800642] [drm:drm_enable_connectors] connector 47 enabled? yes [ 1.800642] [drm:drm_enable_connectors] connector 51 enabled? no [ 1.800642] [drm:drm_enable_connectors] connector 54 enabled? yes [ 1.800643] [drm:drm_enable_connectors] connector 58 enabled? no [ 1.800644] [drm:intel_fb_initial_config] looking for cmdline mode on connector eDP-1 [ 1.800644] [drm:intel_fb_initial_config] looking for preferred mode on connector eDP-1 0 [ 1.800645] [drm:intel_fb_initial_config] connector eDP-1 on [CRTC:26:pipe A]: 1920x1080 [ 1.800646] [drm:intel_fb_initial_config] looking for cmdline mode on connector DP-1 [ 1.800646] [drm:intel_fb_initial_config] looking for preferred mode on connector DP-1 0 [ 1.800647] [drm:intel_fb_initial_config] connector DP-1 on [CRTC:31:pipe B]: 1920x1080 [ 1.800647] [drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping [ 1.800648] [drm:intel_fb_initial_config] looking for cmdline mode on connector DP-2 [ 1.800648] [drm:intel_fb_initial_config] looking for preferred mode on connector DP-2 0 [ 1.800649] [drm:intel_fb_initial_config] connector DP-2 on [CRTC:36:pipe C]: 1920x1080 [ 1.800649] [drm:intel_fb_initial_config] connector HDMI-A-2 not enabled, skipping [ 1.800650] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 26 (0,0) [ 1.800651] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 31 (0,0) [ 1.800652] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 36 (0,0) [ 1.800662] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 1.800663] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 1.800663] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 1.803784] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 1.803785] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 1.803786] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 1.804800] usb 1-4: New USB device found, idVendor=045e, idProduct=0745 [ 1.804801] usb 1-4: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [ 1.804801] usb 1-4: Product: Microsoft® 2.4GHz Transceiver v8.0 [ 1.804802] usb 1-4: Manufacturer: Microsoft [ 1.806788] calling hid_init+0x0/0x1000 [usbhid] @ 151 [ 1.807879] Console: switching to colour frame buffer device 240x67 [ 1.807894] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 1.807895] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 1.807896] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 1.810132] usbcore: registered new interface driver usbhid [ 1.810133] usbhid: USB HID core driver [ 1.810137] initcall hid_init+0x0/0x1000 [usbhid] returned 0 after 13245 usecs [ 1.811187] calling hid_generic_init+0x0/0x1000 [hid_generic] @ 149 [ 1.811275] input: Microsoft Microsoft® 2.4GHz Transceiver v8.0 as /devices/pci0000:00/0000:00:15.0/usb1/1-4/1-4:1.0/0003:045E:0745.0001/input/input5 [ 1.816829] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device [ 1.839359] hid-generic 0003:045E:0745.0001: input,hidraw0: USB HID v1.11 Keyboard [Microsoft Microsoft® 2.4GHz Transceiver v8.0] on usb-0000:00:15.0-4/input0 [ 1.839615] input: Microsoft Microsoft® 2.4GHz Transceiver v8.0 as /devices/pci0000:00/0000:00:15.0/usb1/1-4/1-4:1.1/0003:045E:0745.0002/input/input6 [ 1.853735] hid-generic 0003:045E:0745.0002: input,hidraw1: USB HID v1.11 Mouse [Microsoft Microsoft® 2.4GHz Transceiver v8.0] on usb-0000:00:15.0-4/input1 [ 1.856154] usb 1-7: new full-speed USB device number 4 using xhci_hcd [ 1.856331] input: Microsoft Microsoft® 2.4GHz Transceiver v8.0 as /devices/pci0000:00/0000:00:15.0/usb1/1-4/1-4:1.2/0003:045E:0745.0003/input/input7 [ 1.878038] hid-generic 0003:045E:0745.0003: input,hiddev0,hidraw2: USB HID v1.11 Device [Microsoft Microsoft® 2.4GHz Transceiver v8.0] on usb-0000:00:15.0-4/input2 [ 1.878111] initcall hid_generic_init+0x0/0x1000 [hid_generic] returned 0 after 265013 usecs [ 1.881938] clocksource: timekeeping watchdog on CPU1: Marking clocksource 'tsc' as unstable because the skew is too large: [ 1.881980] clocksource: 'hpet' wd_now: 8de597d wd_last: 8790881 mask: ffffffff [ 1.882009] clocksource: 'tsc' cs_now: 7248daa17 cs_last: 70dfeb16d mask: ffffffffffffffff [ 1.894051] [drm] RC6 on [ 1.901594] usb 1-7: New USB device found, idVendor=8087, idProduct=0a2a [ 1.901624] usb 1-7: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 1.924369] EXT4-fs (sda3): mounted filesystem with ordered data mode. Opts: (null) [ 1.959225] systemd[1]: System time before build time, advancing clock. [ 1.964268] calling init_autofs4_fs+0x0/0x27 [autofs4] @ 1 [ 1.964333] initcall init_autofs4_fs+0x0/0x27 [autofs4] returned 0 after 237 usecs [ 2.001897] systemd[1]: systemd 229 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ -LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN) [ 2.003475] systemd[1]: Detected architecture x86-64. [ 2.010911] systemd[1]: Set hostname to . [ 2.048463] systemd[1]: Listening on fsck to fsckd communication Socket. [ 2.051939] systemd[1]: Listening on udev Kernel Socket. [ 2.055359] systemd[1]: Listening on Journal Socket (/dev/log). [ 2.058744] systemd[1]: Listening on Syslog Socket. [ 2.062232] systemd[1]: Created slice User and Session Slice. [ 2.065786] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point. [ 2.069321] systemd[1]: Listening on Journal Socket. [ 2.072812] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe. [ 2.076339] systemd[1]: Reached target Remote File Systems (Pre). [ 2.079878] systemd[1]: Reached target Remote File Systems. [ 2.083457] systemd[1]: Started Forward Password Requests to Wall Directory Watch. [ 2.087069] systemd[1]: Reached target Encrypted Volumes. [ 2.090661] systemd[1]: Listening on udev Control Socket. [ 2.094263] systemd[1]: Listening on Journal Audit Socket. [ 2.097906] systemd[1]: Created slice System Slice. [ 2.108140] systemd[1]: Mounting Debug File System... [ 2.112080] systemd[1]: Mounting POSIX Message Queue File System... [ 2.116039] systemd[1]: Starting Journal Service... [ 2.120023] systemd[1]: Starting Load Kernel Modules... [ 2.122950] calling parport_default_proc_register+0x0/0x1000 [parport] @ 243 [ 2.122965] initcall parport_default_proc_register+0x0/0x1000 [parport] returned 0 after 44 usecs [ 2.123728] systemd[1]: Starting Braille Device Support... [ 2.125145] calling lp_init_module+0x0/0x1000 [lp] @ 243 [ 2.127026] systemd[1]: Reached target Slices. [ 2.127151] lp: driver loaded but no devices found [ 2.127156] initcall lp_init_module+0x0/0x1000 [lp] returned 0 after 7944 usecs [ 2.130584] calling ppdev_init+0x0/0x1000 [ppdev] @ 243 [ 2.131260] ppdev: user-space parallel port driver [ 2.131266] initcall ppdev_init+0x0/0x1000 [ppdev] returned 0 after 2680 usecs [ 2.132729] calling parport_pc_init+0x0/0xf44 [parport_pc] @ 243 [ 2.132975] initcall parport_pc_init+0x0/0xf44 [parport_pc] returned 0 after 948 usecs [ 2.133044] systemd[1]: Starting Uncomplicated firewall... [ 2.136532] systemd[1]: Starting Create list of required static device nodes for the current kernel... [ 2.140013] systemd[1]: Mounting Huge Pages File System... [ 2.143160] systemd[1]: Created slice system-systemd\x2dfsck.slice. [ 2.146636] systemd[1]: Started Read required files in advance. [ 2.150166] systemd[1]: Created slice system-getty.slice. [ 2.153962] systemd[1]: Mounted Debug File System. [ 2.156562] systemd[1]: Mounted Huge Pages File System. [ 2.159149] systemd[1]: Mounted POSIX Message Queue File System. [ 2.161879] systemd[1]: Started Load Kernel Modules. [ 2.164848] systemd[1]: Started Braille Device Support. [ 2.167824] systemd[1]: Started Uncomplicated firewall. [ 2.170808] systemd[1]: Started Create list of required static device nodes for the current kernel. [ 2.173836] systemd[1]: ureadahead.service: Main process exited, code=exited, status=5/NOTINSTALLED [ 2.175298] systemd[1]: ureadahead.service: Unit entered failed state. [ 2.176559] systemd[1]: ureadahead.service: Failed with result 'exit-code'. [ 2.185233] systemd[1]: Started Journal Service. [ 2.235453] EXT4-fs (sda3): re-mounted. Opts: errors=remount-ro [ 2.252413] systemd-journald[242]: Received request to flush runtime journal from PID 1 [ 2.303330] calling mac_hid_init+0x0/0x1000 [mac_hid] @ 290 [ 2.303339] initcall mac_hid_init+0x0/0x1000 [mac_hid] returned 0 after 14 usecs [ 2.307117] calling intel_pmc_ipc_init+0x0/0x1000 [intel_pmc_ipc] @ 284 [ 2.307151] initcall intel_pmc_ipc_init+0x0/0x1000 [intel_pmc_ipc] returned 0 after 116 usecs [ 2.308242] calling crb_acpi_driver_init+0x0/0x1000 [tpm_crb] @ 293 [ 2.316927] initcall crb_acpi_driver_init+0x0/0x1000 [tpm_crb] returned 0 after 34367 usecs [ 2.328494] calling rfkill_gpio_driver_init+0x0/0x1000 [rfkill_gpio] @ 298 [ 2.328817] rfkill_gpio BCM4752:00: invalid platform data [ 2.340292] calling mei_init+0x0/0xae [mei] @ 283 [ 2.340308] initcall mei_init+0x0/0xae [mei] returned 0 after 40 usecs [ 2.340461] calling shpcd_init+0x0/0x1000 [shpchp] @ 293 [ 2.340478] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4 [ 2.340482] initcall shpcd_init+0x0/0x1000 [shpchp] returned 0 after 60 usecs [ 2.341837] rfkill_gpio: probe of BCM4752:00 failed with error -22 [ 2.341857] initcall rfkill_gpio_driver_init+0x0/0x1000 [rfkill_gpio] returned 0 after 52898 usecs [ 2.342507] calling mei_me_driver_init+0x0/0x1000 [mei_me] @ 283 [ 2.343892] calling init_soundcore+0x0/0x1000 [soundcore] @ 282 [ 2.343902] initcall init_soundcore+0x0/0x1000 [soundcore] returned 0 after 23 usecs [ 2.346569] initcall mei_me_driver_init+0x0/0x1000 [mei_me] returned 0 after 16060 usecs [ 2.347897] calling alsa_sound_init+0x0/0x84 [snd] @ 307 [ 2.347909] initcall alsa_sound_init+0x0/0x84 [snd] returned 0 after 23 usecs [ 2.353175] calling cfg80211_init+0x0/0xdb [cfg80211] @ 298 [ 2.353502] initcall cfg80211_init+0x0/0xdb [cfg80211] returned 0 after 1228 usecs [ 2.357626] calling iwl_drv_init+0x0/0x8e [iwlwifi] @ 298 [ 2.357629] calling alsa_timer_init+0x0/0x1000 [snd_timer] @ 310 [ 2.357633] Intel(R) Wireless WiFi driver for Linux [ 2.357634] Copyright(c) 2003- 2015 Intel Corporation [ 2.357763] initcall alsa_timer_init+0x0/0x1000 [snd_timer] returned 0 after 510 usecs [ 2.358159] initcall iwl_drv_init+0x0/0x8e [iwlwifi] returned 0 after 2049 usecs [ 2.358551] iwlwifi 0000:03:00.0: Direct firmware load for iwlwifi-7265D-21.ucode failed with error -2 [ 2.358553] iwlwifi 0000:03:00.0: Falling back to user helper [ 2.360020] calling alsa_seq_device_init+0x0/0x1000 [snd_seq_device] @ 310 [ 2.360033] initcall alsa_seq_device_init+0x0/0x1000 [snd_seq_device] returned 0 after 32 usecs [ 2.365737] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=96000/96000 [ 2.365739] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 2.371248] calling alsa_seq_init+0x0/0x48 [snd_seq] @ 319 [ 2.371288] initcall alsa_seq_init+0x0/0x48 [snd_seq] returned 0 after 136 usecs [ 2.376571] calling alsa_rawmidi_init+0x0/0x1000 [snd_rawmidi] @ 329 [ 2.376577] initcall alsa_rawmidi_init+0x0/0x1000 [snd_rawmidi] returned 0 after 5 usecs [ 2.378460] calling alsa_seq_midi_event_init+0x0/0x1000 [snd_seq_midi_event] @ 331 [ 2.378467] initcall alsa_seq_midi_event_init+0x0/0x1000 [snd_seq_midi_event] returned 0 after 9 usecs [ 2.379374] calling seq_midisynth_driver_init+0x0/0x1000 [snd_seq_midi] @ 331 [ 2.379389] initcall seq_midisynth_driver_init+0x0/0x1000 [snd_seq_midi] returned 0 after 40 usecs [ 2.381026] calling serio_raw_drv_init+0x0/0x1000 [serio_raw] @ 291 [ 2.381040] initcall serio_raw_drv_init+0x0/0x1000 [serio_raw] returned 0 after 38 usecs [ 2.384205] calling joydev_init+0x0/0x1000 [joydev] @ 295 [ 2.384260] initcall joydev_init+0x0/0x1000 [joydev] returned 0 after 196 usecs [ 2.386951] calling bt_init+0x0/0xb6 [bluetooth] @ 284 [ 2.386955] Bluetooth: Core ver 2.21 [ 2.386962] NET: Registered protocol family 31 [ 2.386963] Bluetooth: HCI device and connection manager initialized [ 2.386966] Bluetooth: HCI socket layer initialized [ 2.386967] Bluetooth: L2CAP socket layer initialized [ 2.386970] Bluetooth: SCO socket layer initialized [ 2.386982] initcall bt_init+0x0/0xb6 [bluetooth] returned 0 after 72 usecs [ 2.393953] calling btusb_driver_init+0x0/0x1000 [btusb] @ 284 [ 2.396293] calling cryptd_init+0x0/0x1000 [cryptd] @ 283 [ 2.396301] initcall cryptd_init+0x0/0x1000 [cryptd] returned 0 after 12 usecs [ 2.400534] calling crypto_module_init+0x0/0x1000 [lrw] @ 297 [ 2.400540] initcall crypto_module_init+0x0/0x1000 [lrw] returned 0 after 6 usecs [ 2.401541] calling aes_init+0x0/0x1000 [aes_x86_64] @ 291 [ 2.402237] initcall aes_init+0x0/0x1000 [aes_x86_64] returned 0 after 2732 usecs [ 2.402635] usbcore: registered new interface driver btusb [ 2.402641] initcall btusb_driver_init+0x0/0x1000 [btusb] returned 0 after 34379 usecs [ 2.404694] calling aesni_init+0x0/0x13e [aesni_intel] @ 297 [ 2.404697] SSE version of gcm_enc/dec engaged. [ 2.408703] Bluetooth: hci0: read Intel version: 370810011003110e00 [ 2.410015] Bluetooth: hci0: Intel Bluetooth firmware file: intel/ibt-hw-37.8.10-fw-1.10.3.11.e.bseq [ 2.420208] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off [ 2.420210] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067 [ 2.425684] initcall aesni_init+0x0/0x13e [aesni_intel] returned 0 after 83089 usecs [ 2.425785] calling alsa_pcm_init+0x0/0x6c [snd_pcm] @ 348 [ 2.425795] initcall alsa_pcm_init+0x0/0x6c [snd_pcm] returned 0 after 12 usecs [ 2.426812] calling ghash_pclmulqdqni_mod_init+0x0/0x1000 [ghash_clmulni_intel] @ 286 [ 2.426986] initcall ghash_pclmulqdqni_mod_init+0x0/0x1000 [ghash_clmulni_intel] returned 0 after 662 usecs [ 2.427906] calling crc32_pclmul_mod_init+0x0/0x1000 [crc32_pclmul] @ 286 [ 2.428235] initcall crc32_pclmul_mod_init+0x0/0x1000 [crc32_pclmul] returned 0 after 1278 usecs [ 2.428398] calling alsa_hwdep_init+0x0/0x1000 [snd_hwdep] @ 282 [ 2.428405] initcall alsa_hwdep_init+0x0/0x1000 [snd_hwdep] returned 0 after 12 usecs [ 2.429210] calling crct10dif_intel_mod_init+0x0/0x1000 [crct10dif_pclmul] @ 286 [ 2.430396] initcall crct10dif_intel_mod_init+0x0/0x1000 [crct10dif_pclmul] returned 0 after 4668 usecs [ 2.431337] calling hda_bus_init+0x0/0x12 [snd_hda_core] @ 282 [ 2.431354] initcall hda_bus_init+0x0/0x12 [snd_hda_core] returned 0 after 38 usecs [ 2.450582] calling azx_driver_init+0x0/0xfce [snd_hda_intel] @ 282 [ 2.450824] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915]) [ 2.450933] initcall azx_driver_init+0x0/0xfce [snd_hda_intel] returned 0 after 1360 usecs [ 2.455357] calling vmx_init+0x0/0x370 [kvm_intel] @ 283 [ 2.455694] initcall vmx_init+0x0/0x370 [kvm_intel] returned 0 after 1302 usecs [ 2.456664] calling coretemp_init+0x0/0x1000 [coretemp] @ 283 [ 2.456746] initcall coretemp_init+0x0/0x1000 [coretemp] returned 0 after 307 usecs [ 2.457825] calling powerclamp_init+0x0/0x1000 [intel_powerclamp] @ 283 [ 2.457855] initcall powerclamp_init+0x0/0x1000 [intel_powerclamp] returned 0 after 109 usecs [ 2.458861] calling pkg_temp_thermal_init+0x0/0x1000 [x86_pkg_temp_thermal] @ 283 [ 2.458899] initcall pkg_temp_thermal_init+0x0/0x1000 [x86_pkg_temp_thermal] returned 0 after 129 usecs [ 2.466783] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 2.466784] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 2.466785] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 2.475427] iwlwifi 0000:03:00.0: Direct firmware load for iwlwifi-7265D-20.ucode failed with error -2 [ 2.475427] iwlwifi 0000:03:00.0: Falling back to user helper [ 2.478070] calling generic_driver_init+0x0/0x1000 [snd_hda_codec_generic] @ 399 [ 2.478083] initcall generic_driver_init+0x0/0x1000 [snd_hda_codec_generic] returned 0 after 36 usecs [ 2.479433] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 2.479434] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 2.479435] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 2.479966] calling realtek_driver_init+0x0/0x1000 [snd_hda_codec_realtek] @ 399 [ 2.480118] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC298: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker [ 2.480119] snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) [ 2.480120] snd_hda_codec_realtek hdaudioC0D0: hp_outs=1 (0x21/0x0/0x0/0x0/0x0) [ 2.480121] snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0 [ 2.480121] snd_hda_codec_realtek hdaudioC0D0: inputs: [ 2.480122] snd_hda_codec_realtek hdaudioC0D0: Mic=0x18 [ 2.483591] initcall realtek_driver_init+0x0/0x1000 [snd_hda_codec_realtek] returned 0 after 14328 usecs [ 2.486347] iwlwifi 0000:03:00.0: Direct firmware load for iwlwifi-7265D-19.ucode failed with error -2 [ 2.486348] iwlwifi 0000:03:00.0: Falling back to user helper [ 2.487879] iwlwifi 0000:03:00.0: Direct firmware load for iwlwifi-7265D-18.ucode failed with error -2 [ 2.487881] iwlwifi 0000:03:00.0: Falling back to user helper [ 2.491285] iwlwifi 0000:03:00.0: Direct firmware load for iwlwifi-7265D-17.ucode failed with error -2 [ 2.491287] iwlwifi 0000:03:00.0: Falling back to user helper [ 2.492105] calling hdmi_driver_init+0x0/0x1000 [snd_hda_codec_hdmi] @ 286 [ 2.493316] initcall hdmi_driver_init+0x0/0x1000 [snd_hda_codec_hdmi] returned 0 after 4767 usecs [ 2.494024] Bluetooth: hci0: Intel Bluetooth firmware patch completed and activated [ 2.494271] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input8 [ 2.494280] iwlwifi 0000:03:00.0: loaded firmware version 16.242414.0 op_mode iwlmvm [ 2.494321] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input9 [ 2.494359] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input10 [ 2.494397] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input11 [ 2.494434] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input12 [ 2.504606] Adding 4658172k swap on /dev/sda2. Priority:-1 extents:1 across:4658172k SSFS [ 2.507532] calling ieee80211_init+0x0/0x3f [mac80211] @ 424 [ 2.507549] initcall ieee80211_init+0x0/0x3f [mac80211] returned 0 after 15 usecs [ 2.508340] random: nonblocking pool is initialized [ 2.512198] calling iwl_mvm_init+0x0/0x1000 [iwlmvm] @ 424 [ 2.512219] iwlwifi 0000:03:00.0: Detected Intel(R) Dual Band Wireless AC 7265, REV=0x210 [ 2.514803] iwlwifi 0000:03:00.0: L1 Enabled - LTR Enabled [ 2.514985] iwlwifi 0000:03:00.0: L1 Enabled - LTR Enabled [ 2.527356] calling init_nls_iso8859_1+0x0/0x1000 [nls_iso8859_1] @ 450 [ 2.527360] initcall init_nls_iso8859_1+0x0/0x1000 [nls_iso8859_1] returned 0 after 4 usecs [ 2.537784] calling arc4_init+0x0/0x1000 [arc4] @ 455 [ 2.537844] initcall arc4_init+0x0/0x1000 [arc4] returned 0 after 217 usecs [ 2.538593] ieee80211 phy0: Selected rate control algorithm 'iwl-mvm-rs' [ 2.538745] initcall iwl_mvm_init+0x0/0x1000 [iwlmvm] returned 0 after 105080 usecs [ 2.539650] iwlwifi 0000:03:00.0 wlp3s0: renamed from wlan0 [ 2.569978] calling init_misc_binfmt+0x0/0x1000 [binfmt_misc] @ 490 [ 2.569985] initcall init_misc_binfmt+0x0/0x1000 [binfmt_misc] returned 0 after 11 usecs [ 2.589289] audit: type=1400 audit(1455208082.547:2): apparmor="STATUS" operation="profile_load" name="/sbin/dhclient" pid=526 comm="apparmor_parser" [ 2.589292] audit: type=1400 audit(1455208082.547:3): apparmor="STATUS" operation="profile_load" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=526 comm="apparmor_parser" [ 2.589294] audit: type=1400 audit(1455208082.547:4): apparmor="STATUS" operation="profile_load" name="/usr/lib/NetworkManager/nm-dhcp-helper" pid=526 comm="apparmor_parser" [ 2.589296] audit: type=1400 audit(1455208082.547:5): apparmor="STATUS" operation="profile_load" name="/usr/lib/connman/scripts/dhclient-script" pid=526 comm="apparmor_parser" [ 2.589442] audit: type=1400 audit(1455208082.547:6): apparmor="STATUS" operation="profile_load" name="/usr/lib/lightdm/lightdm-guest-session" pid=525 comm="apparmor_parser" [ 2.589446] audit: type=1400 audit(1455208082.547:7): apparmor="STATUS" operation="profile_load" name="chromium" pid=525 comm="apparmor_parser" [ 2.592332] audit: type=1400 audit(1455208082.563:8): apparmor="STATUS" operation="profile_load" name="webbrowser-app" pid=531 comm="apparmor_parser" [ 2.592335] audit: type=1400 audit(1455208082.563:9): apparmor="STATUS" operation="profile_load" name="oxide_helper" pid=531 comm="apparmor_parser" [ 2.592392] audit: type=1400 audit(1455208082.563:10): apparmor="STATUS" operation="profile_load" name="/usr/sbin/cups-browsed" pid=533 comm="apparmor_parser" [ 2.677321] calling usbnet_init+0x0/0x1000 [usbnet] @ 285 [ 2.677332] initcall usbnet_init+0x0/0x1000 [usbnet] returned 0 after 20 usecs [ 2.678618] calling asix_driver_init+0x0/0x1000 [asix] @ 285 [ 2.722121] calling bnep_init+0x0/0x71 [bnep] @ 687 [ 2.722124] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 2.722125] Bluetooth: BNEP filters: protocol multicast [ 2.722127] Bluetooth: BNEP socket layer initialized [ 2.722131] initcall bnep_init+0x0/0x71 [bnep] returned 0 after 21 usecs [ 2.872237] IPv6: ADDRCONF(NETDEV_UP): wlp3s0: link is not ready [ 2.874327] iwlwifi 0000:03:00.0: L1 Enabled - LTR Enabled [ 2.874533] iwlwifi 0000:03:00.0: L1 Enabled - LTR Enabled [ 2.895336] iwlwifi 0000:03:00.0: L1 Enabled - LTR Enabled [ 2.895502] iwlwifi 0000:03:00.0: L1 Enabled - LTR Enabled [ 2.902619] IPv6: ADDRCONF(NETDEV_UP): wlp3s0: link is not ready [ 2.902752] asix 1-2:1.0 eth0: register 'asix' at usb-0000:00:15.0-2, ASIX AX88772 USB 2.0 Ethernet, 00:14:d1:da:db:d3 [ 2.902773] usbcore: registered new interface driver asix [ 2.902780] initcall asix_driver_init+0x0/0x1000 [asix] returned 0 after 887696 usecs [ 2.904495] asix 1-2:1.0 enx0014d1dadbd3: renamed from eth0 [ 2.918745] IPv6: ADDRCONF(NETDEV_UP): enx0014d1dadbd3: link is not ready [ 2.919082] asix 1-2:1.0 enx0014d1dadbd3: link down [ 2.919297] IPv6: ADDRCONF(NETDEV_UP): enx0014d1dadbd3: link is not ready [ 2.975139] IPv6: ADDRCONF(NETDEV_UP): wlp3s0: link is not ready [ 3.322809] IPv6: ADDRCONF(NETDEV_CHANGE): enx0014d1dadbd3: link becomes ready [ 3.323056] asix 1-2:1.0 enx0014d1dadbd3: link up, 100Mbps, full-duplex, lpa 0xCDE1 [ 4.791461] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 4.791462] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 4.791462] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 20.379234] kms_pipe_crc_basic: executing [ 20.379296] [drm:i915_gem_open] [ 20.379388] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 20.379390] [drm:i915_pages_create_for_stolen] offset=0x7f9000, size=16384 [ 20.379473] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 20.379475] [drm:i915_pages_create_for_stolen] offset=0x7fd000, size=16384 [ 20.379490] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 20.379492] [drm:i915_pages_create_for_stolen] offset=0x801000, size=16384 [ 20.379504] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 20.379506] [drm:i915_pages_create_for_stolen] offset=0x805000, size=16384 [ 20.379817] [drm:i915_gem_open] [ 20.379865] [drm:i915_gem_open] [ 20.380638] kms_pipe_crc_basic: starting subtest bad-pipe [ 20.380654] [drm:display_crc_ctl_parse] unknown pipe D [ 20.380683] kms_pipe_crc_basic: starting subtest bad-source [ 20.380696] [drm:display_crc_ctl_parse] unknown source foo [ 20.380712] kms_pipe_crc_basic: starting subtest bad-nb-words-1 [ 20.380725] [drm:display_crc_ctl_parse] tokenize failed, a command is 3 words [ 20.380740] kms_pipe_crc_basic: starting subtest bad-nb-words-3 [ 20.380753] [drm:display_crc_ctl_tokenize] too many words, allowed <= 3 [ 20.380754] [drm:display_crc_ctl_parse] tokenize failed, a command is 3 words [ 20.380770] kms_pipe_crc_basic: starting subtest read-crc-pipe-A [ 20.380939] [drm:drm_mode_addfb2] [FB:107] [ 20.385124] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 20.385129] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 20.385138] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 20.393538] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 20.414057] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 20.418199] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 20.418204] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 20.418206] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 20.418219] [drm:intel_edp_backlight_off] [ 20.482166] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 20.482174] [drm:intel_disable_pipe] disabling pipe A [ 20.484635] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 20.484639] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 20.484683] [drm:edp_panel_off] Turn eDP port A panel power off [ 20.484687] [drm:wait_panel_off] Wait for panel power off time [ 20.484689] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 20.497184] [drm:wait_panel_status] Wait complete [ 20.497191] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26 [ 20.497201] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 20.497207] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 20.497209] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.497212] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 20.497214] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 20.497215] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 20.497216] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 20.497217] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 20.497218] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 20.497219] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 20.497220] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 20.497221] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 20.497222] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 20.497224] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 20.497226] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 20.497228] [drm:verify_single_dpll_state] PORT PLL A [ 20.497229] [drm:verify_single_dpll_state] PORT PLL B [ 20.497237] [drm:verify_single_dpll_state] PORT PLL C [ 20.497246] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 20.497248] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.497268] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 20.497270] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.497287] [drm:intel_power_well_disable] disabling dpio-common-a [ 20.497290] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 20.497647] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 20.497650] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 20.497651] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 20.497660] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 20.499579] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun [ 20.499600] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun [ 20.501239] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 20.504190] [drm:drm_mode_addfb2] [FB:107] [ 20.507472] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 20.507476] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 20.507484] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 20.507485] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 20.507488] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 20.507489] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 20.507492] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 20.507493] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 20.507495] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 20.507497] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d5000 for pipe A [ 20.507498] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 20.507499] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 20.507500] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 20.507502] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 20.507503] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 20.507504] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 20.507505] [drm:intel_dump_pipe_config] requested mode: [ 20.507507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 20.507508] [drm:intel_dump_pipe_config] adjusted mode: [ 20.507509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 20.507511] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 20.507512] [drm:intel_dump_pipe_config] port clock: 270000 [ 20.507513] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 20.507514] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 20.507515] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 20.507517] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 20.507517] [drm:intel_dump_pipe_config] ips: 0 [ 20.507518] [drm:intel_dump_pipe_config] double wide: 0 [ 20.507520] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 20.507521] [drm:intel_dump_pipe_config] planes on this crtc [ 20.507522] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 20.507524] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 20.507525] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 20.507526] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 20.507528] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 20.507530] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 20.507533] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A [ 20.507534] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A [ 20.507535] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 20.507632] [drm:intel_power_well_enable] enabling dpio-common-a [ 20.509034] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 20.509037] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 20.509038] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 20.509040] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 20.509041] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 20.509042] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 20.509043] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 20.509044] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 20.509045] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 20.509046] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 20.509049] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 20.509051] [drm:verify_single_dpll_state] PORT PLL A [ 20.509053] [drm:verify_single_dpll_state] PORT PLL B [ 20.509057] [drm:verify_single_dpll_state] PORT PLL C [ 20.509067] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26 [ 20.509068] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 20.509097] [drm:edp_panel_on] Turn eDP port A panel power on [ 20.509098] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 20.624076] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000060 [ 20.640929] [drm:wait_panel_status] Wait complete [ 20.640932] [drm:wait_panel_on] Wait for panel power on [ 20.640935] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 20.667275] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 20.667279] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 20.667280] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 20.667304] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 20.697783] [drm:wait_panel_status] Wait complete [ 20.697790] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 20.697793] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 20.698527] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 20.698529] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 20.698771] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 20.699301] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 20.699346] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d5000 [ 20.699411] [drm:skl_wm_flush_pipe] flush pipe C (pass 1) [ 20.700761] [drm:skl_wm_flush_pipe] flush pipe B (pass 2) [ 20.701394] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 20.701397] [drm:intel_enable_pipe] enabling pipe A [ 20.701405] [drm:intel_edp_backlight_on] [ 20.701406] [drm:intel_panel_enable_backlight] pipe A [ 20.701408] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 20.701411] [drm:intel_psr_enable] PSR not supported on this platform [ 20.701412] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 20.701439] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 20.701440] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 20.701442] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.701463] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 20.701465] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 20.701467] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.705562] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 20.705568] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 20.705586] [drm:verify_single_dpll_state] PORT PLL A [ 20.709714] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 20.730252] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 20.734386] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 20.734391] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 20.734393] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 20.734408] [drm:intel_edp_backlight_off] [ 20.795088] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 20.795098] [drm:intel_disable_pipe] disabling pipe A [ 20.797196] [drm:edp_panel_off] Turn eDP port A panel power off [ 20.797200] [drm:wait_panel_off] Wait for panel power off time [ 20.797203] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 20.810142] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 20.810146] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 20.810147] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 20.810170] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 20.814109] [drm:wait_panel_status] Wait complete [ 20.814116] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26 [ 20.814125] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 20.814132] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 20.814133] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.814137] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 20.814140] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 20.814141] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 20.814142] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 20.814143] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 20.814144] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 20.814145] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 20.814146] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 20.814147] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 20.814148] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 20.814150] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 20.814153] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 20.814155] [drm:verify_single_dpll_state] PORT PLL A [ 20.814157] [drm:verify_single_dpll_state] PORT PLL B [ 20.814162] [drm:verify_single_dpll_state] PORT PLL C [ 20.814172] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 20.814173] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.814197] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 20.814199] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.814214] [drm:intel_power_well_disable] disabling dpio-common-a [ 20.814218] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 20.817940] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 20.820673] [drm:drm_mode_addfb2] [FB:107] [ 20.824139] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 20.824144] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 20.824152] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 20.824154] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 20.824156] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 20.824159] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 20.824160] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 20.824162] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 20.824164] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b6800 for pipe A [ 20.824165] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 20.824166] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 20.824168] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 20.824169] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 20.824171] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 20.824172] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 20.824173] [drm:intel_dump_pipe_config] requested mode: [ 20.824175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 20.824176] [drm:intel_dump_pipe_config] adjusted mode: [ 20.824178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 20.824180] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 20.824181] [drm:intel_dump_pipe_config] port clock: 162000 [ 20.824182] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 20.824183] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 20.824185] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 20.824186] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 20.824187] [drm:intel_dump_pipe_config] ips: 0 [ 20.824188] [drm:intel_dump_pipe_config] double wide: 0 [ 20.824190] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 20.824191] [drm:intel_dump_pipe_config] planes on this crtc [ 20.824192] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 20.824194] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 20.824195] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 20.824196] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 20.824198] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 20.824201] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 20.824203] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 20.824205] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B [ 20.824206] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A [ 20.824208] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 20.824209] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 20.824312] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B [ 20.824325] [drm:intel_disable_pipe] disabling pipe B [ 20.825938] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31 [ 20.825947] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 20.825951] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.825955] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 20.825956] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 20.825958] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 20.825959] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 20.825960] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 20.825961] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 20.825962] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 20.825963] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 20.825964] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 20.825965] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 20.825967] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 20.825969] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 20.825971] [drm:verify_single_dpll_state] PORT PLL A [ 20.825972] [drm:verify_single_dpll_state] PORT PLL B [ 20.825974] [drm:verify_single_dpll_state] PORT PLL C [ 20.825981] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26 [ 20.825982] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 20.826733] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 20.826734] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 20.828701] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 20.832029] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 20.832072] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b6800 [ 20.832127] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 20.832130] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.832131] [drm:intel_enable_pipe] enabling pipe A [ 20.832138] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 20.832140] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 20.832174] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 20.832176] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.836330] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 20.836334] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 20.836346] [drm:verify_single_dpll_state] PORT PLL B [ 20.836353] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 20.840460] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 20.860992] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 20.865084] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 20.865088] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 20.865090] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 20.865101] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 20.865114] [drm:intel_disable_pipe] disabling pipe A [ 20.869191] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26 [ 20.869197] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 20.869201] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.869204] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 20.869206] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 20.869207] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 20.869208] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 20.869209] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 20.869210] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 20.869211] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 20.869211] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 20.869212] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 20.869213] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 20.869214] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 20.869216] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 20.869217] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 20.869219] [drm:verify_single_dpll_state] PORT PLL A [ 20.869221] [drm:verify_single_dpll_state] PORT PLL B [ 20.869222] [drm:verify_single_dpll_state] PORT PLL C [ 20.869228] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.869231] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.869270] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 20.874482] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 20.877578] [drm:drm_mode_addfb2] [FB:107] [ 20.880799] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 20.880804] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 20.880811] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 20.880813] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 20.880815] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 20.880817] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 20.880818] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 20.880820] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 20.880822] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b2800 for pipe A [ 20.880823] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 20.880824] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 20.880825] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 20.880826] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 20.880828] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 20.880829] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 20.880830] [drm:intel_dump_pipe_config] requested mode: [ 20.880832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 20.880833] [drm:intel_dump_pipe_config] adjusted mode: [ 20.880834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 20.880836] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 20.880837] [drm:intel_dump_pipe_config] port clock: 162000 [ 20.880838] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 20.880839] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 20.880840] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 20.880841] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 20.880842] [drm:intel_dump_pipe_config] ips: 0 [ 20.880843] [drm:intel_dump_pipe_config] double wide: 0 [ 20.880845] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 20.880846] [drm:intel_dump_pipe_config] planes on this crtc [ 20.880847] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 20.880848] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 20.880849] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 20.880850] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 20.880852] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 20.880855] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 20.880857] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B [ 20.880858] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A [ 20.880860] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 20.880956] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 20.880958] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 20.880959] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 20.880960] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 20.880961] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 20.880962] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 20.880963] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 20.880964] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 20.880965] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 20.880966] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 20.880967] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 20.880969] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 20.880971] [drm:verify_single_dpll_state] PORT PLL A [ 20.880972] [drm:verify_single_dpll_state] PORT PLL B [ 20.880973] [drm:verify_single_dpll_state] PORT PLL C [ 20.880980] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26 [ 20.880981] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 20.881748] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 20.881749] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 20.882759] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 20.884464] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 20.884513] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b2800 [ 20.884573] [drm:skl_wm_flush_pipe] flush pipe C (pass 1) [ 20.885755] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 20.885760] [drm:intel_enable_pipe] enabling pipe A [ 20.885768] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 20.885770] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 20.885803] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 20.885806] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.885811] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 20.885814] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.889945] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 20.889950] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 20.889963] [drm:verify_single_dpll_state] PORT PLL B [ 20.894067] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 20.914632] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 20.918768] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 20.918773] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 20.918775] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 20.918788] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 20.918805] [drm:intel_disable_pipe] disabling pipe A [ 20.922958] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26 [ 20.922965] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 20.922970] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.922974] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 20.922975] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 20.922977] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 20.922978] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 20.922979] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 20.922980] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 20.922982] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 20.922983] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 20.922984] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 20.922985] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 20.922986] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 20.922988] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 20.922990] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 20.922992] [drm:verify_single_dpll_state] PORT PLL A [ 20.922993] [drm:verify_single_dpll_state] PORT PLL B [ 20.922995] [drm:verify_single_dpll_state] PORT PLL C [ 20.923002] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.923006] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 20.923028] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 20.928195] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 20.931014] [drm:drm_mode_addfb2] [FB:107] [ 20.934476] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 20.934480] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 20.934489] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 20.934491] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 20.934493] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 20.934496] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 20.934497] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 20.934499] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 20.934501] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d1800 for pipe A [ 20.934502] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 20.934503] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 20.934504] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 20.934506] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 20.934508] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 20.934509] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 20.934510] [drm:intel_dump_pipe_config] requested mode: [ 20.934512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 20.934513] [drm:intel_dump_pipe_config] adjusted mode: [ 20.934515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 20.934517] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 20.934518] [drm:intel_dump_pipe_config] port clock: 162000 [ 20.934519] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 20.934520] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 20.934522] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 20.934523] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 20.934524] [drm:intel_dump_pipe_config] ips: 0 [ 20.934525] [drm:intel_dump_pipe_config] double wide: 0 [ 20.934527] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 20.934528] [drm:intel_dump_pipe_config] planes on this crtc [ 20.934529] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 20.934531] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 20.934532] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 20.934533] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 20.934535] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 20.934538] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 20.934540] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 20.934542] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C [ 20.934543] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A [ 20.934545] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 20.934546] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 20.934651] [drm:intel_disable_pipe] disabling pipe C [ 20.938236] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36 [ 20.938242] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 20.938248] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 20.938250] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 20.938252] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 20.938253] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 20.938254] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 20.938255] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 20.938256] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 20.938257] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 20.938258] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 20.938260] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 20.938261] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 20.938263] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 20.938264] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 20.938266] [drm:verify_single_dpll_state] PORT PLL A [ 20.938267] [drm:verify_single_dpll_state] PORT PLL B [ 20.938269] [drm:verify_single_dpll_state] PORT PLL C [ 20.938272] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26 [ 20.938274] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 20.939025] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 20.939027] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 20.939373] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 20.939913] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 20.939914] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 20.941827] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 20.941964] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d1800 [ 20.942018] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 20.942020] [drm:intel_enable_pipe] enabling pipe A [ 20.942047] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 20.946175] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 20.946178] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 20.946190] [drm:verify_single_dpll_state] PORT PLL C [ 20.946196] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 20.950362] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 20.970898] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 20.975030] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 20.975034] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 20.975037] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 20.975052] [drm:intel_disable_pipe] disabling pipe A [ 20.980943] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26 [ 20.980949] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 20.980954] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 20.984819] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 20.984823] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 20.984826] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 20.984828] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 20.984829] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 20.984830] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 20.984831] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 20.984833] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 20.984834] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 20.984835] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 20.984836] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 20.984838] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 20.984839] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 20.984841] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 20.984843] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 20.984844] [drm:verify_single_dpll_state] PORT PLL A [ 20.984846] [drm:verify_single_dpll_state] PORT PLL B [ 20.984847] [drm:verify_single_dpll_state] PORT PLL C [ 20.984853] [drm:intel_power_well_disable] disabling dpio-common-bc [ 20.984855] [drm:intel_power_well_disable] disabling power well 2 [ 20.984859] [drm:skl_set_power_well] Disabling power well 2 [ 20.984862] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 20.984865] [drm:intel_power_well_disable] disabling DC off [ 20.984867] [drm:gen9_enable_dc5] Enabling DC5 [ 20.984868] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 20.984871] [drm:intel_power_well_disable] disabling always-on [ 20.986282] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 20.986382] [drm:drm_mode_addfb2] [FB:107] [ 20.989804] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 20.989809] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 20.989817] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 20.989818] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 20.989820] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 20.989822] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 20.989823] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 20.989825] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 20.989827] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d1800 for pipe A [ 20.989828] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 20.989829] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 20.989830] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 20.989832] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 20.989833] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 20.989834] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 20.989835] [drm:intel_dump_pipe_config] requested mode: [ 20.989837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 20.989838] [drm:intel_dump_pipe_config] adjusted mode: [ 20.989839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 20.989841] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 20.989842] [drm:intel_dump_pipe_config] port clock: 162000 [ 20.989843] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 20.989844] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 20.989845] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 20.989847] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 20.989847] [drm:intel_dump_pipe_config] ips: 0 [ 20.989848] [drm:intel_dump_pipe_config] double wide: 0 [ 20.989850] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 20.989851] [drm:intel_dump_pipe_config] planes on this crtc [ 20.989852] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 20.989853] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 20.989854] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 20.989856] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 20.989858] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 20.989860] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 20.989863] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C [ 20.989864] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A [ 20.989866] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 20.989954] [drm:intel_power_well_enable] enabling always-on [ 20.989956] [drm:intel_power_well_enable] enabling DC off [ 20.990019] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 20.990022] [drm:intel_power_well_enable] enabling power well 2 [ 20.990024] [drm:skl_set_power_well] Enabling power well 2 [ 20.990028] [drm:intel_power_well_enable] enabling dpio-common-bc [ 20.990029] [drm:intel_power_well_enable] enabling dpio-common-a [ 20.990914] [drm:intel_power_well_disable] disabling dpio-common-a [ 20.990923] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 20.994318] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 20.994321] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 20.994324] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 20.994326] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 20.994327] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 20.994328] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 20.994329] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 20.994330] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 20.994331] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 20.994332] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 20.994333] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 20.994335] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 20.994336] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 20.994338] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 20.994339] [drm:verify_single_dpll_state] PORT PLL A [ 20.994341] [drm:verify_single_dpll_state] PORT PLL B [ 20.994342] [drm:verify_single_dpll_state] PORT PLL C [ 20.994348] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26 [ 20.994349] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 20.995097] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 20.995098] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 20.998253] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 20.998793] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 20.998794] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 21.001345] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 21.001389] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d1800 [ 21.001444] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.001445] [drm:intel_enable_pipe] enabling pipe A [ 21.001475] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.001480] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.005602] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.005606] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.005620] [drm:verify_single_dpll_state] PORT PLL C [ 21.009756] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 21.030283] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 21.034417] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 21.034422] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.034424] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.034440] [drm:intel_disable_pipe] disabling pipe A [ 21.039341] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26 [ 21.039349] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 21.039353] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 21.042163] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 21.042167] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.042170] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.042172] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.042173] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.042174] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.042175] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.042177] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.042178] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.042179] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.042181] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.042182] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.042184] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.042185] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.042187] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.042189] [drm:verify_single_dpll_state] PORT PLL A [ 21.042190] [drm:verify_single_dpll_state] PORT PLL B [ 21.042191] [drm:verify_single_dpll_state] PORT PLL C [ 21.042197] [drm:intel_power_well_disable] disabling dpio-common-bc [ 21.042199] [drm:intel_power_well_disable] disabling power well 2 [ 21.042203] [drm:skl_set_power_well] Disabling power well 2 [ 21.042206] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.042209] [drm:intel_power_well_disable] disabling DC off [ 21.042211] [drm:gen9_enable_dc5] Enabling DC5 [ 21.042212] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 21.042214] [drm:intel_power_well_disable] disabling always-on [ 21.043515] kms_pipe_crc_basic: starting subtest read-crc-pipe-A-frame-sequence [ 21.043732] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.043831] [drm:drm_mode_addfb2] [FB:107] [ 21.047145] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.047150] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 21.047174] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 21.047175] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 21.047178] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.047179] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 21.047183] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 21.047184] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 21.047185] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 21.047190] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b1000 for pipe A [ 21.047193] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 21.047197] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 21.047199] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 21.047200] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 21.047202] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 21.047203] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 21.047204] [drm:intel_dump_pipe_config] requested mode: [ 21.047206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 21.047207] [drm:intel_dump_pipe_config] adjusted mode: [ 21.047208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 21.047210] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 21.047211] [drm:intel_dump_pipe_config] port clock: 270000 [ 21.047212] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 21.047215] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 21.047216] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 21.047217] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 21.047218] [drm:intel_dump_pipe_config] ips: 0 [ 21.047219] [drm:intel_dump_pipe_config] double wide: 0 [ 21.047221] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 21.047222] [drm:intel_dump_pipe_config] planes on this crtc [ 21.047223] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 21.047224] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 21.047225] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 21.047226] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 21.047228] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 21.047231] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.047233] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A [ 21.047234] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A [ 21.047235] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.047325] [drm:intel_power_well_enable] enabling always-on [ 21.047327] [drm:intel_power_well_enable] enabling DC off [ 21.047390] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 21.047394] [drm:intel_power_well_enable] enabling dpio-common-a [ 21.048942] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.048945] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.048947] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.048948] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.048949] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.048950] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.048951] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.048952] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.048953] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.048954] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.048956] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.048957] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.048958] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.048959] [drm:verify_single_dpll_state] PORT PLL A [ 21.048960] [drm:verify_single_dpll_state] PORT PLL B [ 21.048962] [drm:verify_single_dpll_state] PORT PLL C [ 21.048969] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26 [ 21.048970] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 21.048999] [drm:edp_panel_on] Turn eDP port A panel power on [ 21.049001] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 21.049004] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 21.049005] [drm:wait_panel_status] Wait complete [ 21.049007] [drm:wait_panel_on] Wait for panel power on [ 21.049008] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 21.082355] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 21.082358] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 21.082360] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 21.082406] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 21.102276] [drm:wait_panel_status] Wait complete [ 21.102304] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 21.102307] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 21.103039] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 21.103040] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 21.103284] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 21.103811] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 21.103852] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b1000 [ 21.103915] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.103917] [drm:intel_enable_pipe] enabling pipe A [ 21.103929] [drm:intel_edp_backlight_on] [ 21.103930] [drm:intel_panel_enable_backlight] pipe A [ 21.103932] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 21.103934] [drm:intel_psr_enable] PSR not supported on this platform [ 21.103935] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 21.103957] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.103962] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.108068] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.108072] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.108087] [drm:verify_single_dpll_state] PORT PLL A [ 21.112253] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 21.132781] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 21.136915] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 21.136919] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.136922] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.136933] [drm:intel_edp_backlight_off] [ 21.244983] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 21.244992] [drm:intel_disable_pipe] disabling pipe A [ 21.249092] [drm:edp_panel_off] Turn eDP port A panel power off [ 21.249097] [drm:wait_panel_off] Wait for panel power off time [ 21.249100] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000060 [ 21.261827] [drm:wait_panel_status] Wait complete [ 21.261834] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26 [ 21.261840] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 21.261845] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.261847] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.261849] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.261850] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.261851] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.261852] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.261853] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.261854] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.261855] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.261856] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.261858] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.261860] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.261861] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.261862] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.261863] [drm:verify_single_dpll_state] PORT PLL A [ 21.261865] [drm:verify_single_dpll_state] PORT PLL B [ 21.261866] [drm:verify_single_dpll_state] PORT PLL C [ 21.261870] [drm:intel_power_well_disable] disabling dpio-common-a [ 21.261873] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.261876] [drm:intel_power_well_disable] disabling DC off [ 21.261878] [drm:gen9_enable_dc5] Enabling DC5 [ 21.261880] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 21.261882] [drm:intel_power_well_disable] disabling always-on [ 21.262009] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 21.262011] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 21.262012] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 21.262054] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 21.263291] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.263391] [drm:drm_mode_addfb2] [FB:107] [ 21.266832] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.266836] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 21.266844] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 21.266846] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 21.266849] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.266850] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 21.266854] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 21.266855] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 21.266857] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 21.266859] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b6000 for pipe A [ 21.266860] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 21.266861] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 21.266862] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 21.266864] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 21.266866] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 21.266867] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 21.266868] [drm:intel_dump_pipe_config] requested mode: [ 21.266870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 21.266871] [drm:intel_dump_pipe_config] adjusted mode: [ 21.266873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 21.266875] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 21.266876] [drm:intel_dump_pipe_config] port clock: 270000 [ 21.266877] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 21.266878] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 21.266880] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 21.266881] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 21.266882] [drm:intel_dump_pipe_config] ips: 0 [ 21.266883] [drm:intel_dump_pipe_config] double wide: 0 [ 21.266885] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 21.266886] [drm:intel_dump_pipe_config] planes on this crtc [ 21.266887] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 21.266888] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 21.266890] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 21.266891] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 21.266893] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 21.266895] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.266898] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A [ 21.266899] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A [ 21.266901] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.266993] [drm:intel_power_well_enable] enabling always-on [ 21.266995] [drm:intel_power_well_enable] enabling DC off [ 21.267070] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 21.267074] [drm:intel_power_well_enable] enabling dpio-common-a [ 21.268477] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.268481] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.268483] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.268484] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.268485] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.268492] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.268494] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.268495] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.268496] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.268497] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.268499] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.268501] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.268503] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.268504] [drm:verify_single_dpll_state] PORT PLL A [ 21.268506] [drm:verify_single_dpll_state] PORT PLL B [ 21.268507] [drm:verify_single_dpll_state] PORT PLL C [ 21.268514] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26 [ 21.268515] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 21.268548] [drm:edp_panel_on] Turn eDP port A panel power on [ 21.268549] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 21.379199] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000060 [ 21.410328] [drm:wait_panel_status] Wait complete [ 21.410332] [drm:wait_panel_on] Wait for panel power on [ 21.410334] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 21.440618] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 21.440622] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 21.440623] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 21.440635] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 21.468682] [drm:wait_panel_status] Wait complete [ 21.468689] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 21.468692] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 21.469425] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 21.469426] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 21.469661] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 21.470187] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 21.470227] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b6000 [ 21.470291] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.470293] [drm:intel_enable_pipe] enabling pipe A [ 21.470304] [drm:intel_edp_backlight_on] [ 21.470305] [drm:intel_panel_enable_backlight] pipe A [ 21.470307] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 21.472609] [drm:intel_psr_enable] PSR not supported on this platform [ 21.472612] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 21.472643] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.472649] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.474453] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.474457] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.474473] [drm:verify_single_dpll_state] PORT PLL A [ 21.478615] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 21.499144] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 21.503276] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 21.503281] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.503283] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.503295] [drm:intel_edp_backlight_off] [ 21.555851] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 21.555861] [drm:intel_disable_pipe] disabling pipe A [ 21.557990] [drm:edp_panel_off] Turn eDP port A panel power off [ 21.557994] [drm:wait_panel_off] Wait for panel power off time [ 21.557996] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 21.572206] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 21.572210] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 21.572211] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 21.572219] [drm:wait_panel_status] Wait complete [ 21.572225] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26 [ 21.572230] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 21.572244] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 21.572249] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.572251] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.572253] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.572254] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.572255] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.572256] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.572257] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.572258] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.572259] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.572260] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.572262] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.572263] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.572265] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.572266] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.572267] [drm:verify_single_dpll_state] PORT PLL A [ 21.572269] [drm:verify_single_dpll_state] PORT PLL B [ 21.572270] [drm:verify_single_dpll_state] PORT PLL C [ 21.572274] [drm:intel_power_well_disable] disabling dpio-common-a [ 21.572277] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.572281] [drm:intel_power_well_disable] disabling DC off [ 21.572283] [drm:gen9_enable_dc5] Enabling DC5 [ 21.572284] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 21.572286] [drm:intel_power_well_disable] disabling always-on [ 21.573705] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.573806] [drm:drm_mode_addfb2] [FB:107] [ 21.577181] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.577186] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 21.577194] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 21.577195] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 21.577197] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 21.577200] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 21.577201] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 21.577203] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 21.577205] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d4800 for pipe A [ 21.577206] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 21.577207] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 21.577209] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 21.577210] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 21.577212] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 21.577213] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 21.577214] [drm:intel_dump_pipe_config] requested mode: [ 21.577216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 21.577217] [drm:intel_dump_pipe_config] adjusted mode: [ 21.577219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 21.577221] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 21.577222] [drm:intel_dump_pipe_config] port clock: 162000 [ 21.577223] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 21.577225] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 21.577226] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 21.577227] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 21.577228] [drm:intel_dump_pipe_config] ips: 0 [ 21.577229] [drm:intel_dump_pipe_config] double wide: 0 [ 21.577231] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 21.577232] [drm:intel_dump_pipe_config] planes on this crtc [ 21.577234] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 21.577235] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 21.577236] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 21.577237] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 21.577240] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 21.577243] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.577245] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B [ 21.577247] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A [ 21.577248] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.577340] [drm:intel_power_well_enable] enabling always-on [ 21.577342] [drm:intel_power_well_enable] enabling DC off [ 21.577405] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 21.577409] [drm:intel_power_well_enable] enabling power well 2 [ 21.577410] [drm:skl_set_power_well] Enabling power well 2 [ 21.577414] [drm:intel_power_well_enable] enabling dpio-common-bc [ 21.577415] [drm:intel_power_well_enable] enabling dpio-common-a [ 21.582640] [drm:intel_power_well_disable] disabling dpio-common-a [ 21.582647] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 21.586591] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 21.586594] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.586597] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.586599] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.586600] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.586601] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.586602] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.586603] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.586604] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.586605] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.586606] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.586608] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.586609] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.586611] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.586612] [drm:verify_single_dpll_state] PORT PLL A [ 21.586614] [drm:verify_single_dpll_state] PORT PLL B [ 21.586615] [drm:verify_single_dpll_state] PORT PLL C [ 21.586621] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26 [ 21.586622] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 21.588638] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 21.588640] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 21.589671] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 21.593044] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 21.593095] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d4800 [ 21.593149] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.593152] [drm:intel_enable_pipe] enabling pipe A [ 21.593164] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 21.593166] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 21.593196] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.593202] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.597309] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.597314] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.597330] [drm:verify_single_dpll_state] PORT PLL B [ 21.601481] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 21.622019] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 21.626146] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 21.626150] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.626153] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.626164] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 21.626179] [drm:intel_disable_pipe] disabling pipe A [ 21.631875] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26 [ 21.631884] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 21.631889] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 21.635463] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 21.635466] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.635470] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.635471] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.635473] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.635474] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.635475] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.635477] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.635478] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.635479] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.635480] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.635481] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.635483] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.635485] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.635486] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.635488] [drm:verify_single_dpll_state] PORT PLL A [ 21.635490] [drm:verify_single_dpll_state] PORT PLL B [ 21.635491] [drm:verify_single_dpll_state] PORT PLL C [ 21.635496] [drm:intel_power_well_disable] disabling dpio-common-bc [ 21.635498] [drm:intel_power_well_disable] disabling power well 2 [ 21.635502] [drm:skl_set_power_well] Disabling power well 2 [ 21.635505] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.635508] [drm:intel_power_well_disable] disabling DC off [ 21.635510] [drm:gen9_enable_dc5] Enabling DC5 [ 21.635512] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 21.635514] [drm:intel_power_well_disable] disabling always-on [ 21.636914] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.637015] [drm:drm_mode_addfb2] [FB:107] [ 21.640331] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.640335] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 21.640343] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 21.640344] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 21.640347] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 21.640349] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 21.640350] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 21.640352] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 21.640353] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b4000 for pipe A [ 21.640355] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 21.640355] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 21.640357] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 21.640358] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 21.640360] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 21.640361] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 21.640361] [drm:intel_dump_pipe_config] requested mode: [ 21.640363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 21.640364] [drm:intel_dump_pipe_config] adjusted mode: [ 21.640366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 21.640368] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 21.640369] [drm:intel_dump_pipe_config] port clock: 162000 [ 21.640370] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 21.640371] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 21.640372] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 21.640373] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 21.640374] [drm:intel_dump_pipe_config] ips: 0 [ 21.640375] [drm:intel_dump_pipe_config] double wide: 0 [ 21.640377] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 21.640378] [drm:intel_dump_pipe_config] planes on this crtc [ 21.640379] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 21.640380] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 21.640382] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 21.640383] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 21.640385] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 21.640387] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.640390] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B [ 21.640391] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A [ 21.640393] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.640481] [drm:intel_power_well_enable] enabling always-on [ 21.640483] [drm:intel_power_well_enable] enabling DC off [ 21.640546] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 21.640549] [drm:intel_power_well_enable] enabling power well 2 [ 21.640550] [drm:skl_set_power_well] Enabling power well 2 [ 21.640554] [drm:intel_power_well_enable] enabling dpio-common-bc [ 21.640555] [drm:intel_power_well_enable] enabling dpio-common-a [ 21.643401] [drm:intel_power_well_disable] disabling dpio-common-a [ 21.643409] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 21.647527] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 21.647530] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.647533] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.647534] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.647535] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.647536] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.647537] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.647539] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.647540] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.647541] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.647542] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.647543] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.647545] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.647546] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.647548] [drm:verify_single_dpll_state] PORT PLL A [ 21.647549] [drm:verify_single_dpll_state] PORT PLL B [ 21.647550] [drm:verify_single_dpll_state] PORT PLL C [ 21.647556] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26 [ 21.647557] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 21.648306] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 21.648307] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 21.650571] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 21.653891] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 21.653942] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b4000 [ 21.653996] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.653999] [drm:intel_enable_pipe] enabling pipe A [ 21.654021] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 21.654023] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 21.654057] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.654063] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.658158] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.658162] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.658177] [drm:verify_single_dpll_state] PORT PLL B [ 21.662290] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 21.682872] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 21.686996] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 21.687000] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.687003] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.687013] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 21.687028] [drm:intel_disable_pipe] disabling pipe A [ 21.691197] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26 [ 21.691205] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 21.691209] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 21.694857] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 21.694861] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.694863] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.694865] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.694866] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.694867] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.694868] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.694870] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.694871] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.694872] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.694873] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.694874] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.694876] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.694877] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.694879] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.694880] [drm:verify_single_dpll_state] PORT PLL A [ 21.694882] [drm:verify_single_dpll_state] PORT PLL B [ 21.694883] [drm:verify_single_dpll_state] PORT PLL C [ 21.694888] [drm:intel_power_well_disable] disabling dpio-common-bc [ 21.694890] [drm:intel_power_well_disable] disabling power well 2 [ 21.694893] [drm:skl_set_power_well] Disabling power well 2 [ 21.694897] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.694899] [drm:intel_power_well_disable] disabling DC off [ 21.694901] [drm:gen9_enable_dc5] Enabling DC5 [ 21.694903] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 21.694904] [drm:intel_power_well_disable] disabling always-on [ 21.696243] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.696341] [drm:drm_mode_addfb2] [FB:107] [ 21.699506] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.699510] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 21.699517] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 21.699519] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 21.699521] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 21.699523] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 21.699524] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 21.699526] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 21.699527] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b6000 for pipe A [ 21.699529] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 21.699529] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 21.699531] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 21.699532] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 21.699534] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 21.699535] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 21.699535] [drm:intel_dump_pipe_config] requested mode: [ 21.699537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 21.699538] [drm:intel_dump_pipe_config] adjusted mode: [ 21.699540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 21.699542] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 21.699543] [drm:intel_dump_pipe_config] port clock: 162000 [ 21.699544] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 21.699545] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 21.699546] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 21.699547] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 21.699548] [drm:intel_dump_pipe_config] ips: 0 [ 21.699549] [drm:intel_dump_pipe_config] double wide: 0 [ 21.699551] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 21.699552] [drm:intel_dump_pipe_config] planes on this crtc [ 21.699553] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 21.699554] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 21.699555] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 21.699556] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 21.699559] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 21.699561] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.699563] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C [ 21.699565] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A [ 21.699566] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.699655] [drm:intel_power_well_enable] enabling always-on [ 21.699656] [drm:intel_power_well_enable] enabling DC off [ 21.699719] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 21.699722] [drm:intel_power_well_enable] enabling power well 2 [ 21.699724] [drm:skl_set_power_well] Enabling power well 2 [ 21.699728] [drm:intel_power_well_enable] enabling dpio-common-bc [ 21.699729] [drm:intel_power_well_enable] enabling dpio-common-a [ 21.702758] [drm:intel_power_well_disable] disabling dpio-common-a [ 21.702765] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 21.706899] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 21.706903] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.706905] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.706907] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.706908] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.706909] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.706910] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.706911] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.706912] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.706913] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.706914] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.706916] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.706917] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.706919] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.706920] [drm:verify_single_dpll_state] PORT PLL A [ 21.706922] [drm:verify_single_dpll_state] PORT PLL B [ 21.706923] [drm:verify_single_dpll_state] PORT PLL C [ 21.706929] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26 [ 21.706930] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 21.707678] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 21.707679] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 21.709209] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 21.709771] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 21.709772] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 21.712049] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 21.712094] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b6000 [ 21.712149] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.712151] [drm:intel_enable_pipe] enabling pipe A [ 21.712187] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.712192] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.716314] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.716318] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.716333] [drm:verify_single_dpll_state] PORT PLL C [ 21.720468] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 21.741018] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 21.745155] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 21.745160] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.745162] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.745177] [drm:intel_disable_pipe] disabling pipe A [ 21.749352] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26 [ 21.749359] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 21.749364] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 21.753290] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 21.753294] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.753297] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.753299] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.753300] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.753301] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.753303] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.753304] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.753305] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.753306] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.753308] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.753309] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.753311] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.753312] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.753314] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.753316] [drm:verify_single_dpll_state] PORT PLL A [ 21.753317] [drm:verify_single_dpll_state] PORT PLL B [ 21.753319] [drm:verify_single_dpll_state] PORT PLL C [ 21.753324] [drm:intel_power_well_disable] disabling dpio-common-bc [ 21.753326] [drm:intel_power_well_disable] disabling power well 2 [ 21.753330] [drm:skl_set_power_well] Disabling power well 2 [ 21.753333] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.753336] [drm:intel_power_well_disable] disabling DC off [ 21.753338] [drm:gen9_enable_dc5] Enabling DC5 [ 21.753339] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 21.753342] [drm:intel_power_well_disable] disabling always-on [ 21.754759] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.754858] [drm:drm_mode_addfb2] [FB:107] [ 21.758280] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.758285] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 21.758293] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 21.758294] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 21.758297] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 21.758299] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 21.758300] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 21.758302] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 21.758304] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d4800 for pipe A [ 21.758305] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 21.758306] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 21.758308] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 21.758309] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 21.758311] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 21.758312] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 21.758313] [drm:intel_dump_pipe_config] requested mode: [ 21.758315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 21.758316] [drm:intel_dump_pipe_config] adjusted mode: [ 21.758318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 21.758320] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 21.758321] [drm:intel_dump_pipe_config] port clock: 162000 [ 21.758322] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 21.758324] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 21.758325] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 21.758326] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 21.758327] [drm:intel_dump_pipe_config] ips: 0 [ 21.758328] [drm:intel_dump_pipe_config] double wide: 0 [ 21.758330] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 21.758331] [drm:intel_dump_pipe_config] planes on this crtc [ 21.758333] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 21.758334] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 21.758335] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 21.758336] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 21.758339] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 21.758342] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.758345] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C [ 21.758346] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A [ 21.758348] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.758439] [drm:intel_power_well_enable] enabling always-on [ 21.758441] [drm:intel_power_well_enable] enabling DC off [ 21.758504] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 21.758507] [drm:intel_power_well_enable] enabling power well 2 [ 21.758509] [drm:skl_set_power_well] Enabling power well 2 [ 21.758513] [drm:intel_power_well_enable] enabling dpio-common-bc [ 21.758514] [drm:intel_power_well_enable] enabling dpio-common-a [ 21.760455] [drm:intel_power_well_disable] disabling dpio-common-a [ 21.760463] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 21.763251] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 21.763255] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.763258] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.763260] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.763261] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.763262] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.763264] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.763265] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.763266] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.763267] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.763268] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.763270] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.763271] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.763273] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.763275] [drm:verify_single_dpll_state] PORT PLL A [ 21.763276] [drm:verify_single_dpll_state] PORT PLL B [ 21.763278] [drm:verify_single_dpll_state] PORT PLL C [ 21.763285] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26 [ 21.763286] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 21.764040] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 21.764041] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 21.764280] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 21.764281] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 21.764513] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 21.765065] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 21.765067] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 21.767067] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 21.767111] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d4800 [ 21.767168] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.767171] [drm:intel_enable_pipe] enabling pipe A [ 21.767209] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.767214] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.771324] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.771327] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.771341] [drm:verify_single_dpll_state] PORT PLL C [ 21.775504] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 21.796034] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 21.800168] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 21.800173] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.800175] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.800190] [drm:intel_disable_pipe] disabling pipe A [ 21.804371] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26 [ 21.804379] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 21.804384] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 21.808508] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 21.808512] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.808515] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.808517] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.808518] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.808519] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.808520] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.808522] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.808523] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.808524] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.808526] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.808527] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.808529] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.808530] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.808532] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.808534] [drm:verify_single_dpll_state] PORT PLL A [ 21.808535] [drm:verify_single_dpll_state] PORT PLL B [ 21.808537] [drm:verify_single_dpll_state] PORT PLL C [ 21.808542] [drm:intel_power_well_disable] disabling dpio-common-bc [ 21.808544] [drm:intel_power_well_disable] disabling power well 2 [ 21.808548] [drm:skl_set_power_well] Disabling power well 2 [ 21.808551] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.808553] [drm:intel_power_well_disable] disabling DC off [ 21.808555] [drm:gen9_enable_dc5] Enabling DC5 [ 21.808557] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 21.808559] [drm:intel_power_well_disable] disabling always-on [ 21.809853] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A [ 21.810074] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.810172] [drm:drm_mode_addfb2] [FB:107] [ 21.813514] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.813518] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 21.813526] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 21.813527] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 21.813530] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.813531] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 21.813534] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 21.813536] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 21.813537] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 21.813539] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b4000 for pipe A [ 21.813540] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 21.813541] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 21.813542] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 21.813544] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 21.813545] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 21.813546] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 21.813547] [drm:intel_dump_pipe_config] requested mode: [ 21.813549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 21.813550] [drm:intel_dump_pipe_config] adjusted mode: [ 21.813552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 21.813553] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 21.813554] [drm:intel_dump_pipe_config] port clock: 270000 [ 21.813555] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 21.813556] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 21.813558] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 21.813559] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 21.813560] [drm:intel_dump_pipe_config] ips: 0 [ 21.813560] [drm:intel_dump_pipe_config] double wide: 0 [ 21.813562] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 21.813564] [drm:intel_dump_pipe_config] planes on this crtc [ 21.813565] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 21.813566] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 21.813567] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 21.813568] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 21.813570] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 21.813572] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.813574] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A [ 21.813576] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A [ 21.813577] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.813666] [drm:intel_power_well_enable] enabling always-on [ 21.813667] [drm:intel_power_well_enable] enabling DC off [ 21.813730] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 21.813734] [drm:intel_power_well_enable] enabling dpio-common-a [ 21.817091] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.817094] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.817096] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.817097] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.817098] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.817099] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.817100] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.817101] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.817102] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.817103] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.817104] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.817106] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.817107] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.817108] [drm:verify_single_dpll_state] PORT PLL A [ 21.817109] [drm:verify_single_dpll_state] PORT PLL B [ 21.817111] [drm:verify_single_dpll_state] PORT PLL C [ 21.817118] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26 [ 21.817119] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 21.817148] [drm:edp_panel_on] Turn eDP port A panel power on [ 21.817150] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 21.817153] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 21.817154] [drm:wait_panel_status] Wait complete [ 21.817155] [drm:wait_panel_on] Wait for panel power on [ 21.817157] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 00000063 [ 21.843475] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 21.843478] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 21.843480] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 21.843501] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 21.867523] [drm:wait_panel_status] Wait complete [ 21.867530] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 21.867532] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 21.868255] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 21.868256] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 21.868482] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 21.869004] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 21.869044] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b4000 [ 21.869107] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.869110] [drm:intel_enable_pipe] enabling pipe A [ 21.869121] [drm:intel_edp_backlight_on] [ 21.869122] [drm:intel_panel_enable_backlight] pipe A [ 21.869124] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 21.870057] [drm:intel_psr_enable] PSR not supported on this platform [ 21.870062] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 21.870090] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.870095] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 21.873271] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.873276] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.873292] [drm:verify_single_dpll_state] PORT PLL A [ 21.877433] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 21.897992] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 21.902098] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 21.902103] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.902105] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.902117] [drm:intel_edp_backlight_off] [ 21.978915] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 21.978926] [drm:intel_disable_pipe] disabling pipe A [ 21.981063] [drm:edp_panel_off] Turn eDP port A panel power off [ 21.981067] [drm:wait_panel_off] Wait for panel power off time [ 21.981070] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 21.994009] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 21.994012] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 21.994014] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 21.994022] [drm:wait_panel_status] Wait complete [ 21.994028] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26 [ 21.994035] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 21.994036] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 21.994039] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.994043] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.994047] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.994050] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.994051] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.994052] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.994053] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.994054] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.994055] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.994056] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 21.994058] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.994059] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.994061] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.994062] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.994063] [drm:verify_single_dpll_state] PORT PLL A [ 21.994065] [drm:verify_single_dpll_state] PORT PLL B [ 21.994066] [drm:verify_single_dpll_state] PORT PLL C [ 21.994070] [drm:intel_power_well_disable] disabling dpio-common-a [ 21.994073] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 21.994076] [drm:intel_power_well_disable] disabling DC off [ 21.994078] [drm:gen9_enable_dc5] Enabling DC5 [ 21.994079] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 21.994083] [drm:intel_power_well_disable] disabling always-on [ 21.995487] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.995602] [drm:drm_mode_addfb2] [FB:107] [ 21.999000] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 21.999005] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 21.999013] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 21.999014] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 21.999017] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.999019] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 21.999022] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 21.999023] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 21.999025] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 21.999027] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b2800 for pipe A [ 21.999028] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 21.999029] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 21.999031] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 21.999032] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 21.999034] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 21.999035] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 21.999036] [drm:intel_dump_pipe_config] requested mode: [ 21.999038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 21.999039] [drm:intel_dump_pipe_config] adjusted mode: [ 21.999041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 21.999043] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 21.999044] [drm:intel_dump_pipe_config] port clock: 270000 [ 21.999045] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 21.999047] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 21.999048] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 21.999049] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 21.999050] [drm:intel_dump_pipe_config] ips: 0 [ 21.999051] [drm:intel_dump_pipe_config] double wide: 0 [ 21.999053] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 21.999054] [drm:intel_dump_pipe_config] planes on this crtc [ 21.999056] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 21.999057] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 21.999058] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 21.999059] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 21.999061] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 21.999064] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 21.999066] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A [ 21.999068] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A [ 21.999069] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 21.999162] [drm:intel_power_well_enable] enabling always-on [ 21.999164] [drm:intel_power_well_enable] enabling DC off [ 21.999227] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 21.999231] [drm:intel_power_well_enable] enabling dpio-common-a [ 21.999670] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 21.999672] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 21.999674] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 21.999675] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 21.999676] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 21.999677] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 21.999678] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 21.999679] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 21.999680] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 21.999682] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 21.999683] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 21.999684] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 21.999686] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 21.999688] [drm:verify_single_dpll_state] PORT PLL A [ 21.999689] [drm:verify_single_dpll_state] PORT PLL B [ 21.999691] [drm:verify_single_dpll_state] PORT PLL C [ 21.999696] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26 [ 21.999698] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 21.999726] [drm:edp_panel_on] Turn eDP port A panel power on [ 21.999729] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 22.136747] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 22.136750] [drm:wait_panel_status] Wait complete [ 22.136751] [drm:wait_panel_on] Wait for panel power on [ 22.136754] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 22.166601] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 22.166604] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 22.166606] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 22.166628] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 22.196703] [drm:wait_panel_status] Wait complete [ 22.196710] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 22.196713] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 22.197446] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 22.197447] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 22.197681] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 22.198215] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 22.198256] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b2800 [ 22.198320] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.198322] [drm:intel_enable_pipe] enabling pipe A [ 22.198333] [drm:intel_edp_backlight_on] [ 22.198334] [drm:intel_panel_enable_backlight] pipe A [ 22.198336] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 22.200484] [drm:intel_psr_enable] PSR not supported on this platform [ 22.200486] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 22.200511] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.200517] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.202477] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 22.202481] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 22.202496] [drm:verify_single_dpll_state] PORT PLL A [ 22.206644] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 22.227238] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 22.231286] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 22.231290] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 22.231293] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.231304] [drm:intel_edp_backlight_off] [ 22.283700] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 22.283709] [drm:intel_disable_pipe] disabling pipe A [ 22.285801] [drm:edp_panel_off] Turn eDP port A panel power off [ 22.285806] [drm:wait_panel_off] Wait for panel power off time [ 22.285809] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 22.299644] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 22.299647] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 22.299649] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 22.299684] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 22.302212] [drm:wait_panel_status] Wait complete [ 22.302219] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26 [ 22.302226] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 22.302231] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 22.302233] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 22.302234] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 22.302235] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 22.302236] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 22.302238] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 22.302239] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 22.302240] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 22.302241] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 22.302242] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 22.302244] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 22.302245] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 22.302246] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 22.302248] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 22.302249] [drm:verify_single_dpll_state] PORT PLL A [ 22.302250] [drm:verify_single_dpll_state] PORT PLL B [ 22.302252] [drm:verify_single_dpll_state] PORT PLL C [ 22.302256] [drm:intel_power_well_disable] disabling dpio-common-a [ 22.302259] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 22.302262] [drm:intel_power_well_disable] disabling DC off [ 22.302264] [drm:gen9_enable_dc5] Enabling DC5 [ 22.302265] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 22.302268] [drm:intel_power_well_disable] disabling always-on [ 22.303678] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 22.303779] [drm:drm_mode_addfb2] [FB:107] [ 22.307179] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 22.307184] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 22.307191] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 22.307193] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 22.307195] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 22.307198] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 22.307199] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 22.307201] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 22.307203] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d7800 for pipe A [ 22.307204] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 22.307205] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 22.307207] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 22.307208] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 22.307210] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 22.307211] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 22.307212] [drm:intel_dump_pipe_config] requested mode: [ 22.307214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 22.307215] [drm:intel_dump_pipe_config] adjusted mode: [ 22.307217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 22.307219] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 22.307220] [drm:intel_dump_pipe_config] port clock: 162000 [ 22.307221] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 22.307222] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 22.307224] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 22.307225] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 22.307226] [drm:intel_dump_pipe_config] ips: 0 [ 22.307227] [drm:intel_dump_pipe_config] double wide: 0 [ 22.307229] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 22.307230] [drm:intel_dump_pipe_config] planes on this crtc [ 22.307232] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 22.307233] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 22.307234] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 22.307235] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 22.307238] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 22.307241] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 22.307243] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B [ 22.307245] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A [ 22.307246] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.307340] [drm:intel_power_well_enable] enabling always-on [ 22.307341] [drm:intel_power_well_enable] enabling DC off [ 22.307404] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 22.307408] [drm:intel_power_well_enable] enabling power well 2 [ 22.307409] [drm:skl_set_power_well] Enabling power well 2 [ 22.307414] [drm:intel_power_well_enable] enabling dpio-common-bc [ 22.307415] [drm:intel_power_well_enable] enabling dpio-common-a [ 22.310787] [drm:intel_power_well_disable] disabling dpio-common-a [ 22.310794] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 22.313932] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 22.313935] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 22.313939] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 22.313940] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 22.313941] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 22.313942] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 22.313943] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 22.313945] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 22.313946] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 22.313947] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 22.313949] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 22.313950] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 22.313952] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 22.313953] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 22.313955] [drm:verify_single_dpll_state] PORT PLL A [ 22.313957] [drm:verify_single_dpll_state] PORT PLL B [ 22.313958] [drm:verify_single_dpll_state] PORT PLL C [ 22.313964] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26 [ 22.313965] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 22.315497] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 22.315500] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 22.316496] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 22.319818] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 22.319863] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d7800 [ 22.319919] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.319923] [drm:intel_enable_pipe] enabling pipe A [ 22.319935] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 22.319937] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 22.319974] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.319980] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.324106] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 22.324112] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 22.324128] [drm:verify_single_dpll_state] PORT PLL B [ 22.328259] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 22.348816] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 22.352922] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 22.352926] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 22.352928] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.352939] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 22.352954] [drm:intel_disable_pipe] disabling pipe A [ 22.357336] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26 [ 22.357344] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 22.357348] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 22.360825] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 22.360828] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 22.360831] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 22.360833] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 22.360834] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 22.360835] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 22.360836] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 22.360838] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 22.360839] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 22.360840] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 22.360841] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 22.360842] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 22.360844] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 22.360845] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 22.360846] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 22.360848] [drm:verify_single_dpll_state] PORT PLL A [ 22.360849] [drm:verify_single_dpll_state] PORT PLL B [ 22.360851] [drm:verify_single_dpll_state] PORT PLL C [ 22.360856] [drm:intel_power_well_disable] disabling dpio-common-bc [ 22.360857] [drm:intel_power_well_disable] disabling power well 2 [ 22.360861] [drm:skl_set_power_well] Disabling power well 2 [ 22.360864] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 22.360867] [drm:intel_power_well_disable] disabling DC off [ 22.360869] [drm:gen9_enable_dc5] Enabling DC5 [ 22.360870] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 22.360872] [drm:intel_power_well_disable] disabling always-on [ 22.362175] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 22.362272] [drm:drm_mode_addfb2] [FB:107] [ 22.366235] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 22.366239] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 22.366247] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 22.366248] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 22.366250] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 22.366253] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 22.366254] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 22.366255] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 22.366257] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d3000 for pipe A [ 22.366258] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 22.366259] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 22.366260] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 22.366262] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 22.366263] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 22.366264] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 22.366265] [drm:intel_dump_pipe_config] requested mode: [ 22.366267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 22.366268] [drm:intel_dump_pipe_config] adjusted mode: [ 22.366270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 22.366271] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 22.366272] [drm:intel_dump_pipe_config] port clock: 162000 [ 22.366273] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 22.366275] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 22.366276] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 22.366277] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 22.366278] [drm:intel_dump_pipe_config] ips: 0 [ 22.366279] [drm:intel_dump_pipe_config] double wide: 0 [ 22.366281] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 22.366282] [drm:intel_dump_pipe_config] planes on this crtc [ 22.366283] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 22.366284] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 22.366285] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 22.366286] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 22.366288] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 22.366291] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 22.366293] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B [ 22.366294] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A [ 22.366296] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.366385] [drm:intel_power_well_enable] enabling always-on [ 22.366386] [drm:intel_power_well_enable] enabling DC off [ 22.366450] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 22.366453] [drm:intel_power_well_enable] enabling power well 2 [ 22.366454] [drm:skl_set_power_well] Enabling power well 2 [ 22.366458] [drm:intel_power_well_enable] enabling dpio-common-bc [ 22.366459] [drm:intel_power_well_enable] enabling dpio-common-a [ 22.368898] [drm:intel_power_well_disable] disabling dpio-common-a [ 22.368906] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 22.372409] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 22.372413] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 22.372416] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 22.372417] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 22.372418] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 22.372419] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 22.372421] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 22.372422] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 22.372424] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 22.372425] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 22.372426] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 22.372427] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 22.372429] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 22.372431] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 22.372432] [drm:verify_single_dpll_state] PORT PLL A [ 22.372434] [drm:verify_single_dpll_state] PORT PLL B [ 22.372435] [drm:verify_single_dpll_state] PORT PLL C [ 22.372441] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26 [ 22.372442] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 22.373196] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 22.373197] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 22.375998] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 22.379165] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 22.379210] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d3000 [ 22.379264] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.379268] [drm:intel_enable_pipe] enabling pipe A [ 22.379275] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 22.379277] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 22.379310] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.379315] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.383454] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 22.383459] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 22.383475] [drm:verify_single_dpll_state] PORT PLL B [ 22.387597] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 22.408154] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 22.412255] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 22.412260] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 22.412262] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.412273] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 22.412289] [drm:intel_disable_pipe] disabling pipe A [ 22.418177] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26 [ 22.418186] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 22.418191] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 22.421857] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 22.421860] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 22.421864] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 22.421866] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 22.421867] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 22.421868] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 22.421869] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 22.421871] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 22.421872] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 22.421873] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 22.421874] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 22.421875] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 22.421877] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 22.421879] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 22.421880] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 22.421882] [drm:verify_single_dpll_state] PORT PLL A [ 22.421884] [drm:verify_single_dpll_state] PORT PLL B [ 22.421885] [drm:verify_single_dpll_state] PORT PLL C [ 22.421890] [drm:intel_power_well_disable] disabling dpio-common-bc [ 22.421892] [drm:intel_power_well_disable] disabling power well 2 [ 22.421896] [drm:skl_set_power_well] Disabling power well 2 [ 22.421899] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 22.421902] [drm:intel_power_well_disable] disabling DC off [ 22.421904] [drm:gen9_enable_dc5] Enabling DC5 [ 22.421906] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 22.421908] [drm:intel_power_well_disable] disabling always-on [ 22.423343] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 22.423442] [drm:drm_mode_addfb2] [FB:107] [ 22.426888] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 22.426893] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 22.426901] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 22.426902] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 22.426905] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 22.426907] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 22.426908] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 22.426910] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 22.426912] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b2800 for pipe A [ 22.426913] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 22.426914] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 22.426916] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 22.426918] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 22.426919] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 22.426920] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 22.426921] [drm:intel_dump_pipe_config] requested mode: [ 22.426923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 22.426925] [drm:intel_dump_pipe_config] adjusted mode: [ 22.426926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 22.426928] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 22.426929] [drm:intel_dump_pipe_config] port clock: 162000 [ 22.426931] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 22.426932] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 22.426933] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 22.426934] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 22.426935] [drm:intel_dump_pipe_config] ips: 0 [ 22.426936] [drm:intel_dump_pipe_config] double wide: 0 [ 22.426939] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 22.426940] [drm:intel_dump_pipe_config] planes on this crtc [ 22.426941] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 22.426942] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 22.426943] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 22.426945] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 22.426947] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 22.426950] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 22.426952] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C [ 22.426954] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A [ 22.426956] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.427047] [drm:intel_power_well_enable] enabling always-on [ 22.427049] [drm:intel_power_well_enable] enabling DC off [ 22.427112] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 22.427115] [drm:intel_power_well_enable] enabling power well 2 [ 22.427117] [drm:skl_set_power_well] Enabling power well 2 [ 22.427121] [drm:intel_power_well_enable] enabling dpio-common-bc [ 22.427122] [drm:intel_power_well_enable] enabling dpio-common-a [ 22.428342] [drm:intel_power_well_disable] disabling dpio-common-a [ 22.428347] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 22.430714] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 22.430718] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 22.430721] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 22.430723] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 22.430724] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 22.430725] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 22.430726] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 22.430727] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 22.430729] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 22.430730] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 22.430731] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 22.430732] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 22.430734] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 22.430736] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 22.430737] [drm:verify_single_dpll_state] PORT PLL A [ 22.430739] [drm:verify_single_dpll_state] PORT PLL B [ 22.430740] [drm:verify_single_dpll_state] PORT PLL C [ 22.430747] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26 [ 22.430749] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 22.431510] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 22.431511] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 22.431755] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 22.431756] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 22.431990] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 22.432529] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 22.432530] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 22.433394] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 22.433515] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b2800 [ 22.433572] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.433576] [drm:intel_enable_pipe] enabling pipe A [ 22.433622] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.433628] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.437728] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 22.437731] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 22.437745] [drm:verify_single_dpll_state] PORT PLL C [ 22.441891] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 22.462449] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 22.466552] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 22.466557] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 22.466559] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.466573] [drm:intel_disable_pipe] disabling pipe A [ 22.472217] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26 [ 22.472224] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 22.472228] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 22.476104] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 22.476107] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 22.476111] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 22.476112] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 22.476113] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 22.476114] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 22.476115] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 22.476117] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 22.476118] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 22.476119] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 22.476120] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 22.476121] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 22.476123] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 22.476124] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 22.476126] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 22.476127] [drm:verify_single_dpll_state] PORT PLL A [ 22.476129] [drm:verify_single_dpll_state] PORT PLL B [ 22.476130] [drm:verify_single_dpll_state] PORT PLL C [ 22.476135] [drm:intel_power_well_disable] disabling dpio-common-bc [ 22.476136] [drm:intel_power_well_disable] disabling power well 2 [ 22.476140] [drm:skl_set_power_well] Disabling power well 2 [ 22.476143] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 22.476146] [drm:intel_power_well_disable] disabling DC off [ 22.476148] [drm:gen9_enable_dc5] Enabling DC5 [ 22.476149] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 22.476151] [drm:intel_power_well_disable] disabling always-on [ 22.477452] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 22.477549] [drm:drm_mode_addfb2] [FB:107] [ 22.480715] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 22.480720] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 22.480727] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 22.480728] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 22.480730] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 22.480733] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 22.480734] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 22.480735] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 22.480737] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b5800 for pipe A [ 22.480738] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 22.480739] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 22.480741] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 22.480742] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 22.480743] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 22.480744] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 22.480745] [drm:intel_dump_pipe_config] requested mode: [ 22.480747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 22.480748] [drm:intel_dump_pipe_config] adjusted mode: [ 22.480750] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 22.480752] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 22.480753] [drm:intel_dump_pipe_config] port clock: 162000 [ 22.480754] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 22.480755] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 22.480756] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 22.480757] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 22.480758] [drm:intel_dump_pipe_config] ips: 0 [ 22.480759] [drm:intel_dump_pipe_config] double wide: 0 [ 22.480761] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 22.480762] [drm:intel_dump_pipe_config] planes on this crtc [ 22.480763] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 22.480764] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 22.480765] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 22.480766] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 22.480768] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 22.480771] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 22.480773] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C [ 22.480775] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A [ 22.480776] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.480865] [drm:intel_power_well_enable] enabling always-on [ 22.480866] [drm:intel_power_well_enable] enabling DC off [ 22.480929] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 22.480932] [drm:intel_power_well_enable] enabling power well 2 [ 22.480934] [drm:skl_set_power_well] Enabling power well 2 [ 22.480938] [drm:intel_power_well_enable] enabling dpio-common-bc [ 22.480939] [drm:intel_power_well_enable] enabling dpio-common-a [ 22.483239] [drm:intel_power_well_disable] disabling dpio-common-a [ 22.483246] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 22.487021] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 22.487024] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 22.487027] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 22.487029] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 22.487030] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 22.487031] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 22.487032] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 22.487033] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 22.487034] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 22.487035] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 22.487036] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 22.487037] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 22.487039] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 22.487040] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 22.487042] [drm:verify_single_dpll_state] PORT PLL A [ 22.487043] [drm:verify_single_dpll_state] PORT PLL B [ 22.487045] [drm:verify_single_dpll_state] PORT PLL C [ 22.487050] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26 [ 22.487051] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 22.487799] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 22.487801] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 22.488038] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 22.488039] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 22.488270] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 22.488804] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 22.488805] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 22.490792] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 22.490835] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b5800 [ 22.490889] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.490892] [drm:intel_enable_pipe] enabling pipe A [ 22.490931] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.490936] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.495049] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 22.495052] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 22.495066] [drm:verify_single_dpll_state] PORT PLL C [ 22.499219] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 22.519768] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 22.523875] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 22.523880] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 22.523882] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.523898] [drm:intel_disable_pipe] disabling pipe A [ 22.529034] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26 [ 22.529041] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 22.529046] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 22.533169] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 22.533173] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 22.533176] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 22.533178] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 22.533179] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 22.533180] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 22.533182] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 22.533183] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 22.533184] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 22.533185] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 22.533187] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 22.533188] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 22.533190] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 22.533191] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 22.533193] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 22.533195] [drm:verify_single_dpll_state] PORT PLL A [ 22.533196] [drm:verify_single_dpll_state] PORT PLL B [ 22.533198] [drm:verify_single_dpll_state] PORT PLL C [ 22.533203] [drm:intel_power_well_disable] disabling dpio-common-bc [ 22.533205] [drm:intel_power_well_disable] disabling power well 2 [ 22.533209] [drm:skl_set_power_well] Disabling power well 2 [ 22.533212] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 22.533215] [drm:intel_power_well_disable] disabling DC off [ 22.533217] [drm:gen9_enable_dc5] Enabling DC5 [ 22.533219] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 22.533221] [drm:intel_power_well_disable] disabling always-on [ 22.534478] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence [ 22.534696] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 22.534793] [drm:drm_mode_addfb2] [FB:107] [ 22.538120] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 22.538124] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 22.538131] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 22.538133] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 22.538135] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.538136] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 22.538140] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 22.538141] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 22.538142] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 22.538144] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b7000 for pipe A [ 22.538145] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 22.538146] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 22.538147] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 22.538149] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 22.538150] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 22.538151] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 22.538152] [drm:intel_dump_pipe_config] requested mode: [ 22.538154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 22.538155] [drm:intel_dump_pipe_config] adjusted mode: [ 22.538157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 22.538158] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 22.538159] [drm:intel_dump_pipe_config] port clock: 270000 [ 22.538160] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 22.538161] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 22.538163] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 22.538164] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 22.538165] [drm:intel_dump_pipe_config] ips: 0 [ 22.538165] [drm:intel_dump_pipe_config] double wide: 0 [ 22.538167] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 22.538168] [drm:intel_dump_pipe_config] planes on this crtc [ 22.538169] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 22.538171] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 22.538172] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 22.538173] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 22.538174] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 22.538177] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 22.538179] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A [ 22.538180] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A [ 22.538182] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.538271] [drm:intel_power_well_enable] enabling always-on [ 22.538273] [drm:intel_power_well_enable] enabling DC off [ 22.538348] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 22.538352] [drm:intel_power_well_enable] enabling dpio-common-a [ 22.540446] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 22.540449] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 22.540451] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 22.540452] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 22.540453] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 22.540454] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 22.540455] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 22.540456] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 22.540457] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 22.540458] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 22.540459] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 22.540460] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 22.540461] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 22.540463] [drm:verify_single_dpll_state] PORT PLL A [ 22.540464] [drm:verify_single_dpll_state] PORT PLL B [ 22.540466] [drm:verify_single_dpll_state] PORT PLL C [ 22.540471] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26 [ 22.540472] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 22.540503] [drm:edp_panel_on] Turn eDP port A panel power on [ 22.540505] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 22.540508] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 22.540509] [drm:wait_panel_status] Wait complete [ 22.540511] [drm:wait_panel_on] Wait for panel power on [ 22.540512] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 22.575111] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 22.575114] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 22.575115] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 22.575134] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 22.592063] [drm:wait_panel_status] Wait complete [ 22.592070] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 22.592072] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 22.592809] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 22.592811] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 22.593039] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 22.593564] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 22.593604] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b7000 [ 22.593668] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.593672] [drm:intel_enable_pipe] enabling pipe A [ 22.593682] [drm:intel_edp_backlight_on] [ 22.593683] [drm:intel_panel_enable_backlight] pipe A [ 22.593685] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 22.593687] [drm:intel_psr_enable] PSR not supported on this platform [ 22.593689] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 22.593711] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.593717] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 22.597819] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 22.597823] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 22.597839] [drm:verify_single_dpll_state] PORT PLL A [ 22.601982] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 22.622561] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 22.626672] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 22.626677] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 22.626680] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.626691] [drm:intel_edp_backlight_off] [ 22.789233] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 22.789243] [drm:intel_disable_pipe] disabling pipe A [ 22.791760] [drm:edp_panel_off] Turn eDP port A panel power off [ 22.791765] [drm:wait_panel_off] Wait for panel power off time [ 22.791768] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 22.804700] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 22.804702] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 22.804703] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 22.804715] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 22.807984] [drm:wait_panel_status] Wait complete [ 22.807990] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26 [ 22.807996] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 22.808001] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 22.808003] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 22.808004] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 22.808005] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 22.808006] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 22.808007] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 22.808008] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 22.808009] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 22.808010] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 22.808011] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 22.808013] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 22.808014] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 22.808015] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 22.808016] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 22.808017] [drm:verify_single_dpll_state] PORT PLL A [ 22.808018] [drm:verify_single_dpll_state] PORT PLL B [ 22.808019] [drm:verify_single_dpll_state] PORT PLL C [ 22.808023] [drm:intel_power_well_disable] disabling dpio-common-a [ 22.808026] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 22.808029] [drm:intel_power_well_disable] disabling DC off [ 22.808031] [drm:gen9_enable_dc5] Enabling DC5 [ 22.808032] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 22.808034] [drm:intel_power_well_disable] disabling always-on [ 22.809331] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 22.809430] [drm:drm_mode_addfb2] [FB:107] [ 22.812543] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 22.812548] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 22.812555] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 22.812556] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 22.812559] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.812560] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 22.812563] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 22.812565] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 22.812566] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 22.812568] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b6000 for pipe A [ 22.812569] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 22.812570] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 22.812571] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 22.812573] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 22.812574] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 22.812575] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 22.812576] [drm:intel_dump_pipe_config] requested mode: [ 22.812578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 22.812579] [drm:intel_dump_pipe_config] adjusted mode: [ 22.812581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 22.812582] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 22.812583] [drm:intel_dump_pipe_config] port clock: 270000 [ 22.812584] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 22.812585] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 22.812587] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 22.812588] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 22.812589] [drm:intel_dump_pipe_config] ips: 0 [ 22.812590] [drm:intel_dump_pipe_config] double wide: 0 [ 22.812591] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 22.812592] [drm:intel_dump_pipe_config] planes on this crtc [ 22.812593] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 22.812595] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 22.812596] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 22.812597] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 22.812599] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 22.812601] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 22.812603] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A [ 22.812605] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A [ 22.812606] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 22.812695] [drm:intel_power_well_enable] enabling always-on [ 22.812697] [drm:intel_power_well_enable] enabling DC off [ 22.812760] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 22.812763] [drm:intel_power_well_enable] enabling dpio-common-a [ 22.848888] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 22.848891] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 22.848893] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 22.848894] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 22.848895] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 22.848896] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 22.848897] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 22.848898] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 22.848899] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 22.848899] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 22.848901] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 22.848902] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 22.848903] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 22.848904] [drm:verify_single_dpll_state] PORT PLL A [ 22.848905] [drm:verify_single_dpll_state] PORT PLL B [ 22.848910] [drm:verify_single_dpll_state] PORT PLL C [ 22.848915] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26 [ 22.848915] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 22.848936] [drm:edp_panel_on] Turn eDP port A panel power on [ 22.848937] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 22.925786] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000060 [ 22.956071] [drm:wait_panel_status] Wait complete [ 22.956075] [drm:wait_panel_on] Wait for panel power on [ 22.956077] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 22.986390] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 22.986392] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 22.986394] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 22.986412] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 23.023200] [drm:wait_panel_status] Wait complete [ 23.023207] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 23.023209] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 23.023964] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 23.023966] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 23.024193] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 23.024718] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 23.024759] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b6000 [ 23.024822] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.024826] [drm:intel_enable_pipe] enabling pipe A [ 23.024836] [drm:intel_edp_backlight_on] [ 23.024837] [drm:intel_panel_enable_backlight] pipe A [ 23.024839] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 23.024841] [drm:intel_psr_enable] PSR not supported on this platform [ 23.024843] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 23.024865] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.024871] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.028973] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 23.028977] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 23.028992] [drm:verify_single_dpll_state] PORT PLL A [ 23.033137] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 23.053698] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 23.057811] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 23.057815] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 23.057817] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.057830] [drm:intel_edp_backlight_off] [ 23.182641] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 23.182651] [drm:intel_disable_pipe] disabling pipe A [ 23.186251] [drm:edp_panel_off] Turn eDP port A panel power off [ 23.186258] [drm:wait_panel_off] Wait for panel power off time [ 23.186260] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 23.208229] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 23.208233] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 23.208234] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 23.208254] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 23.217539] [drm:wait_panel_status] Wait complete [ 23.217548] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26 [ 23.217555] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 23.217559] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 23.217561] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 23.217563] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 23.217566] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 23.217569] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 23.217570] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 23.217572] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 23.217573] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 23.217576] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 23.217577] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 23.217579] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 23.217580] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 23.217581] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 23.217583] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 23.217586] [drm:verify_single_dpll_state] PORT PLL A [ 23.217589] [drm:verify_single_dpll_state] PORT PLL B [ 23.217593] [drm:verify_single_dpll_state] PORT PLL C [ 23.217598] [drm:intel_power_well_disable] disabling dpio-common-a [ 23.217601] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 23.217604] [drm:intel_power_well_disable] disabling DC off [ 23.217606] [drm:gen9_enable_dc5] Enabling DC5 [ 23.217607] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 23.217610] [drm:intel_power_well_disable] disabling always-on [ 23.219005] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 23.219105] [drm:drm_mode_addfb2] [FB:107] [ 23.222497] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 23.222502] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 23.222510] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 23.222511] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 23.222514] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 23.222516] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 23.222517] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 23.222519] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 23.222521] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d3800 for pipe A [ 23.222523] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 23.222524] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 23.222525] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 23.222527] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 23.222528] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 23.222529] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 23.222530] [drm:intel_dump_pipe_config] requested mode: [ 23.222532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 23.222534] [drm:intel_dump_pipe_config] adjusted mode: [ 23.222536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 23.222537] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 23.222538] [drm:intel_dump_pipe_config] port clock: 162000 [ 23.222540] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 23.222541] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 23.222542] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 23.222543] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 23.222544] [drm:intel_dump_pipe_config] ips: 0 [ 23.222545] [drm:intel_dump_pipe_config] double wide: 0 [ 23.222548] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 23.222549] [drm:intel_dump_pipe_config] planes on this crtc [ 23.222550] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 23.222551] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 23.222552] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 23.222554] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 23.222556] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 23.222559] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 23.222561] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B [ 23.222563] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A [ 23.222564] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.222657] [drm:intel_power_well_enable] enabling always-on [ 23.222658] [drm:intel_power_well_enable] enabling DC off [ 23.222721] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 23.222725] [drm:intel_power_well_enable] enabling power well 2 [ 23.222727] [drm:skl_set_power_well] Enabling power well 2 [ 23.222731] [drm:intel_power_well_enable] enabling dpio-common-bc [ 23.222732] [drm:intel_power_well_enable] enabling dpio-common-a [ 23.227531] [drm:intel_power_well_disable] disabling dpio-common-a [ 23.227539] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 23.231674] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 23.231677] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 23.231680] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 23.231682] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 23.231683] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 23.231684] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 23.231685] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 23.231687] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 23.231688] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 23.231689] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 23.231690] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 23.231692] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 23.231694] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 23.231695] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 23.231697] [drm:verify_single_dpll_state] PORT PLL A [ 23.231698] [drm:verify_single_dpll_state] PORT PLL B [ 23.231700] [drm:verify_single_dpll_state] PORT PLL C [ 23.231706] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26 [ 23.231707] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 23.234547] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 23.234550] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 23.235588] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 23.238910] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 23.238954] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d3800 [ 23.239011] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.239015] [drm:intel_enable_pipe] enabling pipe A [ 23.239035] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 23.239037] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 23.239072] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.239078] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.243214] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 23.243220] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 23.243236] [drm:verify_single_dpll_state] PORT PLL B [ 23.247340] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 23.267917] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 23.272010] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 23.272015] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 23.272017] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.272028] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 23.272044] [drm:intel_disable_pipe] disabling pipe A [ 23.276217] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26 [ 23.276225] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 23.276230] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 23.280194] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 23.280197] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 23.280201] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 23.280203] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 23.280204] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 23.280205] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 23.280206] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 23.280208] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 23.280209] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 23.280210] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 23.280211] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 23.280212] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 23.280214] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 23.280216] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 23.280217] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 23.280219] [drm:verify_single_dpll_state] PORT PLL A [ 23.280221] [drm:verify_single_dpll_state] PORT PLL B [ 23.280222] [drm:verify_single_dpll_state] PORT PLL C [ 23.280227] [drm:intel_power_well_disable] disabling dpio-common-bc [ 23.280229] [drm:intel_power_well_disable] disabling power well 2 [ 23.280233] [drm:skl_set_power_well] Disabling power well 2 [ 23.280237] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 23.280240] [drm:intel_power_well_disable] disabling DC off [ 23.280242] [drm:gen9_enable_dc5] Enabling DC5 [ 23.280243] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 23.280245] [drm:intel_power_well_disable] disabling always-on [ 23.281658] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 23.281758] [drm:drm_mode_addfb2] [FB:107] [ 23.285183] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 23.285188] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 23.285196] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 23.285198] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 23.285200] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 23.285203] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 23.285204] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 23.285206] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 23.285208] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d5800 for pipe A [ 23.285209] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 23.285210] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 23.285212] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 23.285213] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 23.285215] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 23.285216] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 23.285217] [drm:intel_dump_pipe_config] requested mode: [ 23.285219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 23.285220] [drm:intel_dump_pipe_config] adjusted mode: [ 23.285222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 23.285224] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 23.285225] [drm:intel_dump_pipe_config] port clock: 162000 [ 23.285226] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 23.285228] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 23.285229] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 23.285230] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 23.285231] [drm:intel_dump_pipe_config] ips: 0 [ 23.285232] [drm:intel_dump_pipe_config] double wide: 0 [ 23.285234] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 23.285235] [drm:intel_dump_pipe_config] planes on this crtc [ 23.285237] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 23.285238] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 23.285239] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 23.285240] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 23.285243] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 23.285246] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 23.285248] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B [ 23.285250] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A [ 23.285251] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.285344] [drm:intel_power_well_enable] enabling always-on [ 23.285345] [drm:intel_power_well_enable] enabling DC off [ 23.285408] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 23.285412] [drm:intel_power_well_enable] enabling power well 2 [ 23.285413] [drm:skl_set_power_well] Enabling power well 2 [ 23.285418] [drm:intel_power_well_enable] enabling dpio-common-bc [ 23.285419] [drm:intel_power_well_enable] enabling dpio-common-a [ 23.288486] [drm:intel_power_well_disable] disabling dpio-common-a [ 23.288494] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 23.291889] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 23.291893] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 23.291896] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 23.291897] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 23.291898] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 23.291899] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 23.291901] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 23.291902] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 23.291904] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 23.291905] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 23.291906] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 23.291907] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 23.291909] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 23.291911] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 23.291912] [drm:verify_single_dpll_state] PORT PLL A [ 23.291914] [drm:verify_single_dpll_state] PORT PLL B [ 23.291915] [drm:verify_single_dpll_state] PORT PLL C [ 23.291921] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26 [ 23.291922] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 23.292797] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 23.292799] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 23.293835] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 23.297198] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 23.297251] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d5800 [ 23.297306] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.297308] [drm:intel_enable_pipe] enabling pipe A [ 23.297330] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 23.297331] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 23.297364] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.297369] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.301510] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 23.301515] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 23.301530] [drm:verify_single_dpll_state] PORT PLL B [ 23.305647] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 23.326209] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 23.330314] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 23.330318] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 23.330320] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.330331] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 23.330345] [drm:intel_disable_pipe] disabling pipe A [ 23.334523] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26 [ 23.334531] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 23.334535] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 23.338143] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 23.338146] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 23.338149] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 23.338151] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 23.338152] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 23.338153] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 23.338154] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 23.338156] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 23.338157] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 23.338158] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 23.338159] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 23.338160] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 23.338161] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 23.338163] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 23.338164] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 23.338166] [drm:verify_single_dpll_state] PORT PLL A [ 23.338167] [drm:verify_single_dpll_state] PORT PLL B [ 23.338169] [drm:verify_single_dpll_state] PORT PLL C [ 23.338173] [drm:intel_power_well_disable] disabling dpio-common-bc [ 23.338175] [drm:intel_power_well_disable] disabling power well 2 [ 23.338179] [drm:skl_set_power_well] Disabling power well 2 [ 23.338182] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 23.338185] [drm:intel_power_well_disable] disabling DC off [ 23.338186] [drm:gen9_enable_dc5] Enabling DC5 [ 23.338188] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 23.338190] [drm:intel_power_well_disable] disabling always-on [ 23.339515] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 23.339612] [drm:drm_mode_addfb2] [FB:107] [ 23.342787] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 23.342792] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 23.342799] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 23.342801] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 23.342803] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 23.342805] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 23.342806] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 23.342808] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 23.342810] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d7000 for pipe A [ 23.342811] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 23.342812] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 23.342813] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 23.342815] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 23.342816] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 23.342817] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 23.342818] [drm:intel_dump_pipe_config] requested mode: [ 23.342820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 23.342821] [drm:intel_dump_pipe_config] adjusted mode: [ 23.342823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 23.342824] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 23.342825] [drm:intel_dump_pipe_config] port clock: 162000 [ 23.342826] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 23.342827] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 23.342828] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 23.342830] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 23.342830] [drm:intel_dump_pipe_config] ips: 0 [ 23.342831] [drm:intel_dump_pipe_config] double wide: 0 [ 23.342833] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 23.342834] [drm:intel_dump_pipe_config] planes on this crtc [ 23.342835] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 23.342837] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 23.342838] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 23.342839] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 23.342841] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 23.342844] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 23.342846] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C [ 23.342847] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A [ 23.342849] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.342938] [drm:intel_power_well_enable] enabling always-on [ 23.342939] [drm:intel_power_well_enable] enabling DC off [ 23.343002] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 23.343005] [drm:intel_power_well_enable] enabling power well 2 [ 23.343007] [drm:skl_set_power_well] Enabling power well 2 [ 23.343011] [drm:intel_power_well_enable] enabling dpio-common-bc [ 23.343012] [drm:intel_power_well_enable] enabling dpio-common-a [ 23.347172] [drm:intel_power_well_disable] disabling dpio-common-a [ 23.347179] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 23.351288] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 23.351292] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 23.351295] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 23.351296] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 23.351297] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 23.351298] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 23.351299] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 23.351300] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 23.351301] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 23.351302] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 23.351304] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 23.351305] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 23.351306] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 23.351308] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 23.351309] [drm:verify_single_dpll_state] PORT PLL A [ 23.351311] [drm:verify_single_dpll_state] PORT PLL B [ 23.351312] [drm:verify_single_dpll_state] PORT PLL C [ 23.351318] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26 [ 23.351319] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 23.352069] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 23.352070] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 23.352308] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 23.352309] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 23.352539] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 23.353093] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 23.353094] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 23.355340] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 23.355384] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d7000 [ 23.355438] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.355442] [drm:intel_enable_pipe] enabling pipe A [ 23.355482] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.355487] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.359596] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 23.359599] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 23.359612] [drm:verify_single_dpll_state] PORT PLL C [ 23.363767] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 23.384336] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 23.388399] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 23.388403] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 23.388405] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.388419] [drm:intel_disable_pipe] disabling pipe A [ 23.392594] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26 [ 23.392601] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 23.392606] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 23.396735] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 23.396738] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 23.396741] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 23.396743] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 23.396744] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 23.396745] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 23.396746] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 23.396747] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 23.396748] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 23.396749] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 23.396750] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 23.396752] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 23.396753] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 23.396755] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 23.396756] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 23.396758] [drm:verify_single_dpll_state] PORT PLL A [ 23.396759] [drm:verify_single_dpll_state] PORT PLL B [ 23.396760] [drm:verify_single_dpll_state] PORT PLL C [ 23.396765] [drm:intel_power_well_disable] disabling dpio-common-bc [ 23.396767] [drm:intel_power_well_disable] disabling power well 2 [ 23.396771] [drm:skl_set_power_well] Disabling power well 2 [ 23.396774] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 23.396776] [drm:intel_power_well_disable] disabling DC off [ 23.396778] [drm:gen9_enable_dc5] Enabling DC5 [ 23.396779] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 23.396781] [drm:intel_power_well_disable] disabling always-on [ 23.398100] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 23.398198] [drm:drm_mode_addfb2] [FB:107] [ 23.401352] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 23.401356] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 23.401363] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 23.401365] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 23.401367] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 23.401369] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 23.401370] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 23.401372] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 23.401374] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b7800 for pipe A [ 23.401375] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 23.401376] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 23.401377] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 23.401378] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 23.401380] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 23.401381] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 23.401382] [drm:intel_dump_pipe_config] requested mode: [ 23.401384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 23.401385] [drm:intel_dump_pipe_config] adjusted mode: [ 23.401386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 23.401388] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 23.401389] [drm:intel_dump_pipe_config] port clock: 162000 [ 23.401390] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 23.401391] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 23.401392] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 23.401393] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 23.401394] [drm:intel_dump_pipe_config] ips: 0 [ 23.401395] [drm:intel_dump_pipe_config] double wide: 0 [ 23.401397] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 23.401398] [drm:intel_dump_pipe_config] planes on this crtc [ 23.401399] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 23.401400] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 23.401401] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 23.401402] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 23.401405] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 23.401408] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 23.401410] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C [ 23.401411] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A [ 23.401413] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.401502] [drm:intel_power_well_enable] enabling always-on [ 23.401503] [drm:intel_power_well_enable] enabling DC off [ 23.401566] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 23.401569] [drm:intel_power_well_enable] enabling power well 2 [ 23.401571] [drm:skl_set_power_well] Enabling power well 2 [ 23.401575] [drm:intel_power_well_enable] enabling dpio-common-bc [ 23.401576] [drm:intel_power_well_enable] enabling dpio-common-a [ 23.402879] [drm:intel_power_well_disable] disabling dpio-common-a [ 23.402885] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 23.405298] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 23.405301] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 23.405304] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 23.405306] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 23.405307] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 23.405308] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 23.405309] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 23.405310] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 23.405311] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 23.405312] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 23.405313] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 23.405314] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 23.405316] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 23.405318] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 23.405319] [drm:verify_single_dpll_state] PORT PLL A [ 23.405321] [drm:verify_single_dpll_state] PORT PLL B [ 23.405322] [drm:verify_single_dpll_state] PORT PLL C [ 23.405328] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26 [ 23.405329] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 23.406086] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 23.406087] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 23.406329] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 23.406330] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 23.406564] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 23.407102] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 23.407103] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 23.409013] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 23.409059] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b7800 [ 23.409112] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.409114] [drm:intel_enable_pipe] enabling pipe A [ 23.409141] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.409146] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.413309] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 23.413313] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 23.413328] [drm:verify_single_dpll_state] PORT PLL C [ 23.417436] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 23.438009] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 23.442100] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 23.442104] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 23.442106] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.442121] [drm:intel_disable_pipe] disabling pipe A [ 23.447701] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26 [ 23.447709] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 23.447713] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 23.451831] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 23.451834] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 23.451837] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 23.451839] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 23.451841] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 23.451842] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 23.451843] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 23.451845] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 23.451846] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 23.451847] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 23.451848] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 23.451849] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 23.451851] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 23.451853] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 23.451854] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 23.451856] [drm:verify_single_dpll_state] PORT PLL A [ 23.451858] [drm:verify_single_dpll_state] PORT PLL B [ 23.451859] [drm:verify_single_dpll_state] PORT PLL C [ 23.451864] [drm:intel_power_well_disable] disabling dpio-common-bc [ 23.451866] [drm:intel_power_well_disable] disabling power well 2 [ 23.451870] [drm:skl_set_power_well] Disabling power well 2 [ 23.451874] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 23.451877] [drm:intel_power_well_disable] disabling DC off [ 23.451879] [drm:gen9_enable_dc5] Enabling DC5 [ 23.451880] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 23.451882] [drm:intel_power_well_disable] disabling always-on [ 23.453172] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A [ 23.471761] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-A [ 23.472075] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 23.472171] [drm:drm_mode_addfb2] [FB:107] [ 23.475557] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 23.475561] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 23.475570] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 23.475571] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 23.475574] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.475576] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 23.475579] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 23.475580] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 23.475582] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 23.475584] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880272d36800 for pipe A [ 23.475585] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 23.475586] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 23.475588] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 23.475589] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 23.475591] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 23.475592] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 23.475593] [drm:intel_dump_pipe_config] requested mode: [ 23.475595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 23.475596] [drm:intel_dump_pipe_config] adjusted mode: [ 23.475598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 23.475600] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 23.475601] [drm:intel_dump_pipe_config] port clock: 270000 [ 23.475602] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 23.475604] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 23.475605] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 23.475606] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 23.475607] [drm:intel_dump_pipe_config] ips: 0 [ 23.475608] [drm:intel_dump_pipe_config] double wide: 0 [ 23.475610] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 23.475611] [drm:intel_dump_pipe_config] planes on this crtc [ 23.475613] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 23.475614] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 23.475615] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 23.475616] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 23.475618] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 23.475621] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 23.475623] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A [ 23.475625] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A [ 23.475626] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.475719] [drm:intel_power_well_enable] enabling always-on [ 23.475720] [drm:intel_power_well_enable] enabling DC off [ 23.475783] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 23.475786] [drm:intel_power_well_enable] enabling dpio-common-a [ 23.476429] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 23.476431] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 23.476437] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 23.476440] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 23.476444] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 23.476447] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 23.476450] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 23.476453] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 23.476457] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 23.476460] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 23.476464] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 23.476468] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 23.476470] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 23.476473] [drm:verify_single_dpll_state] PORT PLL A [ 23.476477] [drm:verify_single_dpll_state] PORT PLL B [ 23.476480] [drm:verify_single_dpll_state] PORT PLL C [ 23.476488] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26 [ 23.476489] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 23.476520] [drm:edp_panel_on] Turn eDP port A panel power on [ 23.476521] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 23.476525] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 23.476526] [drm:wait_panel_status] Wait complete [ 23.476527] [drm:wait_panel_on] Wait for panel power on [ 23.476529] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 23.502850] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 23.502853] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 23.502854] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 23.502871] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 23.530567] [drm:wait_panel_status] Wait complete [ 23.530574] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 23.530577] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 23.531328] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 23.531330] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 23.531571] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 23.532104] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 23.532147] [drm:skylake_pfit_enable] for crtc_state = ffff880272d36800 [ 23.532211] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.532213] [drm:intel_enable_pipe] enabling pipe A [ 23.532231] [drm:intel_edp_backlight_on] [ 23.532232] [drm:intel_panel_enable_backlight] pipe A [ 23.532234] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 23.532237] [drm:intel_psr_enable] PSR not supported on this platform [ 23.532238] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 23.532260] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.532266] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 23.536396] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 23.536401] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 23.536417] [drm:verify_single_dpll_state] PORT PLL A [ 23.540530] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 23.561077] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 23.565211] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 23.565216] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 23.565218] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.565229] [drm:intel_edp_backlight_off] [ 23.692123] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 23.692133] [drm:intel_disable_pipe] disabling pipe A [ 23.694254] [drm:edp_panel_off] Turn eDP port A panel power off [ 23.694259] [drm:wait_panel_off] Wait for panel power off time [ 23.694261] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 23.707215] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 23.707219] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 23.707220] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 23.707243] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 23.725364] [drm:wait_panel_status] Wait complete [ 23.725371] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26 [ 23.725378] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 23.725382] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 23.725384] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 23.725386] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 23.725387] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 23.725388] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 23.725389] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 23.725390] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 23.725391] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 23.725392] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 23.725394] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 23.725395] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 23.725397] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 23.725398] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 23.725399] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 23.725400] [drm:verify_single_dpll_state] PORT PLL A [ 23.725402] [drm:verify_single_dpll_state] PORT PLL B [ 23.725403] [drm:verify_single_dpll_state] PORT PLL C [ 23.725407] [drm:intel_power_well_disable] disabling dpio-common-a [ 23.725411] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 23.725414] [drm:intel_power_well_disable] disabling DC off [ 23.725416] [drm:gen9_enable_dc5] Enabling DC5 [ 23.725417] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 23.725419] [drm:intel_power_well_disable] disabling always-on [ 23.726804] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 23.726907] [drm:drm_mode_addfb2] [FB:107] [ 23.730245] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 23.730250] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 23.730258] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 23.730259] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 23.730262] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.730264] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 23.730267] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 23.730268] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 23.730270] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 23.730272] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88026e44a000 for pipe A [ 23.730273] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 23.730274] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 23.730276] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 23.730277] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 23.730279] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 23.730280] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 23.730281] [drm:intel_dump_pipe_config] requested mode: [ 23.730283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 23.730284] [drm:intel_dump_pipe_config] adjusted mode: [ 23.730286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 23.730288] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 23.730289] [drm:intel_dump_pipe_config] port clock: 270000 [ 23.730290] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 23.730291] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 23.730293] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 23.730294] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 23.730295] [drm:intel_dump_pipe_config] ips: 0 [ 23.730296] [drm:intel_dump_pipe_config] double wide: 0 [ 23.730298] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 23.730299] [drm:intel_dump_pipe_config] planes on this crtc [ 23.730300] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 23.730302] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 23.730303] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 23.730304] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 23.730306] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 23.730309] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 23.730311] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A [ 23.730312] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A [ 23.730314] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 23.730406] [drm:intel_power_well_enable] enabling always-on [ 23.730408] [drm:intel_power_well_enable] enabling DC off [ 23.730471] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 23.730474] [drm:intel_power_well_enable] enabling dpio-common-a [ 23.748776] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 23.748779] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 23.748781] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 23.748783] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 23.748784] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 23.748785] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 23.748786] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 23.748787] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 23.748788] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 23.748789] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 23.748791] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 23.748792] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 23.748793] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 23.748795] [drm:verify_single_dpll_state] PORT PLL A [ 23.748796] [drm:verify_single_dpll_state] PORT PLL B [ 23.748798] [drm:verify_single_dpll_state] PORT PLL C [ 23.748806] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26 [ 23.748807] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 23.748838] [drm:edp_panel_on] Turn eDP port A panel power on [ 23.748839] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 23.971179] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 23.971182] [drm:wait_panel_status] Wait complete [ 23.971184] [drm:wait_panel_on] Wait for panel power on [ 23.971186] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 00000063 [ 23.997501] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 23.997505] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 23.997507] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 23.997531] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 24.037607] [drm:wait_panel_status] Wait complete [ 24.037614] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 24.037616] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 24.038373] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 24.038376] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 24.038603] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 24.039127] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 24.039168] [drm:skylake_pfit_enable] for crtc_state = ffff88026e44a000 [ 24.039232] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.039236] [drm:intel_enable_pipe] enabling pipe A [ 24.039246] [drm:intel_edp_backlight_on] [ 24.039247] [drm:intel_panel_enable_backlight] pipe A [ 24.039249] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 24.041704] [drm:intel_psr_enable] PSR not supported on this platform [ 24.041706] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 24.041729] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.041735] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.043376] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 24.043380] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 24.043396] [drm:verify_single_dpll_state] PORT PLL A [ 24.047537] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 24.068086] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 24.072212] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 24.072217] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 24.072219] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 24.072231] [drm:intel_edp_backlight_off] [ 24.129478] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 24.129487] [drm:intel_disable_pipe] disabling pipe A [ 24.131486] [drm:edp_panel_off] Turn eDP port A panel power off [ 24.131492] [drm:wait_panel_off] Wait for panel power off time [ 24.131495] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 24.144434] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 24.144438] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 24.144440] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 24.144466] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 24.144691] [drm:wait_panel_status] Wait complete [ 24.144697] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26 [ 24.144704] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 24.144708] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 24.144710] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 24.144712] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 24.144713] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 24.144714] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 24.144715] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 24.144716] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 24.144717] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 24.144718] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 24.144719] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 24.144721] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 24.144722] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 24.144724] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 24.144725] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 24.144726] [drm:verify_single_dpll_state] PORT PLL A [ 24.144728] [drm:verify_single_dpll_state] PORT PLL B [ 24.144729] [drm:verify_single_dpll_state] PORT PLL C [ 24.144733] [drm:intel_power_well_disable] disabling dpio-common-a [ 24.144736] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 24.144739] [drm:intel_power_well_disable] disabling DC off [ 24.144741] [drm:gen9_enable_dc5] Enabling DC5 [ 24.144742] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 24.144744] [drm:intel_power_well_disable] disabling always-on [ 24.146933] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 24.147032] [drm:drm_mode_addfb2] [FB:107] [ 24.150438] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 24.150443] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 24.150451] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 24.150452] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 24.150454] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 24.150457] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 24.150458] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 24.150460] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 24.150462] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b0800 for pipe A [ 24.150463] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 24.150464] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 24.150466] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 24.150467] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 24.150469] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 24.150470] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 24.150471] [drm:intel_dump_pipe_config] requested mode: [ 24.150473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 24.150474] [drm:intel_dump_pipe_config] adjusted mode: [ 24.150476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 24.150478] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 24.150479] [drm:intel_dump_pipe_config] port clock: 162000 [ 24.150480] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 24.150481] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 24.150483] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 24.150484] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 24.150485] [drm:intel_dump_pipe_config] ips: 0 [ 24.150486] [drm:intel_dump_pipe_config] double wide: 0 [ 24.150488] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 24.150489] [drm:intel_dump_pipe_config] planes on this crtc [ 24.150490] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 24.150492] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 24.150493] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 24.150494] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 24.150497] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 24.150499] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 24.150502] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B [ 24.150503] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A [ 24.150505] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 24.150597] [drm:intel_power_well_enable] enabling always-on [ 24.150599] [drm:intel_power_well_enable] enabling DC off [ 24.150662] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 24.150665] [drm:intel_power_well_enable] enabling power well 2 [ 24.150667] [drm:skl_set_power_well] Enabling power well 2 [ 24.150671] [drm:intel_power_well_enable] enabling dpio-common-bc [ 24.150672] [drm:intel_power_well_enable] enabling dpio-common-a [ 24.154721] [drm:intel_power_well_disable] disabling dpio-common-a [ 24.154729] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 24.158815] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 24.158819] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 24.158822] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 24.158823] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 24.158825] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 24.158826] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 24.158827] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 24.158829] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 24.158830] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 24.158831] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 24.158832] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 24.158833] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 24.158835] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 24.158837] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 24.158838] [drm:verify_single_dpll_state] PORT PLL A [ 24.158840] [drm:verify_single_dpll_state] PORT PLL B [ 24.158841] [drm:verify_single_dpll_state] PORT PLL C [ 24.158847] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26 [ 24.158848] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 24.161945] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 24.161948] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 24.162958] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 24.166266] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 24.166311] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b0800 [ 24.166367] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.166371] [drm:intel_enable_pipe] enabling pipe A [ 24.166385] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 24.166387] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 24.166422] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.166427] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.170542] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 24.170547] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 24.170564] [drm:verify_single_dpll_state] PORT PLL B [ 24.174693] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 24.195217] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 24.199351] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 24.199355] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 24.199357] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 24.199368] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 24.199383] [drm:intel_disable_pipe] disabling pipe A [ 24.203512] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26 [ 24.203520] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 24.203525] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 24.207206] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 24.207209] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 24.207212] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 24.207214] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 24.207215] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 24.207216] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 24.207217] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 24.207218] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 24.207219] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 24.207220] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 24.207221] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 24.207222] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 24.207224] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 24.207225] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 24.207227] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 24.207228] [drm:verify_single_dpll_state] PORT PLL A [ 24.207230] [drm:verify_single_dpll_state] PORT PLL B [ 24.207231] [drm:verify_single_dpll_state] PORT PLL C [ 24.207236] [drm:intel_power_well_disable] disabling dpio-common-bc [ 24.207238] [drm:intel_power_well_disable] disabling power well 2 [ 24.207241] [drm:skl_set_power_well] Disabling power well 2 [ 24.207244] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 24.207247] [drm:intel_power_well_disable] disabling DC off [ 24.207249] [drm:gen9_enable_dc5] Enabling DC5 [ 24.207250] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 24.207252] [drm:intel_power_well_disable] disabling always-on [ 24.208554] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 24.208650] [drm:drm_mode_addfb2] [FB:107] [ 24.211796] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 24.211801] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 24.211809] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 24.211810] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 24.211812] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 24.211814] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 24.211816] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 24.211817] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 24.211819] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d2000 for pipe A [ 24.211820] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 24.211821] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 24.211822] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 24.211824] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 24.211825] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 24.211826] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 24.211827] [drm:intel_dump_pipe_config] requested mode: [ 24.211829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 24.211830] [drm:intel_dump_pipe_config] adjusted mode: [ 24.211831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 24.211833] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 24.211834] [drm:intel_dump_pipe_config] port clock: 162000 [ 24.211835] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 24.211836] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 24.211837] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 24.211838] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 24.211839] [drm:intel_dump_pipe_config] ips: 0 [ 24.211840] [drm:intel_dump_pipe_config] double wide: 0 [ 24.211842] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 24.211843] [drm:intel_dump_pipe_config] planes on this crtc [ 24.211844] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 24.211845] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 24.211846] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 24.211847] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 24.211850] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 24.211852] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 24.211855] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B [ 24.211856] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A [ 24.211857] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 24.211946] [drm:intel_power_well_enable] enabling always-on [ 24.211947] [drm:intel_power_well_enable] enabling DC off [ 24.212010] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 24.212013] [drm:intel_power_well_enable] enabling power well 2 [ 24.212015] [drm:skl_set_power_well] Enabling power well 2 [ 24.212018] [drm:intel_power_well_enable] enabling dpio-common-bc [ 24.212019] [drm:intel_power_well_enable] enabling dpio-common-a [ 24.213950] [drm:intel_power_well_disable] disabling dpio-common-a [ 24.213957] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 24.218041] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 24.218044] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 24.218048] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 24.218049] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 24.218050] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 24.218051] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 24.218052] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 24.218054] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 24.218055] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 24.218056] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 24.218057] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 24.218059] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 24.218061] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 24.218062] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 24.218064] [drm:verify_single_dpll_state] PORT PLL A [ 24.218065] [drm:verify_single_dpll_state] PORT PLL B [ 24.218067] [drm:verify_single_dpll_state] PORT PLL C [ 24.218073] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26 [ 24.218074] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 24.218837] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 24.218839] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 24.221152] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 24.224477] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 24.224530] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d2000 [ 24.224586] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.224590] [drm:intel_enable_pipe] enabling pipe A [ 24.224600] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 24.224602] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 24.224637] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.224643] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.228760] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 24.228765] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 24.228782] [drm:verify_single_dpll_state] PORT PLL B [ 24.232909] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 24.253435] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 24.257571] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 24.257576] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 24.257578] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 24.257589] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 24.257605] [drm:intel_disable_pipe] disabling pipe A [ 24.263526] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26 [ 24.263534] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 24.263539] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 24.267395] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 24.267398] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 24.267401] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 24.267403] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 24.267405] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 24.267406] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 24.267407] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 24.267408] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 24.267409] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 24.267411] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 24.267412] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 24.267413] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 24.267415] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 24.267416] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 24.267418] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 24.267420] [drm:verify_single_dpll_state] PORT PLL A [ 24.267421] [drm:verify_single_dpll_state] PORT PLL B [ 24.267423] [drm:verify_single_dpll_state] PORT PLL C [ 24.267428] [drm:intel_power_well_disable] disabling dpio-common-bc [ 24.267430] [drm:intel_power_well_disable] disabling power well 2 [ 24.267433] [drm:skl_set_power_well] Disabling power well 2 [ 24.267437] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 24.267440] [drm:intel_power_well_disable] disabling DC off [ 24.267442] [drm:gen9_enable_dc5] Enabling DC5 [ 24.267443] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 24.267445] [drm:intel_power_well_disable] disabling always-on [ 24.268843] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 24.268942] [drm:drm_mode_addfb2] [FB:107] [ 24.272337] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 24.272341] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 24.272348] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 24.272350] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 24.272352] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 24.272354] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 24.272355] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 24.272357] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 24.272359] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d2800 for pipe A [ 24.272360] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 24.272361] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 24.272362] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 24.272363] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 24.272365] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 24.272366] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 24.272367] [drm:intel_dump_pipe_config] requested mode: [ 24.272368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 24.272369] [drm:intel_dump_pipe_config] adjusted mode: [ 24.272371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 24.272373] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 24.272374] [drm:intel_dump_pipe_config] port clock: 162000 [ 24.272375] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 24.272376] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 24.272377] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 24.272378] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 24.272379] [drm:intel_dump_pipe_config] ips: 0 [ 24.272380] [drm:intel_dump_pipe_config] double wide: 0 [ 24.272382] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 24.272383] [drm:intel_dump_pipe_config] planes on this crtc [ 24.272384] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 24.272385] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 24.272386] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 24.272387] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 24.272390] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 24.272392] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 24.272394] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C [ 24.272396] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A [ 24.272397] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 24.272486] [drm:intel_power_well_enable] enabling always-on [ 24.272487] [drm:intel_power_well_enable] enabling DC off [ 24.272550] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 24.272553] [drm:intel_power_well_enable] enabling power well 2 [ 24.272554] [drm:skl_set_power_well] Enabling power well 2 [ 24.272558] [drm:intel_power_well_enable] enabling dpio-common-bc [ 24.272559] [drm:intel_power_well_enable] enabling dpio-common-a [ 24.274180] [drm:intel_power_well_disable] disabling dpio-common-a [ 24.274187] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 24.278276] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 24.278279] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 24.278282] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 24.278284] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 24.278285] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 24.278286] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 24.278287] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 24.278288] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 24.278289] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 24.278290] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 24.278291] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 24.278292] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 24.278293] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 24.278295] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 24.278296] [drm:verify_single_dpll_state] PORT PLL A [ 24.278298] [drm:verify_single_dpll_state] PORT PLL B [ 24.278299] [drm:verify_single_dpll_state] PORT PLL C [ 24.278305] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26 [ 24.278306] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 24.280843] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 24.280846] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 24.281216] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 24.281218] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 24.281449] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 24.281983] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 24.281984] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 24.284520] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 24.284564] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d2800 [ 24.284618] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.284620] [drm:intel_enable_pipe] enabling pipe A [ 24.284651] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.284656] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.288778] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 24.288782] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 24.288796] [drm:verify_single_dpll_state] PORT PLL C [ 24.292907] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 24.313457] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 24.317571] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 24.317575] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 24.317577] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 24.317593] [drm:intel_disable_pipe] disabling pipe A [ 24.321714] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26 [ 24.321722] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 24.321727] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 24.325454] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 24.325457] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 24.325460] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 24.325462] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 24.325463] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 24.325465] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 24.325466] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 24.325467] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 24.325468] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 24.325470] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 24.325471] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 24.325472] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 24.325474] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 24.325475] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 24.325477] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 24.325479] [drm:verify_single_dpll_state] PORT PLL A [ 24.325480] [drm:verify_single_dpll_state] PORT PLL B [ 24.325482] [drm:verify_single_dpll_state] PORT PLL C [ 24.325487] [drm:intel_power_well_disable] disabling dpio-common-bc [ 24.325489] [drm:intel_power_well_disable] disabling power well 2 [ 24.325492] [drm:skl_set_power_well] Disabling power well 2 [ 24.325496] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 24.325498] [drm:intel_power_well_disable] disabling DC off [ 24.325500] [drm:gen9_enable_dc5] Enabling DC5 [ 24.325502] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 24.325504] [drm:intel_power_well_disable] disabling always-on [ 24.326901] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 24.327001] [drm:drm_mode_addfb2] [FB:107] [ 24.330403] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 24.330408] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 24.330416] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 24.330417] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 24.330420] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 24.330422] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 24.330424] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 24.330425] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 24.330427] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802704b4800 for pipe A [ 24.330428] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 24.330429] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 24.330431] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 24.330433] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 24.330434] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 24.330435] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 24.330436] [drm:intel_dump_pipe_config] requested mode: [ 24.330438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 24.330440] [drm:intel_dump_pipe_config] adjusted mode: [ 24.330442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 24.330443] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 24.330444] [drm:intel_dump_pipe_config] port clock: 162000 [ 24.330446] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 24.330447] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 24.330448] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 24.330449] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 24.330450] [drm:intel_dump_pipe_config] ips: 0 [ 24.330451] [drm:intel_dump_pipe_config] double wide: 0 [ 24.330454] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 24.330455] [drm:intel_dump_pipe_config] planes on this crtc [ 24.330456] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 24.330457] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 24.330458] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 24.330460] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 24.330462] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 24.330465] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 24.330467] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C [ 24.330469] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A [ 24.330470] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 24.330562] [drm:intel_power_well_enable] enabling always-on [ 24.330564] [drm:intel_power_well_enable] enabling DC off [ 24.330627] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 24.330630] [drm:intel_power_well_enable] enabling power well 2 [ 24.330632] [drm:skl_set_power_well] Enabling power well 2 [ 24.330636] [drm:intel_power_well_enable] enabling dpio-common-bc [ 24.330637] [drm:intel_power_well_enable] enabling dpio-common-a [ 24.332749] [drm:intel_power_well_disable] disabling dpio-common-a [ 24.332758] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 24.336362] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 24.336365] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 24.336368] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 24.336370] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 24.336371] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 24.336372] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 24.336373] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 24.336374] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 24.336375] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 24.336376] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 24.336377] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 24.336378] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 24.336380] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 24.336381] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 24.336383] [drm:verify_single_dpll_state] PORT PLL A [ 24.336384] [drm:verify_single_dpll_state] PORT PLL B [ 24.336385] [drm:verify_single_dpll_state] PORT PLL C [ 24.336391] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26 [ 24.336392] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 24.339345] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 24.339347] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 24.339703] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 24.339705] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 24.339943] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 24.340483] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 24.340485] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 24.342156] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 24.342207] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b4800 [ 24.342261] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.342265] [drm:intel_enable_pipe] enabling pipe A [ 24.342311] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.342316] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 24.346444] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 24.346449] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 24.346463] [drm:verify_single_dpll_state] PORT PLL C [ 24.350590] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 24.371117] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 24.375252] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 24.375256] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 24.375258] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 24.375274] [drm:intel_disable_pipe] disabling pipe A [ 24.380871] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26 [ 24.380879] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 24.380883] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 24.384970] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 24.384974] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 24.384977] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 24.384979] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 24.384980] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 24.384981] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 24.384982] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 24.384984] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 24.384985] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 24.384986] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 24.384987] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 24.384988] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 24.384990] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 24.384992] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 24.384993] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 24.384995] [drm:verify_single_dpll_state] PORT PLL A [ 24.384997] [drm:verify_single_dpll_state] PORT PLL B [ 24.384998] [drm:verify_single_dpll_state] PORT PLL C [ 24.385003] [drm:intel_power_well_disable] disabling dpio-common-bc [ 24.385005] [drm:intel_power_well_disable] disabling power well 2 [ 24.385009] [drm:skl_set_power_well] Disabling power well 2 [ 24.385012] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 24.385015] [drm:intel_power_well_disable] disabling DC off [ 24.385017] [drm:gen9_enable_dc5] Enabling DC5 [ 24.385018] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 24.385020] [drm:intel_power_well_disable] disabling always-on [ 26.749910] [drm] stuck on render ring [ 26.751176] [drm] GPU HANG: ecode 9:0:0xe757fffe, in kms_pipe_crc_ba [1613], reason: Engine(s) hung, action: reset [ 26.751177] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace. [ 26.751178] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel [ 26.751178] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue. [ 26.751178] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it. [ 26.751179] [drm] GPU crash dump saved to /sys/class/drm/card0/error [ 26.751196] [drm:i915_reset_and_wakeup] resetting chip [ 26.851084] drm/i915: Resetting chip after gpu hang [ 26.851096] [drm:gen8_init_common_ring] Execlists enabled for render ring [ 26.851114] [drm:gen8_init_common_ring] Execlists enabled for blitter ring [ 26.851129] [drm:gen8_init_common_ring] Execlists enabled for bsd ring [ 26.851143] [drm:gen8_init_common_ring] Execlists enabled for video enhancement ring [ 26.851158] [drm:intel_guc_setup] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch SUCCESS, load SUCCESS [ 26.851159] [drm:intel_guc_setup] GuC fw status: fetch SUCCESS, load PENDING [ 26.852608] [drm:guc_ucode_xfer_dma] DMA status 0x10, GuC status 0x8002f0ec [ 26.852610] [drm:guc_ucode_xfer_dma] returning 0 [ 26.852611] [drm:intel_guc_setup] GuC fw status: fetch SUCCESS, load SUCCESS [ 26.852627] [drm:select_doorbell_register] assigned normal priority doorbell id 0x0 [ 26.852628] [drm:select_doorbell_cacheline] selected doorbell cacheline 0x40, next 0x80, linesize 64 [ 26.852635] [drm:guc_client_alloc] new priority 2 client ffff880271990580: ctx_index 0 [ 26.852636] [drm:guc_client_alloc] doorbell id 0, cacheline offset 0x40 [ 26.854419] [drm:i915_error_state_write] Resetting error state [ 26.854572] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 26.854665] [drm:drm_mode_addfb2] [FB:107] [ 26.857603] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 26.857607] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 26.857614] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 26.857615] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 26.857617] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 26.857619] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 26.857621] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 26.857622] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 26.857624] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 26.857625] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88007798f800 for pipe A [ 26.857626] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 26.857627] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 26.857628] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 26.857630] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 26.857631] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 26.857632] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 26.857633] [drm:intel_dump_pipe_config] requested mode: [ 26.857634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 26.857635] [drm:intel_dump_pipe_config] adjusted mode: [ 26.857637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 26.857638] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 26.857639] [drm:intel_dump_pipe_config] port clock: 270000 [ 26.857640] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 26.857641] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 26.857642] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 26.857643] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 26.857644] [drm:intel_dump_pipe_config] ips: 0 [ 26.857645] [drm:intel_dump_pipe_config] double wide: 0 [ 26.857647] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 26.857647] [drm:intel_dump_pipe_config] planes on this crtc [ 26.857648] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 26.857649] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 26.857650] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 26.857651] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 26.857653] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 26.857655] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 26.857657] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A [ 26.857659] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A [ 26.857660] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 26.857745] [drm:intel_power_well_enable] enabling always-on [ 26.857746] [drm:intel_power_well_enable] enabling DC off [ 26.857808] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 26.857812] [drm:intel_power_well_enable] enabling dpio-common-a [ 26.861311] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 26.861314] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 26.861316] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 26.861317] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 26.861318] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 26.861319] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 26.861320] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 26.861321] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 26.861322] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 26.861323] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 26.861324] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 26.861325] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 26.861326] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 26.861327] [drm:verify_single_dpll_state] PORT PLL A [ 26.861328] [drm:verify_single_dpll_state] PORT PLL B [ 26.861329] [drm:verify_single_dpll_state] PORT PLL C [ 26.861336] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26 [ 26.861337] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 26.861362] [drm:edp_panel_on] Turn eDP port A panel power on [ 26.861363] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 26.861366] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 26.861367] [drm:wait_panel_status] Wait complete [ 26.861368] [drm:wait_panel_on] Wait for panel power on [ 26.861370] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 26.888546] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 26.888549] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 26.888550] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 26.888593] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 26.929604] [drm:wait_panel_status] Wait complete [ 26.929611] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 26.929613] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 26.930347] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 26.930348] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 26.930581] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 26.931106] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 26.931147] [drm:skylake_pfit_enable] for crtc_state = ffff88007798f800 [ 26.931210] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 26.931212] [drm:intel_enable_pipe] enabling pipe A [ 26.931224] [drm:intel_edp_backlight_on] [ 26.931225] [drm:intel_panel_enable_backlight] pipe A [ 26.931226] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 26.932419] [drm:intel_psr_enable] PSR not supported on this platform [ 26.932421] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 26.932445] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 26.932450] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 26.935363] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 26.935366] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 26.935381] [drm:verify_single_dpll_state] PORT PLL A [ 26.939531] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 26.960050] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 26.964183] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 26.964187] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 26.964189] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 26.964198] [drm:intel_edp_backlight_off] [ 27.116132] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 27.116141] [drm:intel_disable_pipe] disabling pipe A [ 27.118239] [drm:edp_panel_off] Turn eDP port A panel power off [ 27.118243] [drm:wait_panel_off] Wait for panel power off time [ 27.118246] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 27.133185] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 27.133189] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 27.133190] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 27.133228] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 27.134339] [drm:wait_panel_status] Wait complete [ 27.134345] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26 [ 27.134352] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 27.134356] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 27.134359] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 27.134360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 27.134361] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 27.134362] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 27.134365] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 27.134367] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 27.134368] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 27.134369] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 27.134370] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 27.134372] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 27.134373] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 27.134374] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 27.134375] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 27.134377] [drm:verify_single_dpll_state] PORT PLL A [ 27.134378] [drm:verify_single_dpll_state] PORT PLL B [ 27.134379] [drm:verify_single_dpll_state] PORT PLL C [ 27.134383] [drm:intel_power_well_disable] disabling dpio-common-a [ 27.134387] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 27.134390] [drm:intel_power_well_disable] disabling DC off [ 27.134392] [drm:gen9_enable_dc5] Enabling DC5 [ 27.134393] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 27.134395] [drm:intel_power_well_disable] disabling always-on [ 27.135799] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 27.135901] [drm:drm_mode_addfb2] [FB:107] [ 27.139324] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 27.139328] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 27.139337] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 27.139338] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 27.139341] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 27.139342] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 27.139346] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 27.139347] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 27.139349] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 27.139351] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88007798d800 for pipe A [ 27.139352] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 27.139353] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 27.139354] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 27.139356] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 27.139357] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 27.139359] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 27.139360] [drm:intel_dump_pipe_config] requested mode: [ 27.139362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 27.139363] [drm:intel_dump_pipe_config] adjusted mode: [ 27.139365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 27.139367] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 27.139368] [drm:intel_dump_pipe_config] port clock: 270000 [ 27.139369] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 27.139370] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 27.139372] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 27.139373] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 27.139374] [drm:intel_dump_pipe_config] ips: 0 [ 27.139375] [drm:intel_dump_pipe_config] double wide: 0 [ 27.139377] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 27.139378] [drm:intel_dump_pipe_config] planes on this crtc [ 27.139379] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 27.139380] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 27.139382] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 27.139383] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 27.139385] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 27.139387] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 27.139390] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A [ 27.139391] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A [ 27.139393] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 27.139486] [drm:intel_power_well_enable] enabling always-on [ 27.139487] [drm:intel_power_well_enable] enabling DC off [ 27.139550] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 27.139554] [drm:intel_power_well_enable] enabling dpio-common-a [ 27.143418] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 27.143422] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 27.143424] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 27.143425] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 27.143426] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 27.143427] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 27.143429] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 27.143430] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 27.143431] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 27.143432] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 27.143433] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 27.143435] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 27.143436] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 27.143437] [drm:verify_single_dpll_state] PORT PLL A [ 27.143439] [drm:verify_single_dpll_state] PORT PLL B [ 27.143440] [drm:verify_single_dpll_state] PORT PLL C [ 27.143447] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26 [ 27.143448] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 27.143480] [drm:edp_panel_on] Turn eDP port A panel power on [ 27.143482] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 27.376643] [drm] RC6 on [ 27.378416] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 27.378418] [drm:wait_panel_status] Wait complete [ 27.378419] [drm:wait_panel_on] Wait for panel power on [ 27.378420] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 27.404725] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 27.404727] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 27.404727] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 27.404759] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 27.428391] [drm:wait_panel_status] Wait complete [ 27.428395] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 27.428396] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 27.429140] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 27.429141] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 27.429360] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 27.429878] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 27.429916] [drm:skylake_pfit_enable] for crtc_state = ffff88007798d800 [ 27.429978] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.429980] [drm:intel_enable_pipe] enabling pipe A [ 27.429988] [drm:intel_edp_backlight_on] [ 27.429988] [drm:intel_panel_enable_backlight] pipe A [ 27.429989] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 27.429991] [drm:intel_psr_enable] PSR not supported on this platform [ 27.429991] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 27.430008] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.430012] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.434127] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 27.434130] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 27.434142] [drm:verify_single_dpll_state] PORT PLL A [ 27.438254] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 27.458794] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 27.462931] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 27.462934] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 27.462935] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 27.462941] [drm:intel_edp_backlight_off] [ 27.520976] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 27.520983] [drm:intel_disable_pipe] disabling pipe A [ 27.525606] [drm:edp_panel_off] Turn eDP port A panel power off [ 27.525613] [drm:wait_panel_off] Wait for panel power off time [ 27.525614] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 27.538539] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 27.538541] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 27.538541] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 27.538558] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 27.539733] [drm:wait_panel_status] Wait complete [ 27.539737] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26 [ 27.539742] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 27.539745] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 27.539746] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 27.539746] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 27.539747] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 27.539747] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 27.539748] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 27.539749] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 27.539749] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 27.539749] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 27.539750] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 27.539751] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 27.539751] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 27.539751] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 27.539752] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 27.539752] [drm:verify_single_dpll_state] PORT PLL A [ 27.539753] [drm:verify_single_dpll_state] PORT PLL B [ 27.539753] [drm:verify_single_dpll_state] PORT PLL C [ 27.539755] [drm:intel_power_well_disable] disabling dpio-common-a [ 27.539757] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 27.539758] [drm:intel_power_well_disable] disabling DC off [ 27.539759] [drm:gen9_enable_dc5] Enabling DC5 [ 27.539760] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 27.539761] [drm:intel_power_well_disable] disabling always-on [ 27.540630] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 27.540715] [drm:drm_mode_addfb2] [FB:107] [ 27.542690] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 27.542693] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 27.542697] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 27.542697] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 27.542699] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 27.542700] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 27.542700] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 27.542701] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 27.542702] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d5800 for pipe A [ 27.542702] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 27.542703] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 27.542703] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 27.542704] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 27.542704] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 27.542704] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 27.542705] [drm:intel_dump_pipe_config] requested mode: [ 27.542706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 27.542706] [drm:intel_dump_pipe_config] adjusted mode: [ 27.542707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 27.542707] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 27.542708] [drm:intel_dump_pipe_config] port clock: 162000 [ 27.542708] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 27.542708] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 27.542709] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 27.542709] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 27.542710] [drm:intel_dump_pipe_config] ips: 0 [ 27.542710] [drm:intel_dump_pipe_config] double wide: 0 [ 27.542711] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 27.542711] [drm:intel_dump_pipe_config] planes on this crtc [ 27.542711] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 27.542712] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 27.542712] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 27.542713] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 27.542714] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 27.542715] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 27.542717] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B [ 27.542717] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A [ 27.542718] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 27.542787] [drm:intel_power_well_enable] enabling always-on [ 27.542787] [drm:intel_power_well_enable] enabling DC off [ 27.542849] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 27.542851] [drm:intel_power_well_enable] enabling power well 2 [ 27.542852] [drm:skl_set_power_well] Enabling power well 2 [ 27.543900] [drm:intel_power_well_enable] enabling dpio-common-bc [ 27.543902] [drm:intel_power_well_enable] enabling dpio-common-a [ 27.604400] [drm:intel_power_well_disable] disabling dpio-common-a [ 27.604404] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 27.608548] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 27.608550] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 27.608552] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 27.608552] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 27.608553] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 27.608553] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 27.608554] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 27.608554] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 27.608555] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 27.608555] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 27.608556] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 27.608556] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 27.608557] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 27.608558] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 27.608558] [drm:verify_single_dpll_state] PORT PLL A [ 27.608559] [drm:verify_single_dpll_state] PORT PLL B [ 27.608559] [drm:verify_single_dpll_state] PORT PLL C [ 27.608563] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26 [ 27.608563] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 27.610367] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 27.610368] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 27.611374] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 27.613388] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 27.613432] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d5800 [ 27.613470] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.613471] [drm:intel_enable_pipe] enabling pipe A [ 27.613494] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 27.613495] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 27.613524] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.613527] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.617638] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 27.617641] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 27.617652] [drm:verify_single_dpll_state] PORT PLL B [ 27.621775] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 27.642313] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 27.646447] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 27.646450] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 27.646451] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 27.646457] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 27.646468] [drm:intel_disable_pipe] disabling pipe A [ 27.650574] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26 [ 27.650580] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 27.650582] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 27.654647] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 27.654649] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 27.654650] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 27.654651] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 27.654652] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 27.654652] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 27.654653] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 27.654653] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 27.654654] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 27.654654] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 27.654655] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 27.654655] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 27.654656] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 27.654656] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 27.654657] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 27.654658] [drm:verify_single_dpll_state] PORT PLL A [ 27.654658] [drm:verify_single_dpll_state] PORT PLL B [ 27.654659] [drm:verify_single_dpll_state] PORT PLL C [ 27.654662] [drm:intel_power_well_disable] disabling dpio-common-bc [ 27.654663] [drm:intel_power_well_disable] disabling power well 2 [ 27.654665] [drm:skl_set_power_well] Disabling power well 2 [ 27.654667] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 27.654668] [drm:intel_power_well_disable] disabling DC off [ 27.654669] [drm:gen9_enable_dc5] Enabling DC5 [ 27.654670] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 27.654671] [drm:intel_power_well_disable] disabling always-on [ 27.655463] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 27.655545] [drm:drm_mode_addfb2] [FB:107] [ 27.657452] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 27.657454] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 27.657459] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 27.657459] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 27.657460] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 27.657461] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 27.657462] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 27.657463] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 27.657463] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88026e44a000 for pipe A [ 27.657464] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 27.657464] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 27.657465] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 27.657465] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 27.657466] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 27.657466] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 27.657466] [drm:intel_dump_pipe_config] requested mode: [ 27.657467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 27.657468] [drm:intel_dump_pipe_config] adjusted mode: [ 27.657468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 27.657469] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 27.657469] [drm:intel_dump_pipe_config] port clock: 162000 [ 27.657470] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 27.657470] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 27.657471] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 27.657471] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 27.657471] [drm:intel_dump_pipe_config] ips: 0 [ 27.657472] [drm:intel_dump_pipe_config] double wide: 0 [ 27.657472] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 27.657473] [drm:intel_dump_pipe_config] planes on this crtc [ 27.657473] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 27.657474] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 27.657474] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 27.657474] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 27.657476] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 27.657477] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 27.657478] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL B [ 27.657479] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe A [ 27.657480] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 27.657547] [drm:intel_power_well_enable] enabling always-on [ 27.657547] [drm:intel_power_well_enable] enabling DC off [ 27.657610] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 27.657611] [drm:intel_power_well_enable] enabling power well 2 [ 27.657612] [drm:skl_set_power_well] Enabling power well 2 [ 27.659110] [drm:intel_power_well_enable] enabling dpio-common-bc [ 27.659111] [drm:intel_power_well_enable] enabling dpio-common-a [ 27.659596] [drm:intel_power_well_disable] disabling dpio-common-a [ 27.659600] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 27.663662] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 27.663664] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 27.663666] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 27.663667] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 27.663667] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 27.663667] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 27.663668] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 27.663669] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 27.663669] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 27.663669] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 27.663670] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 27.663670] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 27.663671] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 27.663672] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 27.663672] [drm:verify_single_dpll_state] PORT PLL A [ 27.663673] [drm:verify_single_dpll_state] PORT PLL B [ 27.663673] [drm:verify_single_dpll_state] PORT PLL C [ 27.663677] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 1, on? 0) for crtc 26 [ 27.663677] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 27.664447] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 27.664448] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 27.665571] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 27.668850] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 27.668893] [drm:skylake_pfit_enable] for crtc_state = ffff88026e44a000 [ 27.668931] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.668933] [drm:intel_enable_pipe] enabling pipe A [ 27.668942] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 27.668943] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 27.669002] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.669006] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.673087] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 27.673090] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 27.673101] [drm:verify_single_dpll_state] PORT PLL B [ 27.677211] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 27.697745] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 27.701877] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 27.701880] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 27.701881] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 27.701887] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 27.701898] [drm:intel_disable_pipe] disabling pipe A [ 27.705993] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 26 [ 27.705999] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 27.706001] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 27.710059] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 27.710061] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 27.710063] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 27.710064] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 27.710064] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 27.710065] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 27.710065] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 27.710066] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 27.710066] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 27.710066] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 27.710067] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 27.710067] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 27.710068] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 27.710069] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 27.710069] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 27.710070] [drm:verify_single_dpll_state] PORT PLL A [ 27.710071] [drm:verify_single_dpll_state] PORT PLL B [ 27.710071] [drm:verify_single_dpll_state] PORT PLL C [ 27.710074] [drm:intel_power_well_disable] disabling dpio-common-bc [ 27.710075] [drm:intel_power_well_disable] disabling power well 2 [ 27.710077] [drm:skl_set_power_well] Disabling power well 2 [ 27.710079] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 27.710080] [drm:intel_power_well_disable] disabling DC off [ 27.710081] [drm:gen9_enable_dc5] Enabling DC5 [ 27.710082] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 27.710083] [drm:intel_power_well_disable] disabling always-on [ 27.710922] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 27.711003] [drm:drm_mode_addfb2] [FB:107] [ 27.713633] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 27.713636] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 27.713640] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 27.713641] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 27.713642] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 27.713643] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 27.713644] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 27.713644] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 27.713645] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d2000 for pipe A [ 27.713645] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 27.713646] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 27.713646] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 27.713647] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 27.713647] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 27.713648] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 27.713648] [drm:intel_dump_pipe_config] requested mode: [ 27.713649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 27.713649] [drm:intel_dump_pipe_config] adjusted mode: [ 27.713650] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 27.713651] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 27.713651] [drm:intel_dump_pipe_config] port clock: 162000 [ 27.713651] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 27.713652] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 27.713652] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 27.713653] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 27.713653] [drm:intel_dump_pipe_config] ips: 0 [ 27.713653] [drm:intel_dump_pipe_config] double wide: 0 [ 27.713654] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 27.713654] [drm:intel_dump_pipe_config] planes on this crtc [ 27.713655] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 27.713655] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 27.713656] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 27.713656] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 27.713657] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 27.713659] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 27.713660] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C [ 27.713660] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A [ 27.713661] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 27.713733] [drm:intel_power_well_enable] enabling always-on [ 27.713734] [drm:intel_power_well_enable] enabling DC off [ 27.713796] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 27.713798] [drm:intel_power_well_enable] enabling power well 2 [ 27.713799] [drm:skl_set_power_well] Enabling power well 2 [ 27.715264] [drm:intel_power_well_enable] enabling dpio-common-bc [ 27.715266] [drm:intel_power_well_enable] enabling dpio-common-a [ 27.717606] [drm:intel_power_well_disable] disabling dpio-common-a [ 27.717611] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 27.721723] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 27.721725] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 27.721727] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 27.721727] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 27.721728] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 27.721728] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 27.721729] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 27.721729] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 27.721729] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 27.721730] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 27.721730] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 27.721731] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 27.721732] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 27.721732] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 27.721733] [drm:verify_single_dpll_state] PORT PLL A [ 27.721733] [drm:verify_single_dpll_state] PORT PLL B [ 27.721734] [drm:verify_single_dpll_state] PORT PLL C [ 27.721737] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26 [ 27.721738] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 27.724901] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 27.724902] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 27.725425] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 27.725957] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 27.725957] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 27.729028] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 27.729071] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d2000 [ 27.729108] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.729109] [drm:intel_enable_pipe] enabling pipe A [ 27.729160] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.729162] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.733272] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 27.733274] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 27.733284] [drm:verify_single_dpll_state] PORT PLL C [ 27.737381] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 27.757954] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 27.762060] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 27.762062] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 27.762063] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 27.762074] [drm:intel_disable_pipe] disabling pipe A [ 27.766192] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26 [ 27.766197] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 27.766200] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 27.769961] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 27.769963] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 27.769964] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 27.769965] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 27.769966] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 27.769966] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 27.769967] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 27.769967] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 27.769968] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 27.769968] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 27.769969] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 27.769969] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 27.769970] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 27.769970] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 27.769971] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 27.769972] [drm:verify_single_dpll_state] PORT PLL A [ 27.769972] [drm:verify_single_dpll_state] PORT PLL B [ 27.769973] [drm:verify_single_dpll_state] PORT PLL C [ 27.769976] [drm:intel_power_well_disable] disabling dpio-common-bc [ 27.769977] [drm:intel_power_well_disable] disabling power well 2 [ 27.769979] [drm:skl_set_power_well] Disabling power well 2 [ 27.769981] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 27.769982] [drm:intel_power_well_disable] disabling DC off [ 27.769983] [drm:gen9_enable_dc5] Enabling DC5 [ 27.769984] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 27.769985] [drm:intel_power_well_disable] disabling always-on [ 27.770778] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 27.770860] [drm:drm_mode_addfb2] [FB:107] [ 27.772741] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 27.772744] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 27.772748] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 27.772749] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 27.772750] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 27.772751] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 27.772751] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 27.772752] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 27.772753] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88026e448800 for pipe A [ 27.772753] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 27.772754] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 27.772754] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 27.772755] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 27.772755] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 27.772756] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 27.772756] [drm:intel_dump_pipe_config] requested mode: [ 27.772757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 27.772757] [drm:intel_dump_pipe_config] adjusted mode: [ 27.772758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 27.772759] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 27.772759] [drm:intel_dump_pipe_config] port clock: 162000 [ 27.772759] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 27.772760] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 27.772760] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 27.772761] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 27.772761] [drm:intel_dump_pipe_config] ips: 0 [ 27.772761] [drm:intel_dump_pipe_config] double wide: 0 [ 27.772762] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 27.772762] [drm:intel_dump_pipe_config] planes on this crtc [ 27.772763] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 27.772763] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 27.772764] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 27.772764] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 27.772765] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 27.772767] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 27.772768] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL C [ 27.772769] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe A [ 27.772769] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 27.772837] [drm:intel_power_well_enable] enabling always-on [ 27.772837] [drm:intel_power_well_enable] enabling DC off [ 27.772899] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 27.772901] [drm:intel_power_well_enable] enabling power well 2 [ 27.772902] [drm:skl_set_power_well] Enabling power well 2 [ 27.773479] [drm:intel_power_well_enable] enabling dpio-common-bc [ 27.773480] [drm:intel_power_well_enable] enabling dpio-common-a [ 27.774185] [drm:intel_power_well_disable] disabling dpio-common-a [ 27.774188] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 27.778104] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 27.778106] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 27.778108] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 27.778108] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 27.778109] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 27.778109] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 27.778110] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 27.778110] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 27.778111] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 27.778111] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 27.778111] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 27.778112] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 27.778113] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 27.778113] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 27.778114] [drm:verify_single_dpll_state] PORT PLL A [ 27.778115] [drm:verify_single_dpll_state] PORT PLL B [ 27.778115] [drm:verify_single_dpll_state] PORT PLL C [ 27.778120] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 1, on? 0) for crtc 26 [ 27.778120] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 27.780319] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 27.780320] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 27.780881] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 27.781426] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 27.781426] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 27.784034] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 27.784076] [drm:skylake_pfit_enable] for crtc_state = ffff88026e448800 [ 27.784114] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.784115] [drm:intel_enable_pipe] enabling pipe A [ 27.784160] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.784163] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 27.788269] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 27.788271] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 27.788281] [drm:verify_single_dpll_state] PORT PLL C [ 27.792443] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 27.812959] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 27.817102] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 27.817104] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 27.817105] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 27.817117] [drm:intel_disable_pipe] disabling pipe A [ 27.821236] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 1, on? 1) for crtc 26 [ 27.821241] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 27.821244] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 27.825312] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 27.825313] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 27.825315] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 27.825316] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 27.825317] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 27.825317] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 27.825318] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 27.825318] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 27.825319] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 27.825319] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 27.825319] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 27.825320] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 27.825321] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 27.825321] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 27.825322] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 27.825323] [drm:verify_single_dpll_state] PORT PLL A [ 27.825323] [drm:verify_single_dpll_state] PORT PLL B [ 27.825324] [drm:verify_single_dpll_state] PORT PLL C [ 27.825327] [drm:intel_power_well_disable] disabling dpio-common-bc [ 27.825328] [drm:intel_power_well_disable] disabling power well 2 [ 27.825330] [drm:skl_set_power_well] Disabling power well 2 [ 27.825332] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 27.825334] [drm:intel_power_well_disable] disabling DC off [ 27.825335] [drm:gen9_enable_dc5] Enabling DC5 [ 27.825335] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 27.825336] [drm:intel_power_well_disable] disabling always-on [ 27.826089] kms_pipe_crc_basic: starting subtest read-crc-pipe-B [ 27.826155] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 27.826233] [drm:drm_mode_addfb2] [FB:107] [ 27.828915] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 27.828917] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 27.828922] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 27.828922] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 27.828924] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 27.828924] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 27.828926] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 27.828926] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 27.828927] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 27.828928] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88026e449800 for pipe B [ 27.828928] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 27.828929] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 27.828929] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 27.828930] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 27.828930] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 27.828930] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 27.828931] [drm:intel_dump_pipe_config] requested mode: [ 27.828932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 27.828932] [drm:intel_dump_pipe_config] adjusted mode: [ 27.828933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 27.828933] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 27.828934] [drm:intel_dump_pipe_config] port clock: 270000 [ 27.828934] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 27.828934] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 27.828935] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 27.828935] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 27.828936] [drm:intel_dump_pipe_config] ips: 0 [ 27.828936] [drm:intel_dump_pipe_config] double wide: 0 [ 27.828937] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 27.828937] [drm:intel_dump_pipe_config] planes on this crtc [ 27.828938] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] enabled [ 27.828938] [drm:intel_dump_pipe_config] FB:60, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 27.828939] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+0+0 dst 0x0+0+0 [ 27.828939] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 27.828940] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 27.828940] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 27.828941] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 27.828942] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 27.828944] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL A [ 27.828944] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe B [ 27.828945] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 27.829013] [drm:intel_power_well_enable] enabling always-on [ 27.829013] [drm:intel_power_well_enable] enabling DC off [ 27.829075] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 27.829077] [drm:intel_power_well_enable] enabling power well 2 [ 27.829078] [drm:skl_set_power_well] Enabling power well 2 [ 27.830076] [drm:intel_power_well_enable] enabling dpio-common-a [ 27.833348] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 27.833349] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 27.833350] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 27.833351] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 27.833351] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 27.833352] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 27.833352] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 27.833353] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 27.833353] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 27.833353] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 27.833354] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 27.833354] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 27.833355] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 27.833355] [drm:verify_single_dpll_state] PORT PLL A [ 27.833356] [drm:verify_single_dpll_state] PORT PLL B [ 27.833356] [drm:verify_single_dpll_state] PORT PLL C [ 27.833362] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 2, on? 0) for crtc 31 [ 27.833362] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 27.833382] [drm:edp_panel_on] Turn eDP port A panel power on [ 27.833383] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 27.833386] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 27.833386] [drm:wait_panel_status] Wait complete [ 27.833387] [drm:wait_panel_on] Wait for panel power on [ 27.833388] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 27.859698] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 27.859700] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 27.859701] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 27.859717] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 27.885561] [drm:wait_panel_status] Wait complete [ 27.885565] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 27.885566] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 27.886283] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 27.886284] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 27.886506] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 27.887027] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 27.887065] [drm:skylake_pfit_enable] for crtc_state = ffff88026e449800 [ 27.887123] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 27.887124] [drm:intel_enable_pipe] enabling pipe B [ 27.887145] [drm:intel_edp_backlight_on] [ 27.887146] [drm:intel_panel_enable_backlight] pipe B [ 27.887146] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 27.887864] [drm:intel_psr_enable] PSR not supported on this platform [ 27.887865] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 27.887890] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 27.891286] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 27.891288] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 27.891300] [drm:verify_single_dpll_state] PORT PLL A [ 27.895427] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 27.915975] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 27.920104] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 27.920106] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 27.920108] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 27.920114] [drm:intel_edp_backlight_off] [ 28.097812] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 28.097820] [drm:intel_disable_pipe] disabling pipe B [ 28.101387] [drm:edp_panel_off] Turn eDP port A panel power off [ 28.101392] [drm:wait_panel_off] Wait for panel power off time [ 28.101393] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 28.114324] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 28.114326] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 28.114327] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 28.114342] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 28.119159] [drm:wait_panel_status] Wait complete [ 28.119162] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 2, on? 1) for crtc 31 [ 28.119168] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 28.119170] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.119171] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.119172] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.119172] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.119172] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.119173] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.119173] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.119174] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.119174] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.119174] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 28.119175] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.119175] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.119176] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.119176] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.119177] [drm:verify_single_dpll_state] PORT PLL A [ 28.119177] [drm:verify_single_dpll_state] PORT PLL B [ 28.119178] [drm:verify_single_dpll_state] PORT PLL C [ 28.119180] [drm:intel_power_well_disable] disabling power well 2 [ 28.119183] [drm:skl_set_power_well] Disabling power well 2 [ 28.119184] [drm:intel_power_well_disable] disabling dpio-common-a [ 28.119185] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 28.119186] [drm:intel_power_well_disable] disabling DC off [ 28.119187] [drm:gen9_enable_dc5] Enabling DC5 [ 28.119187] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 28.119189] [drm:intel_power_well_disable] disabling always-on [ 28.119991] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.120072] [drm:drm_mode_addfb2] [FB:107] [ 28.121971] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.121974] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 28.121978] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 28.121978] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 28.121980] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.121980] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 28.121982] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 28.121982] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 28.121983] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 28.121984] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88007798f000 for pipe B [ 28.121984] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 28.121984] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 28.121985] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 28.121985] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 28.121986] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 28.121986] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 28.121987] [drm:intel_dump_pipe_config] requested mode: [ 28.121987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 28.121988] [drm:intel_dump_pipe_config] adjusted mode: [ 28.121989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 28.121989] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 28.121990] [drm:intel_dump_pipe_config] port clock: 270000 [ 28.121990] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 28.121990] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 28.121991] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 28.121991] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 28.121992] [drm:intel_dump_pipe_config] ips: 0 [ 28.121992] [drm:intel_dump_pipe_config] double wide: 0 [ 28.121993] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 28.121993] [drm:intel_dump_pipe_config] planes on this crtc [ 28.121993] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 28.121994] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 28.121994] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 28.121995] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 28.121996] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 28.121997] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 28.121998] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL A [ 28.121999] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe B [ 28.121999] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.122067] [drm:intel_power_well_enable] enabling always-on [ 28.122067] [drm:intel_power_well_enable] enabling DC off [ 28.122129] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 28.122131] [drm:intel_power_well_enable] enabling power well 2 [ 28.122132] [drm:skl_set_power_well] Enabling power well 2 [ 28.122966] [drm:intel_power_well_enable] enabling dpio-common-a [ 28.125036] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.125038] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.125039] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.125039] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.125040] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.125040] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.125040] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.125041] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.125041] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.125042] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.125042] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.125043] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.125043] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.125044] [drm:verify_single_dpll_state] PORT PLL A [ 28.125044] [drm:verify_single_dpll_state] PORT PLL B [ 28.125045] [drm:verify_single_dpll_state] PORT PLL C [ 28.125050] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 2, on? 0) for crtc 31 [ 28.125050] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 28.125071] [drm:edp_panel_on] Turn eDP port A panel power on [ 28.125071] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 28.229059] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000060 [ 28.251114] [drm:wait_panel_status] Wait complete [ 28.251117] [drm:wait_panel_on] Wait for panel power on [ 28.251118] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 28.277433] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 28.277434] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 28.277435] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 28.277451] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 28.307902] [drm:wait_panel_status] Wait complete [ 28.307906] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 28.307908] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 28.308632] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 28.308632] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 28.308854] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 28.309376] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 28.309413] [drm:skylake_pfit_enable] for crtc_state = ffff88007798f000 [ 28.309487] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 28.309488] [drm:intel_enable_pipe] enabling pipe B [ 28.309502] [drm:intel_edp_backlight_on] [ 28.309503] [drm:intel_panel_enable_backlight] pipe B [ 28.309503] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 28.309505] [drm:intel_psr_enable] PSR not supported on this platform [ 28.309505] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 28.309531] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 28.313641] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 28.313643] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 28.313655] [drm:verify_single_dpll_state] PORT PLL A [ 28.317794] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 28.338340] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 28.342464] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 28.342467] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 28.342468] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.342474] [drm:intel_edp_backlight_off] [ 28.412257] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 28.412272] [drm:intel_disable_pipe] disabling pipe B [ 28.418389] [drm:edp_panel_off] Turn eDP port A panel power off [ 28.418395] [drm:wait_panel_off] Wait for panel power off time [ 28.418397] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000060 [ 28.431326] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 28.431328] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 28.431328] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 28.431343] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 28.433744] [drm:wait_panel_status] Wait complete [ 28.433748] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 2, on? 1) for crtc 31 [ 28.433753] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 28.433756] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.433757] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.433757] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.433758] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.433758] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.433758] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.433759] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.433759] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.433760] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.433760] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 28.433761] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.433761] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.433762] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.433762] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.433763] [drm:verify_single_dpll_state] PORT PLL A [ 28.433763] [drm:verify_single_dpll_state] PORT PLL B [ 28.433764] [drm:verify_single_dpll_state] PORT PLL C [ 28.433766] [drm:intel_power_well_disable] disabling power well 2 [ 28.433768] [drm:skl_set_power_well] Disabling power well 2 [ 28.433769] [drm:intel_power_well_disable] disabling dpio-common-a [ 28.433771] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 28.433772] [drm:intel_power_well_disable] disabling DC off [ 28.433773] [drm:gen9_enable_dc5] Enabling DC5 [ 28.433773] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 28.433774] [drm:intel_power_well_disable] disabling always-on [ 28.434574] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.434655] [drm:drm_mode_addfb2] [FB:107] [ 28.436514] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.436517] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 28.436521] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 28.436522] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 28.436523] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 28.436524] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 28.436524] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 28.436525] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 28.436526] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff880077988000 for pipe B [ 28.436526] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 28.436527] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 28.436527] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 28.436528] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 28.436528] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 28.436529] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 28.436529] [drm:intel_dump_pipe_config] requested mode: [ 28.436530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 28.436530] [drm:intel_dump_pipe_config] adjusted mode: [ 28.436531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 28.436531] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 28.436532] [drm:intel_dump_pipe_config] port clock: 162000 [ 28.436532] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 28.436533] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 28.436533] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 28.436534] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 28.436534] [drm:intel_dump_pipe_config] ips: 0 [ 28.436534] [drm:intel_dump_pipe_config] double wide: 0 [ 28.436535] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 28.436535] [drm:intel_dump_pipe_config] planes on this crtc [ 28.436536] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 28.436536] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 28.436537] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 28.436537] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 28.436538] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 28.436540] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 28.436541] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 28.436542] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 28.436542] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.436610] [drm:intel_power_well_enable] enabling always-on [ 28.436610] [drm:intel_power_well_enable] enabling DC off [ 28.436672] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 28.436674] [drm:intel_power_well_enable] enabling power well 2 [ 28.436675] [drm:skl_set_power_well] Enabling power well 2 [ 28.444338] [drm:intel_power_well_enable] enabling dpio-common-bc [ 28.444339] [drm:intel_power_well_enable] enabling dpio-common-a [ 28.445945] [drm:intel_power_well_disable] disabling dpio-common-a [ 28.445949] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 28.449788] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 28.449789] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.449791] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.449792] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.449792] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.449793] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.449793] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.449794] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.449794] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.449795] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.449795] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 28.449796] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.449796] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.449797] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.449798] [drm:verify_single_dpll_state] PORT PLL A [ 28.449798] [drm:verify_single_dpll_state] PORT PLL B [ 28.449799] [drm:verify_single_dpll_state] PORT PLL C [ 28.449803] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 28.449803] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 28.452192] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 28.452193] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 28.452944] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 28.456267] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 28.456314] [drm:skylake_pfit_enable] for crtc_state = ffff880077988000 [ 28.456351] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 28.456352] [drm:intel_enable_pipe] enabling pipe B [ 28.456378] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 28.456379] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 28.456415] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 28.460530] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.460534] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 28.460544] [drm:verify_single_dpll_state] PORT PLL B [ 28.464662] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 28.485198] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 28.489332] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 28.489334] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 28.489335] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.489341] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B [ 28.489352] [drm:intel_disable_pipe] disabling pipe B [ 28.495344] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31 [ 28.495350] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 28.495353] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 28.498812] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 28.498814] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.498816] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.498817] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.498817] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.498818] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.498818] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.498819] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.498819] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.498820] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.498820] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 28.498821] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.498821] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.498822] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.498823] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.498823] [drm:verify_single_dpll_state] PORT PLL A [ 28.498824] [drm:verify_single_dpll_state] PORT PLL B [ 28.498824] [drm:verify_single_dpll_state] PORT PLL C [ 28.498828] [drm:intel_power_well_disable] disabling dpio-common-bc [ 28.498828] [drm:intel_power_well_disable] disabling power well 2 [ 28.498831] [drm:skl_set_power_well] Disabling power well 2 [ 28.498833] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 28.498833] [drm:intel_power_well_disable] disabling DC off [ 28.498834] [drm:gen9_enable_dc5] Enabling DC5 [ 28.498835] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 28.498836] [drm:intel_power_well_disable] disabling always-on [ 28.499615] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.499696] [drm:drm_mode_addfb2] [FB:107] [ 28.501559] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.501562] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 28.501566] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 28.501567] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 28.501568] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 28.501569] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 28.501569] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 28.501570] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 28.501571] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88026e44e000 for pipe B [ 28.501571] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 28.501572] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 28.501572] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 28.501573] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 28.501573] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 28.501574] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 28.501574] [drm:intel_dump_pipe_config] requested mode: [ 28.501575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 28.501575] [drm:intel_dump_pipe_config] adjusted mode: [ 28.501576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 28.501577] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 28.501577] [drm:intel_dump_pipe_config] port clock: 162000 [ 28.501577] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 28.501578] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 28.501578] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 28.501579] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 28.501579] [drm:intel_dump_pipe_config] ips: 0 [ 28.501579] [drm:intel_dump_pipe_config] double wide: 0 [ 28.501580] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 28.501580] [drm:intel_dump_pipe_config] planes on this crtc [ 28.501581] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 28.501581] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 28.501582] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 28.501582] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 28.501583] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 28.501585] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 28.501586] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 28.501587] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 28.501587] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.501654] [drm:intel_power_well_enable] enabling always-on [ 28.501655] [drm:intel_power_well_enable] enabling DC off [ 28.501717] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 28.501719] [drm:intel_power_well_enable] enabling power well 2 [ 28.501720] [drm:skl_set_power_well] Enabling power well 2 [ 28.532376] [drm:intel_power_well_enable] enabling dpio-common-bc [ 28.532378] [drm:intel_power_well_enable] enabling dpio-common-a [ 28.534443] [drm:intel_power_well_disable] disabling dpio-common-a [ 28.534447] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 28.538466] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 28.538467] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.538470] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.538471] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.538471] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.538472] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.538472] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.538473] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.538473] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.538474] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.538474] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 28.538475] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.538475] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.538476] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.538477] [drm:verify_single_dpll_state] PORT PLL A [ 28.538477] [drm:verify_single_dpll_state] PORT PLL B [ 28.538478] [drm:verify_single_dpll_state] PORT PLL C [ 28.538482] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 28.538483] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 28.539228] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 28.539229] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 28.541943] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 28.546025] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 28.546066] [drm:skylake_pfit_enable] for crtc_state = ffff88026e44e000 [ 28.546104] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 28.546105] [drm:intel_enable_pipe] enabling pipe B [ 28.546129] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 28.546130] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 28.546161] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 28.550294] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.550297] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 28.550308] [drm:verify_single_dpll_state] PORT PLL B [ 28.554420] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 28.574955] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 28.579077] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 28.579080] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 28.579081] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.579086] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B [ 28.579099] [drm:intel_disable_pipe] disabling pipe B [ 28.583177] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31 [ 28.583182] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 28.583185] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 28.586312] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 28.586314] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.586316] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.586316] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.586317] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.586317] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.586318] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.586318] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.586319] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.586319] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.586320] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 28.586320] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.586321] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.586321] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.586322] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.586323] [drm:verify_single_dpll_state] PORT PLL A [ 28.586323] [drm:verify_single_dpll_state] PORT PLL B [ 28.586324] [drm:verify_single_dpll_state] PORT PLL C [ 28.586327] [drm:intel_power_well_disable] disabling dpio-common-bc [ 28.586328] [drm:intel_power_well_disable] disabling power well 2 [ 28.586331] [drm:skl_set_power_well] Disabling power well 2 [ 28.586332] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 28.586333] [drm:intel_power_well_disable] disabling DC off [ 28.586334] [drm:gen9_enable_dc5] Enabling DC5 [ 28.586335] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 28.586336] [drm:intel_power_well_disable] disabling always-on [ 28.587136] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.587217] [drm:drm_mode_addfb2] [FB:107] [ 28.589127] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.589129] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 28.589133] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 28.589134] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 28.589135] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 28.589136] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 28.589136] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 28.589137] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 28.589138] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88026e448800 for pipe B [ 28.589138] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 28.589139] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 28.589139] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 28.589140] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 28.589140] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 28.589141] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 28.589141] [drm:intel_dump_pipe_config] requested mode: [ 28.589142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 28.589142] [drm:intel_dump_pipe_config] adjusted mode: [ 28.589143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 28.589144] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 28.589144] [drm:intel_dump_pipe_config] port clock: 162000 [ 28.589144] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 28.589145] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 28.589145] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 28.589146] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 28.589146] [drm:intel_dump_pipe_config] ips: 0 [ 28.589146] [drm:intel_dump_pipe_config] double wide: 0 [ 28.589147] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 28.589147] [drm:intel_dump_pipe_config] planes on this crtc [ 28.589148] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 28.589148] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 28.589149] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 28.589149] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 28.589150] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 28.589152] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 28.589153] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL C [ 28.589154] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe B [ 28.589154] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.589222] [drm:intel_power_well_enable] enabling always-on [ 28.589222] [drm:intel_power_well_enable] enabling DC off [ 28.589285] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 28.589286] [drm:intel_power_well_enable] enabling power well 2 [ 28.589287] [drm:skl_set_power_well] Enabling power well 2 [ 28.590376] [drm:intel_power_well_enable] enabling dpio-common-bc [ 28.590378] [drm:intel_power_well_enable] enabling dpio-common-a [ 28.592477] [drm:intel_power_well_disable] disabling dpio-common-a [ 28.592481] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 28.596546] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 28.596547] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.596549] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.596550] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.596551] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.596551] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.596551] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.596552] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.596552] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.596553] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.596553] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 28.596554] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.596554] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.596555] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.596556] [drm:verify_single_dpll_state] PORT PLL A [ 28.596556] [drm:verify_single_dpll_state] PORT PLL B [ 28.596557] [drm:verify_single_dpll_state] PORT PLL C [ 28.596561] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 2, on? 0) for crtc 31 [ 28.596561] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 28.598050] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 28.598051] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 28.598389] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 28.598390] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 28.598615] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 28.599176] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 28.599177] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 28.601729] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 28.601771] [drm:skylake_pfit_enable] for crtc_state = ffff88026e448800 [ 28.601808] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 28.601810] [drm:intel_enable_pipe] enabling pipe B [ 28.601854] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 28.605965] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.605968] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 28.605978] [drm:verify_single_dpll_state] PORT PLL C [ 28.610090] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 28.630642] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 28.634767] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 28.634770] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 28.634771] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.634782] [drm:intel_disable_pipe] disabling pipe B [ 28.640745] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 2, on? 1) for crtc 31 [ 28.640750] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 28.640753] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 28.644796] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 28.644798] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.644799] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.644800] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.644801] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.644801] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.644801] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.644802] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.644802] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.644803] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.644803] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 28.644804] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.644804] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.644805] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.644806] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.644806] [drm:verify_single_dpll_state] PORT PLL A [ 28.644807] [drm:verify_single_dpll_state] PORT PLL B [ 28.644808] [drm:verify_single_dpll_state] PORT PLL C [ 28.644811] [drm:intel_power_well_disable] disabling dpio-common-bc [ 28.644812] [drm:intel_power_well_disable] disabling power well 2 [ 28.644814] [drm:skl_set_power_well] Disabling power well 2 [ 28.644816] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 28.644817] [drm:intel_power_well_disable] disabling DC off [ 28.644818] [drm:gen9_enable_dc5] Enabling DC5 [ 28.644818] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 28.644820] [drm:intel_power_well_disable] disabling always-on [ 28.645596] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.645679] [drm:drm_mode_addfb2] [FB:107] [ 28.647582] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.647585] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 28.647589] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 28.647590] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 28.647591] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 28.647592] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 28.647593] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 28.647593] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 28.647594] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802709d3800 for pipe B [ 28.647595] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 28.647595] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 28.647595] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 28.647596] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 28.647596] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 28.647597] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 28.647597] [drm:intel_dump_pipe_config] requested mode: [ 28.647598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 28.647598] [drm:intel_dump_pipe_config] adjusted mode: [ 28.647599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 28.647600] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 28.647600] [drm:intel_dump_pipe_config] port clock: 162000 [ 28.647600] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 28.647601] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 28.647601] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 28.647602] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 28.647602] [drm:intel_dump_pipe_config] ips: 0 [ 28.647602] [drm:intel_dump_pipe_config] double wide: 0 [ 28.647603] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 28.647604] [drm:intel_dump_pipe_config] planes on this crtc [ 28.647604] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 28.647604] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 28.647605] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 28.647605] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 28.647606] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 28.647608] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 28.647609] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL C [ 28.647610] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe B [ 28.647610] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.647678] [drm:intel_power_well_enable] enabling always-on [ 28.647679] [drm:intel_power_well_enable] enabling DC off [ 28.647741] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 28.647743] [drm:intel_power_well_enable] enabling power well 2 [ 28.647743] [drm:skl_set_power_well] Enabling power well 2 [ 28.648166] [drm:intel_power_well_enable] enabling dpio-common-bc [ 28.648167] [drm:intel_power_well_enable] enabling dpio-common-a [ 28.649839] [drm:intel_power_well_disable] disabling dpio-common-a [ 28.649843] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 28.653893] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 28.653895] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.653897] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.653897] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.653898] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.653898] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.653899] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.653899] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.653900] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.653900] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.653900] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 28.653901] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.653902] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.653902] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.653903] [drm:verify_single_dpll_state] PORT PLL A [ 28.653904] [drm:verify_single_dpll_state] PORT PLL B [ 28.653904] [drm:verify_single_dpll_state] PORT PLL C [ 28.653908] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 2, on? 0) for crtc 31 [ 28.653909] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 28.656423] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 28.656424] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 28.656790] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 28.656791] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 28.657018] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 28.657548] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 28.657548] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 28.659502] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 28.659546] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d3800 [ 28.659584] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 28.659586] [drm:intel_enable_pipe] enabling pipe B [ 28.659634] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 28.663735] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.663737] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 28.663748] [drm:verify_single_dpll_state] PORT PLL C [ 28.667877] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 28.688415] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 28.692534] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 28.692537] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 28.692538] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.692550] [drm:intel_disable_pipe] disabling pipe B [ 28.698490] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 2, on? 1) for crtc 31 [ 28.698496] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 28.698498] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 28.702139] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 28.702141] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.702143] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.702144] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.702144] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.702145] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.702145] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.702146] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.702146] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.702147] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.702147] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 28.702148] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.702148] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.702149] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.702150] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.702150] [drm:verify_single_dpll_state] PORT PLL A [ 28.702151] [drm:verify_single_dpll_state] PORT PLL B [ 28.702151] [drm:verify_single_dpll_state] PORT PLL C [ 28.702154] [drm:intel_power_well_disable] disabling dpio-common-bc [ 28.702155] [drm:intel_power_well_disable] disabling power well 2 [ 28.702158] [drm:skl_set_power_well] Disabling power well 2 [ 28.702159] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 28.702160] [drm:intel_power_well_disable] disabling DC off [ 28.702161] [drm:gen9_enable_dc5] Enabling DC5 [ 28.702162] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 28.702163] [drm:intel_power_well_disable] disabling always-on [ 28.702966] kms_pipe_crc_basic: starting subtest read-crc-pipe-B-frame-sequence [ 28.703066] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.703147] [drm:drm_mode_addfb2] [FB:107] [ 28.705076] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.705078] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 28.705084] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 28.705084] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 28.705086] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.705086] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 28.705089] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 28.705090] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 28.705090] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 28.705091] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802709d2000 for pipe B [ 28.705092] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 28.705092] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 28.705093] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 28.705093] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 28.705094] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 28.705094] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 28.705094] [drm:intel_dump_pipe_config] requested mode: [ 28.705095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 28.705095] [drm:intel_dump_pipe_config] adjusted mode: [ 28.705096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 28.705097] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 28.705097] [drm:intel_dump_pipe_config] port clock: 270000 [ 28.705097] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 28.705098] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 28.705098] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 28.705099] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 28.705099] [drm:intel_dump_pipe_config] ips: 0 [ 28.705099] [drm:intel_dump_pipe_config] double wide: 0 [ 28.705100] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 28.705101] [drm:intel_dump_pipe_config] planes on this crtc [ 28.705101] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 28.705102] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 28.705103] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 28.705103] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 28.705104] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 28.705105] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 28.705107] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL A [ 28.705107] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe B [ 28.705111] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.705185] [drm:intel_power_well_enable] enabling always-on [ 28.705185] [drm:intel_power_well_enable] enabling DC off [ 28.705247] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 28.705249] [drm:intel_power_well_enable] enabling power well 2 [ 28.705250] [drm:skl_set_power_well] Enabling power well 2 [ 28.707275] [drm:intel_power_well_enable] enabling dpio-common-a [ 28.709218] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.709220] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.709221] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.709221] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.709221] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.709222] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.709222] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.709223] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.709223] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.709224] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.709224] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.709224] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.709225] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.709225] [drm:verify_single_dpll_state] PORT PLL A [ 28.709227] [drm:verify_single_dpll_state] PORT PLL B [ 28.709229] [drm:verify_single_dpll_state] PORT PLL C [ 28.709238] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 2, on? 0) for crtc 31 [ 28.709238] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 28.709259] [drm:edp_panel_on] Turn eDP port A panel power on [ 28.709259] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 28.709263] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 28.709264] [drm:wait_panel_status] Wait complete [ 28.709264] [drm:wait_panel_on] Wait for panel power on [ 28.709265] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 28.735589] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 28.735591] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 28.735591] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 28.735604] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 28.763044] [drm:wait_panel_status] Wait complete [ 28.763048] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 28.763049] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 28.763774] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 28.763774] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 28.763991] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 28.764506] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 28.764542] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d2000 [ 28.764599] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 28.764601] [drm:intel_enable_pipe] enabling pipe B [ 28.764608] [drm:intel_edp_backlight_on] [ 28.764608] [drm:intel_panel_enable_backlight] pipe B [ 28.764609] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 28.765971] [drm:intel_psr_enable] PSR not supported on this platform [ 28.765973] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 28.765999] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 28.768741] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 28.768744] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 28.768755] [drm:verify_single_dpll_state] PORT PLL A [ 28.772894] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 28.793422] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 28.797563] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 28.797565] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 28.797566] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.797573] [drm:intel_edp_backlight_off] [ 28.927632] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 28.927641] [drm:intel_disable_pipe] disabling pipe B [ 28.930260] [drm:edp_panel_off] Turn eDP port A panel power off [ 28.930270] [drm:wait_panel_off] Wait for panel power off time [ 28.930271] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 28.943211] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 28.943213] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 28.943214] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 28.943228] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 28.944394] [drm:wait_panel_status] Wait complete [ 28.944397] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 2, on? 1) for crtc 31 [ 28.944402] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 28.944405] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.944406] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.944406] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.944407] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.944407] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.944407] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.944408] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.944408] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.944409] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.944409] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 28.944410] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.944410] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.944411] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.944411] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.944411] [drm:verify_single_dpll_state] PORT PLL A [ 28.944412] [drm:verify_single_dpll_state] PORT PLL B [ 28.944412] [drm:verify_single_dpll_state] PORT PLL C [ 28.944414] [drm:intel_power_well_disable] disabling power well 2 [ 28.944417] [drm:skl_set_power_well] Disabling power well 2 [ 28.944418] [drm:intel_power_well_disable] disabling dpio-common-a [ 28.944419] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 28.944420] [drm:intel_power_well_disable] disabling DC off [ 28.944421] [drm:gen9_enable_dc5] Enabling DC5 [ 28.944422] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 28.944423] [drm:intel_power_well_disable] disabling always-on [ 28.945207] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.945289] [drm:drm_mode_addfb2] [FB:107] [ 28.947204] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 28.947207] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 28.947211] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 28.947212] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 28.947213] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.947214] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 28.947216] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 28.947216] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 28.947217] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 28.947217] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802709d7800 for pipe B [ 28.947218] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 28.947218] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 28.947219] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 28.947219] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 28.947220] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 28.947220] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 28.947220] [drm:intel_dump_pipe_config] requested mode: [ 28.947221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 28.947222] [drm:intel_dump_pipe_config] adjusted mode: [ 28.947222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 28.947223] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 28.947223] [drm:intel_dump_pipe_config] port clock: 270000 [ 28.947224] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 28.947224] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 28.947225] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 28.947225] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 28.947225] [drm:intel_dump_pipe_config] ips: 0 [ 28.947226] [drm:intel_dump_pipe_config] double wide: 0 [ 28.947226] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 28.947227] [drm:intel_dump_pipe_config] planes on this crtc [ 28.947227] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 28.947228] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 28.947228] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 28.947229] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 28.947229] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 28.947231] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 28.947232] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL A [ 28.947232] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe B [ 28.947233] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 28.947302] [drm:intel_power_well_enable] enabling always-on [ 28.947302] [drm:intel_power_well_enable] enabling DC off [ 28.947364] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 28.947366] [drm:intel_power_well_enable] enabling power well 2 [ 28.947367] [drm:skl_set_power_well] Enabling power well 2 [ 28.948911] [drm:intel_power_well_enable] enabling dpio-common-a [ 28.951003] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 28.951004] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 28.951005] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 28.951006] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 28.951006] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 28.951006] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 28.951007] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 28.951007] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 28.951008] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 28.951008] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 28.951009] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 28.951009] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 28.951010] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 28.951010] [drm:verify_single_dpll_state] PORT PLL A [ 28.951011] [drm:verify_single_dpll_state] PORT PLL B [ 28.951011] [drm:verify_single_dpll_state] PORT PLL C [ 28.951016] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 2, on? 0) for crtc 31 [ 28.951017] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 28.951037] [drm:edp_panel_on] Turn eDP port A panel power on [ 28.951038] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 29.118234] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 29.118235] [drm:wait_panel_status] Wait complete [ 29.118236] [drm:wait_panel_on] Wait for panel power on [ 29.118237] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 29.144544] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 29.144546] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 29.144547] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 29.144563] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 29.184045] [drm:wait_panel_status] Wait complete [ 29.184049] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 29.184051] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 29.184826] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 29.184827] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 29.185044] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 29.185558] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 29.185594] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d7800 [ 29.185652] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 29.185654] [drm:intel_enable_pipe] enabling pipe B [ 29.185674] [drm:intel_edp_backlight_on] [ 29.185674] [drm:intel_panel_enable_backlight] pipe B [ 29.185675] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 29.185677] [drm:intel_psr_enable] PSR not supported on this platform [ 29.185677] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 29.185701] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 29.189812] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 29.189815] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 29.189827] [drm:verify_single_dpll_state] PORT PLL A [ 29.193939] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 29.214476] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 29.218607] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 29.218610] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 29.218611] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 29.218617] [drm:intel_edp_backlight_off] [ 29.364835] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 29.364843] [drm:intel_disable_pipe] disabling pipe B [ 29.366942] [drm:edp_panel_off] Turn eDP port A panel power off [ 29.366947] [drm:wait_panel_off] Wait for panel power off time [ 29.366948] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 29.379889] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 29.379891] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 29.379892] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 29.379905] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 29.386936] [drm:wait_panel_status] Wait complete [ 29.386940] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 2, on? 1) for crtc 31 [ 29.386945] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 29.386948] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 29.386949] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 29.386950] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 29.386950] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 29.386950] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 29.386951] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 29.386951] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 29.386951] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 29.386952] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 29.386952] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 29.386953] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 29.386953] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 29.386954] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 29.386954] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 29.386955] [drm:verify_single_dpll_state] PORT PLL A [ 29.386955] [drm:verify_single_dpll_state] PORT PLL B [ 29.386956] [drm:verify_single_dpll_state] PORT PLL C [ 29.386958] [drm:intel_power_well_disable] disabling power well 2 [ 29.386961] [drm:skl_set_power_well] Disabling power well 2 [ 29.386962] [drm:intel_power_well_disable] disabling dpio-common-a [ 29.386963] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 29.386964] [drm:intel_power_well_disable] disabling DC off [ 29.386965] [drm:gen9_enable_dc5] Enabling DC5 [ 29.386965] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 29.386967] [drm:intel_power_well_disable] disabling always-on [ 29.387802] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 29.387885] [drm:drm_mode_addfb2] [FB:107] [ 29.390061] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 29.390063] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 29.390068] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 29.390068] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 29.390070] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 29.390071] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 29.390071] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 29.390072] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 29.390073] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802709d0800 for pipe B [ 29.390073] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 29.390073] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 29.390074] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 29.390074] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 29.390075] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 29.390075] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 29.390076] [drm:intel_dump_pipe_config] requested mode: [ 29.390076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 29.390077] [drm:intel_dump_pipe_config] adjusted mode: [ 29.390078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 29.390078] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 29.390078] [drm:intel_dump_pipe_config] port clock: 162000 [ 29.390079] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 29.390079] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 29.390080] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 29.390080] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 29.390080] [drm:intel_dump_pipe_config] ips: 0 [ 29.390081] [drm:intel_dump_pipe_config] double wide: 0 [ 29.390082] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 29.390082] [drm:intel_dump_pipe_config] planes on this crtc [ 29.390082] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 29.390083] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 29.390083] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 29.390084] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 29.390085] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 29.390086] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 29.390087] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 29.390088] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 29.390089] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 29.390157] [drm:intel_power_well_enable] enabling always-on [ 29.390158] [drm:intel_power_well_enable] enabling DC off [ 29.390220] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 29.390222] [drm:intel_power_well_enable] enabling power well 2 [ 29.390222] [drm:skl_set_power_well] Enabling power well 2 [ 29.391529] [drm:intel_power_well_enable] enabling dpio-common-bc [ 29.391531] [drm:intel_power_well_enable] enabling dpio-common-a [ 29.393867] [drm:intel_power_well_disable] disabling dpio-common-a [ 29.393871] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 29.585033] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 29.585035] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 29.585036] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 29.585037] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 29.585037] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 29.585038] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 29.585038] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 29.585039] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 29.585039] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 29.585040] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 29.585040] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 29.585041] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 29.585041] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 29.585042] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 29.585042] [drm:verify_single_dpll_state] PORT PLL A [ 29.585043] [drm:verify_single_dpll_state] PORT PLL B [ 29.585043] [drm:verify_single_dpll_state] PORT PLL C [ 29.585048] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 29.585048] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 29.587876] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 29.587878] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 29.588871] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 29.592286] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 29.592333] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d0800 [ 29.592371] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 29.592372] [drm:intel_enable_pipe] enabling pipe B [ 29.592394] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 29.592395] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 29.592430] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 29.596547] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 29.596550] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 29.596560] [drm:verify_single_dpll_state] PORT PLL B [ 29.600681] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 29.621214] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 29.625345] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 29.625348] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 29.625349] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 29.625354] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B [ 29.625364] [drm:intel_disable_pipe] disabling pipe B [ 29.629480] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31 [ 29.629486] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 29.629488] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 29.633402] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 29.633404] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 29.633406] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 29.633407] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 29.633407] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 29.633407] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 29.633408] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 29.633409] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 29.633409] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 29.633409] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 29.633410] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 29.633410] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 29.633411] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 29.633412] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 29.633412] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 29.633413] [drm:verify_single_dpll_state] PORT PLL A [ 29.633413] [drm:verify_single_dpll_state] PORT PLL B [ 29.633414] [drm:verify_single_dpll_state] PORT PLL C [ 29.633417] [drm:intel_power_well_disable] disabling dpio-common-bc [ 29.633418] [drm:intel_power_well_disable] disabling power well 2 [ 29.633421] [drm:skl_set_power_well] Disabling power well 2 [ 29.633423] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 29.633423] [drm:intel_power_well_disable] disabling DC off [ 29.633424] [drm:gen9_enable_dc5] Enabling DC5 [ 29.633425] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 29.633426] [drm:intel_power_well_disable] disabling always-on [ 29.634214] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 29.634295] [drm:drm_mode_addfb2] [FB:107] [ 29.636206] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 29.636208] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 29.636213] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 29.636213] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 29.636214] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 29.636215] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 29.636216] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 29.636217] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 29.636217] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88026e44a800 for pipe B [ 29.636218] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 29.636218] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 29.636219] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 29.636219] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 29.636220] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 29.636220] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 29.636220] [drm:intel_dump_pipe_config] requested mode: [ 29.636221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 29.636222] [drm:intel_dump_pipe_config] adjusted mode: [ 29.636222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 29.636223] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 29.636223] [drm:intel_dump_pipe_config] port clock: 162000 [ 29.636224] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 29.636224] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 29.636225] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 29.636225] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 29.636225] [drm:intel_dump_pipe_config] ips: 0 [ 29.636226] [drm:intel_dump_pipe_config] double wide: 0 [ 29.636226] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 29.636227] [drm:intel_dump_pipe_config] planes on this crtc [ 29.636227] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 29.636228] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 29.636228] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 29.636228] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 29.636230] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 29.636231] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 29.636232] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 29.636233] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 29.636234] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 29.636301] [drm:intel_power_well_enable] enabling always-on [ 29.636301] [drm:intel_power_well_enable] enabling DC off [ 29.636363] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 29.636365] [drm:intel_power_well_enable] enabling power well 2 [ 29.636366] [drm:skl_set_power_well] Enabling power well 2 [ 29.636786] [drm:intel_power_well_enable] enabling dpio-common-bc [ 29.636787] [drm:intel_power_well_enable] enabling dpio-common-a [ 29.638605] [drm:intel_power_well_disable] disabling dpio-common-a [ 29.638609] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 29.641941] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 29.641943] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 29.641945] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 29.641945] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 29.641946] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 29.641946] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 29.641946] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 29.641947] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 29.641948] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 29.641948] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 29.641949] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 29.641949] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 29.641950] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 29.641950] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 29.641951] [drm:verify_single_dpll_state] PORT PLL A [ 29.641951] [drm:verify_single_dpll_state] PORT PLL B [ 29.641952] [drm:verify_single_dpll_state] PORT PLL C [ 29.641957] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 29.641958] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 29.642701] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 29.642702] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 29.646062] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 29.649388] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 29.649435] [drm:skylake_pfit_enable] for crtc_state = ffff88026e44a800 [ 29.649473] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 29.649474] [drm:intel_enable_pipe] enabling pipe B [ 29.649487] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 29.649488] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 29.649522] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 29.653643] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 29.653646] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 29.653656] [drm:verify_single_dpll_state] PORT PLL B [ 29.657780] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 29.678315] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 29.682445] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 29.682448] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 29.682449] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 29.682455] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B [ 29.682466] [drm:intel_disable_pipe] disabling pipe B [ 29.686579] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31 [ 29.686585] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 29.686588] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 29.690652] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 29.690653] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 29.690655] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 29.690656] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 29.690657] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 29.690657] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 29.690657] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 29.690658] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 29.690659] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 29.690659] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 29.690659] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 29.690660] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 29.690661] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 29.690661] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 29.690662] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 29.690663] [drm:verify_single_dpll_state] PORT PLL A [ 29.690663] [drm:verify_single_dpll_state] PORT PLL B [ 29.690664] [drm:verify_single_dpll_state] PORT PLL C [ 29.690667] [drm:intel_power_well_disable] disabling dpio-common-bc [ 29.690668] [drm:intel_power_well_disable] disabling power well 2 [ 29.690670] [drm:skl_set_power_well] Disabling power well 2 [ 29.690672] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 29.690673] [drm:intel_power_well_disable] disabling DC off [ 29.690674] [drm:gen9_enable_dc5] Enabling DC5 [ 29.690674] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 29.690676] [drm:intel_power_well_disable] disabling always-on [ 29.691485] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 29.691566] [drm:drm_mode_addfb2] [FB:107] [ 29.693443] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 29.693445] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 29.693449] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 29.693450] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 29.693451] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 29.693452] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 29.693453] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 29.693453] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 29.693454] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88007798d800 for pipe B [ 29.693454] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 29.693455] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 29.693455] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 29.693456] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 29.693456] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 29.693457] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 29.693457] [drm:intel_dump_pipe_config] requested mode: [ 29.693458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 29.693458] [drm:intel_dump_pipe_config] adjusted mode: [ 29.693459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 29.693460] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 29.693460] [drm:intel_dump_pipe_config] port clock: 162000 [ 29.693460] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 29.693461] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 29.693461] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 29.693462] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 29.693462] [drm:intel_dump_pipe_config] ips: 0 [ 29.693462] [drm:intel_dump_pipe_config] double wide: 0 [ 29.693463] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 29.693463] [drm:intel_dump_pipe_config] planes on this crtc [ 29.693464] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 29.693464] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 29.693465] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 29.693465] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 29.693466] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 29.693468] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 29.693469] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL C [ 29.693470] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe B [ 29.693470] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 29.693538] [drm:intel_power_well_enable] enabling always-on [ 29.693539] [drm:intel_power_well_enable] enabling DC off [ 29.693601] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 29.693603] [drm:intel_power_well_enable] enabling power well 2 [ 29.693603] [drm:skl_set_power_well] Enabling power well 2 [ 29.695711] [drm:intel_power_well_enable] enabling dpio-common-bc [ 29.695713] [drm:intel_power_well_enable] enabling dpio-common-a [ 29.697045] [drm:intel_power_well_disable] disabling dpio-common-a [ 29.697048] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 29.699365] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 29.699367] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 29.699368] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 29.699369] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 29.699370] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 29.699370] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 29.699371] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 29.699371] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 29.699371] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 29.699372] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 29.699372] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 29.699373] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 29.699373] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 29.699374] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 29.699375] [drm:verify_single_dpll_state] PORT PLL A [ 29.699375] [drm:verify_single_dpll_state] PORT PLL B [ 29.699376] [drm:verify_single_dpll_state] PORT PLL C [ 29.699380] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 2, on? 0) for crtc 31 [ 29.699381] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 29.702315] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 29.702316] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 29.702918] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 29.703470] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 29.703471] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 29.705690] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 29.705730] [drm:skylake_pfit_enable] for crtc_state = ffff88007798d800 [ 29.705768] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 29.705769] [drm:intel_enable_pipe] enabling pipe B [ 29.705817] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 29.709919] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 29.709921] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 29.709931] [drm:verify_single_dpll_state] PORT PLL C [ 29.714069] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 29.734617] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 29.738750] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 29.738752] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 29.738753] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 29.738765] [drm:intel_disable_pipe] disabling pipe B [ 29.742877] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 2, on? 1) for crtc 31 [ 29.742882] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 29.742885] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 29.746951] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 29.746953] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 29.746955] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 29.746955] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 29.746956] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 29.746956] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 29.746957] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 29.746957] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 29.746958] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 29.746958] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 29.746959] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 29.746959] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 29.746960] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 29.746960] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 29.746961] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 29.746962] [drm:verify_single_dpll_state] PORT PLL A [ 29.746962] [drm:verify_single_dpll_state] PORT PLL B [ 29.746963] [drm:verify_single_dpll_state] PORT PLL C [ 29.746966] [drm:intel_power_well_disable] disabling dpio-common-bc [ 29.746967] [drm:intel_power_well_disable] disabling power well 2 [ 29.746969] [drm:skl_set_power_well] Disabling power well 2 [ 29.746971] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 29.746972] [drm:intel_power_well_disable] disabling DC off [ 29.746973] [drm:gen9_enable_dc5] Enabling DC5 [ 29.746974] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 29.746975] [drm:intel_power_well_disable] disabling always-on [ 29.747758] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 29.747839] [drm:drm_mode_addfb2] [FB:107] [ 29.749738] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 29.749741] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 29.749745] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 29.749746] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 29.749747] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 29.749748] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 29.749748] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 29.749749] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 29.749750] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88007798e000 for pipe B [ 29.749750] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 29.749750] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 29.749751] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 29.749752] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 29.749752] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 29.749752] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 29.749753] [drm:intel_dump_pipe_config] requested mode: [ 29.749754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 29.749754] [drm:intel_dump_pipe_config] adjusted mode: [ 29.749755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 29.749755] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 29.749756] [drm:intel_dump_pipe_config] port clock: 162000 [ 29.749756] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 29.749756] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 29.749757] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 29.749757] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 29.749758] [drm:intel_dump_pipe_config] ips: 0 [ 29.749758] [drm:intel_dump_pipe_config] double wide: 0 [ 29.749759] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 29.749759] [drm:intel_dump_pipe_config] planes on this crtc [ 29.749759] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 29.749760] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 29.749760] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 29.749761] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 29.749762] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 29.749764] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 29.749765] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL C [ 29.749765] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe B [ 29.749766] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 29.749834] [drm:intel_power_well_enable] enabling always-on [ 29.749834] [drm:intel_power_well_enable] enabling DC off [ 29.749896] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 29.749898] [drm:intel_power_well_enable] enabling power well 2 [ 29.749899] [drm:skl_set_power_well] Enabling power well 2 [ 29.751804] [drm:intel_power_well_enable] enabling dpio-common-bc [ 29.751806] [drm:intel_power_well_enable] enabling dpio-common-a [ 29.753882] [drm:intel_power_well_disable] disabling dpio-common-a [ 29.753887] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 29.757740] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 29.757742] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 29.757743] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 29.757744] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 29.757745] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 29.757745] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 29.757746] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 29.757746] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 29.757746] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 29.757747] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 29.757747] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 29.757748] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 29.757748] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 29.757749] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 29.757750] [drm:verify_single_dpll_state] PORT PLL A [ 29.757750] [drm:verify_single_dpll_state] PORT PLL B [ 29.757751] [drm:verify_single_dpll_state] PORT PLL C [ 29.757755] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 2, on? 0) for crtc 31 [ 29.757756] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 29.759969] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 29.759970] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 29.760568] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 29.761103] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 29.761104] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 29.763238] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 29.763278] [drm:skylake_pfit_enable] for crtc_state = ffff88007798e000 [ 29.763316] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 29.763317] [drm:intel_enable_pipe] enabling pipe B [ 29.763350] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 29.767460] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 29.767462] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 29.767472] [drm:verify_single_dpll_state] PORT PLL C [ 29.771599] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 29.792156] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 29.796282] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 29.796284] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 29.796285] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 29.796298] [drm:intel_disable_pipe] disabling pipe B [ 29.802225] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 2, on? 1) for crtc 31 [ 29.802230] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 29.802233] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 29.806035] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 29.806036] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 29.806038] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 29.806039] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 29.806040] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 29.806040] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 29.806040] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 29.806041] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 29.806042] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 29.806042] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 29.806042] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 29.806043] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 29.806044] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 29.806044] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 29.806045] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 29.806045] [drm:verify_single_dpll_state] PORT PLL A [ 29.806046] [drm:verify_single_dpll_state] PORT PLL B [ 29.806047] [drm:verify_single_dpll_state] PORT PLL C [ 29.806050] [drm:intel_power_well_disable] disabling dpio-common-bc [ 29.806051] [drm:intel_power_well_disable] disabling power well 2 [ 29.806053] [drm:skl_set_power_well] Disabling power well 2 [ 29.806055] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 29.806056] [drm:intel_power_well_disable] disabling DC off [ 29.806057] [drm:gen9_enable_dc5] Enabling DC5 [ 29.806057] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 29.806058] [drm:intel_power_well_disable] disabling always-on [ 29.806821] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-B [ 29.806887] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 29.806966] [drm:drm_mode_addfb2] [FB:107] [ 29.808843] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 29.808846] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 29.808850] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 29.808851] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 29.808852] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 29.808853] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 29.808854] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 29.808855] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 29.808855] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 29.808856] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88026e44f000 for pipe B [ 29.808857] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 29.808857] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 29.808857] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 29.808858] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 29.808858] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 29.808859] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 29.808859] [drm:intel_dump_pipe_config] requested mode: [ 29.808860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 29.808860] [drm:intel_dump_pipe_config] adjusted mode: [ 29.808861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 29.808862] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 29.808862] [drm:intel_dump_pipe_config] port clock: 270000 [ 29.808862] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 29.808863] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 29.808863] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 29.808864] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 29.808864] [drm:intel_dump_pipe_config] ips: 0 [ 29.808864] [drm:intel_dump_pipe_config] double wide: 0 [ 29.808865] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 29.808865] [drm:intel_dump_pipe_config] planes on this crtc [ 29.808866] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 29.808866] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 29.808867] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 29.808867] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 29.808868] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 29.808869] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 29.808871] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL A [ 29.808871] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe B [ 29.808872] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 29.808940] [drm:intel_power_well_enable] enabling always-on [ 29.808941] [drm:intel_power_well_enable] enabling DC off [ 29.809003] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 29.809005] [drm:intel_power_well_enable] enabling power well 2 [ 29.809005] [drm:skl_set_power_well] Enabling power well 2 [ 29.811257] [drm:intel_power_well_enable] enabling dpio-common-a [ 29.812350] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 29.812353] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 29.812354] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 29.812354] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 29.812355] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 29.812355] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 29.812355] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 29.812356] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 29.812356] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 29.812357] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 29.812357] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 29.812358] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 29.812358] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 29.812359] [drm:verify_single_dpll_state] PORT PLL A [ 29.812359] [drm:verify_single_dpll_state] PORT PLL B [ 29.812360] [drm:verify_single_dpll_state] PORT PLL C [ 29.812365] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 2, on? 0) for crtc 31 [ 29.812365] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 29.812387] [drm:edp_panel_on] Turn eDP port A panel power on [ 29.812387] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 29.812391] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 29.812392] [drm:wait_panel_status] Wait complete [ 29.812392] [drm:wait_panel_on] Wait for panel power on [ 29.812393] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 29.838713] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 29.838714] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 29.838715] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 29.838729] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 29.868733] [drm:wait_panel_status] Wait complete [ 29.868737] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 29.868738] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 29.869484] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 29.869486] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 29.869703] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 29.870218] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 29.870255] [drm:skylake_pfit_enable] for crtc_state = ffff88026e44f000 [ 29.870313] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 29.870315] [drm:intel_enable_pipe] enabling pipe B [ 29.870333] [drm:intel_edp_backlight_on] [ 29.870334] [drm:intel_panel_enable_backlight] pipe B [ 29.870335] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 29.870336] [drm:intel_psr_enable] PSR not supported on this platform [ 29.870337] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 29.870361] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 29.874474] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 29.874477] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 29.874489] [drm:verify_single_dpll_state] PORT PLL A [ 29.878605] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 29.899182] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 29.903273] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 29.903276] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 29.903277] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 29.903283] [drm:intel_edp_backlight_off] [ 29.987655] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 29.987663] [drm:intel_disable_pipe] disabling pipe B [ 29.991543] [drm:edp_panel_off] Turn eDP port A panel power off [ 29.991547] [drm:wait_panel_off] Wait for panel power off time [ 29.991548] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 30.004493] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 30.004495] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 30.004496] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 30.004510] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 30.005199] [drm:wait_panel_status] Wait complete [ 30.005203] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 2, on? 1) for crtc 31 [ 30.005208] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 30.005210] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 30.005211] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 30.005212] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 30.005212] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 30.005213] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 30.005213] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 30.005213] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 30.005214] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 30.005214] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 30.005214] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 30.005215] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 30.005216] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 30.005216] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 30.005216] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 30.005217] [drm:verify_single_dpll_state] PORT PLL A [ 30.005218] [drm:verify_single_dpll_state] PORT PLL B [ 30.005218] [drm:verify_single_dpll_state] PORT PLL C [ 30.005220] [drm:intel_power_well_disable] disabling power well 2 [ 30.005223] [drm:skl_set_power_well] Disabling power well 2 [ 30.005223] [drm:intel_power_well_disable] disabling dpio-common-a [ 30.005225] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 30.005226] [drm:intel_power_well_disable] disabling DC off [ 30.005227] [drm:gen9_enable_dc5] Enabling DC5 [ 30.005227] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 30.005229] [drm:intel_power_well_disable] disabling always-on [ 30.006004] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 30.006086] [drm:drm_mode_addfb2] [FB:107] [ 30.008116] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 30.008119] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 30.008123] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 30.008124] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 30.008125] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.008125] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 30.008127] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 30.008127] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 30.008128] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 30.008129] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802709d5800 for pipe B [ 30.008129] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 30.008130] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 30.008130] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 30.008131] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 30.008131] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 30.008132] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 30.008132] [drm:intel_dump_pipe_config] requested mode: [ 30.008133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 30.008133] [drm:intel_dump_pipe_config] adjusted mode: [ 30.008134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 30.008134] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 30.008135] [drm:intel_dump_pipe_config] port clock: 270000 [ 30.008135] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 30.008136] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 30.008136] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 30.008136] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 30.008137] [drm:intel_dump_pipe_config] ips: 0 [ 30.008137] [drm:intel_dump_pipe_config] double wide: 0 [ 30.008138] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 30.008138] [drm:intel_dump_pipe_config] planes on this crtc [ 30.008139] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 30.008139] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 30.008140] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 30.008140] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 30.008141] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 30.008142] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 30.008143] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL A [ 30.008144] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe B [ 30.008144] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.008213] [drm:intel_power_well_enable] enabling always-on [ 30.008214] [drm:intel_power_well_enable] enabling DC off [ 30.008276] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 30.008278] [drm:intel_power_well_enable] enabling power well 2 [ 30.008279] [drm:skl_set_power_well] Enabling power well 2 [ 30.011535] [drm:intel_power_well_enable] enabling dpio-common-a [ 30.014357] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 30.014359] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 30.014360] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 30.014360] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 30.014361] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 30.014361] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 30.014362] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 30.014362] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 30.014363] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 30.014363] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 30.014364] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 30.014364] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 30.014364] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 30.014365] [drm:verify_single_dpll_state] PORT PLL A [ 30.014366] [drm:verify_single_dpll_state] PORT PLL B [ 30.014366] [drm:verify_single_dpll_state] PORT PLL C [ 30.014371] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 2, on? 0) for crtc 31 [ 30.014372] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 30.014392] [drm:edp_panel_on] Turn eDP port A panel power on [ 30.014393] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 30.314922] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 30.314924] [drm:wait_panel_status] Wait complete [ 30.314924] [drm:wait_panel_on] Wait for panel power on [ 30.314925] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 30.341232] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 30.341233] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 30.341234] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 30.341248] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 30.366505] [drm:wait_panel_status] Wait complete [ 30.366509] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 30.366510] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 30.367222] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 30.367222] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 30.367439] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 30.367954] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 30.367990] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d5800 [ 30.368348] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 30.368351] [drm:intel_enable_pipe] enabling pipe B [ 30.368369] [drm:intel_edp_backlight_on] [ 30.368370] [drm:intel_panel_enable_backlight] pipe B [ 30.368371] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 30.368373] [drm:intel_psr_enable] PSR not supported on this platform [ 30.368373] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 30.368397] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 30.372506] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 30.372509] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 30.372521] [drm:verify_single_dpll_state] PORT PLL A [ 30.376654] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 30.397214] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 30.401311] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 30.401313] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 30.401314] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.401320] [drm:intel_edp_backlight_off] [ 30.470922] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 30.470930] [drm:intel_disable_pipe] disabling pipe B [ 30.473043] [drm:edp_panel_off] Turn eDP port A panel power off [ 30.473048] [drm:wait_panel_off] Wait for panel power off time [ 30.473049] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 30.485995] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 30.485997] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 30.485997] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 30.486011] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 30.487968] [drm:wait_panel_status] Wait complete [ 30.487972] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 2, on? 1) for crtc 31 [ 30.487977] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 30.487980] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 30.487981] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 30.487981] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 30.487982] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 30.487982] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 30.487982] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 30.487983] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 30.487983] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 30.487983] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 30.487984] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 30.487985] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 30.487986] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 30.487986] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 30.487987] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 30.487987] [drm:verify_single_dpll_state] PORT PLL A [ 30.487988] [drm:verify_single_dpll_state] PORT PLL B [ 30.487988] [drm:verify_single_dpll_state] PORT PLL C [ 30.487990] [drm:intel_power_well_disable] disabling power well 2 [ 30.487993] [drm:skl_set_power_well] Disabling power well 2 [ 30.487994] [drm:intel_power_well_disable] disabling dpio-common-a [ 30.487995] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 30.487996] [drm:intel_power_well_disable] disabling DC off [ 30.487997] [drm:gen9_enable_dc5] Enabling DC5 [ 30.487997] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 30.487998] [drm:intel_power_well_disable] disabling always-on [ 30.489085] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 30.489170] [drm:drm_mode_addfb2] [FB:107] [ 30.491192] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 30.491194] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 30.491198] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 30.491199] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 30.491200] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 30.491201] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 30.491202] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 30.491202] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 30.491203] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802709d1800 for pipe B [ 30.491204] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 30.491204] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 30.491205] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 30.491205] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 30.491206] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 30.491206] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 30.491206] [drm:intel_dump_pipe_config] requested mode: [ 30.491207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 30.491208] [drm:intel_dump_pipe_config] adjusted mode: [ 30.491208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 30.491209] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 30.491209] [drm:intel_dump_pipe_config] port clock: 162000 [ 30.491210] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 30.491210] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 30.491210] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 30.491211] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 30.491211] [drm:intel_dump_pipe_config] ips: 0 [ 30.491212] [drm:intel_dump_pipe_config] double wide: 0 [ 30.491212] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 30.491213] [drm:intel_dump_pipe_config] planes on this crtc [ 30.491213] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 30.491214] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 30.491214] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 30.491214] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 30.491215] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 30.491217] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 30.491218] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 30.491219] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 30.491219] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.491288] [drm:intel_power_well_enable] enabling always-on [ 30.491288] [drm:intel_power_well_enable] enabling DC off [ 30.491350] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 30.491352] [drm:intel_power_well_enable] enabling power well 2 [ 30.491353] [drm:skl_set_power_well] Enabling power well 2 [ 30.492929] [drm:intel_power_well_enable] enabling dpio-common-bc [ 30.492930] [drm:intel_power_well_enable] enabling dpio-common-a [ 30.536437] [drm:intel_power_well_disable] disabling dpio-common-a [ 30.536442] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 30.539663] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 30.539665] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 30.539667] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 30.539667] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 30.539668] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 30.539668] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 30.539668] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 30.539669] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 30.539670] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 30.539670] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 30.539670] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 30.539671] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 30.539672] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 30.539672] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 30.539673] [drm:verify_single_dpll_state] PORT PLL A [ 30.539674] [drm:verify_single_dpll_state] PORT PLL B [ 30.539674] [drm:verify_single_dpll_state] PORT PLL C [ 30.539678] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 30.539679] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 30.543285] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 30.543286] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 30.544169] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 30.547751] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 30.547794] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d1800 [ 30.547831] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 30.547832] [drm:intel_enable_pipe] enabling pipe B [ 30.547854] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 30.547854] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 30.547887] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 30.552005] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 30.552008] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 30.552019] [drm:verify_single_dpll_state] PORT PLL B [ 30.556144] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 30.576710] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 30.580801] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 30.580803] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 30.580804] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.580810] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B [ 30.580820] [drm:intel_disable_pipe] disabling pipe B [ 30.586267] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31 [ 30.586273] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 30.586275] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 30.590173] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 30.590175] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 30.590177] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 30.590178] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 30.590178] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 30.590179] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 30.590179] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 30.590180] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 30.590180] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 30.590181] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 30.590181] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 30.590182] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 30.590182] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 30.590183] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 30.590184] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 30.590184] [drm:verify_single_dpll_state] PORT PLL A [ 30.590185] [drm:verify_single_dpll_state] PORT PLL B [ 30.590185] [drm:verify_single_dpll_state] PORT PLL C [ 30.590189] [drm:intel_power_well_disable] disabling dpio-common-bc [ 30.590189] [drm:intel_power_well_disable] disabling power well 2 [ 30.590192] [drm:skl_set_power_well] Disabling power well 2 [ 30.590194] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 30.590195] [drm:intel_power_well_disable] disabling DC off [ 30.590196] [drm:gen9_enable_dc5] Enabling DC5 [ 30.590196] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 30.590197] [drm:intel_power_well_disable] disabling always-on [ 30.590975] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 30.591057] [drm:drm_mode_addfb2] [FB:107] [ 30.593713] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 30.593716] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 30.593720] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 30.593721] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 30.593722] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 30.593723] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 30.593723] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 30.593724] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 30.593725] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88007798d800 for pipe B [ 30.593725] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 30.593726] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 30.593726] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 30.593727] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 30.593727] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 30.593728] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 30.593728] [drm:intel_dump_pipe_config] requested mode: [ 30.593729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 30.593729] [drm:intel_dump_pipe_config] adjusted mode: [ 30.593730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 30.593730] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 30.593731] [drm:intel_dump_pipe_config] port clock: 162000 [ 30.593731] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 30.593732] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 30.593732] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 30.593732] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 30.593733] [drm:intel_dump_pipe_config] ips: 0 [ 30.593733] [drm:intel_dump_pipe_config] double wide: 0 [ 30.593734] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 30.593734] [drm:intel_dump_pipe_config] planes on this crtc [ 30.593735] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 30.593735] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 30.593736] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 30.593736] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 30.593737] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 30.593738] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 30.593740] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 30.593740] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 30.593741] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.593808] [drm:intel_power_well_enable] enabling always-on [ 30.593809] [drm:intel_power_well_enable] enabling DC off [ 30.593871] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 30.593873] [drm:intel_power_well_enable] enabling power well 2 [ 30.593874] [drm:skl_set_power_well] Enabling power well 2 [ 30.595085] [drm:intel_power_well_enable] enabling dpio-common-bc [ 30.595087] [drm:intel_power_well_enable] enabling dpio-common-a [ 30.597899] [drm:intel_power_well_disable] disabling dpio-common-a [ 30.597904] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 30.601970] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 30.601972] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 30.601974] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 30.601974] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 30.601974] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 30.601975] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 30.601975] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 30.601976] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 30.601976] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 30.601977] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 30.601977] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 30.601978] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 30.601979] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 30.601979] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 30.601980] [drm:verify_single_dpll_state] PORT PLL A [ 30.601980] [drm:verify_single_dpll_state] PORT PLL B [ 30.601981] [drm:verify_single_dpll_state] PORT PLL C [ 30.601985] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 30.601986] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 30.602751] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 30.602753] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 30.603861] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 30.607098] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 30.607139] [drm:skylake_pfit_enable] for crtc_state = ffff88007798d800 [ 30.607177] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 30.607179] [drm:intel_enable_pipe] enabling pipe B [ 30.607200] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 30.607201] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 30.607263] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 30.611351] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 30.611353] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 30.611364] [drm:verify_single_dpll_state] PORT PLL B [ 30.615474] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 30.636047] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 30.640141] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 30.640144] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 30.640145] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.640151] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B [ 30.640164] [drm:intel_disable_pipe] disabling pipe B [ 30.644261] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31 [ 30.644267] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 30.644269] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 30.648313] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 30.648314] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 30.648316] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 30.648317] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 30.648318] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 30.648318] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 30.648318] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 30.648319] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 30.648319] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 30.648320] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 30.648320] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 30.648321] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 30.648321] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 30.648322] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 30.648323] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 30.648323] [drm:verify_single_dpll_state] PORT PLL A [ 30.648324] [drm:verify_single_dpll_state] PORT PLL B [ 30.648325] [drm:verify_single_dpll_state] PORT PLL C [ 30.648328] [drm:intel_power_well_disable] disabling dpio-common-bc [ 30.648329] [drm:intel_power_well_disable] disabling power well 2 [ 30.648331] [drm:skl_set_power_well] Disabling power well 2 [ 30.648333] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 30.648334] [drm:intel_power_well_disable] disabling DC off [ 30.648335] [drm:gen9_enable_dc5] Enabling DC5 [ 30.648336] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 30.648337] [drm:intel_power_well_disable] disabling always-on [ 30.649188] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 30.649270] [drm:drm_mode_addfb2] [FB:107] [ 30.651972] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 30.651974] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 30.651979] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 30.651979] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 30.651980] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 30.651981] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 30.651982] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 30.651982] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 30.651983] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802709d7800 for pipe B [ 30.651984] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 30.651984] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 30.651985] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 30.651985] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 30.651986] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 30.651986] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 30.651986] [drm:intel_dump_pipe_config] requested mode: [ 30.651987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 30.651988] [drm:intel_dump_pipe_config] adjusted mode: [ 30.651988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 30.651989] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 30.651989] [drm:intel_dump_pipe_config] port clock: 162000 [ 30.651990] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 30.651990] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 30.651991] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 30.651991] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 30.651991] [drm:intel_dump_pipe_config] ips: 0 [ 30.651992] [drm:intel_dump_pipe_config] double wide: 0 [ 30.651992] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 30.651993] [drm:intel_dump_pipe_config] planes on this crtc [ 30.651993] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 30.651994] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 30.651994] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 30.651994] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 30.651996] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 30.651997] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 30.651999] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL C [ 30.651999] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe B [ 30.652000] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.652068] [drm:intel_power_well_enable] enabling always-on [ 30.652069] [drm:intel_power_well_enable] enabling DC off [ 30.652131] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 30.652133] [drm:intel_power_well_enable] enabling power well 2 [ 30.652134] [drm:skl_set_power_well] Enabling power well 2 [ 30.654971] [drm:intel_power_well_enable] enabling dpio-common-bc [ 30.654972] [drm:intel_power_well_enable] enabling dpio-common-a [ 30.657348] [drm:intel_power_well_disable] disabling dpio-common-a [ 30.657353] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 30.661256] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 30.661258] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 30.661259] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 30.661260] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 30.661261] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 30.661261] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 30.661261] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 30.661262] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 30.661262] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 30.661263] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 30.661263] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 30.661264] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 30.661264] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 30.661265] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 30.661266] [drm:verify_single_dpll_state] PORT PLL A [ 30.661266] [drm:verify_single_dpll_state] PORT PLL B [ 30.661267] [drm:verify_single_dpll_state] PORT PLL C [ 30.661272] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 2, on? 0) for crtc 31 [ 30.661273] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 30.663643] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 30.663644] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 30.663877] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 30.663877] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 30.664104] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 30.664647] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 30.664648] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 30.667236] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 30.667278] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d7800 [ 30.667316] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 30.667317] [drm:intel_enable_pipe] enabling pipe B [ 30.667355] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 30.671477] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 30.671478] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 30.671489] [drm:verify_single_dpll_state] PORT PLL C [ 30.675614] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 30.696183] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 30.700285] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 30.700287] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 30.700288] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.700298] [drm:intel_disable_pipe] disabling pipe B [ 30.704413] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 2, on? 1) for crtc 31 [ 30.704420] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 30.704425] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 30.708482] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 30.708485] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 30.708488] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 30.708489] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 30.708490] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 30.708491] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 30.708492] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 30.708494] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 30.708495] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 30.708496] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 30.708497] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 30.708498] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 30.708500] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 30.708501] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 30.708502] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 30.708504] [drm:verify_single_dpll_state] PORT PLL A [ 30.708505] [drm:verify_single_dpll_state] PORT PLL B [ 30.708507] [drm:verify_single_dpll_state] PORT PLL C [ 30.708511] [drm:intel_power_well_disable] disabling dpio-common-bc [ 30.708513] [drm:intel_power_well_disable] disabling power well 2 [ 30.708517] [drm:skl_set_power_well] Disabling power well 2 [ 30.708520] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 30.708521] [drm:intel_power_well_disable] disabling DC off [ 30.708523] [drm:gen9_enable_dc5] Enabling DC5 [ 30.708524] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 30.708526] [drm:intel_power_well_disable] disabling always-on [ 30.709824] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 30.709922] [drm:drm_mode_addfb2] [FB:107] [ 30.713077] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 30.713081] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 30.713089] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 30.713090] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 30.713093] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 30.713095] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 30.713096] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 30.713097] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 30.713099] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88007798f000 for pipe B [ 30.713100] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 30.713101] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 30.713103] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 30.713104] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 30.713105] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 30.713106] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 30.713107] [drm:intel_dump_pipe_config] requested mode: [ 30.713109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 30.713110] [drm:intel_dump_pipe_config] adjusted mode: [ 30.713112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 30.713114] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 30.713114] [drm:intel_dump_pipe_config] port clock: 162000 [ 30.713115] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 30.713117] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 30.713118] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 30.713119] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 30.713120] [drm:intel_dump_pipe_config] ips: 0 [ 30.713121] [drm:intel_dump_pipe_config] double wide: 0 [ 30.713123] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 30.713124] [drm:intel_dump_pipe_config] planes on this crtc [ 30.713125] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 30.713126] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 30.713127] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 30.713128] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 30.713130] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 30.713133] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 30.713135] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL C [ 30.713137] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe B [ 30.713138] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.713227] [drm:intel_power_well_enable] enabling always-on [ 30.713228] [drm:intel_power_well_enable] enabling DC off [ 30.713291] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 30.713294] [drm:intel_power_well_enable] enabling power well 2 [ 30.713296] [drm:skl_set_power_well] Enabling power well 2 [ 30.713300] [drm:intel_power_well_enable] enabling dpio-common-bc [ 30.713301] [drm:intel_power_well_enable] enabling dpio-common-a [ 30.716632] [drm:intel_power_well_disable] disabling dpio-common-a [ 30.716640] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 30.720400] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 30.720403] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 30.720406] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 30.720408] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 30.720409] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 30.720410] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 30.720411] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 30.720412] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 30.720413] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 30.720414] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 30.720415] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 30.720417] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 30.720418] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 30.720420] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 30.720421] [drm:verify_single_dpll_state] PORT PLL A [ 30.720423] [drm:verify_single_dpll_state] PORT PLL B [ 30.720424] [drm:verify_single_dpll_state] PORT PLL C [ 30.720431] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 2, on? 0) for crtc 31 [ 30.720432] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 30.722888] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 30.722890] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 30.723249] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 30.723251] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 30.723486] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 30.724025] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 30.724026] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 30.726570] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 30.726615] [drm:skylake_pfit_enable] for crtc_state = ffff88007798f000 [ 30.726669] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 30.726671] [drm:intel_enable_pipe] enabling pipe B [ 30.726700] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 30.730827] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 30.730831] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 30.730845] [drm:verify_single_dpll_state] PORT PLL C [ 30.734987] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 30.755578] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 30.759659] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 30.759664] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 30.759666] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.759681] [drm:intel_disable_pipe] disabling pipe B [ 30.763855] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 2, on? 1) for crtc 31 [ 30.763862] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 30.763866] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 30.767661] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 30.767664] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 30.767667] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 30.767669] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 30.767670] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 30.767671] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 30.767672] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 30.767674] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 30.767675] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 30.767676] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 30.767677] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 30.767678] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 30.767679] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 30.767681] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 30.767682] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 30.767684] [drm:verify_single_dpll_state] PORT PLL A [ 30.767685] [drm:verify_single_dpll_state] PORT PLL B [ 30.767686] [drm:verify_single_dpll_state] PORT PLL C [ 30.767691] [drm:intel_power_well_disable] disabling dpio-common-bc [ 30.767693] [drm:intel_power_well_disable] disabling power well 2 [ 30.767697] [drm:skl_set_power_well] Disabling power well 2 [ 30.767700] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 30.767702] [drm:intel_power_well_disable] disabling DC off [ 30.767703] [drm:gen9_enable_dc5] Enabling DC5 [ 30.767705] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 30.767707] [drm:intel_power_well_disable] disabling always-on [ 30.768897] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-B-frame-sequence [ 30.769054] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 30.769148] [drm:drm_mode_addfb2] [FB:107] [ 30.772447] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 30.772451] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 30.772459] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 30.772461] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 30.772464] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.772465] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 30.772469] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 30.772470] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 30.772472] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 30.772474] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff880077988000 for pipe B [ 30.772475] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 30.772476] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 30.772477] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 30.772479] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 30.772481] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 30.772482] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 30.772483] [drm:intel_dump_pipe_config] requested mode: [ 30.772485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 30.772486] [drm:intel_dump_pipe_config] adjusted mode: [ 30.772488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 30.772490] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 30.772491] [drm:intel_dump_pipe_config] port clock: 270000 [ 30.772492] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 30.772493] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 30.772495] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 30.772496] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 30.772497] [drm:intel_dump_pipe_config] ips: 0 [ 30.772498] [drm:intel_dump_pipe_config] double wide: 0 [ 30.772500] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 30.772501] [drm:intel_dump_pipe_config] planes on this crtc [ 30.772502] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 30.772504] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 30.772505] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 30.772506] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 30.772508] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 30.772511] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 30.772513] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL A [ 30.772515] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe B [ 30.772516] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.772609] [drm:intel_power_well_enable] enabling always-on [ 30.772610] [drm:intel_power_well_enable] enabling DC off [ 30.772673] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 30.772677] [drm:intel_power_well_enable] enabling power well 2 [ 30.772678] [drm:skl_set_power_well] Enabling power well 2 [ 30.772683] [drm:intel_power_well_enable] enabling dpio-common-a [ 30.775721] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 30.775725] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 30.775727] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 30.775728] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 30.775729] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 30.775730] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 30.775731] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 30.775732] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 30.775733] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 30.775734] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 30.775735] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 30.775736] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 30.775737] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 30.775739] [drm:verify_single_dpll_state] PORT PLL A [ 30.775740] [drm:verify_single_dpll_state] PORT PLL B [ 30.775741] [drm:verify_single_dpll_state] PORT PLL C [ 30.775749] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 2, on? 0) for crtc 31 [ 30.775750] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 30.775780] [drm:edp_panel_on] Turn eDP port A panel power on [ 30.775781] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 30.775785] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 30.775786] [drm:wait_panel_status] Wait complete [ 30.775787] [drm:wait_panel_on] Wait for panel power on [ 30.775789] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 30.803548] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 30.803551] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 30.803552] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 30.803574] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 30.829715] [drm:wait_panel_status] Wait complete [ 30.829722] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 30.829725] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 30.830486] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 30.830489] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 30.830717] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 30.831242] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 30.831283] [drm:skylake_pfit_enable] for crtc_state = ffff880077988000 [ 30.831343] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 30.831347] [drm:intel_enable_pipe] enabling pipe B [ 30.831359] [drm:intel_edp_backlight_on] [ 30.831360] [drm:intel_panel_enable_backlight] pipe B [ 30.831362] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 30.834474] [drm:intel_psr_enable] PSR not supported on this platform [ 30.834476] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 30.834499] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 30.835492] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 30.835496] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 30.835512] [drm:verify_single_dpll_state] PORT PLL A [ 30.839661] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 30.860222] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 30.864326] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 30.864330] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 30.864333] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 30.864344] [drm:intel_edp_backlight_off] [ 31.008944] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 31.008953] [drm:intel_disable_pipe] disabling pipe B [ 31.013326] [drm:edp_panel_off] Turn eDP port A panel power off [ 31.013330] [drm:wait_panel_off] Wait for panel power off time [ 31.013333] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 31.026254] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 31.026257] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 31.026258] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 31.026282] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 31.031182] [drm:wait_panel_status] Wait complete [ 31.031189] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 2, on? 1) for crtc 31 [ 31.031195] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 31.031200] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.031202] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.031204] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.031205] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.031206] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.031207] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.031208] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.031209] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.031210] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.031211] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 31.031213] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.031215] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.031216] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.031217] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.031218] [drm:verify_single_dpll_state] PORT PLL A [ 31.031220] [drm:verify_single_dpll_state] PORT PLL B [ 31.031221] [drm:verify_single_dpll_state] PORT PLL C [ 31.031225] [drm:intel_power_well_disable] disabling power well 2 [ 31.031229] [drm:skl_set_power_well] Disabling power well 2 [ 31.031231] [drm:intel_power_well_disable] disabling dpio-common-a [ 31.031234] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 31.031236] [drm:intel_power_well_disable] disabling DC off [ 31.031238] [drm:gen9_enable_dc5] Enabling DC5 [ 31.031240] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 31.031242] [drm:intel_power_well_disable] disabling always-on [ 31.032471] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.032567] [drm:drm_mode_addfb2] [FB:107] [ 31.035500] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.035505] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 31.035511] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 31.035513] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 31.035515] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.035516] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 31.035519] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 31.035520] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 31.035521] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 31.035523] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802704b2000 for pipe B [ 31.035524] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 31.035525] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 31.035526] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 31.035527] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 31.035529] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 31.035529] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 31.035530] [drm:intel_dump_pipe_config] requested mode: [ 31.035532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 31.035533] [drm:intel_dump_pipe_config] adjusted mode: [ 31.035534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 31.035536] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 31.035537] [drm:intel_dump_pipe_config] port clock: 270000 [ 31.035538] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 31.035539] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 31.035540] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 31.035541] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 31.035542] [drm:intel_dump_pipe_config] ips: 0 [ 31.035542] [drm:intel_dump_pipe_config] double wide: 0 [ 31.035544] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 31.035545] [drm:intel_dump_pipe_config] planes on this crtc [ 31.035546] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 31.035547] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 31.035548] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 31.035549] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 31.035551] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 31.035553] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 31.035555] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL A [ 31.035556] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe B [ 31.035557] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.035643] [drm:intel_power_well_enable] enabling always-on [ 31.035644] [drm:intel_power_well_enable] enabling DC off [ 31.035707] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 31.035710] [drm:intel_power_well_enable] enabling power well 2 [ 31.035711] [drm:skl_set_power_well] Enabling power well 2 [ 31.035715] [drm:intel_power_well_enable] enabling dpio-common-a [ 31.038472] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.038475] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.038477] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.038478] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.038479] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.038480] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.038481] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.038482] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.038483] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.038484] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.038485] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.038486] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.038487] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.038488] [drm:verify_single_dpll_state] PORT PLL A [ 31.038489] [drm:verify_single_dpll_state] PORT PLL B [ 31.038490] [drm:verify_single_dpll_state] PORT PLL C [ 31.038498] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 2, on? 0) for crtc 31 [ 31.038499] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 31.038525] [drm:edp_panel_on] Turn eDP port A panel power on [ 31.038527] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 31.151447] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000060 [ 31.163550] [drm:wait_panel_status] Wait complete [ 31.163554] [drm:wait_panel_on] Wait for panel power on [ 31.163556] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 31.194036] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 31.194040] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 31.194041] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 31.194057] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 31.218924] [drm:wait_panel_status] Wait complete [ 31.218931] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 31.218933] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 31.219658] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 31.219660] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 31.219903] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 31.220426] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 31.220466] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b2000 [ 31.220526] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 31.220530] [drm:intel_enable_pipe] enabling pipe B [ 31.220546] [drm:intel_edp_backlight_on] [ 31.220547] [drm:intel_panel_enable_backlight] pipe B [ 31.220549] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 31.220551] [drm:intel_psr_enable] PSR not supported on this platform [ 31.220552] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 31.220574] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 31.224685] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 31.224688] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 31.224704] [drm:verify_single_dpll_state] PORT PLL A [ 31.228854] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 31.249416] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 31.253519] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 31.253524] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 31.253526] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.253538] [drm:intel_edp_backlight_off] [ 31.322032] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 31.322042] [drm:intel_disable_pipe] disabling pipe B [ 31.324139] [drm:edp_panel_off] Turn eDP port A panel power off [ 31.324143] [drm:wait_panel_off] Wait for panel power off time [ 31.324146] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 31.337077] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 31.337081] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 31.337082] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 31.337087] [drm:wait_panel_status] Wait complete [ 31.337093] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 2, on? 1) for crtc 31 [ 31.337099] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 31.337103] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.337106] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 31.337107] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.337108] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.337109] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.337110] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.337111] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.337113] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.337114] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.337115] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.337116] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 31.337117] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.337118] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.337119] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.337120] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.337121] [drm:verify_single_dpll_state] PORT PLL A [ 31.337123] [drm:verify_single_dpll_state] PORT PLL B [ 31.337124] [drm:verify_single_dpll_state] PORT PLL C [ 31.337130] [drm:intel_power_well_disable] disabling power well 2 [ 31.337136] [drm:skl_set_power_well] Disabling power well 2 [ 31.337139] [drm:intel_power_well_disable] disabling dpio-common-a [ 31.337144] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 31.337147] [drm:intel_power_well_disable] disabling DC off [ 31.337149] [drm:gen9_enable_dc5] Enabling DC5 [ 31.337150] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 31.337152] [drm:intel_power_well_disable] disabling always-on [ 31.338610] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.338730] [drm:drm_mode_addfb2] [FB:107] [ 31.342138] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.342143] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 31.342151] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 31.342152] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 31.342154] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 31.342157] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 31.342158] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 31.342160] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 31.342162] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802704b4000 for pipe B [ 31.342163] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 31.342164] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 31.342165] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 31.342167] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 31.342169] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 31.342170] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 31.342171] [drm:intel_dump_pipe_config] requested mode: [ 31.342173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 31.342174] [drm:intel_dump_pipe_config] adjusted mode: [ 31.342176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 31.342178] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 31.342179] [drm:intel_dump_pipe_config] port clock: 162000 [ 31.342180] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 31.342181] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 31.342183] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 31.342184] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 31.342185] [drm:intel_dump_pipe_config] ips: 0 [ 31.342186] [drm:intel_dump_pipe_config] double wide: 0 [ 31.342188] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 31.342189] [drm:intel_dump_pipe_config] planes on this crtc [ 31.342190] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 31.342192] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 31.342193] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 31.342194] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 31.342197] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 31.342200] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 31.342202] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 31.342204] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 31.342205] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.342297] [drm:intel_power_well_enable] enabling always-on [ 31.342299] [drm:intel_power_well_enable] enabling DC off [ 31.342362] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 31.342365] [drm:intel_power_well_enable] enabling power well 2 [ 31.342367] [drm:skl_set_power_well] Enabling power well 2 [ 31.342371] [drm:intel_power_well_enable] enabling dpio-common-bc [ 31.342372] [drm:intel_power_well_enable] enabling dpio-common-a [ 31.344188] [drm:intel_power_well_disable] disabling dpio-common-a [ 31.344195] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 31.347150] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 31.347154] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.347157] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.347158] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.347159] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.347161] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.347162] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.347164] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.347165] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.347166] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.347167] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 31.347168] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.347170] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.347172] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.347173] [drm:verify_single_dpll_state] PORT PLL A [ 31.347175] [drm:verify_single_dpll_state] PORT PLL B [ 31.347176] [drm:verify_single_dpll_state] PORT PLL C [ 31.347184] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 31.347185] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 31.348869] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 31.348871] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 31.349899] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 31.386216] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 31.386268] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b4000 [ 31.386322] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 31.386324] [drm:intel_enable_pipe] enabling pipe B [ 31.386335] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 31.386337] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 31.386369] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 31.390502] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.390507] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 31.390523] [drm:verify_single_dpll_state] PORT PLL B [ 31.394681] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 31.415230] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 31.419343] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 31.419347] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 31.419349] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.419359] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B [ 31.419374] [drm:intel_disable_pipe] disabling pipe B [ 31.425074] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31 [ 31.425083] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 31.425087] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 31.427841] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 31.427844] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.427847] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.427849] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.427850] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.427851] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.427852] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.427854] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.427855] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.427856] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.427857] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 31.427858] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.427860] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.427861] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.427863] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.427864] [drm:verify_single_dpll_state] PORT PLL A [ 31.427866] [drm:verify_single_dpll_state] PORT PLL B [ 31.427867] [drm:verify_single_dpll_state] PORT PLL C [ 31.427872] [drm:intel_power_well_disable] disabling dpio-common-bc [ 31.427874] [drm:intel_power_well_disable] disabling power well 2 [ 31.427877] [drm:skl_set_power_well] Disabling power well 2 [ 31.427881] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 31.427882] [drm:intel_power_well_disable] disabling DC off [ 31.427884] [drm:gen9_enable_dc5] Enabling DC5 [ 31.427886] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 31.427888] [drm:intel_power_well_disable] disabling always-on [ 31.429206] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.429304] [drm:drm_mode_addfb2] [FB:107] [ 31.432452] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.432457] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 31.432464] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 31.432465] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 31.432467] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 31.432470] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 31.432471] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 31.432472] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 31.432474] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88026e44f800 for pipe B [ 31.432475] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 31.432476] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 31.432478] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 31.432479] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 31.432480] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 31.432481] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 31.432482] [drm:intel_dump_pipe_config] requested mode: [ 31.432484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 31.432485] [drm:intel_dump_pipe_config] adjusted mode: [ 31.432487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 31.432489] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 31.432490] [drm:intel_dump_pipe_config] port clock: 162000 [ 31.432491] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 31.432492] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 31.432493] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 31.432494] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 31.432495] [drm:intel_dump_pipe_config] ips: 0 [ 31.432496] [drm:intel_dump_pipe_config] double wide: 0 [ 31.432498] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 31.432499] [drm:intel_dump_pipe_config] planes on this crtc [ 31.432500] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 31.432501] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 31.432502] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 31.432503] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 31.432506] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 31.432508] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 31.432511] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 31.432512] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 31.432513] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.432602] [drm:intel_power_well_enable] enabling always-on [ 31.432603] [drm:intel_power_well_enable] enabling DC off [ 31.432666] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 31.432670] [drm:intel_power_well_enable] enabling power well 2 [ 31.432671] [drm:skl_set_power_well] Enabling power well 2 [ 31.432675] [drm:intel_power_well_enable] enabling dpio-common-bc [ 31.432676] [drm:intel_power_well_enable] enabling dpio-common-a [ 31.435551] [drm:intel_power_well_disable] disabling dpio-common-a [ 31.435558] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 31.438642] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 31.438645] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.438648] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.438649] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.438650] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.438651] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.438652] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.438654] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.438655] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.438656] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.438657] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 31.438658] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.438660] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.438661] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.438663] [drm:verify_single_dpll_state] PORT PLL A [ 31.438664] [drm:verify_single_dpll_state] PORT PLL B [ 31.438665] [drm:verify_single_dpll_state] PORT PLL C [ 31.438673] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 31.438673] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 31.439454] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 31.439457] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 31.440565] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 31.443841] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 31.443884] [drm:skylake_pfit_enable] for crtc_state = ffff88026e44f800 [ 31.443939] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 31.443942] [drm:intel_enable_pipe] enabling pipe B [ 31.443962] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 31.443964] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 31.443997] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 31.448103] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.448108] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 31.448124] [drm:verify_single_dpll_state] PORT PLL B [ 31.452241] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 31.472801] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 31.476938] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 31.476942] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 31.476944] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.476953] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B [ 31.476967] [drm:intel_disable_pipe] disabling pipe B [ 31.481890] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31 [ 31.481898] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 31.481901] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 31.485643] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 31.485647] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.485650] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.485652] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.485653] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.485654] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.485655] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.485657] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.485658] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.485659] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.485661] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 31.485662] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.485664] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.485665] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.485667] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.485669] [drm:verify_single_dpll_state] PORT PLL A [ 31.485670] [drm:verify_single_dpll_state] PORT PLL B [ 31.485672] [drm:verify_single_dpll_state] PORT PLL C [ 31.485677] [drm:intel_power_well_disable] disabling dpio-common-bc [ 31.485679] [drm:intel_power_well_disable] disabling power well 2 [ 31.485683] [drm:skl_set_power_well] Disabling power well 2 [ 31.485687] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 31.485688] [drm:intel_power_well_disable] disabling DC off [ 31.485690] [drm:gen9_enable_dc5] Enabling DC5 [ 31.485692] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 31.485694] [drm:intel_power_well_disable] disabling always-on [ 31.487192] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.487292] [drm:drm_mode_addfb2] [FB:107] [ 31.490678] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.490683] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 31.490691] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 31.490693] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 31.490695] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 31.490698] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 31.490699] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 31.490701] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 31.490703] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802704b6800 for pipe B [ 31.490704] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 31.490705] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 31.490706] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 31.490708] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 31.490710] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 31.490711] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 31.490712] [drm:intel_dump_pipe_config] requested mode: [ 31.490714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 31.490715] [drm:intel_dump_pipe_config] adjusted mode: [ 31.490717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 31.490719] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 31.490720] [drm:intel_dump_pipe_config] port clock: 162000 [ 31.490721] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 31.490722] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 31.490724] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 31.490725] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 31.490726] [drm:intel_dump_pipe_config] ips: 0 [ 31.490727] [drm:intel_dump_pipe_config] double wide: 0 [ 31.490729] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 31.490730] [drm:intel_dump_pipe_config] planes on this crtc [ 31.490731] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 31.490733] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 31.490734] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 31.490735] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 31.490738] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 31.490740] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 31.490743] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL C [ 31.490745] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe B [ 31.490746] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.490838] [drm:intel_power_well_enable] enabling always-on [ 31.490840] [drm:intel_power_well_enable] enabling DC off [ 31.490903] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 31.490906] [drm:intel_power_well_enable] enabling power well 2 [ 31.490908] [drm:skl_set_power_well] Enabling power well 2 [ 31.490912] [drm:intel_power_well_enable] enabling dpio-common-bc [ 31.490913] [drm:intel_power_well_enable] enabling dpio-common-a [ 31.492966] [drm:intel_power_well_disable] disabling dpio-common-a [ 31.492974] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 31.496513] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 31.496516] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.496518] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.496520] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.496521] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.496522] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.496523] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.496524] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.496525] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.496526] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.496527] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 31.496529] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.496530] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.496532] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.496533] [drm:verify_single_dpll_state] PORT PLL A [ 31.496535] [drm:verify_single_dpll_state] PORT PLL B [ 31.496536] [drm:verify_single_dpll_state] PORT PLL C [ 31.496542] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 2, on? 0) for crtc 31 [ 31.496543] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 31.499728] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 31.499730] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 31.500337] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 31.500873] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 31.500875] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 31.502035] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 31.502086] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b6800 [ 31.502140] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 31.502142] [drm:intel_enable_pipe] enabling pipe B [ 31.502181] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 31.506311] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.506315] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 31.506329] [drm:verify_single_dpll_state] PORT PLL C [ 31.510447] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 31.530982] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 31.535119] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 31.535124] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 31.535126] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.535141] [drm:intel_disable_pipe] disabling pipe B [ 31.539265] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 2, on? 1) for crtc 31 [ 31.539273] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 31.539277] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 31.543211] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 31.543214] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.543217] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.543219] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.543221] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.543222] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.543223] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.543225] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.543226] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.543227] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.543228] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 31.543229] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.543231] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.543233] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.543234] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.543236] [drm:verify_single_dpll_state] PORT PLL A [ 31.543238] [drm:verify_single_dpll_state] PORT PLL B [ 31.543239] [drm:verify_single_dpll_state] PORT PLL C [ 31.543244] [drm:intel_power_well_disable] disabling dpio-common-bc [ 31.543246] [drm:intel_power_well_disable] disabling power well 2 [ 31.543250] [drm:skl_set_power_well] Disabling power well 2 [ 31.543254] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 31.543256] [drm:intel_power_well_disable] disabling DC off [ 31.543258] [drm:gen9_enable_dc5] Enabling DC5 [ 31.543259] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 31.543261] [drm:intel_power_well_disable] disabling always-on [ 31.544673] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.544773] [drm:drm_mode_addfb2] [FB:107] [ 31.548111] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.548117] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 31.548124] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 31.548125] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 31.548127] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 31.548130] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 31.548131] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 31.548132] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 31.548134] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802704b7800 for pipe B [ 31.548135] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 31.548136] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 31.548138] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 31.548139] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 31.548140] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 31.548141] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 31.548142] [drm:intel_dump_pipe_config] requested mode: [ 31.548144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 31.548145] [drm:intel_dump_pipe_config] adjusted mode: [ 31.548147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 31.548149] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 31.548150] [drm:intel_dump_pipe_config] port clock: 162000 [ 31.548151] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 31.548152] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 31.548153] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 31.548154] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 31.548155] [drm:intel_dump_pipe_config] ips: 0 [ 31.548156] [drm:intel_dump_pipe_config] double wide: 0 [ 31.548158] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 31.548159] [drm:intel_dump_pipe_config] planes on this crtc [ 31.548160] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 31.548161] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 31.548162] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 31.548163] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 31.548166] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 31.548168] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 31.548171] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL C [ 31.548172] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe B [ 31.548173] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.548263] [drm:intel_power_well_enable] enabling always-on [ 31.548264] [drm:intel_power_well_enable] enabling DC off [ 31.548327] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 31.548330] [drm:intel_power_well_enable] enabling power well 2 [ 31.548332] [drm:skl_set_power_well] Enabling power well 2 [ 31.548336] [drm:intel_power_well_enable] enabling dpio-common-bc [ 31.548337] [drm:intel_power_well_enable] enabling dpio-common-a [ 31.552044] [drm:intel_power_well_disable] disabling dpio-common-a [ 31.552051] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 31.556065] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 31.556068] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.556071] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.556073] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.556074] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.556075] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.556076] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.556077] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.556078] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.556079] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.556080] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 31.556081] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.556083] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.556085] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.556086] [drm:verify_single_dpll_state] PORT PLL A [ 31.556088] [drm:verify_single_dpll_state] PORT PLL B [ 31.556089] [drm:verify_single_dpll_state] PORT PLL C [ 31.556096] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 2, on? 0) for crtc 31 [ 31.556097] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 31.557863] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 31.557865] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 31.558420] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 31.558959] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 31.558960] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 31.560210] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 31.560252] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b7800 [ 31.560306] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 31.560308] [drm:intel_enable_pipe] enabling pipe B [ 31.560346] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 31.564467] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.564470] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 31.564484] [drm:verify_single_dpll_state] PORT PLL C [ 31.568632] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 31.589186] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 31.593294] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 31.593298] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 31.593301] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.593316] [drm:intel_disable_pipe] disabling pipe B [ 31.597583] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 2, on? 1) for crtc 31 [ 31.597590] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 31.597595] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 31.600870] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 31.600873] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.600876] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.600878] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.600880] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.600881] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.600882] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.600884] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.600885] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.600886] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.600887] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 31.600888] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.600890] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.600892] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.600893] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.600895] [drm:verify_single_dpll_state] PORT PLL A [ 31.600897] [drm:verify_single_dpll_state] PORT PLL B [ 31.600898] [drm:verify_single_dpll_state] PORT PLL C [ 31.600903] [drm:intel_power_well_disable] disabling dpio-common-bc [ 31.600905] [drm:intel_power_well_disable] disabling power well 2 [ 31.600909] [drm:skl_set_power_well] Disabling power well 2 [ 31.600912] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 31.600914] [drm:intel_power_well_disable] disabling DC off [ 31.600916] [drm:gen9_enable_dc5] Enabling DC5 [ 31.600918] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 31.600920] [drm:intel_power_well_disable] disabling always-on [ 31.602212] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-B [ 31.622330] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-B [ 31.622776] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.622870] [drm:drm_mode_addfb2] [FB:107] [ 31.626284] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.626288] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 31.626296] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 31.626298] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 31.626300] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.626302] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 31.626305] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 31.626307] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 31.626308] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 31.626310] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff88007798d800 for pipe B [ 31.626312] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 31.626313] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 31.626314] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 31.626316] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 31.626317] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 31.626318] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 31.626319] [drm:intel_dump_pipe_config] requested mode: [ 31.626322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 31.626323] [drm:intel_dump_pipe_config] adjusted mode: [ 31.626325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 31.626326] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 31.626328] [drm:intel_dump_pipe_config] port clock: 270000 [ 31.626329] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 31.626330] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 31.626331] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 31.626332] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 31.626333] [drm:intel_dump_pipe_config] ips: 0 [ 31.626334] [drm:intel_dump_pipe_config] double wide: 0 [ 31.626337] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 31.626338] [drm:intel_dump_pipe_config] planes on this crtc [ 31.626339] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 31.626340] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 31.626341] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 31.626343] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 31.626345] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 31.626347] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 31.626350] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL A [ 31.626351] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe B [ 31.626353] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.626483] [drm:intel_power_well_enable] enabling always-on [ 31.626484] [drm:intel_power_well_enable] enabling DC off [ 31.626486] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 31.626489] [drm:intel_power_well_enable] enabling power well 2 [ 31.626491] [drm:skl_set_power_well] Enabling power well 2 [ 31.626495] [drm:intel_power_well_enable] enabling dpio-common-a [ 31.631051] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.631054] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.631056] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.631057] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.631059] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.631060] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.631061] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.631062] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.631063] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.631064] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.631066] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.631067] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.631068] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.631069] [drm:verify_single_dpll_state] PORT PLL A [ 31.631071] [drm:verify_single_dpll_state] PORT PLL B [ 31.631072] [drm:verify_single_dpll_state] PORT PLL C [ 31.631080] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 2, on? 0) for crtc 31 [ 31.631081] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 31.631112] [drm:edp_panel_on] Turn eDP port A panel power on [ 31.631114] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 31.631118] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 31.631119] [drm:wait_panel_status] Wait complete [ 31.631120] [drm:wait_panel_on] Wait for panel power on [ 31.631122] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 31.657453] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 31.657456] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 31.657458] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 31.657483] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 31.700151] [drm:wait_panel_status] Wait complete [ 31.700157] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 31.700160] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 31.700891] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 31.700893] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 31.701124] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 31.701658] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 31.701699] [drm:skylake_pfit_enable] for crtc_state = ffff88007798d800 [ 31.701759] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 31.701762] [drm:intel_enable_pipe] enabling pipe B [ 31.701776] [drm:intel_edp_backlight_on] [ 31.701778] [drm:intel_panel_enable_backlight] pipe B [ 31.701779] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 31.701782] [drm:intel_psr_enable] PSR not supported on this platform [ 31.701783] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 31.701805] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 31.705950] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 31.705956] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 31.705972] [drm:verify_single_dpll_state] PORT PLL A [ 31.710079] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 31.730604] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 31.734738] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 31.734742] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 31.734745] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.734756] [drm:intel_edp_backlight_off] [ 31.931933] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 31.931942] [drm:intel_disable_pipe] disabling pipe B [ 31.933425] [drm:edp_panel_off] Turn eDP port A panel power off [ 31.933429] [drm:wait_panel_off] Wait for panel power off time [ 31.933431] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 31.946371] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 31.946375] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 31.946376] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 31.946395] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 31.950170] [drm:wait_panel_status] Wait complete [ 31.950177] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 2, on? 1) for crtc 31 [ 31.950184] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 31.950188] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.950190] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.950192] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.950193] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.950194] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.950195] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.950196] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.950197] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.950198] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.950200] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 31.950201] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.950203] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.950204] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.950205] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.950206] [drm:verify_single_dpll_state] PORT PLL A [ 31.950208] [drm:verify_single_dpll_state] PORT PLL B [ 31.950209] [drm:verify_single_dpll_state] PORT PLL C [ 31.950213] [drm:intel_power_well_disable] disabling power well 2 [ 31.950217] [drm:skl_set_power_well] Disabling power well 2 [ 31.950219] [drm:intel_power_well_disable] disabling dpio-common-a [ 31.950222] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 31.950224] [drm:intel_power_well_disable] disabling DC off [ 31.950226] [drm:gen9_enable_dc5] Enabling DC5 [ 31.950227] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 31.950229] [drm:intel_power_well_disable] disabling always-on [ 31.951607] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.951706] [drm:drm_mode_addfb2] [FB:107] [ 31.955010] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 31.955014] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 31.955022] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 31.955023] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 31.955026] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.955027] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 31.955030] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 31.955031] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 31.955033] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 31.955034] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802704b5000 for pipe B [ 31.955036] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 31.955037] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 31.955038] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 31.955039] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 31.955041] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 31.955042] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 31.955043] [drm:intel_dump_pipe_config] requested mode: [ 31.955044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 31.955045] [drm:intel_dump_pipe_config] adjusted mode: [ 31.955047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 31.955049] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 31.955050] [drm:intel_dump_pipe_config] port clock: 270000 [ 31.955051] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 31.955052] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 31.955053] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 31.955054] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 31.955055] [drm:intel_dump_pipe_config] ips: 0 [ 31.955056] [drm:intel_dump_pipe_config] double wide: 0 [ 31.955058] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 31.955059] [drm:intel_dump_pipe_config] planes on this crtc [ 31.955060] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 31.955061] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 31.955062] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 31.955063] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 31.955065] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 31.955067] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 31.955070] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL A [ 31.955071] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe B [ 31.955072] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 31.955161] [drm:intel_power_well_enable] enabling always-on [ 31.955163] [drm:intel_power_well_enable] enabling DC off [ 31.955225] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 31.955229] [drm:intel_power_well_enable] enabling power well 2 [ 31.955230] [drm:skl_set_power_well] Enabling power well 2 [ 31.955234] [drm:intel_power_well_enable] enabling dpio-common-a [ 31.959064] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 31.959067] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 31.959069] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 31.959070] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 31.959071] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 31.959072] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 31.959074] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 31.959074] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 31.959075] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 31.959077] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 31.959078] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 31.959079] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 31.959080] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 31.959081] [drm:verify_single_dpll_state] PORT PLL A [ 31.959082] [drm:verify_single_dpll_state] PORT PLL B [ 31.959084] [drm:verify_single_dpll_state] PORT PLL C [ 31.959091] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 2, on? 0) for crtc 31 [ 31.959092] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 31.959122] [drm:edp_panel_on] Turn eDP port A panel power on [ 31.959123] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 32.099569] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 32.099572] [drm:wait_panel_status] Wait complete [ 32.099573] [drm:wait_panel_on] Wait for panel power on [ 32.099575] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 32.125891] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 32.125894] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 32.125896] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 32.125920] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 32.154986] [drm:wait_panel_status] Wait complete [ 32.154993] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 32.154996] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 32.155722] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 32.155723] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 32.155964] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 32.156496] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 32.156538] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b5000 [ 32.156598] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 32.156600] [drm:intel_enable_pipe] enabling pipe B [ 32.156616] [drm:intel_edp_backlight_on] [ 32.156617] [drm:intel_panel_enable_backlight] pipe B [ 32.156619] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 32.156621] [drm:intel_psr_enable] PSR not supported on this platform [ 32.156622] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 32.156645] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 32.160753] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 32.160757] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 32.160773] [drm:verify_single_dpll_state] PORT PLL A [ 32.164925] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 32.185446] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 32.189590] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 32.189594] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 32.189596] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 32.189608] [drm:intel_edp_backlight_off] [ 32.253579] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 32.253588] [drm:intel_disable_pipe] disabling pipe B [ 32.256633] [drm:edp_panel_off] Turn eDP port A panel power off [ 32.256638] [drm:wait_panel_off] Wait for panel power off time [ 32.256641] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 32.269595] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 32.269599] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 32.269601] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 32.269628] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 32.274511] [drm:wait_panel_status] Wait complete [ 32.274519] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 2, on? 1) for crtc 31 [ 32.274526] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 32.274531] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 32.274533] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 32.274534] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 32.274535] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 32.274537] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 32.274538] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 32.274541] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 32.274545] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 32.274550] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 32.274552] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 32.274553] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 32.274555] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 32.274556] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 32.274557] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 32.274558] [drm:verify_single_dpll_state] PORT PLL A [ 32.274560] [drm:verify_single_dpll_state] PORT PLL B [ 32.274561] [drm:verify_single_dpll_state] PORT PLL C [ 32.274565] [drm:intel_power_well_disable] disabling power well 2 [ 32.274569] [drm:skl_set_power_well] Disabling power well 2 [ 32.274571] [drm:intel_power_well_disable] disabling dpio-common-a [ 32.274574] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 32.274578] [drm:intel_power_well_disable] disabling DC off [ 32.274582] [drm:gen9_enable_dc5] Enabling DC5 [ 32.274585] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 32.274588] [drm:intel_power_well_disable] disabling always-on [ 32.275987] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 32.276086] [drm:drm_mode_addfb2] [FB:107] [ 32.279458] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 32.279462] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 32.279470] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 32.279472] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 32.279474] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 32.279477] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 32.279478] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 32.279480] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 32.279481] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802709d3000 for pipe B [ 32.279483] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 32.279484] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 32.279485] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 32.279487] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 32.279488] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 32.279490] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 32.279490] [drm:intel_dump_pipe_config] requested mode: [ 32.279493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 32.279494] [drm:intel_dump_pipe_config] adjusted mode: [ 32.279496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 32.279497] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 32.279499] [drm:intel_dump_pipe_config] port clock: 162000 [ 32.279500] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 32.279501] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 32.279502] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 32.279504] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 32.279505] [drm:intel_dump_pipe_config] ips: 0 [ 32.279506] [drm:intel_dump_pipe_config] double wide: 0 [ 32.279508] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 32.279509] [drm:intel_dump_pipe_config] planes on this crtc [ 32.279510] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 32.279511] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 32.279512] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 32.279514] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 32.279516] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 32.279519] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 32.279522] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 32.279523] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 32.279525] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 32.279616] [drm:intel_power_well_enable] enabling always-on [ 32.279618] [drm:intel_power_well_enable] enabling DC off [ 32.279681] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 32.279684] [drm:intel_power_well_enable] enabling power well 2 [ 32.279686] [drm:skl_set_power_well] Enabling power well 2 [ 32.279690] [drm:intel_power_well_enable] enabling dpio-common-bc [ 32.279691] [drm:intel_power_well_enable] enabling dpio-common-a [ 32.281793] [drm:intel_power_well_disable] disabling dpio-common-a [ 32.281801] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 32.285888] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 32.285892] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 32.285895] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 32.285896] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 32.285897] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 32.285898] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 32.285900] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 32.285901] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 32.285903] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 32.285904] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 32.285905] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 32.285906] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 32.285908] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 32.285910] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 32.285911] [drm:verify_single_dpll_state] PORT PLL A [ 32.285913] [drm:verify_single_dpll_state] PORT PLL B [ 32.285914] [drm:verify_single_dpll_state] PORT PLL C [ 32.285921] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 32.285922] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 32.288156] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 32.288158] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 32.289285] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 32.292185] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 32.292231] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d3000 [ 32.292287] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 32.292289] [drm:intel_enable_pipe] enabling pipe B [ 32.292304] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 32.292306] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 32.292339] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 32.296471] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 32.296477] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 32.296493] [drm:verify_single_dpll_state] PORT PLL B [ 32.300586] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 32.321130] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 32.325267] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 32.325271] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 32.325274] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 32.325284] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B [ 32.325299] [drm:intel_disable_pipe] disabling pipe B [ 32.330513] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31 [ 32.330522] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 32.330526] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 32.333528] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 32.333531] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 32.333534] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 32.333536] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 32.333538] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 32.333539] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 32.333540] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 32.333541] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 32.333542] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 32.333544] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 32.333545] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 32.333546] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 32.333548] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 32.333549] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 32.333551] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 32.333553] [drm:verify_single_dpll_state] PORT PLL A [ 32.333554] [drm:verify_single_dpll_state] PORT PLL B [ 32.333556] [drm:verify_single_dpll_state] PORT PLL C [ 32.333561] [drm:intel_power_well_disable] disabling dpio-common-bc [ 32.333563] [drm:intel_power_well_disable] disabling power well 2 [ 32.333567] [drm:skl_set_power_well] Disabling power well 2 [ 32.333570] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 32.333572] [drm:intel_power_well_disable] disabling DC off [ 32.333574] [drm:gen9_enable_dc5] Enabling DC5 [ 32.333575] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 32.333577] [drm:intel_power_well_disable] disabling always-on [ 32.335005] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 32.335105] [drm:drm_mode_addfb2] [FB:107] [ 32.338450] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 32.338455] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 32.338462] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 32.338464] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 32.338466] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 32.338468] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 32.338469] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 32.338471] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 32.338473] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802704b6000 for pipe B [ 32.338474] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 32.338475] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 32.338476] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 32.338477] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 32.338479] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 32.338480] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 32.338481] [drm:intel_dump_pipe_config] requested mode: [ 32.338483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 32.338484] [drm:intel_dump_pipe_config] adjusted mode: [ 32.338485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 32.338487] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 32.338488] [drm:intel_dump_pipe_config] port clock: 162000 [ 32.338489] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 32.338490] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 32.338491] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 32.338492] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 32.338493] [drm:intel_dump_pipe_config] ips: 0 [ 32.338494] [drm:intel_dump_pipe_config] double wide: 0 [ 32.338496] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 32.338497] [drm:intel_dump_pipe_config] planes on this crtc [ 32.338498] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 32.338499] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 32.338500] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 32.338501] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 32.338504] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 32.338506] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 32.338509] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 32.338510] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 32.338511] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 32.338601] [drm:intel_power_well_enable] enabling always-on [ 32.338602] [drm:intel_power_well_enable] enabling DC off [ 32.338665] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 32.338668] [drm:intel_power_well_enable] enabling power well 2 [ 32.338669] [drm:skl_set_power_well] Enabling power well 2 [ 32.338673] [drm:intel_power_well_enable] enabling dpio-common-bc [ 32.338674] [drm:intel_power_well_enable] enabling dpio-common-a [ 32.343758] [drm:intel_power_well_disable] disabling dpio-common-a [ 32.343765] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 32.347851] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 32.347854] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 32.347857] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 32.347858] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 32.347859] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 32.347860] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 32.347861] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 32.347863] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 32.347864] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 32.347865] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 32.347866] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 32.347867] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 32.347869] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 32.347870] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 32.347872] [drm:verify_single_dpll_state] PORT PLL A [ 32.347873] [drm:verify_single_dpll_state] PORT PLL B [ 32.347874] [drm:verify_single_dpll_state] PORT PLL C [ 32.347881] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 32.347882] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 32.348630] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 32.348632] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 32.350923] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 32.354212] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 32.354262] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b6000 [ 32.354316] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 32.354319] [drm:intel_enable_pipe] enabling pipe B [ 32.354339] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 32.354341] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 32.354375] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 32.358497] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 32.358502] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 32.358517] [drm:verify_single_dpll_state] PORT PLL B [ 32.362637] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 32.383164] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 32.387299] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 32.387304] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 32.387306] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 32.387317] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B [ 32.387332] [drm:intel_disable_pipe] disabling pipe B [ 32.391467] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31 [ 32.391476] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 32.391480] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 32.395408] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 32.395411] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 32.395414] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 32.395416] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 32.395417] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 32.395419] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 32.395420] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 32.395421] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 32.395422] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 32.395423] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 32.395425] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 32.395426] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 32.395428] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 32.395429] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 32.395431] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 32.395433] [drm:verify_single_dpll_state] PORT PLL A [ 32.395434] [drm:verify_single_dpll_state] PORT PLL B [ 32.395436] [drm:verify_single_dpll_state] PORT PLL C [ 32.395441] [drm:intel_power_well_disable] disabling dpio-common-bc [ 32.395443] [drm:intel_power_well_disable] disabling power well 2 [ 32.395447] [drm:skl_set_power_well] Disabling power well 2 [ 32.395450] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 32.395452] [drm:intel_power_well_disable] disabling DC off [ 32.395454] [drm:gen9_enable_dc5] Enabling DC5 [ 32.395456] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 32.395458] [drm:intel_power_well_disable] disabling always-on [ 32.396904] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 32.397003] [drm:drm_mode_addfb2] [FB:107] [ 32.400303] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 32.400307] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 32.400314] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 32.400316] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 32.400318] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 32.400320] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 32.400321] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 32.400323] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 32.400325] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802704b5800 for pipe B [ 32.400326] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 32.400327] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 32.400328] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 32.400329] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 32.400331] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 32.400332] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 32.400333] [drm:intel_dump_pipe_config] requested mode: [ 32.400335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 32.400336] [drm:intel_dump_pipe_config] adjusted mode: [ 32.400337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 32.400339] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 32.400340] [drm:intel_dump_pipe_config] port clock: 162000 [ 32.400341] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 32.400342] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 32.400343] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 32.400344] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 32.400345] [drm:intel_dump_pipe_config] ips: 0 [ 32.400346] [drm:intel_dump_pipe_config] double wide: 0 [ 32.400348] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 32.400349] [drm:intel_dump_pipe_config] planes on this crtc [ 32.400350] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 32.400351] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 32.400352] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 32.400353] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 32.400356] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 32.400358] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 32.400361] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL C [ 32.400362] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe B [ 32.400364] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 32.400452] [drm:intel_power_well_enable] enabling always-on [ 32.400453] [drm:intel_power_well_enable] enabling DC off [ 32.400516] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 32.400519] [drm:intel_power_well_enable] enabling power well 2 [ 32.400521] [drm:skl_set_power_well] Enabling power well 2 [ 32.400525] [drm:intel_power_well_enable] enabling dpio-common-bc [ 32.400526] [drm:intel_power_well_enable] enabling dpio-common-a [ 32.404259] [drm:intel_power_well_disable] disabling dpio-common-a [ 32.404267] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 32.408326] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 32.408329] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 32.408332] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 32.408334] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 32.408335] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 32.408336] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 32.408337] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 32.408338] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 32.408339] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 32.408340] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 32.408341] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 32.408342] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 32.408344] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 32.408345] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 32.408347] [drm:verify_single_dpll_state] PORT PLL A [ 32.408348] [drm:verify_single_dpll_state] PORT PLL B [ 32.408349] [drm:verify_single_dpll_state] PORT PLL C [ 32.408356] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 2, on? 0) for crtc 31 [ 32.408357] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 32.409956] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 32.409959] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 32.410309] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 32.410311] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 32.410545] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 32.411085] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 32.411086] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 32.412871] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 32.412915] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b5800 [ 32.412968] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 32.412970] [drm:intel_enable_pipe] enabling pipe B [ 32.413006] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 32.417125] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 32.417129] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 32.417142] [drm:verify_single_dpll_state] PORT PLL C [ 32.421287] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 32.441816] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 32.445949] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 32.445954] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 32.445956] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 32.445970] [drm:intel_disable_pipe] disabling pipe B [ 32.451502] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 2, on? 1) for crtc 31 [ 32.451509] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 32.451513] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 32.455595] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 32.455598] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 32.455601] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 32.455602] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 32.455604] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 32.455605] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 32.455606] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 32.455607] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 32.455608] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 32.455609] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 32.455610] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 32.455611] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 32.455613] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 32.455614] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 32.455616] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 32.455617] [drm:verify_single_dpll_state] PORT PLL A [ 32.455619] [drm:verify_single_dpll_state] PORT PLL B [ 32.455620] [drm:verify_single_dpll_state] PORT PLL C [ 32.455625] [drm:intel_power_well_disable] disabling dpio-common-bc [ 32.455626] [drm:intel_power_well_disable] disabling power well 2 [ 32.455630] [drm:skl_set_power_well] Disabling power well 2 [ 32.455633] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 32.455635] [drm:intel_power_well_disable] disabling DC off [ 32.455636] [drm:gen9_enable_dc5] Enabling DC5 [ 32.455638] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 32.455640] [drm:intel_power_well_disable] disabling always-on [ 32.457039] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 32.457139] [drm:drm_mode_addfb2] [FB:107] [ 32.460309] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 32.460313] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 32.460320] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 32.460322] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 32.460324] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 32.460326] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 32.460327] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 32.460329] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 32.460331] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802709d2000 for pipe B [ 32.460332] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 32.460333] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 32.460334] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 32.460335] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 32.460337] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 32.460338] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 32.460339] [drm:intel_dump_pipe_config] requested mode: [ 32.460341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 32.460342] [drm:intel_dump_pipe_config] adjusted mode: [ 32.460343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 32.460345] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 32.460346] [drm:intel_dump_pipe_config] port clock: 162000 [ 32.460347] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 32.460348] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 32.460349] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 32.460350] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 32.460351] [drm:intel_dump_pipe_config] ips: 0 [ 32.460352] [drm:intel_dump_pipe_config] double wide: 0 [ 32.460354] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 32.460355] [drm:intel_dump_pipe_config] planes on this crtc [ 32.460356] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 32.460357] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 32.460358] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 32.460359] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 32.460362] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 32.460364] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 32.460367] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL C [ 32.460368] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe B [ 32.460369] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 32.460458] [drm:intel_power_well_enable] enabling always-on [ 32.460459] [drm:intel_power_well_enable] enabling DC off [ 32.460522] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 32.460525] [drm:intel_power_well_enable] enabling power well 2 [ 32.460527] [drm:skl_set_power_well] Enabling power well 2 [ 32.460530] [drm:intel_power_well_enable] enabling dpio-common-bc [ 32.460531] [drm:intel_power_well_enable] enabling dpio-common-a [ 32.462314] [drm:intel_power_well_disable] disabling dpio-common-a [ 32.462323] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 32.466410] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 32.466413] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 32.466416] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 32.466418] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 32.466419] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 32.466420] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 32.466421] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 32.466422] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 32.466423] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 32.466424] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 32.466425] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 32.466426] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 32.466428] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 32.466429] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 32.466431] [drm:verify_single_dpll_state] PORT PLL A [ 32.466432] [drm:verify_single_dpll_state] PORT PLL B [ 32.466433] [drm:verify_single_dpll_state] PORT PLL C [ 32.466440] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 2, on? 0) for crtc 31 [ 32.466441] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 32.469007] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 32.469009] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 32.469248] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 32.469249] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 32.469480] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 32.470014] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 32.470015] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 32.472547] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 32.472589] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d2000 [ 32.472643] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 32.472646] [drm:intel_enable_pipe] enabling pipe B [ 32.472687] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 32.476811] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 32.476815] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 32.476829] [drm:verify_single_dpll_state] PORT PLL C [ 32.480960] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 32.501503] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 32.505622] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 32.505626] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 32.505628] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 32.505642] [drm:intel_disable_pipe] disabling pipe B [ 32.509750] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 2, on? 1) for crtc 31 [ 32.509758] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 32.509763] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 32.513483] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 32.513486] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 32.513489] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 32.513491] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 32.513492] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 32.513494] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 32.513495] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 32.513496] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 32.513497] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 32.513498] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 32.513500] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 32.513501] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 32.513503] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 32.513504] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 32.513506] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 32.513508] [drm:verify_single_dpll_state] PORT PLL A [ 32.513509] [drm:verify_single_dpll_state] PORT PLL B [ 32.513511] [drm:verify_single_dpll_state] PORT PLL C [ 32.513516] [drm:intel_power_well_disable] disabling dpio-common-bc [ 32.513518] [drm:intel_power_well_disable] disabling power well 2 [ 32.513522] [drm:skl_set_power_well] Disabling power well 2 [ 32.513525] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 32.513527] [drm:intel_power_well_disable] disabling DC off [ 32.513529] [drm:gen9_enable_dc5] Enabling DC5 [ 32.513530] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 32.513532] [drm:intel_power_well_disable] disabling always-on [ 33.971334] [drm] stuck on render ring [ 33.972646] [drm] GPU HANG: ecode 9:0:0xe757fffe, in kms_pipe_crc_ba [1613], reason: Engine(s) hung, action: reset [ 33.972666] [drm:i915_reset_and_wakeup] resetting chip [ 33.973662] drm/i915: Resetting chip after gpu hang [ 33.973666] [drm:gen8_init_common_ring] Execlists enabled for render ring [ 33.973684] [drm:gen8_init_common_ring] Execlists enabled for blitter ring [ 33.973705] [drm:gen8_init_common_ring] Execlists enabled for bsd ring [ 33.973720] [drm:gen8_init_common_ring] Execlists enabled for video enhancement ring [ 33.973740] [drm:intel_guc_setup] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch SUCCESS, load SUCCESS [ 33.973742] [drm:intel_guc_setup] GuC fw status: fetch SUCCESS, load PENDING [ 33.976606] [drm:guc_ucode_xfer_dma] DMA status 0x10, GuC status 0x8002f0ec [ 33.976607] [drm:guc_ucode_xfer_dma] returning 0 [ 33.976608] [drm:intel_guc_setup] GuC fw status: fetch SUCCESS, load SUCCESS [ 33.976618] [drm:select_doorbell_register] assigned normal priority doorbell id 0x0 [ 33.976619] [drm:select_doorbell_cacheline] selected doorbell cacheline 0x80, next 0xc0, linesize 64 [ 33.976625] [drm:guc_client_alloc] new priority 2 client ffff880271990a00: ctx_index 0 [ 33.976626] [drm:guc_client_alloc] doorbell id 0, cacheline offset 0x80 [ 33.978271] [drm:i915_error_state_write] Resetting error state [ 33.978928] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 33.979015] [drm:drm_mode_addfb2] [FB:107] [ 33.980864] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 33.980867] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 33.980871] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 33.980872] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 33.980873] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 33.980874] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 33.980875] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 33.980876] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 33.980876] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 33.980877] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802704b4800 for pipe B [ 33.980878] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 33.980878] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 33.980879] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 33.980879] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 33.980880] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 33.980880] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 33.980880] [drm:intel_dump_pipe_config] requested mode: [ 33.980881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 33.980881] [drm:intel_dump_pipe_config] adjusted mode: [ 33.980882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 33.980883] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 33.980883] [drm:intel_dump_pipe_config] port clock: 270000 [ 33.980883] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 33.980884] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 33.980884] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 33.980885] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 33.980885] [drm:intel_dump_pipe_config] ips: 0 [ 33.980885] [drm:intel_dump_pipe_config] double wide: 0 [ 33.980886] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 33.980886] [drm:intel_dump_pipe_config] planes on this crtc [ 33.980887] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 33.980887] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 33.980888] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 33.980888] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 33.980889] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 33.980890] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 33.980891] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL A [ 33.980892] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe B [ 33.980892] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 33.980960] [drm:intel_power_well_enable] enabling always-on [ 33.980960] [drm:intel_power_well_enable] enabling DC off [ 33.981023] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 33.981025] [drm:intel_power_well_enable] enabling power well 2 [ 33.981026] [drm:skl_set_power_well] Enabling power well 2 [ 34.191629] [drm:intel_power_well_enable] enabling dpio-common-a [ 34.193488] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 34.193490] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 34.193492] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 34.193492] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 34.193493] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 34.193493] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 34.193495] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 34.193497] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 34.193503] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 34.193503] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 34.193504] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 34.193504] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 34.193505] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 34.193505] [drm:verify_single_dpll_state] PORT PLL A [ 34.193506] [drm:verify_single_dpll_state] PORT PLL B [ 34.193506] [drm:verify_single_dpll_state] PORT PLL C [ 34.193512] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 2, on? 0) for crtc 31 [ 34.193512] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 34.193532] [drm:edp_panel_on] Turn eDP port A panel power on [ 34.193533] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 34.193535] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 34.193536] [drm:wait_panel_status] Wait complete [ 34.193537] [drm:wait_panel_on] Wait for panel power on [ 34.193538] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 34.220674] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 34.220678] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 34.220679] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 34.220707] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 34.246218] [drm:wait_panel_status] Wait complete [ 34.246225] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 34.246227] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 34.246965] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 34.246967] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 34.247194] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 34.247719] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 34.247759] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b4800 [ 34.247819] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 34.247823] [drm:intel_enable_pipe] enabling pipe B [ 34.247839] [drm:intel_edp_backlight_on] [ 34.247840] [drm:intel_panel_enable_backlight] pipe B [ 34.247842] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 34.247844] [drm:intel_psr_enable] PSR not supported on this platform [ 34.247846] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 34.247868] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 34.251974] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 34.251978] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 34.251994] [drm:verify_single_dpll_state] PORT PLL A [ 34.256135] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 34.276668] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 34.280803] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 34.280808] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 34.280810] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 34.280822] [drm:intel_edp_backlight_off] [ 34.409370] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 34.409379] [drm:intel_disable_pipe] disabling pipe B [ 34.413513] [drm:edp_panel_off] Turn eDP port A panel power off [ 34.413519] [drm:wait_panel_off] Wait for panel power off time [ 34.413522] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 34.426961] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 34.426964] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 34.426966] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 34.426983] [drm:wait_panel_status] Wait complete [ 34.426988] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 2, on? 1) for crtc 31 [ 34.426994] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 34.426998] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 34.427001] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 34.427007] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 34.427007] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 34.427009] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 34.427012] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 34.427019] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 34.427021] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 34.427022] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 34.427024] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 34.427025] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 34.427027] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 34.427029] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 34.427030] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 34.427033] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 34.427035] [drm:verify_single_dpll_state] PORT PLL A [ 34.427037] [drm:verify_single_dpll_state] PORT PLL B [ 34.427038] [drm:verify_single_dpll_state] PORT PLL C [ 34.427042] [drm:intel_power_well_disable] disabling power well 2 [ 34.427046] [drm:skl_set_power_well] Disabling power well 2 [ 34.427048] [drm:intel_power_well_disable] disabling dpio-common-a [ 34.427051] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 34.427053] [drm:intel_power_well_disable] disabling DC off [ 34.427054] [drm:gen9_enable_dc5] Enabling DC5 [ 34.427056] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 34.427058] [drm:intel_power_well_disable] disabling always-on [ 34.428354] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 34.428452] [drm:drm_mode_addfb2] [FB:107] [ 34.431588] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 34.431593] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 34.431600] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 34.431601] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 34.431604] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 34.431605] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 34.431608] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 34.431609] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 34.431611] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 34.431613] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802709d0000 for pipe B [ 34.431614] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 34.431615] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 34.431616] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 34.431617] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 34.431619] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 34.431620] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 34.431621] [drm:intel_dump_pipe_config] requested mode: [ 34.431623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 34.431624] [drm:intel_dump_pipe_config] adjusted mode: [ 34.431625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 34.431627] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 34.431628] [drm:intel_dump_pipe_config] port clock: 270000 [ 34.431629] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 34.431630] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 34.431631] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 34.431632] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 34.431633] [drm:intel_dump_pipe_config] ips: 0 [ 34.431634] [drm:intel_dump_pipe_config] double wide: 0 [ 34.431636] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 34.431637] [drm:intel_dump_pipe_config] planes on this crtc [ 34.431638] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 34.431639] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 34.431640] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 34.431641] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 34.431643] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 34.431646] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 34.431648] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL A [ 34.431649] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe B [ 34.431651] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 34.431740] [drm:intel_power_well_enable] enabling always-on [ 34.431741] [drm:intel_power_well_enable] enabling DC off [ 34.431804] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 34.431807] [drm:intel_power_well_enable] enabling power well 2 [ 34.431809] [drm:skl_set_power_well] Enabling power well 2 [ 34.431813] [drm:intel_power_well_enable] enabling dpio-common-a [ 34.445414] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 34.445418] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 34.445420] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 34.445421] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 34.445422] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 34.445423] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 34.445424] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 34.445425] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 34.445426] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 34.445427] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 34.445428] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 34.445429] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 34.445430] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 34.445431] [drm:verify_single_dpll_state] PORT PLL A [ 34.445433] [drm:verify_single_dpll_state] PORT PLL B [ 34.445434] [drm:verify_single_dpll_state] PORT PLL C [ 34.445441] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 2, on? 0) for crtc 31 [ 34.445442] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 34.445470] [drm:edp_panel_on] Turn eDP port A panel power on [ 34.445472] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 34.591639] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 34.591642] [drm:wait_panel_status] Wait complete [ 34.591643] [drm:wait_panel_on] Wait for panel power on [ 34.591645] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 34.619947] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 34.619950] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 34.619952] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 34.619986] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 34.620588] [drm] RC6 on [ 34.659774] [drm:wait_panel_status] Wait complete [ 34.659781] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 34.659783] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 34.660509] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 34.660511] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 34.660738] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 34.661263] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 34.661303] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d0000 [ 34.661364] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 34.661367] [drm:intel_enable_pipe] enabling pipe B [ 34.661380] [drm:intel_edp_backlight_on] [ 34.661381] [drm:intel_panel_enable_backlight] pipe B [ 34.661383] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 34.663260] [drm:intel_psr_enable] PSR not supported on this platform [ 34.663265] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 34.663289] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 34.665518] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 34.665522] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 34.665538] [drm:verify_single_dpll_state] PORT PLL A [ 34.669682] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 34.690211] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 34.694341] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 34.694345] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 34.694348] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 34.694359] [drm:intel_edp_backlight_off] [ 34.762557] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 34.762563] [drm:intel_disable_pipe] disabling pipe B [ 34.764689] [drm:edp_panel_off] Turn eDP port A panel power off [ 34.764694] [drm:wait_panel_off] Wait for panel power off time [ 34.764695] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 34.777469] [drm:wait_panel_status] Wait complete [ 34.777475] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 2, on? 1) for crtc 31 [ 34.777482] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 34.777486] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 34.777488] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 34.777490] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 34.777491] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 34.777492] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 34.777493] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 34.777494] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 34.777495] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 34.777501] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 34.777502] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 34.777502] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 34.777503] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 34.777503] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 34.777504] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 34.777504] [drm:verify_single_dpll_state] PORT PLL A [ 34.777505] [drm:verify_single_dpll_state] PORT PLL B [ 34.777505] [drm:verify_single_dpll_state] PORT PLL C [ 34.777507] [drm:intel_power_well_disable] disabling power well 2 [ 34.777510] [drm:skl_set_power_well] Disabling power well 2 [ 34.777511] [drm:intel_power_well_disable] disabling dpio-common-a [ 34.777512] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 34.777513] [drm:intel_power_well_disable] disabling DC off [ 34.777514] [drm:gen9_enable_dc5] Enabling DC5 [ 34.777515] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 34.777516] [drm:intel_power_well_disable] disabling always-on [ 34.777642] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 34.777643] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 34.777644] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 34.777677] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 34.779866] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 34.779968] [drm:drm_mode_addfb2] [FB:107] [ 34.783363] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 34.783368] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 34.783376] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 34.783378] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 34.783380] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 34.783383] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 34.783384] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 34.783386] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 34.783388] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802709d6800 for pipe B [ 34.783389] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 34.783390] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 34.783391] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 34.783393] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 34.783394] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 34.783396] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 34.783397] [drm:intel_dump_pipe_config] requested mode: [ 34.783399] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 34.783400] [drm:intel_dump_pipe_config] adjusted mode: [ 34.783402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 34.783404] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 34.783405] [drm:intel_dump_pipe_config] port clock: 162000 [ 34.783406] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 34.783407] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 34.783408] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 34.783410] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 34.783411] [drm:intel_dump_pipe_config] ips: 0 [ 34.783412] [drm:intel_dump_pipe_config] double wide: 0 [ 34.783414] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 34.783415] [drm:intel_dump_pipe_config] planes on this crtc [ 34.783416] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 34.783417] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 34.783419] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 34.783420] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 34.783434] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 34.783436] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 34.783439] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 34.783442] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 34.783443] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 34.783536] [drm:intel_power_well_enable] enabling always-on [ 34.783537] [drm:intel_power_well_enable] enabling DC off [ 34.783601] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 34.783605] [drm:intel_power_well_enable] enabling power well 2 [ 34.783607] [drm:skl_set_power_well] Enabling power well 2 [ 34.783611] [drm:intel_power_well_enable] enabling dpio-common-bc [ 34.783612] [drm:intel_power_well_enable] enabling dpio-common-a [ 34.784851] [drm:intel_power_well_disable] disabling dpio-common-a [ 34.784856] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 34.788259] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 34.788262] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 34.788266] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 34.788267] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 34.788268] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 34.788269] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 34.788270] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 34.788272] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 34.788273] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 34.788274] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 34.788276] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 34.788277] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 34.788279] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 34.788280] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 34.788282] [drm:verify_single_dpll_state] PORT PLL A [ 34.788284] [drm:verify_single_dpll_state] PORT PLL B [ 34.788285] [drm:verify_single_dpll_state] PORT PLL C [ 34.788292] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 34.788293] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 34.790948] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 34.790951] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 34.791956] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 34.795042] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 34.795086] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d6800 [ 34.795143] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 34.795146] [drm:intel_enable_pipe] enabling pipe B [ 34.795158] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 34.795160] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 34.795195] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 34.799323] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 34.799328] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 34.799344] [drm:verify_single_dpll_state] PORT PLL B [ 34.803489] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 34.823986] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 34.828150] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 34.828155] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 34.828157] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 34.828168] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B [ 34.828184] [drm:intel_disable_pipe] disabling pipe B [ 34.833861] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31 [ 34.833870] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 34.833874] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 34.837472] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 34.837498] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 34.837501] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 34.837503] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 34.837504] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 34.837505] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 34.837506] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 34.837508] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 34.837509] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 34.837510] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 34.837511] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 34.837513] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 34.837515] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 34.837516] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 34.837518] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 34.837520] [drm:verify_single_dpll_state] PORT PLL A [ 34.837521] [drm:verify_single_dpll_state] PORT PLL B [ 34.837523] [drm:verify_single_dpll_state] PORT PLL C [ 34.837528] [drm:intel_power_well_disable] disabling dpio-common-bc [ 34.837530] [drm:intel_power_well_disable] disabling power well 2 [ 34.837534] [drm:skl_set_power_well] Disabling power well 2 [ 34.837537] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 34.837539] [drm:intel_power_well_disable] disabling DC off [ 34.837541] [drm:gen9_enable_dc5] Enabling DC5 [ 34.837543] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 34.837545] [drm:intel_power_well_disable] disabling always-on [ 34.838938] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 34.839037] [drm:drm_mode_addfb2] [FB:107] [ 34.842370] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 34.842374] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 34.842382] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 34.842383] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 34.842385] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 34.842388] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 34.842389] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 34.842390] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 34.842392] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802709d1800 for pipe B [ 34.842393] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 34.842394] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 34.842395] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 34.842397] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 34.842398] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 34.842399] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 34.842400] [drm:intel_dump_pipe_config] requested mode: [ 34.842402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 34.842403] [drm:intel_dump_pipe_config] adjusted mode: [ 34.842405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 34.842406] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 34.842407] [drm:intel_dump_pipe_config] port clock: 162000 [ 34.842408] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 34.842409] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 34.842411] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 34.842412] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 34.842413] [drm:intel_dump_pipe_config] ips: 0 [ 34.842413] [drm:intel_dump_pipe_config] double wide: 0 [ 34.842415] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 34.842416] [drm:intel_dump_pipe_config] planes on this crtc [ 34.842417] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 34.842419] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 34.842420] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 34.842421] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 34.842423] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 34.842426] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 34.842428] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 34.842429] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 34.842431] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 34.842519] [drm:intel_power_well_enable] enabling always-on [ 34.842521] [drm:intel_power_well_enable] enabling DC off [ 34.842584] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 34.842587] [drm:intel_power_well_enable] enabling power well 2 [ 34.842588] [drm:skl_set_power_well] Enabling power well 2 [ 34.842592] [drm:intel_power_well_enable] enabling dpio-common-bc [ 34.842593] [drm:intel_power_well_enable] enabling dpio-common-a [ 34.844827] [drm:intel_power_well_disable] disabling dpio-common-a [ 34.844834] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 34.847859] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 34.847863] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 34.847866] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 34.847867] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 34.847868] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 34.847869] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 34.847870] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 34.847872] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 34.847873] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 34.847874] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 34.847875] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 34.847876] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 34.847878] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 34.847879] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 34.847880] [drm:verify_single_dpll_state] PORT PLL A [ 34.847882] [drm:verify_single_dpll_state] PORT PLL B [ 34.847883] [drm:verify_single_dpll_state] PORT PLL C [ 34.847890] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 34.847891] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 34.848738] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 34.848740] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 34.849731] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 34.853025] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 34.853071] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d1800 [ 34.853125] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 34.853126] [drm:intel_enable_pipe] enabling pipe B [ 34.853148] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 34.853150] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 34.853181] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 34.857330] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 34.857335] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 34.857350] [drm:verify_single_dpll_state] PORT PLL B [ 34.861470] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 34.881989] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 34.886127] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 34.886131] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 34.886134] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 34.886145] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B [ 34.886160] [drm:intel_disable_pipe] disabling pipe B [ 34.892024] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 2, on? 1) for crtc 31 [ 34.892032] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 34.892037] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 34.895773] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 34.895777] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 34.895780] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 34.895782] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 34.895783] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 34.895784] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 34.895786] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 34.895787] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 34.895788] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 34.895789] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 34.895791] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 34.895792] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 34.895794] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 34.895795] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 34.895797] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 34.895799] [drm:verify_single_dpll_state] PORT PLL A [ 34.895800] [drm:verify_single_dpll_state] PORT PLL B [ 34.895802] [drm:verify_single_dpll_state] PORT PLL C [ 34.895807] [drm:intel_power_well_disable] disabling dpio-common-bc [ 34.895809] [drm:intel_power_well_disable] disabling power well 2 [ 34.895813] [drm:skl_set_power_well] Disabling power well 2 [ 34.895816] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 34.895818] [drm:intel_power_well_disable] disabling DC off [ 34.895820] [drm:gen9_enable_dc5] Enabling DC5 [ 34.895822] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 34.895824] [drm:intel_power_well_disable] disabling always-on [ 34.897280] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 34.897380] [drm:drm_mode_addfb2] [FB:107] [ 34.900809] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 34.900814] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 34.900821] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 34.900822] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 34.900825] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 34.900827] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 34.900828] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 34.900830] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 34.900831] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802704b2000 for pipe B [ 34.900833] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 34.900833] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 34.900835] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 34.900836] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 34.900838] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 34.900839] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 34.900839] [drm:intel_dump_pipe_config] requested mode: [ 34.900841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 34.900842] [drm:intel_dump_pipe_config] adjusted mode: [ 34.900844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 34.900846] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 34.900847] [drm:intel_dump_pipe_config] port clock: 162000 [ 34.900848] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 34.900849] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 34.900850] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 34.900851] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 34.900852] [drm:intel_dump_pipe_config] ips: 0 [ 34.900853] [drm:intel_dump_pipe_config] double wide: 0 [ 34.900855] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 34.900856] [drm:intel_dump_pipe_config] planes on this crtc [ 34.900857] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 34.900858] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 34.900859] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 34.900860] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 34.900863] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 34.900866] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 34.900868] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL C [ 34.900869] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe B [ 34.900871] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 34.900960] [drm:intel_power_well_enable] enabling always-on [ 34.900961] [drm:intel_power_well_enable] enabling DC off [ 34.901024] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 34.901027] [drm:intel_power_well_enable] enabling power well 2 [ 34.901029] [drm:skl_set_power_well] Enabling power well 2 [ 34.901033] [drm:intel_power_well_enable] enabling dpio-common-bc [ 34.901034] [drm:intel_power_well_enable] enabling dpio-common-a [ 34.902160] [drm:intel_power_well_disable] disabling dpio-common-a [ 34.902167] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 34.904759] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 34.904762] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 34.904765] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 34.904767] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 34.904768] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 34.904769] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 34.904770] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 34.904771] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 34.904772] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 34.904773] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 34.904774] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 34.904775] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 34.904777] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 34.904779] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 34.904780] [drm:verify_single_dpll_state] PORT PLL A [ 34.904781] [drm:verify_single_dpll_state] PORT PLL B [ 34.904783] [drm:verify_single_dpll_state] PORT PLL C [ 34.904790] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 2, on? 0) for crtc 31 [ 34.904791] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 34.906296] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 34.906299] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 34.906649] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 34.906651] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 34.906898] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 34.907436] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 34.907438] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 34.909227] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 34.909271] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b2000 [ 34.909325] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 34.909329] [drm:intel_enable_pipe] enabling pipe B [ 34.909365] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 34.913521] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 34.913526] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 34.913541] [drm:verify_single_dpll_state] PORT PLL C [ 34.917652] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 34.938188] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 34.942321] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 34.942325] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 34.942328] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 34.942342] [drm:intel_disable_pipe] disabling pipe B [ 34.948335] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 2, on? 1) for crtc 31 [ 34.948342] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 34.948347] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 34.951756] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 34.951759] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 34.951762] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 34.951764] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 34.951765] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 34.951766] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 34.951767] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 34.951768] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 34.951769] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 34.951770] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 34.951771] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 34.951773] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 34.951774] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 34.951776] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 34.951777] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 34.951779] [drm:verify_single_dpll_state] PORT PLL A [ 34.951780] [drm:verify_single_dpll_state] PORT PLL B [ 34.951781] [drm:verify_single_dpll_state] PORT PLL C [ 34.951787] [drm:intel_power_well_disable] disabling dpio-common-bc [ 34.951788] [drm:intel_power_well_disable] disabling power well 2 [ 34.951792] [drm:skl_set_power_well] Disabling power well 2 [ 34.951795] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 34.951797] [drm:intel_power_well_disable] disabling DC off [ 34.951799] [drm:gen9_enable_dc5] Enabling DC5 [ 34.951800] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 34.951802] [drm:intel_power_well_disable] disabling always-on [ 34.953097] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 34.953194] [drm:drm_mode_addfb2] [FB:107] [ 34.956340] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 34.956344] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 34.956351] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 34.956353] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 34.956355] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 34.956357] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 34.956358] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 34.956360] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 34.956361] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802704b5800 for pipe B [ 34.956362] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 34.956363] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 34.956365] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 34.956366] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 34.956368] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 34.956369] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 34.956369] [drm:intel_dump_pipe_config] requested mode: [ 34.956371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 34.956372] [drm:intel_dump_pipe_config] adjusted mode: [ 34.956374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 34.956376] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 34.956377] [drm:intel_dump_pipe_config] port clock: 162000 [ 34.956378] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 34.956379] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 34.956380] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 34.956381] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 34.956382] [drm:intel_dump_pipe_config] ips: 0 [ 34.956383] [drm:intel_dump_pipe_config] double wide: 0 [ 34.956385] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 34.956386] [drm:intel_dump_pipe_config] planes on this crtc [ 34.956387] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 34.956388] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 34.956389] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 34.956390] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 34.956393] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 34.956395] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 34.956398] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL C [ 34.956399] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe B [ 34.956400] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 34.956489] [drm:intel_power_well_enable] enabling always-on [ 34.956490] [drm:intel_power_well_enable] enabling DC off [ 34.956553] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 34.956556] [drm:intel_power_well_enable] enabling power well 2 [ 34.956558] [drm:skl_set_power_well] Enabling power well 2 [ 34.956562] [drm:intel_power_well_enable] enabling dpio-common-bc [ 34.956563] [drm:intel_power_well_enable] enabling dpio-common-a [ 34.960673] [drm:intel_power_well_disable] disabling dpio-common-a [ 34.960680] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 34.964811] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 34.964814] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 34.964817] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 34.964819] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 34.964820] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 34.964821] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 34.964822] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 34.964823] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 34.964824] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 34.964825] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 34.964826] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 34.964827] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 34.964829] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 34.964830] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 34.964832] [drm:verify_single_dpll_state] PORT PLL A [ 34.964833] [drm:verify_single_dpll_state] PORT PLL B [ 34.964835] [drm:verify_single_dpll_state] PORT PLL C [ 34.964842] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 2, on? 0) for crtc 31 [ 34.964843] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 34.967421] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 34.967423] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 34.967779] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 34.967781] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 34.968019] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 34.968558] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 34.968560] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 34.971061] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 34.971104] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b5800 [ 34.971159] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 34.971160] [drm:intel_enable_pipe] enabling pipe B [ 34.971198] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 34.975315] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 34.975318] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 34.975332] [drm:verify_single_dpll_state] PORT PLL C [ 34.979472] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf [ 35.000003] [drm:pipe_crc_set_source] stopping CRCs for pipe B [ 35.004135] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 35.004139] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 35.004142] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 35.004157] [drm:intel_disable_pipe] disabling pipe B [ 35.008282] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 2, on? 1) for crtc 31 [ 35.008289] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 35.008294] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 35.012155] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 35.012158] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.012161] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.012163] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.012165] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.012166] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.012167] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.012168] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.012170] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.012171] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.012172] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.012173] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.012175] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.012177] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.012178] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.012180] [drm:verify_single_dpll_state] PORT PLL A [ 35.012182] [drm:verify_single_dpll_state] PORT PLL B [ 35.012183] [drm:verify_single_dpll_state] PORT PLL C [ 35.012188] [drm:intel_power_well_disable] disabling dpio-common-bc [ 35.012190] [drm:intel_power_well_disable] disabling power well 2 [ 35.012194] [drm:skl_set_power_well] Disabling power well 2 [ 35.012198] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 35.012200] [drm:intel_power_well_disable] disabling DC off [ 35.012201] [drm:gen9_enable_dc5] Enabling DC5 [ 35.012203] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 35.012205] [drm:intel_power_well_disable] disabling always-on [ 35.013501] kms_pipe_crc_basic: starting subtest read-crc-pipe-C [ 35.013710] [drm:drm_mode_setcrtc] [CRTC:31:pipe B] [ 35.013809] [drm:drm_mode_addfb2] [FB:107] [ 35.017222] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 35.017227] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 35.017235] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 35.017236] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 35.017238] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.017240] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 35.017243] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 35.017244] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 35.017246] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 35.017248] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802704b1800 for pipe C [ 35.017249] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 35.017250] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 35.017251] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 35.017252] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 35.017254] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 35.017255] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 35.017256] [drm:intel_dump_pipe_config] requested mode: [ 35.017258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 35.017259] [drm:intel_dump_pipe_config] adjusted mode: [ 35.017260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 35.017262] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 35.017263] [drm:intel_dump_pipe_config] port clock: 270000 [ 35.017264] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 35.017265] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 35.017266] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 35.017267] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 35.017268] [drm:intel_dump_pipe_config] ips: 0 [ 35.017269] [drm:intel_dump_pipe_config] double wide: 0 [ 35.017271] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 35.017272] [drm:intel_dump_pipe_config] planes on this crtc [ 35.017273] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled [ 35.017275] [drm:intel_dump_pipe_config] FB:60, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 35.017277] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+0+0 dst 0x0+0+0 [ 35.017278] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 35.017279] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 35.017281] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 35.017283] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.017286] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A [ 35.017287] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C [ 35.017288] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.017377] [drm:intel_power_well_enable] enabling always-on [ 35.017379] [drm:intel_power_well_enable] enabling DC off [ 35.017442] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 35.017445] [drm:intel_power_well_enable] enabling power well 2 [ 35.017447] [drm:skl_set_power_well] Enabling power well 2 [ 35.017451] [drm:intel_power_well_enable] enabling dpio-common-a [ 35.018438] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.018443] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.018447] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.018450] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.018453] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.018457] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.018460] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.018463] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.018465] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.018471] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.018474] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.018477] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.018480] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.018482] [drm:verify_single_dpll_state] PORT PLL A [ 35.018483] [drm:verify_single_dpll_state] PORT PLL B [ 35.018484] [drm:verify_single_dpll_state] PORT PLL C [ 35.018491] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36 [ 35.018492] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 35.018520] [drm:edp_panel_on] Turn eDP port A panel power on [ 35.018522] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 35.018526] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 35.018527] [drm:wait_panel_status] Wait complete [ 35.018528] [drm:wait_panel_on] Wait for panel power on [ 35.018530] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 35.044901] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 35.044904] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 35.044906] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 35.044947] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 35.071559] [drm:wait_panel_status] Wait complete [ 35.071566] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 35.071569] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 35.072303] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 35.072304] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 35.072537] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 35.073063] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 35.073104] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b1800 [ 35.073175] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 35.073177] [drm:intel_enable_pipe] enabling pipe C [ 35.073189] [drm:intel_edp_backlight_on] [ 35.073190] [drm:intel_panel_enable_backlight] pipe C [ 35.073265] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 35.073269] [drm:intel_psr_enable] PSR not supported on this platform [ 35.073270] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 35.077327] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.077331] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 35.077347] [drm:verify_single_dpll_state] PORT PLL A [ 35.081497] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 35.102025] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 35.106163] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 35.106168] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.106170] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.106181] [drm:intel_edp_backlight_off] [ 35.172898] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 35.172908] [drm:intel_disable_pipe] disabling pipe C [ 35.177043] [drm:edp_panel_off] Turn eDP port A panel power off [ 35.177049] [drm:wait_panel_off] Wait for panel power off time [ 35.177052] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 35.189999] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 35.190002] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 35.190004] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 35.190032] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 35.199623] [drm:wait_panel_status] Wait complete [ 35.199630] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36 [ 35.199638] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 35.199642] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.199644] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.199646] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.199647] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.199648] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.199649] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.199650] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.199651] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.199652] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.199654] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.199655] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.199657] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.199658] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.199659] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.199660] [drm:verify_single_dpll_state] PORT PLL A [ 35.199662] [drm:verify_single_dpll_state] PORT PLL B [ 35.199663] [drm:verify_single_dpll_state] PORT PLL C [ 35.199667] [drm:intel_power_well_disable] disabling power well 2 [ 35.199671] [drm:skl_set_power_well] Disabling power well 2 [ 35.199673] [drm:intel_power_well_disable] disabling dpio-common-a [ 35.199676] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 35.199678] [drm:intel_power_well_disable] disabling DC off [ 35.199680] [drm:gen9_enable_dc5] Enabling DC5 [ 35.199681] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 35.199683] [drm:intel_power_well_disable] disabling always-on [ 35.201073] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 35.201174] [drm:drm_mode_addfb2] [FB:107] [ 35.204593] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 35.204598] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 35.204605] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 35.204607] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 35.204609] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.204611] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 35.204615] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 35.204616] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 35.204618] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 35.204620] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802709d3800 for pipe C [ 35.204621] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 35.204622] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 35.204623] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 35.204625] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 35.204627] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 35.204628] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 35.204629] [drm:intel_dump_pipe_config] requested mode: [ 35.204631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 35.204632] [drm:intel_dump_pipe_config] adjusted mode: [ 35.204634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 35.204636] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 35.204637] [drm:intel_dump_pipe_config] port clock: 270000 [ 35.204638] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 35.204639] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 35.204641] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 35.204642] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 35.204643] [drm:intel_dump_pipe_config] ips: 0 [ 35.204644] [drm:intel_dump_pipe_config] double wide: 0 [ 35.204646] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 35.204647] [drm:intel_dump_pipe_config] planes on this crtc [ 35.204648] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 35.204650] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 35.204651] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 35.204653] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 35.204655] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.204658] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A [ 35.204659] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C [ 35.204661] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.204753] [drm:intel_power_well_enable] enabling always-on [ 35.204754] [drm:intel_power_well_enable] enabling DC off [ 35.204817] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 35.204821] [drm:intel_power_well_enable] enabling power well 2 [ 35.204822] [drm:skl_set_power_well] Enabling power well 2 [ 35.204827] [drm:intel_power_well_enable] enabling dpio-common-a [ 35.206159] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.206162] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.206164] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.206166] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.206167] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.206168] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.206169] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.206170] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.206171] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.206173] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.206174] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.206175] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.206176] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.206178] [drm:verify_single_dpll_state] PORT PLL A [ 35.206180] [drm:verify_single_dpll_state] PORT PLL B [ 35.206181] [drm:verify_single_dpll_state] PORT PLL C [ 35.206190] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36 [ 35.206192] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 35.206222] [drm:edp_panel_on] Turn eDP port A panel power on [ 35.206223] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 35.417882] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 35.417885] [drm:wait_panel_status] Wait complete [ 35.417887] [drm:wait_panel_on] Wait for panel power on [ 35.417889] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 00000063 [ 35.444249] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 35.444252] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 35.444254] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 35.444292] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 35.473948] [drm:wait_panel_status] Wait complete [ 35.473955] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 35.473958] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 35.474685] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 35.474686] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 35.474914] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 35.475439] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 35.475480] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d3800 [ 35.475536] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 35.475539] [drm:intel_enable_pipe] enabling pipe C [ 35.475549] [drm:intel_edp_backlight_on] [ 35.475550] [drm:intel_panel_enable_backlight] pipe C [ 35.475552] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 35.475555] [drm:intel_psr_enable] PSR not supported on this platform [ 35.475556] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 35.479687] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.479691] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 35.479707] [drm:verify_single_dpll_state] PORT PLL A [ 35.483833] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 35.504379] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 35.508535] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 35.508539] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.508542] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.508553] [drm:intel_edp_backlight_off] [ 35.583152] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 35.583160] [drm:intel_disable_pipe] disabling pipe C [ 35.587332] [drm:edp_panel_off] Turn eDP port A panel power off [ 35.587337] [drm:wait_panel_off] Wait for panel power off time [ 35.587340] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 35.600866] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 35.600869] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 35.600870] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 35.600880] [drm:wait_panel_status] Wait complete [ 35.600884] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36 [ 35.600891] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 35.600894] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.600896] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.600898] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.600901] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.600904] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.600906] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.600907] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.600908] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.600910] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 35.600911] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.600912] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.600913] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.600914] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.600921] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.600923] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.600924] [drm:verify_single_dpll_state] PORT PLL A [ 35.600925] [drm:verify_single_dpll_state] PORT PLL B [ 35.600927] [drm:verify_single_dpll_state] PORT PLL C [ 35.600931] [drm:intel_power_well_disable] disabling power well 2 [ 35.600934] [drm:skl_set_power_well] Disabling power well 2 [ 35.600937] [drm:intel_power_well_disable] disabling dpio-common-a [ 35.600941] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 35.600942] [drm:intel_power_well_disable] disabling DC off [ 35.600944] [drm:gen9_enable_dc5] Enabling DC5 [ 35.600946] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 35.600948] [drm:intel_power_well_disable] disabling always-on [ 35.602396] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 35.602496] [drm:drm_mode_addfb2] [FB:107] [ 35.605905] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 35.605909] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 35.605918] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 35.605919] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 35.605921] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 35.605924] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 35.605925] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 35.605927] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 35.605929] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802704b4000 for pipe C [ 35.605930] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 35.605931] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 35.605933] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 35.605934] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 35.605936] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 35.605937] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 35.605938] [drm:intel_dump_pipe_config] requested mode: [ 35.605940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 35.605941] [drm:intel_dump_pipe_config] adjusted mode: [ 35.605943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 35.605945] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 35.605946] [drm:intel_dump_pipe_config] port clock: 162000 [ 35.605947] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 35.605948] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 35.605950] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 35.605951] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 35.605952] [drm:intel_dump_pipe_config] ips: 0 [ 35.605953] [drm:intel_dump_pipe_config] double wide: 0 [ 35.605955] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 35.605956] [drm:intel_dump_pipe_config] planes on this crtc [ 35.605958] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 35.605959] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 35.605960] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 35.605963] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 35.605965] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.605968] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B [ 35.605970] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C [ 35.605971] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.606063] [drm:intel_power_well_enable] enabling always-on [ 35.606064] [drm:intel_power_well_enable] enabling DC off [ 35.606127] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 35.606131] [drm:intel_power_well_enable] enabling power well 2 [ 35.606132] [drm:skl_set_power_well] Enabling power well 2 [ 35.606137] [drm:intel_power_well_enable] enabling dpio-common-bc [ 35.606138] [drm:intel_power_well_enable] enabling dpio-common-a [ 35.608668] [drm:intel_power_well_disable] disabling dpio-common-a [ 35.608676] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 35.612809] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 35.612813] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.612816] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.612817] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.612818] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.612819] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.612820] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.612822] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.612823] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.612824] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.612826] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.612827] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.612829] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.612831] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.612832] [drm:verify_single_dpll_state] PORT PLL A [ 35.612834] [drm:verify_single_dpll_state] PORT PLL B [ 35.612835] [drm:verify_single_dpll_state] PORT PLL C [ 35.612843] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36 [ 35.612844] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 35.615804] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 35.615806] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 35.616836] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 35.620159] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 35.620205] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b4000 [ 35.620259] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 35.620260] [drm:intel_enable_pipe] enabling pipe C [ 35.620270] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 35.620272] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD [ 35.624456] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.624461] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 35.624477] [drm:verify_single_dpll_state] PORT PLL B [ 35.628586] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 35.649081] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 35.653260] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 35.653264] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.653267] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.653278] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C [ 35.653293] [drm:intel_disable_pipe] disabling pipe C [ 35.657464] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36 [ 35.657473] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 35.657477] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 35.661170] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 35.661174] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.661177] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.661179] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.661180] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.661181] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.661182] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.661184] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.661185] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.661186] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.661187] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.661189] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.661191] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.661192] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.661194] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.661196] [drm:verify_single_dpll_state] PORT PLL A [ 35.661197] [drm:verify_single_dpll_state] PORT PLL B [ 35.661198] [drm:verify_single_dpll_state] PORT PLL C [ 35.661204] [drm:intel_power_well_disable] disabling dpio-common-bc [ 35.661206] [drm:intel_power_well_disable] disabling power well 2 [ 35.661210] [drm:skl_set_power_well] Disabling power well 2 [ 35.661213] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 35.661215] [drm:intel_power_well_disable] disabling DC off [ 35.661217] [drm:gen9_enable_dc5] Enabling DC5 [ 35.661218] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 35.661220] [drm:intel_power_well_disable] disabling always-on [ 35.662642] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 35.662742] [drm:drm_mode_addfb2] [FB:107] [ 35.666067] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 35.666071] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 35.666079] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 35.666080] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 35.666082] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 35.666085] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 35.666086] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 35.666087] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 35.666089] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802709d4800 for pipe C [ 35.666090] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 35.666091] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 35.666092] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 35.666094] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 35.666095] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 35.666096] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 35.666097] [drm:intel_dump_pipe_config] requested mode: [ 35.666099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 35.666100] [drm:intel_dump_pipe_config] adjusted mode: [ 35.666102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 35.666103] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 35.666104] [drm:intel_dump_pipe_config] port clock: 162000 [ 35.666105] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 35.666106] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 35.666108] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 35.666109] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 35.666110] [drm:intel_dump_pipe_config] ips: 0 [ 35.666110] [drm:intel_dump_pipe_config] double wide: 0 [ 35.666112] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 35.666113] [drm:intel_dump_pipe_config] planes on this crtc [ 35.666115] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 35.666116] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 35.666117] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 35.666119] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 35.666122] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.666124] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B [ 35.666126] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C [ 35.666127] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.666216] [drm:intel_power_well_enable] enabling always-on [ 35.666217] [drm:intel_power_well_enable] enabling DC off [ 35.666280] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 35.666283] [drm:intel_power_well_enable] enabling power well 2 [ 35.666285] [drm:skl_set_power_well] Enabling power well 2 [ 35.666289] [drm:intel_power_well_enable] enabling dpio-common-bc [ 35.666290] [drm:intel_power_well_enable] enabling dpio-common-a [ 35.669811] [drm:intel_power_well_disable] disabling dpio-common-a [ 35.669818] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 35.673945] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 35.673948] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.673951] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.673953] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.673954] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.673955] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.673956] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.673957] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.673958] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.673959] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.673961] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.673962] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.673963] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.673965] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.673966] [drm:verify_single_dpll_state] PORT PLL A [ 35.673968] [drm:verify_single_dpll_state] PORT PLL B [ 35.673969] [drm:verify_single_dpll_state] PORT PLL C [ 35.673976] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36 [ 35.673977] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 35.674728] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 35.674729] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 35.677142] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 35.680453] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 35.680500] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d4800 [ 35.680553] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 35.680555] [drm:intel_enable_pipe] enabling pipe C [ 35.680565] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 35.680567] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD [ 35.684743] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.684748] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 35.684763] [drm:verify_single_dpll_state] PORT PLL B [ 35.688857] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 35.709409] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 35.713546] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 35.713551] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.713554] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.713564] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C [ 35.713579] [drm:intel_disable_pipe] disabling pipe C [ 35.719332] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36 [ 35.719341] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 35.719345] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 35.723443] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 35.723447] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.723450] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.723452] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.723453] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.723454] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.723455] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.723457] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.723458] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.723459] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.723460] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.723462] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.723463] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.723465] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.723467] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.723468] [drm:verify_single_dpll_state] PORT PLL A [ 35.723470] [drm:verify_single_dpll_state] PORT PLL B [ 35.723471] [drm:verify_single_dpll_state] PORT PLL C [ 35.723477] [drm:intel_power_well_disable] disabling dpio-common-bc [ 35.723478] [drm:intel_power_well_disable] disabling power well 2 [ 35.723482] [drm:skl_set_power_well] Disabling power well 2 [ 35.723486] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 35.723487] [drm:intel_power_well_disable] disabling DC off [ 35.723489] [drm:gen9_enable_dc5] Enabling DC5 [ 35.723491] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 35.723493] [drm:intel_power_well_disable] disabling always-on [ 35.724906] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 35.725025] [drm:drm_mode_addfb2] [FB:107] [ 35.728461] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 35.728466] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 35.728474] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 35.728476] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 35.728478] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 35.728481] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 35.728482] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 35.728484] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 35.728486] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802704b7000 for pipe C [ 35.728487] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 35.728488] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 35.728489] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 35.728491] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 35.728493] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 35.728494] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 35.728495] [drm:intel_dump_pipe_config] requested mode: [ 35.728497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 35.728498] [drm:intel_dump_pipe_config] adjusted mode: [ 35.728500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 35.728502] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 35.728503] [drm:intel_dump_pipe_config] port clock: 162000 [ 35.728504] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 35.728505] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 35.728507] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 35.728508] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 35.728509] [drm:intel_dump_pipe_config] ips: 0 [ 35.728510] [drm:intel_dump_pipe_config] double wide: 0 [ 35.728512] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 35.728513] [drm:intel_dump_pipe_config] planes on this crtc [ 35.728514] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 35.728516] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 35.728517] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 35.728520] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 35.728522] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.728525] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C [ 35.728527] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C [ 35.728528] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.728620] [drm:intel_power_well_enable] enabling always-on [ 35.728621] [drm:intel_power_well_enable] enabling DC off [ 35.728685] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 35.728688] [drm:intel_power_well_enable] enabling power well 2 [ 35.728690] [drm:skl_set_power_well] Enabling power well 2 [ 35.728694] [drm:intel_power_well_enable] enabling dpio-common-bc [ 35.728695] [drm:intel_power_well_enable] enabling dpio-common-a [ 35.733287] [drm:intel_power_well_disable] disabling dpio-common-a [ 35.733295] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 35.737321] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 35.737324] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.737326] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.737328] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.737329] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.737330] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.737331] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.737332] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.737333] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.737334] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.737335] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.737336] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.737338] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.737340] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.737341] [drm:verify_single_dpll_state] PORT PLL A [ 35.737342] [drm:verify_single_dpll_state] PORT PLL B [ 35.737344] [drm:verify_single_dpll_state] PORT PLL C [ 35.737352] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36 [ 35.737353] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 35.739235] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 35.739237] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 35.739803] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 35.740343] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 35.740344] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 35.741284] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 35.741327] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b7000 [ 35.741380] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 35.741382] [drm:intel_enable_pipe] enabling pipe C [ 35.745557] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.745562] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 35.745577] [drm:verify_single_dpll_state] PORT PLL C [ 35.749686] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 35.770229] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 35.774364] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 35.774368] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.774371] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.774385] [drm:intel_disable_pipe] disabling pipe C [ 35.778500] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36 [ 35.778508] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 35.778512] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 35.782637] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 35.782641] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.782644] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.782646] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.782647] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.782648] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.782649] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.782651] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.782652] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.782653] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.782654] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.782656] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.782657] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.782659] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.782661] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.782662] [drm:verify_single_dpll_state] PORT PLL A [ 35.782664] [drm:verify_single_dpll_state] PORT PLL B [ 35.782665] [drm:verify_single_dpll_state] PORT PLL C [ 35.782671] [drm:intel_power_well_disable] disabling dpio-common-bc [ 35.782673] [drm:intel_power_well_disable] disabling power well 2 [ 35.782677] [drm:skl_set_power_well] Disabling power well 2 [ 35.782680] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 35.782682] [drm:intel_power_well_disable] disabling DC off [ 35.782684] [drm:gen9_enable_dc5] Enabling DC5 [ 35.782685] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 35.782687] [drm:intel_power_well_disable] disabling always-on [ 35.784120] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 35.784221] [drm:drm_mode_addfb2] [FB:107] [ 35.787644] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 35.787648] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 35.787656] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 35.787658] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 35.787660] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 35.787663] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 35.787664] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 35.787666] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 35.787668] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802709d0800 for pipe C [ 35.787669] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 35.787670] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 35.787671] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 35.787673] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 35.787675] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 35.787676] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 35.787677] [drm:intel_dump_pipe_config] requested mode: [ 35.787679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 35.787680] [drm:intel_dump_pipe_config] adjusted mode: [ 35.787682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 35.787684] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 35.787685] [drm:intel_dump_pipe_config] port clock: 162000 [ 35.787686] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 35.787687] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 35.787689] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 35.787690] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 35.787691] [drm:intel_dump_pipe_config] ips: 0 [ 35.787692] [drm:intel_dump_pipe_config] double wide: 0 [ 35.787694] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 35.787695] [drm:intel_dump_pipe_config] planes on this crtc [ 35.787696] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 35.787698] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 35.787699] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 35.787702] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 35.787704] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.787707] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C [ 35.787709] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C [ 35.787710] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.787802] [drm:intel_power_well_enable] enabling always-on [ 35.787803] [drm:intel_power_well_enable] enabling DC off [ 35.787867] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 35.787870] [drm:intel_power_well_enable] enabling power well 2 [ 35.787872] [drm:skl_set_power_well] Enabling power well 2 [ 35.787876] [drm:intel_power_well_enable] enabling dpio-common-bc [ 35.787877] [drm:intel_power_well_enable] enabling dpio-common-a [ 35.788670] [drm:intel_power_well_disable] disabling dpio-common-a [ 35.788677] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 35.792349] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 35.792352] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.792355] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.792357] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.792359] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.792360] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.792361] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.792362] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.792363] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.792364] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.792365] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.792367] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.792369] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.792370] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.792372] [drm:verify_single_dpll_state] PORT PLL A [ 35.792374] [drm:verify_single_dpll_state] PORT PLL B [ 35.792375] [drm:verify_single_dpll_state] PORT PLL C [ 35.792383] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36 [ 35.792384] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 35.795220] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 35.795224] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 35.795779] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 35.796316] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 35.796317] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 35.798615] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 35.798664] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d0800 [ 35.798717] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 35.798720] [drm:intel_enable_pipe] enabling pipe C [ 35.802875] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.802879] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 35.802893] [drm:verify_single_dpll_state] PORT PLL C [ 35.807011] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 35.827564] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 35.831697] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 35.831701] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.831704] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.831718] [drm:intel_disable_pipe] disabling pipe C [ 35.835846] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36 [ 35.835853] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 35.835858] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 35.839755] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 35.839759] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.839762] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.839764] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.839765] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.839766] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.839768] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.839769] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.839770] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.839772] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.839773] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.839774] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.839776] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.839778] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.839779] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.839781] [drm:verify_single_dpll_state] PORT PLL A [ 35.839782] [drm:verify_single_dpll_state] PORT PLL B [ 35.839784] [drm:verify_single_dpll_state] PORT PLL C [ 35.839789] [drm:intel_power_well_disable] disabling dpio-common-bc [ 35.839791] [drm:intel_power_well_disable] disabling power well 2 [ 35.839795] [drm:skl_set_power_well] Disabling power well 2 [ 35.839799] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 35.839800] [drm:intel_power_well_disable] disabling DC off [ 35.839802] [drm:gen9_enable_dc5] Enabling DC5 [ 35.839804] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 35.839806] [drm:intel_power_well_disable] disabling always-on [ 35.841120] kms_pipe_crc_basic: starting subtest read-crc-pipe-C-frame-sequence [ 35.841335] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 35.841433] [drm:drm_mode_addfb2] [FB:107] [ 35.844819] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 35.844824] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 35.844832] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 35.844833] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 35.844836] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.844838] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 35.844841] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 35.844843] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 35.844844] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 35.844846] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802704b6800 for pipe C [ 35.844848] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 35.844849] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 35.844850] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 35.844852] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 35.844853] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 35.844854] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 35.844855] [drm:intel_dump_pipe_config] requested mode: [ 35.844858] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 35.844859] [drm:intel_dump_pipe_config] adjusted mode: [ 35.844861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 35.844863] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 35.844864] [drm:intel_dump_pipe_config] port clock: 270000 [ 35.844865] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 35.844866] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 35.844867] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 35.844869] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 35.844870] [drm:intel_dump_pipe_config] ips: 0 [ 35.844871] [drm:intel_dump_pipe_config] double wide: 0 [ 35.844873] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 35.844874] [drm:intel_dump_pipe_config] planes on this crtc [ 35.844875] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 35.844876] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 35.844878] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 35.844880] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 35.844882] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.844885] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A [ 35.844886] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C [ 35.844888] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.844980] [drm:intel_power_well_enable] enabling always-on [ 35.844981] [drm:intel_power_well_enable] enabling DC off [ 35.845044] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 35.845048] [drm:intel_power_well_enable] enabling power well 2 [ 35.845049] [drm:skl_set_power_well] Enabling power well 2 [ 35.845054] [drm:intel_power_well_enable] enabling dpio-common-a [ 35.867921] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 35.867924] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 35.867926] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 35.867927] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 35.867928] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 35.867929] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 35.867931] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 35.867932] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 35.867933] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 35.867934] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 35.867935] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 35.867936] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 35.867937] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 35.867938] [drm:verify_single_dpll_state] PORT PLL A [ 35.867940] [drm:verify_single_dpll_state] PORT PLL B [ 35.867941] [drm:verify_single_dpll_state] PORT PLL C [ 35.867948] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36 [ 35.867949] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 35.867979] [drm:edp_panel_on] Turn eDP port A panel power on [ 35.867980] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 35.867984] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 35.867985] [drm:wait_panel_status] Wait complete [ 35.867986] [drm:wait_panel_on] Wait for panel power on [ 35.867988] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 35.897141] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 35.897145] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 35.897146] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 35.897165] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 35.927039] [drm:wait_panel_status] Wait complete [ 35.927046] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 35.927048] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 35.927791] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 35.927793] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 35.928021] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 35.928545] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 35.928586] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b6800 [ 35.928642] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 35.928645] [drm:intel_enable_pipe] enabling pipe C [ 35.928655] [drm:intel_edp_backlight_on] [ 35.928656] [drm:intel_panel_enable_backlight] pipe C [ 35.928658] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 35.928661] [drm:intel_psr_enable] PSR not supported on this platform [ 35.928662] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 35.932794] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 35.932798] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 35.932814] [drm:verify_single_dpll_state] PORT PLL A [ 35.936957] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 35.957493] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 35.961628] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 35.961632] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 35.961635] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 35.961646] [drm:intel_edp_backlight_off] [ 36.020599] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 36.020608] [drm:intel_disable_pipe] disabling pipe C [ 36.023593] [drm:edp_panel_off] Turn eDP port A panel power off [ 36.023600] [drm:wait_panel_off] Wait for panel power off time [ 36.023602] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 36.040528] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 36.040532] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 36.040533] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 36.040541] [drm:wait_panel_status] Wait complete [ 36.040546] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36 [ 36.040549] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 36.040553] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 36.040557] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.040561] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.040565] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.040566] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.040567] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.040568] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.040569] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.040570] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.040571] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.040572] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 36.040573] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.040574] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.040575] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.040576] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.040578] [drm:verify_single_dpll_state] PORT PLL A [ 36.040579] [drm:verify_single_dpll_state] PORT PLL B [ 36.040580] [drm:verify_single_dpll_state] PORT PLL C [ 36.040584] [drm:intel_power_well_disable] disabling power well 2 [ 36.040587] [drm:skl_set_power_well] Disabling power well 2 [ 36.040589] [drm:intel_power_well_disable] disabling dpio-common-a [ 36.040592] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 36.040594] [drm:intel_power_well_disable] disabling DC off [ 36.040595] [drm:gen9_enable_dc5] Enabling DC5 [ 36.040597] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 36.040598] [drm:intel_power_well_disable] disabling always-on [ 36.041901] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.041999] [drm:drm_mode_addfb2] [FB:107] [ 36.045125] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.045129] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 36.045137] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 36.045138] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 36.045140] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.045142] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 36.045145] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 36.045146] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 36.045148] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 36.045149] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802704b4800 for pipe C [ 36.045150] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 36.045151] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 36.045153] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 36.045154] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 36.045156] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 36.045157] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 36.045157] [drm:intel_dump_pipe_config] requested mode: [ 36.045159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 36.045160] [drm:intel_dump_pipe_config] adjusted mode: [ 36.045162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 36.045164] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 36.045165] [drm:intel_dump_pipe_config] port clock: 270000 [ 36.045166] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 36.045167] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 36.045168] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 36.045169] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 36.045170] [drm:intel_dump_pipe_config] ips: 0 [ 36.045171] [drm:intel_dump_pipe_config] double wide: 0 [ 36.045173] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 36.045174] [drm:intel_dump_pipe_config] planes on this crtc [ 36.045175] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 36.045176] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 36.045177] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 36.045179] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 36.045181] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 36.045184] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A [ 36.045185] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C [ 36.045186] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.045275] [drm:intel_power_well_enable] enabling always-on [ 36.045277] [drm:intel_power_well_enable] enabling DC off [ 36.045340] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 36.045343] [drm:intel_power_well_enable] enabling power well 2 [ 36.045344] [drm:skl_set_power_well] Enabling power well 2 [ 36.045348] [drm:intel_power_well_enable] enabling dpio-common-a [ 36.047884] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.047887] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.047889] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.047890] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.047891] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.047892] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.047894] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.047895] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.047896] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.047897] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.047898] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.047899] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.047900] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.047901] [drm:verify_single_dpll_state] PORT PLL A [ 36.047903] [drm:verify_single_dpll_state] PORT PLL B [ 36.047904] [drm:verify_single_dpll_state] PORT PLL C [ 36.047912] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36 [ 36.047913] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 36.047941] [drm:edp_panel_on] Turn eDP port A panel power on [ 36.047943] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 36.151364] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000060 [ 36.182592] [drm:wait_panel_status] Wait complete [ 36.182596] [drm:wait_panel_on] Wait for panel power on [ 36.182598] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 36.212785] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 36.212789] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 36.212790] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 36.212812] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 36.237650] [drm:wait_panel_status] Wait complete [ 36.237657] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 36.237660] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 36.238414] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 36.238416] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 36.238645] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 36.239169] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 36.239210] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b4800 [ 36.239266] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 36.239270] [drm:intel_enable_pipe] enabling pipe C [ 36.239279] [drm:intel_edp_backlight_on] [ 36.239281] [drm:intel_panel_enable_backlight] pipe C [ 36.239282] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 36.239285] [drm:intel_psr_enable] PSR not supported on this platform [ 36.239286] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 36.243418] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 36.243422] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 36.243438] [drm:verify_single_dpll_state] PORT PLL A [ 36.247590] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 36.268119] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 36.272255] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 36.272260] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 36.272262] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.272274] [drm:intel_edp_backlight_off] [ 36.426591] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 36.426601] [drm:intel_disable_pipe] disabling pipe C [ 36.428738] [drm:edp_panel_off] Turn eDP port A panel power off [ 36.428742] [drm:wait_panel_off] Wait for panel power off time [ 36.428745] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 36.442221] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 36.442224] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 36.442226] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 36.442238] [drm:wait_panel_status] Wait complete [ 36.442243] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36 [ 36.442245] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 36.442251] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 36.442257] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.442259] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.442261] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.442262] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.442263] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.442264] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.442265] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.442266] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.442267] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.442268] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 36.442270] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.442271] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.442273] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.442274] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.442275] [drm:verify_single_dpll_state] PORT PLL A [ 36.442276] [drm:verify_single_dpll_state] PORT PLL B [ 36.442278] [drm:verify_single_dpll_state] PORT PLL C [ 36.442282] [drm:intel_power_well_disable] disabling power well 2 [ 36.442285] [drm:skl_set_power_well] Disabling power well 2 [ 36.442290] [drm:intel_power_well_disable] disabling dpio-common-a [ 36.442296] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 36.442300] [drm:intel_power_well_disable] disabling DC off [ 36.442305] [drm:gen9_enable_dc5] Enabling DC5 [ 36.442308] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 36.442310] [drm:intel_power_well_disable] disabling always-on [ 36.443727] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.443827] [drm:drm_mode_addfb2] [FB:107] [ 36.447241] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.447246] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 36.447254] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 36.447255] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 36.447258] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 36.447260] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 36.447261] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 36.447263] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 36.447265] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802704b6800 for pipe C [ 36.447266] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 36.447267] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 36.447269] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 36.447270] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 36.447272] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 36.447273] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 36.447274] [drm:intel_dump_pipe_config] requested mode: [ 36.447276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 36.447277] [drm:intel_dump_pipe_config] adjusted mode: [ 36.447279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 36.447281] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 36.447282] [drm:intel_dump_pipe_config] port clock: 162000 [ 36.447283] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 36.447285] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 36.447286] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 36.447287] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 36.447288] [drm:intel_dump_pipe_config] ips: 0 [ 36.447289] [drm:intel_dump_pipe_config] double wide: 0 [ 36.447291] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 36.447292] [drm:intel_dump_pipe_config] planes on this crtc [ 36.447294] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 36.447295] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 36.447296] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 36.447299] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 36.447301] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 36.447304] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B [ 36.447306] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C [ 36.447307] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.447399] [drm:intel_power_well_enable] enabling always-on [ 36.447401] [drm:intel_power_well_enable] enabling DC off [ 36.447464] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 36.447467] [drm:intel_power_well_enable] enabling power well 2 [ 36.447469] [drm:skl_set_power_well] Enabling power well 2 [ 36.447473] [drm:intel_power_well_enable] enabling dpio-common-bc [ 36.447474] [drm:intel_power_well_enable] enabling dpio-common-a [ 36.506435] [drm:intel_power_well_disable] disabling dpio-common-a [ 36.506442] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 36.510563] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 36.510566] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.510569] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.510571] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.510572] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.510573] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.510574] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.510576] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.510577] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.510578] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.510580] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 36.510581] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.510583] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.510584] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.510586] [drm:verify_single_dpll_state] PORT PLL A [ 36.510588] [drm:verify_single_dpll_state] PORT PLL B [ 36.510589] [drm:verify_single_dpll_state] PORT PLL C [ 36.510598] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36 [ 36.510599] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 36.512165] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 36.512168] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 36.513699] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 36.517108] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 36.517158] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b6800 [ 36.517212] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 36.517215] [drm:intel_enable_pipe] enabling pipe C [ 36.517238] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 36.517239] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD [ 36.521413] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.521418] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 36.521433] [drm:verify_single_dpll_state] PORT PLL B [ 36.525551] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 36.546080] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 36.550217] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 36.550222] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 36.550224] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.550235] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C [ 36.550250] [drm:intel_disable_pipe] disabling pipe C [ 36.555878] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36 [ 36.555887] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 36.555892] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 36.559776] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 36.559779] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.559782] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.559784] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.559786] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.559787] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.559788] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.559790] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.559791] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.559792] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.559793] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 36.559794] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.559796] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.559798] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.559799] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.559801] [drm:verify_single_dpll_state] PORT PLL A [ 36.559803] [drm:verify_single_dpll_state] PORT PLL B [ 36.559804] [drm:verify_single_dpll_state] PORT PLL C [ 36.559809] [drm:intel_power_well_disable] disabling dpio-common-bc [ 36.559811] [drm:intel_power_well_disable] disabling power well 2 [ 36.559815] [drm:skl_set_power_well] Disabling power well 2 [ 36.559819] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 36.559821] [drm:intel_power_well_disable] disabling DC off [ 36.559823] [drm:gen9_enable_dc5] Enabling DC5 [ 36.559824] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 36.559826] [drm:intel_power_well_disable] disabling always-on [ 36.561234] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.561335] [drm:drm_mode_addfb2] [FB:107] [ 36.564656] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.564660] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 36.564668] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 36.564669] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 36.564671] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 36.564674] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 36.564675] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 36.564676] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 36.564678] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802704b5800 for pipe C [ 36.564679] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 36.564680] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 36.564682] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 36.564683] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 36.564684] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 36.564685] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 36.564686] [drm:intel_dump_pipe_config] requested mode: [ 36.564688] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 36.564689] [drm:intel_dump_pipe_config] adjusted mode: [ 36.564691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 36.564693] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 36.564694] [drm:intel_dump_pipe_config] port clock: 162000 [ 36.564694] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 36.564696] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 36.564697] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 36.564698] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 36.564699] [drm:intel_dump_pipe_config] ips: 0 [ 36.564700] [drm:intel_dump_pipe_config] double wide: 0 [ 36.564702] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 36.564703] [drm:intel_dump_pipe_config] planes on this crtc [ 36.564704] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 36.564705] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 36.564706] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 36.564708] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 36.564711] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 36.564714] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B [ 36.564715] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C [ 36.564716] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.564805] [drm:intel_power_well_enable] enabling always-on [ 36.564806] [drm:intel_power_well_enable] enabling DC off [ 36.564869] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 36.564872] [drm:intel_power_well_enable] enabling power well 2 [ 36.564874] [drm:skl_set_power_well] Enabling power well 2 [ 36.564878] [drm:intel_power_well_enable] enabling dpio-common-bc [ 36.564879] [drm:intel_power_well_enable] enabling dpio-common-a [ 36.566790] [drm:intel_power_well_disable] disabling dpio-common-a [ 36.566797] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 36.570902] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 36.570905] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.570908] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.570909] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.570910] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.570911] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.570912] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.570913] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.570914] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.570915] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.570917] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 36.570918] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.570919] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.570921] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.570922] [drm:verify_single_dpll_state] PORT PLL A [ 36.570924] [drm:verify_single_dpll_state] PORT PLL B [ 36.570925] [drm:verify_single_dpll_state] PORT PLL C [ 36.570932] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36 [ 36.570933] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 36.571682] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 36.571683] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 36.572702] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 36.576021] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 36.576071] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b5800 [ 36.576125] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 36.576128] [drm:intel_enable_pipe] enabling pipe C [ 36.576140] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 36.576141] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD [ 36.580310] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.580315] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 36.580330] [drm:verify_single_dpll_state] PORT PLL B [ 36.584447] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 36.604985] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 36.609118] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 36.609123] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 36.609125] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.609139] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C [ 36.609154] [drm:intel_disable_pipe] disabling pipe C [ 36.613886] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36 [ 36.613894] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 36.613899] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 36.618017] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 36.618020] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.618023] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.618025] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.618027] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.618028] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.618029] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.618031] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.618032] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.618033] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.618034] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 36.618035] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.618037] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.618039] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.618040] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.618042] [drm:verify_single_dpll_state] PORT PLL A [ 36.618044] [drm:verify_single_dpll_state] PORT PLL B [ 36.618045] [drm:verify_single_dpll_state] PORT PLL C [ 36.618050] [drm:intel_power_well_disable] disabling dpio-common-bc [ 36.618052] [drm:intel_power_well_disable] disabling power well 2 [ 36.618056] [drm:skl_set_power_well] Disabling power well 2 [ 36.618060] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 36.618061] [drm:intel_power_well_disable] disabling DC off [ 36.618063] [drm:gen9_enable_dc5] Enabling DC5 [ 36.618065] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 36.618067] [drm:intel_power_well_disable] disabling always-on [ 36.619526] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.619626] [drm:drm_mode_addfb2] [FB:107] [ 36.623035] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.623041] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 36.623049] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 36.623050] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 36.623053] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 36.623055] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 36.623056] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 36.623058] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 36.623060] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802704b2800 for pipe C [ 36.623061] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 36.623063] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 36.623064] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 36.623066] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 36.623067] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 36.623068] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 36.623069] [drm:intel_dump_pipe_config] requested mode: [ 36.623071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 36.623073] [drm:intel_dump_pipe_config] adjusted mode: [ 36.623075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 36.623076] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 36.623087] [drm:intel_dump_pipe_config] port clock: 162000 [ 36.623088] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 36.623089] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 36.623091] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 36.623092] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 36.623093] [drm:intel_dump_pipe_config] ips: 0 [ 36.623094] [drm:intel_dump_pipe_config] double wide: 0 [ 36.623096] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 36.623098] [drm:intel_dump_pipe_config] planes on this crtc [ 36.623099] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 36.623100] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 36.623101] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 36.623104] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 36.623107] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 36.623110] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C [ 36.623111] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C [ 36.623113] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.623205] [drm:intel_power_well_enable] enabling always-on [ 36.623206] [drm:intel_power_well_enable] enabling DC off [ 36.623270] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 36.623273] [drm:intel_power_well_enable] enabling power well 2 [ 36.623275] [drm:skl_set_power_well] Enabling power well 2 [ 36.623279] [drm:intel_power_well_enable] enabling dpio-common-bc [ 36.623280] [drm:intel_power_well_enable] enabling dpio-common-a [ 36.626635] [drm:intel_power_well_disable] disabling dpio-common-a [ 36.626643] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 36.630778] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 36.630781] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.630785] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.630786] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.630788] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.630789] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.630790] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.630791] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.630792] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.630793] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.630795] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 36.630796] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.630798] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.630799] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.630801] [drm:verify_single_dpll_state] PORT PLL A [ 36.630803] [drm:verify_single_dpll_state] PORT PLL B [ 36.630804] [drm:verify_single_dpll_state] PORT PLL C [ 36.630813] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36 [ 36.630814] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 36.633658] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 36.633660] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 36.633907] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 36.633908] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 36.634144] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 36.634685] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 36.634687] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 36.636976] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 36.637036] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b2800 [ 36.637092] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 36.637096] [drm:intel_enable_pipe] enabling pipe C [ 36.641269] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.641275] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 36.641290] [drm:verify_single_dpll_state] PORT PLL C [ 36.645400] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 36.665954] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 36.670087] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 36.670091] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 36.670093] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.670107] [drm:intel_disable_pipe] disabling pipe C [ 36.674282] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36 [ 36.674289] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 36.674294] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 36.678196] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 36.678199] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.678202] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.678204] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.678205] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.678206] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.678207] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.678209] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.678210] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.678211] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.678212] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 36.678213] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.678215] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.678216] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.678218] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.678219] [drm:verify_single_dpll_state] PORT PLL A [ 36.678220] [drm:verify_single_dpll_state] PORT PLL B [ 36.678222] [drm:verify_single_dpll_state] PORT PLL C [ 36.678227] [drm:intel_power_well_disable] disabling dpio-common-bc [ 36.678228] [drm:intel_power_well_disable] disabling power well 2 [ 36.678232] [drm:skl_set_power_well] Disabling power well 2 [ 36.678236] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 36.678237] [drm:intel_power_well_disable] disabling DC off [ 36.678239] [drm:gen9_enable_dc5] Enabling DC5 [ 36.678240] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 36.678242] [drm:intel_power_well_disable] disabling always-on [ 36.679553] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.679651] [drm:drm_mode_addfb2] [FB:107] [ 36.682789] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.682794] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 36.682801] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 36.682803] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 36.682805] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 36.682807] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 36.682808] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 36.682810] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 36.682811] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802704b7800 for pipe C [ 36.682813] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 36.682813] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 36.682815] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 36.682816] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 36.682818] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 36.682819] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 36.682819] [drm:intel_dump_pipe_config] requested mode: [ 36.682821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 36.682822] [drm:intel_dump_pipe_config] adjusted mode: [ 36.682824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 36.682826] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 36.682827] [drm:intel_dump_pipe_config] port clock: 162000 [ 36.682828] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 36.682829] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 36.682830] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 36.682831] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 36.682832] [drm:intel_dump_pipe_config] ips: 0 [ 36.682833] [drm:intel_dump_pipe_config] double wide: 0 [ 36.682835] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 36.682836] [drm:intel_dump_pipe_config] planes on this crtc [ 36.682837] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 36.682838] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 36.682839] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 36.682842] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 36.682844] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 36.682847] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C [ 36.682848] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C [ 36.682849] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.682938] [drm:intel_power_well_enable] enabling always-on [ 36.682939] [drm:intel_power_well_enable] enabling DC off [ 36.683002] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 36.683005] [drm:intel_power_well_enable] enabling power well 2 [ 36.683007] [drm:skl_set_power_well] Enabling power well 2 [ 36.683011] [drm:intel_power_well_enable] enabling dpio-common-bc [ 36.683012] [drm:intel_power_well_enable] enabling dpio-common-a [ 36.684930] [drm:intel_power_well_disable] disabling dpio-common-a [ 36.684938] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 36.689064] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 36.689068] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.689071] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.689073] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.689074] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.689075] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.689076] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.689077] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.689078] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.689080] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.689081] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 36.689082] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.689084] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.689086] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.689087] [drm:verify_single_dpll_state] PORT PLL A [ 36.689089] [drm:verify_single_dpll_state] PORT PLL B [ 36.689090] [drm:verify_single_dpll_state] PORT PLL C [ 36.689099] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36 [ 36.689100] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 36.691572] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 36.691575] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 36.691824] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 36.691826] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 36.692065] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 36.692608] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 36.692609] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2 [ 36.694184] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 36.694228] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b7800 [ 36.694284] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 36.694286] [drm:intel_enable_pipe] enabling pipe C [ 36.698463] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.698468] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 36.698482] [drm:verify_single_dpll_state] PORT PLL C [ 36.702603] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 36.723130] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 36.727282] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 36.727287] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 36.727289] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.727304] [drm:intel_disable_pipe] disabling pipe C [ 36.731443] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36 [ 36.731451] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 36.731456] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 36.735352] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 36.735356] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.735359] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.735361] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.735362] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.735363] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.735364] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.735366] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.735367] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.735368] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.735370] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 36.735371] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.735373] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.735374] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.735376] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.735378] [drm:verify_single_dpll_state] PORT PLL A [ 36.735379] [drm:verify_single_dpll_state] PORT PLL B [ 36.735381] [drm:verify_single_dpll_state] PORT PLL C [ 36.735386] [drm:intel_power_well_disable] disabling dpio-common-bc [ 36.735388] [drm:intel_power_well_disable] disabling power well 2 [ 36.735392] [drm:skl_set_power_well] Disabling power well 2 [ 36.735395] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 36.735397] [drm:intel_power_well_disable] disabling DC off [ 36.735399] [drm:gen9_enable_dc5] Enabling DC5 [ 36.735400] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 36.735402] [drm:intel_power_well_disable] disabling always-on [ 36.736677] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C [ 36.736860] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.736958] [drm:drm_mode_addfb2] [FB:107] [ 36.740395] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.740400] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 36.740408] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 36.740409] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 36.740412] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.740413] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 36.740417] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 36.740418] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 36.740420] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 36.740422] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802709d5000 for pipe C [ 36.740423] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 36.740424] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 36.740426] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 36.740427] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 36.740429] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 36.740430] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 36.740431] [drm:intel_dump_pipe_config] requested mode: [ 36.740433] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 36.740434] [drm:intel_dump_pipe_config] adjusted mode: [ 36.740436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 36.740438] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 36.740439] [drm:intel_dump_pipe_config] port clock: 270000 [ 36.740440] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 36.740441] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 36.740443] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 36.740444] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 36.740445] [drm:intel_dump_pipe_config] ips: 0 [ 36.740446] [drm:intel_dump_pipe_config] double wide: 0 [ 36.740448] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 36.740449] [drm:intel_dump_pipe_config] planes on this crtc [ 36.740450] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 36.740452] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 36.740453] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 36.740455] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 36.740457] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 36.740460] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A [ 36.740461] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C [ 36.740463] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.740555] [drm:intel_power_well_enable] enabling always-on [ 36.740556] [drm:intel_power_well_enable] enabling DC off [ 36.740619] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 36.740623] [drm:intel_power_well_enable] enabling power well 2 [ 36.740624] [drm:skl_set_power_well] Enabling power well 2 [ 36.740629] [drm:intel_power_well_enable] enabling dpio-common-a [ 36.741933] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.741936] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.741938] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.741939] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.741940] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.741941] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.741942] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.741943] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.741944] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.741945] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.741946] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.741947] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.741948] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.741949] [drm:verify_single_dpll_state] PORT PLL A [ 36.741951] [drm:verify_single_dpll_state] PORT PLL B [ 36.741952] [drm:verify_single_dpll_state] PORT PLL C [ 36.741958] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36 [ 36.741959] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 36.741981] [drm:edp_panel_on] Turn eDP port A panel power on [ 36.741983] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 36.741986] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 36.741987] [drm:wait_panel_status] Wait complete [ 36.741988] [drm:wait_panel_on] Wait for panel power on [ 36.741990] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 36.769976] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 36.769978] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 36.769980] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 36.769999] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 36.810484] [drm:wait_panel_status] Wait complete [ 36.810491] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 36.810493] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 36.811217] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 36.811219] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 36.811444] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 36.811967] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 36.812007] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d5000 [ 36.812060] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 36.812063] [drm:intel_enable_pipe] enabling pipe C [ 36.812079] [drm:intel_edp_backlight_on] [ 36.812080] [drm:intel_panel_enable_backlight] pipe C [ 36.812082] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 36.812084] [drm:intel_psr_enable] PSR not supported on this platform [ 36.812085] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 36.816222] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 36.816226] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 36.816241] [drm:verify_single_dpll_state] PORT PLL A [ 36.820373] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 36.840937] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 36.845041] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 36.845045] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 36.845047] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.845059] [drm:intel_edp_backlight_off] [ 36.930753] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 36.930763] [drm:intel_disable_pipe] disabling pipe C [ 36.932850] [drm:edp_panel_off] Turn eDP port A panel power off [ 36.932855] [drm:wait_panel_off] Wait for panel power off time [ 36.932858] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 36.945800] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 36.945804] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 36.945805] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 36.945826] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 36.957399] [drm:wait_panel_status] Wait complete [ 36.957405] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36 [ 36.957412] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 36.957416] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.957418] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.957419] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.957420] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.957421] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.957422] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.957423] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.957424] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.957425] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.957426] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 36.957428] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.957429] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.957430] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.957431] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.957432] [drm:verify_single_dpll_state] PORT PLL A [ 36.957434] [drm:verify_single_dpll_state] PORT PLL B [ 36.957435] [drm:verify_single_dpll_state] PORT PLL C [ 36.957439] [drm:intel_power_well_disable] disabling power well 2 [ 36.957443] [drm:skl_set_power_well] Disabling power well 2 [ 36.957444] [drm:intel_power_well_disable] disabling dpio-common-a [ 36.957447] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 36.957449] [drm:intel_power_well_disable] disabling DC off [ 36.957451] [drm:gen9_enable_dc5] Enabling DC5 [ 36.957452] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 36.957454] [drm:intel_power_well_disable] disabling always-on [ 36.958778] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.958876] [drm:drm_mode_addfb2] [FB:107] [ 36.962019] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 36.962024] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 36.962031] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 36.962033] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 36.962035] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.962037] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 36.962040] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 36.962041] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 36.962042] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 36.962044] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88007798d000 for pipe C [ 36.962045] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 36.962046] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 36.962048] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 36.962049] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 36.962050] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 36.962051] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 36.962052] [drm:intel_dump_pipe_config] requested mode: [ 36.962054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 36.962055] [drm:intel_dump_pipe_config] adjusted mode: [ 36.962057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 36.962059] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 36.962060] [drm:intel_dump_pipe_config] port clock: 270000 [ 36.962061] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 36.962062] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 36.962063] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 36.962064] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 36.962065] [drm:intel_dump_pipe_config] ips: 0 [ 36.962066] [drm:intel_dump_pipe_config] double wide: 0 [ 36.962068] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 36.962069] [drm:intel_dump_pipe_config] planes on this crtc [ 36.962070] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 36.962071] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 36.962072] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 36.962074] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 36.962076] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 36.962079] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A [ 36.962080] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C [ 36.962081] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 36.962170] [drm:intel_power_well_enable] enabling always-on [ 36.962171] [drm:intel_power_well_enable] enabling DC off [ 36.962234] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 36.962238] [drm:intel_power_well_enable] enabling power well 2 [ 36.962239] [drm:skl_set_power_well] Enabling power well 2 [ 36.962243] [drm:intel_power_well_enable] enabling dpio-common-a [ 36.964713] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 36.964717] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 36.964719] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 36.964720] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 36.964721] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 36.964722] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 36.964723] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 36.964724] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 36.964725] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 36.964726] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 36.964727] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 36.964728] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 36.964729] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 36.964730] [drm:verify_single_dpll_state] PORT PLL A [ 36.964732] [drm:verify_single_dpll_state] PORT PLL B [ 36.964733] [drm:verify_single_dpll_state] PORT PLL C [ 36.964740] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36 [ 36.964741] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 36.964771] [drm:edp_panel_on] Turn eDP port A panel power on [ 36.964772] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 37.132567] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 37.132570] [drm:wait_panel_status] Wait complete [ 37.132571] [drm:wait_panel_on] Wait for panel power on [ 37.132573] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 37.159720] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 37.159724] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 37.159725] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 37.159747] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 37.194098] [drm:wait_panel_status] Wait complete [ 37.194105] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 37.194107] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 37.194845] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 37.194847] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 37.195082] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 37.195609] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 37.195653] [drm:skylake_pfit_enable] for crtc_state = ffff88007798d000 [ 37.195708] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 37.195710] [drm:intel_enable_pipe] enabling pipe C [ 37.195718] [drm:intel_edp_backlight_on] [ 37.195720] [drm:intel_panel_enable_backlight] pipe C [ 37.195721] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 37.195724] [drm:intel_psr_enable] PSR not supported on this platform [ 37.195725] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 37.199861] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 37.199865] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 37.199881] [drm:verify_single_dpll_state] PORT PLL A [ 37.204027] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 37.224621] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 37.228728] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 37.228733] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 37.228735] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 37.228747] [drm:intel_edp_backlight_off] [ 37.335220] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 37.335230] [drm:intel_disable_pipe] disabling pipe C [ 37.337360] [drm:edp_panel_off] Turn eDP port A panel power off [ 37.337364] [drm:wait_panel_off] Wait for panel power off time [ 37.337366] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 37.352394] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 37.352397] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 37.352399] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 37.352411] [drm:wait_panel_status] Wait complete [ 37.352418] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36 [ 37.352420] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 37.352425] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 37.352430] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 37.352435] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 37.352437] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 37.352438] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 37.352439] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 37.352440] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 37.352441] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 37.352442] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 37.352443] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 37.352444] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 37.352446] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 37.352448] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 37.352449] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 37.352450] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 37.352452] [drm:verify_single_dpll_state] PORT PLL A [ 37.352453] [drm:verify_single_dpll_state] PORT PLL B [ 37.352454] [drm:verify_single_dpll_state] PORT PLL C [ 37.352459] [drm:intel_power_well_disable] disabling power well 2 [ 37.352462] [drm:skl_set_power_well] Disabling power well 2 [ 37.352465] [drm:intel_power_well_disable] disabling dpio-common-a [ 37.352469] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 37.352471] [drm:intel_power_well_disable] disabling DC off [ 37.352475] [drm:gen9_enable_dc5] Enabling DC5 [ 37.352479] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 37.352485] [drm:intel_power_well_disable] disabling always-on [ 37.353911] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 37.354011] [drm:drm_mode_addfb2] [FB:107] [ 37.357404] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 37.357409] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 37.357417] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 37.357418] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 37.357421] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 37.357423] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 37.357424] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 37.357426] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 37.357428] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88026e44b000 for pipe C [ 37.357429] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 37.357430] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 37.357432] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 37.357434] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 37.357435] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 37.357436] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 37.357437] [drm:intel_dump_pipe_config] requested mode: [ 37.357439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 37.357440] [drm:intel_dump_pipe_config] adjusted mode: [ 37.357442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 37.357444] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 37.357445] [drm:intel_dump_pipe_config] port clock: 162000 [ 37.357446] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 37.357448] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 37.357449] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 37.357450] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 37.357451] [drm:intel_dump_pipe_config] ips: 0 [ 37.357452] [drm:intel_dump_pipe_config] double wide: 0 [ 37.357454] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 37.357456] [drm:intel_dump_pipe_config] planes on this crtc [ 37.357457] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 37.357458] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 37.357459] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 37.357462] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 37.357465] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 37.357468] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B [ 37.357469] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C [ 37.357471] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 37.357563] [drm:intel_power_well_enable] enabling always-on [ 37.357564] [drm:intel_power_well_enable] enabling DC off [ 37.357627] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 37.357630] [drm:intel_power_well_enable] enabling power well 2 [ 37.357632] [drm:skl_set_power_well] Enabling power well 2 [ 37.357636] [drm:intel_power_well_enable] enabling dpio-common-bc [ 37.357638] [drm:intel_power_well_enable] enabling dpio-common-a [ 37.443917] [drm:intel_power_well_disable] disabling dpio-common-a [ 37.443922] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 37.447333] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 37.447336] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 37.447338] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 37.447339] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 37.447340] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 37.447341] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 37.447342] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 37.447343] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 37.447344] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 37.447345] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 37.447346] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 37.447347] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 37.447348] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 37.447349] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 37.447351] [drm:verify_single_dpll_state] PORT PLL A [ 37.447352] [drm:verify_single_dpll_state] PORT PLL B [ 37.447353] [drm:verify_single_dpll_state] PORT PLL C [ 37.447363] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36 [ 37.447363] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 37.450925] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 37.450927] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 37.451991] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 37.455010] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 37.455057] [drm:skylake_pfit_enable] for crtc_state = ffff88026e44b000 [ 37.455113] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 37.455115] [drm:intel_enable_pipe] enabling pipe C [ 37.455129] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 37.455131] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD [ 37.459265] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 37.459270] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 37.459286] [drm:verify_single_dpll_state] PORT PLL B [ 37.463456] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 37.484010] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 37.488119] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 37.488123] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 37.488126] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 37.488136] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C [ 37.488152] [drm:intel_disable_pipe] disabling pipe C [ 37.494153] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36 [ 37.494162] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 37.494166] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 37.497766] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 37.497769] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 37.497772] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 37.497774] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 37.497775] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 37.497777] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 37.497778] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 37.497779] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 37.497780] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 37.497782] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 37.497783] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 37.497784] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 37.497786] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 37.497788] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 37.497789] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 37.497791] [drm:verify_single_dpll_state] PORT PLL A [ 37.497792] [drm:verify_single_dpll_state] PORT PLL B [ 37.497794] [drm:verify_single_dpll_state] PORT PLL C [ 37.497799] [drm:intel_power_well_disable] disabling dpio-common-bc [ 37.497801] [drm:intel_power_well_disable] disabling power well 2 [ 37.497805] [drm:skl_set_power_well] Disabling power well 2 [ 37.497809] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 37.497810] [drm:intel_power_well_disable] disabling DC off [ 37.497812] [drm:gen9_enable_dc5] Enabling DC5 [ 37.497814] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 37.497816] [drm:intel_power_well_disable] disabling always-on [ 37.499216] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 37.499318] [drm:drm_mode_addfb2] [FB:107] [ 37.502762] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 37.502767] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 37.502776] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 37.502777] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 37.502780] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 37.502782] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 37.502784] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 37.502785] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 37.502787] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802709d3800 for pipe C [ 37.502789] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 37.502790] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 37.502791] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 37.502793] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 37.502794] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 37.502795] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 37.502796] [drm:intel_dump_pipe_config] requested mode: [ 37.502798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 37.502800] [drm:intel_dump_pipe_config] adjusted mode: [ 37.502802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 37.502803] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 37.502805] [drm:intel_dump_pipe_config] port clock: 162000 [ 37.502806] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 37.502807] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 37.502808] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 37.502810] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 37.502811] [drm:intel_dump_pipe_config] ips: 0 [ 37.502812] [drm:intel_dump_pipe_config] double wide: 0 [ 37.502814] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 37.502815] [drm:intel_dump_pipe_config] planes on this crtc [ 37.502816] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 37.502817] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 37.502819] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 37.502821] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 37.502824] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 37.502827] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B [ 37.502828] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C [ 37.502830] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 37.502922] [drm:intel_power_well_enable] enabling always-on [ 37.502923] [drm:intel_power_well_enable] enabling DC off [ 37.502986] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 37.502990] [drm:intel_power_well_enable] enabling power well 2 [ 37.502991] [drm:skl_set_power_well] Enabling power well 2 [ 37.502996] [drm:intel_power_well_enable] enabling dpio-common-bc [ 37.502997] [drm:intel_power_well_enable] enabling dpio-common-a [ 37.506654] [drm:intel_power_well_disable] disabling dpio-common-a [ 37.506662] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 37.510790] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 37.510794] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 37.510797] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 37.510798] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 37.510799] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 37.510801] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 37.510802] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 37.510804] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 37.510805] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 37.510806] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 37.510807] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 37.510808] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 37.510810] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 37.510812] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 37.510813] [drm:verify_single_dpll_state] PORT PLL A [ 37.510815] [drm:verify_single_dpll_state] PORT PLL B [ 37.510816] [drm:verify_single_dpll_state] PORT PLL C [ 37.510824] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36 [ 37.510825] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 37.511588] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 37.511589] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 37.513234] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 37.516562] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 37.516611] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d3800 [ 37.516667] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 37.516669] [drm:intel_enable_pipe] enabling pipe C [ 37.516677] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 37.516678] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD [ 37.520864] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 37.520870] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 37.520886] [drm:verify_single_dpll_state] PORT PLL B [ 37.525008] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 37.545553] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 37.549668] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 37.549673] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 37.549675] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 37.549685] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C [ 37.549702] [drm:intel_disable_pipe] disabling pipe C [ 37.554339] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36 [ 37.554347] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 37.554352] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 37.557886] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 37.557890] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 37.557893] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 37.557895] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 37.557896] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 37.557897] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 37.557898] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 37.557900] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 37.557901] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 37.557902] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 37.557903] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 37.557905] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 37.557906] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 37.557908] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 37.557910] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 37.557911] [drm:verify_single_dpll_state] PORT PLL A [ 37.557913] [drm:verify_single_dpll_state] PORT PLL B [ 37.557914] [drm:verify_single_dpll_state] PORT PLL C [ 37.557920] [drm:intel_power_well_disable] disabling dpio-common-bc [ 37.557922] [drm:intel_power_well_disable] disabling power well 2 [ 37.557926] [drm:skl_set_power_well] Disabling power well 2 [ 37.557929] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 37.557931] [drm:intel_power_well_disable] disabling DC off [ 37.557933] [drm:gen9_enable_dc5] Enabling DC5 [ 37.557934] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 37.557936] [drm:intel_power_well_disable] disabling always-on [ 37.559400] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 37.559500] [drm:drm_mode_addfb2] [FB:107] [ 37.562921] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 37.562926] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 37.562934] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 37.562935] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 37.562938] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 37.562940] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 37.562942] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 37.562943] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 37.562945] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802704b7800 for pipe C [ 37.562946] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 37.562948] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 37.562949] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 37.562951] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 37.562952] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 37.562953] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 37.562954] [drm:intel_dump_pipe_config] requested mode: [ 37.562957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 37.562958] [drm:intel_dump_pipe_config] adjusted mode: [ 37.562960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 37.562961] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 37.562963] [drm:intel_dump_pipe_config] port clock: 162000 [ 37.562964] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 37.562965] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 37.562966] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 37.562968] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 37.562969] [drm:intel_dump_pipe_config] ips: 0 [ 37.562970] [drm:intel_dump_pipe_config] double wide: 0 [ 37.562972] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 37.562973] [drm:intel_dump_pipe_config] planes on this crtc [ 37.562974] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 37.562975] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 37.562977] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 37.562980] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 37.562982] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 37.562985] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C [ 37.562987] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C [ 37.562988] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 37.563080] [drm:intel_power_well_enable] enabling always-on [ 37.563081] [drm:intel_power_well_enable] enabling DC off [ 37.563144] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 37.563148] [drm:intel_power_well_enable] enabling power well 2 [ 37.563149] [drm:skl_set_power_well] Enabling power well 2 [ 37.563154] [drm:intel_power_well_enable] enabling dpio-common-bc [ 37.563155] [drm:intel_power_well_enable] enabling dpio-common-a [ 37.565658] [drm:intel_power_well_disable] disabling dpio-common-a [ 37.565666] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 37.569787] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 37.569791] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 37.569794] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 37.569796] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 37.569797] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 37.569798] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 37.569799] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 37.569801] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 37.569802] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 37.569803] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 37.569804] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 37.569805] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 37.569807] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 37.569809] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 37.569811] [drm:verify_single_dpll_state] PORT PLL A [ 37.569812] [drm:verify_single_dpll_state] PORT PLL B [ 37.569813] [drm:verify_single_dpll_state] PORT PLL C [ 37.569821] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36 [ 37.569822] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 37.572718] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 37.572721] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 37.573275] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 37.573815] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 37.573816] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 37.575888] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 37.575943] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b7800 [ 37.575999] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 37.576002] [drm:intel_enable_pipe] enabling pipe C [ 37.580155] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 37.580160] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 37.580174] [drm:verify_single_dpll_state] PORT PLL C [ 37.584333] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 37.604870] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 37.608997] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 37.609002] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 37.609005] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 37.609019] [drm:intel_disable_pipe] disabling pipe C [ 37.613292] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36 [ 37.613300] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 37.613304] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 37.617357] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 37.617360] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 37.617363] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 37.617365] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 37.617366] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 37.617368] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 37.617369] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 37.617370] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 37.617371] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 37.617372] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 37.617374] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 37.617375] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 37.617377] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 37.617378] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 37.617380] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 37.617382] [drm:verify_single_dpll_state] PORT PLL A [ 37.617383] [drm:verify_single_dpll_state] PORT PLL B [ 37.617384] [drm:verify_single_dpll_state] PORT PLL C [ 37.617390] [drm:intel_power_well_disable] disabling dpio-common-bc [ 37.617391] [drm:intel_power_well_disable] disabling power well 2 [ 37.617395] [drm:skl_set_power_well] Disabling power well 2 [ 37.617399] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 37.617400] [drm:intel_power_well_disable] disabling DC off [ 37.617402] [drm:gen9_enable_dc5] Enabling DC5 [ 37.617404] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 37.617406] [drm:intel_power_well_disable] disabling always-on [ 37.618783] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 37.618884] [drm:drm_mode_addfb2] [FB:107] [ 37.622322] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 37.622326] [drm:drm_mode_setcrtc] [CONNECTOR:54:DP-2] [ 37.622335] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 37.622336] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 37.622338] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 37.622341] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 37.622342] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 37.622344] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 37.622346] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802704b2800 for pipe C [ 37.622347] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 37.622348] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 37.622350] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 37.622352] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 37.622353] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 37.622354] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 37.622355] [drm:intel_dump_pipe_config] requested mode: [ 37.622357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 37.622358] [drm:intel_dump_pipe_config] adjusted mode: [ 37.622360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 37.622362] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 37.622363] [drm:intel_dump_pipe_config] port clock: 162000 [ 37.622364] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 37.622366] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 37.622367] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 37.622368] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 37.622369] [drm:intel_dump_pipe_config] ips: 0 [ 37.622370] [drm:intel_dump_pipe_config] double wide: 0 [ 37.622372] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 37.622374] [drm:intel_dump_pipe_config] planes on this crtc [ 37.622375] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 37.622376] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 37.622377] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 37.622380] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 37.622383] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 37.622385] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C [ 37.622387] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C [ 37.622388] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 37.622480] [drm:intel_power_well_enable] enabling always-on [ 37.622481] [drm:intel_power_well_enable] enabling DC off [ 37.622544] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 37.622548] [drm:intel_power_well_enable] enabling power well 2 [ 37.622549] [drm:skl_set_power_well] Enabling power well 2 [ 37.622554] [drm:intel_power_well_enable] enabling dpio-common-bc [ 37.622555] [drm:intel_power_well_enable] enabling dpio-common-a [ 37.626003] [drm:intel_power_well_disable] disabling dpio-common-a [ 37.626010] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 37.630166] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 37.630169] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 37.630172] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 37.630174] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 37.630175] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 37.630176] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 37.630177] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 37.630178] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 37.630179] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 37.630179] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 37.630180] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 37.630182] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 37.630183] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 37.630184] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 37.630186] [drm:verify_single_dpll_state] PORT PLL A [ 37.630187] [drm:verify_single_dpll_state] PORT PLL B [ 37.630188] [drm:verify_single_dpll_state] PORT PLL C [ 37.630195] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36 [ 37.630196] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 37.632366] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 37.632368] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 37.633021] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 37.633563] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 37.633565] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 37.636094] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 37.636137] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b2800 [ 37.636187] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 37.636190] [drm:intel_enable_pipe] enabling pipe C [ 37.640366] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 37.640371] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 37.640385] [drm:verify_single_dpll_state] PORT PLL C [ 37.644498] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 37.665093] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 37.669208] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 37.669212] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 37.669214] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 37.669227] [drm:intel_disable_pipe] disabling pipe C [ 37.673404] [drm:intel_disable_shared_dpll] disable PORT PLL C (active 4, on? 1) for crtc 36 [ 37.673412] [drm:intel_disable_shared_dpll] disabling PORT PLL C [ 37.673416] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 37.677521] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 37.677525] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 37.677528] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 37.677530] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 37.677531] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 37.677532] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 37.677534] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 37.677535] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 37.677536] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 37.677537] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 37.677539] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 37.677540] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 37.677542] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 37.677543] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 37.677545] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 37.677547] [drm:verify_single_dpll_state] PORT PLL A [ 37.677548] [drm:verify_single_dpll_state] PORT PLL B [ 37.677550] [drm:verify_single_dpll_state] PORT PLL C [ 37.677555] [drm:intel_power_well_disable] disabling dpio-common-bc [ 37.677557] [drm:intel_power_well_disable] disabling power well 2 [ 37.677561] [drm:skl_set_power_well] Disabling power well 2 [ 37.677565] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 37.677566] [drm:intel_power_well_disable] disabling DC off [ 37.677568] [drm:gen9_enable_dc5] Enabling DC5 [ 37.677570] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 37.677572] [drm:intel_power_well_disable] disabling always-on [ 37.678877] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C-frame-sequence [ 37.679057] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 37.679155] [drm:drm_mode_addfb2] [FB:107] [ 37.682559] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 37.682564] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 37.682572] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 37.682573] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 37.682576] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 37.682578] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 37.682581] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 37.682582] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 37.682584] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 37.682586] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88007798f000 for pipe C [ 37.682587] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 37.682588] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 37.682590] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 37.682592] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 37.682593] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 37.682594] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 37.682595] [drm:intel_dump_pipe_config] requested mode: [ 37.682597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 37.682598] [drm:intel_dump_pipe_config] adjusted mode: [ 37.682600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 37.682602] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 37.682603] [drm:intel_dump_pipe_config] port clock: 270000 [ 37.682604] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 37.682606] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 37.682607] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 37.682608] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 37.682609] [drm:intel_dump_pipe_config] ips: 0 [ 37.682610] [drm:intel_dump_pipe_config] double wide: 0 [ 37.682612] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 37.682614] [drm:intel_dump_pipe_config] planes on this crtc [ 37.682615] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 37.682616] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 37.682617] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 37.682619] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 37.682622] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 37.682624] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A [ 37.682626] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C [ 37.682627] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 37.682719] [drm:intel_power_well_enable] enabling always-on [ 37.682720] [drm:intel_power_well_enable] enabling DC off [ 37.682783] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 37.682787] [drm:intel_power_well_enable] enabling power well 2 [ 37.682789] [drm:skl_set_power_well] Enabling power well 2 [ 37.682793] [drm:intel_power_well_enable] enabling dpio-common-a [ 37.685009] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 37.685012] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 37.685014] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 37.685015] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 37.685016] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 37.685017] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 37.685019] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 37.685020] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 37.685020] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 37.685022] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 37.685023] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 37.685024] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 37.685025] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 37.685026] [drm:verify_single_dpll_state] PORT PLL A [ 37.685028] [drm:verify_single_dpll_state] PORT PLL B [ 37.685029] [drm:verify_single_dpll_state] PORT PLL C [ 37.685036] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36 [ 37.685037] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 37.685066] [drm:edp_panel_on] Turn eDP port A panel power on [ 37.685067] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 37.685071] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 37.685072] [drm:wait_panel_status] Wait complete [ 37.685073] [drm:wait_panel_on] Wait for panel power on [ 37.685075] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 37.714025] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 37.714029] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 37.714030] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 37.714064] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 37.748771] [drm:wait_panel_status] Wait complete [ 37.748778] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 37.748780] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 37.749548] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 37.749551] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 37.749784] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 37.750316] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 37.750358] [drm:skylake_pfit_enable] for crtc_state = ffff88007798f000 [ 37.750414] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 37.750417] [drm:intel_enable_pipe] enabling pipe C [ 37.750427] [drm:intel_edp_backlight_on] [ 37.750428] [drm:intel_panel_enable_backlight] pipe C [ 37.750430] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 37.750432] [drm:intel_psr_enable] PSR not supported on this platform [ 37.750434] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 37.754566] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 37.754570] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 37.754586] [drm:verify_single_dpll_state] PORT PLL A [ 37.758708] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 37.779288] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 37.783403] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 37.783407] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 37.783410] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 37.783421] [drm:intel_edp_backlight_off] [ 37.970500] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 37.970510] [drm:intel_disable_pipe] disabling pipe C [ 37.973424] [drm:edp_panel_off] Turn eDP port A panel power off [ 37.973428] [drm:wait_panel_off] Wait for panel power off time [ 37.973430] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 37.986373] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 37.986376] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 37.986377] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 37.986411] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 38.000464] [drm:wait_panel_status] Wait complete [ 38.000470] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36 [ 38.000476] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 38.000480] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 38.000482] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 38.000483] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 38.000484] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 38.000485] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 38.000486] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 38.000487] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 38.000487] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 38.000488] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 38.000489] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 38.000491] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 38.000492] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 38.000493] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 38.000494] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 38.000495] [drm:verify_single_dpll_state] PORT PLL A [ 38.000496] [drm:verify_single_dpll_state] PORT PLL B [ 38.000497] [drm:verify_single_dpll_state] PORT PLL C [ 38.000501] [drm:intel_power_well_disable] disabling power well 2 [ 38.000504] [drm:skl_set_power_well] Disabling power well 2 [ 38.000506] [drm:intel_power_well_disable] disabling dpio-common-a [ 38.000509] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 38.000510] [drm:intel_power_well_disable] disabling DC off [ 38.000512] [drm:gen9_enable_dc5] Enabling DC5 [ 38.000513] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 38.000515] [drm:intel_power_well_disable] disabling always-on [ 38.001744] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 38.001840] [drm:drm_mode_addfb2] [FB:107] [ 38.004751] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 38.004755] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1] [ 38.004762] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 38.004763] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 38.004765] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 38.004766] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 38.004769] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 38.004770] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 38.004772] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 38.004773] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802704b1800 for pipe C [ 38.004774] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 38.004775] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 38.004776] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 38.004778] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 38.004779] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 38.004780] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 38.004780] [drm:intel_dump_pipe_config] requested mode: [ 38.004782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 38.004783] [drm:intel_dump_pipe_config] adjusted mode: [ 38.004785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 38.004786] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 38.004787] [drm:intel_dump_pipe_config] port clock: 270000 [ 38.004788] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 38.004789] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 38.004790] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 38.004791] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 38.004792] [drm:intel_dump_pipe_config] ips: 0 [ 38.004793] [drm:intel_dump_pipe_config] double wide: 0 [ 38.004794] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 38.004795] [drm:intel_dump_pipe_config] planes on this crtc [ 38.004796] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 38.004797] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 38.004798] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 38.004800] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 38.004802] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 38.004804] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL A [ 38.004805] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe C [ 38.004807] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 38.004892] [drm:intel_power_well_enable] enabling always-on [ 38.004893] [drm:intel_power_well_enable] enabling DC off [ 38.004956] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 38.004959] [drm:intel_power_well_enable] enabling power well 2 [ 38.004960] [drm:skl_set_power_well] Enabling power well 2 [ 38.004964] [drm:intel_power_well_enable] enabling dpio-common-a [ 38.007841] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 38.007844] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 38.007845] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 38.007846] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 38.007847] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 38.007848] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 38.007849] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 38.007850] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 38.007851] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 38.007852] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 38.007853] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 38.007854] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 38.007855] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 38.007856] [drm:verify_single_dpll_state] PORT PLL A [ 38.007858] [drm:verify_single_dpll_state] PORT PLL B [ 38.007859] [drm:verify_single_dpll_state] PORT PLL C [ 38.007865] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 4, on? 0) for crtc 36 [ 38.007866] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 38.007889] [drm:edp_panel_on] Turn eDP port A panel power on [ 38.007891] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 38.279032] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 38.279035] [drm:wait_panel_status] Wait complete [ 38.279036] [drm:wait_panel_on] Wait for panel power on [ 38.279038] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 38.327605] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 38.327609] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 38.327610] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 38.327649] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 38.374454] [drm:wait_panel_status] Wait complete [ 38.374460] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 38.374463] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 38.376033] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 38.376036] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 38.376263] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 38.376788] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 38.376829] [drm:skylake_pfit_enable] for crtc_state = ffff8802704b1800 [ 38.376885] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 38.376889] [drm:intel_enable_pipe] enabling pipe C [ 38.376898] [drm:intel_edp_backlight_on] [ 38.376899] [drm:intel_panel_enable_backlight] pipe C [ 38.376901] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 38.376904] [drm:intel_psr_enable] PSR not supported on this platform [ 38.376905] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 38.381034] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 38.381038] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 38.381054] [drm:verify_single_dpll_state] PORT PLL A [ 38.385222] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 38.405804] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 38.409904] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 38.409909] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 38.409911] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 38.409923] [drm:intel_edp_backlight_off] [ 39.021781] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 39.021791] [drm:intel_disable_pipe] disabling pipe C [ 39.023910] [drm:edp_panel_off] Turn eDP port A panel power off [ 39.023914] [drm:wait_panel_off] Wait for panel power off time [ 39.023917] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000060 [ 39.036970] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 39.036974] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 39.036975] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [ 39.036987] [drm:wait_panel_status] Wait complete [ 39.036993] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 4, on? 1) for crtc 36 [ 39.036997] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 39.037000] [drm:intel_disable_shared_dpll] disabling PORT PLL A [ 39.037006] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 39.037012] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 39.037014] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 39.037015] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 39.037017] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 39.037018] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 39.037019] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 39.037020] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 39.037021] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 39.037022] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 39.037024] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 39.037025] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 39.037027] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 39.037028] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 39.037029] [drm:verify_single_dpll_state] PORT PLL A [ 39.037031] [drm:verify_single_dpll_state] PORT PLL B [ 39.037033] [drm:verify_single_dpll_state] PORT PLL C [ 39.037038] [drm:intel_power_well_disable] disabling power well 2 [ 39.037041] [drm:skl_set_power_well] Disabling power well 2 [ 39.037043] [drm:intel_power_well_disable] disabling dpio-common-a [ 39.037047] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 39.037049] [drm:intel_power_well_disable] disabling DC off [ 39.037050] [drm:gen9_enable_dc5] Enabling DC5 [ 39.037052] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 39.037057] [drm:intel_power_well_disable] disabling always-on [ 39.038469] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 39.038570] [drm:drm_mode_addfb2] [FB:107] [ 39.041989] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 39.041994] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 39.042003] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 39.042004] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 39.042007] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 39.042009] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 39.042010] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 39.042012] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 39.042014] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88026e44f000 for pipe C [ 39.042015] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 39.042016] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 39.042018] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 39.042020] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 39.042021] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 39.042022] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 39.042023] [drm:intel_dump_pipe_config] requested mode: [ 39.042025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 39.042026] [drm:intel_dump_pipe_config] adjusted mode: [ 39.042028] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 39.042030] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 39.042031] [drm:intel_dump_pipe_config] port clock: 162000 [ 39.042032] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 39.042034] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 39.042035] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 39.042036] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 39.042037] [drm:intel_dump_pipe_config] ips: 0 [ 39.042038] [drm:intel_dump_pipe_config] double wide: 0 [ 39.042040] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 39.042042] [drm:intel_dump_pipe_config] planes on this crtc [ 39.042043] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 39.042044] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 39.042045] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 39.042048] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 39.042051] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 39.042054] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B [ 39.042055] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C [ 39.042057] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 39.042148] [drm:intel_power_well_enable] enabling always-on [ 39.042149] [drm:intel_power_well_enable] enabling DC off [ 39.042213] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 39.042216] [drm:intel_power_well_enable] enabling power well 2 [ 39.042218] [drm:skl_set_power_well] Enabling power well 2 [ 39.042222] [drm:intel_power_well_enable] enabling dpio-common-bc [ 39.042223] [drm:intel_power_well_enable] enabling dpio-common-a [ 39.045518] [drm:intel_power_well_disable] disabling dpio-common-a [ 39.045526] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 39.049402] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 39.049406] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 39.049409] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 39.049410] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 39.049412] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 39.049413] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 39.049414] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 39.049416] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 39.049417] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 39.049418] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 39.049419] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 39.049421] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 39.049422] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 39.049424] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 39.049426] [drm:verify_single_dpll_state] PORT PLL A [ 39.049427] [drm:verify_single_dpll_state] PORT PLL B [ 39.049429] [drm:verify_single_dpll_state] PORT PLL C [ 39.049436] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36 [ 39.049437] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 39.052386] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 39.052388] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 39.053432] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 39.056728] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 39.056777] [drm:skylake_pfit_enable] for crtc_state = ffff88026e44f000 [ 39.056834] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 39.056835] [drm:intel_enable_pipe] enabling pipe C [ 39.056847] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 39.056849] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD [ 39.061016] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 39.061021] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 39.061037] [drm:verify_single_dpll_state] PORT PLL B [ 39.065184] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 39.085703] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 39.089847] [drm:intel_modeset_checks] New cdclk calculated to be atomic 144000, actual 144000 [ 39.089852] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 39.089854] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 39.089865] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C [ 39.089882] [drm:intel_disable_pipe] disabling pipe C [ 39.094064] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36 [ 39.094073] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 39.094078] [drm:bxt_set_cdclk] Changing CDCLK to 144000 kHz (VCO 1152000 kHz) [ 39.097706] [drm:intel_update_cdclk] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 39.097710] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 39.097713] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 39.097715] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 39.097716] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 39.097717] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 39.097718] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 39.097720] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 39.097721] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 39.097722] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 39.097723] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 39.097725] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 39.097726] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 39.097728] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 39.097730] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 39.097731] [drm:verify_single_dpll_state] PORT PLL A [ 39.097733] [drm:verify_single_dpll_state] PORT PLL B [ 39.097734] [drm:verify_single_dpll_state] PORT PLL C [ 39.097740] [drm:intel_power_well_disable] disabling dpio-common-bc [ 39.097742] [drm:intel_power_well_disable] disabling power well 2 [ 39.097746] [drm:skl_set_power_well] Disabling power well 2 [ 39.097749] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 39.097750] [drm:intel_power_well_disable] disabling DC off [ 39.097752] [drm:gen9_enable_dc5] Enabling DC5 [ 39.097754] [drm:gen9_set_dc_state] Setting DC state from 00 to 01 [ 39.097756] [drm:intel_power_well_disable] disabling always-on [ 39.099171] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 39.099272] [drm:drm_mode_addfb2] [FB:107] [ 39.102699] [drm:drm_mode_setcrtc] [CRTC:36:pipe C] [ 39.102704] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-1] [ 39.102712] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 39.102714] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 39.102716] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 39.102718] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 39.102720] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 39.102721] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 39.102723] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff88007798a000 for pipe C [ 39.102725] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 39.102726] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 39.102727] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 39.102729] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 39.102730] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 39.102732] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 39.102732] [drm:intel_dump_pipe_config] requested mode: [ 39.102735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 39.102736] [drm:intel_dump_pipe_config] adjusted mode: [ 39.102738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 39.102740] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 39.102741] [drm:intel_dump_pipe_config] port clock: 162000 [ 39.102742] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 39.102743] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 39.102745] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 39.102746] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 39.102747] [drm:intel_dump_pipe_config] ips: 0 [ 39.102748] [drm:intel_dump_pipe_config] double wide: 0 [ 39.102750] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 39.102751] [drm:intel_dump_pipe_config] planes on this crtc [ 39.102752] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] disabled, scaler_id = -1 [ 39.102754] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 39.102755] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 39.102758] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 39.102760] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 39.102763] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL B [ 39.102765] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe C [ 39.102766] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 39.102858] [drm:intel_power_well_enable] enabling always-on [ 39.102859] [drm:intel_power_well_enable] enabling DC off [ 39.102922] [drm:gen9_set_dc_state] Setting DC state from 01 to 00 [ 39.102926] [drm:intel_power_well_enable] enabling power well 2 [ 39.102927] [drm:skl_set_power_well] Enabling power well 2 [ 39.102932] [drm:intel_power_well_enable] enabling dpio-common-bc [ 39.102933] [drm:intel_power_well_enable] enabling dpio-common-a [ 39.106349] [drm:intel_power_well_disable] disabling dpio-common-a [ 39.106357] [drm:bxt_set_cdclk] Changing CDCLK to 288000 kHz (VCO 1152000 kHz) [ 39.110490] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz [ 39.110493] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 39.110496] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 39.110497] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 39.110498] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 39.110499] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 39.110500] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 39.110502] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 39.110503] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 39.110504] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 39.110505] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 39.110506] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 39.110507] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 39.110509] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 39.110510] [drm:verify_single_dpll_state] PORT PLL A [ 39.110512] [drm:verify_single_dpll_state] PORT PLL B [ 39.110513] [drm:verify_single_dpll_state] PORT PLL C [ 39.110520] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 4, on? 0) for crtc 36 [ 39.110521] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 39.111281] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 39.111283] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 39.113924] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 39.117567] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 39.117621] [drm:skylake_pfit_enable] for crtc_state = ffff88007798a000 [ 39.117675] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 39.117676] [drm:intel_enable_pipe] enabling pipe C [ 39.117689] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 39.117690] [drm:hsw_audio_codec_enable] Enable audio codec on pipe C, 36 bytes ELD [ 39.121843] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 39.121848] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 39.121863] [drm:verify_single_dpll_state] PORT PLL B [ 39.125997] [drm:pipe_crc_set_source] collecting CRCs for pipe C, pf [ 39.156393] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-C [ 39.199303] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-C [ 39.200208] kms_pipe_crc_basic: exiting, ret=99 [ 39.200235] [drm:pipe_crc_set_source] stopping CRCs for pipe C [ 39.204057] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains [ 39.204058] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 39.204060] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 39.204061] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz [ 39.204063] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [ 39.204064] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000 [ 39.204065] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 39.204066] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8802709d3800 for pipe A [ 39.204066] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 39.204067] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 39.204068] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 39.204068] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 [ 39.204069] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 39.204070] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 39.204070] [drm:intel_dump_pipe_config] requested mode: [ 39.204071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 39.204072] [drm:intel_dump_pipe_config] adjusted mode: [ 39.204073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [ 39.204074] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa [ 39.204074] [drm:intel_dump_pipe_config] port clock: 270000 [ 39.204075] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 39.204075] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 39.204076] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 39.204077] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 39.204077] [drm:intel_dump_pipe_config] ips: 0 [ 39.204077] [drm:intel_dump_pipe_config] double wide: 0 [ 39.204079] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 39.204079] [drm:intel_dump_pipe_config] planes on this crtc [ 39.204080] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 39.204080] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 39.204081] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 39.204081] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1 [ 39.204082] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-1] checking for sink bpp constrains [ 39.204082] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 39.204083] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 39.204084] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 39.204085] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 39.204085] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 39.204086] [drm:intel_dump_pipe_config] [CRTC:31:pipe B][modeset] config ffff8802709d0800 for pipe B [ 39.204087] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 39.204087] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 39.204088] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 39.204089] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 39.204089] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 39.204090] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 39.204090] [drm:intel_dump_pipe_config] requested mode: [ 39.204091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 39.204091] [drm:intel_dump_pipe_config] adjusted mode: [ 39.204093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 39.204094] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 39.204094] [drm:intel_dump_pipe_config] port clock: 162000 [ 39.204094] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 39.204095] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 39.204096] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 39.204096] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 39.204096] [drm:intel_dump_pipe_config] ips: 0 [ 39.204097] [drm:intel_dump_pipe_config] double wide: 0 [ 39.204098] [drm:intel_dump_pipe_config] ddi_pll_sel: 2; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 39.204098] [drm:intel_dump_pipe_config] planes on this crtc [ 39.204099] [drm:intel_dump_pipe_config] [PLANE:29:plane 1B] disabled, scaler_id = -1 [ 39.204099] [drm:intel_dump_pipe_config] [PLANE:30:cursor B] disabled, scaler_id = -1 [ 39.204100] [drm:intel_dump_pipe_config] [PLANE:32:plane 2B] disabled, scaler_id = -1 [ 39.204100] [drm:intel_dump_pipe_config] [PLANE:33:plane 3B] disabled, scaler_id = -1 [ 39.204101] [drm:connected_sink_compute_bpp] [CONNECTOR:54:DP-2] checking for sink bpp constrains [ 39.204102] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [ 39.204102] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz [ 39.204103] [drm:intel_dp_compute_config] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 39.204104] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400 [ 39.204104] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 39.204105] [drm:intel_dump_pipe_config] [CRTC:36:pipe C][modeset] config ffff8802709d7800 for pipe C [ 39.204106] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 39.204106] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 39.204107] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 39.204107] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 39.204108] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 39.204109] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 39.204109] [drm:intel_dump_pipe_config] requested mode: [ 39.204110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 39.204110] [drm:intel_dump_pipe_config] adjusted mode: [ 39.204112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 [ 39.204113] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 [ 39.204113] [drm:intel_dump_pipe_config] port clock: 162000 [ 39.204113] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 39.204114] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 [ 39.204114] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 39.204115] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 39.204115] [drm:intel_dump_pipe_config] ips: 0 [ 39.204116] [drm:intel_dump_pipe_config] double wide: 0 [ 39.204117] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d [ 39.204117] [drm:intel_dump_pipe_config] planes on this crtc [ 39.204119] [drm:intel_dump_pipe_config] [PLANE:34:plane 1C] enabled [ 39.204120] [drm:intel_dump_pipe_config] FB:107, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 39.204120] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 [ 39.204121] [drm:intel_dump_pipe_config] [PLANE:35:cursor C] disabled, scaler_id = -1 [ 39.204121] [drm:intel_dump_pipe_config] [PLANE:37:plane 2C] disabled, scaler_id = -1 [ 39.204122] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000 [ 39.204124] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 39.204125] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 39.204126] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 39.204127] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A [ 39.204128] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A [ 39.204129] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 39.204129] [drm:bxt_get_dpll] [CRTC:31:pipe B] using pre-allocated PORT PLL B [ 39.204130] [drm:intel_reference_shared_dpll] using PORT PLL B for pipe B [ 39.204130] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:31:pipe B] scaler_user index 1.31 [ 39.204131] [drm:bxt_get_dpll] [CRTC:36:pipe C] using pre-allocated PORT PLL C [ 39.204132] [drm:intel_reference_shared_dpll] using PORT PLL C for pipe C [ 39.204132] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:36:pipe C] scaler_user index 2.31 [ 39.204144] [drm:intel_power_well_enable] enabling dpio-common-a [ 39.206198] [drm:hsw_audio_codec_disable] Disable audio codec on pipe C [ 39.206211] [drm:intel_disable_pipe] disabling pipe C [ 39.208309] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 4, on? 1) for crtc 36 [ 39.208316] [drm:intel_disable_shared_dpll] disabling PORT PLL B [ 39.208319] [drm:verify_encoder_state] [ENCODER:38:DDI A] [ 39.208319] [drm:verify_encoder_state] [ENCODER:46:DDI B] [ 39.208320] [drm:verify_encoder_state] [ENCODER:48:DP-MST A] [ 39.208320] [drm:verify_encoder_state] [ENCODER:49:DP-MST B] [ 39.208321] [drm:verify_encoder_state] [ENCODER:50:DP-MST C] [ 39.208321] [drm:verify_encoder_state] [ENCODER:53:DDI C] [ 39.208322] [drm:verify_encoder_state] [ENCODER:55:DP-MST A] [ 39.208322] [drm:verify_encoder_state] [ENCODER:56:DP-MST B] [ 39.208322] [drm:verify_encoder_state] [ENCODER:57:DP-MST C] [ 39.208323] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1] [ 39.208324] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2] [ 39.208325] [drm:verify_single_dpll_state] PORT PLL A [ 39.208326] [drm:verify_single_dpll_state] PORT PLL B [ 39.208327] [drm:verify_single_dpll_state] PORT PLL C [ 39.208332] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26 [ 39.208332] [drm:intel_enable_shared_dpll] enabling PORT PLL A [ 39.208355] [drm:edp_panel_on] Turn eDP port A panel power on [ 39.208355] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 39.208358] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060 [ 39.208359] [drm:wait_panel_status] Wait complete [ 39.208359] [drm:wait_panel_on] Wait for panel power on [ 39.208361] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000063 [ 39.234672] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 [ 39.234673] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 39.234673] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1 [ 39.234696] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 39.268429] [drm:wait_panel_status] Wait complete [ 39.268433] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 39.268435] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b [ 39.269167] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 39.269167] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 39.269401] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 39.269933] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 39.269976] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d3800 [ 39.270029] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 39.270032] [drm:intel_enable_pipe] enabling pipe A [ 39.270043] [drm:intel_edp_backlight_on] [ 39.270044] [drm:intel_panel_enable_backlight] pipe A [ 39.270045] [drm:intel_panel_actually_set_backlight] set backlight PWM = 96000 [ 39.273607] [drm:intel_psr_enable] PSR not supported on this platform [ 39.273607] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 39.273630] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 2, on? 0) for crtc 31 [ 39.273631] [drm:intel_enable_shared_dpll] enabling PORT PLL B [ 39.274387] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 39.274387] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 39.275388] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 39.278669] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 39.278715] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d0800 [ 39.278774] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 39.278775] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 39.278778] [drm:intel_enable_pipe] enabling pipe B [ 39.278791] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:DP-1], [ENCODER:46:DDI B] [ 39.278792] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD [ 39.278829] [drm:intel_enable_shared_dpll] enable PORT PLL C (active 4, on? 0) for crtc 36 [ 39.278829] [drm:intel_enable_shared_dpll] enabling PORT PLL C [ 39.280297] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 39.280297] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 39.280875] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 39.281420] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 39.281420] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 39.283972] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 39.284020] [drm:skylake_pfit_enable] for crtc_state = ffff8802709d7800 [ 39.284079] [drm:skl_wm_flush_pipe] flush pipe A (pass 3) [ 39.284081] [drm:skl_wm_flush_pipe] flush pipe B (pass 3) [ 39.284082] [drm:skl_wm_flush_pipe] flush pipe C (pass 3) [ 39.284084] [drm:intel_enable_pipe] enabling pipe C [ 39.288263] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1] [ 39.288266] [drm:verify_crtc_state] [CRTC:26:pipe A] [ 39.288283] [drm:verify_single_dpll_state] PORT PLL A [ 39.288290] [drm:intel_connector_verify_state] [CONNECTOR:47:DP-1] [ 39.288292] [drm:verify_crtc_state] [CRTC:31:pipe B] [ 39.288303] [drm:verify_single_dpll_state] PORT PLL B [ 39.288309] [drm:intel_connector_verify_state] [CONNECTOR:54:DP-2] [ 39.288312] [drm:verify_crtc_state] [CRTC:36:pipe C] [ 39.288323] [drm:verify_single_dpll_state] PORT PLL C [ 39.293669] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 39.293671] [drm:i915_pages_create_for_stolen] offset=0x809000, size=16384 [ 39.293718] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 39.293720] [drm:i915_pages_create_for_stolen] offset=0x80d000, size=16384 [ 39.293735] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 39.293737] [drm:i915_pages_create_for_stolen] offset=0x811000, size=16384 [ 39.293751] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 39.293754] [drm:i915_pages_create_for_stolen] offset=0x815000, size=16384 [ 39.894371] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off [ 39.894373] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067 [ 41.368637] [drm] stuck on render ring [ 41.369864] [drm] GPU HANG: ecode 9:0:0xe7577ffe, in kms_pipe_crc_ba [1613], reason: Engine(s) hung, action: reset [ 41.369882] [drm:i915_reset_and_wakeup] resetting chip [ 41.370742] drm/i915: Resetting chip after gpu hang [ 41.370754] [drm:gen8_init_common_ring] Execlists enabled for render ring [ 41.370771] [drm:gen8_init_common_ring] Execlists enabled for blitter ring [ 41.370787] [drm:gen8_init_common_ring] Execlists enabled for bsd ring [ 41.370802] [drm:gen8_init_common_ring] Execlists enabled for video enhancement ring [ 41.370823] [drm:intel_guc_setup] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch SUCCESS, load SUCCESS [ 41.370825] [drm:intel_guc_setup] GuC fw status: fetch SUCCESS, load PENDING [ 41.372597] [drm:guc_ucode_xfer_dma] DMA status 0x10, GuC status 0x8002f0ec [ 41.372598] [drm:guc_ucode_xfer_dma] returning 0 [ 41.372599] [drm:intel_guc_setup] GuC fw status: fetch SUCCESS, load SUCCESS [ 41.372608] [drm:select_doorbell_register] assigned normal priority doorbell id 0x0 [ 41.372609] [drm:select_doorbell_cacheline] selected doorbell cacheline 0xc0, next 0x100, linesize 64 [ 41.372615] [drm:guc_client_alloc] new priority 2 client ffff88027002c480: ctx_index 0 [ 41.372615] [drm:guc_client_alloc] doorbell id 0, cacheline offset 0xc0 [ 41.377010] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 41.377011] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4 [ 41.377012] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8 [ 41.841952] [drm] RC6 on