Command: ./specops.i386 Driver vendor: X.Org Device vendor: AMD Device name: AMD TONGA (DRM 3.2.0 / 4.7.0-gentoo, LLVM 4.0.0) Draw call sequence # = 18870557 HW reached sequence # = 18870556 Elapsed time = 10000 ms draw_info: {indexed = 1, mode = triangles, start = 0, count = 10128, start_instance = 0, instance_count = 1, vertices_per_patch = 3, index_bias = 0, min_index = 0, max_index = 4294967295, primitive_restart = 0, restart_index = 0, count_from_stream_output = NULL, indirect = NULL, indirect_offset = 0, } index_buffer: {index_size = 2, offset = 0, buffer = 0xe2964260, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 20256, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 32, flags = 0, } vertex_buffer 0: {stride = 32, buffer_offset = 16, buffer = 0xe2964068, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 103200, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 16, flags = 0, } vertex_buffer 1: {stride = 32, buffer_offset = 0, buffer = 0xe2964068, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 103200, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 16, flags = 0, } vertex_buffer 2: {stride = 32, buffer_offset = 4, buffer = 0xe2964068, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 103200, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 16, flags = 0, } vertex_buffer 3: {stride = 32, buffer_offset = 8, buffer = 0xe2964068, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 103200, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 16, flags = 0, } vertex_buffer 4: {stride = 32, buffer_offset = 12, buffer = 0xe2964068, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 103200, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 16, flags = 0, } vertex_buffer 5: {stride = 32, buffer_offset = 28, buffer = 0xe2964068, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 103200, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 16, flags = 0, } vertex_buffer 6: {stride = 0, buffer_offset = 585456, buffer = 0x84c94af0, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 1048576, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 3, bind = 16, flags = 3, } num vertex elements = 7 vertex_element 0: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_FLOAT, } vertex_element 1: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 1, src_format = PIPE_FORMAT_R8G8B8A8_USCALED, } vertex_element 2: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 2, src_format = PIPE_FORMAT_R8G8B8A8_USCALED, } vertex_element 3: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 3, src_format = PIPE_FORMAT_R8G8B8A8_USCALED, } vertex_element 4: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 4, src_format = PIPE_FORMAT_R8G8B8A8_UNORM, } vertex_element 5: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 5, src_format = PIPE_FORMAT_R16G16_FLOAT, } vertex_element 6: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 6, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } num stream output targets = 0 begin shader: VERTEX shader_state: {tokens = " VERT PROPERTY NEXT_SHADER FRAG DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL IN[5] DCL IN[6] DCL OUT[0], POSITION DCL OUT[1..10], ARRAY(1), GENERIC[0] DCL CONST[1][0..31] DCL CONST[2][0..255] DCL CONST[3][0..31] DCL CONST[4][0..8] DCL TEMP[0..9], ARRAY(1), LOCAL DCL TEMP[10..18], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0.0000, 2.0000, 0.0000, 0.0000} IMM[1] UINT32 {1, 3824, 3808, 80} IMM[2] INT32 {7, 4, 6, 8} IMM[3] UINT32 {16, 3712, 3696, 3728} IMM[4] UINT32 {3744, 64, 3776, 3760} IMM[5] UINT32 {3792, 3840, 3856, 0} IMM[6] UINT32 {32, 48, 3, 0} 0: MOV TEMP[0], IMM[0].xxxx 1: MOV TEMP[1], IMM[0].xxxx 2: MOV TEMP[2], IMM[0].xxxx 3: MOV TEMP[3], IMM[0].xxxx 4: MOV TEMP[4], IMM[0].xxxx 5: MOV TEMP[5], IMM[0].xxxx 6: MOV TEMP[6], IMM[0].xxxx 7: MOV TEMP[7], IMM[0].xxxx 8: MOV TEMP[8], IMM[0].xxxx 9: MOV TEMP[9], IMM[0].xxxx 10: MAD TEMP[10].xyz, IN[0].xyzz, CONST[2][239].xyzz, CONST[2][238].xyzz 11: MOV TEMP[10].w, CONST[2][5].wwww 12: MUL TEMP[11], CONST[2][5].xxxx, IN[3] 13: ROUND TEMP[12], TEMP[11] 14: F2I TEMP[12], TEMP[12] 15: UADD TEMP[13].x, TEMP[12].yyyy, IMM[2].xxxx 16: UMUL TEMP[13].x, TEMP[13].xxxx, IMM[3].xxxx 17: USHR TEMP[14].x, TEMP[13].xxxx, IMM[2].yyyy 18: UARL ADDR[0].x, TEMP[14].xxxx 19: MOV TEMP[13], CONST[2][ADDR[0].x] 20: MUL TEMP[11], IN[4].yyyy, TEMP[13] 21: UADD TEMP[13].x, TEMP[12].xxxx, IMM[2].xxxx 22: UMUL TEMP[13].x, TEMP[13].xxxx, IMM[3].xxxx 23: USHR TEMP[14].x, TEMP[13].xxxx, IMM[2].yyyy 24: UARL ADDR[0].x, TEMP[14].xxxx 25: MOV TEMP[13], CONST[2][ADDR[0].x] 26: MAD TEMP[11], IN[4].xxxx, TEMP[13], TEMP[11] 27: UADD TEMP[13].x, TEMP[12].zzzz, IMM[2].xxxx 28: UMUL TEMP[13].x, TEMP[13].xxxx, IMM[3].xxxx 29: USHR TEMP[14].x, TEMP[13].xxxx, IMM[2].yyyy 30: UARL ADDR[0].x, TEMP[14].xxxx 31: MOV TEMP[13], CONST[2][ADDR[0].x] 32: MAD TEMP[11], IN[4].zzzz, TEMP[13], TEMP[11] 33: UADD TEMP[13].x, TEMP[12].wwww, IMM[2].xxxx 34: UMUL TEMP[13].x, TEMP[13].xxxx, IMM[3].xxxx 35: USHR TEMP[14].x, TEMP[13].xxxx, IMM[2].yyyy 36: UARL ADDR[0].x, TEMP[14].xxxx 37: MOV TEMP[13], CONST[2][ADDR[0].x] 38: MAD TEMP[11], IN[4].wwww, TEMP[13], TEMP[11] 39: DP4 TEMP[13].x, TEMP[10], TEMP[11] 40: MUL TEMP[13], TEMP[13].xxxx, CONST[2][232] 41: UADD TEMP[14].x, TEMP[12].yyyy, IMM[2].zzzz 42: UMUL TEMP[14].x, TEMP[14].xxxx, IMM[3].xxxx 43: USHR TEMP[15].x, TEMP[14].xxxx, IMM[2].yyyy 44: UARL ADDR[0].x, TEMP[15].xxxx 45: MOV TEMP[14], CONST[2][ADDR[0].x] 46: MUL TEMP[14], IN[4].yyyy, TEMP[14] 47: UADD TEMP[15].x, TEMP[12].xxxx, IMM[2].zzzz 48: UMUL TEMP[15].x, TEMP[15].xxxx, IMM[3].xxxx 49: USHR TEMP[16].x, TEMP[15].xxxx, IMM[2].yyyy 50: UARL ADDR[0].x, TEMP[16].xxxx 51: MOV TEMP[15], CONST[2][ADDR[0].x] 52: MAD TEMP[14], IN[4].xxxx, TEMP[15], TEMP[14] 53: UADD TEMP[15].x, TEMP[12].zzzz, IMM[2].zzzz 54: UMUL TEMP[15].x, TEMP[15].xxxx, IMM[3].xxxx 55: USHR TEMP[16].x, TEMP[15].xxxx, IMM[2].yyyy 56: UARL ADDR[0].x, TEMP[16].xxxx 57: MOV TEMP[15], CONST[2][ADDR[0].x] 58: MAD TEMP[14], IN[4].zzzz, TEMP[15], TEMP[14] 59: UADD TEMP[15].x, TEMP[12].wwww, IMM[2].zzzz 60: UMUL TEMP[15].x, TEMP[15].xxxx, IMM[3].xxxx 61: USHR TEMP[16].x, TEMP[15].xxxx, IMM[2].yyyy 62: UARL ADDR[0].x, TEMP[16].xxxx 63: MOV TEMP[15], CONST[2][ADDR[0].x] 64: MAD TEMP[14], IN[4].wwww, TEMP[15], TEMP[14] 65: DP4 TEMP[15].x, TEMP[10], TEMP[14] 66: MAD TEMP[13], CONST[2][231], TEMP[15].xxxx, TEMP[13] 67: UADD TEMP[15].x, TEMP[12].yyyy, IMM[2].wwww 68: UMUL TEMP[15].x, TEMP[15].xxxx, IMM[3].xxxx 69: USHR TEMP[16].x, TEMP[15].xxxx, IMM[2].yyyy 70: UARL ADDR[0].x, TEMP[16].xxxx 71: MOV TEMP[15], CONST[2][ADDR[0].x] 72: MUL TEMP[15], IN[4].yyyy, TEMP[15] 73: UADD TEMP[16].x, TEMP[12].xxxx, IMM[2].wwww 74: UMUL TEMP[16].x, TEMP[16].xxxx, IMM[3].xxxx 75: USHR TEMP[17].x, TEMP[16].xxxx, IMM[2].yyyy 76: UARL ADDR[0].x, TEMP[17].xxxx 77: MOV TEMP[16], CONST[2][ADDR[0].x] 78: MAD TEMP[15], IN[4].xxxx, TEMP[16], TEMP[15] 79: UADD TEMP[16].x, TEMP[12].zzzz, IMM[2].wwww 80: UMUL TEMP[16].x, TEMP[16].xxxx, IMM[3].xxxx 81: USHR TEMP[17].x, TEMP[16].xxxx, IMM[2].yyyy 82: UARL ADDR[0].x, TEMP[17].xxxx 83: MOV TEMP[16], CONST[2][ADDR[0].x] 84: MAD TEMP[15], IN[4].zzzz, TEMP[16], TEMP[15] 85: UADD TEMP[12].x, TEMP[12].wwww, IMM[2].wwww 86: UMUL TEMP[12].x, TEMP[12].xxxx, IMM[3].xxxx 87: USHR TEMP[16].x, TEMP[12].xxxx, IMM[2].yyyy 88: UARL ADDR[0].x, TEMP[16].xxxx 89: MOV TEMP[12], CONST[2][ADDR[0].x] 90: MAD TEMP[15], IN[4].wwww, TEMP[12], TEMP[15] 91: DP4 TEMP[12].x, TEMP[10], TEMP[15] 92: MAD TEMP[10], CONST[2][233], TEMP[12].xxxx, TEMP[13] 93: ADD TEMP[10], TEMP[10], CONST[2][234] 94: MAD TEMP[13].xyz, TEMP[10].xyzz, -CONST[2][4].wwww, CONST[2][4].xyzz 95: MUL TEMP[12].xyz, TEMP[13].yyyy, CONST[2][236].xyzz 96: MAD TEMP[16].xyz, CONST[2][235].xyzz, TEMP[13].xxxx, TEMP[12].xyzz 97: MAD TEMP[13].xyz, CONST[2][237].xyzz, TEMP[13].zzzz, TEMP[16].xyzz 98: MAD TEMP[12].xyz, IN[1].xyzz, CONST[2][5].yyyy, CONST[2][5].zzzz 99: DP3 TEMP[16].x, TEMP[12].xyzz, TEMP[14].xyzz 100: DP3 TEMP[17].x, TEMP[12].xyzz, TEMP[11].xyzz 101: MOV TEMP[16].y, TEMP[17].xxxx 102: DP3 TEMP[17].x, TEMP[12].xyzz, TEMP[15].xyzz 103: MOV TEMP[16].z, TEMP[17].xxxx 104: DP3 TEMP[17].x, TEMP[16].xyzz, TEMP[13].xyzz 105: MAD TEMP[12], IN[2], CONST[2][5].yyyy, CONST[2][5].zzzz 106: DP3 TEMP[14].x, TEMP[12].xyzz, TEMP[14].xyzz 107: DP3 TEMP[18].x, TEMP[12].xyzz, TEMP[11].xyzz 108: MOV TEMP[14].y, TEMP[18].xxxx 109: DP3 TEMP[18].x, TEMP[12].xyzz, TEMP[15].xyzz 110: MOV TEMP[14].z, TEMP[18].xxxx 111: MUL TEMP[11].xyz, TEMP[16].yzxx, TEMP[14].zxyy 112: MAD TEMP[11].xyz, TEMP[14].yzxx, TEMP[16].zxyy, -TEMP[11].xyzz 113: MUL TEMP[11].xyz, TEMP[12].wwww, TEMP[11].xyzz 114: DP3 TEMP[12].x, TEMP[11].xyzz, TEMP[13].xyzz 115: MOV TEMP[17].y, TEMP[12].xxxx 116: DP3 TEMP[12].x, TEMP[14].xyzz, TEMP[13].xyzz 117: MOV TEMP[17].z, TEMP[12].xxxx 118: MUL TEMP[15].xyz, CONST[2][240].yyyy, CONST[2][236].xyzz 119: MAD TEMP[12].xyz, CONST[2][235].xyzz, CONST[2][240].xxxx, TEMP[15].xyzz 120: MAD TEMP[13].xyz, CONST[2][237].xyzz, CONST[2][240].zzzz, TEMP[12].xyzz 121: DP3 TEMP[12].x, TEMP[16].xyzz, TEMP[13].xyzz 122: DP3 TEMP[15].x, TEMP[16].xyzz, CONST[2][237].xyzz 123: DP3 TEMP[16].x, TEMP[11].xyzz, TEMP[13].xyzz 124: MOV TEMP[12].y, TEMP[16].xxxx 125: DP3 TEMP[16].x, TEMP[11].xyzz, CONST[2][237].xyzz 126: MOV TEMP[15].y, TEMP[16].xxxx 127: DP3 TEMP[13].x, TEMP[14].xyzz, TEMP[13].xyzz 128: MOV TEMP[12].z, TEMP[13].xxxx 129: DP3 TEMP[13].x, TEMP[14].xyzz, CONST[2][237].xyzz 130: MOV TEMP[15].z, TEMP[13].xxxx 131: MOV TEMP[13].xyz, TEMP[14].xyzx 132: MOV TEMP[12].w, CONST[2][241].xxxx 133: MUL TEMP[11], TEMP[10].yyyy, CONST[2][1] 134: MAD TEMP[11], CONST[2][0], TEMP[10].xxxx, TEMP[11] 135: MAD TEMP[11], CONST[2][2], TEMP[10].zzzz, TEMP[11] 136: MAD TEMP[10], CONST[2][3], TEMP[10].wwww, TEMP[11] 137: MOV TEMP[17].w, CONST[2][5].wwww 138: MOV TEMP[13].w, CONST[2][5].wwww 139: MOV TEMP[1], IN[6].zyxw 140: MOV TEMP[0].xy, IN[5].xyxx 141: MOV TEMP[4], TEMP[12] 142: MOV TEMP[5], TEMP[10] 143: MOV TEMP[6], TEMP[17] 144: MOV TEMP[7].xyz, TEMP[15].xyzx 145: MOV TEMP[2], TEMP[13] 146: MOV TEMP[11].xw, TEMP[10].xxzw 147: MOV TEMP[11].y, -TEMP[10].yyyy 148: MAD TEMP[11].xy, TEMP[10].wwww, CONST[4][0].zwww, TEMP[11].xyyy 149: MAD TEMP[10].x, TEMP[10].zzzz, IMM[0].yyyy, -TEMP[10].wwww 150: MOV TEMP[11].z, TEMP[10].xxxx 151: MOV OUT[0], TEMP[11] 152: MOV OUT[1], TEMP[0] 153: MOV OUT[2], TEMP[1] 154: MOV OUT[3], TEMP[2] 155: MOV OUT[4], TEMP[3] 156: MOV OUT[5], TEMP[4] 157: MOV OUT[6], TEMP[5] 158: MOV OUT[7], TEMP[6] 159: MOV OUT[8], TEMP[7] 160: MOV OUT[9], TEMP[8] 161: MOV OUT[10], TEMP[9] 162: END ", } constant_buffer 1: {buffer = 0xeb27e8a8, buffer_offset = 0, buffer_size = 256, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 258048, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 2: {buffer = 0xeb27e4b8, buffer_offset = 3485696, buffer_size = 4096, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 4096000, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 3: {buffer = 0xeb27ed08, buffer_offset = 0, buffer_size = 64, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 65536, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 4: {buffer = 0xb3f66eb8, buffer_offset = 129312, buffer_size = 144, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 147456, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } end shader: VERTEX viewport_state 0: {scale = {960, 540, 0.5, }, translate = {960, 540, 0.5, }, } rasterizer_state: {flatshade = 0, light_twoside = 0, clamp_vertex_color = 0, clamp_fragment_color = 0, front_ccw = 1, cull_face = 2, fill_front = 0, fill_back = 0, offset_point = 0, offset_line = 0, offset_tri = 0, scissor = 0, poly_smooth = 0, poly_stipple_enable = 0, point_smooth = 0, sprite_coord_enable = 0, sprite_coord_mode = 1, point_quad_rasterization = 1, point_tri_clip = 0, point_size_per_vertex = 0, multisample = 0, line_smooth = 0, line_stipple_enable = 0, line_stipple_factor = 0, line_stipple_pattern = 65535, line_last_pixel = 0, flatshade_first = 0, half_pixel_center = 1, bottom_edge_rule = 0, rasterizer_discard = 0, depth_clip = 1, clip_halfz = 0, clip_plane_enable = 0, line_width = 1, point_size = 1, offset_units = 0, offset_scale = 0, offset_clamp = 0, } begin shader: FRAGMENT shader_state: {tokens = " FRAG DCL IN[0..6], ARRAY(1), GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL OUT[1], COLOR[1] DCL OUT[2], COLOR[2] DCL OUT[3], COLOR[3] DCL OUT[4], COLOR[4] DCL OUT[5], COLOR[5] DCL OUT[6], COLOR[6] DCL OUT[7], COLOR[7] DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], 2D, FLOAT DCL CONST[1][0..15] DCL CONST[2][0..8] DCL CONST[3][0..1] DCL CONST[4][0..223] DCL CONST[5][0..15] DCL TEMP[0..9], LOCAL DCL TEMP[10..17], ARRAY(1), LOCAL IMM[0] FLT32 { 2.0000, -1.0000, 1.0000, 0.0000} IMM[1] UINT32 {3, 112, 128, 80} IMM[2] FLT32 { -0.0000, 0.0000, 0.0000, 0.0000} IMM[3] UINT32 {0, 96, 64, 144} IMM[4] UINT32 {160, 32, 0, 0} 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D 2: MAD TEMP[0].xyz, TEMP[0].xyzz, IMM[0].xxxx, IMM[0].yyyy 3: DP3 TEMP[1].x, IN[6].xyzz, IN[6].xyzz 4: RSQ TEMP[1].x, TEMP[1].xxxx 5: MUL TEMP[1].xyz, IN[6].xyzz, TEMP[1].xxxx 6: DP3 TEMP[2].x, TEMP[0].xyzz, TEMP[1].xyzz 7: DP3 TEMP[3].x, TEMP[0].xyzz, TEMP[0].xyzz 8: RSQ TEMP[3].x, TEMP[3].xxxx 9: MUL TEMP[3].xyz, TEMP[0].xyzz, TEMP[3].xxxx 10: ADD TEMP[0].x, -TEMP[2].xxxx, IMM[0].zzzz 11: FSLT TEMP[4].x, TEMP[2].xxxx, IMM[0].wwww 12: UIF TEMP[4].xxxx :0 13: MOV TEMP[4].x, IMM[0].zzzz 14: ELSE :0 15: MOV TEMP[4].x, TEMP[0].xxxx 16: ENDIF 17: ABS TEMP[5].x, TEMP[4].xxxx 18: ABS TEMP[6].x, TEMP[4].xxxx 19: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 20: MUL TEMP[6].x, TEMP[5].xxxx, TEMP[5].xxxx 21: MUL TEMP[5].x, TEMP[5].xxxx, CONST[4][7].wwww 22: ABS TEMP[7].x, TEMP[4].xxxx 23: MUL TEMP[6].x, TEMP[6].xxxx, TEMP[7].xxxx 24: ABS TEMP[4].x, TEMP[4].xxxx 25: ADD TEMP[0].x, TEMP[4].xxxx, IMM[2].xxxx 26: FSLT TEMP[4].x, TEMP[0].xxxx, IMM[0].wwww 27: UIF TEMP[4].xxxx :0 28: MOV TEMP[4].x, IMM[0].wwww 29: ELSE :0 30: MOV TEMP[4].x, TEMP[6].xxxx 31: ENDIF 32: ADD TEMP[6].x, TEMP[4].xxxx, IMM[2].xxxx 33: ABS TEMP[4].x, TEMP[4].xxxx 34: POW TEMP[4].x, TEMP[4].xxxx, CONST[4][8].yyyy 35: MOV TEMP[7].xy, IN[0].xyyy 36: TEX TEMP[7].xyz, TEMP[7], SAMP[1], 2D 37: MUL TEMP[8].xyz, TEMP[4].xxxx, TEMP[7].xyzz 38: FSLT TEMP[6].x, TEMP[6].xxxx, IMM[0].wwww 39: UIF TEMP[6].xxxx :0 40: MOV TEMP[6].xyz, IMM[0].wwww 41: ELSE :0 42: MOV TEMP[6].xyz, TEMP[8].xyzx 43: ENDIF 44: MAX TEMP[6].xyz, TEMP[6].xyzz, IMM[0].wwww 45: MIN TEMP[9].xyz, TEMP[6].xyzz, IMM[0].xxxx 46: MUL TEMP[6].xyz, CONST[4][5].xyzz, CONST[4][5].wwww 47: MAD TEMP[8].xyz, TEMP[7].xyzz, -TEMP[6].xyzz, TEMP[9].xyzz 48: MUL TEMP[4].xyz, TEMP[7].xyzz, TEMP[6].xyzz 49: MAD TEMP[4].xyz, CONST[4][8].zzzz, TEMP[8].xyzz, TEMP[4].xyzz 50: ADD TEMP[8].xyz, IMM[0].zzzz, -CONST[4][0].xyzz 51: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[8].xyzz 52: DP3 TEMP[6].x, TEMP[3].xyzz, TEMP[1].xyzz 53: MUL TEMP[8].xyz, TEMP[6].xxxx, TEMP[3].xyzz 54: MAD TEMP[1].xyz, TEMP[8].xyzz, IMM[0].xxxx, -TEMP[1].xyzz 55: DP3 TEMP[6].x, IN[4].xyzz, IN[4].xyzz 56: RSQ TEMP[6].x, TEMP[6].xxxx 57: MUL TEMP[8].xyz, IN[4].xyzz, TEMP[6].xxxx 58: DP3 TEMP[6].x, TEMP[1].xyzz, TEMP[8].xyzz 59: MOV_SAT TEMP[6].x, TEMP[6].xxxx 60: DP3 TEMP[3].x, TEMP[3].xyzz, TEMP[8].xyzz 61: MOV_SAT TEMP[3].x, TEMP[3].xxxx 62: ADD TEMP[1].x, TEMP[6].xxxx, IMM[2].xxxx 63: MOV TEMP[7].xy, IN[0].xyyy 64: TEX TEMP[7].xyz, TEMP[7], SAMP[2], 2D 65: MUL TEMP[8].xyz, CONST[4][6].xyzz, CONST[4][6].wwww 66: MUL TEMP[2].xyz, TEMP[7].xyzz, TEMP[8].xyzz 67: ABS TEMP[6].x, TEMP[6].xxxx 68: POW TEMP[6].x, TEMP[6].xxxx, CONST[4][8].wwww 69: MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[2].xyzz 70: FSLT TEMP[7].x, TEMP[1].xxxx, IMM[0].wwww 71: UIF TEMP[7].xxxx :0 72: MOV TEMP[7].xyz, IMM[0].wwww 73: ELSE :0 74: MOV TEMP[7].xyz, TEMP[6].xyzx 75: ENDIF 76: ADD TEMP[6].x, TEMP[3].xxxx, IMM[2].xxxx 77: FSLT TEMP[6].x, TEMP[6].xxxx, IMM[0].wwww 78: UIF TEMP[6].xxxx :0 79: MOV TEMP[6].x, IMM[0].wwww 80: ELSE :0 81: MOV TEMP[6].x, TEMP[3].xxxx 82: ENDIF 83: MAD TEMP[1].xyz, TEMP[4].xyzz, TEMP[6].xxxx, TEMP[7].xyzz 84: MUL TEMP[2].xyz, CONST[4][4].xyzz, CONST[4][4].wwww 85: MUL TEMP[2].xyz, TEMP[5].xxxx, TEMP[2].xyzz 86: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[4][8].xxxx 87: FSLT TEMP[3].x, TEMP[0].xxxx, IMM[0].wwww 88: UIF TEMP[3].xxxx :0 89: MOV TEMP[3].xyz, IMM[0].wwww 90: ELSE :0 91: MOV TEMP[3].xyz, TEMP[2].xyzx 92: ENDIF 93: ADD TEMP[0].xyz, TEMP[3].xyzz, CONST[4][0].xyzz 94: MAD TEMP[0].xyz, TEMP[1].xyzz, CONST[4][9].xyzz, TEMP[0].xyzz 95: MAD TEMP[10].xyz, TEMP[4].xyzz, CONST[4][10].xyzz, TEMP[0].xyzz 96: RCP TEMP[0].x, IN[5].wwww 97: MAD TEMP[0].x, CONST[4][2].xxxx, TEMP[0].xxxx, CONST[4][2].yyyy 98: MOV TEMP[10].w, TEMP[0].xxxx 99: MOV OUT[0], TEMP[10] 100: MOV OUT[1], TEMP[11] 101: MOV OUT[2], TEMP[12] 102: MOV OUT[3], TEMP[13] 103: MOV OUT[4], TEMP[14] 104: MOV OUT[5], TEMP[15] 105: MOV OUT[6], TEMP[16] 106: MOV OUT[7], TEMP[17] 107: END ", } constant_buffer 0: {buffer = NULL, buffer_offset = 0, buffer_size = 48, user_buffer = 0x96c11f80, } constant_buffer 1: {buffer = 0xeb27efb8, buffer_offset = 7744, buffer_size = 64, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 65536, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 2: {buffer = 0xb3f66eb8, buffer_offset = 129312, buffer_size = 144, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 147456, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 3: {buffer = 0xeb27fa08, buffer_offset = 0, buffer_size = 24, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 4096, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 4: {buffer = 0xeb27e6b0, buffer_offset = 2306048, buffer_size = 4096, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 4096000, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 5: {buffer = 0xeb27eb10, buffer_offset = 0, buffer_size = 256, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 258048, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } sampler_state 0: {wrap_s = repeat, wrap_t = repeat, wrap_r = repeat, min_img_filter = linear, min_mip_filter = linear, mag_img_filter = linear, compare_mode = 0, compare_func = never, normalized_coords = 1, max_anisotropy = 4, seamless_cube_map = 0, lod_bias = 0, min_lod = 0, max_lod = 1000, border_color.f = {0, 0, 0, 0, }, } sampler_state 1: {wrap_s = repeat, wrap_t = repeat, wrap_r = repeat, min_img_filter = linear, min_mip_filter = linear, mag_img_filter = linear, compare_mode = 0, compare_func = never, normalized_coords = 1, max_anisotropy = 4, seamless_cube_map = 0, lod_bias = 0, min_lod = 0, max_lod = 1000, border_color.f = {0, 0, 0, 0, }, } sampler_state 2: {wrap_s = repeat, wrap_t = repeat, wrap_r = repeat, min_img_filter = linear, min_mip_filter = linear, mag_img_filter = linear, compare_mode = 0, compare_func = never, normalized_coords = 1, max_anisotropy = 4, seamless_cube_map = 0, lod_bias = 0, min_lod = 0, max_lod = 1000, border_color.f = {0, 0, 0, 0, }, } sampler_view 0: {target = 2d, format = PIPE_FORMAT_DXT1_RGBA, texture = 0x8d920728, u.tex.first_layer = 0, u.tex.last_layer = 0, u.tex.last_level = 10, u.tex.last_level = 10, swizzle_r = 0, swizzle_g = 1, swizzle_b = 2, swizzle_a = 3, } texture: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, width0 = 1024, height0 = 1024, depth0 = 1, array_size = 1, last_level = 10, nr_samples = 0, usage = 0, bind = 8, flags = 0, } sampler_view 1: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, texture = 0x8915baa0, u.tex.first_layer = 0, u.tex.last_layer = 0, u.tex.last_level = 10, u.tex.last_level = 10, swizzle_r = 0, swizzle_g = 1, swizzle_b = 2, swizzle_a = 3, } texture: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, width0 = 1024, height0 = 1024, depth0 = 1, array_size = 1, last_level = 10, nr_samples = 0, usage = 0, bind = 8, flags = 0, } sampler_view 2: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, texture = 0x8f2b8468, u.tex.first_layer = 0, u.tex.last_layer = 0, u.tex.last_level = 10, u.tex.last_level = 10, swizzle_r = 0, swizzle_g = 1, swizzle_b = 2, swizzle_a = 3, } texture: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, width0 = 1024, height0 = 1024, depth0 = 1, array_size = 1, last_level = 10, nr_samples = 0, usage = 0, bind = 8, flags = 0, } end shader: FRAGMENT depth_stencil_alpha_state: {depth = {enabled = 1, writemask = 1, func = less_equal, }, stencil = {{enabled = 0, }, {enabled = 0, }, }, alpha = {enabled = 0, }, } stencil_ref: {ref_value = {0, 0, }, } blend_state: {dither = 0, alpha_to_coverage = 0, alpha_to_one = 0, logicop_enable = 0, independent_blend_enable = 0, rt = {{blend_enable = 0, colormask = 15, }, }, } blend_color: {color = {1, 1, 1, 1, }, } min_samples = 1 sample_mask = 0xffffffff framebuffer_state: {width = 1920, height = 1200, samples = 0, layers = 0, nr_cbufs = 1, cbufs = {0xdda9cd58, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, zsbuf = 0xdfab34b8, } cbufs[0]: surface: {format = PIPE_FORMAT_R16G16B16A16_FLOAT, width = 1920, height = 1200, texture = 0xdfab6898, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, } resource: {target = 2d, format = PIPE_FORMAT_R16G16B16A16_FLOAT, width0 = 1920, height0 = 1200, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 10, flags = 0, } zsbuf: surface: {format = PIPE_FORMAT_Z24_UNORM_S8_UINT, width = 1920, height = 1200, texture = 0xdfab1e40, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, } resource: {target = 2d, format = PIPE_FORMAT_Z24_UNORM_S8_UINT, width0 = 1920, height0 = 1200, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 1, flags = 0, } ***************************************************************************** Driver-specific state: SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 Vertex Shader as VS - main shader part - LLVM IR: ; ModuleID = 'tgsi' source_filename = "tgsi" target triple = "amdgcn--" define amdgpu_vs <{ float, float, float }> @main([17 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), [32 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) { main_body: %21 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 2, !amdgpu.uniform !0 %22 = load <16 x i8>, <16 x i8> addrspace(2)* %21, align 16, !invariant.load !0 %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0) %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4) %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8) %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 12) %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16) %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20) %29 = call float @llvm.SI.load.const(<16 x i8> %22, i32 24) %30 = call float @llvm.SI.load.const(<16 x i8> %22, i32 28) %31 = call float @llvm.SI.load.const(<16 x i8> %22, i32 32) %32 = call float @llvm.SI.load.const(<16 x i8> %22, i32 36) %33 = call float @llvm.SI.load.const(<16 x i8> %22, i32 40) %34 = call float @llvm.SI.load.const(<16 x i8> %22, i32 44) %35 = call float @llvm.SI.load.const(<16 x i8> %22, i32 48) %36 = call float @llvm.SI.load.const(<16 x i8> %22, i32 52) %37 = call float @llvm.SI.load.const(<16 x i8> %22, i32 56) %38 = call float @llvm.SI.load.const(<16 x i8> %22, i32 60) %39 = call float @llvm.SI.load.const(<16 x i8> %22, i32 64) %40 = call float @llvm.SI.load.const(<16 x i8> %22, i32 68) %41 = call float @llvm.SI.load.const(<16 x i8> %22, i32 72) %42 = call float @llvm.SI.load.const(<16 x i8> %22, i32 76) %43 = call float @llvm.SI.load.const(<16 x i8> %22, i32 80) %44 = call float @llvm.SI.load.const(<16 x i8> %22, i32 84) %45 = call float @llvm.SI.load.const(<16 x i8> %22, i32 88) %46 = call float @llvm.SI.load.const(<16 x i8> %22, i32 92) %47 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3696) %48 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3700) %49 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3704) %50 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3708) %51 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3712) %52 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3716) %53 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3720) %54 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3724) %55 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3728) %56 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3732) %57 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3736) %58 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3740) %59 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3744) %60 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3748) %61 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3752) %62 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3756) %63 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3760) %64 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3764) %65 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3768) %66 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3776) %67 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3780) %68 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3784) %69 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3792) %70 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3796) %71 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3800) %72 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3808) %73 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3812) %74 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3816) %75 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3824) %76 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3828) %77 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3832) %78 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3840) %79 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3844) %80 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3848) %81 = call float @llvm.SI.load.const(<16 x i8> %22, i32 3856) %82 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 4, !amdgpu.uniform !0 %83 = load <16 x i8>, <16 x i8> addrspace(2)* %82, align 16, !invariant.load !0 %84 = call float @llvm.SI.load.const(<16 x i8> %83, i32 8) %85 = call float @llvm.SI.load.const(<16 x i8> %83, i32 12) %86 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 0, !amdgpu.uniform !0 %87 = load <16 x i8>, <16 x i8> addrspace(2)* %86, align 16, !invariant.load !0 %88 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %87, i32 0, i32 %14) %89 = extractelement <4 x float> %88, i32 0 %90 = extractelement <4 x float> %88, i32 1 %91 = extractelement <4 x float> %88, i32 2 %92 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 1, !amdgpu.uniform !0 %93 = load <16 x i8>, <16 x i8> addrspace(2)* %92, align 16, !invariant.load !0 %94 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %93, i32 0, i32 %15) %95 = extractelement <4 x float> %94, i32 0 %96 = extractelement <4 x float> %94, i32 1 %97 = extractelement <4 x float> %94, i32 2 %98 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 2, !amdgpu.uniform !0 %99 = load <16 x i8>, <16 x i8> addrspace(2)* %98, align 16, !invariant.load !0 %100 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %99, i32 0, i32 %16) %101 = extractelement <4 x float> %100, i32 0 %102 = extractelement <4 x float> %100, i32 1 %103 = extractelement <4 x float> %100, i32 2 %104 = extractelement <4 x float> %100, i32 3 %105 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 3, !amdgpu.uniform !0 %106 = load <16 x i8>, <16 x i8> addrspace(2)* %105, align 16, !invariant.load !0 %107 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %106, i32 0, i32 %17) %108 = extractelement <4 x float> %107, i32 0 %109 = extractelement <4 x float> %107, i32 1 %110 = extractelement <4 x float> %107, i32 2 %111 = extractelement <4 x float> %107, i32 3 %112 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 4, !amdgpu.uniform !0 %113 = load <16 x i8>, <16 x i8> addrspace(2)* %112, align 16, !invariant.load !0 %114 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %113, i32 0, i32 %18) %115 = extractelement <4 x float> %114, i32 0 %116 = extractelement <4 x float> %114, i32 1 %117 = extractelement <4 x float> %114, i32 2 %118 = extractelement <4 x float> %114, i32 3 %119 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 5, !amdgpu.uniform !0 %120 = load <16 x i8>, <16 x i8> addrspace(2)* %119, align 16, !invariant.load !0 %121 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %120, i32 0, i32 %19) %122 = extractelement <4 x float> %121, i32 0 %123 = extractelement <4 x float> %121, i32 1 %124 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 6, !amdgpu.uniform !0 %125 = load <16 x i8>, <16 x i8> addrspace(2)* %124, align 16, !invariant.load !0 %126 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %125, i32 0, i32 %20) %127 = extractelement <4 x float> %126, i32 0 %128 = extractelement <4 x float> %126, i32 1 %129 = extractelement <4 x float> %126, i32 2 %130 = extractelement <4 x float> %126, i32 3 %131 = fmul float %89, %75 %132 = fadd float %131, %72 %133 = fmul float %90, %76 %134 = fadd float %133, %73 %135 = fmul float %91, %77 %136 = fadd float %135, %74 %137 = fmul float %43, %108 %138 = fmul float %43, %109 %139 = fmul float %43, %110 %140 = fmul float %43, %111 %141 = call float @llvm.rint.f32(float %137) %142 = call float @llvm.rint.f32(float %138) %143 = call float @llvm.rint.f32(float %139) %144 = call float @llvm.rint.f32(float %140) %145 = fptosi float %141 to i32 %146 = fptosi float %142 to i32 %147 = fptosi float %143 to i32 %148 = fptosi float %144 to i32 %149 = shl i32 %146, 4 %150 = add i32 %149, 112 %151 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %150) %152 = add i32 %149, 116 %153 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %152) %154 = add i32 %149, 120 %155 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %154) %156 = add i32 %149, 124 %157 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %156) %158 = fmul float %116, %151 %159 = fmul float %116, %153 %160 = fmul float %116, %155 %161 = fmul float %116, %157 %162 = shl i32 %145, 4 %163 = add i32 %162, 112 %164 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %163) %165 = add i32 %162, 116 %166 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %165) %167 = add i32 %162, 120 %168 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %167) %169 = add i32 %162, 124 %170 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %169) %171 = fmul float %115, %164 %172 = fadd float %171, %158 %173 = fmul float %115, %166 %174 = fadd float %173, %159 %175 = fmul float %115, %168 %176 = fadd float %175, %160 %177 = fmul float %115, %170 %178 = fadd float %177, %161 %179 = shl i32 %147, 4 %180 = add i32 %179, 112 %181 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %180) %182 = add i32 %179, 116 %183 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %182) %184 = add i32 %179, 120 %185 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %184) %186 = add i32 %179, 124 %187 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %186) %188 = fmul float %117, %181 %189 = fadd float %188, %172 %190 = fmul float %117, %183 %191 = fadd float %190, %174 %192 = fmul float %117, %185 %193 = fadd float %192, %176 %194 = fmul float %117, %187 %195 = fadd float %194, %178 %196 = shl i32 %148, 4 %197 = add i32 %196, 112 %198 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %197) %199 = add i32 %196, 116 %200 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %199) %201 = add i32 %196, 120 %202 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %201) %203 = add i32 %196, 124 %204 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %203) %205 = fmul float %118, %198 %206 = fadd float %205, %189 %207 = fmul float %118, %200 %208 = fadd float %207, %191 %209 = fmul float %118, %202 %210 = fadd float %209, %193 %211 = fmul float %118, %204 %212 = fadd float %211, %195 %213 = fmul float %132, %206 %214 = fmul float %134, %208 %215 = fadd float %213, %214 %216 = fmul float %136, %210 %217 = fadd float %215, %216 %218 = fmul float %46, %212 %219 = fadd float %217, %218 %220 = fmul float %219, %51 %221 = fmul float %219, %52 %222 = fmul float %219, %53 %223 = fmul float %219, %54 %224 = shl i32 %146, 4 %225 = add i32 %224, 96 %226 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %225) %227 = add i32 %224, 100 %228 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %227) %229 = add i32 %224, 104 %230 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %229) %231 = add i32 %224, 108 %232 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %231) %233 = fmul float %116, %226 %234 = fmul float %116, %228 %235 = fmul float %116, %230 %236 = fmul float %116, %232 %237 = shl i32 %145, 4 %238 = add i32 %237, 96 %239 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %238) %240 = add i32 %237, 100 %241 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %240) %242 = add i32 %237, 104 %243 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %242) %244 = add i32 %237, 108 %245 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %244) %246 = fmul float %115, %239 %247 = fadd float %246, %233 %248 = fmul float %115, %241 %249 = fadd float %248, %234 %250 = fmul float %115, %243 %251 = fadd float %250, %235 %252 = fmul float %115, %245 %253 = fadd float %252, %236 %254 = shl i32 %147, 4 %255 = add i32 %254, 96 %256 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %255) %257 = add i32 %254, 100 %258 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %257) %259 = add i32 %254, 104 %260 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %259) %261 = add i32 %254, 108 %262 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %261) %263 = fmul float %117, %256 %264 = fadd float %263, %247 %265 = fmul float %117, %258 %266 = fadd float %265, %249 %267 = fmul float %117, %260 %268 = fadd float %267, %251 %269 = fmul float %117, %262 %270 = fadd float %269, %253 %271 = shl i32 %148, 4 %272 = add i32 %271, 96 %273 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %272) %274 = add i32 %271, 100 %275 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %274) %276 = add i32 %271, 104 %277 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %276) %278 = add i32 %271, 108 %279 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %278) %280 = fmul float %118, %273 %281 = fadd float %280, %264 %282 = fmul float %118, %275 %283 = fadd float %282, %266 %284 = fmul float %118, %277 %285 = fadd float %284, %268 %286 = fmul float %118, %279 %287 = fadd float %286, %270 %288 = fmul float %132, %281 %289 = fmul float %134, %283 %290 = fadd float %288, %289 %291 = fmul float %136, %285 %292 = fadd float %290, %291 %293 = fmul float %46, %287 %294 = fadd float %292, %293 %295 = fmul float %47, %294 %296 = fadd float %295, %220 %297 = fmul float %48, %294 %298 = fadd float %297, %221 %299 = fmul float %49, %294 %300 = fadd float %299, %222 %301 = fmul float %50, %294 %302 = fadd float %301, %223 %303 = shl i32 %146, 4 %304 = add i32 %303, 128 %305 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %304) %306 = add i32 %303, 132 %307 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %306) %308 = add i32 %303, 136 %309 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %308) %310 = add i32 %303, 140 %311 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %310) %312 = fmul float %116, %305 %313 = fmul float %116, %307 %314 = fmul float %116, %309 %315 = fmul float %116, %311 %316 = shl i32 %145, 4 %317 = add i32 %316, 128 %318 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %317) %319 = add i32 %316, 132 %320 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %319) %321 = add i32 %316, 136 %322 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %321) %323 = add i32 %316, 140 %324 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %323) %325 = fmul float %115, %318 %326 = fadd float %325, %312 %327 = fmul float %115, %320 %328 = fadd float %327, %313 %329 = fmul float %115, %322 %330 = fadd float %329, %314 %331 = fmul float %115, %324 %332 = fadd float %331, %315 %333 = shl i32 %147, 4 %334 = add i32 %333, 128 %335 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %334) %336 = add i32 %333, 132 %337 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %336) %338 = add i32 %333, 136 %339 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %338) %340 = add i32 %333, 140 %341 = call float @llvm.SI.load.const(<16 x i8> %22, i32 %340) %342 = fmul float %117, %335 %343 = fadd float %342, %326 %344 = fmul float %117, %337 %345 = fadd float %344, %328 %346 = fmul float %117, %339 %347 = fadd float %346, %330 %348 = fmul float %117, %341 %349 = fadd float %348, %332 %350 = shl i32 %148, 4 %351 = add i32 %350 Memory-mapped registers: GRBM_STATUS <- ME0PIPE0_CMDFIFO_AVAIL = 8 SRBM_RQ_PENDING = 1 ME0PIPE0_CF_RQ_PENDING = 0 ME0PIPE0_PF_RQ_PENDING = 0 GDS_DMA_RQ_PENDING = 0 DB_CLEAN = 0 CB_CLEAN = 0 TA_BUSY = 0 GDS_BUSY = 0 WD_BUSY_NO_DMA = 0 VGT_BUSY = 0 IA_BUSY_NO_DMA = 0 IA_BUSY = 0 SX_BUSY = 0 WD_BUSY = 0 SPI_BUSY = 1 BCI_BUSY = 0 SC_BUSY = 0 PA_BUSY = 0 DB_BUSY = 1 CP_COHERENCY_BUSY = 0 CP_BUSY = 1 CB_BUSY = 1 GUI_ACTIVE = 1 GRBM_STATUS2 <- ME0PIPE1_CMDFIFO_AVAIL = 8 ME0PIPE1_CF_RQ_PENDING = 0 ME0PIPE1_PF_RQ_PENDING = 0 ME1PIPE0_RQ_PENDING = 0 ME1PIPE1_RQ_PENDING = 0 ME1PIPE2_RQ_PENDING = 0 ME1PIPE3_RQ_PENDING = 0 ME2PIPE0_RQ_PENDING = 0 ME2PIPE1_RQ_PENDING = 0 ME2PIPE2_RQ_PENDING = 0 ME2PIPE3_RQ_PENDING = 0 RLC_RQ_PENDING = 0 RLC_BUSY = 0 TC_BUSY = 0 TCC_CC_RESIDENT = 0 CPF_BUSY = 1 CPC_BUSY = 0 CPG_BUSY = 1 GRBM_STATUS_SE0 <- DB_CLEAN = 0 CB_CLEAN = 0 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 0 SC_BUSY = 0 DB_BUSY = 0 CB_BUSY = 0 GRBM_STATUS_SE1 <- DB_CLEAN = 0 CB_CLEAN = 0 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 1 SC_BUSY = 0 DB_BUSY = 1 CB_BUSY = 1 GRBM_STATUS_SE2 <- DB_CLEAN = 0 CB_CLEAN = 0 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 1 SC_BUSY = 0 DB_BUSY = 1 CB_BUSY = 1 GRBM_STATUS_SE3 <- DB_CLEAN = 0 CB_CLEAN = 0 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 1 SC_BUSY = 0 DB_BUSY = 1 CB_BUSY = 1 SDMA0_STATUS_REG <- IDLE = 1 REG_IDLE = 1 RB_EMPTY = 1 RB_FULL = 0 RB_CMD_IDLE = 1 RB_CMD_FULL = 0 IB_CMD_IDLE = 1 IB_CMD_FULL = 0 BLOCK_IDLE = 1 INSIDE_IB = 0 EX_IDLE = 1 EX_IDLE_POLL_TIMER_EXPIRE = 1 PACKET_READY = 0 MC_WR_IDLE = 1 SRBM_IDLE = 1 CONTEXT_EMPTY = 1 DELTA_RPTR_FULL = 0 RB_MC_RREQ_IDLE = 1 IB_MC_RREQ_IDLE = 1 MC_RD_IDLE = 1 DELTA_RPTR_EMPTY = 1 MC_RD_RET_STALL = 0 MC_RD_NO_POLL_IDLE = 1 PREV_CMD_IDLE = 1 SEM_IDLE = 1 SEM_REQ_STALL = 0 SEM_RESP_STATE = 0 INT_IDLE = 1 INT_REQ_STALL = 0 SDMA1_STATUS_REG <- IDLE = 1 REG_IDLE = 1 RB_EMPTY = 1 RB_FULL = 0 RB_CMD_IDLE = 1 RB_CMD_FULL = 0 IB_CMD_IDLE = 1 IB_CMD_FULL = 0 BLOCK_IDLE = 1 INSIDE_IB = 0 EX_IDLE = 1 EX_IDLE_POLL_TIMER_EXPIRE = 1 PACKET_READY = 0 MC_WR_IDLE = 1 SRBM_IDLE = 1 CONTEXT_EMPTY = 1 DELTA_RPTR_FULL = 0 RB_MC_RREQ_IDLE = 1 IB_MC_RREQ_IDLE = 1 MC_RD_IDLE = 1 DELTA_RPTR_EMPTY = 1 MC_RD_RET_STALL = 0 MC_RD_NO_POLL_IDLE = 1 PREV_CMD_IDLE = 1 SEM_IDLE = 1 SEM_REQ_STALL = 0 SEM_RESP_STATE = 0 INT_IDLE = 1 INT_REQ_STALL = 0 SRBM_STATUS <- UVD_RQ_PENDING = 0 SAMMSP_RQ_PENDING = 0 ACP_RQ_PENDING = 0 SMU_RQ_PENDING = 0 GRBM_RQ_PENDING = 0 HI_RQ_PENDING = 1 VMC_BUSY = 0 MCB_BUSY = 1 MCB_NON_DISPLAY_BUSY = 0 MCC_BUSY = 1 MCD_BUSY = 0 VMC1_BUSY = 0 SEM_BUSY = 0 ACP_BUSY = 0 IH_BUSY = 0 UVD_BUSY = 0 SAMMSP_BUSY = 0 GCATCL2_BUSY = 0 OSATCL2_BUSY = 0 BIF_BUSY = 1 SRBM_STATUS2 <- SDMA_RQ_PENDING = 0 TST_RQ_PENDING = 0 SDMA1_RQ_PENDING = 0 VCE0_RQ_PENDING = 0 VP8_BUSY = 0 SDMA_BUSY = 0 SDMA1_BUSY = 0 VCE0_BUSY = 1 XDMA_BUSY = 0 CHUB_BUSY = 0 SDMA2_BUSY = 0 SDMA3_BUSY = 0 SAMSCP_BUSY = 0 ISP_BUSY = 0 VCE1_BUSY = 0 ODE_BUSY = 0 SDMA2_RQ_PENDING = 0 SDMA3_RQ_PENDING = 0 SAMSCP_RQ_PENDING = 0 ISP_RQ_PENDING = 0 VCE1_RQ_PENDING = 0 SRBM_STATUS3 <- MCC0_BUSY = 0 MCC1_BUSY = 0 MCC2_BUSY = 0 MCC3_BUSY = 0 MCC4_BUSY = 0 MCC5_BUSY = 0 MCC6_BUSY = 0 MCC7_BUSY = 0 MCD0_BUSY = 0 MCD1_BUSY = 0 MCD2_BUSY = 0 MCD3_BUSY = 0 MCD4_BUSY = 0 MCD5_BUSY = 0 MCD6_BUSY = 0 MCD7_BUSY = 0 CP_STAT <- ROQ_RING_BUSY = 1 ROQ_INDIRECT1_BUSY = 1 ROQ_INDIRECT2_BUSY = 0 ROQ_STATE_BUSY = 0 DC_BUSY = 0 ATCL2IU_BUSY = 0 PFP_BUSY = 1 MEQ_BUSY = 1 ME_BUSY = 1 QUERY_BUSY = 0 SEMAPHORE_BUSY = 0 INTERRUPT_BUSY = 0 SURFACE_SYNC_BUSY = 0 DMA_BUSY = 0 RCIU_BUSY = 0 SCRATCH_RAM_BUSY = 0 CPC_CPG_BUSY = 0 CE_BUSY = 0 TCIU_BUSY = 0 ROQ_CE_RING_BUSY = 0 ROQ_CE_INDIRECT1_BUSY = 0 ROQ_CE_INDIRECT2_BUSY = 0 CP_BUSY = 1 CP_STALLED_STAT1 <- RBIU_TO_DMA_NOT_RDY_TO_RCV = 0 RBIU_TO_SEM_NOT_RDY_TO_RCV = 0 RBIU_TO_MEMWR_NOT_RDY_TO_RCV = 0 ME_HAS_ACTIVE_CE_BUFFER_FLAG = 1 ME_HAS_ACTIVE_DE_BUFFER_FLAG = 1 ME_STALLED_ON_TC_WR_CONFIRM = 0 ME_STALLED_ON_ATOMIC_RTN_DATA = 0 ME_WAITING_ON_TC_READ_DATA = 0 ME_WAITING_ON_REG_READ_DATA = 0 RCIU_WAITING_ON_GDS_FREE = 0 RCIU_WAITING_ON_GRBM_FREE = 0 RCIU_WAITING_ON_VGT_FREE = 0 RCIU_STALLED_ON_ME_READ = 0 RCIU_STALLED_ON_DMA_READ = 0 RCIU_STALLED_ON_APPEND_READ = 0 RCIU_HALTED_BY_REG_VIOLATION = 0 CP_STALLED_STAT2 <- PFP_TO_CSF_NOT_RDY_TO_RCV = 0 PFP_TO_MEQ_NOT_RDY_TO_RCV = 0 PFP_TO_RCIU_NOT_RDY_TO_RCV = 0 PFP_TO_VGT_WRITES_PENDING = 0 PFP_RCIU_READ_PENDING = 0 PFP_WAITING_ON_BUFFER_DATA = 0 ME_WAIT_ON_CE_COUNTER = 0 ME_WAIT_ON_AVAIL_BUFFER = 0 GFX_CNTX_NOT_AVAIL_TO_ME = 0 ME_RCIU_NOT_RDY_TO_RCV = 0 ME_TO_CONST_NOT_RDY_TO_RCV = 0 ME_WAITING_DATA_FROM_PFP = 0 ME_WAITING_ON_PARTIAL_FLUSH = 1 MEQ_TO_ME_NOT_RDY_TO_RCV = 1 STQ_TO_ME_NOT_RDY_TO_RCV = 0 ME_WAITING_DATA_FROM_STQ = 0 PFP_STALLED_ON_TC_WR_CONFIRM = 0 PFP_STALLED_ON_ATOMIC_RTN_DATA = 0 EOPD_FIFO_NEEDS_SC_EOP_DONE = 0 EOPD_FIFO_NEEDS_WR_CONFIRM = 0 STRMO_WR_OF_PRIM_DATA_PENDING = 0 PIPE_STATS_WR_DATA_PENDING = 0 APPEND_RDY_WAIT_ON_CS_DONE = 0 APPEND_RDY_WAIT_ON_PS_DONE = 0 APPEND_WAIT_ON_WR_CONFIRM = 0 APPEND_ACTIVE_PARTITION = 0 APPEND_WAITING_TO_SEND_MEMWRITE = 0 SURF_SYNC_NEEDS_IDLE_CNTXS = 0 SURF_SYNC_NEEDS_ALL_CLEAN = 0 CP_STALLED_STAT3 <- CE_TO_CSF_NOT_RDY_TO_RCV = 0 CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV = 0 CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER = 0 CE_TO_RAM_INIT_NOT_RDY = 0 CE_TO_RAM_DUMP_NOT_RDY = 0 CE_TO_RAM_WRITE_NOT_RDY = 0 CE_TO_INC_FIFO_NOT_RDY_TO_RCV = 0 CE_TO_WR_FIFO_NOT_RDY_TO_RCV = 0 CE_WAITING_ON_BUFFER_DATA = 0 CE_WAITING_ON_CE_BUFFER_FLAG = 0 CE_WAITING_ON_DE_COUNTER = 0 CE_WAITING_ON_DE_COUNTER_UNDERFLOW = 0 TCIU_WAITING_ON_FREE = 0 TCIU_WAITING_ON_TAGS = 0 CE_STALLED_ON_TC_WR_CONFIRM = 0 CE_STALLED_ON_ATOMIC_RTN_DATA = 0 ATCL2IU_WAITING_ON_FREE = 0 ATCL2IU_WAITING_ON_TAGS = 0 ATCL1_WAITING_ON_TRANS = 0 CP_CPC_STATUS <- MEC1_BUSY = 0 MEC2_BUSY = 0 DC0_BUSY = 0 DC1_BUSY = 0 RCIU1_BUSY = 0 RCIU2_BUSY = 0 ROQ1_BUSY = 0 ROQ2_BUSY = 0 TCIU_BUSY = 0 SCRATCH_RAM_BUSY = 0 QU_BUSY = 0 ATCL2IU_BUSY = 0 CPG_CPC_BUSY = 0 CPF_CPC_BUSY = 0 CPC_BUSY = 0 CP_CPC_BUSY_STAT <- MEC1_LOAD_BUSY = 0 MEC1_SEMAPOHRE_BUSY = 0 MEC1_MUTEX_BUSY = 0 MEC1_MESSAGE_BUSY = 0 MEC1_EOP_QUEUE_BUSY = 0 MEC1_IQ_QUEUE_BUSY = 0 MEC1_IB_QUEUE_BUSY = 0 MEC1_TC_BUSY = 0 MEC1_DMA_BUSY = 0 MEC1_PARTIAL_FLUSH_BUSY = 0 MEC1_PIPE0_BUSY = 0 MEC1_PIPE1_BUSY = 0 MEC1_PIPE2_BUSY = 0 MEC1_PIPE3_BUSY = 0 MEC2_LOAD_BUSY = 0 MEC2_SEMAPOHRE_BUSY = 0 MEC2_MUTEX_BUSY = 0 MEC2_MESSAGE_BUSY = 0 MEC2_EOP_QUEUE_BUSY = 0 MEC2_IQ_QUEUE_BUSY = 0 MEC2_IB_QUEUE_BUSY = 0 MEC2_TC_BUSY = 0 MEC2_DMA_BUSY = 0 MEC2_PARTIAL_FLUSH_BUSY = 0 MEC2_PIPE0_BUSY = 0 MEC2_PIPE1_BUSY = 0 MEC2_PIPE2_BUSY = 0 MEC2_PIPE3_BUSY = 0 CP_CPC_STALLED_STAT1 <- RCIU_TX_FREE_STALL = 0 RCIU_PRIV_VIOLATION = 0 TCIU_TX_FREE_STALL = 0 MEC1_DECODING_PACKET = 0 MEC1_WAIT_ON_RCIU = 0 MEC1_WAIT_ON_RCIU_READ = 0 MEC1_WAIT_ON_ROQ_DATA = 0 MEC2_DECODING_PACKET = 0 MEC2_WAIT_ON_RCIU = 0 MEC2_WAIT_ON_RCIU_READ = 0 MEC2_WAIT_ON_ROQ_DATA = 0 ATCL2IU_WAITING_ON_FREE = 0 ATCL2IU_WAITING_ON_TAGS = 0 ATCL1_WAITING_ON_TRANS = 0 CP_CPF_STATUS <- POST_WPTR_GFX_BUSY = 1 CSF_BUSY = 1 ROQ_ALIGN_BUSY = 0 ROQ_RING_BUSY = 1 ROQ_INDIRECT1_BUSY = 1 ROQ_INDIRECT2_BUSY = 0 ROQ_STATE_BUSY = 0 ROQ_CE_RING_BUSY = 0 ROQ_CE_INDIRECT1_BUSY = 0 ROQ_CE_INDIRECT2_BUSY = 0 SEMAPHORE_BUSY = 0 INTERRUPT_BUSY = 0 TCIU_BUSY = 0 HQD_BUSY = 0 PRT_BUSY = 0 ATCL2IU_BUSY = 0 CPF_GFX_BUSY = 1 CPF_CMP_BUSY = 0 GRBM_CPF_STAT_BUSY = 3 CPC_CPF_BUSY = 0 CPF_BUSY = 1 CP_CPF_BUSY_STAT <- REG_BUS_FIFO_BUSY = 0 CSF_RING_BUSY = 1 CSF_INDIRECT1_BUSY = 1 CSF_INDIRECT2_BUSY = 0 CSF_STATE_BUSY = 0 CSF_CE_INDR1_BUSY = 0 CSF_CE_INDR2_BUSY = 0 CSF_ARBITER_BUSY = 0 CSF_INPUT_BUSY = 0 OUTSTANDING_READ_TAGS = 0 HPD_PROCESSING_EOP_BUSY = 0 HQD_DISPATCH_BUSY = 0 HQD_IQ_TIMER_BUSY = 0 HQD_DMA_OFFLOAD_BUSY = 0 HQD_WAIT_SEMAPHORE_BUSY = 0 HQD_SIGNAL_SEMAPHORE_BUSY = 0 HQD_MESSAGE_BUSY = 0 HQD_PQ_FETCHER_BUSY = 0 HQD_IB_FETCHER_BUSY = 0 HQD_IQ_FETCHER_BUSY = 0 HQD_EOP_FETCHER_BUSY = 0 HQD_CONSUMED_RPTR_BUSY = 0 HQD_FETCHER_ARB_BUSY = 0 HQD_ROQ_ALIGN_BUSY = 0 HQD_ROQ_EOP_BUSY = 0 HQD_ROQ_IQ_BUSY = 0 HQD_ROQ_PQ_BUSY = 0 HQD_ROQ_IB_BUSY = 0 HQD_WPTR_POLL_BUSY = 0 HQD_PQ_BUSY = 0 HQD_IB_BUSY = 0 CP_CPF_STALLED_STAT1 <- RING_FETCHING_DATA = 0 INDR1_FETCHING_DATA = 1 INDR2_FETCHING_DATA = 0 STATE_FETCHING_DATA = 0 TCIU_WAITING_ON_FREE = 0 TCIU_WAITING_ON_TAGS = 0 ATCL2IU_WAITING_ON_FREE = 0 ATCL2IU_WAITING_ON_TAGS = 0 ATCL1_WAITING_ON_TRANS = 0 Last 60 lines of dmesg: [ 2.914056] amdgpu 0000:01:00.0: fence driver on ring 9 use gpu addr 0x00000001000000bc, cpu addr 0xffff88081624b0bc [ 2.914097] amdgpu 0000:01:00.0: fence driver on ring 10 use gpu addr 0x00000001000000d0, cpu addr 0xffff88081624b0d0 [ 2.916249] [drm] Found UVD firmware Version: 1.52 Family ID: 10 [ 2.917470] amdgpu 0000:01:00.0: fence driver on ring 11 use gpu addr 0x00000000008907b0, cpu addr 0xffffc9000524e7b0 [ 2.918477] [drm] Found VCE firmware Version: 50.17 Binary ID: 3 [ 2.918585] amdgpu 0000:01:00.0: fence driver on ring 12 use gpu addr 0x00000001000000f8, cpu addr 0xffff88081624b0f8 [ 2.918616] amdgpu 0000:01:00.0: fence driver on ring 13 use gpu addr 0x000000010000010c, cpu addr 0xffff88081624b10c [ 2.941189] kvm: Nested Virtualization enabled [ 2.941192] kvm: Nested Paging enabled [ 3.039370] [drm] ring test on 0 succeeded in 11 usecs [ 3.039579] [drm] ring test on 1 succeeded in 26 usecs [ 3.039613] [drm] ring test on 2 succeeded in 16 usecs [ 3.039623] [drm] ring test on 3 succeeded in 4 usecs [ 3.039628] [drm] ring test on 4 succeeded in 2 usecs [ 3.039636] [drm] ring test on 5 succeeded in 3 usecs [ 3.039644] [drm] ring test on 6 succeeded in 3 usecs [ 3.039651] [drm] ring test on 7 succeeded in 3 usecs [ 3.039659] [drm] ring test on 8 succeeded in 3 usecs [ 3.039700] [drm] ring test on 9 succeeded in 5 usecs [ 3.039706] [drm] ring test on 10 succeeded in 5 usecs [ 3.085761] [drm] ring test on 11 succeeded in 2 usecs [ 3.105783] [drm] UVD initialized successfully. [ 3.105798] clocksource: Switched to clocksource tsc [ 3.110276] usbcore: registered new interface driver snd-usb-audio [ 3.325872] [drm] ring test on 12 succeeded in 18 usecs [ 3.325885] [drm] ring test on 13 succeeded in 4 usecs [ 3.325886] [drm] VCE initialized successfully. [ 3.480436] EXT4-fs (sda2): re-mounted. Opts: discard [ 3.516376] [drm] fb mappable at 0xC0A9A000 [ 3.516378] [drm] vram apper at 0xC0000000 [ 3.516379] [drm] size 9216000 [ 3.516380] [drm] fb depth is 24 [ 3.516381] [drm] pitch is 7680 [ 3.516489] fbcon: amdgpudrmfb (fb0) is primary device [ 3.775070] Console: switching to colour frame buffer device 240x75 [ 3.779180] amdgpu 0000:01:00.0: fb0: amdgpudrmfb frame buffer device [ 3.786134] [drm] ib test on ring 0 succeeded in 0 usecs [ 3.786215] [drm] ib test on ring 1 succeeded in 0 usecs [ 3.786238] [drm] ib test on ring 2 succeeded in 0 usecs [ 3.786266] [drm] ib test on ring 3 succeeded in 0 usecs [ 3.786289] [drm] ib test on ring 4 succeeded in 0 usecs [ 3.786315] [drm] ib test on ring 5 succeeded in 0 usecs [ 3.786336] [drm] ib test on ring 6 succeeded in 0 usecs [ 3.786355] [drm] ib test on ring 7 succeeded in 0 usecs [ 3.786376] [drm] ib test on ring 8 succeeded in 0 usecs [ 3.786397] [drm] ib test on ring 9 succeeded in 0 usecs [ 3.786415] [drm] ib test on ring 10 succeeded in 0 usecs [ 3.807365] [drm] ib test on ring 11 succeeded [ 3.827499] [drm] ib test on ring 12 succeeded [ 3.829084] [drm] Initialized amdgpu 3.2.0 20150101 for 0000:01:00.0 on minor 0 [ 4.662540] EXT4-fs (sdc1): recovery complete [ 4.688596] EXT4-fs (sdc1): mounted filesystem with ordered data mode. Opts: (null) [ 5.549838] r8169 0000:02:00.0 eth0: link down [ 5.549888] r8169 0000:02:00.0 eth0: link down [ 5.549889] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready [ 6.523032] it87: Found IT8721F chip at 0x290, revision 3 [ 8.042353] r8169 0000:02:00.0 eth0: link up [ 8.042364] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready [ 5234.990282] E.d3d9.OpenGL[3729]: segfault at 0 ip 00000000f6f92959 sp 00000000e77ff208 error 6 in libc-2.23.so[f6e72000+1a3000] [12248.682752] kactivitymanage[2550]: segfault at 7f7b30037c50 ip 00007f7b28447071 sp 00007ffe5b856b58 error 4 in libQt5Sql.so.5.6.1[7f7b28432000+42000]