Command: ./specops.i386 Driver vendor: X.Org Device vendor: AMD Device name: AMD TONGA (DRM 3.2.0 / 4.7.0-gentoo, LLVM 4.0.0) Draw call sequence # = 18028853 HW reached sequence # = 18028852 Elapsed time = 10003 ms draw_info: {indexed = 1, mode = triangles, start = 0, count = 540, start_instance = 0, instance_count = 1, vertices_per_patch = 3, index_bias = 0, min_index = 0, max_index = 165, primitive_restart = 0, restart_index = 0, count_from_stream_output = NULL, indirect = NULL, indirect_offset = 0, } index_buffer: {index_size = 2, offset = 0, buffer = 0xbc56f130, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 1080, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 32, flags = 0, } vertex_buffer 0: {stride = 12, buffer_offset = 0, buffer = 0x87151a88, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 1980, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 16, flags = 0, } vertex_buffer 1: {stride = 16, buffer_offset = 0, buffer = 0xa0024ff8, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 2640, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 16, flags = 0, } vertex_buffer 2: {stride = 16, buffer_offset = 4, buffer = 0xa0024ff8, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 2640, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 16, flags = 0, } vertex_buffer 3: {stride = 16, buffer_offset = 8, buffer = 0xa0024ff8, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 2640, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 16, flags = 0, } vertex_buffer 4: {stride = 16, buffer_offset = 12, buffer = 0xa0024ff8, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 2640, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 16, flags = 0, } num vertex elements = 5 vertex_element 0: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_FLOAT, } vertex_element 1: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 1, src_format = PIPE_FORMAT_R8G8B8A8_USCALED, } vertex_element 2: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 2, src_format = PIPE_FORMAT_R8G8B8A8_USCALED, } vertex_element 3: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 3, src_format = PIPE_FORMAT_R16G16_FLOAT, } vertex_element 4: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 4, src_format = PIPE_FORMAT_R16G16_FLOAT, } num stream output targets = 0 begin shader: VERTEX shader_state: {tokens = " VERT PROPERTY NEXT_SHADER FRAG DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL OUT[0], POSITION DCL OUT[1..10], ARRAY(1), GENERIC[0] DCL CONST[1][0..31] DCL CONST[2][0..255] DCL CONST[3][0..31] DCL CONST[4][0..8] DCL TEMP[0..9], ARRAY(1), LOCAL DCL TEMP[10..19], LOCAL IMM[0] FLT32 { 0.0000, 0.0078, -1.0000, 1.0000} IMM[1] UINT32 {1, 224, 208, 112} IMM[2] UINT32 {96, 128, 144, 64} IMM[3] UINT32 {176, 160, 192, 16} IMM[4] UINT32 {0, 32, 48, 3} IMM[5] FLT32 { 2.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0], IMM[0].xxxx 1: MOV TEMP[1], IMM[0].xxxx 2: MOV TEMP[2], IMM[0].xxxx 3: MOV TEMP[3], IMM[0].xxxx 4: MOV TEMP[4], IMM[0].xxxx 5: MOV TEMP[5], IMM[0].xxxx 6: MOV TEMP[6], IMM[0].xxxx 7: MOV TEMP[7], IMM[0].xxxx 8: MOV TEMP[8], IMM[0].xxxx 9: MOV TEMP[9], IMM[0].xxxx 10: MAD TEMP[10].xy, IN[4].xyyy, CONST[2][14].xyyy, CONST[2][14].wzzz 11: MAD TEMP[11], IN[2], IMM[0].yyyy, IMM[0].zzzz 12: MUL TEMP[12].x, TEMP[11].wwww, CONST[2][13].xxxx 13: MOV TEMP[12].w, TEMP[12].xxxx 14: MUL TEMP[13], CONST[2][7], IN[0].yyyy 15: MAD TEMP[13], CONST[2][6], IN[0].xxxx, TEMP[13] 16: MAD TEMP[13], CONST[2][8], IN[0].zzzz, TEMP[13] 17: MAD TEMP[13], CONST[2][9], IN[0].wwww, TEMP[13] 18: MAD TEMP[14].xyz, TEMP[13].xyzz, -CONST[2][4].wwww, CONST[2][4].xyzz 19: MUL TEMP[15].xyz, TEMP[14].yyyy, CONST[2][11].xyzz 20: MAD TEMP[16].xyz, CONST[2][10].xyzz, TEMP[14].xxxx, TEMP[15].xyzz 21: MAD TEMP[14].xyz, CONST[2][12].xyzz, TEMP[14].zzzz, TEMP[16].xyzz 22: MAD TEMP[15].xyz, IN[1].yzxx, IMM[0].yyyy, IMM[0].zzzz 23: MUL TEMP[16].xyz, TEMP[11].zxyy, TEMP[15].xyzz 24: MAD TEMP[15].xyz, TEMP[11].yzxx, TEMP[15].yzxx, -TEMP[16].xyzz 25: MUL TEMP[15].xyz, TEMP[11].wwww, TEMP[15].xyzz 26: MUL TEMP[16].xyz, TEMP[11].yzxx, TEMP[15].zxyy 27: MAD TEMP[16].xyz, TEMP[15].yzxx, TEMP[11].zxyy, -TEMP[16].xyzz 28: MUL TEMP[16].xyz, TEMP[11].wwww, TEMP[16].xyzz 29: DP3 TEMP[17].x, TEMP[16].xyzz, TEMP[14].xyzz 30: DP3 TEMP[18].x, TEMP[15].xyzz, TEMP[14].xyzz 31: MOV TEMP[17].y, TEMP[18].xxxx 32: DP3 TEMP[18].x, TEMP[11].xyzz, TEMP[14].xyzz 33: MOV TEMP[17].z, TEMP[18].xxxx 34: DP3 TEMP[18].x, TEMP[16].xyzz, CONST[2][12].xyzz 35: DP3 TEMP[19].x, TEMP[15].xyzz, CONST[2][12].xyzz 36: MOV TEMP[18].y, TEMP[19].xxxx 37: DP3 TEMP[19].x, TEMP[11].xyzz, CONST[2][12].xyzz 38: MOV TEMP[18].z, TEMP[19].xxxx 39: MUL TEMP[19].xy, TEMP[11].yyyy, CONST[2][7].xzzz 40: MAD TEMP[11].xy, CONST[2][6].xzzz, TEMP[11].xxxx, TEMP[19].xyyy 41: MAD TEMP[19].xy, CONST[2][8].zxxx, TEMP[11].zzzz, TEMP[11].yxxx 42: MOV TEMP[11].w, TEMP[19].xxxy 43: MOV TEMP[12].z, TEMP[19].xxxx 44: MUL TEMP[14].xy, TEMP[15].yyyy, CONST[2][7].xzzz 45: MAD TEMP[14].xy, CONST[2][6].xzzz, TEMP[15].xxxx, TEMP[14].xyyy 46: MAD TEMP[15].xy, CONST[2][8].zxxx, TEMP[15].zzzz, TEMP[14].yxxx 47: MOV TEMP[11].z, TEMP[15].xxyx 48: MOV TEMP[12].y, TEMP[15].xxxx 49: MUL TEMP[14].xy, TEMP[16].yyyy, CONST[2][7].xzzz 50: MAD TEMP[14].xy, CONST[2][6].xzzz, TEMP[16].xxxx, TEMP[14].xyyy 51: MAD TEMP[11].xy, CONST[2][8].xzzz, TEMP[16].zzzz, TEMP[14].xyyy 52: MOV TEMP[14].xyz, TEMP[11].xzwx 53: MOV TEMP[12].x, TEMP[11].yyyy 54: MUL TEMP[11], TEMP[13].yyyy, CONST[2][1] 55: MAD TEMP[11], CONST[2][0], TEMP[13].xxxx, TEMP[11] 56: MAD TEMP[11], CONST[2][2], TEMP[13].zzzz, TEMP[11] 57: MAD TEMP[11], CONST[2][3], TEMP[13].wwww, TEMP[11] 58: MOV TEMP[17].w, IMM[0].wwww 59: MOV TEMP[2].xyz, TEMP[14].xyzx 60: MOV TEMP[3], TEMP[12] 61: MOV TEMP[0].xy, TEMP[10].xyxx 62: MUL TEMP[1], IMM[0].wwxx, IN[3].xyxx 63: MOV TEMP[5], TEMP[11] 64: MOV TEMP[6], TEMP[17] 65: MOV TEMP[7].xyz, TEMP[18].xyzx 66: MOV TEMP[10].xw, TEMP[11].xxzw 67: MOV TEMP[10].y, -TEMP[11].yyyy 68: MAD TEMP[10].xy, TEMP[11].wwww, CONST[4][0].zwww, TEMP[10].xyyy 69: MAD TEMP[11].x, TEMP[11].zzzz, IMM[5].xxxx, -TEMP[11].wwww 70: MOV TEMP[10].z, TEMP[11].xxxx 71: MOV OUT[0], TEMP[10] 72: MOV OUT[1], TEMP[0] 73: MOV OUT[2], TEMP[1] 74: MOV OUT[3], TEMP[2] 75: MOV OUT[4], TEMP[3] 76: MOV OUT[5], TEMP[4] 77: MOV OUT[6], TEMP[5] 78: MOV OUT[7], TEMP[6] 79: MOV OUT[8], TEMP[7] 80: MOV OUT[9], TEMP[8] 81: MOV OUT[10], TEMP[9] 82: END ", } constant_buffer 1: {buffer = 0xeb17e900, buffer_offset = 0, buffer_size = 256, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 258048, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 2: {buffer = 0xeb17e510, buffer_offset = 2682880, buffer_size = 4096, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 4096000, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 3: {buffer = 0xeb17ecf0, buffer_offset = 0, buffer_size = 64, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 65536, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 4: {buffer = 0xb39dc648, buffer_offset = 78048, buffer_size = 144, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 147456, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } end shader: VERTEX viewport_state 0: {scale = {960, 540, 0.5, }, translate = {960, 540, 0.5, }, } rasterizer_state: {flatshade = 0, light_twoside = 0, clamp_vertex_color = 0, clamp_fragment_color = 0, front_ccw = 1, cull_face = 1, fill_front = 0, fill_back = 0, offset_point = 0, offset_line = 0, offset_tri = 0, scissor = 0, poly_smooth = 0, poly_stipple_enable = 0, point_smooth = 0, sprite_coord_enable = 0, sprite_coord_mode = 1, point_quad_rasterization = 1, point_tri_clip = 0, point_size_per_vertex = 0, multisample = 0, line_smooth = 0, line_stipple_enable = 0, line_stipple_factor = 0, line_stipple_pattern = 65535, line_last_pixel = 0, flatshade_first = 0, half_pixel_center = 1, bottom_edge_rule = 0, rasterizer_discard = 0, depth_clip = 1, clip_halfz = 0, clip_plane_enable = 0, line_width = 1, point_size = 1, offset_units = 0, offset_scale = 0, offset_clamp = 0, } begin shader: FRAGMENT shader_state: {tokens = " FRAG DCL IN[0..6], ARRAY(1), GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL OUT[1], COLOR[1] DCL OUT[2], COLOR[2] DCL OUT[3], COLOR[3] DCL OUT[4], COLOR[4] DCL OUT[5], COLOR[5] DCL OUT[6], COLOR[6] DCL OUT[7], COLOR[7] DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SAMP[5] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], 2D, FLOAT DCL SVIEW[3], 2D, FLOAT DCL SVIEW[4], 2D, FLOAT DCL SVIEW[5], CUBE, FLOAT DCL CONST[1][0..15] DCL CONST[2][0..8] DCL CONST[3][0..1] DCL CONST[4][0..223] DCL CONST[5][0..15] DCL TEMP[0..8], LOCAL DCL TEMP[9..16], ARRAY(1), LOCAL IMM[0] UINT32 {3, 160, 224, 208} IMM[1] UINT32 {96, 112, 176, 128} IMM[2] FLT32 { 2.0000, -1.0000, 1.0000, 0.0000} IMM[3] FLT32 { 0.3000, 0.5900, 0.1100, -0.4082} IMM[4] UINT32 {144, 0, 64, 80} IMM[5] FLT32 { 0.8165, 0.5774, -0.7071, -0.4082} IMM[6] FLT32 { -0.4082, 0.5774, 0.7071, 0.0000} IMM[7] UINT32 {192, 240, 32, 0} 0: MUL TEMP[0].xy, CONST[4][10].xyyy, IN[1].xyyy 1: MOV TEMP[1].xy, TEMP[0].xyyy 2: TEX TEMP[1].x, TEMP[1], SAMP[4], 2D 3: MOV_SAT TEMP[1].x, TEMP[1].xxxx 4: ADD TEMP[2].x, -CONST[4][14].xxxx, CONST[4][13].wwww 5: MAD TEMP[0].x, TEMP[1].xxxx, TEMP[2].xxxx, CONST[4][14].xxxx 6: DP3 TEMP[2].x, IN[3].xyzz, IN[3].xyzz 7: RSQ TEMP[2].x, TEMP[2].xxxx 8: MUL TEMP[2].xyz, IN[3].xyzz, TEMP[2].xxxx 9: DP3 TEMP[3].x, IN[2].xyzz, IN[2].xyzz 10: RSQ TEMP[3].x, TEMP[3].xxxx 11: MUL TEMP[3].xyz, IN[2].xyzz, TEMP[3].xxxx 12: MUL TEMP[4].xyz, TEMP[2].zxyy, TEMP[3].yzxx 13: MAD TEMP[4].xyz, TEMP[2].yzxx, TEMP[3].zxyy, -TEMP[4].xyzz 14: MUL TEMP[4].xyz, TEMP[4].xyzz, IN[3].wwww 15: MUL TEMP[1].xy, CONST[4][6].xyyy, IN[1].xyyy 16: MOV TEMP[5].xy, TEMP[1].xyyy 17: TEX TEMP[5].xyz, TEMP[5], SAMP[2], 2D 18: MAD TEMP[5].xyz, TEMP[5].xyzz, IMM[2].xxxx, IMM[2].yyyy 19: MUL TEMP[5].xyz, TEMP[5].xyzz, CONST[4][7].xyzz 20: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz 21: RSQ TEMP[6].x, TEMP[6].xxxx 22: MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xxxx 23: DP3 TEMP[6].x, IN[6].xyzz, IN[6].xyzz 24: RSQ TEMP[6].x, TEMP[6].xxxx 25: MUL TEMP[6].xyz, IN[6].xyzz, TEMP[6].xxxx 26: DP3 TEMP[7].x, TEMP[5].xyzz, TEMP[6].xyzz 27: MUL TEMP[7].xyz, TEMP[7].xxxx, TEMP[5].xyzz 28: MAD TEMP[6].xyz, TEMP[7].xyzz, IMM[2].xxxx, -TEMP[6].xyzz 29: DP3 TEMP[4].x, TEMP[4].xyzz, TEMP[6].xyzz 30: MOV TEMP[4].y, TEMP[4].xxxx 31: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[6].xyzz 32: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[6].xyzz 33: MOV TEMP[4].z, TEMP[3].xxxx 34: MOV TEMP[3].xyz, TEMP[4].xyzz 35: TEX TEMP[3].xyz, TEMP[3], SAMP[5], CUBE 36: DP3 TEMP[7].x, TEMP[3].xyzz, IMM[3].xyzz 37: LRP TEMP[7].xyz, CONST[4][14].yyyy, TEMP[7].xxxx, TEMP[3].xyzz 38: MUL TEMP[8].xyz, CONST[4][11].xyzz, CONST[4][11].wwww 39: MUL TEMP[7].xyz, TEMP[7].xyzz, TEMP[8].xyzz 40: MUL TEMP[0].xyz, TEMP[7].xyzz, TEMP[0].xxxx 41: MUL TEMP[3].xy, CONST[4][8].xyyy, IN[1].xyyy 42: MOV TEMP[7].xy, TEMP[3].xyyy 43: TEX TEMP[7].xyz, TEMP[7], SAMP[3], 2D 44: MUL TEMP[8].xyz, CONST[4][9].xyzz, CONST[4][9].wwww 45: MAD TEMP[0].xyz, TEMP[7].xyzz, TEMP[8].xyzz, TEMP[0].xyzz 46: ADD TEMP[3].xyz, IMM[2].zzzz, -CONST[4][0].xyzz 47: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[3].xyzz 48: MOV TEMP[7].xy, IN[0].xyyy 49: TEX TEMP[7].xyz, TEMP[7], SAMP[0], 2D 50: MUL TEMP[3].xyz, TEMP[7].xyzz, CONST[4][4].xyzz 51: MUL TEMP[8].xyz, TEMP[0].xyzz, TEMP[3].xyzz 52: DP2 TEMP[4].x, TEMP[5].yzzz, IMM[5].xyyy 53: MOV_SAT TEMP[4].x, TEMP[4].xxxx 54: DP3 TEMP[7].x, TEMP[5].xyzz, IMM[5].zwyy 55: MOV_SAT TEMP[7].x, TEMP[7].xxxx 56: MOV TEMP[4].y, TEMP[7].xxxx 57: DP3 TEMP[5].x, TEMP[5].yzxx, IMM[6].xyzz 58: MOV_SAT TEMP[5].x, TEMP[5].xxxx 59: MOV TEMP[4].z, TEMP[5].xxxx 60: MUL TEMP[2].xyz, TEMP[4].xyzz, TEMP[4].xyzz 61: MAX TEMP[4].xyz, TEMP[2].xyzz, IMM[2].wwww 62: MOV TEMP[5].xy, IN[0].xyyy 63: TEX TEMP[5].xyz, TEMP[5], SAMP[1], 2D 64: MUL TEMP[2].xyz, TEMP[5].xyzz, CONST[4][5].xyzz 65: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[4].xyzz 66: DP2 TEMP[4].x, TEMP[6].yzzz, IMM[5].xyyy 67: MOV_SAT TEMP[4].x, TEMP[4].xxxx 68: DP3 TEMP[7].x, TEMP[6].xyzz, IMM[5].zwyy 69: MOV_SAT TEMP[7].x, TEMP[7].xxxx 70: MOV TEMP[4].y, TEMP[7].xxxx 71: DP3 TEMP[6].x, TEMP[6].yzxx, IMM[6].xyzz 72: MOV_SAT TEMP[6].x, TEMP[6].xxxx 73: MOV TEMP[4].z, TEMP[6].xxxx 74: MAX TEMP[6].xyz, TEMP[4].xyzz, IMM[2].wwww 75: ABS TEMP[7].x, TEMP[6].xxxx 76: LG2 TEMP[4].x, TEMP[7].xxxx 77: ABS TEMP[7].x, TEMP[6].yyyy 78: LG2 TEMP[7].x, TEMP[7].xxxx 79: MOV TEMP[4].y, TEMP[7].xxxx 80: ABS TEMP[6].x, TEMP[6].zzzz 81: LG2 TEMP[6].x, TEMP[6].xxxx 82: MOV TEMP[4].z, TEMP[6].xxxx 83: ADD TEMP[1].x, CONST[4][14].zzzz, IMM[2].zzzz 84: MUL TEMP[1].xyz, TEMP[4].xyzz, TEMP[1].xxxx 85: EX2 TEMP[4].x, TEMP[1].xxxx 86: EX2 TEMP[6].x, TEMP[1].yyyy 87: MOV TEMP[4].y, TEMP[6].xxxx 88: EX2 TEMP[6].x, TEMP[1].zzzz 89: MOV TEMP[4].z, TEMP[6].xxxx 90: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[4].xyzz 91: MUL TEMP[4].xyz, CONST[4][12].xyzz, CONST[4][12].wwww 92: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xyzz 93: MUL TEMP[1].xyz, TEMP[2].xxxx, TEMP[3].xyzz 94: MAD TEMP[1].xyz, TEMP[8].xyzz, TEMP[5].xxxx, TEMP[1].xyzz 95: ADD TEMP[1].xyz, TEMP[1].xyzz, CONST[4][0].xyzz 96: MAD TEMP[9].xyz, TEMP[0].xyzz, CONST[4][15].xyzz, TEMP[1].xyzz 97: RCP TEMP[0].x, IN[5].wwww 98: MAD TEMP[0].x, CONST[4][2].xxxx, TEMP[0].xxxx, CONST[4][2].yyyy 99: MOV TEMP[9].w, TEMP[0].xxxx 100: MOV OUT[0], TEMP[9] 101: MOV OUT[1], TEMP[10] 102: MOV OUT[2], TEMP[11] 103: MOV OUT[3], TEMP[12] 104: MOV OUT[4], TEMP[13] 105: MOV OUT[5], TEMP[14] 106: MOV OUT[6], TEMP[15] 107: MOV OUT[7], TEMP[16] 108: END ", } constant_buffer 0: {buffer = NULL, buffer_offset = 0, buffer_size = 96, user_buffer = 0x87ad7490, } constant_buffer 1: {buffer = 0xeb17efa0, buffer_offset = 42432, buffer_size = 64, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 65536, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 2: {buffer = 0xb39dc648, buffer_offset = 78048, buffer_size = 144, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 147456, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 3: {buffer = 0xeb17f9f0, buffer_offset = 0, buffer_size = 24, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 4096, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 4: {buffer = 0xbeb54100, buffer_offset = 3227648, buffer_size = 4096, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 4096000, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } constant_buffer 5: {buffer = 0xeb17eaf8, buffer_offset = 0, buffer_size = 256, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 258048, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 64, flags = 3, } sampler_state 0: {wrap_s = repeat, wrap_t = mirror_clamp, wrap_r = mirror_clamp_to_border, min_img_filter = , min_mip_filter = , mag_img_filter = nearest, compare_mode = 1, compare_func = less_equal, normalized_coords = 0, max_anisotropy = 47, seamless_cube_map = 1, lod_bias = 0, min_lod = 0, max_lod = 1000, border_color.f = {0, 0, 0, 0, }, } sampler_state 1: {wrap_s = repeat, wrap_t = mirror_clamp, wrap_r = mirror_clamp_to_border, min_img_filter = , min_mip_filter = , mag_img_filter = nearest, compare_mode = 1, compare_func = less_equal, normalized_coords = 0, max_anisotropy = 47, seamless_cube_map = 1, lod_bias = 0, min_lod = 0, max_lod = 1000, border_color.f = {0, 0, 0, 0, }, } sampler_state 2: {wrap_s = repeat, wrap_t = repeat, wrap_r = repeat, min_img_filter = linear, min_mip_filter = linear, mag_img_filter = linear, compare_mode = 0, compare_func = never, normalized_coords = 1, max_anisotropy = 4, seamless_cube_map = 0, lod_bias = 0.932658, min_lod = 0, max_lod = 1000, border_color.f = {0, 0, 0, 0, }, } sampler_state 3: {wrap_s = repeat, wrap_t = repeat, wrap_r = repeat, min_img_filter = linear, min_mip_filter = linear, mag_img_filter = linear, compare_mode = 0, compare_func = never, normalized_coords = 1, max_anisotropy = 4, seamless_cube_map = 0, lod_bias = 0.932658, min_lod = 0, max_lod = 1000, border_color.f = {0, 0, 0, 0, }, } sampler_state 4: {wrap_s = repeat, wrap_t = repeat, wrap_r = repeat, min_img_filter = linear, min_mip_filter = linear, mag_img_filter = linear, compare_mode = 0, compare_func = never, normalized_coords = 1, max_anisotropy = 4, seamless_cube_map = 0, lod_bias = 0.932658, min_lod = 0, max_lod = 1000, border_color.f = {0, 0, 0, 0, }, } sampler_state 5: {wrap_s = clamp_to_edge, wrap_t = clamp_to_edge, wrap_r = clamp_to_edge, min_img_filter = linear, min_mip_filter = linear, mag_img_filter = linear, compare_mode = 0, compare_func = never, normalized_coords = 1, max_anisotropy = 16, seamless_cube_map = 0, lod_bias = 0, min_lod = 0, max_lod = 1000, border_color.f = {0, 0, 0, 0, }, } sampler_view 0: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, texture = 0xdd032a20, u.tex.first_layer = 0, u.tex.last_layer = 0, u.tex.last_level = 10, u.tex.last_level = 10, swizzle_r = 0, swizzle_g = 1, swizzle_b = 2, swizzle_a = 3, } texture: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, width0 = 1024, height0 = 128, depth0 = 1, array_size = 1, last_level = 10, nr_samples = 0, usage = 0, bind = 8, flags = 0, } sampler_view 1: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, texture = 0x860c12c8, u.tex.first_layer = 0, u.tex.last_layer = 0, u.tex.last_level = 10, u.tex.last_level = 10, swizzle_r = 0, swizzle_g = 1, swizzle_b = 2, swizzle_a = 3, } texture: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, width0 = 1024, height0 = 128, depth0 = 1, array_size = 1, last_level = 10, nr_samples = 0, usage = 0, bind = 8, flags = 0, } sampler_view 2: {target = 2d, format = PIPE_FORMAT_DXT1_RGBA, texture = 0x5e997888, u.tex.first_layer = 0, u.tex.last_layer = 0, u.tex.last_level = 8, u.tex.last_level = 8, swizzle_r = 0, swizzle_g = 1, swizzle_b = 2, swizzle_a = 3, } texture: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, width0 = 256, height0 = 64, depth0 = 1, array_size = 1, last_level = 8, nr_samples = 0, usage = 0, bind = 8, flags = 0, } sampler_view 3: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, texture = 0x5c4c4470, u.tex.first_layer = 0, u.tex.last_layer = 0, u.tex.last_level = 8, u.tex.last_level = 8, swizzle_r = 0, swizzle_g = 1, swizzle_b = 2, swizzle_a = 3, } texture: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, width0 = 256, height0 = 64, depth0 = 1, array_size = 1, last_level = 8, nr_samples = 0, usage = 0, bind = 8, flags = 0, } sampler_view 4: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, texture = 0x702b4750, u.tex.first_layer = 0, u.tex.last_layer = 0, u.tex.last_level = 8, u.tex.last_level = 8, swizzle_r = 0, swizzle_g = 1, swizzle_b = 2, swizzle_a = 3, } texture: {target = 2d, format = PIPE_FORMAT_DXT1_SRGBA, width0 = 256, height0 = 64, depth0 = 1, array_size = 1, last_level = 8, nr_samples = 0, usage = 0, bind = 8, flags = 0, } sampler_view 5: {target = cube, format = PIPE_FORMAT_DXT1_SRGBA, texture = 0xe0a7ee70, u.tex.first_layer = 0, u.tex.last_layer = 5, u.tex.last_level = 8, u.tex.last_level = 8, swizzle_r = 0, swizzle_g = 1, swizzle_b = 2, swizzle_a = 3, } texture: {target = cube, format = PIPE_FORMAT_DXT1_SRGBA, width0 = 256, height0 = 256, depth0 = 1, array_size = 6, last_level = 8, nr_samples = 0, usage = 0, bind = 8, flags = 0, } end shader: FRAGMENT depth_stencil_alpha_state: {depth = {enabled = 1, writemask = 1, func = less_equal, }, stencil = {{enabled = 0, }, {enabled = 0, }, }, alpha = {enabled = 0, }, } stencil_ref: {ref_value = {0, 0, }, } blend_state: {dither = 0, alpha_to_coverage = 0, alpha_to_one = 0, logicop_enable = 0, independent_blend_enable = 0, rt = {{blend_enable = 0, colormask = 15, }, }, } blend_color: {color = {1, 1, 1, 1, }, } min_samples = 1 sample_mask = 0xffffffff framebuffer_state: {width = 1920, height = 1200, samples = 0, layers = 0, nr_cbufs = 1, cbufs = {0xddc450c8, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, zsbuf = 0xdf9d8798, } cbufs[0]: surface: {format = PIPE_FORMAT_R16G16B16A16_FLOAT, width = 1920, height = 1200, texture = 0xdf9dbb78, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, } resource: {target = 2d, format = PIPE_FORMAT_R16G16B16A16_FLOAT, width0 = 1920, height0 = 1200, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 10, flags = 0, } zsbuf: surface: {format = PIPE_FORMAT_Z24_UNORM_S8_UINT, width = 1920, height = 1200, texture = 0xdf9d7100, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, } resource: {target = 2d, format = PIPE_FORMAT_Z24_UNORM_S8_UINT, width0 = 1920, height0 = 1200, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 1, flags = 0, } ***************************************************************************** Driver-specific state: SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 Vertex Shader as VS - main shader part - LLVM IR: ; ModuleID = 'tgsi' source_filename = "tgsi" target triple = "amdgcn--" define amdgpu_vs <{ float, float, float }> @main([17 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), [32 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32, i32) { main_body: %19 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 2, !amdgpu.uniform !0 %20 = load <16 x i8>, <16 x i8> addrspace(2)* %19, align 16, !invariant.load !0 %21 = call float @llvm.SI.load.const(<16 x i8> %20, i32 0) %22 = call float @llvm.SI.load.const(<16 x i8> %20, i32 4) %23 = call float @llvm.SI.load.const(<16 x i8> %20, i32 8) %24 = call float @llvm.SI.load.const(<16 x i8> %20, i32 12) %25 = call float @llvm.SI.load.const(<16 x i8> %20, i32 16) %26 = call float @llvm.SI.load.const(<16 x i8> %20, i32 20) %27 = call float @llvm.SI.load.const(<16 x i8> %20, i32 24) %28 = call float @llvm.SI.load.const(<16 x i8> %20, i32 28) %29 = call float @llvm.SI.load.const(<16 x i8> %20, i32 32) %30 = call float @llvm.SI.load.const(<16 x i8> %20, i32 36) %31 = call float @llvm.SI.load.const(<16 x i8> %20, i32 40) %32 = call float @llvm.SI.load.const(<16 x i8> %20, i32 44) %33 = call float @llvm.SI.load.const(<16 x i8> %20, i32 48) %34 = call float @llvm.SI.load.const(<16 x i8> %20, i32 52) %35 = call float @llvm.SI.load.const(<16 x i8> %20, i32 56) %36 = call float @llvm.SI.load.const(<16 x i8> %20, i32 60) %37 = call float @llvm.SI.load.const(<16 x i8> %20, i32 64) %38 = call float @llvm.SI.load.const(<16 x i8> %20, i32 68) %39 = call float @llvm.SI.load.const(<16 x i8> %20, i32 72) %40 = call float @llvm.SI.load.const(<16 x i8> %20, i32 76) %41 = call float @llvm.SI.load.const(<16 x i8> %20, i32 96) %42 = call float @llvm.SI.load.const(<16 x i8> %20, i32 100) %43 = call float @llvm.SI.load.const(<16 x i8> %20, i32 104) %44 = call float @llvm.SI.load.const(<16 x i8> %20, i32 108) %45 = call float @llvm.SI.load.const(<16 x i8> %20, i32 112) %46 = call float @llvm.SI.load.const(<16 x i8> %20, i32 116) %47 = call float @llvm.SI.load.const(<16 x i8> %20, i32 120) %48 = call float @llvm.SI.load.const(<16 x i8> %20, i32 124) %49 = call float @llvm.SI.load.const(<16 x i8> %20, i32 128) %50 = call float @llvm.SI.load.const(<16 x i8> %20, i32 132) %51 = call float @llvm.SI.load.const(<16 x i8> %20, i32 136) %52 = call float @llvm.SI.load.const(<16 x i8> %20, i32 140) %53 = call float @llvm.SI.load.const(<16 x i8> %20, i32 144) %54 = call float @llvm.SI.load.const(<16 x i8> %20, i32 148) %55 = call float @llvm.SI.load.const(<16 x i8> %20, i32 152) %56 = call float @llvm.SI.load.const(<16 x i8> %20, i32 156) %57 = call float @llvm.SI.load.const(<16 x i8> %20, i32 160) %58 = call float @llvm.SI.load.const(<16 x i8> %20, i32 164) %59 = call float @llvm.SI.load.const(<16 x i8> %20, i32 168) %60 = call float @llvm.SI.load.const(<16 x i8> %20, i32 176) %61 = call float @llvm.SI.load.const(<16 x i8> %20, i32 180) %62 = call float @llvm.SI.load.const(<16 x i8> %20, i32 184) %63 = call float @llvm.SI.load.const(<16 x i8> %20, i32 192) %64 = call float @llvm.SI.load.const(<16 x i8> %20, i32 196) %65 = call float @llvm.SI.load.const(<16 x i8> %20, i32 200) %66 = call float @llvm.SI.load.const(<16 x i8> %20, i32 208) %67 = call float @llvm.SI.load.const(<16 x i8> %20, i32 224) %68 = call float @llvm.SI.load.const(<16 x i8> %20, i32 228) %69 = call float @llvm.SI.load.const(<16 x i8> %20, i32 232) %70 = call float @llvm.SI.load.const(<16 x i8> %20, i32 236) %71 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 4, !amdgpu.uniform !0 %72 = load <16 x i8>, <16 x i8> addrspace(2)* %71, align 16, !invariant.load !0 %73 = call float @llvm.SI.load.const(<16 x i8> %72, i32 8) %74 = call float @llvm.SI.load.const(<16 x i8> %72, i32 12) %75 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 0, !amdgpu.uniform !0 %76 = load <16 x i8>, <16 x i8> addrspace(2)* %75, align 16, !invariant.load !0 %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %76, i32 0, i32 %14) %78 = extractelement <4 x float> %77, i32 0 %79 = extractelement <4 x float> %77, i32 1 %80 = extractelement <4 x float> %77, i32 2 %81 = extractelement <4 x float> %77, i32 3 %82 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 1, !amdgpu.uniform !0 %83 = load <16 x i8>, <16 x i8> addrspace(2)* %82, align 16, !invariant.load !0 %84 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %83, i32 0, i32 %15) %85 = extractelement <4 x float> %84, i32 0 %86 = extractelement <4 x float> %84, i32 1 %87 = extractelement <4 x float> %84, i32 2 %88 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 2, !amdgpu.uniform !0 %89 = load <16 x i8>, <16 x i8> addrspace(2)* %88, align 16, !invariant.load !0 %90 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %89, i32 0, i32 %16) %91 = extractelement <4 x float> %90, i32 0 %92 = extractelement <4 x float> %90, i32 1 %93 = extractelement <4 x float> %90, i32 2 %94 = extractelement <4 x float> %90, i32 3 %95 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 3, !amdgpu.uniform !0 %96 = load <16 x i8>, <16 x i8> addrspace(2)* %95, align 16, !invariant.load !0 %97 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %96, i32 0, i32 %17) %98 = extractelement <4 x float> %97, i32 0 %99 = extractelement <4 x float> %97, i32 1 %100 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 4, !amdgpu.uniform !0 %101 = load <16 x i8>, <16 x i8> addrspace(2)* %100, align 16, !invariant.load !0 %102 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %101, i32 0, i32 %18) %103 = extractelement <4 x float> %102, i32 0 %104 = extractelement <4 x float> %102, i32 1 %105 = fmul float %103, %67 %106 = fadd float %105, %70 %107 = fmul float %104, %68 %108 = fadd float %107, %69 %109 = fmul float %91, 0x3F80101020000000 %110 = fadd float %109, -1.000000e+00 %111 = fmul float %92, 0x3F80101020000000 %112 = fadd float %111, -1.000000e+00 %113 = fmul float %93, 0x3F80101020000000 %114 = fadd float %113, -1.000000e+00 %115 = fmul float %94, 0x3F80101020000000 %116 = fadd float %115, -1.000000e+00 %117 = fmul float %116, %66 %118 = fmul float %45, %79 %119 = fmul float %46, %79 %120 = fmul float %47, %79 %121 = fmul float %48, %79 %122 = fmul float %41, %78 %123 = fadd float %122, %118 %124 = fmul float %42, %78 %125 = fadd float %124, %119 %126 = fmul float %43, %78 %127 = fadd float %126, %120 %128 = fmul float %44, %78 %129 = fadd float %128, %121 %130 = fmul float %49, %80 %131 = fadd float %130, %123 %132 = fmul float %50, %80 %133 = fadd float %132, %125 %134 = fmul float %51, %80 %135 = fadd float %134, %127 %136 = fmul float %52, %80 %137 = fadd float %136, %129 %138 = fmul float %53, %81 %139 = fadd float %138, %131 %140 = fmul float %54, %81 %141 = fadd float %140, %133 %142 = fmul float %55, %81 %143 = fadd float %142, %135 %144 = fmul float %56, %81 %145 = fadd float %144, %137 %146 = fmul float %40, %139 %147 = fsub float %37, %146 %148 = fmul float %40, %141 %149 = fsub float %38, %148 %150 = fmul float %40, %143 %151 = fsub float %39, %150 %152 = fmul float %149, %60 %153 = fmul float %149, %61 %154 = fmul float %149, %62 %155 = fmul float %57, %147 %156 = fadd float %155, %152 %157 = fmul float %58, %147 %158 = fadd float %157, %153 %159 = fmul float %59, %147 %160 = fadd float %159, %154 %161 = fmul float %63, %151 %162 = fadd float %161, %156 %163 = fmul float %64, %151 %164 = fadd float %163, %158 %165 = fmul float %65, %151 %166 = fadd float %165, %160 %167 = fmul float %86, 0x3F80101020000000 %168 = fadd float %167, -1.000000e+00 %169 = fmul float %87, 0x3F80101020000000 %170 = fadd float %169, -1.000000e+00 %171 = fmul float %85, 0x3F80101020000000 %172 = fadd float %171, -1.000000e+00 %173 = fmul float %114, %168 %174 = fmul float %110, %170 %175 = fmul float %112, %172 %176 = fmul float %112, %170 %177 = fsub float %176, %173 %178 = fmul float %114, %172 %179 = fsub float %178, %174 %180 = fmul float %110, %168 %181 = fsub float %180, %175 %182 = fmul float %116, %177 %183 = fmul float %116, %179 %184 = fmul float %116, %181 %185 = fmul float %112, %184 %186 = fmul float %114, %182 %187 = fmul float %110, %183 %188 = fmul float %183, %114 %189 = fsub float %188, %185 %190 = fmul float %184, %110 %191 = fsub float %190, %186 %192 = fmul float %182, %112 %193 = fsub float %192, %187 %194 = fmul float %116, %189 %195 = fmul float %116, %191 %196 = fmul float %116, %193 %197 = fmul float %194, %162 %198 = fmul float %195, %164 %199 = fadd float %198, %197 %200 = fmul float %196, %166 %201 = fadd float %199, %200 %202 = fmul float %182, %162 %203 = fmul float %183, %164 %204 = fadd float %203, %202 %205 = fmul float %184, %166 %206 = fadd float %204, %205 %207 = fmul float %110, %162 %208 = fmul float %112, %164 %209 = fadd float %208, %207 %210 = fmul float %114, %166 %211 = fadd float %209, %210 %212 = fmul float %194, %63 %213 = fmul float %195, %64 %214 = fadd float %213, %212 %215 = fmul float %196, %65 %216 = fadd float %214, %215 %217 = fmul float %182, %63 %218 = fmul float %183, %64 %219 = fadd float %218, %217 %220 = fmul float %184, %65 %221 = fadd float %219, %220 %222 = fmul float %110, %63 %223 = fmul float %112, %64 %224 = fadd float %223, %222 %225 = fmul float %114, %65 %226 = fadd float %224, %225 %227 = fmul float %112, %45 %228 = fmul float %112, %47 %229 = fmul float %41, %110 %230 = fadd float %229, %227 %231 = fmul float %43, %110 %232 = fadd float %231, %228 %233 = fmul float %51, %114 %234 = fadd float %233, %232 %235 = fmul float %49, %114 %236 = fadd float %235, %230 %237 = fmul float %183, %45 %238 = fmul float %183, %47 %239 = fmul float %41, %182 %240 = fadd float %239, %237 %241 = fmul float %43, %182 %242 = fadd float %241, %238 %243 = fmul float %51, %184 %244 = fadd float %243, %242 %245 = fmul float %49, %184 %246 = fadd float %245, %240 %247 = fmul float %195, %45 %248 = fmul float %195, %47 %249 = fmul float %41, %194 %250 = fadd float %249, %247 %251 = fmul float %43, %194 %252 = fadd float %251, %248 %253 = fmul float %49, %196 %254 = fadd float %253, %250 %255 = fmul float %51, %196 %256 = fadd float %255, %252 %257 = fmul float %141, %25 %258 = fmul float %141, %26 %259 = fmul float %141, %27 %260 = fmul float %141, %28 %261 = fmul float %21, %139 %262 = fadd float %261, %257 %263 = fmul float %22, %139 %264 = fadd float %263, %258 %265 = fmul float %23, %139 %266 = fadd float %265, %259 %267 = fmul float %24, %139 %268 = fadd float %267, %260 %269 = fmul float %29, %143 %270 = fadd float %269, %262 %271 = fmul float %30, %143 %272 = fadd float %271, %264 %273 = fmul float %31, %143 %274 = fadd float %273, %266 %275 = fmul float %32, %143 %276 = fadd float %275, %268 %277 = fmul float %33, %145 %278 = fadd float %277, %270 %279 = fmul float %34, %145 %280 = fadd float %279, %272 %281 = fmul float %35, %145 %282 = fadd float %281, %274 %283 = fmul float %36, %145 %284 = fadd float %283, %276 %285 = fmul float %98, 0.000000e+00 %286 = fmul float %98, 0.000000e+00 %287 = fmul float %284, %73 %288 = fadd float %287, %278 %289 = fmul float %284, %74 %290 = fsub float %289, %280 %291 = fmul float %282, 2.000000e+00 %292 = fsub float %291, %284 %293 = bitcast i32 %12 to float %294 = insertvalue <{ float, float, float }> undef, float %293, 2 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %106, float %108, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %98, float %99, float %285, float %286) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %254, float %246, float %236, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %256, float %244, float %234, float %117) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %278, float %280, float %282, float %284) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %201, float %206, float %211, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %216, float %221, float %226, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 40, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 41, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %288, float %290, float %292, float %284) ret <{ float, float, float }> %294 } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #0 ; Function Attrs: nounwind declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) #1 attributes #0 = { nounwind readnone } attributes #1 = { nounwind } !0 = !{} Vertex Shader as VS: Shader prolog disassembly: v_add_i32_e32 v4, vcc, s12, v0 ; 3208000C v_mov_b32_e32 v5, v4 ; 7E0A0304 v_mov_b32_e32 v6, v4 ; 7E0C0304 v_mov_b32_e32 v7, v4 ; 7E0E0304 v_mov_b32_e32 v8, v4 ; 7E100304 Shader main disassembly: s_load_dwordx4 s[4:7], s[10:11], 0x0 ; C00A0105 00000000 s_load_dwordx4 s[12:15], s[10:11], 0x10 ; C00A0305 00000010 s_load_dwordx4 s[16:19], s[10:11], 0x20 ; C00A0405 00000020 s_load_dwordx4 s[20:23], s[10:11], 0x30 ; C00A0505 00000030 s_load_dwordx4 s[8:11], s[10:11], 0x40 ; C00A0205 00000040 s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[9:12], v4, s[4:7], 0 idxen ; E00C2000 80010904 s_nop 0 ; BF800000 buffer_load_format_xyzw v[13:16], v5, s[12:15], 0 idxen ; E00C2000 80030D05 s_nop 0 ; BF800000 buffer_load_format_xyzw v[3:6], v6, s[16:19], 0 idxen ; E00C2000 80040306 s_waitcnt vmcnt(1) ; BF8C0F71 buffer_load_format_xyzw v[16:19], v7, s[20:23], 0 idxen ; E00C2000 80051007 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_load_format_xyzw v[18:21], v8, s[8:11], 0 idxen ; E00C2000 80021208 s_load_dwordx4 s[4:7], s[2:3], 0x20 ; C00A0101 00000020 s_load_dwordx4 s[0:3], s[2:3], 0x40 ; C00A0001 00000040 s_nop 0 ; BF800000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s51, s[4:7], 0xe8 ; C0220CC2 000000E8 s_buffer_load_dword s52, s[4:7], 0xec ; C0220D02 000000EC s_buffer_load_dword s33, s[4:7], 0x74 ; C0220842 00000074 s_buffer_load_d Memory-mapped registers: GRBM_STATUS <- ME0PIPE0_CMDFIFO_AVAIL = 8 SRBM_RQ_PENDING = 1 ME0PIPE0_CF_RQ_PENDING = 0 ME0PIPE0_PF_RQ_PENDING = 0 GDS_DMA_RQ_PENDING = 0 DB_CLEAN = 0 CB_CLEAN = 0 TA_BUSY = 0 GDS_BUSY = 0 WD_BUSY_NO_DMA = 0 VGT_BUSY = 0 IA_BUSY_NO_DMA = 0 IA_BUSY = 0 SX_BUSY = 0 WD_BUSY = 0 SPI_BUSY = 1 BCI_BUSY = 0 SC_BUSY = 0 PA_BUSY = 0 DB_BUSY = 1 CP_COHERENCY_BUSY = 0 CP_BUSY = 1 CB_BUSY = 1 GUI_ACTIVE = 1 GRBM_STATUS2 <- ME0PIPE1_CMDFIFO_AVAIL = 8 ME0PIPE1_CF_RQ_PENDING = 0 ME0PIPE1_PF_RQ_PENDING = 0 ME1PIPE0_RQ_PENDING = 0 ME1PIPE1_RQ_PENDING = 0 ME1PIPE2_RQ_PENDING = 0 ME1PIPE3_RQ_PENDING = 0 ME2PIPE0_RQ_PENDING = 0 ME2PIPE1_RQ_PENDING = 0 ME2PIPE2_RQ_PENDING = 0 ME2PIPE3_RQ_PENDING = 0 RLC_RQ_PENDING = 0 RLC_BUSY = 0 TC_BUSY = 0 TCC_CC_RESIDENT = 0 CPF_BUSY = 1 CPC_BUSY = 0 CPG_BUSY = 1 GRBM_STATUS_SE0 <- DB_CLEAN = 0 CB_CLEAN = 0 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 1 SC_BUSY = 0 DB_BUSY = 1 CB_BUSY = 1 GRBM_STATUS_SE1 <- DB_CLEAN = 0 CB_CLEAN = 0 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 1 SC_BUSY = 0 DB_BUSY = 1 CB_BUSY = 1 GRBM_STATUS_SE2 <- DB_CLEAN = 0 CB_CLEAN = 0 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 1 SC_BUSY = 0 DB_BUSY = 1 CB_BUSY = 1 GRBM_STATUS_SE3 <- DB_CLEAN = 0 CB_CLEAN = 0 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 1 SC_BUSY = 0 DB_BUSY = 1 CB_BUSY = 1 SDMA0_STATUS_REG <- IDLE = 1 REG_IDLE = 1 RB_EMPTY = 1 RB_FULL = 0 RB_CMD_IDLE = 1 RB_CMD_FULL = 0 IB_CMD_IDLE = 1 IB_CMD_FULL = 0 BLOCK_IDLE = 1 INSIDE_IB = 0 EX_IDLE = 1 EX_IDLE_POLL_TIMER_EXPIRE = 1 PACKET_READY = 0 MC_WR_IDLE = 1 SRBM_IDLE = 1 CONTEXT_EMPTY = 1 DELTA_RPTR_FULL = 0 RB_MC_RREQ_IDLE = 1 IB_MC_RREQ_IDLE = 1 MC_RD_IDLE = 1 DELTA_RPTR_EMPTY = 1 MC_RD_RET_STALL = 0 MC_RD_NO_POLL_IDLE = 1 PREV_CMD_IDLE = 1 SEM_IDLE = 1 SEM_REQ_STALL = 0 SEM_RESP_STATE = 0 INT_IDLE = 1 INT_REQ_STALL = 0 SDMA1_STATUS_REG <- IDLE = 1 REG_IDLE = 1 RB_EMPTY = 1 RB_FULL = 0 RB_CMD_IDLE = 1 RB_CMD_FULL = 0 IB_CMD_IDLE = 1 IB_CMD_FULL = 0 BLOCK_IDLE = 1 INSIDE_IB = 0 EX_IDLE = 1 EX_IDLE_POLL_TIMER_EXPIRE = 1 PACKET_READY = 0 MC_WR_IDLE = 1 SRBM_IDLE = 1 CONTEXT_EMPTY = 1 DELTA_RPTR_FULL = 0 RB_MC_RREQ_IDLE = 1 IB_MC_RREQ_IDLE = 1 MC_RD_IDLE = 1 DELTA_RPTR_EMPTY = 1 MC_RD_RET_STALL = 0 MC_RD_NO_POLL_IDLE = 1 PREV_CMD_IDLE = 1 SEM_IDLE = 1 SEM_REQ_STALL = 0 SEM_RESP_STATE = 0 INT_IDLE = 1 INT_REQ_STALL = 0 SRBM_STATUS <- UVD_RQ_PENDING = 0 SAMMSP_RQ_PENDING = 0 ACP_RQ_PENDING = 0 SMU_RQ_PENDING = 0 GRBM_RQ_PENDING = 0 HI_RQ_PENDING = 1 VMC_BUSY = 0 MCB_BUSY = 0 MCB_NON_DISPLAY_BUSY = 0 MCC_BUSY = 0 MCD_BUSY = 0 VMC1_BUSY = 0 SEM_BUSY = 0 ACP_BUSY = 0 IH_BUSY = 0 UVD_BUSY = 0 SAMMSP_BUSY = 0 GCATCL2_BUSY = 0 OSATCL2_BUSY = 0 BIF_BUSY = 1 SRBM_STATUS2 <- SDMA_RQ_PENDING = 0 TST_RQ_PENDING = 0 SDMA1_RQ_PENDING = 0 VCE0_RQ_PENDING = 0 VP8_BUSY = 0 SDMA_BUSY = 0 SDMA1_BUSY = 0 VCE0_BUSY = 0 XDMA_BUSY = 0 CHUB_BUSY = 0 SDMA2_BUSY = 0 SDMA3_BUSY = 0 SAMSCP_BUSY = 0 ISP_BUSY = 0 VCE1_BUSY = 0 ODE_BUSY = 0 SDMA2_RQ_PENDING = 0 SDMA3_RQ_PENDING = 0 SAMSCP_RQ_PENDING = 0 ISP_RQ_PENDING = 0 VCE1_RQ_PENDING = 0 SRBM_STATUS3 <- MCC0_BUSY = 0 MCC1_BUSY = 0 MCC2_BUSY = 0 MCC3_BUSY = 0 MCC4_BUSY = 0 MCC5_BUSY = 0 MCC6_BUSY = 0 MCC7_BUSY = 0 MCD0_BUSY = 0 MCD1_BUSY = 0 MCD2_BUSY = 0 MCD3_BUSY = 0 MCD4_BUSY = 0 MCD5_BUSY = 0 MCD6_BUSY = 0 MCD7_BUSY = 0 CP_STAT <- ROQ_RING_BUSY = 1 ROQ_INDIRECT1_BUSY = 1 ROQ_INDIRECT2_BUSY = 0 ROQ_STATE_BUSY = 0 DC_BUSY = 0 ATCL2IU_BUSY = 0 PFP_BUSY = 1 MEQ_BUSY = 1 ME_BUSY = 1 QUERY_BUSY = 0 SEMAPHORE_BUSY = 0 INTERRUPT_BUSY = 0 SURFACE_SYNC_BUSY = 0 DMA_BUSY = 0 RCIU_BUSY = 0 SCRATCH_RAM_BUSY = 0 CPC_CPG_BUSY = 0 CE_BUSY = 0 TCIU_BUSY = 0 ROQ_CE_RING_BUSY = 0 ROQ_CE_INDIRECT1_BUSY = 0 ROQ_CE_INDIRECT2_BUSY = 0 CP_BUSY = 1 CP_STALLED_STAT1 <- RBIU_TO_DMA_NOT_RDY_TO_RCV = 0 RBIU_TO_SEM_NOT_RDY_TO_RCV = 0 RBIU_TO_MEMWR_NOT_RDY_TO_RCV = 0 ME_HAS_ACTIVE_CE_BUFFER_FLAG = 1 ME_HAS_ACTIVE_DE_BUFFER_FLAG = 1 ME_STALLED_ON_TC_WR_CONFIRM = 0 ME_STALLED_ON_ATOMIC_RTN_DATA = 0 ME_WAITING_ON_TC_READ_DATA = 0 ME_WAITING_ON_REG_READ_DATA = 0 RCIU_WAITING_ON_GDS_FREE = 0 RCIU_WAITING_ON_GRBM_FREE = 0 RCIU_WAITING_ON_VGT_FREE = 0 RCIU_STALLED_ON_ME_READ = 0 RCIU_STALLED_ON_DMA_READ = 0 RCIU_STALLED_ON_APPEND_READ = 0 RCIU_HALTED_BY_REG_VIOLATION = 0 CP_STALLED_STAT2 <- PFP_TO_CSF_NOT_RDY_TO_RCV = 0 PFP_TO_MEQ_NOT_RDY_TO_RCV = 0 PFP_TO_RCIU_NOT_RDY_TO_RCV = 0 PFP_TO_VGT_WRITES_PENDING = 0 PFP_RCIU_READ_PENDING = 0 PFP_WAITING_ON_BUFFER_DATA = 0 ME_WAIT_ON_CE_COUNTER = 0 ME_WAIT_ON_AVAIL_BUFFER = 0 GFX_CNTX_NOT_AVAIL_TO_ME = 0 ME_RCIU_NOT_RDY_TO_RCV = 0 ME_TO_CONST_NOT_RDY_TO_RCV = 0 ME_WAITING_DATA_FROM_PFP = 0 ME_WAITING_ON_PARTIAL_FLUSH = 1 MEQ_TO_ME_NOT_RDY_TO_RCV = 1 STQ_TO_ME_NOT_RDY_TO_RCV = 0 ME_WAITING_DATA_FROM_STQ = 0 PFP_STALLED_ON_TC_WR_CONFIRM = 0 PFP_STALLED_ON_ATOMIC_RTN_DATA = 0 EOPD_FIFO_NEEDS_SC_EOP_DONE = 0 EOPD_FIFO_NEEDS_WR_CONFIRM = 0 STRMO_WR_OF_PRIM_DATA_PENDING = 0 PIPE_STATS_WR_DATA_PENDING = 0 APPEND_RDY_WAIT_ON_CS_DONE = 0 APPEND_RDY_WAIT_ON_PS_DONE = 0 APPEND_WAIT_ON_WR_CONFIRM = 0 APPEND_ACTIVE_PARTITION = 0 APPEND_WAITING_TO_SEND_MEMWRITE = 0 SURF_SYNC_NEEDS_IDLE_CNTXS = 0 SURF_SYNC_NEEDS_ALL_CLEAN = 0 CP_STALLED_STAT3 <- CE_TO_CSF_NOT_RDY_TO_RCV = 0 CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV = 0 CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER = 0 CE_TO_RAM_INIT_NOT_RDY = 0 CE_TO_RAM_DUMP_NOT_RDY = 0 CE_TO_RAM_WRITE_NOT_RDY = 0 CE_TO_INC_FIFO_NOT_RDY_TO_RCV = 0 CE_TO_WR_FIFO_NOT_RDY_TO_RCV = 0 CE_WAITING_ON_BUFFER_DATA = 0 CE_WAITING_ON_CE_BUFFER_FLAG = 0 CE_WAITING_ON_DE_COUNTER = 0 CE_WAITING_ON_DE_COUNTER_UNDERFLOW = 0 TCIU_WAITING_ON_FREE = 0 TCIU_WAITING_ON_TAGS = 0 CE_STALLED_ON_TC_WR_CONFIRM = 0 CE_STALLED_ON_ATOMIC_RTN_DATA = 0 ATCL2IU_WAITING_ON_FREE = 0 ATCL2IU_WAITING_ON_TAGS = 0 ATCL1_WAITING_ON_TRANS = 0 CP_CPC_STATUS <- MEC1_BUSY = 0 MEC2_BUSY = 0 DC0_BUSY = 0 DC1_BUSY = 0 RCIU1_BUSY = 0 RCIU2_BUSY = 0 ROQ1_BUSY = 0 ROQ2_BUSY = 0 TCIU_BUSY = 0 SCRATCH_RAM_BUSY = 0 QU_BUSY = 0 ATCL2IU_BUSY = 0 CPG_CPC_BUSY = 0 CPF_CPC_BUSY = 0 CPC_BUSY = 0 CP_CPC_BUSY_STAT <- MEC1_LOAD_BUSY = 0 MEC1_SEMAPOHRE_BUSY = 0 MEC1_MUTEX_BUSY = 0 MEC1_MESSAGE_BUSY = 0 MEC1_EOP_QUEUE_BUSY = 0 MEC1_IQ_QUEUE_BUSY = 0 MEC1_IB_QUEUE_BUSY = 0 MEC1_TC_BUSY = 0 MEC1_DMA_BUSY = 0 MEC1_PARTIAL_FLUSH_BUSY = 0 MEC1_PIPE0_BUSY = 0 MEC1_PIPE1_BUSY = 0 MEC1_PIPE2_BUSY = 0 MEC1_PIPE3_BUSY = 0 MEC2_LOAD_BUSY = 0 MEC2_SEMAPOHRE_BUSY = 0 MEC2_MUTEX_BUSY = 0 MEC2_MESSAGE_BUSY = 0 MEC2_EOP_QUEUE_BUSY = 0 MEC2_IQ_QUEUE_BUSY = 0 MEC2_IB_QUEUE_BUSY = 0 MEC2_TC_BUSY = 0 MEC2_DMA_BUSY = 0 MEC2_PARTIAL_FLUSH_BUSY = 0 MEC2_PIPE0_BUSY = 0 MEC2_PIPE1_BUSY = 0 MEC2_PIPE2_BUSY = 0 MEC2_PIPE3_BUSY = 0 CP_CPC_STALLED_STAT1 <- RCIU_TX_FREE_STALL = 0 RCIU_PRIV_VIOLATION = 0 TCIU_TX_FREE_STALL = 0 MEC1_DECODING_PACKET = 0 MEC1_WAIT_ON_RCIU = 0 MEC1_WAIT_ON_RCIU_READ = 0 MEC1_WAIT_ON_ROQ_DATA = 0 MEC2_DECODING_PACKET = 0 MEC2_WAIT_ON_RCIU = 0 MEC2_WAIT_ON_RCIU_READ = 0 MEC2_WAIT_ON_ROQ_DATA = 0 ATCL2IU_WAITING_ON_FREE = 0 ATCL2IU_WAITING_ON_TAGS = 0 ATCL1_WAITING_ON_TRANS = 0 CP_CPF_STATUS <- POST_WPTR_GFX_BUSY = 1 CSF_BUSY = 1 ROQ_ALIGN_BUSY = 0 ROQ_RING_BUSY = 1 ROQ_INDIRECT1_BUSY = 1 ROQ_INDIRECT2_BUSY = 0 ROQ_STATE_BUSY = 0 ROQ_CE_RING_BUSY = 0 ROQ_CE_INDIRECT1_BUSY = 0 ROQ_CE_INDIRECT2_BUSY = 0 SEMAPHORE_BUSY = 0 INTERRUPT_BUSY = 0 TCIU_BUSY = 0 HQD_BUSY = 0 PRT_BUSY = 0 ATCL2IU_BUSY = 0 CPF_GFX_BUSY = 1 CPF_CMP_BUSY = 0 GRBM_CPF_STAT_BUSY = 3 CPC_CPF_BUSY = 0 CPF_BUSY = 1 CP_CPF_BUSY_STAT <- REG_BUS_FIFO_BUSY = 0 CSF_RING_BUSY = 1 CSF_INDIRECT1_BUSY = 1 CSF_INDIRECT2_BUSY = 0 CSF_STATE_BUSY = 0 CSF_CE_INDR1_BUSY = 0 CSF_CE_INDR2_BUSY = 0 CSF_ARBITER_BUSY = 0 CSF_INPUT_BUSY = 0 OUTSTANDING_READ_TAGS = 0 HPD_PROCESSING_EOP_BUSY = 0 HQD_DISPATCH_BUSY = 0 HQD_IQ_TIMER_BUSY = 0 HQD_DMA_OFFLOAD_BUSY = 0 HQD_WAIT_SEMAPHORE_BUSY = 0 HQD_SIGNAL_SEMAPHORE_BUSY = 0 HQD_MESSAGE_BUSY = 0 HQD_PQ_FETCHER_BUSY = 0 HQD_IB_FETCHER_BUSY = 0 HQD_IQ_FETCHER_BUSY = 0 HQD_EOP_FETCHER_BUSY = 0 HQD_CONSUMED_RPTR_BUSY = 0 HQD_FETCHER_ARB_BUSY = 0 HQD_ROQ_ALIGN_BUSY = 0 HQD_ROQ_EOP_BUSY = 0 HQD_ROQ_IQ_BUSY = 0 HQD_ROQ_PQ_BUSY = 0 HQD_ROQ_IB_BUSY = 0 HQD_WPTR_POLL_BUSY = 0 HQD_PQ_BUSY = 0 HQD_IB_BUSY = 0 CP_CPF_STALLED_STAT1 <- RING_FETCHING_DATA = 0 INDR1_FETCHING_DATA = 1 INDR2_FETCHING_DATA = 0 STATE_FETCHING_DATA = 0 TCIU_WAITING_ON_FREE = 0 TCIU_WAITING_ON_TAGS = 0 ATCL2IU_WAITING_ON_FREE = 0 ATCL2IU_WAITING_ON_TAGS = 0 ATCL1_WAITING_ON_TRANS = 0 Last 60 lines of dmesg: [ 2.951637] amdgpu 0000:01:00.0: fence driver on ring 7 use gpu addr 0x0000000100000094, cpu addr 0xffff8800ac81a094 [ 2.951725] amdgpu 0000:01:00.0: fence driver on ring 8 use gpu addr 0x00000001000000a8, cpu addr 0xffff8800ac81a0a8 [ 2.953523] amdgpu 0000:01:00.0: fence driver on ring 9 use gpu addr 0x00000001000000bc, cpu addr 0xffff8800ac81a0bc [ 2.953586] amdgpu 0000:01:00.0: fence driver on ring 10 use gpu addr 0x00000001000000d0, cpu addr 0xffff8800ac81a0d0 [ 2.956438] [drm] Found UVD firmware Version: 1.52 Family ID: 10 [ 2.956728] amdgpu 0000:01:00.0: fence driver on ring 11 use gpu addr 0x00000000008907b0, cpu addr 0xffffc9000524e7b0 [ 2.958367] [drm] Found VCE firmware Version: 50.17 Binary ID: 3 [ 2.958442] amdgpu 0000:01:00.0: fence driver on ring 12 use gpu addr 0x00000001000000f8, cpu addr 0xffff8800ac81a0f8 [ 2.958474] amdgpu 0000:01:00.0: fence driver on ring 13 use gpu addr 0x000000010000010c, cpu addr 0xffff8800ac81a10c [ 3.035429] kvm: Nested Virtualization enabled [ 3.035433] kvm: Nested Paging enabled [ 3.078560] [drm] ring test on 0 succeeded in 11 usecs [ 3.078823] [drm] ring test on 1 succeeded in 25 usecs [ 3.078859] [drm] ring test on 2 succeeded in 17 usecs [ 3.078869] [drm] ring test on 3 succeeded in 4 usecs [ 3.078874] [drm] ring test on 4 succeeded in 2 usecs [ 3.078882] [drm] ring test on 5 succeeded in 3 usecs [ 3.078890] [drm] ring test on 6 succeeded in 3 usecs [ 3.078898] [drm] ring test on 7 succeeded in 3 usecs [ 3.078905] [drm] ring test on 8 succeeded in 3 usecs [ 3.078946] [drm] ring test on 9 succeeded in 5 usecs [ 3.078953] [drm] ring test on 10 succeeded in 5 usecs [ 3.125018] [drm] ring test on 11 succeeded in 2 usecs [ 3.125034] clocksource: Switched to clocksource tsc [ 3.145046] [drm] UVD initialized successfully. [ 3.224074] usbcore: registered new interface driver snd-usb-audio [ 3.365120] [drm] ring test on 12 succeeded in 22 usecs [ 3.365133] [drm] ring test on 13 succeeded in 4 usecs [ 3.365133] [drm] VCE initialized successfully. [ 3.558193] [drm] fb mappable at 0xC0A9A000 [ 3.558195] [drm] vram apper at 0xC0000000 [ 3.558195] [drm] size 9216000 [ 3.558196] [drm] fb depth is 24 [ 3.558197] [drm] pitch is 7680 [ 3.558297] fbcon: amdgpudrmfb (fb0) is primary device [ 3.808237] Console: switching to colour frame buffer device 240x75 [ 3.812483] amdgpu 0000:01:00.0: fb0: amdgpudrmfb frame buffer device [ 3.816948] [drm] ib test on ring 0 succeeded in 0 usecs [ 3.817018] [drm] ib test on ring 1 succeeded in 0 usecs [ 3.817037] [drm] ib test on ring 2 succeeded in 0 usecs [ 3.817063] [drm] ib test on ring 3 succeeded in 0 usecs [ 3.817085] [drm] ib test on ring 4 succeeded in 0 usecs [ 3.817105] [drm] ib test on ring 5 succeeded in 0 usecs [ 3.817124] [drm] ib test on ring 6 succeeded in 0 usecs [ 3.817142] [drm] ib test on ring 7 succeeded in 0 usecs [ 3.817161] [drm] ib test on ring 8 succeeded in 0 usecs [ 3.817179] [drm] ib test on ring 9 succeeded in 0 usecs [ 3.817197] [drm] ib test on ring 10 succeeded in 0 usecs [ 3.838192] [drm] ib test on ring 11 succeeded [ 3.858358] [drm] ib test on ring 12 succeeded [ 3.859239] [drm] Initialized amdgpu 3.2.0 20150101 for 0000:01:00.0 on minor 0 [ 3.951963] EXT4-fs (sda2): re-mounted. Opts: discard [ 5.671175] EXT4-fs (sdc1): recovery complete [ 5.697302] EXT4-fs (sdc1): mounted filesystem with ordered data mode. Opts: (null) [ 6.572659] r8169 0000:02:00.0 eth0: link down [ 6.572660] r8169 0000:02:00.0 eth0: link down [ 6.572699] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready [ 7.579043] it87: Found IT8721F chip at 0x290, revision 3 [ 8.973216] r8169 0000:02:00.0 eth0: link up [ 8.973225] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready