; ModuleID = 'bugpoint-reduced-simplified.bc'
source_filename = "bugpoint-output-3362a25.bc"
target triple = "amdgcn--"

define amdgpu_ps void @main() #0 {
main_body:
  br i1 undef, label %IF, label %ELSE

IF:                                               ; preds = %main_body
  unreachable

ELSE:                                             ; preds = %main_body
  br i1 undef, label %IF553, label %ELSE554

IF553:                                            ; preds = %ELSE
  ret void

ELSE554:                                          ; preds = %ELSE
  br i1 undef, label %IF580, label %ELSE581

IF580:                                            ; preds = %ELSE554
  unreachable

ELSE581:                                          ; preds = %ELSE554
  br i1 undef, label %IF655, label %ELSE656

IF655:                                            ; preds = %ELSE581
  unreachable

ELSE656:                                          ; preds = %ELSE581
  br label %LOOP

LOOP:                                             ; preds = %ENDIF945, %ELSE656
  %temp76.0 = phi float [ undef, %ELSE656 ], [ %25, %ENDIF945 ]
  %0 = phi i32 [ 49, %ELSE656 ], [ 0, %ENDIF945 ]
  br i1 false, label %IF946, label %ENDIF945

IF946:                                            ; preds = %LOOP
  %1 = fmul float undef, %temp76.0
  %2 = fmul float %1, undef
  %3 = fadd float %2, undef
  unreachable

ENDIF945:                                         ; preds = %LOOP
  %4 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %0
  %5 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %0
  %6 = fmul float undef, %4
  %7 = fmul float undef, %5
  %8 = fmul float undef, %6
  %9 = fmul float undef, %7
  %10 = fadd float undef, %8
  %11 = fadd float undef, %9
  %12 = fmul float %10, undef
  %13 = fadd float %12, undef
  %14 = fmul float %11, undef
  %15 = fadd float %14, undef
  %16 = bitcast float %13 to i32
  %17 = bitcast float %15 to i32
  %18 = insertelement <4 x i32> undef, i32 %16, i32 0
  %19 = insertelement <4 x i32> %18, i32 %17, i32 1
  %20 = insertelement <4 x i32> %19, i32 0, i32 2
  %21 = call <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32> %20, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  %22 = extractelement <4 x float> %21, i32 0
  %23 = fmul float undef, %22
  %24 = fmul float %23, undef
  %25 = fadd float %24, %temp76.0
  br label %LOOP
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1

attributes #0 = { "InitialPSInputAddr"="36983" }
attributes #1 = { nounwind readnone }