From e93e306e097103eeee5ddd117a91703bdb9f310b Mon Sep 17 00:00:00 2001 From: Yu Kang Ku Date: Tue, 4 Oct 2016 19:21:38 -0700 Subject: [PATCH] Experiment DDL=0 and latency=45us Change-Id: I47211028b5224504b76dfa372defd42177521878 --- drivers/gpu/drm/i915/intel_pm.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5d39ad2..f836231 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -942,13 +942,13 @@ static void vlv_setup_wm_latency(struct drm_device *dev) struct drm_i915_private *dev_priv = to_i915(dev); /* all latencies in usec */ - dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; + dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 45; dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; if (IS_CHERRYVIEW(dev_priv)) { - dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; - dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; + dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 45; + dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 45; dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; } @@ -1320,10 +1320,10 @@ static void vlv_merge_wm(struct drm_device *dev, if (wm->cxsr) wm->sr = wm_state->sr[wm->level]; - wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; - wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; - wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; - wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; + wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 0; + wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 0; + wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 0; + wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 0; } } -- 1.9.1