(II): DumpRegsBegin (II): VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) (II): VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4) (II): DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled) (II): D_STATE: 0x0000030f (II): DSPCLK_GATE_D: 0x00000000 (II): RENCLK_GATE_D1: 0x00000001 (II): RENCLK_GATE_D2: 0x00000000 (II): SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected) (II): SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected) (II): SDVOUDI: 0x00000000 (II): DSPARB: 0x00015455 (II): DSPFW1: 0x00000000 (II): DSPFW2: 0x00000000 (II): DSPFW3: 0x00000000 (II): ADPA: 0x40009c18 (disabled, pipe B, +hsync, +vsync) (II): LVDS: 0xc0000300 (enabled, pipe B, 18 bit, 1 channel) (II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOA_SRCDIM: 0x00000000 (II): DVOB_SRCDIM: 0x00000000 (II): DVOC_SRCDIM: 0x00000000 (II): PP_CONTROL: 0x00000001 (power target: on) (II): PP_STATUS: 0xc0000008 (on, ready, sequencing idle) (II): PFIT_CONTROL: 0x00000008 (II): PFIT_PGM_RATIOS: 0x00000000 (II): PORT_HOTPLUG_EN: 0x00000000 (II): PORT_HOTPLUG_STAT: 0x00000000 (II): DSPACNTR: 0x58000000 (disabled, pipe A) (II): DSPASTRIDE: 0x00001000 (4096 bytes) (II): DSPAPOS: 0x00000000 (0, 0) (II): DSPASIZE: 0x01df027f (640, 480) (II): DSPABASE: 0x007f0000 (II): DSPASURF: 0x00000000 (II): DSPATILEOFF: 0x00000000 (II): PIPEACONF: 0x00000000 (disabled, single-wide) (II): PIPEASRC: 0x027f01df (640, 480) (II): FBC_CFB_BASE: 0x00000000 (II): FBC_LL_BASE: 0x00000000 (II): FBC_CONTROL: 0x00000000 (II): FBC_COMMAND: 0x00000000 (II): FBC_STATUS: 0x20000000 (II): FBC_CONTROL2: 0x00000000 (II): FBC_FENCE_OFF: 0x00000000 (II): FBC_MOD_NUM: 0x00000000 (II): FPA0: 0x0004140e (n = 4, m1 = 20, m2 = 14) (II): FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): DPLL_A: 0x10860000 (disabled, non-dvo, default clock, DAC/serial mode, p1 = 8, p2 = 4) (II): DPLL_A_MD: 0x00000000 (II): HTOTAL_A: 0x033f027f (640 active, 832 total) (II): HBLANK_A: 0x033f027f (640 start, 832 end) (II): HSYNC_A: 0x02bf0297 (664 start, 704 end) (II): VTOTAL_A: 0x020701df (480 active, 520 total) (II): VBLANK_A: 0x020701e8 (489 start, 520 end) (II): VSYNC_A: 0x01ea01e8 (489 start, 491 end) (II): BCLRPAT_A: 0x00000000 (II): VSYNCSHIFT_A: 0x00000000 (II): DSPBCNTR: 0xd9000000 (enabled, pipe B) (II): DSPBSTRIDE: 0x00001000 (4096 bytes) (II): DSPBPOS: 0x00000000 (0, 0) (II): DSPBSIZE: 0x02ff03ff (1024, 768) (II): DSPBBASE: 0x007f0000 (II): DSPBSURF: 0x00000000 (II): DSPBTILEOFF: 0x00000000 (II): PIPEBCONF: 0x80000000 (enabled, single-wide) (II): PIPEBSRC: 0x03ff02ff (1024, 768) (II): FPB0: 0x0005160e (n = 5, m1 = 22, m2 = 14) (II): FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): DPLL_B: 0x90010000 (enabled, non-dvo, default clock, LVDS mode, p1 = 1, p2 = 14) (II): DPLL_B_MD: 0x00000000 (II): HTOTAL_B: 0x053f03ff (1024 active, 1344 total) (II): HBLANK_B: 0x053f03ff (1024 start, 1344 end) (II): HSYNC_B: 0x049f0417 (1048 start, 1184 end) (II): VTOTAL_B: 0x032502ff (768 active, 806 total) (II): VBLANK_B: 0x03250302 (771 start, 806 end) (II): VSYNC_B: 0x03080302 (771 start, 777 end) (II): BCLRPAT_B: 0x00000000 (II): VSYNCSHIFT_B: 0x00000000 (II): VCLK_DIVISOR_VGA0: 0x00021207 (II): VCLK_DIVISOR_VGA1: 0x00031406 (II): VCLK_POST_DIV: 0x0000888b (II): VGACNTRL: 0x80000000 (disabled) (II): TV_CTL: 0x00000000 (II): TV_DAC: 0x00000000 (II): TV_CSC_Y: 0x00000000 (II): TV_CSC_Y2: 0x00000000 (II): TV_CSC_U: 0x00000000 (II): TV_CSC_U2: 0x00000000 (II): TV_CSC_V: 0x00000000 (II): TV_CSC_V2: 0x00000000 (II): TV_CLR_KNOBS: 0x00000000 (II): TV_CLR_LEVEL: 0x00000000 (II): TV_H_CTL_1: 0x00000000 (II): TV_H_CTL_2: 0x00000000 (II): TV_H_CTL_3: 0x00000000 (II): TV_V_CTL_1: 0x00000000 (II): TV_V_CTL_2: 0x00000000 (II): TV_V_CTL_3: 0x00000000 (II): TV_V_CTL_4: 0x00000000 (II): TV_V_CTL_5: 0x00000000 (II): TV_V_CTL_6: 0x00000000 (II): TV_V_CTL_7: 0x00000000 (II): TV_SC_CTL_1: 0x00000000 (II): TV_SC_CTL_2: 0x00000000 (II): TV_SC_CTL_3: 0x00000000 (II): TV_WIN_POS: 0x00000000 (II): TV_WIN_SIZE: 0x00000000 (II): TV_FILTER_CTL_1: 0x00000000 (II): TV_FILTER_CTL_2: 0x00000000 (II): TV_FILTER_CTL_3: 0x00000000 (II): TV_CC_CONTROL: 0x00000000 (II): TV_CC_DATA: 0x00000000 (II): TV_H_LUMA_0: 0x00000000 (II): TV_H_LUMA_59: 0x00000000 (II): TV_H_CHROMA_0: 0x00000000 (II): TV_H_CHROMA_59: 0x00000000 (II): SR00: 0x03 (II): SR01: 0x01 (II): SR02: 0x0f (II): SR03: 0x00 (II): SR04: 0x0e (II): SR05: 0x00 (II): SR06: 0x00 (II): SR07: 0x00 (II): MSR: 0x67 (II): ARX: 0x30 (II): AR00: 0x00 (II): AR01: 0x01 (II): AR02: 0x02 (II): AR03: 0x03 (II): AR04: 0x04 (II): AR05: 0x05 (II): AR06: 0x14 (II): AR07: 0x07 (II): AR08: 0x38 (II): AR09: 0x39 (II): AR0a: 0x3a (II): AR0b: 0x3b (II): AR0c: 0x3c (II): AR0d: 0x3d (II): AR0e: 0x3e (II): AR0f: 0x3f (II): AR10: 0x0c (II): AR11: 0x00 (II): AR12: 0x0f (II): AR13: 0x08 (II): AR14: 0x00 (II): CR00: 0x5f (II): CR01: 0x4f (II): CR02: 0x50 (II): CR03: 0x82 (II): CR04: 0x55 (II): CR05: 0x81 (II): CR06: 0xbf (II): CR07: 0x1f (II): CR08: 0x00 (II): CR09: 0x4f (II): CR0a: 0x0d (II): CR0b: 0x0e (II): CR0c: 0x00 (II): CR0d: 0x00 (II): CR0e: 0x02 (II): CR0f: 0x30 (II): CR10: 0x9c (II): CR11: 0x0e (II): CR12: 0x8f (II): CR13: 0x28 (II): CR14: 0x1f (II): CR15: 0x96 (II): CR16: 0xb9 (II): CR17: 0xa3 (II): CR18: 0xff (II): CR19: 0x00 (II): CR1a: 0x00 (II): CR1b: 0x00 (II): CR1c: 0x00 (II): CR1d: 0x00 (II): CR1e: 0x00 (II): CR1f: 0x00 (II): CR20: 0x00 (II): CR21: 0x00 (II): CR22: 0x20 (II): CR23: 0x00 (II): CR24: 0x80 (II): pipe A dot 63000 n 4 m1 20 m2 14 p1 8 p2 4 (II): pipe B dot 133224 n 5 m1 22 m2 14 p1 1 p2 14 (II): DumpRegsEnd