[ 0.000000] Linux version 4.9.2+ (root@localhost) (gcc version 5.4.0 (Gentoo 5.4.0 p1.0, pie-0.6.5) ) #29 SMP Tue Jan 10 16:26:00 MSK 2017 [ 0.000000] Command line: BOOT_IMAGE=/vmlinuz-4.9.2+ crypt_root=UUID=b26d3712-3152-4a24-856d-d87602543db9 root=/dev/mapper/root root_trim=yes snd_hda_intel.probe_mask=1 pcie_aspm=force pcie_aspm.policy=powersave usbcore.autosuspend=5 snd_hda_intel.bdl_pos_adj=32 drm.debug=0x1e log_buf_len=1M [ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR' [ 0.000000] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256 [ 0.000000] x86/fpu: xstate_offset[3]: 832, xstate_sizes[3]: 64 [ 0.000000] x86/fpu: xstate_offset[4]: 896, xstate_sizes[4]: 64 [ 0.000000] x86/fpu: Enabled xstate features 0x1f, context size is 960 bytes, using 'compacted' format. [ 0.000000] x86/fpu: Using 'eager' FPU context switches. [ 0.000000] e820: BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable [ 0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000000059000-0x000000000009efff] usable [ 0.000000] BIOS-e820: [mem 0x000000000009f000-0x000000000009ffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000681d9fff] usable [ 0.000000] BIOS-e820: [mem 0x00000000681da000-0x00000000681dafff] ACPI NVS [ 0.000000] BIOS-e820: [mem 0x00000000681db000-0x00000000681dbfff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000681dc000-0x000000007a191fff] usable [ 0.000000] BIOS-e820: [mem 0x000000007a192000-0x000000007a51ffff] reserved [ 0.000000] BIOS-e820: [mem 0x000000007a520000-0x000000007a55dfff] ACPI data [ 0.000000] BIOS-e820: [mem 0x000000007a55e000-0x000000007ac04fff] ACPI NVS [ 0.000000] BIOS-e820: [mem 0x000000007ac05000-0x000000007b48efff] reserved [ 0.000000] BIOS-e820: [mem 0x000000007b48f000-0x000000007b4fefff] type 20 [ 0.000000] BIOS-e820: [mem 0x000000007b4ff000-0x000000007b4fffff] usable [ 0.000000] BIOS-e820: [mem 0x000000007b500000-0x000000007b5fffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000fe000000-0x00000000fe010fff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000047e7fffff] usable [ 0.000000] NX (Execute Disable) protection: active [ 0.000000] efi: EFI v2.40 by American Megatrends [ 0.000000] efi: ACPI=0x7a52d000 ACPI 2.0=0x7a52d000 SMBIOS=0xf05e0 SMBIOS 3.0=0xf0600 ESRT=0x7b261598 MPS=0xfcbc0 [ 0.000000] SMBIOS 3.0.0 present. [ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved [ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable [ 0.000000] e820: last_pfn = 0x47e800 max_arch_pfn = 0x400000000 [ 0.000000] MTRR default type: write-back [ 0.000000] MTRR fixed ranges enabled: [ 0.000000] 00000-9FFFF write-back [ 0.000000] A0000-BFFFF uncachable [ 0.000000] C0000-FFFFF write-protect [ 0.000000] MTRR variable ranges enabled: [ 0.000000] 0 base 0080000000 mask 7F80000000 uncachable [ 0.000000] 1 base 007E000000 mask 7FFE000000 uncachable [ 0.000000] 2 base 007D000000 mask 7FFF000000 uncachable [ 0.000000] 3 disabled [ 0.000000] 4 disabled [ 0.000000] 5 disabled [ 0.000000] 6 disabled [ 0.000000] 7 disabled [ 0.000000] 8 disabled [ 0.000000] 9 disabled [ 0.000000] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WC UC- WT [ 0.000000] e820: last_pfn = 0x7b500 max_arch_pfn = 0x400000000 [ 0.000000] found SMP MP-table at [mem 0x000fce70-0x000fce7f] mapped at [ffffa2a1c00fce70] [ 0.000000] esrt: Reserving ESRT space from 0x000000007b261598 to 0x000000007b2615d0. [ 0.000000] Scanning 1 areas for low memory corruption [ 0.000000] Base memory trampoline at [ffffa2a1c0097000] 97000 size 24576 [ 0.000000] Using GB pages for direct mapping [ 0.000000] BRK [0x33157b000, 0x33157bfff] PGTABLE [ 0.000000] BRK [0x33157c000, 0x33157cfff] PGTABLE [ 0.000000] BRK [0x33157d000, 0x33157dfff] PGTABLE [ 0.000000] BRK [0x33157e000, 0x33157efff] PGTABLE [ 0.000000] BRK [0x33157f000, 0x33157ffff] PGTABLE [ 0.000000] BRK [0x331580000, 0x331580fff] PGTABLE [ 0.000000] BRK [0x331581000, 0x331581fff] PGTABLE [ 0.000000] BRK [0x331582000, 0x331582fff] PGTABLE [ 0.000000] BRK [0x331583000, 0x331583fff] PGTABLE [ 0.000000] log_buf_len: 1048576 bytes [ 0.000000] early log buf free: 257032(98%) [ 0.000000] RAMDISK: [mem 0x37861000-0x37c27fff] [ 0.000000] ACPI: Early table checksum verification disabled [ 0.000000] ACPI: RSDP 0x000000007A52D000 000024 (v02 DELL ) [ 0.000000] ACPI: XSDT 0x000000007A52D0B8 0000F4 (v01 DELL CBX3 01072009 AMI 00010013) [ 0.000000] ACPI: FACP 0x000000007A551A48 00010C (v05 DELL CBX3 01072009 AMI 00010013) [ 0.000000] ACPI: DSDT 0x000000007A52D240 024807 (v02 DELL CBX3 01072009 INTL 20160422) [ 0.000000] ACPI: FACS 0x000000007ABFEF80 000040 [ 0.000000] ACPI: APIC 0x000000007A551B58 000084 (v03 DELL CBX3 01072009 AMI 00010013) [ 0.000000] ACPI: FPDT 0x000000007A551BE0 000044 (v01 DELL CBX3 01072009 AMI 00010013) [ 0.000000] ACPI: FIDT 0x000000007A551C28 00009C (v01 DELL CBX3 01072009 AMI 00010013) [ 0.000000] ACPI: MCFG 0x000000007A551CC8 00003C (v01 DELL CBX3 01072009 MSFT 00000097) [ 0.000000] ACPI: HPET 0x000000007A551D08 000038 (v01 DELL CBX3 01072009 AMI. 0005000B) [ 0.000000] ACPI: SSDT 0x000000007A551D40 000372 (v01 SataRe SataTabl 00001000 INTL 20160422) [ 0.000000] ACPI: BOOT 0x000000007A5520B8 000028 (v01 DELL CBX3 01072009 AMI 00010013) [ 0.000000] ACPI: SSDT 0x000000007A5520E0 0012E1 (v02 SaSsdt SaSsdt 00003000 INTL 20160422) [ 0.000000] ACPI: HPET 0x000000007A5533C8 000038 (v01 INTEL KBL-ULT 00000001 MSFT 0000005F) [ 0.000000] ACPI: SSDT 0x000000007A553400 000CDB (v02 INTEL xh_rvp07 00000000 INTL 20160422) [ 0.000000] ACPI: UEFI 0x000000007A5540E0 000042 (v01 00000000 00000000) [ 0.000000] ACPI: SSDT 0x000000007A554128 000EDE (v02 CpuRef CpuSsdt 00003000 INTL 20160422) [ 0.000000] ACPI: LPIT 0x000000007A555008 000094 (v01 INTEL KBL-ULT 00000000 MSFT 0000005F) [ 0.000000] ACPI: WSMT 0x000000007A5550A0 000028 (v01 INTEL KBL-ULT 00000000 MSFT 0000005F) [ 0.000000] ACPI: SSDT 0x000000007A5550C8 00029F (v02 INTEL sensrhub 00000000 INTL 20160422) [ 0.000000] ACPI: SSDT 0x000000007A555368 003002 (v02 INTEL PtidDevc 00001000 INTL 20160422) [ 0.000000] ACPI: DBGP 0x000000007A558370 000034 (v01 INTEL 00000002 MSFT 0000005F) [ 0.000000] ACPI: DBG2 0x000000007A5583A8 000054 (v00 INTEL 00000002 MSFT 0000005F) [ 0.000000] ACPI: MSDM 0x000000007A558400 000055 (v03 DELL CBX3 06222004 AMI 00010013) [ 0.000000] ACPI: SSDT 0x000000007A558458 004605 (v02 DptfTa DptfTabl 00001000 INTL 20160422) [ 0.000000] ACPI: SLIC 0x000000007A55CA60 000176 (v03 DELL CBX3 01072009 MSFT 00010013) [ 0.000000] ACPI: DMAR 0x000000007A55CBD8 0000F0 (v01 INTEL KBL 00000001 INTL 00000001) [ 0.000000] ACPI: NHLT 0x000000007A55CCC8 00002D (v00 INTEL EDK2 00000002 01000013) [ 0.000000] ACPI: ASF! 0x000000007A55CCF8 0000A0 (v32 INTEL HCG 00000001 TFSM 000F4240) [ 0.000000] ACPI: BGRT 0x000000007A55CD98 000038 (v00 \xfffffff3\xffffffee 01072009 AMI 00010013) [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] No NUMA configuration found [ 0.000000] Faking a node at [mem 0x0000000000000000-0x000000047e7fffff] [ 0.000000] NODE_DATA(0) allocated [mem 0x47e6fc000-0x47e6fffff] [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000000001000-0x0000000000ffffff] [ 0.000000] DMA32 [mem 0x0000000001000000-0x00000000ffffffff] [ 0.000000] Normal [mem 0x0000000100000000-0x000000047e7fffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000000001000-0x0000000000057fff] [ 0.000000] node 0: [mem 0x0000000000059000-0x000000000009efff] [ 0.000000] node 0: [mem 0x0000000000100000-0x00000000681d9fff] [ 0.000000] node 0: [mem 0x00000000681dc000-0x000000007a191fff] [ 0.000000] node 0: [mem 0x000000007b4ff000-0x000000007b4fffff] [ 0.000000] node 0: [mem 0x0000000100000000-0x000000047e7fffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000047e7fffff] [ 0.000000] On node 0 totalpages: 4163886 [ 0.000000] DMA zone: 64 pages used for memmap [ 0.000000] DMA zone: 25 pages reserved [ 0.000000] DMA zone: 3997 pages, LIFO batch:0 [ 0.000000] DMA32 zone: 7751 pages used for memmap [ 0.000000] DMA32 zone: 496017 pages, LIFO batch:31 [ 0.000000] Normal zone: 57248 pages used for memmap [ 0.000000] Normal zone: 3663872 pages, LIFO batch:31 [ 0.000000] Reserving Intel graphics memory at 0x000000007d800000-0x000000007f7fffff [ 0.000000] ACPI: PM-Timer IO Port: 0x1808 [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1]) [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1]) [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1]) [ 0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-119 [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) [ 0.000000] ACPI: IRQ0 used by override. [ 0.000000] ACPI: IRQ9 used by override. [ 0.000000] Using ACPI (MADT) for SMP configuration information [ 0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000 [ 0.000000] smpboot: Allowing 4 CPUs, 0 hotplug CPUs [ 0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff] [ 0.000000] PM: Registered nosave memory: [mem 0x00058000-0x00058fff] [ 0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff] [ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000fffff] [ 0.000000] PM: Registered nosave memory: [mem 0x681da000-0x681dafff] [ 0.000000] PM: Registered nosave memory: [mem 0x681db000-0x681dbfff] [ 0.000000] PM: Registered nosave memory: [mem 0x7a192000-0x7a51ffff] [ 0.000000] PM: Registered nosave memory: [mem 0x7a520000-0x7a55dfff] [ 0.000000] PM: Registered nosave memory: [mem 0x7a55e000-0x7ac04fff] [ 0.000000] PM: Registered nosave memory: [mem 0x7ac05000-0x7b48efff] [ 0.000000] PM: Registered nosave memory: [mem 0x7b48f000-0x7b4fefff] [ 0.000000] PM: Registered nosave memory: [mem 0x7b500000-0x7b5fffff] [ 0.000000] PM: Registered nosave memory: [mem 0x7b600000-0x7d7fffff] [ 0.000000] PM: Registered nosave memory: [mem 0x7d800000-0x7f7fffff] [ 0.000000] PM: Registered nosave memory: [mem 0x7f800000-0xdfffffff] [ 0.000000] PM: Registered nosave memory: [mem 0xe0000000-0xefffffff] [ 0.000000] PM: Registered nosave memory: [mem 0xf0000000-0xfdffffff] [ 0.000000] PM: Registered nosave memory: [mem 0xfe000000-0xfe010fff] [ 0.000000] PM: Registered nosave memory: [mem 0xfe011000-0xfebfffff] [ 0.000000] PM: Registered nosave memory: [mem 0xfec00000-0xfec00fff] [ 0.000000] PM: Registered nosave memory: [mem 0xfec01000-0xfedfffff] [ 0.000000] PM: Registered nosave memory: [mem 0xfee00000-0xfee00fff] [ 0.000000] PM: Registered nosave memory: [mem 0xfee01000-0xfeffffff] [ 0.000000] PM: Registered nosave memory: [mem 0xff000000-0xffffffff] [ 0.000000] e820: [mem 0x7f800000-0xdfffffff] available for PCI devices [ 0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns [ 0.000000] setup_percpu: NR_CPUS:4 nr_cpumask_bits:4 nr_cpu_ids:4 nr_node_ids:1 [ 0.000000] percpu: Embedded 34 pages/cpu @ffffa2a63e400000 s101016 r8192 d30056 u524288 [ 0.000000] pcpu-alloc: s101016 r8192 d30056 u524288 alloc=1*2097152 [ 0.000000] pcpu-alloc: [0] 0 1 2 3 [ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 4098798 [ 0.000000] Policy zone: Normal [ 0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz-4.9.2+ crypt_root=UUID=b26d3712-3152-4a24-856d-d87602543db9 root=/dev/mapper/root root_trim=yes snd_hda_intel.probe_mask=1 pcie_aspm=force pcie_aspm.policy=powersave usbcore.autosuspend=5 snd_hda_intel.bdl_pos_adj=32 drm.debug=0x1e log_buf_len=1M [ 0.000000] PCIe ASPM is forcibly enabled [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) [ 0.000000] Calgary: detecting Calgary via BIOS EBDA area [ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing! [ 0.000000] Memory: 16203472K/16655544K available (9226K kernel code, 1296K rwdata, 3868K rodata, 1432K init, 788K bss, 452072K reserved, 0K cma-reserved) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 [ 0.000000] Hierarchical RCU implementation. [ 0.000000] Build-time adjustment of leaf fanout to 64. [ 0.000000] NR_IRQS:4352 nr_irqs:1024 16 [ 0.000000] spurious 8259A interrupt: IRQ7. [ 0.000000] Console: colour dummy device 80x25 [ 0.000000] console [tty0] enabled [ 0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635855245 ns [ 0.000000] hpet clockevent registered [ 0.000000] tsc: Detected 2900.000 MHz processor [ 0.000038] Calibrating delay loop (skipped), value calculated using timer frequency.. 5808.00 BogoMIPS (lpj=2904000) [ 0.000044] pid_max: default: 32768 minimum: 301 [ 0.000048] ACPI: Core revision 20160831 [ 0.031691] ACPI: 8 ACPI AML tables successfully acquired and loaded [ 0.032501] Security Framework initialized [ 0.032506] SELinux: Initializing. [ 0.032512] SELinux: Starting in permissive mode [ 0.033235] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes) [ 0.036359] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes) [ 0.037735] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes) [ 0.037749] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes) [ 0.038070] CPU: Physical Processor ID: 0 [ 0.038073] CPU: Processor Core ID: 0 [ 0.038079] ENERGY_PERF_BIAS: Set to 'normal', was 'performance' [ 0.038081] ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8) [ 0.038088] mce: CPU supports 8 MCE banks [ 0.038100] mce: [Hardware Error]: Machine check events logged [ 0.038108] CPU0: Thermal monitoring enabled (TM1) [ 0.038125] process: using mwait in idle threads [ 0.038130] Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8 [ 0.038133] Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4 [ 0.039160] Freeing SMP alternatives memory: 32K (ffffffffb34ac000 - ffffffffb34b4000) [ 0.045366] ftrace: allocating 34362 entries in 135 pages [ 0.060360] smpboot: Max logical packages: 2 [ 0.060386] DMAR: Host address width 39 [ 0.060389] DMAR: DRHD base: 0x000000fed90000 flags: 0x0 [ 0.060399] DMAR: dmar0: reg_base_addr fed90000 ver 1:0 cap 1c0000c40660462 ecap 19e2ff0505e [ 0.060403] DMAR: DRHD base: 0x000000fed91000 flags: 0x1 [ 0.060408] DMAR: dmar1: reg_base_addr fed91000 ver 1:0 cap d2008c40660462 ecap f050da [ 0.060413] DMAR: RMRR base: 0x0000007a261000 end: 0x0000007a280fff [ 0.060416] DMAR: RMRR base: 0x0000007d000000 end: 0x0000007f7fffff [ 0.060419] DMAR: ANDD device: 1 name: \_SB.PCI0.I2C0 [ 0.060421] DMAR: ANDD device: 2 name: \_SB.PCI0.I2C1 [ 0.060425] DMAR-IR: IOAPIC id 2 under DRHD base 0xfed91000 IOMMU 1 [ 0.060428] DMAR-IR: HPET id 0 under DRHD base 0xfed91000 [ 0.062035] DMAR-IR: Enabled IRQ remapping in xapic mode [ 0.066118] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 [ 0.076129] TSC deadline timer enabled [ 0.076135] smpboot: CPU0: Intel(R) Core(TM) i7-7500U CPU @ 2.70GHz (family: 0x6, model: 0x8e, stepping: 0x9) [ 0.076142] Performance Events: PEBS fmt3+, Skylake events, 32-deep LBR, full-width counters, Intel PMU driver. [ 0.076174] ... version: 4 [ 0.076176] ... bit width: 48 [ 0.076178] ... generic registers: 4 [ 0.076180] ... value mask: 0000ffffffffffff [ 0.076183] ... max period: 00007fffffffffff [ 0.076185] ... fixed-purpose events: 3 [ 0.076187] ... event mask: 000000070000000f [ 0.076449] x86: Booting SMP configuration: [ 0.076453] .... node #0, CPUs: #1 #2 #3 [ 0.262422] x86: Booted up 1 node, 4 CPUs [ 0.262430] smpboot: Total of 4 processors activated (23245.66 BogoMIPS) [ 0.266818] devtmpfs: initialized [ 0.267094] PM: Registering ACPI NVS region [mem 0x681da000-0x681dafff] (4096 bytes) [ 0.267099] PM: Registering ACPI NVS region [mem 0x7a55e000-0x7ac04fff] (6975488 bytes) [ 0.267231] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns [ 0.267265] pinctrl core: initialized pinctrl subsystem [ 0.267428] RTC time: 13:53:52, date: 01/10/17 [ 0.267489] NET: Registered protocol family 16 [ 0.272447] cpuidle: using governor menu [ 0.272533] Simple Boot Flag at 0x47 set to 0x80 [ 0.272562] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it [ 0.272570] ACPI: bus type PCI registered [ 0.272624] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) [ 0.272629] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820 [ 0.272641] PCI: Using configuration type 1 for base access [ 0.272648] dmi type 0xB1 record - unknown flag [ 0.278527] HugeTLB registered 2 MB page size, pre-allocated 0 pages [ 0.278651] ACPI: Added _OSI(Module Device) [ 0.278654] ACPI: Added _OSI(Processor Device) [ 0.278657] ACPI: Added _OSI(3.0 _SCP Extensions) [ 0.278659] ACPI: Added _OSI(Processor Aggregator Device) [ 0.279894] ACPI: Executed 31 blocks of module-level executable AML code [ 0.288569] ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored [ 0.350632] ACPI: Dynamic OEM Table Load: [ 0.350655] ACPI: SSDT 0xFFFFA2A62BBE1800 0006F6 (v02 PmRef Cpu0Ist 00003000 INTL 20160422) [ 0.350793] ACPI: Executed 1 blocks of module-level executable AML code [ 0.350849] ACPI: \_PR_.CPU0: _OSC native thermal LVT Acked [ 0.351634] ACPI: Dynamic OEM Table Load: [ 0.351641] ACPI: SSDT 0xFFFFA2A62B4DC800 0003FF (v02 PmRef Cpu0Cst 00003001 INTL 20160422) [ 0.351762] ACPI: Executed 1 blocks of module-level executable AML code [ 0.352075] ACPI: Dynamic OEM Table Load: [ 0.352082] ACPI: SSDT 0xFFFFA2A62BBE2000 00065C (v02 PmRef ApIst 00003000 INTL 20160422) [ 0.352374] ACPI: Executed 1 blocks of module-level executable AML code [ 0.352502] ACPI: Dynamic OEM Table Load: [ 0.352508] ACPI: SSDT 0xFFFFA2A62B58D200 00018A (v02 PmRef ApCst 00003000 INTL 20160422) [ 0.352632] ACPI: Executed 1 blocks of module-level executable AML code [ 0.353693] ACPI : EC: EC started [ 0.372099] ACPI: \_SB_.PCI0.LPCB.ECDV: Used as first EC [ 0.372103] ACPI: \_SB_.PCI0.LPCB.ECDV: GPE=0x14, EC_CMD/EC_SC=0x934, EC_DATA=0x930 [ 0.372108] ACPI: \_SB_.PCI0.LPCB.ECDV: Used as boot DSDT EC to handle transactions [ 0.372112] ACPI: Interpreter enabled [ 0.372161] ACPI: (supports S0 S3 S4 S5) [ 0.372164] ACPI: Using IOAPIC for interrupt routing [ 0.372199] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.379335] ACPI: Power Resource [WRST] (on) [ 0.379641] ACPI: Power Resource [WRST] (on) [ 0.379937] ACPI: Power Resource [WRST] (on) [ 0.380236] ACPI: Power Resource [WRST] (on) [ 0.380541] ACPI: Power Resource [WRST] (on) [ 0.380841] ACPI: Power Resource [WRST] (on) [ 0.381324] ACPI: Power Resource [WRST] (on) [ 0.381619] ACPI: Power Resource [WRST] (on) [ 0.381914] ACPI: Power Resource [WRST] (on) [ 0.382367] ACPI: Power Resource [WRST] (on) [ 0.382738] ACPI: Power Resource [WRST] (on) [ 0.383035] ACPI: Power Resource [WRST] (on) [ 0.383334] ACPI: Power Resource [WRST] (on) [ 0.383634] ACPI: Power Resource [WRST] (on) [ 0.383928] ACPI: Power Resource [WRST] (on) [ 0.384224] ACPI: Power Resource [WRST] (on) [ 0.384528] ACPI: Power Resource [WRST] (on) [ 0.385659] ACPI: Power Resource [WRST] (on) [ 0.385957] ACPI: Power Resource [WRST] (on) [ 0.386260] ACPI: Power Resource [WRST] (on) [ 0.406343] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe]) [ 0.406350] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] [ 0.406381] acpi PNP0A08:00: _OSC failed (AE_ERROR); disabling ASPM [ 0.406670] PCI host bridge to bus 0000:00 [ 0.406674] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] [ 0.406677] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] [ 0.406680] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] [ 0.406685] pci_bus 0000:00: root bus resource [mem 0x7f800000-0xdfffffff window] [ 0.406689] pci_bus 0000:00: root bus resource [mem 0xfd000000-0xfe7fffff window] [ 0.406693] pci_bus 0000:00: root bus resource [bus 00-fe] [ 0.406706] pci 0000:00:00.0: [8086:5904] type 00 class 0x060000 [ 0.406833] pci 0000:00:02.0: [8086:5916] type 00 class 0x030000 [ 0.406842] pci 0000:00:02.0: reg 0x10: [mem 0xdb000000-0xdbffffff 64bit] [ 0.406848] pci 0000:00:02.0: reg 0x18: [mem 0x90000000-0x9fffffff 64bit pref] [ 0.406853] pci 0000:00:02.0: reg 0x20: [io 0xf000-0xf03f] [ 0.406989] pci 0000:00:04.0: [8086:1903] type 00 class 0x118000 [ 0.407000] pci 0000:00:04.0: reg 0x10: [mem 0xdc420000-0xdc427fff 64bit] [ 0.407198] pci 0000:00:14.0: [8086:9d2f] type 00 class 0x0c0330 [ 0.407217] pci 0000:00:14.0: reg 0x10: [mem 0xdc410000-0xdc41ffff 64bit] [ 0.407287] pci 0000:00:14.0: PME# supported from D3hot D3cold [ 0.407434] pci 0000:00:14.0: System wakeup disabled by ACPI [ 0.407479] pci 0000:00:14.2: [8086:9d31] type 00 class 0x118000 [ 0.407497] pci 0000:00:14.2: reg 0x10: [mem 0xdc434000-0xdc434fff 64bit] [ 0.407745] pci 0000:00:15.0: [8086:9d60] type 00 class 0x118000 [ 0.407953] pci 0000:00:15.0: reg 0x10: [mem 0xdc433000-0xdc433fff 64bit] [ 0.408902] pci 0000:00:15.1: [8086:9d61] type 00 class 0x118000 [ 0.409111] pci 0000:00:15.1: reg 0x10: [mem 0xdc432000-0xdc432fff 64bit] [ 0.409999] pci 0000:00:16.0: [8086:9d3a] type 00 class 0x078000 [ 0.410019] pci 0000:00:16.0: reg 0x10: [mem 0xdc431000-0xdc431fff 64bit] [ 0.410092] pci 0000:00:16.0: PME# supported from D3hot [ 0.410244] pci 0000:00:1c.0: [8086:9d10] type 01 class 0x060400 [ 0.410315] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold [ 0.410425] pci 0000:00:1c.0: System wakeup disabled by ACPI [ 0.410473] pci 0000:00:1c.4: [8086:9d14] type 01 class 0x060400 [ 0.410542] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold [ 0.410654] pci 0000:00:1c.4: System wakeup disabled by ACPI [ 0.410694] pci 0000:00:1c.5: [8086:9d15] type 01 class 0x060400 [ 0.410765] pci 0000:00:1c.5: PME# supported from D0 D3hot D3cold [ 0.410875] pci 0000:00:1c.5: System wakeup disabled by ACPI [ 0.410928] pci 0000:00:1d.0: [8086:9d18] type 01 class 0x060400 [ 0.410998] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold [ 0.411106] pci 0000:00:1d.0: System wakeup disabled by ACPI [ 0.411168] pci 0000:00:1f.0: [8086:9d58] type 00 class 0x060100 [ 0.411369] pci 0000:00:1f.2: [8086:9d21] type 00 class 0x058000 [ 0.411378] pci 0000:00:1f.2: reg 0x10: [mem 0xdc42c000-0xdc42ffff] [ 0.411519] pci 0000:00:1f.3: [8086:9d71] type 00 class 0x040380 [ 0.411540] pci 0000:00:1f.3: reg 0x10: [mem 0xdc428000-0xdc42bfff 64bit] [ 0.411565] pci 0000:00:1f.3: reg 0x20: [mem 0xdc400000-0xdc40ffff 64bit] [ 0.411612] pci 0000:00:1f.3: PME# supported from D3hot D3cold [ 0.411749] pci 0000:00:1f.3: System wakeup disabled by ACPI [ 0.411785] pci 0000:00:1f.4: [8086:9d23] type 00 class 0x0c0500 [ 0.411833] pci 0000:00:1f.4: reg 0x10: [mem 0xdc430000-0xdc4300ff 64bit] [ 0.411903] pci 0000:00:1f.4: reg 0x20: [io 0xf040-0xf05f] [ 0.412111] pci 0000:00:1c.0: PCI bridge to [bus 01-39] [ 0.412118] pci 0000:00:1c.0: bridge window [mem 0xc4000000-0xda0fffff] [ 0.412122] pci 0000:00:1c.0: bridge window [mem 0xa0000000-0xc1ffffff 64bit pref] [ 0.412416] pci 0000:3a:00.0: [168c:003e] type 00 class 0x028000 [ 0.412643] pci 0000:3a:00.0: reg 0x10: [mem 0xdc000000-0xdc1fffff 64bit] [ 0.413783] pci 0000:3a:00.0: PME# supported from D0 D3hot D3cold [ 0.414383] pci 0000:3a:00.0: System wakeup disabled by ACPI [ 0.417367] pci 0000:00:1c.4: PCI bridge to [bus 3a] [ 0.417374] pci 0000:00:1c.4: bridge window [mem 0xdc000000-0xdc1fffff] [ 0.417493] pci 0000:3b:00.0: [10ec:525a] type 00 class 0xff0000 [ 0.417520] pci 0000:3b:00.0: reg 0x14: [mem 0xdc300000-0xdc300fff] [ 0.417633] pci 0000:3b:00.0: supports D1 D2 [ 0.417634] pci 0000:3b:00.0: PME# supported from D1 D2 D3hot D3cold [ 0.417723] pci 0000:3b:00.0: System wakeup disabled by ACPI [ 0.420209] pci 0000:00:1c.5: PCI bridge to [bus 3b] [ 0.420215] pci 0000:00:1c.5: bridge window [mem 0xdc300000-0xdc3fffff] [ 0.420592] pci 0000:3c:00.0: [14a4:2200] type 00 class 0x010802 [ 0.420611] pci 0000:3c:00.0: reg 0x10: [mem 0xdc200000-0xdc203fff 64bit] [ 0.420799] pci 0000:3c:00.0: System wakeup disabled by ACPI [ 0.424579] pci 0000:00:1d.0: PCI bridge to [bus 3c] [ 0.424585] pci 0000:00:1d.0: bridge window [mem 0xdc200000-0xdc2fffff] [ 0.426593] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.426643] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 *10 11 12 14 15) [ 0.426697] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.426748] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.426798] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.426845] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.426892] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.426939] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.432077] ACPI: Enabled 5 GPEs in block 00 to 7F [ 0.433111] ACPI : EC: event unblocked [ 0.433138] ACPI: \_SB_.PCI0.LPCB.ECDV: GPE=0x14, EC_CMD/EC_SC=0x934, EC_DATA=0x930 [ 0.433143] ACPI: \_SB_.PCI0.LPCB.ECDV: Used as boot DSDT EC to handle transactions and events [ 0.433266] vgaarb: setting as boot device: PCI:0000:00:02.0 [ 0.433270] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none [ 0.433276] vgaarb: loaded [ 0.433278] vgaarb: bridge control possible 0000:00:02.0 [ 0.433325] SCSI subsystem initialized [ 0.433360] libata version 3.00 loaded. [ 0.433394] ACPI: bus type USB registered [ 0.433417] usbcore: registered new interface driver usbfs [ 0.433426] usbcore: registered new interface driver hub [ 0.433439] usbcore: registered new device driver usb [ 0.433459] pps_core: LinuxPPS API ver. 1 registered [ 0.433462] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti [ 0.433471] PTP clock support registered [ 0.433497] Registered efivars operations [ 0.439933] wmi: Mapper loaded [ 0.439987] Advanced Linux Sound Architecture Driver Initialized. [ 0.439998] PCI: Using ACPI for IRQ routing [ 0.464980] PCI: pci_cache_line_size set to 64 bytes [ 0.466081] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff] [ 0.466082] e820: reserve RAM buffer [mem 0x0009f000-0x0009ffff] [ 0.466082] e820: reserve RAM buffer [mem 0x681da000-0x6bffffff] [ 0.466083] e820: reserve RAM buffer [mem 0x7a192000-0x7bffffff] [ 0.466084] e820: reserve RAM buffer [mem 0x7b500000-0x7bffffff] [ 0.466085] e820: reserve RAM buffer [mem 0x47e800000-0x47fffffff] [ 0.466245] NetLabel: Initializing [ 0.466249] NetLabel: domain hash size = 128 [ 0.466251] NetLabel: protocols = UNLABELED CIPSOv4 [ 0.466264] NetLabel: unlabeled traffic allowed by default [ 0.466435] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 [ 0.466442] hpet0: 8 comparators, 64-bit 24.000000 MHz counter [ 0.468511] clocksource: Switched to clocksource hpet [ 0.477410] VFS: Disk quotas dquot_6.6.0 [ 0.477425] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) [ 0.477481] pnp: PnP ACPI init [ 0.477731] system 00:00: [io 0x0680-0x069f] has been reserved [ 0.477741] system 00:00: [io 0xffff] has been reserved [ 0.477745] system 00:00: [io 0xffff] has been reserved [ 0.477749] system 00:00: [io 0xffff] has been reserved [ 0.477752] system 00:00: [io 0x1800-0x18fe] has been reserved [ 0.477755] system 00:00: [io 0x164e-0x164f] has been reserved [ 0.477761] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.477844] pnp 00:01: Plug and Play ACPI device, IDs PNP0b00 (active) [ 0.477892] system 00:02: [io 0x1854-0x1857] has been reserved [ 0.477897] system 00:02: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active) [ 0.478025] pnp 00:03: Plug and Play ACPI device, IDs PNP0303 (active) [ 0.478051] pnp 00:04: Plug and Play ACPI device, IDs DLL075b PNP0f13 (active) [ 0.478268] system 00:05: [mem 0xfed10000-0xfed17fff] has been reserved [ 0.478272] system 00:05: [mem 0xfed18000-0xfed18fff] has been reserved [ 0.478275] system 00:05: [mem 0xfed19000-0xfed19fff] has been reserved [ 0.478279] system 00:05: [mem 0xe0000000-0xefffffff] has been reserved [ 0.478283] system 00:05: [mem 0xfed20000-0xfed3ffff] has been reserved [ 0.478288] system 00:05: [mem 0xfed90000-0xfed93fff] could not be reserved [ 0.478291] system 00:05: [mem 0xfed45000-0xfed8ffff] has been reserved [ 0.478295] system 00:05: [mem 0xff000000-0xffffffff] has been reserved [ 0.478299] system 00:05: [mem 0xfee00000-0xfeefffff] could not be reserved [ 0.478303] system 00:05: [mem 0xdffe0000-0xdfffffff] has been reserved [ 0.478307] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.478347] system 00:06: [mem 0xfd000000-0xfdabffff] has been reserved [ 0.478351] system 00:06: [mem 0xfdad0000-0xfdadffff] has been reserved [ 0.478355] system 00:06: [mem 0xfdb00000-0xfdffffff] has been reserved [ 0.478359] system 00:06: [mem 0xfe000000-0xfe01ffff] could not be reserved [ 0.478363] system 00:06: [mem 0xfe036000-0xfe03bfff] has been reserved [ 0.478367] system 00:06: [mem 0xfe03d000-0xfe3fffff] has been reserved [ 0.478370] system 00:06: [mem 0xfe410000-0xfe7fffff] has been reserved [ 0.478374] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.478640] system 00:07: [io 0xff00-0xfffe] has been reserved [ 0.478652] system 00:07: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.479532] system 00:08: [mem 0xfe029000-0xfe029fff] has been reserved [ 0.479536] system 00:08: [mem 0xfe028000-0xfe028fff] has been reserved [ 0.479544] system 00:08: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.481331] pnp: PnP ACPI: found 9 devices [ 0.488056] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns [ 0.488076] pci 0000:00:1c.0: bridge window [io 0x1000-0x0fff] to [bus 01-39] add_size 1000 [ 0.488104] pci 0000:00:1c.0: res[13]=[io 0x1000-0x0fff] res_to_dev_res add_size 1000 min_align 1000 [ 0.488105] pci 0000:00:1c.0: res[13]=[io 0x1000-0x1fff] res_to_dev_res add_size 1000 min_align 1000 [ 0.488108] pci 0000:00:1c.0: BAR 13: assigned [io 0x2000-0x2fff] [ 0.488112] pci 0000:00:1c.0: PCI bridge to [bus 01-39] [ 0.488121] pci 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 0.488127] pci 0000:00:1c.0: bridge window [mem 0xc4000000-0xda0fffff] [ 0.488132] pci 0000:00:1c.0: bridge window [mem 0xa0000000-0xc1ffffff 64bit pref] [ 0.488143] pci 0000:00:1c.4: PCI bridge to [bus 3a] [ 0.488149] pci 0000:00:1c.4: bridge window [mem 0xdc000000-0xdc1fffff] [ 0.488158] pci 0000:00:1c.5: PCI bridge to [bus 3b] [ 0.488163] pci 0000:00:1c.5: bridge window [mem 0xdc300000-0xdc3fffff] [ 0.488171] pci 0000:00:1d.0: PCI bridge to [bus 3c] [ 0.488184] pci 0000:00:1d.0: bridge window [mem 0xdc200000-0xdc2fffff] [ 0.488193] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7 window] [ 0.488194] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff window] [ 0.488195] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window] [ 0.488196] pci_bus 0000:00: resource 7 [mem 0x7f800000-0xdfffffff window] [ 0.488197] pci_bus 0000:00: resource 8 [mem 0xfd000000-0xfe7fffff window] [ 0.488198] pci_bus 0000:01: resource 0 [io 0x2000-0x2fff] [ 0.488199] pci_bus 0000:01: resource 1 [mem 0xc4000000-0xda0fffff] [ 0.488199] pci_bus 0000:01: resource 2 [mem 0xa0000000-0xc1ffffff 64bit pref] [ 0.488200] pci_bus 0000:3a: resource 1 [mem 0xdc000000-0xdc1fffff] [ 0.488206] pci_bus 0000:3b: resource 1 [mem 0xdc300000-0xdc3fffff] [ 0.488208] pci_bus 0000:3c: resource 1 [mem 0xdc200000-0xdc2fffff] [ 0.488334] NET: Registered protocol family 2 [ 0.488482] TCP established hash table entries: 131072 (order: 8, 1048576 bytes) [ 0.488690] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes) [ 0.488848] TCP: Hash tables configured (established 131072 bind 65536) [ 0.488870] UDP hash table entries: 8192 (order: 6, 262144 bytes) [ 0.488912] UDP-Lite hash table entries: 8192 (order: 6, 262144 bytes) [ 0.488993] NET: Registered protocol family 1 [ 0.489007] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff] [ 0.490562] PCI: CLS 0 bytes, default 64 [ 0.490594] Unpacking initramfs... [ 0.891178] Freeing initrd memory: 3868K (ffffa2a1f7861000 - ffffa2a1f7c28000) [ 0.891210] DMAR: ACPI device "device:78" under DMAR at fed91000 as 00:15.0 [ 0.891215] DMAR: ACPI device "device:79" under DMAR at fed91000 as 00:15.1 [ 0.891246] DMAR: No ATSR found [ 0.891672] DMAR: dmar0: Using Queued invalidation [ 0.891784] dmar0: Allocated order 8 PASID table. [ 0.891875] DMAR: dmar1: Using Queued invalidation [ 0.892011] DMAR: Setting RMRR: [ 0.892065] DMAR: Setting identity map for device 0000:00:02.0 [0x7d000000 - 0x7f7fffff] [ 0.892092] DMAR: Setting identity map for device 0000:00:14.0 [0x7a261000 - 0x7a280fff] [ 0.892101] DMAR: Prepare 0-16MiB unity mapping for LPC [ 0.892139] DMAR: Setting identity map for device 0000:00:1f.0 [0x0 - 0xffffff] [ 0.892408] DMAR: Intel(R) Virtualization Technology for Directed I/O [ 0.892459] iommu: Adding device 0000:00:00.0 to group 0 [ 0.892471] iommu: Adding device 0000:00:02.0 to group 1 [ 0.892495] iommu: Adding device 0000:00:04.0 to group 2 [ 0.892545] iommu: Adding device 0000:00:14.0 to group 3 [ 0.892555] iommu: Adding device 0000:00:14.2 to group 3 [ 0.892568] iommu: Adding device 0000:00:15.0 to group 4 [ 0.892577] iommu: Adding device 0000:00:15.1 to group 4 [ 0.892588] iommu: Adding device 0000:00:16.0 to group 5 [ 0.892620] iommu: Adding device 0000:00:1c.0 to group 6 [ 0.892642] iommu: Adding device 0000:00:1c.4 to group 6 [ 0.892660] iommu: Adding device 0000:00:1c.5 to group 6 [ 0.892699] iommu: Adding device 0000:00:1d.0 to group 7 [ 0.892717] iommu: Adding device 0000:00:1f.0 to group 8 [ 0.892725] iommu: Adding device 0000:00:1f.2 to group 8 [ 0.892734] iommu: Adding device 0000:00:1f.3 to group 8 [ 0.892743] iommu: Adding device 0000:00:1f.4 to group 8 [ 0.892760] iommu: Adding device 0000:3a:00.0 to group 6 [ 0.892772] iommu: Adding device 0000:3b:00.0 to group 6 [ 0.892792] iommu: Adding device 0000:3c:00.0 to group 7 [ 0.894537] Scanning for low memory corruption every 60 seconds [ 0.894788] futex hash table entries: 1024 (order: 4, 65536 bytes) [ 0.894810] audit: initializing netlink subsys (disabled) [ 0.894825] audit: type=2000 audit(1484056432.873:1): initialized [ 0.895085] Initialise system trusted keyrings [ 0.895166] workingset: timestamp_bits=56 max_order=22 bucket_order=0 [ 0.897059] SELinux: Registering netfilter hooks [ 0.898962] Key type asymmetric registered [ 0.898966] Asymmetric key parser 'x509' registered [ 0.898992] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249) [ 0.898997] io scheduler noop registered (default) [ 0.898999] io scheduler deadline registered [ 0.899005] io scheduler cfq registered [ 0.899748] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 [ 0.899784] efifb: probing for efifb [ 0.899799] efifb: framebuffer at 0x90000000, using 22528k, total 22528k [ 0.899802] efifb: mode is 3200x1800x32, linelength=12800, pages=1 [ 0.899804] efifb: scrolling: redraw [ 0.899807] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0 [ 0.910267] Console: switching to colour frame buffer device 400x112 [ 0.920224] fb0: EFI VGA frame buffer device [ 0.920249] intel_idle: MWAIT substates: 0x11142120 [ 0.920249] intel_idle: v0.4.1 model 0x8E [ 0.920466] intel_idle: lapic_timer_reliable_states 0xffffffff [ 0.922230] ACPI: AC Adapter [AC] (on-line) [ 0.922799] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input0 [ 0.923444] ACPI: Lid Switch [LID0] [ 0.923494] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1 [ 0.923560] ACPI: Power Button [PBTN] [ 0.923602] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input2 [ 0.923640] ACPI: Sleep Button [SBTN] [ 0.923682] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input3 [ 0.923726] ACPI: Power Button [PWRF] [ 0.925629] thermal LNXTHERM:00: registered as thermal_zone0 [ 0.925651] ACPI: Thermal Zone [THM] (25 C) [ 0.925862] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 0.926951] Non-volatile memory driver v1.3 [ 0.927002] [drm] Initialized [ 0.927246] [drm:intel_gvt_init] GVT-g is disabled by kernel params [ 0.927249] [drm:i915_driver_load] Found SunrisePoint LP PCH [ 0.927252] [drm:intel_power_domains_init] Allowed DC state mask 03 [ 0.927284] [drm:intel_device_info_dump] i915 device info: gen=9, pciid=0x5916 rev=0x02 flags=is_kabylake,has_fbc,has_psr,has_runtime_pm,has_csr,has_resource_streamer,has_rc6,has_dp_mst,has_gmbus_irq,has_hw_contexts,has_logical_ring_contexts,has_guc,has_hotplug,has_llc,has_ddi,has_fpga_dbg, [ 0.927553] [drm:intel_device_info_runtime_init] slice mask: 0001 [ 0.927555] [drm:intel_device_info_runtime_init] slice total: 1 [ 0.927557] [drm:intel_device_info_runtime_init] subslice total: 3 [ 0.927558] [drm:intel_device_info_runtime_init] subslice mask 0007 [ 0.927560] [drm:intel_device_info_runtime_init] subslice per slice: 3 [ 0.927562] [drm:intel_device_info_runtime_init] EU total: 24 [ 0.927563] [drm:intel_device_info_runtime_init] EU per subslice: 8 [ 0.927565] [drm:intel_device_info_runtime_init] has slice power gating: n [ 0.927567] [drm:intel_device_info_runtime_init] has subslice power gating: n [ 0.927568] [drm:intel_device_info_runtime_init] has EU power gating: y [ 0.927570] [drm:i915_driver_load] ppgtt mode: 3 [ 0.927571] [drm:i915_driver_load] use GPU sempahores? no [ 0.927592] [drm] Memory usable by graphics device = 4096M [ 0.927621] [drm:i915_ggtt_probe_hw] GMADR size = 256M [ 0.927622] [drm:i915_ggtt_probe_hw] GTT stolen size = 32M [ 0.927623] [drm] VT-d active for gfx access [ 0.927640] checking generic (90000000 1600000) vs hw (90000000 10000000) [ 0.927641] fb: switching to inteldrmfb from EFI VGA [ 0.927672] Console: switching to colour dummy device 80x25 [ 0.927745] [drm] Replacing VGA console driver [ 0.927788] [drm:i915_gem_init_stolen] Memory reserved for graphics device: 32768K, usable: 31744K [ 0.927806] [drm:intel_opregion_setup] graphic opregion physical addr: 0x7abf8018 [ 0.927811] [drm:intel_opregion_setup] Public ACPI methods supported [ 0.927812] [drm:intel_opregion_setup] SWSCI supported [ 0.933542] [drm:intel_opregion_setup] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300583 [ 0.933544] [drm:intel_opregion_setup] ASLE supported [ 0.933545] [drm:intel_opregion_setup] ASLE extension supported [ 0.933548] [drm:intel_opregion_setup] Found valid VBT in ACPI OpRegion (Mailbox #4) [ 0.933601] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 0.933605] [drm] Driver supports precise vblank timestamp query. [ 0.933609] [drm:intel_bios_init] Set default to SSC at 120000 kHz [ 0.933610] [drm:intel_bios_init] VBT signature "$VBT SKYLAKE ", BDB version 206 [ 0.933612] [drm:intel_bios_init] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0 [ 0.933612] [drm:intel_bios_init] crt_ddc_bus_pin: 2 [ 0.935540] [drm:intel_opregion_get_panel_type] Ignoring OpRegion panel type (0) [ 0.935541] [drm:intel_bios_init] Panel type: 2 (VBT) [ 0.935542] [drm:intel_bios_init] DRRS supported mode is seamless [ 0.935544] [drm:intel_bios_init] Found panel mode in BIOS VBT tables: [ 0.935547] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 0 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x8 0xa [ 0.935548] [drm:intel_bios_init] VBT initial LVDS value 30033c [ 0.935550] [drm:intel_bios_init] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 10, level 255 [ 0.935551] [drm:intel_bios_init] Unsupported child device size for SDVO mapping. [ 0.935552] [drm:intel_bios_init] Expected child device config size for VBT version 206 not known; assuming 38 [ 0.935553] [drm:intel_bios_init] DRRS State Enabled:0 [ 0.935555] [drm:intel_bios_init] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0 [ 0.935556] [drm:intel_bios_init] VBT HDMI level shift for port A: 0 [ 0.935557] [drm:intel_bios_init] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0 [ 0.935558] [drm:intel_bios_init] VBT HDMI level shift for port B: 8 [ 0.935559] [drm:intel_bios_init] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0 [ 0.935560] [drm:intel_bios_init] VBT HDMI level shift for port C: 8 [ 0.935663] [drm:intel_dsm_detect] no _DSM method for intel device [ 0.935686] [drm:intel_update_rawclk] rawclk rate: 24000 kHz [ 0.935688] [drm:gen9_set_dc_state] Setting DC state from 00 to 00 [ 0.935693] [drm:intel_power_well_enable] enabling power well 1 [ 0.935697] [drm:intel_power_well_enable] enabling MISC IO power well [ 0.935701] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 0.935703] [drm:intel_update_max_cdclk] Max CD clock rate: 675000 kHz [ 0.935704] [drm:intel_update_max_cdclk] Max dotclock rate: 675000 kHz [ 0.935717] [drm:intel_power_well_enable] enabling always-on [ 0.935718] [drm:intel_power_well_enable] enabling DC off [ 0.935720] [drm:gen9_set_dc_state] Setting DC state from 00 to 00 [ 0.935725] [drm:intel_power_well_enable] enabling power well 2 [ 0.935727] [drm:intel_power_well_enable] enabling DDI A/E power well [ 0.935729] [drm:intel_power_well_enable] enabling DDI B power well [ 0.935731] [drm:skl_set_power_well] Enabling DDI B power well [ 0.935733] [drm:intel_power_well_enable] enabling DDI C power well [ 0.935738] [drm:skl_set_power_well] Enabling DDI C power well [ 0.935740] [drm:intel_power_well_enable] enabling DDI D power well [ 0.935748] [drm:skl_set_power_well] Enabling DDI D power well [ 0.935754] [drm:gen9_set_dc_state] Setting DC state from 00 to 00 [ 0.935786] [drm:intel_csr_ucode_init] Loading i915/kbl_dmc_ver1_01.bin [ 0.936480] [drm] Finished loading i915/kbl_dmc_ver1_01.bin (v1.1) [ 0.936846] [drm:intel_fbc_init] Sanitized enable_fbc value: 0 [ 0.938582] [drm:intel_print_wm_latency] Gen9 Plane WM0 latency 2 (2.0 usec) [ 0.938584] [drm:intel_print_wm_latency] Gen9 Plane WM1 latency 19 (19.0 usec) [ 0.938585] [drm:intel_print_wm_latency] Gen9 Plane WM2 latency 28 (28.0 usec) [ 0.938585] [drm:intel_print_wm_latency] Gen9 Plane WM3 latency 32 (32.0 usec) [ 0.938586] [drm:intel_print_wm_latency] Gen9 Plane WM4 latency 63 (63.0 usec) [ 0.938587] [drm:intel_print_wm_latency] Gen9 Plane WM5 latency 77 (77.0 usec) [ 0.938588] [drm:intel_print_wm_latency] Gen9 Plane WM6 latency 83 (83.0 usec) [ 0.938589] [drm:intel_print_wm_latency] Gen9 Plane WM7 latency 99 (99.0 usec) [ 0.938590] [drm:intel_modeset_init] 3 display pipes available. [ 0.938607] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 0.938609] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem [ 0.938933] [drm:intel_dp_init_connector] Adding eDP connector on port A [ 0.938941] [drm:intel_dp_init_connector] using AUX A for port A (VBT) [ 0.939008] [drm:intel_pps_dump_state] cur t1_t3 0 t8 0 t9 0 t10 500 t11_t12 6000 [ 0.939010] [drm:intel_pps_dump_state] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000 [ 0.939012] [drm:intel_dp_init_panel_power_sequencer.part.17] panel power up delay 200, power down delay 50, power cycle delay 600 [ 0.939015] [drm:intel_dp_init_panel_power_sequencer.part.17] backlight on delay 1, off delay 200 [ 0.939094] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x4af06 [ 0.939128] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 0.939214] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f [ 0.939683] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 0.940083] [drm:intel_dp_init_connector] Detected EDP PSR Panel. [ 0.940479] [drm:intel_dp_init_connector] EDP DPCD : 02 9f 40 [ 0.944660] [drm:drm_edid_to_eld] ELD: no CEA Extension found [ 0.944661] [drm:intel_dp_init_connector] VBT doesn't support DRRS [ 0.944713] [drm:intel_panel_setup_backlight] Connector eDP-1 backlight initialized, enabled, brightness 282/937 [ 0.944736] [drm:intel_dp_init_connector] Adding DP connector on port B [ 0.944741] [drm:intel_dp_init_connector] using AUX B for port B (VBT) [ 0.944747] [drm:intel_hdmi_init_connector] Adding HDMI connector on port B [ 0.944756] [drm:intel_hdmi_init_connector] Using DDC pin 0x5 for port B (VBT) [ 0.944763] [drm:intel_dp_init_connector] Adding DP connector on port C [ 0.944766] [drm:intel_dp_init_connector] using AUX C for port C (VBT) [ 0.944771] [drm:intel_hdmi_init_connector] Adding HDMI connector on port C [ 0.944775] [drm:intel_hdmi_init_connector] Using DDC pin 0x4 for port C (VBT) [ 0.944820] [drm:intel_modeset_setup_hw_state] [CRTC:26:pipe A] hw state readout: enabled [ 0.944822] [drm:intel_modeset_setup_hw_state] [CRTC:30:pipe B] hw state readout: disabled [ 0.944825] [drm:intel_modeset_setup_hw_state] [CRTC:34:pipe C] hw state readout: disabled [ 0.944827] [drm:intel_modeset_setup_hw_state] DPLL 0 hw state readout: crtc_mask 0x00000001, on 1 [ 0.944828] [drm:intel_modeset_setup_hw_state] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0 [ 0.944830] [drm:intel_modeset_setup_hw_state] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0 [ 0.944831] [drm:intel_modeset_setup_hw_state] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0 [ 0.944836] [drm:intel_modeset_setup_hw_state] [ENCODER:36:DDI A] hw state readout: enabled, pipe A [ 0.944838] [drm:intel_modeset_setup_hw_state] [ENCODER:45:DDI B] hw state readout: disabled, pipe A [ 0.944839] [drm:intel_modeset_setup_hw_state] [ENCODER:47:DP-MST A] hw state readout: disabled, pipe A [ 0.944840] [drm:intel_modeset_setup_hw_state] [ENCODER:48:DP-MST B] hw state readout: disabled, pipe B [ 0.944841] [drm:intel_modeset_setup_hw_state] [ENCODER:49:DP-MST C] hw state readout: disabled, pipe C [ 0.944842] [drm:intel_modeset_setup_hw_state] [ENCODER:52:DDI C] hw state readout: disabled, pipe A [ 0.944843] [drm:intel_modeset_setup_hw_state] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A [ 0.944844] [drm:intel_modeset_setup_hw_state] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B [ 0.944845] [drm:intel_modeset_setup_hw_state] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C [ 0.944847] [drm:intel_modeset_setup_hw_state] [CONNECTOR:37:eDP-1] hw state readout: enabled [ 0.944849] [drm:intel_modeset_setup_hw_state] [CONNECTOR:46:DP-1] hw state readout: disabled [ 0.944850] [drm:intel_modeset_setup_hw_state] [CONNECTOR:50:HDMI-A-1] hw state readout: disabled [ 0.944852] [drm:intel_modeset_setup_hw_state] [CONNECTOR:53:DP-2] hw state readout: disabled [ 0.944853] [drm:intel_modeset_setup_hw_state] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled [ 0.944857] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a62b6d7800 [ 0.944884] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][setup_hw_state] config ffffa2a62b6d7800 for pipe A [ 0.944886] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 0.944887] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 0.944888] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 0.944889] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 362389, link_n: 524288, tu: 64 [ 0.944891] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 0.944892] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 0.944892] [drm:intel_dump_pipe_config] requested mode: [ 0.944895] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373249 3200 3248 3280 3360 1800 1803 1808 1852 0x40 0xa [ 0.944896] [drm:intel_dump_pipe_config] adjusted mode: [ 0.944898] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373249 3200 3248 3280 3360 1800 1803 1808 1852 0x40 0xa [ 0.944899] [drm:intel_dump_pipe_config] crtc timings: 373249 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x40 flags: 0xa [ 0.944900] [drm:intel_dump_pipe_config] port clock: 540000 [ 0.944901] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 0.944902] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0 [ 0.944904] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 0.944905] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x0c800708, enabled [ 0.944906] [drm:intel_dump_pipe_config] ips: 0 [ 0.944906] [drm:intel_dump_pipe_config] double wide: 0 [ 0.944908] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 0.944908] [drm:intel_dump_pipe_config] planes on this crtc [ 0.944910] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 0.944911] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 0.944911] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 0.944913] [drm:intel_dump_pipe_config] [CRTC:30:pipe B][setup_hw_state] config ffffa2a62acc8800 for pipe B [ 0.944914] [drm:intel_dump_pipe_config] cpu_transcoder: B [ 0.944915] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0 [ 0.944916] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 0.944918] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 0.944919] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 0.944920] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 0.944921] [drm:intel_dump_pipe_config] requested mode: [ 0.944922] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [ 0.944923] [drm:intel_dump_pipe_config] adjusted mode: [ 0.944925] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [ 0.944926] [drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 [ 0.944927] [drm:intel_dump_pipe_config] port clock: 0 [ 0.944928] [drm:intel_dump_pipe_config] pipe src size: 0x0 [ 0.944929] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 [ 0.944930] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 0.944931] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 0.944932] [drm:intel_dump_pipe_config] ips: 0 [ 0.944933] [drm:intel_dump_pipe_config] double wide: 0 [ 0.944934] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0 [ 0.944935] [drm:intel_dump_pipe_config] planes on this crtc [ 0.944936] [drm:intel_dump_pipe_config] [PLANE:28:plane 1B] disabled, scaler_id = -1 [ 0.944937] [drm:intel_dump_pipe_config] [PLANE:29:cursor B] disabled, scaler_id = -1 [ 0.944938] [drm:intel_dump_pipe_config] [PLANE:31:plane 2B] disabled, scaler_id = -1 [ 0.944940] [drm:intel_dump_pipe_config] [CRTC:34:pipe C][setup_hw_state] config ffffa2a62acc9800 for pipe C [ 0.944942] [drm:intel_dump_pipe_config] cpu_transcoder: C [ 0.944943] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0 [ 0.944944] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 0.944945] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 0.944946] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 0.944947] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 0.944948] [drm:intel_dump_pipe_config] requested mode: [ 0.944950] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [ 0.944951] [drm:intel_dump_pipe_config] adjusted mode: [ 0.944952] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [ 0.944954] [drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 [ 0.944955] [drm:intel_dump_pipe_config] port clock: 0 [ 0.944955] [drm:intel_dump_pipe_config] pipe src size: 0x0 [ 0.944956] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: 0 [ 0.944957] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 0.944958] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 0.944959] [drm:intel_dump_pipe_config] ips: 0 [ 0.944960] [drm:intel_dump_pipe_config] double wide: 0 [ 0.944961] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0 [ 0.944962] [drm:intel_dump_pipe_config] planes on this crtc [ 0.944963] [drm:intel_dump_pipe_config] [PLANE:32:plane 1C] disabled, scaler_id = -1 [ 0.944964] [drm:intel_dump_pipe_config] [PLANE:33:cursor C] disabled, scaler_id = -1 [ 0.944965] [drm:intel_dump_pipe_config] [PLANE:35:plane 2C] disabled, scaler_id = -1 [ 0.945000] [drm:intel_power_well_disable] disabling DDI D power well [ 0.945002] [drm:skl_set_power_well] Disabling DDI D power well [ 0.945004] [drm:intel_power_well_disable] disabling DDI C power well [ 0.945007] [drm:skl_set_power_well] Disabling DDI C power well [ 0.945009] [drm:intel_power_well_disable] disabling DDI B power well [ 0.945011] [drm:skl_set_power_well] Disabling DDI B power well [ 0.945013] [drm:intel_power_well_disable] disabling power well 2 [ 0.945019] [drm:skl_set_power_well] Disabling power well 2 [ 0.945025] [drm:skylake_get_initial_plane_config] pipe A with fb: size=3200x1800@32, offset=0, pitch 12800, size 0x15f9000 [ 0.945262] [drm:i915_gem_init_ggtt] clearing unused GTT space: [0, fffff000] [ 0.945402] ACPI: Battery Slot [BAT0] (battery present) [ 0.947236] [drm:i915_gem_context_init] LR context support initialized [ 0.947239] [drm:i915_gem_object_create_stolen] creating stolen object: size=1000 [ 0.947243] [drm:_i915_gem_object_create_stolen] offset=0x1000, size=4096 [ 0.947246] [drm:intel_engine_create_scratch] render ring pipe control offset: 0xffffe000 [ 0.947383] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 0.947385] [drm:_i915_gem_object_create_stolen] offset=0x2000, size=16384 [ 0.947450] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 0.947452] [drm:_i915_gem_object_create_stolen] offset=0x6000, size=16384 [ 0.947484] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 0.947486] [drm:_i915_gem_object_create_stolen] offset=0xa000, size=16384 [ 0.947566] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 0.947567] [drm:_i915_gem_object_create_stolen] offset=0xe000, size=16384 [ 0.947615] [drm:gen8_init_common_ring] Execlists enabled for render ring [ 0.947671] [drm:gen8_init_common_ring] Execlists enabled for blitter ring [ 0.947713] [drm:gen8_init_common_ring] Execlists enabled for bsd ring [ 0.947753] [drm:gen8_init_common_ring] Execlists enabled for video enhancement ring [ 0.947790] [drm:intel_guc_setup] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE [ 0.947796] [drm] GuC firmware load skipped [ 0.947828] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 0.947834] [drm:intel_fbdev_init] pipe A not active or no fb, skipping [ 0.947835] [drm:intel_fbdev_init] pipe B not active or no fb, skipping [ 0.947837] [drm:intel_fbdev_init] pipe C not active or no fb, skipping [ 0.947838] [drm:intel_fbdev_init] no active fbs found, not using BIOS config [ 0.947925] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1] [ 0.947928] [drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no [ 0.947931] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 0.947933] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000 [ 0.947935] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000 [ 0.948321] [drm:drm_helper_hpd_irq_event] [CONNECTOR:37:eDP-1] status updated from unknown to connected [ 0.948323] [drm:intel_dp_detect] [CONNECTOR:46:DP-1] [ 0.948325] [drm:intel_power_well_enable] enabling power well 2 [ 0.948329] [drm:skl_set_power_well] Enabling power well 2 [ 0.948351] [drm:intel_power_well_disable] disabling power well 2 [ 0.948357] [drm:skl_set_power_well] Disabling power well 2 [ 0.948360] [drm:drm_helper_hpd_irq_event] [CONNECTOR:46:DP-1] status updated from unknown to disconnected [ 0.948362] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-1] [ 0.948658] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 0.948659] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 0.948996] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 0.948998] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 0.949393] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 0.949394] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 0.949669] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 0.949672] [drm:drm_helper_hpd_irq_event] [CONNECTOR:50:HDMI-A-1] status updated from unknown to disconnected [ 0.949674] [drm:intel_dp_detect] [CONNECTOR:53:DP-2] [ 0.949676] [drm:intel_power_well_enable] enabling power well 2 [ 0.949678] [drm:skl_set_power_well] Enabling power well 2 [ 0.949706] [drm:intel_power_well_disable] disabling power well 2 [ 0.949720] [drm:skl_set_power_well] Disabling power well 2 [ 0.949723] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-2] status updated from unknown to disconnected [ 0.949724] [drm:intel_hdmi_detect] [CONNECTOR:57:HDMI-A-2] [ 0.950140] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 0.950141] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 0.950594] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 0.950596] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [ 0.951016] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 0.951017] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 0.951393] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 0.951397] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from unknown to disconnected [ 0.951751] [drm:intel_backlight_device_register] Connector eDP-1 backlight sysfs interface registered [ 0.951756] [drm:intel_dp_connector_register] registering DPDDC-A bus for card0-eDP-1 [ 0.951801] [drm:intel_dp_connector_register] registering DPDDC-B bus for card0-DP-1 [ 0.951862] [drm:intel_dp_connector_register] registering DPDDC-C bus for card0-DP-2 [ 0.952452] [drm:intel_opregion_register] 9 outputs detected [ 0.953604] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) [ 0.954332] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input4 [ 0.954362] [drm] Initialized i915 1.6.0 20160919 for 0000:00:02.0 on minor 0 [ 0.954398] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] [ 0.954401] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1] [ 0.954405] [drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no [ 0.954408] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 0.954410] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000 [ 0.954413] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000 [ 0.954839] [drm:drm_edid_to_eld] ELD: no CEA Extension found [ 0.954842] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes : [ 0.954845] [drm:drm_mode_debug_printmodeline] Modeline 38:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 0.954847] [drm:drm_mode_debug_printmodeline] Modeline 39:"3200x1800" 48 298600 3200 3248 3280 3360 1800 1803 1808 1852 0x40 0xa [ 0.954848] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:46:DP-1] [ 0.954850] [drm:intel_dp_detect] [CONNECTOR:46:DP-1] [ 0.954852] [drm:intel_power_well_enable] enabling power well 2 [ 0.954854] [drm:skl_set_power_well] Enabling power well 2 [ 0.954880] [drm:intel_power_well_disable] disabling power well 2 [ 0.954889] [drm:skl_set_power_well] Disabling power well 2 [ 0.954898] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:46:DP-1] disconnected [ 0.954900] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:HDMI-A-1] [ 0.954901] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-1] [ 0.955208] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 0.955210] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 0.955542] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 0.955545] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 0.955851] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 0.955853] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 0.956143] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 0.956147] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:HDMI-A-1] disconnected [ 0.956149] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-2] [ 0.956151] [drm:intel_dp_detect] [CONNECTOR:53:DP-2] [ 0.956153] [drm:intel_power_well_enable] enabling power well 2 [ 0.956158] [drm:skl_set_power_well] Enabling power well 2 [ 0.956183] [drm:intel_power_well_disable] disabling power well 2 [ 0.956199] [drm:skl_set_power_well] Disabling power well 2 [ 0.956202] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-2] disconnected [ 0.956203] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] [ 0.956205] [drm:intel_hdmi_detect] [CONNECTOR:57:HDMI-A-2] [ 0.956523] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 0.956525] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 0.956555] loop: module loaded [ 0.956721] nvme nvme0: pci function 0000:3c:00.0 [ 0.957101] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 0.957104] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [ 0.957348] e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI [ 0.957353] e100: Copyright(c) 1999-2006 Intel Corporation [ 0.957372] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI [ 0.957375] e1000: Copyright (c) 1999-2006 Intel Corporation. [ 0.957390] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k [ 0.957394] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. [ 0.957413] sky2: driver version 1.30 [ 0.957422] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 0.957423] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 0.957927] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 0.957929] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected [ 0.957931] [drm:drm_setup_crtcs] [ 0.957933] [drm:drm_setup_crtcs] connector 37 enabled? yes [ 0.957934] [drm:drm_setup_crtcs] connector 46 enabled? no [ 0.957935] [drm:drm_setup_crtcs] connector 50 enabled? no [ 0.957937] [drm:drm_setup_crtcs] connector 53 enabled? no [ 0.957938] [drm:drm_setup_crtcs] connector 57 enabled? no [ 0.957941] [drm:intel_fb_initial_config] looking for cmdline mode on connector eDP-1 [ 0.957943] [drm:intel_fb_initial_config] looking for preferred mode on connector eDP-1 0 [ 0.957946] [drm:intel_fb_initial_config] connector eDP-1 on [CRTC:26:pipe A]: 3200x1800 [ 0.957948] [drm:intel_fb_initial_config] connector DP-1 not enabled, skipping [ 0.957950] [drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping [ 0.957952] [drm:intel_fb_initial_config] connector DP-2 not enabled, skipping [ 0.957953] [drm:intel_fb_initial_config] connector HDMI-A-2 not enabled, skipping [ 0.957956] [drm:drm_setup_crtcs] desired mode 3200x1800 set on crtc 26 (0,0) [ 0.957958] [drm:intelfb_create] no BIOS fb, allocating a new one [ 0.958320] ath10k_pci 0000:3a:00.0: enabling device (0000 -> 0002) [ 0.960992] ath10k_pci 0000:3a:00.0: pci irq msi oper_irq_mode 2 irq_mode 0 reset_mode 0 [ 0.963166] [drm:intelfb_create] allocated 3200x1800 fb: 0x000c0000 [ 0.963248] fbcon: inteldrmfb (fb0) is primary device [ 0.963314] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62bb4c800 [ 0.963318] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a62bb34e40 state to ffffa2a62bb4c800 [ 0.963320] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62bb34180 state to ffffa2a62bb4c800 [ 0.963321] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62bb34180 to [NOCRTC] [ 0.963322] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62bb34180 [ 0.963324] [drm:drm_atomic_get_plane_state] Added [PLANE:27:plane 2A] ffffa2a62bb349c0 state to ffffa2a62bb4c800 [ 0.963325] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62bb349c0 to [NOCRTC] [ 0.963326] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62bb349c0 [ 0.963327] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 1B] ffffa2a62bb34840 state to ffffa2a62bb4c800 [ 0.963328] [drm:drm_atomic_get_plane_state] Added [PLANE:29:cursor B] ffffa2a62bb340c0 state to ffffa2a62bb4c800 [ 0.963329] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62bb340c0 to [NOCRTC] [ 0.963330] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62bb340c0 [ 0.963331] [drm:drm_atomic_get_plane_state] Added [PLANE:31:plane 2B] ffffa2a62bb34d80 state to ffffa2a62bb4c800 [ 0.963332] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62bb34d80 to [NOCRTC] [ 0.963333] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62bb34d80 [ 0.963334] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 1C] ffffa2a62bb34cc0 state to ffffa2a62bb4c800 [ 0.963335] [drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor C] ffffa2a62bb34a80 state to ffffa2a62bb4c800 [ 0.963336] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62bb34a80 to [NOCRTC] [ 0.963337] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62bb34a80 [ 0.963338] [drm:drm_atomic_get_plane_state] Added [PLANE:35:plane 2C] ffffa2a62bb34900 state to ffffa2a62bb4c800 [ 0.963338] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62bb34900 to [NOCRTC] [ 0.963339] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62bb34900 [ 0.963342] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62bb4d000 state to ffffa2a62bb4c800 [ 0.963344] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a62bb4d000 [ 0.963345] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62bb34e40 to [CRTC:26:pipe A] [ 0.963346] [drm:drm_atomic_set_fb_for_plane] Set [FB:60] for plane state ffffa2a62bb34e40 [ 0.963348] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62bb4c800 [ 0.963350] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b43fa60 state to ffffa2a62bb4c800 [ 0.963351] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b43fa60 to [NOCRTC] [ 0.963353] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b43fa60 to [CRTC:26:pipe A] [ 0.963354] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a62bb4d800 state to ffffa2a62bb4c800 [ 0.963355] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffffa2a62bb4d800 [ 0.963356] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62bb34840 to [NOCRTC] [ 0.963357] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62bb34840 [ 0.963358] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffffa2a62bb4c800 [ 0.963360] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a62bb4e000 state to ffffa2a62bb4c800 [ 0.963361] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffffa2a62bb4e000 [ 0.963362] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62bb34cc0 to [NOCRTC] [ 0.963362] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62bb34cc0 [ 0.963363] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffffa2a62bb4c800 [ 0.963365] [drm:drm_atomic_check_only] checking ffffa2a62bb4c800 [ 0.963369] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 0.963370] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 0.963372] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62bb4c800 [ 0.963373] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 0.963374] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 0.963379] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 0.963380] [drm:skl_update_scaler] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0 [ 0.963383] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 0.963388] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 0.963389] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 0.963391] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 0.963393] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a62bb4d000 for pipe A [ 0.963394] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 0.963395] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 0.963396] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 0.963397] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 0.963398] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 0.963399] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 0.963400] [drm:intel_dump_pipe_config] requested mode: [ 0.963403] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 0.963403] [drm:intel_dump_pipe_config] adjusted mode: [ 0.963405] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 0.963407] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 0.963407] [drm:intel_dump_pipe_config] port clock: 540000 [ 0.963408] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 0.963409] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 0.963411] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 0.963412] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 0.963413] [drm:intel_dump_pipe_config] ips: 0 [ 0.963413] [drm:intel_dump_pipe_config] double wide: 0 [ 0.963414] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 0.963415] [drm:intel_dump_pipe_config] planes on this crtc [ 0.963416] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1 [ 0.963417] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 0.963418] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 0.963420] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 0.963424] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 0.963425] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 60 [ 0.963427] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 0.963429] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 0.963430] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 0.963432] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 0.963439] [drm:drm_atomic_commit] commiting ffffa2a62bb4c800 [ 0.964558] [drm:intel_edp_backlight_off.part.30] [ 1.063399] xhci_hcd 0000:00:14.0: xHCI Host Controller [ 1.063405] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1 [ 1.064582] xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00109810 [ 1.064587] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported [ 1.064684] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 [ 1.064684] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 1.064685] usb usb1: Product: xHCI Host Controller [ 1.064686] usb usb1: Manufacturer: Linux 4.9.2+ xhci-hcd [ 1.064687] usb usb1: SerialNumber: 0000:00:14.0 [ 1.064883] hub 1-0:1.0: USB hub found [ 1.064924] hub 1-0:1.0: 12 ports detected [ 1.071612] xhci_hcd 0000:00:14.0: xHCI Host Controller [ 1.071614] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2 [ 1.071639] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003 [ 1.071640] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 1.071641] usb usb2: Product: xHCI Host Controller [ 1.071641] usb usb2: Manufacturer: Linux 4.9.2+ xhci-hcd [ 1.071642] usb usb2: SerialNumber: 0000:00:14.0 [ 1.071815] hub 2-0:1.0: USB hub found [ 1.071836] hub 2-0:1.0: 6 ports detected [ 1.074076] usb: port power management may be unreliable [ 1.075359] usbcore: registered new interface driver usb-storage [ 1.075384] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at 0x60,0x64 irq 1,12 [ 1.076069] i8042: Warning: Keylock active [ 1.078493] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 1.078496] serio: i8042 AUX port at 0x60,0x64 irq 12 [ 1.078636] mousedev: PS/2 mouse device common for all mice [ 1.079271] rtc_cmos 00:01: RTC can wake from S4 [ 1.079713] rtc_cmos 00:01: rtc core: registered rtc_cmos as rtc0 [ 1.079814] rtc_cmos 00:01: alarms up to one month, y3k, 242 bytes nvram, hpet irqs [ 1.079965] i801_smbus 0000:00:1f.4: SPD Write Disable is set [ 1.079998] i801_smbus 0000:00:1f.4: SMBus using PCI interrupt [ 1.081006] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input5 [ 1.087763] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel@redhat.com [ 1.087768] intel_pstate: Intel P-state driver initializing [ 1.088059] intel_pstate: HWP enabled [ 1.088096] dcdbas dcdbas: Dell Systems Management Base Driver (version 5.6.0-3.2) [ 1.088098] EFI Variables Facility v0.08 2004-May-17 [ 1.097187] hidraw: raw HID events driver (C) Jiri Kosina [ 1.097349] usbcore: registered new interface driver usbhid [ 1.097349] usbhid: USB HID core driver [ 1.098869] dell_wmi: Detected Dell WMI interface version 1 [ 1.098896] input: Dell WMI hotkeys as /devices/virtual/input/input8 [ 1.099030] intel_pmc_core 0000:00:1f.2: enabling device (0000 -> 0002) [ 1.099198] Netfilter messages via NETLINK v0.30. [ 1.099268] nf_conntrack version 0.5.0 (65536 buckets, 262144 max) [ 1.099310] ctnetlink v0.93: registering with nfnetlink. [ 1.099438] ip_tables: (C) 2000-2006 Netfilter Core Team [ 1.099448] Initializing XFRM netlink socket [ 1.099533] NET: Registered protocol family 10 [ 1.099669] ip6_tables: (C) 2000-2006 Netfilter Core Team [ 1.099772] NET: Registered protocol family 17 [ 1.099778] Key type dns_resolver registered [ 1.099949] microcode: sig=0x806e9, pf=0x80, revision=0x42 [ 1.099985] microcode: Microcode Update Driver: v2.01 , Peter Oruba [ 1.100093] registered taskstats version 1 [ 1.100099] Loading compiled-in X.509 certificates [ 1.101038] Loaded X.509 cert 'Build time autogenerated kernel key: f0011d6ae5e2a58a8bf4b0444932808bbba5dd50' [ 1.102190] Magic number: 1:437:887 [ 1.102199] graphics fb0: hash matches [ 1.102229] pci 0000:00:1f.0: hash matches [ 1.172542] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 1.172569] [drm:lpt_disable_backlight] cpu backlight was enabled, disabling [ 1.172600] [drm:intel_disable_pipe] disabling pipe A [ 1.174137] ath10k_pci 0000:3a:00.0: Direct firmware load for ath10k/pre-cal-pci-0000:3a:00.0.bin failed with error -2 [ 1.174141] ath10k_pci 0000:3a:00.0: Direct firmware load for ath10k/cal-pci-0000:3a:00.0.bin failed with error -2 [ 1.174145] ath10k_pci 0000:3a:00.0: Direct firmware load for ath10k/QCA6174/hw3.0/firmware-5.bin failed with error -2 [ 1.174146] ath10k_pci 0000:3a:00.0: could not fetch firmware file 'ath10k/QCA6174/hw3.0/firmware-5.bin': -2 [ 1.174149] ath10k_pci 0000:3a:00.0: qca6174 hw3.2 target 0x05030000 chip_id 0x00340aff sub 1a56:1535 [ 1.174150] ath10k_pci 0000:3a:00.0: kconfig debug 0 debugfs 1 tracing 0 dfs 0 testmode 0 [ 1.174537] ath10k_pci 0000:3a:00.0: firmware ver WLAN.RM.2.0-00180-QCARMSWPZ-1 api 4 features wowlan,ignore-otp,no-4addr-pad crc32 75dee6c5 [ 1.175357] nvme0n1: p1 p2 [ 1.184823] [drm:edp_panel_off] Turn eDP port A panel power off [ 1.184858] [drm:edp_panel_off] Wait for panel power off time [ 1.184923] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 1.185327] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 1.185329] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 1.185372] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 1.236771] [drm:wait_panel_status] Wait complete [ 1.236774] ath10k_pci 0000:3a:00.0: board_file api 2 bmi_id N/A crc32 6fc88fe7 [ 1.236776] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 1.236782] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 1.236791] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 1.236793] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 1.236794] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 1.236796] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 1.236797] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 1.236800] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 1.236801] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 1.236802] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 1.236804] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 1.236805] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 1.236806] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 1.236808] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 1.236809] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 1.236810] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 1.236811] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 1.236813] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 1.236819] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 1.236821] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 1.236822] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 1.236826] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 1.236827] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 1.237081] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 1.237082] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 1.237083] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 1.432569] usb 1-3: new full-speed USB device number 2 using xhci_hcd [ 1.601789] usb 1-3: New USB device found, idVendor=0cf3, idProduct=e300 [ 1.601790] usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 1.654990] random: fast init done [ 1.757571] usb 1-4: new full-speed USB device number 3 using xhci_hcd [ 1.844638] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 1.844646] [drm:wait_panel_status] Wait complete [ 1.844686] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 1.844694] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 1.877735] psmouse serio1: synaptics: queried max coordinates: x [..5666], y [..4734] [ 1.893764] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 1.893765] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 1.893766] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 1.905884] psmouse serio1: synaptics: queried min coordinates: x [1276..], y [1118..] [ 1.908549] tsc: Refined TSC clocksource calibration: 2904.022 MHz [ 1.908556] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x29dc1adb82b, max_idle_ns: 440795316431 ns [ 1.931193] usb 1-4: New USB device found, idVendor=04f3, idProduct=20d0 [ 1.931193] usb 1-4: New USB device strings: Mfr=4, Product=14, SerialNumber=0 [ 1.931194] usb 1-4: Product: Touchscreen [ 1.931194] usb 1-4: Manufacturer: ELAN [ 1.964525] psmouse serio1: synaptics: Touchpad model: 1, fw: 8.2, id: 0x1e2a1, caps: 0xf00323/0x840300/0x12e800/0x0, board id: 3038, fw id: 2375007 [ 1.999189] input: SynPS/2 Synaptics TouchPad as /devices/platform/i8042/serio1/input/input7 [ 2.053078] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 2.053480] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 2.053485] [drm:edp_panel_on] Turn eDP port A panel power on [ 2.053497] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 2.053581] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 2.053591] [drm:wait_panel_status] Wait complete [ 2.053615] [drm:edp_panel_on] Wait for panel power on [ 2.053671] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 0000000b [ 2.092583] usb 1-5: new high-speed USB device number 4 using xhci_hcd [ 2.254322] [drm:wait_panel_status] Wait complete [ 2.255571] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 2.255572] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 2.255573] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 2.255578] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 2.256320] [drm:intel_dp_start_link_train] clock recovery OK [ 2.256321] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 2.256322] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 2.257387] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 2.257387] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 2.257388] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 2.258419] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 2.258632] [drm:skylake_pfit_enable] for crtc_state = ffffa2a62bb4d000 [ 2.260532] [drm:intel_enable_pipe] enabling pipe A [ 2.260563] [drm:intel_edp_backlight_on.part.29] [ 2.260564] [drm:intel_panel_enable_backlight] pipe A [ 2.260621] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 2.260662] [drm:intel_psr_enable] PSR disable by flag [ 2.260662] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 2.289595] usb 1-5: New USB device found, idVendor=0bda, idProduct=568b [ 2.289596] usb 1-5: New USB device strings: Mfr=3, Product=1, SerialNumber=2 [ 2.289597] usb 1-5: Product: Integrated_Webcam_HD [ 2.289597] usb 1-5: Manufacturer: CKFGH10M306030007890 [ 2.289598] usb 1-5: SerialNumber: 200901010001 [ 2.293957] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 2.293965] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 2.294015] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 2.294020] [drm:intel_enable_sagv] Enabling the SAGV [ 2.294026] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62bb4c800 [ 2.294030] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62bb4c800 [ 2.294082] [drm:i915_hotplug_work_func] running encoder hotplug functions [ 2.294085] [drm:i915_hotplug_work_func] Connector eDP-1 (pin 4) received hotplug event. [ 2.294087] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1] [ 2.294089] [drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no [ 2.294091] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 2.294093] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000 [ 2.294094] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000 [ 2.294504] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62855e800 [ 2.294506] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62855f000 state to ffffa2a62855e800 [ 2.294507] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a62852ac00 state to ffffa2a62855e800 [ 2.294523] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a62855f000 [ 2.294524] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62852ac00 to [CRTC:26:pipe A] [ 2.294525] [drm:drm_atomic_set_fb_for_plane] Set [FB:60] for plane state ffffa2a62852ac00 [ 2.294527] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62855e800 [ 2.294528] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62d8047e0 state to ffffa2a62855e800 [ 2.294529] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62d8047e0 to [NOCRTC] [ 2.294530] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62d8047e0 to [CRTC:26:pipe A] [ 2.294532] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a62855f800 state to ffffa2a62855e800 [ 2.294533] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 1B] ffffa2a62852ae40 state to ffffa2a62855e800 [ 2.294534] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffffa2a62855f800 [ 2.294534] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62852ae40 to [NOCRTC] [ 2.294535] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62852ae40 [ 2.294536] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffffa2a62855e800 [ 2.294538] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a62bb4c800 state to ffffa2a62855e800 [ 2.294539] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 1C] ffffa2a62852ab40 state to ffffa2a62855e800 [ 2.294540] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffffa2a62bb4c800 [ 2.294541] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62852ab40 to [NOCRTC] [ 2.294541] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62852ab40 [ 2.294542] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffffa2a62855e800 [ 2.294544] [drm:drm_atomic_check_only] checking ffffa2a62855e800 [ 2.294547] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 2.294548] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 2.294553] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 2.294554] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 60 [ 2.294555] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.294561] [drm:drm_atomic_commit] commiting ffffa2a62855e800 [ 2.310626] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62855e800 [ 2.310628] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62855e800 [ 2.319619] Console: switching to colour frame buffer device 400x112 [ 2.319623] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62bb4e000 [ 2.319625] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62bb4d800 state to ffffa2a62bb4e000 [ 2.319626] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a62852a840 state to ffffa2a62bb4e000 [ 2.319627] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a62bb4d800 [ 2.319628] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62852a840 to [CRTC:26:pipe A] [ 2.319629] [drm:drm_atomic_set_fb_for_plane] Set [FB:60] for plane state ffffa2a62852a840 [ 2.319630] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62bb4e000 [ 2.319631] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62d804780 state to ffffa2a62bb4e000 [ 2.319632] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62d804780 to [NOCRTC] [ 2.319633] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62d804780 to [CRTC:26:pipe A] [ 2.319634] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a62bb4d000 state to ffffa2a62bb4e000 [ 2.319635] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 1B] ffffa2a62852aa80 state to ffffa2a62bb4e000 [ 2.319636] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffffa2a62bb4d000 [ 2.319637] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62852aa80 to [NOCRTC] [ 2.319638] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62852aa80 [ 2.319639] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffffa2a62bb4e000 [ 2.319640] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a62855e800 state to ffffa2a62bb4e000 [ 2.319641] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 1C] ffffa2a62852a780 state to ffffa2a62bb4e000 [ 2.319642] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffffa2a62855e800 [ 2.319642] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62852a780 to [NOCRTC] [ 2.319643] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62852a780 [ 2.319644] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffffa2a62bb4e000 [ 2.319645] [drm:drm_atomic_check_only] checking ffffa2a62bb4e000 [ 2.319646] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 2.319647] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 2.319649] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 2.319650] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 60 [ 2.319651] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.319655] [drm:drm_atomic_commit] commiting ffffa2a62bb4e000 [ 2.327283] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62bb4e000 [ 2.327284] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62bb4e000 [ 2.347082] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device [ 2.349189] console [netcon0] enabled [ 2.351286] netconsole: network logging started [ 2.355705] PM: Hibernation image not present or could not be loaded. [ 2.355707] ALSA device list: [ 2.357781] No soundcards found. [ 2.360586] Freeing unused kernel memory: 1432K (ffffffffb3346000 - ffffffffb34ac000) [ 2.362644] Write protecting the kernel read-only data: 14336k [ 2.364946] Freeing unused kernel memory: 992K (ffffa2a4f0d08000 - ffffa2a4f0e00000) [ 2.367035] Freeing unused kernel memory: 228K (ffffa2a4f11c7000 - ffffa2a4f1200000) [ 2.445880] udevd[1748]: starting version 3.1.5 [ 2.741169] [drm] RC6 on [ 2.916638] clocksource: Switched to clocksource tsc [ 3.357881] ath10k_pci 0000:3a:00.0: htt-ver 3.26 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1 [ 3.425613] ath: EEPROM regdomain: 0x6c [ 3.425614] ath: EEPROM indicates we should expect a direct regpair map [ 3.425616] ath: Country alpha2 being used: 00 [ 3.425617] ath: Regpair used: 0x6c [ 5.300784] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off [ 5.300844] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007 [ 5.300849] [drm:intel_power_well_disable] disabling DC off [ 5.300853] [drm:skl_enable_dc6] Enabling DC6 [ 5.300856] [drm:gen9_set_dc_state] Setting DC state from 00 to 02 [ 8.603485] random: crng init done [ 11.801482] EXT4-fs (dm-0): mounted filesystem with writeback data mode. Opts: (null) [ 12.576085] udevd[2833]: starting version 3.1.5 [ 12.660080] input: Intel HID events as /devices/platform/INT33D5:00/input/input9 [ 12.664366] intel-lpss 0000:00:15.0: enabling device (0000 -> 0002) [ 12.667258] input: Intel Virtual Button driver as /devices/pci0000:00/0000:00:1f.0/PNP0C09:00/INT33D6:00/input/input10 [ 12.667864] intel-lpss 0000:00:15.1: enabling device (0000 -> 0002) [ 12.668810] mei_me 0000:00:16.0: enabling device (0000 -> 0002) [ 12.684197] rtsx_pci 0000:3b:00.0: rtsx_pci_acquire_irq: pcr->msi_en = 1, pci->irq = 131 [ 12.684537] ath10k_pci 0000:3a:00.0 wlp58s0: renamed from wlan0 [ 12.694917] Linux video capture interface: v2.00 [ 12.720768] Bluetooth: Core ver 2.22 [ 12.720779] NET: Registered protocol family 31 [ 12.720780] Bluetooth: HCI device and connection manager initialized [ 12.720797] Bluetooth: HCI socket layer initialized [ 12.720801] Bluetooth: L2CAP socket layer initialized [ 12.720805] Bluetooth: SCO socket layer initialized [ 12.728524] uvcvideo: Found UVC 1.00 device Integrated_Webcam_HD (0bda:568b) [ 12.729154] usbcore: registered new interface driver btusb [ 12.756711] input: Integrated_Webcam_HD as /devices/pci0000:00/0000:00:14.0/usb1/1-5/1-5:1.0/input/input11 [ 12.757215] usbcore: registered new interface driver uvcvideo [ 12.757216] USB Video Class driver (1.1.1) [ 12.758987] snd_hda_intel 0000:00:1f.3: enabling device (0000 -> 0002) [ 12.759201] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops 0xffffffffb2e864e0) [ 12.761549] [drm:intel_power_well_enable] enabling DC off [ 12.761552] [drm:gen9_set_dc_state] Setting DC state from 02 to 00 [ 12.761556] [drm:intel_power_well_enable] enabling power well 2 [ 12.761558] [drm:skl_set_power_well] Enabling power well 2 [ 12.824086] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC3246: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker [ 12.824087] snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) [ 12.824088] snd_hda_codec_realtek hdaudioC0D0: hp_outs=1 (0x21/0x0/0x0/0x0/0x0) [ 12.824088] snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0 [ 12.824089] snd_hda_codec_realtek hdaudioC0D0: inputs: [ 12.824090] snd_hda_codec_realtek hdaudioC0D0: Headset Mic=0x19 [ 12.824090] snd_hda_codec_realtek hdaudioC0D0: Headphone Mic=0x1a [ 12.824091] snd_hda_codec_realtek hdaudioC0D0: Internal Mic=0x12 [ 12.831447] input: HDA Intel PCH Headphone Mic as /devices/pci0000:00/0000:00:1f.3/sound/card0/input12 [ 12.831478] [drm:intel_power_well_disable] disabling power well 2 [ 12.831485] [drm:skl_set_power_well] Disabling power well 2 [ 12.831487] [drm:intel_power_well_disable] disabling DC off [ 12.831490] [drm:skl_enable_dc6] Enabling DC6 [ 12.831492] [drm:gen9_set_dc_state] Setting DC state from 00 to 02 [ 13.503937] EXT4-fs (dm-0): re-mounted. Opts: data=writeback,barrier=0,discard [ 16.366696] IPv6: ADDRCONF(NETDEV_UP): wlp58s0: link is not ready [ 16.709630] [drm:i915_gem_open] [ 16.709689] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1a000 [ 16.709691] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a62581be40 state to ffffa2a625e1a000 [ 16.709693] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e1d000 state to ffffa2a625e1a000 [ 16.709694] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62581bf00 state to ffffa2a625e1a000 [ 16.709695] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62581bf00 to [NOCRTC] [ 16.709696] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62581bf00 [ 16.709697] [drm:drm_atomic_get_plane_state] Added [PLANE:27:plane 2A] ffffa2a62581b000 state to ffffa2a625e1a000 [ 16.709697] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62581b000 to [NOCRTC] [ 16.709698] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62581b000 [ 16.709699] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 1B] ffffa2a626219000 state to ffffa2a625e1a000 [ 16.709700] [drm:drm_atomic_get_plane_state] Added [PLANE:29:cursor B] ffffa2a6262190c0 state to ffffa2a625e1a000 [ 16.709701] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6262190c0 to [NOCRTC] [ 16.709702] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a6262190c0 [ 16.709703] [drm:drm_atomic_get_plane_state] Added [PLANE:31:plane 2B] ffffa2a626219180 state to ffffa2a625e1a000 [ 16.709703] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626219180 to [NOCRTC] [ 16.709704] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a626219180 [ 16.709705] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 1C] ffffa2a626219240 state to ffffa2a625e1a000 [ 16.709705] [drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor C] ffffa2a626219300 state to ffffa2a625e1a000 [ 16.709706] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626219300 to [NOCRTC] [ 16.709707] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a626219300 [ 16.709708] [drm:drm_atomic_get_plane_state] Added [PLANE:35:plane 2C] ffffa2a6262193c0 state to ffffa2a625e1a000 [ 16.709708] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6262193c0 to [NOCRTC] [ 16.709709] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a6262193c0 [ 16.709710] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625e1d000 [ 16.709711] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62581be40 to [CRTC:26:pipe A] [ 16.709712] [drm:drm_atomic_set_fb_for_plane] Set [FB:60] for plane state ffffa2a62581be40 [ 16.709713] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1a000 [ 16.709715] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba6fc0 state to ffffa2a625e1a000 [ 16.709716] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a628ba6fc0 to [NOCRTC] [ 16.709717] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a628ba6fc0 to [CRTC:26:pipe A] [ 16.709719] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625e1e000 state to ffffa2a625e1a000 [ 16.709719] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffffa2a625e1e000 [ 16.709720] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626219000 to [NOCRTC] [ 16.709721] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a626219000 [ 16.709722] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffffa2a625e1a000 [ 16.709723] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625e1c000 state to ffffa2a625e1a000 [ 16.709723] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffffa2a625e1c000 [ 16.709724] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626219240 to [NOCRTC] [ 16.709725] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a626219240 [ 16.709725] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffffa2a625e1a000 [ 16.709726] [drm:drm_atomic_check_only] checking ffffa2a625e1a000 [ 16.709729] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 16.709731] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 16.709735] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 16.709736] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 60 [ 16.709737] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 16.709742] [drm:drm_atomic_commit] commiting ffffa2a625e1a000 [ 16.714983] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1a000 [ 16.714986] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1a000 [ 16.728165] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62585b000 [ 16.728168] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62585b800 state to ffffa2a62585b000 [ 16.728170] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6296b90c0 state to ffffa2a62585b000 [ 16.728172] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a62585b800 [ 16.728173] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6296b90c0 to [CRTC:26:pipe A] [ 16.728174] [drm:drm_atomic_set_fb_for_plane] Set [FB:60] for plane state ffffa2a6296b90c0 [ 16.728175] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62585b000 [ 16.728177] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b4698c0 state to ffffa2a62585b000 [ 16.728178] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b4698c0 to [NOCRTC] [ 16.728179] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b4698c0 to [CRTC:26:pipe A] [ 16.728181] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a62585a000 state to ffffa2a62585b000 [ 16.728182] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 1B] ffffa2a6296b9840 state to ffffa2a62585b000 [ 16.728182] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffffa2a62585a000 [ 16.728183] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6296b9840 to [NOCRTC] [ 16.728184] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a6296b9840 [ 16.728185] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffffa2a62585b000 [ 16.728186] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a62585c800 state to ffffa2a62585b000 [ 16.728187] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 1C] ffffa2a6296b99c0 state to ffffa2a62585b000 [ 16.728188] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffffa2a62585c800 [ 16.728188] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6296b99c0 to [NOCRTC] [ 16.728189] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a6296b99c0 [ 16.728190] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffffa2a62585b000 [ 16.728191] [drm:drm_atomic_check_only] checking ffffa2a62585b000 [ 16.728194] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 16.728195] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 16.728201] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 16.728202] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 60 [ 16.728203] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 16.728208] [drm:drm_atomic_commit] commiting ffffa2a62585b000 [ 16.731704] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62585b000 [ 16.731707] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62585b000 [ 16.739033] [drm:i915_gem_open] [ 16.741502] [drm:drm_mode_addfb2] [FB:58] [ 16.741581] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000 [ 16.741583] [drm:_i915_gem_object_create_stolen] offset=0x12000, size=16384 [ 16.741684] [drm:drm_internal_framebuffer_create] could not create framebuffer [ 16.741687] [drm:drm_mode_addfb2] [FB:58] [ 16.741692] [drm:drm_mode_addfb2] [FB:58] [ 16.779259] [drm:drm_mode_addfb2] [FB:58] [ 16.779501] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6267bc800 [ 16.779505] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6267be800 state to ffffa2a6267bc800 [ 16.779506] [drm:drm_atomic_check_only] checking ffffa2a6267bc800 [ 16.779512] [drm:drm_atomic_commit] commiting ffffa2a6267bc800 [ 16.781698] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6267bc800 [ 16.781700] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6267bc800 [ 16.879959] [drm:drm_mode_addfb2] [FB:63] [ 16.880094] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 16.880100] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 16.880105] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625859000 [ 16.880109] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62585c000 state to ffffa2a625859000 [ 16.880113] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6265ba0c0 state to ffffa2a625859000 [ 16.880117] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a62585c000 [ 16.880119] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6265ba0c0 to [CRTC:26:pipe A] [ 16.880121] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6265ba0c0 [ 16.880123] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625859000 [ 16.880127] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b4697c0 state to ffffa2a625859000 [ 16.880130] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b4697c0 to [NOCRTC] [ 16.880132] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b4697c0 to [CRTC:26:pipe A] [ 16.880134] [drm:drm_atomic_check_only] checking ffffa2a625859000 [ 16.880139] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 16.880141] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 16.880148] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 16.880151] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58 [ 16.880153] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 16.880162] [drm:drm_atomic_commit] commiting ffffa2a625859000 [ 16.898479] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625859000 [ 16.898486] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625859000 [ 18.380690] [drm:drm_mode_addfb2] [FB:61] [ 18.750511] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] [ 18.750516] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1] [ 18.750523] [drm:intel_power_well_enable] enabling DC off [ 18.750527] [drm:gen9_set_dc_state] Setting DC state from 02 to 00 [ 18.750535] [drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no [ 18.750540] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 18.750543] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000 [ 18.750547] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000 [ 18.750569] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 18.750650] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f [ 18.751073] [drm:drm_edid_to_eld] ELD: no CEA Extension found [ 18.751080] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes : [ 18.751084] [drm:drm_mode_debug_printmodeline] Modeline 38:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 18.751088] [drm:drm_mode_debug_printmodeline] Modeline 39:"3200x1800" 48 298600 3200 3248 3280 3360 1800 1803 1808 1852 0x40 0xa [ 18.751397] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:46:DP-1] [ 18.751401] [drm:intel_dp_detect] [CONNECTOR:46:DP-1] [ 18.751405] [drm:intel_power_well_enable] enabling power well 2 [ 18.751409] [drm:skl_set_power_well] Enabling power well 2 [ 18.751434] [drm:intel_power_well_disable] disabling power well 2 [ 18.751445] [drm:skl_set_power_well] Disabling power well 2 [ 18.751452] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:46:DP-1] disconnected [ 18.751463] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-2] [ 18.751466] [drm:intel_dp_detect] [CONNECTOR:53:DP-2] [ 18.751469] [drm:intel_power_well_enable] enabling power well 2 [ 18.751472] [drm:skl_set_power_well] Enabling power well 2 [ 18.751486] [drm:intel_power_well_disable] disabling power well 2 [ 18.751497] [drm:skl_set_power_well] Disabling power well 2 [ 18.751502] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-2] disconnected [ 18.751508] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:HDMI-A-1] [ 18.751510] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-1] [ 18.751842] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 18.751845] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 18.752116] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 18.752122] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 18.752393] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 18.752395] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 18.752673] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 18.752678] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:HDMI-A-1] disconnected [ 18.752695] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] [ 18.752697] [drm:intel_hdmi_detect] [CONNECTOR:57:HDMI-A-2] [ 18.752969] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 18.752971] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 18.753237] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 18.753240] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [ 18.753508] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 18.753510] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 18.753778] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 18.753782] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected [ 21.240139] wlp58s0: authenticate with b8:be:bf:68:94:7f [ 21.284559] wlp58s0: send auth to b8:be:bf:68:94:7f (try 1/3) [ 21.286643] wlp58s0: authenticated [ 21.292731] wlp58s0: associate with b8:be:bf:68:94:7f (try 1/3) [ 21.396795] wlp58s0: associate with b8:be:bf:68:94:7f (try 2/3) [ 21.399454] wlp58s0: RX AssocResp from b8:be:bf:68:94:7f (capab=0x1 status=12 aid=0) [ 21.399456] wlp58s0: b8:be:bf:68:94:7f denied association (code=12) [ 21.812758] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off [ 21.812821] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007 [ 21.812831] [drm:intel_power_well_disable] disabling DC off [ 21.812837] [drm:skl_enable_dc6] Enabling DC6 [ 21.812840] [drm:gen9_set_dc_state] Setting DC state from 00 to 02 [ 22.582615] wlp58s0: authenticate with b8:be:bf:68:94:7d [ 22.627224] wlp58s0: send auth to b8:be:bf:68:94:7d (try 1/3) [ 22.628915] wlp58s0: authenticated [ 22.629737] wlp58s0: associate with b8:be:bf:68:94:7d (try 1/3) [ 22.632954] wlp58s0: RX AssocResp from b8:be:bf:68:94:7d (capab=0x11 status=0 aid=7) [ 22.636307] wlp58s0: associated [ 22.636345] IPv6: ADDRCONF(NETDEV_CHANGE): wlp58s0: link becomes ready [ 22.639607] ath: EEPROM regdomain: 0x8283 [ 22.639609] ath: EEPROM indicates we should expect a country code [ 22.639610] ath: doing EEPROM country->regdmn map search [ 22.639611] ath: country maps to regdmn code: 0x3 [ 22.639612] ath: Country alpha2 being used: RU [ 22.639613] ath: Regpair used: 0x3 [ 22.639614] ath: regdomain 0x8283 dynamically updated by country IE [ 22.657842] wlp58s0: Limiting TX power to 14 dBm as advertised by b8:be:bf:68:94:7d [ 23.703378] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625859000 [ 23.703384] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625c563c0 state to ffffa2a625859000 [ 23.703390] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ae0000 state to ffffa2a625859000 [ 23.703392] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625c563c0 to [CRTC:26:pipe A] [ 23.703394] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffffa2a625c563c0 [ 23.703396] [drm:drm_atomic_check_only] checking ffffa2a625859000 [ 23.703404] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59 [ 23.703406] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 23.703416] [drm:drm_atomic_commit] commiting ffffa2a625859000 [ 23.703485] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625859000 [ 23.703488] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625859000 [ 62.881922] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e19800 [ 62.881929] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e18800 state to ffffa2a625e19800 [ 62.881932] [drm:drm_atomic_check_only] checking ffffa2a625e19800 [ 62.881937] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 62.881940] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 62.881943] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e19800 [ 62.881948] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba6740 state to ffffa2a625e19800 [ 62.881951] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625aade40 state to ffffa2a625e19800 [ 62.881954] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625aad6c0 state to ffffa2a625e19800 [ 62.881958] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e19800 [ 62.881962] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 62.881964] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 62.881994] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 62.882000] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 62.882009] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 62.882013] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 62.882016] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 62.882021] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625e18800 for pipe A [ 62.882023] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 62.882025] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 62.882028] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 62.882032] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 62.882034] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 62.882037] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 62.882039] [drm:intel_dump_pipe_config] requested mode: [ 62.882044] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 62.882046] [drm:intel_dump_pipe_config] adjusted mode: [ 62.882051] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 62.882054] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 62.882056] [drm:intel_dump_pipe_config] port clock: 540000 [ 62.882058] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 62.882061] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 62.882063] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 62.882066] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 62.882068] [drm:intel_dump_pipe_config] ips: 0 [ 62.882070] [drm:intel_dump_pipe_config] double wide: 0 [ 62.882072] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 62.882074] [drm:intel_dump_pipe_config] planes on this crtc [ 62.882078] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 62.882081] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 62.882084] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 62.882087] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 62.882090] [drm:intel_dump_pipe_config] FB:59, fb = 64x64 format = AR24 little-endian (0x34325241) [ 62.882093] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+64+64 dst 1599x899+64+64 [ 62.882096] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 62.882102] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625e1d000 state to ffffa2a625e19800 [ 62.882105] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625e1b800 state to ffffa2a625e19800 [ 62.882107] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 62.882115] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 62.882118] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 62.882121] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 62.882123] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59 [ 62.882126] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 62.882131] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 62.882134] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 62.882139] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 62.882151] [drm:drm_atomic_commit] commiting ffffa2a625e19800 [ 62.882182] [drm:intel_power_well_enable] enabling DC off [ 62.882187] [drm:gen9_set_dc_state] Setting DC state from 02 to 00 [ 62.884116] [drm:intel_edp_backlight_off.part.30] [ 63.093176] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 63.093235] [drm:intel_disable_pipe] disabling pipe A [ 63.097540] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 63.097613] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b [ 63.097826] [drm:edp_panel_off] Turn eDP port A panel power off [ 63.097865] [drm:edp_panel_off] Wait for panel power off time [ 63.097942] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 63.098435] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 63.098440] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 63.098462] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 63.149503] [drm:wait_panel_status] Wait complete [ 63.149520] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 63.149539] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 63.149541] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 63.149559] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 63.149575] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 63.150327] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 63.150332] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 63.150335] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 63.153722] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 63.153728] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 63.153732] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 63.153738] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 63.153741] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 63.153745] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 63.153748] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 63.153751] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 63.153754] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 63.153757] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 63.153760] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 63.153764] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 63.153766] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 63.153769] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 63.153773] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 63.153777] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 63.153780] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 63.153784] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 63.153793] [drm:intel_power_well_disable] disabling DDI A/E power well [ 63.153798] [drm:skl_set_power_well] Disabling DDI A/E power well [ 63.153802] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 63.153807] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 63.153811] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 63.153820] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e19800 [ 63.153827] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e19800 [ 63.165073] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 63.165078] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a626261cc0 state to ffffa2a625baa000 [ 63.165081] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625baa000 [ 63.165084] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626261cc0 to [CRTC:26:pipe A] [ 63.165086] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffffa2a626261cc0 [ 63.165088] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 63.165100] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 63.165107] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 63.165110] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 63.165175] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 63.165178] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a626261d80 state to ffffa2a625baa000 [ 63.165180] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf800 state to ffffa2a625baa000 [ 63.165182] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626261d80 to [NOCRTC] [ 63.165184] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a626261d80 [ 63.165186] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 63.165190] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 63.165196] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 63.165199] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 63.165207] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 63.165212] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 63.165215] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 63.165217] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625baa000 [ 63.165219] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a626261cc0 state to ffffa2a625baa000 [ 63.165222] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625ba9800 [ 63.165224] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626261cc0 to [CRTC:26:pipe A] [ 63.165226] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a626261cc0 [ 63.165229] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baa000 [ 63.165232] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf7760 state to ffffa2a625baa000 [ 63.165235] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf7760 to [NOCRTC] [ 63.165237] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf7760 to [CRTC:26:pipe A] [ 63.165239] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 63.165243] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 63.165245] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 63.165247] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 63.165249] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 63.165251] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baa000 [ 63.165254] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baa000 [ 63.165258] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 63.165259] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 63.165266] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 63.165271] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 63.165279] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 63.165282] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 63.165285] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 63.165288] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ba9800 for pipe A [ 63.165290] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 63.165292] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 63.165294] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 63.165296] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 63.165298] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 63.165300] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 63.165302] [drm:intel_dump_pipe_config] requested mode: [ 63.165306] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 63.165307] [drm:intel_dump_pipe_config] adjusted mode: [ 63.165311] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 63.165314] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 63.165315] [drm:intel_dump_pipe_config] port clock: 540000 [ 63.165317] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 63.165319] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 63.165321] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 63.165323] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 63.165325] [drm:intel_dump_pipe_config] ips: 0 [ 63.165326] [drm:intel_dump_pipe_config] double wide: 0 [ 63.165328] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 63.165330] [drm:intel_dump_pipe_config] planes on this crtc [ 63.165332] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 63.165335] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 63.165338] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 63.165340] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 63.165341] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 63.165346] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625baa800 state to ffffa2a625baa000 [ 63.165348] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625ba8800 state to ffffa2a625baa000 [ 63.165350] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 63.165356] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 63.165358] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 63.165360] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 63.165364] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 63.165366] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 63.165370] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 63.165379] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 63.165389] [drm:intel_power_well_enable] enabling DDI A/E power well [ 63.165393] [drm:skl_set_power_well] Enabling DDI A/E power well [ 63.165398] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 63.173374] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled [ 63.175479] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 63.175486] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 63.175490] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 63.175496] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 63.175499] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 63.175502] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 63.175505] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 63.175508] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 63.175511] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 63.175514] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 63.175518] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 63.175521] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 63.175524] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 63.175526] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 63.175529] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 63.175533] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 63.175536] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 63.175539] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 63.175545] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 63.175547] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 63.733513] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 63.733534] [drm:wait_panel_status] Wait complete [ 63.733589] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 63.733603] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 63.782765] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 63.782771] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 63.782774] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 63.941266] [drm:edp_panel_on] Turn eDP port A panel power on [ 63.941286] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 63.941365] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 63.941383] [drm:wait_panel_status] Wait complete [ 63.941417] [drm:edp_panel_on] Wait for panel power on [ 63.941493] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 64.143559] [drm:wait_panel_status] Wait complete [ 64.143871] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 64.145083] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 64.145085] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 64.145087] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 64.145090] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 64.145761] [drm:intel_dp_start_link_train] clock recovery OK [ 64.145764] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 64.145765] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 64.146737] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 64.146739] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 64.146741] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 64.147716] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 64.147889] [drm:skylake_pfit_enable] for crtc_state = ffffa2a625ba9800 [ 64.147994] [drm:intel_enable_pipe] enabling pipe A [ 64.148003] [drm:intel_edp_backlight_on.part.29] [ 64.148007] [drm:intel_panel_enable_backlight] pipe A [ 64.148089] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 64.148145] [drm:intel_psr_enable] PSR disable by flag [ 64.148147] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 64.164796] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 64.164807] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 64.164827] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 64.164837] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 64.164844] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 64.165252] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 64.165254] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 64.165260] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf800 state to ffffa2a625baa000 [ 64.165263] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 64.165273] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 64.181523] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 64.181528] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 64.181563] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 64.181566] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 64.181801] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 64.181807] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b0480 state to ffffa2a625baa000 [ 64.181811] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625baa000 [ 64.181814] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b0480 to [CRTC:26:pipe A] [ 64.181817] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b0480 [ 64.181820] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 64.181828] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 64.181831] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 64.181844] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 64.181877] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 64.181882] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 64.181923] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 64.181926] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b03c0 state to ffffa2a625baa000 [ 64.181929] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf800 state to ffffa2a625baa000 [ 64.181932] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b03c0 to [CRTC:26:pipe A] [ 64.181934] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b03c0 [ 64.181936] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 64.181941] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 64.181944] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 64.181953] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 64.181971] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 64.181975] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 64.190890] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 64.190895] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b0480 state to ffffa2a625baa000 [ 64.190899] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625baa000 [ 64.190902] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b0480 to [CRTC:26:pipe A] [ 64.190904] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b0480 [ 64.190907] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 64.190914] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 64.190916] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 64.190928] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 64.190950] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 64.190953] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 64.204685] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 64.204689] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b03c0 state to ffffa2a625baa000 [ 64.204692] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf800 state to ffffa2a625baa000 [ 64.204695] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b03c0 to [CRTC:26:pipe A] [ 64.204697] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b03c0 [ 64.204699] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 64.204704] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 64.204706] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 64.204714] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 64.204730] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 64.204733] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 64.215230] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 64.215234] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b0480 state to ffffa2a625baa000 [ 64.215237] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625baa000 [ 64.215239] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b0480 to [CRTC:26:pipe A] [ 64.215241] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b0480 [ 64.215243] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 64.215248] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 64.215250] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 64.215257] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 64.215272] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 64.215275] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 64.227768] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 64.227772] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b03c0 state to ffffa2a625baa000 [ 64.227775] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf800 state to ffffa2a625baa000 [ 64.227777] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b03c0 to [CRTC:26:pipe A] [ 64.227779] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b03c0 [ 64.227781] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 64.227785] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 64.227788] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 64.227795] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 64.227810] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 64.227813] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 64.240516] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 64.240520] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b0480 state to ffffa2a625baa000 [ 64.240523] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625baa000 [ 64.240525] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b0480 to [CRTC:26:pipe A] [ 64.240527] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b0480 [ 64.240529] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 64.240534] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 64.240536] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 64.240544] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 64.240559] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 64.240562] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 64.253105] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 64.253108] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b03c0 state to ffffa2a625baf800 [ 64.253111] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625baf800 [ 64.253113] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b03c0 to [CRTC:26:pipe A] [ 64.253116] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b03c0 [ 64.253117] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 64.253122] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 64.253124] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 64.253132] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 64.253147] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 64.253150] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 64.265820] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 64.265824] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b0480 state to ffffa2a625baf800 [ 64.265827] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625baf800 [ 64.265829] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b0480 to [CRTC:26:pipe A] [ 64.265831] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b0480 [ 64.265833] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 64.265837] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 64.265840] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 64.265847] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 64.265864] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 64.265866] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 64.278504] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 64.278508] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b03c0 state to ffffa2a625baf800 [ 64.278511] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625baf800 [ 64.278513] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b03c0 to [CRTC:26:pipe A] [ 64.278515] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b03c0 [ 64.278517] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 64.278521] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 64.278524] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 64.278531] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 64.278548] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 64.278550] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 64.290128] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 64.290132] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b0480 state to ffffa2a625baf800 [ 64.290135] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625baf800 [ 64.290137] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b0480 to [CRTC:26:pipe A] [ 64.290139] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b0480 [ 64.290141] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 64.290146] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 64.290148] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 64.290155] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 64.290172] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 64.290175] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 64.305466] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 64.305470] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b03c0 state to ffffa2a625baf800 [ 64.305473] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625baf800 [ 64.305475] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b03c0 to [CRTC:26:pipe A] [ 64.305477] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b03c0 [ 64.305479] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 64.305483] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 64.305486] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 64.305493] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 64.305510] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 64.305513] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 64.365664] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 64.365668] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b0480 state to ffffa2a625baf800 [ 64.365670] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625baf800 [ 64.365673] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b0480 to [CRTC:26:pipe A] [ 64.365675] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b0480 [ 64.365677] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 64.365681] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 64.365683] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 64.365690] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 64.365706] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 64.365709] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 65.270412] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab000 [ 65.270418] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf000 state to ffffa2a625bab000 [ 65.270422] [drm:drm_atomic_check_only] checking ffffa2a625bab000 [ 65.270427] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 65.270429] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 65.270432] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bab000 [ 65.270436] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf7560 state to ffffa2a625bab000 [ 65.270439] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a628790e40 state to ffffa2a625bab000 [ 65.270442] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628790d80 state to ffffa2a625bab000 [ 65.270445] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bab000 [ 65.270448] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 65.270450] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 65.270458] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 65.270463] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 65.270471] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 65.270474] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 65.270477] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 65.270481] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625baf000 for pipe A [ 65.270483] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 65.270485] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 65.270487] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 65.270490] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 65.270492] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 65.270494] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 65.270495] [drm:intel_dump_pipe_config] requested mode: [ 65.270500] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 65.270502] [drm:intel_dump_pipe_config] adjusted mode: [ 65.270505] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 65.270508] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 65.270510] [drm:intel_dump_pipe_config] port clock: 540000 [ 65.270512] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 65.270514] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 65.270516] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 65.270518] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 65.270520] [drm:intel_dump_pipe_config] ips: 0 [ 65.270522] [drm:intel_dump_pipe_config] double wide: 0 [ 65.270524] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 65.270525] [drm:intel_dump_pipe_config] planes on this crtc [ 65.270529] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 65.270531] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 65.270534] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 65.270537] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 65.270539] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 65.270542] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+64+64 dst 1585x779+64+64 [ 65.270544] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 65.270550] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ba9000 state to ffffa2a625bab000 [ 65.270553] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625bae000 state to ffffa2a625bab000 [ 65.270555] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 65.270561] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 65.270564] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 65.270566] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 65.270568] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 65.270571] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 65.270575] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 65.270578] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 65.270581] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 65.270590] [drm:drm_atomic_commit] commiting ffffa2a625bab000 [ 65.272061] [drm:intel_edp_backlight_off.part.30] [ 65.477211] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 65.477269] [drm:intel_disable_pipe] disabling pipe A [ 65.483957] [drm:edp_panel_off] Turn eDP port A panel power off [ 65.484006] [drm:edp_panel_off] Wait for panel power off time [ 65.484088] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 65.484666] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 65.484672] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 65.484696] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 65.534859] [drm:wait_panel_status] Wait complete [ 65.534876] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 65.534896] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 65.534898] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 65.534916] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 65.534931] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 65.536420] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 65.536426] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 65.536429] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 65.541664] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 65.541670] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 65.541674] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 65.541679] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 65.541682] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 65.541686] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 65.541689] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 65.541692] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 65.541694] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 65.541697] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 65.541700] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 65.541703] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 65.541706] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 65.541708] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 65.541712] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 65.541716] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 65.541719] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 65.541722] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 65.541732] [drm:intel_power_well_disable] disabling DDI A/E power well [ 65.541736] [drm:skl_set_power_well] Disabling DDI A/E power well [ 65.541741] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 65.541745] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 65.541749] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 65.541758] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab000 [ 65.541764] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab000 [ 66.101300] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 66.101322] [drm:wait_panel_status] Wait complete [ 66.101382] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 66.101400] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 66.150683] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 66.150690] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 66.150694] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 66.309560] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 66.310652] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 67.553052] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.553057] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625a8f9c0 state to ffffa2a625bad800 [ 67.553062] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab800 state to ffffa2a625bad800 [ 67.553064] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625a8f9c0 to [CRTC:26:pipe A] [ 67.553066] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625a8f9c0 [ 67.553068] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.553079] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.553087] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.553090] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.553123] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.553125] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625a8f900 state to ffffa2a625bad800 [ 67.553128] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf000 state to ffffa2a625bad800 [ 67.553129] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625a8f900 to [NOCRTC] [ 67.553131] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a625a8f900 [ 67.553133] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.553138] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.553143] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.553145] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.553154] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 67.553159] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 67.553161] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.553163] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab800 state to ffffa2a625bad800 [ 67.553165] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625a8f9c0 state to ffffa2a625bad800 [ 67.553168] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625bab800 [ 67.553170] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625a8f9c0 to [CRTC:26:pipe A] [ 67.553172] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a625a8f9c0 [ 67.553174] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bad800 [ 67.553178] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf78a0 state to ffffa2a625bad800 [ 67.553180] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf78a0 to [NOCRTC] [ 67.553183] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf78a0 to [CRTC:26:pipe A] [ 67.553184] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.553188] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 67.553191] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 67.553193] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 67.553194] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 67.553196] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bad800 [ 67.553199] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bad800 [ 67.553202] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 67.553204] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 67.553211] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 67.553216] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 67.553224] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 67.553227] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 67.553229] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 67.553232] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625bab800 for pipe A [ 67.553234] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 67.553236] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 67.553238] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 67.553240] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 67.553243] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 67.553244] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 67.553246] [drm:intel_dump_pipe_config] requested mode: [ 67.553250] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 67.553251] [drm:intel_dump_pipe_config] adjusted mode: [ 67.553254] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 67.553257] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 67.553258] [drm:intel_dump_pipe_config] port clock: 540000 [ 67.553260] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 67.553262] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 67.553264] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 67.553266] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 67.553267] [drm:intel_dump_pipe_config] ips: 0 [ 67.553269] [drm:intel_dump_pipe_config] double wide: 0 [ 67.553270] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 67.553272] [drm:intel_dump_pipe_config] planes on this crtc [ 67.553274] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 67.553277] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 67.553279] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 67.553281] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 67.553283] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 67.553288] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625bab000 state to ffffa2a625bad800 [ 67.553290] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625ba8800 state to ffffa2a625bad800 [ 67.553292] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 67.553297] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 67.553299] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 67.553301] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 67.553305] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 67.553308] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 67.553311] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 67.553320] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.553330] [drm:intel_power_well_enable] enabling DDI A/E power well [ 67.553334] [drm:skl_set_power_well] Enabling DDI A/E power well [ 67.553340] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 67.561884] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 67.561888] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 67.561891] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 67.561895] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 67.561898] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 67.561901] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 67.561903] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 67.561906] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 67.561908] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 67.561911] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 67.561913] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 67.561916] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 67.561918] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 67.561921] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 67.561923] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 67.561927] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 67.561930] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 67.561932] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 67.561938] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 67.561939] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 67.561953] [drm:edp_panel_on] Turn eDP port A panel power on [ 67.561971] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 67.562057] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 67.562074] [drm:wait_panel_status] Wait complete [ 67.562108] [drm:edp_panel_on] Wait for panel power on [ 67.562182] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 67.763108] [drm:wait_panel_status] Wait complete [ 67.764247] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 67.764249] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 67.764250] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 67.764253] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 67.764918] [drm:intel_dp_start_link_train] clock recovery OK [ 67.764921] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 67.764922] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 67.766070] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 67.766072] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 67.766073] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 67.767028] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 67.767199] [drm:skylake_pfit_enable] for crtc_state = ffffa2a625bab800 [ 67.767294] [drm:intel_enable_pipe] enabling pipe A [ 67.767303] [drm:intel_edp_backlight_on.part.29] [ 67.767307] [drm:intel_panel_enable_backlight] pipe A [ 67.767387] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 67.767443] [drm:intel_psr_enable] PSR disable by flag [ 67.767444] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 67.784174] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 67.784185] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 67.784204] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 67.784214] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.784219] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.784241] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.784245] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625bad800 [ 67.784247] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.784256] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.800821] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.800826] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.800852] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 67.800855] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 67.801065] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.801070] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6287909c0 state to ffffa2a625bad800 [ 67.801075] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab800 state to ffffa2a625bad800 [ 67.801077] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6287909c0 to [CRTC:26:pipe A] [ 67.801079] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6287909c0 [ 67.801081] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.801090] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.801092] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 67.801104] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.801139] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.801143] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.801177] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.801218] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628790d80 state to ffffa2a625bad800 [ 67.801221] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625bad800 [ 67.801223] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628790d80 to [CRTC:26:pipe A] [ 67.801225] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628790d80 [ 67.801227] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.801232] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.801234] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.801242] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.801257] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.801260] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.801281] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.801284] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6287909c0 state to ffffa2a625bad800 [ 67.801287] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab800 state to ffffa2a625bad800 [ 67.801289] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6287909c0 to [CRTC:26:pipe A] [ 67.801291] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6287909c0 [ 67.801293] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.801297] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.801300] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.801306] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.801319] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.801322] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.801341] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.801344] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628790d80 state to ffffa2a625bad800 [ 67.801348] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625bad800 [ 67.801350] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628790d80 to [CRTC:26:pipe A] [ 67.801352] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628790d80 [ 67.801353] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.801357] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.801359] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.801365] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.801377] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.801380] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.801398] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.801401] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6287909c0 state to ffffa2a625bad800 [ 67.801404] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab800 state to ffffa2a625bad800 [ 67.801406] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6287909c0 to [CRTC:26:pipe A] [ 67.801408] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6287909c0 [ 67.801410] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.801413] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.801414] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.801420] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.801432] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.801434] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.801450] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.801452] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628790d80 state to ffffa2a625bad800 [ 67.801455] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625bad800 [ 67.801457] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628790d80 to [CRTC:26:pipe A] [ 67.801459] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628790d80 [ 67.801461] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.801464] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.801467] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.801472] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.801485] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.801487] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.801515] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.801519] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6287909c0 state to ffffa2a625bad800 [ 67.801522] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab800 state to ffffa2a625bad800 [ 67.801524] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6287909c0 to [CRTC:26:pipe A] [ 67.801526] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6287909c0 [ 67.801527] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.801531] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.801533] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.801540] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.801552] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.801554] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.801574] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.801577] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628790d80 state to ffffa2a625bad800 [ 67.801579] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625bad800 [ 67.801581] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628790d80 to [CRTC:26:pipe A] [ 67.801583] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628790d80 [ 67.801585] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.801588] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.801590] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.801597] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.801610] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.801613] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.801630] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.801632] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6287909c0 state to ffffa2a625bad800 [ 67.801634] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab800 state to ffffa2a625bad800 [ 67.801636] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6287909c0 to [CRTC:26:pipe A] [ 67.801638] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6287909c0 [ 67.801640] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.801643] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.801645] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.801650] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.801662] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.801664] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.801679] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.801681] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628790d80 state to ffffa2a625bad800 [ 67.801684] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625bad800 [ 67.801685] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628790d80 to [CRTC:26:pipe A] [ 67.801687] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628790d80 [ 67.801689] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.801692] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.801693] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.801698] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.801711] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.801713] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.801727] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.801730] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6287909c0 state to ffffa2a625bad800 [ 67.801732] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab800 state to ffffa2a625bad800 [ 67.801734] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6287909c0 to [CRTC:26:pipe A] [ 67.801735] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6287909c0 [ 67.801737] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.801740] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.801741] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.801747] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.801761] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.801764] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.809407] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1d000 [ 67.809412] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263ab600 state to ffffa2a625e1d000 [ 67.809415] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e18800 state to ffffa2a625e1d000 [ 67.809417] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263ab600 to [CRTC:26:pipe A] [ 67.809419] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263ab600 [ 67.809421] [drm:drm_atomic_check_only] checking ffffa2a625e1d000 [ 67.809430] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.809432] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.809447] [drm:drm_atomic_commit] commiting ffffa2a625e1d000 [ 67.809465] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1d000 [ 67.809468] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1d000 [ 67.809496] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1d000 [ 67.809499] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263ab6c0 state to ffffa2a625e1d000 [ 67.809501] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e19800 state to ffffa2a625e1d000 [ 67.809503] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263ab6c0 to [CRTC:26:pipe A] [ 67.809505] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263ab6c0 [ 67.809506] [drm:drm_atomic_check_only] checking ffffa2a625e1d000 [ 67.809509] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.809511] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.809517] [drm:drm_atomic_commit] commiting ffffa2a625e1d000 [ 67.809528] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1d000 [ 67.809531] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1d000 [ 67.809543] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1d000 [ 67.809545] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263ab600 state to ffffa2a625e1d000 [ 67.809547] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e18800 state to ffffa2a625e1d000 [ 67.809549] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263ab600 to [CRTC:26:pipe A] [ 67.809551] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263ab600 [ 67.809553] [drm:drm_atomic_check_only] checking ffffa2a625e1d000 [ 67.809555] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.809557] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.809561] [drm:drm_atomic_commit] commiting ffffa2a625e1d000 [ 67.809572] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1d000 [ 67.809574] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1d000 [ 67.809586] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1d000 [ 67.809588] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263ab6c0 state to ffffa2a625e1d000 [ 67.809590] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e19800 state to ffffa2a625e1d000 [ 67.809592] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263ab6c0 to [CRTC:26:pipe A] [ 67.809594] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263ab6c0 [ 67.809595] [drm:drm_atomic_check_only] checking ffffa2a625e1d000 [ 67.809597] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.809599] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.809604] [drm:drm_atomic_commit] commiting ffffa2a625e1d000 [ 67.809614] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1d000 [ 67.809616] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1d000 [ 67.809627] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1d000 [ 67.809629] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263ab600 state to ffffa2a625e1d000 [ 67.809631] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e18800 state to ffffa2a625e1d000 [ 67.809632] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263ab600 to [CRTC:26:pipe A] [ 67.809634] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263ab600 [ 67.809636] [drm:drm_atomic_check_only] checking ffffa2a625e1d000 [ 67.809638] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.809639] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.809644] [drm:drm_atomic_commit] commiting ffffa2a625e1d000 [ 67.809654] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1d000 [ 67.809655] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1d000 [ 67.809666] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1d000 [ 67.809668] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263ab6c0 state to ffffa2a625e1d000 [ 67.809670] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e19800 state to ffffa2a625e1d000 [ 67.809672] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263ab6c0 to [CRTC:26:pipe A] [ 67.809674] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263ab6c0 [ 67.809675] [drm:drm_atomic_check_only] checking ffffa2a625e1d000 [ 67.809677] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.809679] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.809683] [drm:drm_atomic_commit] commiting ffffa2a625e1d000 [ 67.809693] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1d000 [ 67.809695] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1d000 [ 67.809707] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1d000 [ 67.809709] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263ab600 state to ffffa2a625e1d000 [ 67.809711] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e18800 state to ffffa2a625e1d000 [ 67.809712] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263ab600 to [CRTC:26:pipe A] [ 67.809714] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263ab600 [ 67.809715] [drm:drm_atomic_check_only] checking ffffa2a625e1d000 [ 67.809718] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.809719] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.809724] [drm:drm_atomic_commit] commiting ffffa2a625e1d000 [ 67.809734] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1d000 [ 67.809735] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1d000 [ 67.809747] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1d000 [ 67.809749] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263ab6c0 state to ffffa2a625e1d000 [ 67.809751] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e19800 state to ffffa2a625e1d000 [ 67.809753] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263ab6c0 to [CRTC:26:pipe A] [ 67.809754] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263ab6c0 [ 67.809756] [drm:drm_atomic_check_only] checking ffffa2a625e1d000 [ 67.809758] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.809760] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.809764] [drm:drm_atomic_commit] commiting ffffa2a625e1d000 [ 67.809774] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1d000 [ 67.809775] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1d000 [ 67.809788] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1d000 [ 67.809790] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263ab600 state to ffffa2a625e1d000 [ 67.809792] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e18800 state to ffffa2a625e1d000 [ 67.809793] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263ab600 to [CRTC:26:pipe A] [ 67.809795] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263ab600 [ 67.809797] [drm:drm_atomic_check_only] checking ffffa2a625e1d000 [ 67.809799] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.809800] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.809805] [drm:drm_atomic_commit] commiting ffffa2a625e1d000 [ 67.809815] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1d000 [ 67.809816] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1d000 [ 67.809847] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1d000 [ 67.809849] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263ab6c0 state to ffffa2a625e1d000 [ 67.809851] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e19800 state to ffffa2a625e1d000 [ 67.809853] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263ab6c0 to [CRTC:26:pipe A] [ 67.809855] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263ab6c0 [ 67.809856] [drm:drm_atomic_check_only] checking ffffa2a625e1d000 [ 67.809858] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.809860] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.809864] [drm:drm_atomic_commit] commiting ffffa2a625e1d000 [ 67.809874] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1d000 [ 67.809876] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1d000 [ 67.815562] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.815566] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628790d80 state to ffffa2a625bad800 [ 67.815569] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625bad800 [ 67.815571] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628790d80 to [CRTC:26:pipe A] [ 67.815573] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628790d80 [ 67.815575] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.815579] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.815581] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.815589] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.815603] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.815606] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.828384] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.828389] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628790000 state to ffffa2a625bad800 [ 67.828393] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9000 state to ffffa2a625bad800 [ 67.828395] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628790000 to [CRTC:26:pipe A] [ 67.828397] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628790000 [ 67.828399] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.828406] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.828408] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.828419] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.828435] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.828438] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 67.841636] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 67.841641] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628790d80 state to ffffa2a625bad800 [ 67.841644] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625bad800 [ 67.841646] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628790d80 to [CRTC:26:pipe A] [ 67.841648] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628790d80 [ 67.841650] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 67.841657] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 67.841659] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 67.841669] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 67.841690] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 67.841693] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 70.773519] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off [ 70.773571] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007 [ 70.773578] [drm:intel_power_well_disable] disabling DC off [ 70.773590] [drm:skl_enable_dc6] Enabling DC6 [ 70.773594] [drm:gen9_set_dc_state] Setting DC state from 00 to 02 [ 98.285639] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1d800 [ 98.285645] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e1c000 state to ffffa2a625e1d800 [ 98.285648] [drm:drm_atomic_check_only] checking ffffa2a625e1d800 [ 98.285652] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 98.285654] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 98.285656] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1d800 [ 98.285660] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba6520 state to ffffa2a625e1d800 [ 98.285663] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6263ab840 state to ffffa2a625e1d800 [ 98.285665] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263abf00 state to ffffa2a625e1d800 [ 98.285668] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1d800 [ 98.285671] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 98.285672] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 98.285679] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 98.285683] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 98.285690] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 98.285693] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 98.285696] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 98.285699] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625e1c000 for pipe A [ 98.285701] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 98.285702] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 98.285705] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 98.285707] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 98.285709] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 98.285711] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 98.285712] [drm:intel_dump_pipe_config] requested mode: [ 98.285716] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 98.285718] [drm:intel_dump_pipe_config] adjusted mode: [ 98.285721] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 98.285723] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 98.285725] [drm:intel_dump_pipe_config] port clock: 540000 [ 98.285726] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 98.285728] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 98.285730] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 98.285732] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 98.285733] [drm:intel_dump_pipe_config] ips: 0 [ 98.285735] [drm:intel_dump_pipe_config] double wide: 0 [ 98.285737] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 98.285738] [drm:intel_dump_pipe_config] planes on this crtc [ 98.285741] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 98.285743] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 98.285746] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 98.285748] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 98.285750] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 98.285753] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2005x0+64+63 [ 98.285755] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 98.285759] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625e1e000 state to ffffa2a625e1d800 [ 98.285762] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625e1d000 state to ffffa2a625e1d800 [ 98.285764] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 98.285770] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 98.285772] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 98.285774] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 98.285776] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 98.285778] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 98.285783] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 98.285785] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 98.285788] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 98.285796] [drm:drm_atomic_commit] commiting ffffa2a625e1d800 [ 98.285804] [drm:intel_power_well_enable] enabling DC off [ 98.285808] [drm:gen9_set_dc_state] Setting DC state from 02 to 00 [ 98.287376] [drm:intel_edp_backlight_off.part.30] [ 98.493525] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 98.493585] [drm:intel_disable_pipe] disabling pipe A [ 98.511178] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 98.511264] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b [ 98.511486] [drm:edp_panel_off] Turn eDP port A panel power off [ 98.511525] [drm:edp_panel_off] Wait for panel power off time [ 98.511603] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 98.512074] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 98.512081] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 98.512109] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 98.562485] [drm:wait_panel_status] Wait complete [ 98.562505] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 98.562526] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 98.562529] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 98.562549] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 98.562567] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 98.563983] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 98.563990] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 98.563994] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 98.564811] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 98.564818] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 98.564823] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 98.564830] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 98.564834] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 98.564838] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 98.564842] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 98.564846] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 98.564849] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 98.564853] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 98.564857] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 98.564861] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 98.564864] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 98.564868] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 98.564872] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 98.564877] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 98.564881] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 98.564884] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 98.564896] [drm:intel_power_well_disable] disabling DDI A/E power well [ 98.564901] [drm:skl_set_power_well] Disabling DDI A/E power well [ 98.564906] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 98.564912] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 98.564916] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 98.564927] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1d800 [ 98.564934] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1d800 [ 99.125515] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 99.125535] [drm:wait_panel_status] Wait complete [ 99.125606] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 99.125625] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 99.174905] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 99.174911] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 99.174914] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 99.333914] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 99.335040] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 101.577457] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 101.577464] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62652f900 state to ffffa2a625bac800 [ 101.577468] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625bac800 [ 101.577471] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62652f900 to [NOCRTC] [ 101.577473] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62652f900 [ 101.577475] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 101.577487] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 101.577497] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 101.577501] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 101.577511] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 101.577517] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 101.577520] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 101.577524] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa800 state to ffffa2a625bac800 [ 101.577527] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a62652fa80 state to ffffa2a625bac800 [ 101.577530] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625baa800 [ 101.577532] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62652fa80 to [CRTC:26:pipe A] [ 101.577535] [drm:drm_atomic_set_fb_for_plane] Set [FB:63] for plane state ffffa2a62652fa80 [ 101.577538] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bac800 [ 101.577542] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf78e0 state to ffffa2a625bac800 [ 101.577545] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf78e0 to [NOCRTC] [ 101.577548] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf78e0 to [CRTC:26:pipe A] [ 101.577550] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 101.577555] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 101.577558] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 101.577560] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 101.577562] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 101.577564] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bac800 [ 101.577568] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bac800 [ 101.577572] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 101.577573] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 101.577581] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 101.577587] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 101.577596] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 101.577599] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 101.577602] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 101.577606] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625baa800 for pipe A [ 101.577608] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 101.577610] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 101.577612] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 101.577615] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 101.577618] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 101.577620] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 101.577622] [drm:intel_dump_pipe_config] requested mode: [ 101.577626] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 101.577628] [drm:intel_dump_pipe_config] adjusted mode: [ 101.577632] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 101.577635] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 101.577637] [drm:intel_dump_pipe_config] port clock: 540000 [ 101.577639] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 101.577641] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 101.577643] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 101.577646] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 101.577648] [drm:intel_dump_pipe_config] ips: 0 [ 101.577649] [drm:intel_dump_pipe_config] double wide: 0 [ 101.577652] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 101.577653] [drm:intel_dump_pipe_config] planes on this crtc [ 101.577657] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 101.577660] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 101.577663] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 101.577666] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 101.577668] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 101.577673] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625baf000 state to ffffa2a625bac800 [ 101.577677] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625bad800 state to ffffa2a625bac800 [ 101.577679] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 101.577685] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 101.577688] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 101.577690] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 101.577695] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 101.577698] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 101.577702] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 101.577713] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 101.577725] [drm:intel_power_well_enable] enabling DDI A/E power well [ 101.577729] [drm:skl_set_power_well] Enabling DDI A/E power well [ 101.577736] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 101.584465] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled [ 101.588630] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 101.588637] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 101.588642] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 101.588648] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 101.588652] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 101.588655] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 101.588658] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 101.588662] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 101.588665] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 101.588668] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 101.588671] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 101.588675] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 101.588678] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 101.588680] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 101.588684] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 101.588688] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 101.588692] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 101.588695] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 101.588701] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 101.588704] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 101.588720] [drm:edp_panel_on] Turn eDP port A panel power on [ 101.588770] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 101.588853] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 101.588883] [drm:wait_panel_status] Wait complete [ 101.588918] [drm:edp_panel_on] Wait for panel power on [ 101.588994] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 101.790130] [drm:wait_panel_status] Wait complete [ 101.791283] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 101.791285] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 101.791286] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 101.791289] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 101.791956] [drm:intel_dp_start_link_train] clock recovery OK [ 101.791959] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 101.791960] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 101.792928] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 101.792930] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 101.792931] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 101.793888] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 101.794060] [drm:skylake_pfit_enable] for crtc_state = ffffa2a625baa800 [ 101.794156] [drm:intel_enable_pipe] enabling pipe A [ 101.794177] [drm:intel_edp_backlight_on.part.29] [ 101.794179] [drm:intel_panel_enable_backlight] pipe A [ 101.794258] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 101.794313] [drm:intel_psr_enable] PSR disable by flag [ 101.794314] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 101.811117] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 101.811124] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 101.811138] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 101.811144] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 101.811148] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 101.811166] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 101.811169] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625bac800 [ 101.811170] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 101.811176] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 101.827660] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 101.827664] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 101.827688] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 101.827690] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 101.827893] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 101.827899] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62652fcc0 state to ffffa2a625bac800 [ 101.827902] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa800 state to ffffa2a625bac800 [ 101.827904] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62652fcc0 to [CRTC:26:pipe A] [ 101.827906] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a62652fcc0 [ 101.827908] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 101.827916] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 101.827918] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 101.827929] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 101.827959] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 101.827962] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 101.827992] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 101.827996] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62652f900 state to ffffa2a625bac800 [ 101.827998] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625bac800 [ 101.828000] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62652f900 to [CRTC:26:pipe A] [ 101.828002] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a62652f900 [ 101.828004] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 101.828008] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 101.828011] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 101.828019] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 101.828034] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 101.828036] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 101.828056] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 101.828059] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62652fcc0 state to ffffa2a625bac800 [ 101.828062] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa800 state to ffffa2a625bac800 [ 101.828065] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62652fcc0 to [CRTC:26:pipe A] [ 101.828066] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a62652fcc0 [ 101.828068] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 101.828073] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 101.828074] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 101.828081] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 101.828097] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 101.828100] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 101.828121] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 101.828124] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62652f900 state to ffffa2a625bac800 [ 101.828127] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625bac800 [ 101.828129] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62652f900 to [CRTC:26:pipe A] [ 101.828131] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a62652f900 [ 101.828133] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 101.828137] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 101.828139] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 101.828147] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 101.828162] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 101.828164] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 101.828184] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 101.828187] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62652fcc0 state to ffffa2a625bac800 [ 101.828189] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa800 state to ffffa2a625bac800 [ 101.828191] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62652fcc0 to [CRTC:26:pipe A] [ 101.828193] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a62652fcc0 [ 101.828195] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 101.828198] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 101.828200] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 101.828206] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 101.828306] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 101.828310] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 101.828332] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 101.828335] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62652f900 state to ffffa2a625bac800 [ 101.828338] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625bac800 [ 101.828339] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62652f900 to [CRTC:26:pipe A] [ 101.828341] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a62652f900 [ 101.828343] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 101.828347] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 101.828348] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 101.828355] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 101.828367] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 101.828370] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 101.828388] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 101.828390] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62652fcc0 state to ffffa2a625bac800 [ 101.828392] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa800 state to ffffa2a625bac800 [ 101.828394] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62652fcc0 to [CRTC:26:pipe A] [ 101.828396] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a62652fcc0 [ 101.828398] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 101.828401] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 101.828402] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 101.828408] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 101.828420] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 101.828422] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 101.828465] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 101.828469] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62652f900 state to ffffa2a625bac800 [ 101.828471] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625bac800 [ 101.828473] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62652f900 to [CRTC:26:pipe A] [ 101.828475] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a62652f900 [ 101.828476] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 101.828479] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 101.828481] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 101.828488] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 101.828501] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 101.828503] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 104.821526] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off [ 104.821589] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007 [ 104.821595] [drm:intel_power_well_disable] disabling DC off [ 104.821600] [drm:skl_enable_dc6] Enabling DC6 [ 104.821604] [drm:gen9_set_dc_state] Setting DC state from 00 to 02 [ 115.617804] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1b800 [ 115.617810] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e1b000 state to ffffa2a625e1b800 [ 115.617814] [drm:drm_atomic_check_only] checking ffffa2a625e1b800 [ 115.617818] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 115.617821] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 115.617824] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1b800 [ 115.617827] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba6020 state to ffffa2a625e1b800 [ 115.617831] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6263abcc0 state to ffffa2a625e1b800 [ 115.617834] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263ab300 state to ffffa2a625e1b800 [ 115.617837] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1b800 [ 115.617841] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 115.617843] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 115.617851] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 115.617856] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 115.617865] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 115.617869] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 115.617872] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 115.617876] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625e1b000 for pipe A [ 115.617878] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 115.617880] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 115.617882] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 115.617885] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 115.617888] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 115.617890] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 115.617892] [drm:intel_dump_pipe_config] requested mode: [ 115.617901] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 115.617903] [drm:intel_dump_pipe_config] adjusted mode: [ 115.617907] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 115.617910] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 115.617912] [drm:intel_dump_pipe_config] port clock: 540000 [ 115.617914] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 115.617916] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 115.617918] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 115.617921] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 115.617922] [drm:intel_dump_pipe_config] ips: 0 [ 115.617924] [drm:intel_dump_pipe_config] double wide: 0 [ 115.617926] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 115.617928] [drm:intel_dump_pipe_config] planes on this crtc [ 115.617931] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 115.617934] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 115.617937] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 115.617940] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 115.617943] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 115.617946] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2037x0+64+63 [ 115.617948] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 115.617954] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625e19800 state to ffffa2a625e1b800 [ 115.617957] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625e18800 state to ffffa2a625e1b800 [ 115.617959] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 115.617967] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 115.617969] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 115.617972] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 115.617974] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 115.617976] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 115.617981] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 115.617984] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 115.617988] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 115.617997] [drm:drm_atomic_commit] commiting ffffa2a625e1b800 [ 115.618008] [drm:intel_power_well_enable] enabling DC off [ 115.618011] [drm:gen9_set_dc_state] Setting DC state from 02 to 00 [ 115.619448] [drm:intel_edp_backlight_off.part.30] [ 115.821603] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 115.821660] [drm:intel_disable_pipe] disabling pipe A [ 115.832498] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 115.832571] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b [ 115.832787] [drm:edp_panel_off] Turn eDP port A panel power off [ 115.832826] [drm:edp_panel_off] Wait for panel power off time [ 115.832903] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 115.833372] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 115.833378] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 115.833406] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 115.883666] [drm:wait_panel_status] Wait complete [ 115.883684] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 115.883704] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 115.883706] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 115.883724] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 115.883740] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 115.885289] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 115.885295] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 115.885298] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 115.885972] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 115.885979] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 115.885984] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 115.885990] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 115.885994] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 115.885997] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 115.886000] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 115.886003] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 115.886006] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 115.886009] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 115.886013] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 115.886016] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 115.886019] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 115.886022] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 115.886025] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 115.886029] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 115.886033] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 115.886036] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 115.886046] [drm:intel_power_well_disable] disabling DDI A/E power well [ 115.886050] [drm:skl_set_power_well] Disabling DDI A/E power well [ 115.886055] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 115.886060] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 115.886064] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 115.886073] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1b800 [ 115.886080] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1b800 [ 116.469677] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 116.469698] [drm:wait_panel_status] Wait complete [ 116.469754] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 116.469768] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 116.519044] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 116.519050] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 116.519053] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 116.678063] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 116.679158] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 117.588191] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 117.588198] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646900 state to ffffa2a625bab800 [ 117.588202] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 117.588204] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646900 to [NOCRTC] [ 117.588207] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a628646900 [ 117.588209] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 117.588220] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 117.588229] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 117.588233] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 117.588243] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 117.588249] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 117.588252] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 117.588255] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 117.588257] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a628646480 state to ffffa2a625bab800 [ 117.588261] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625ba8800 [ 117.588263] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646480 to [CRTC:26:pipe A] [ 117.588265] [drm:drm_atomic_set_fb_for_plane] Set [FB:63] for plane state ffffa2a628646480 [ 117.588268] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bab800 [ 117.588272] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf70c0 state to ffffa2a625bab800 [ 117.588275] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf70c0 to [NOCRTC] [ 117.588277] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf70c0 to [CRTC:26:pipe A] [ 117.588279] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 117.588283] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 117.588286] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 117.588288] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 117.588290] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 117.588292] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bab800 [ 117.588295] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bab800 [ 117.588299] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 117.588300] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 117.588308] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 117.588312] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 117.588321] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 117.588324] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 117.588327] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 117.588330] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ba8800 for pipe A [ 117.588333] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 117.588334] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 117.588337] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 117.588340] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 117.588342] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 117.588344] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 117.588346] [drm:intel_dump_pipe_config] requested mode: [ 117.588350] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 117.588352] [drm:intel_dump_pipe_config] adjusted mode: [ 117.588355] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 117.588358] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 117.588360] [drm:intel_dump_pipe_config] port clock: 540000 [ 117.588362] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 117.588364] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 117.588366] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 117.588368] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 117.588370] [drm:intel_dump_pipe_config] ips: 0 [ 117.588372] [drm:intel_dump_pipe_config] double wide: 0 [ 117.588374] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 117.588375] [drm:intel_dump_pipe_config] planes on this crtc [ 117.588379] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 117.588381] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 117.588384] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 117.588387] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 117.588402] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 117.588408] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625bab000 state to ffffa2a625bab800 [ 117.588411] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625bae000 state to ffffa2a625bab800 [ 117.588413] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 117.588419] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 117.588422] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 117.588424] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 117.588428] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 117.588431] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 117.588435] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 117.588445] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 117.588456] [drm:intel_power_well_enable] enabling DDI A/E power well [ 117.588461] [drm:skl_set_power_well] Enabling DDI A/E power well [ 117.588467] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 117.594883] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 117.594888] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 117.594891] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 117.594895] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 117.594898] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 117.594901] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 117.594903] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 117.594906] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 117.594909] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 117.594911] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 117.594914] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 117.594916] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 117.594919] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 117.594921] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 117.594924] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 117.594927] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 117.594930] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 117.594933] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 117.594937] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 117.594939] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 117.594952] [drm:edp_panel_on] Turn eDP port A panel power on [ 117.594971] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 117.595046] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 117.595060] [drm:wait_panel_status] Wait complete [ 117.595093] [drm:edp_panel_on] Wait for panel power on [ 117.595168] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 117.797145] [drm:wait_panel_status] Wait complete [ 117.798292] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 117.798294] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 117.798296] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 117.798298] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 117.798966] [drm:intel_dp_start_link_train] clock recovery OK [ 117.798969] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 117.798970] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 117.799938] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 117.799940] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 117.799941] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 117.800900] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 117.801065] [drm:skylake_pfit_enable] for crtc_state = ffffa2a625ba8800 [ 117.801137] [drm:intel_enable_pipe] enabling pipe A [ 117.801143] [drm:intel_edp_backlight_on.part.29] [ 117.801145] [drm:intel_panel_enable_backlight] pipe A [ 117.801224] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 117.801277] [drm:intel_psr_enable] PSR disable by flag [ 117.801278] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 117.818080] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 117.818088] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 117.818103] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 117.818110] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 117.818114] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 117.818132] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 117.818135] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 117.818137] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 117.818144] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 117.834716] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 117.834721] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 117.834743] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 117.834746] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 117.834944] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.834948] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3cc0 state to ffffa2a62848f800 [ 117.834953] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848e000 state to ffffa2a62848f800 [ 117.834955] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3cc0 to [CRTC:26:pipe A] [ 117.834957] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3cc0 [ 117.834959] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.834966] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.834969] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 117.834978] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835003] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835006] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835032] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835035] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3b40 state to ffffa2a62848f800 [ 117.835037] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848d000 state to ffffa2a62848f800 [ 117.835039] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3b40 to [CRTC:26:pipe A] [ 117.835041] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3b40 [ 117.835043] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835047] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835049] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835055] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835068] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835070] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835091] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835094] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3cc0 state to ffffa2a62848f800 [ 117.835096] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848e000 state to ffffa2a62848f800 [ 117.835098] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3cc0 to [CRTC:26:pipe A] [ 117.835100] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3cc0 [ 117.835103] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835106] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835108] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835114] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835128] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835131] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835151] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835154] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3b40 state to ffffa2a62848f800 [ 117.835157] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848d000 state to ffffa2a62848f800 [ 117.835159] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3b40 to [CRTC:26:pipe A] [ 117.835160] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3b40 [ 117.835162] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835165] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835167] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835173] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835186] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835189] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835208] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835211] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3cc0 state to ffffa2a62848f800 [ 117.835213] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848e000 state to ffffa2a62848f800 [ 117.835215] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3cc0 to [CRTC:26:pipe A] [ 117.835217] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3cc0 [ 117.835218] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835222] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835224] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835229] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835241] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835243] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835259] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835261] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3b40 state to ffffa2a62848f800 [ 117.835265] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848d000 state to ffffa2a62848f800 [ 117.835269] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3b40 to [CRTC:26:pipe A] [ 117.835270] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3b40 [ 117.835272] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835279] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835281] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835287] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835299] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835301] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835320] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835322] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3cc0 state to ffffa2a62848f800 [ 117.835325] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848e000 state to ffffa2a62848f800 [ 117.835326] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3cc0 to [CRTC:26:pipe A] [ 117.835328] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3cc0 [ 117.835329] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835333] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835334] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835340] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835352] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835354] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835370] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835373] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3b40 state to ffffa2a62848f800 [ 117.835376] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848d000 state to ffffa2a62848f800 [ 117.835378] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3b40 to [CRTC:26:pipe A] [ 117.835380] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3b40 [ 117.835382] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835385] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835387] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835414] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835429] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835431] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835455] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835457] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3cc0 state to ffffa2a62848f800 [ 117.835460] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848e000 state to ffffa2a62848f800 [ 117.835461] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3cc0 to [CRTC:26:pipe A] [ 117.835463] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3cc0 [ 117.835465] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835469] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835472] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835491] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835504] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835506] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835525] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835527] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3b40 state to ffffa2a62848f800 [ 117.835529] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848d000 state to ffffa2a62848f800 [ 117.835531] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3b40 to [CRTC:26:pipe A] [ 117.835533] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3b40 [ 117.835534] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835537] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835539] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835544] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835555] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835558] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835573] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835575] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3cc0 state to ffffa2a62848f800 [ 117.835577] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848e000 state to ffffa2a62848f800 [ 117.835578] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3cc0 to [CRTC:26:pipe A] [ 117.835581] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3cc0 [ 117.835582] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835585] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835587] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835592] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835604] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835607] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835633] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835636] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3b40 state to ffffa2a62848f800 [ 117.835638] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848d000 state to ffffa2a62848f800 [ 117.835640] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3b40 to [CRTC:26:pipe A] [ 117.835641] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3b40 [ 117.835643] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835646] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835648] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835654] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835666] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835668] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835687] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835689] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3cc0 state to ffffa2a62848f800 [ 117.835691] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848e000 state to ffffa2a62848f800 [ 117.835693] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3cc0 to [CRTC:26:pipe A] [ 117.835694] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3cc0 [ 117.835696] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835698] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835700] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835705] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835716] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835718] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835731] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835733] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3b40 state to ffffa2a62848f800 [ 117.835735] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848d000 state to ffffa2a62848f800 [ 117.835737] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3b40 to [CRTC:26:pipe A] [ 117.835738] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3b40 [ 117.835740] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835742] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835744] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835748] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835758] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835760] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.835784] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.835786] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3cc0 state to ffffa2a62848f800 [ 117.835788] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848e000 state to ffffa2a62848f800 [ 117.835790] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3cc0 to [CRTC:26:pipe A] [ 117.835791] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3cc0 [ 117.835793] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.835795] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.835797] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.835801] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.835811] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.835813] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.838734] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.838738] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3b40 state to ffffa2a62848f800 [ 117.838740] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848d000 state to ffffa2a62848f800 [ 117.838742] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3b40 to [CRTC:26:pipe A] [ 117.838744] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3b40 [ 117.838746] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.838750] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.838752] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.838759] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.838789] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.838791] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.851570] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.851575] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3cc0 state to ffffa2a62848f800 [ 117.851579] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848e000 state to ffffa2a62848f800 [ 117.851581] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3cc0 to [CRTC:26:pipe A] [ 117.851584] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3cc0 [ 117.851586] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.851593] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.851595] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.851606] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.851628] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.851631] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.863251] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848f800 [ 117.863256] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6250c3b40 state to ffffa2a62848f800 [ 117.863260] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848d000 state to ffffa2a62848f800 [ 117.863262] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6250c3b40 to [CRTC:26:pipe A] [ 117.863265] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6250c3b40 [ 117.863267] [drm:drm_atomic_check_only] checking ffffa2a62848f800 [ 117.863274] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.863276] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.863286] [drm:drm_atomic_commit] commiting ffffa2a62848f800 [ 117.863307] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848f800 [ 117.863310] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848f800 [ 117.875807] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 117.875813] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646840 state to ffffa2a625baa000 [ 117.875817] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf800 state to ffffa2a625baa000 [ 117.875820] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646840 to [CRTC:26:pipe A] [ 117.875822] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646840 [ 117.875825] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 117.875832] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.875835] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.875846] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 117.875869] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 117.875872] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 117.889348] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 117.889354] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6286460c0 state to ffffa2a625baa000 [ 117.889358] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9000 state to ffffa2a625baa000 [ 117.889361] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6286460c0 to [CRTC:26:pipe A] [ 117.889363] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6286460c0 [ 117.889366] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 117.889373] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 117.889376] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 117.889388] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 117.889421] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 117.889425] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 119.063733] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 119.063740] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf800 state to ffffa2a625baa000 [ 119.063744] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 119.063748] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 119.063751] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 119.063754] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baa000 [ 119.063758] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf7560 state to ffffa2a625baa000 [ 119.063761] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a628646840 state to ffffa2a625baa000 [ 119.063764] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646600 state to ffffa2a625baa000 [ 119.063767] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baa000 [ 119.063771] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 119.063772] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 119.063780] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 119.063786] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 119.063795] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 119.063798] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 119.063801] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 119.063805] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625baf800 for pipe A [ 119.063807] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 119.063810] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 119.063812] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 119.063815] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 119.063818] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 119.063819] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 119.063821] [drm:intel_dump_pipe_config] requested mode: [ 119.063826] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 119.063828] [drm:intel_dump_pipe_config] adjusted mode: [ 119.063832] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 119.063835] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 119.063837] [drm:intel_dump_pipe_config] port clock: 540000 [ 119.063839] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 119.063842] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 119.063845] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 119.063848] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 119.063850] [drm:intel_dump_pipe_config] ips: 0 [ 119.063852] [drm:intel_dump_pipe_config] double wide: 0 [ 119.063854] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 119.063856] [drm:intel_dump_pipe_config] planes on this crtc [ 119.063868] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 119.063905] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 119.063908] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 119.063911] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 119.063913] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 119.063916] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2163x0+64+63 [ 119.063919] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 119.063924] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625bac800 state to ffffa2a625baa000 [ 119.063927] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625bab800 state to ffffa2a625baa000 [ 119.063929] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 119.063936] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 119.063938] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 119.063941] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 119.063944] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 119.063946] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 119.063951] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 119.063954] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 119.063958] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 119.063967] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 119.065474] [drm:intel_edp_backlight_off.part.30] [ 119.269635] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 119.269731] [drm:intel_disable_pipe] disabling pipe A [ 119.285170] [drm:edp_panel_off] Turn eDP port A panel power off [ 119.285211] [drm:edp_panel_off] Wait for panel power off time [ 119.285289] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 119.285820] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 119.285827] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 119.285853] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 119.335934] [drm:wait_panel_status] Wait complete [ 119.335952] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 119.335972] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 119.335975] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 119.335995] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 119.336013] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 119.337669] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 119.337676] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 119.337679] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 119.344902] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled [ 119.344915] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 119.344921] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 119.344927] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 119.344933] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 119.344937] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 119.344941] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 119.344944] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 119.344948] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 119.344951] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 119.344954] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 119.344958] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 119.344961] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 119.344964] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 119.344967] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 119.344971] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 119.344975] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 119.344979] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 119.344982] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 119.344992] [drm:intel_power_well_disable] disabling DDI A/E power well [ 119.344997] [drm:skl_set_power_well] Disabling DDI A/E power well [ 119.345002] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 119.345007] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 119.345012] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 119.345022] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 119.345029] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 119.662764] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848e000 [ 119.662769] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62978ccc0 state to ffffa2a62848e000 [ 119.662773] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848d000 state to ffffa2a62848e000 [ 119.662776] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62978ccc0 to [CRTC:26:pipe A] [ 119.662778] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a62978ccc0 [ 119.662780] [drm:drm_atomic_check_only] checking ffffa2a62848e000 [ 119.662791] [drm:drm_atomic_commit] commiting ffffa2a62848e000 [ 119.662799] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848e000 [ 119.662803] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848e000 [ 119.662842] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848e000 [ 119.662845] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62978c240 state to ffffa2a62848e000 [ 119.662848] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848f800 state to ffffa2a62848e000 [ 119.662850] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62978c240 to [NOCRTC] [ 119.662852] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62978c240 [ 119.662854] [drm:drm_atomic_check_only] checking ffffa2a62848e000 [ 119.662859] [drm:drm_atomic_commit] commiting ffffa2a62848e000 [ 119.662865] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848e000 [ 119.662868] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848e000 [ 119.662877] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 119.662882] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 119.662885] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62848e000 [ 119.662887] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62848d000 state to ffffa2a62848e000 [ 119.662890] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a62978ccc0 state to ffffa2a62848e000 [ 119.662893] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a62848d000 [ 119.662895] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62978ccc0 to [CRTC:26:pipe A] [ 119.662897] [drm:drm_atomic_set_fb_for_plane] Set [FB:63] for plane state ffffa2a62978ccc0 [ 119.662900] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62848e000 [ 119.662903] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9c00 state to ffffa2a62848e000 [ 119.662907] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9c00 to [NOCRTC] [ 119.662909] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9c00 to [CRTC:26:pipe A] [ 119.662911] [drm:drm_atomic_check_only] checking ffffa2a62848e000 [ 119.662915] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 119.662918] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 119.662920] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 119.662922] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 119.662924] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62848e000 [ 119.662927] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62848e000 [ 119.662930] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 119.662932] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 119.662939] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 119.662944] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 119.662953] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 119.662956] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 119.662958] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 119.662962] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a62848d000 for pipe A [ 119.662964] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 119.662966] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 119.662968] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 119.662971] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 119.662973] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 119.662975] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 119.662976] [drm:intel_dump_pipe_config] requested mode: [ 119.662981] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 119.662982] [drm:intel_dump_pipe_config] adjusted mode: [ 119.662986] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 119.662989] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 119.662991] [drm:intel_dump_pipe_config] port clock: 540000 [ 119.662992] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 119.662994] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 119.662997] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 119.662999] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 119.663001] [drm:intel_dump_pipe_config] ips: 0 [ 119.663002] [drm:intel_dump_pipe_config] double wide: 0 [ 119.663004] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 119.663006] [drm:intel_dump_pipe_config] planes on this crtc [ 119.663009] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 119.663012] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 119.663015] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 119.663017] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 119.663019] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 119.663025] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e2800 state to ffffa2a62848e000 [ 119.663027] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e0800 state to ffffa2a62848e000 [ 119.663029] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 119.663035] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 119.663037] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 119.663040] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 119.663044] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 119.663047] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 119.663050] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 119.663061] [drm:drm_atomic_commit] commiting ffffa2a62848e000 [ 119.663071] [drm:intel_power_well_enable] enabling DDI A/E power well [ 119.663075] [drm:skl_set_power_well] Enabling DDI A/E power well [ 119.663082] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 119.665351] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 119.665355] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 119.665358] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 119.665362] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 119.665365] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 119.665367] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 119.665370] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 119.665373] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 119.665375] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 119.665378] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 119.665381] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 119.665384] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 119.665386] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 119.665389] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 119.665391] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 119.665395] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 119.665398] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 119.665400] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 119.665415] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 119.665417] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 119.925635] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 119.925656] [drm:wait_panel_status] Wait complete [ 119.925711] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 119.925725] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 119.974976] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 119.974982] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 119.974985] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 120.133988] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 120.133994] [drm:edp_panel_on] Turn eDP port A panel power on [ 120.134014] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 120.134096] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 120.134113] [drm:wait_panel_status] Wait complete [ 120.134147] [drm:edp_panel_on] Wait for panel power on [ 120.134223] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 120.335526] [drm:wait_panel_status] Wait complete [ 120.337430] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 120.337433] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 120.337435] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 120.337437] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 120.338108] [drm:intel_dp_start_link_train] clock recovery OK [ 120.338111] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 120.338113] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 120.339085] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 120.339087] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 120.339088] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 120.340048] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 120.340222] [drm:skylake_pfit_enable] for crtc_state = ffffa2a62848d000 [ 120.340324] [drm:intel_enable_pipe] enabling pipe A [ 120.340334] [drm:intel_edp_backlight_on.part.29] [ 120.340338] [drm:intel_panel_enable_backlight] pipe A [ 120.340419] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 120.340482] [drm:intel_psr_enable] PSR disable by flag [ 120.340484] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 120.357147] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 120.357153] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 120.357166] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 120.357171] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62848e000 [ 120.357175] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62848e000 [ 120.357553] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 120.357554] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.357558] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.357559] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.357566] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.373826] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.373831] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.373856] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 120.373858] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 120.374039] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374043] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.374046] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.374062] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.374064] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.374067] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374074] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374076] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 120.374088] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374121] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374125] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374165] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374170] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.374173] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.374175] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.374177] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.374179] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374184] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374187] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374231] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374247] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374250] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374273] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374276] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.374279] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.374280] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.374282] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.374284] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374288] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374290] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374295] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374308] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374310] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374325] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374328] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.374330] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.374331] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.374333] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.374335] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374338] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374340] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374346] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374358] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374361] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374380] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374382] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.374385] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.374387] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.374389] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.374391] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374395] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374397] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374404] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374431] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374435] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374459] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374462] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.374464] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.374466] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.374468] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.374470] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374473] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374475] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374481] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374494] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374496] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374514] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374517] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.374519] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.374520] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.374522] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.374524] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374527] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374528] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374533] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374545] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374547] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374560] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374562] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.374564] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.374565] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.374567] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.374569] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374571] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374573] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374577] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374587] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374589] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374602] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374604] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.374606] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.374607] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.374609] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.374611] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374613] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374615] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374619] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374629] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374631] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374643] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374645] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.374647] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.374648] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.374650] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.374652] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374654] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374656] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374660] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374670] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374672] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374683] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374685] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.374687] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.374689] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.374691] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.374692] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374694] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374696] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374701] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374711] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374713] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374725] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374727] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.374729] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.374731] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.374732] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.374734] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374736] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374738] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374742] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374752] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374754] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374765] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374767] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.374769] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.374771] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.374772] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.374774] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374776] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374778] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374782] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374792] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374794] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374805] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374807] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.374809] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.374811] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.374813] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.374814] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374816] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374818] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374822] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374832] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374834] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374845] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374847] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.374849] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.374851] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.374852] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.374854] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374859] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374861] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374867] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374891] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374894] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374907] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374909] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.374911] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.374912] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.374914] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.374915] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374918] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374920] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374924] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374934] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374936] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374946] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374948] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.374951] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.374952] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.374954] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.374955] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374958] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374959] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.374964] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.374974] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.374975] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.374985] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.374987] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.374989] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.374991] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.374992] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.374994] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.374996] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.374998] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375002] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375012] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375014] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375023] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375025] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.375027] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.375029] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.375030] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.375032] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375034] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375036] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375040] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375050] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375052] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375062] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375064] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.375066] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.375068] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.375069] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.375071] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375073] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375075] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375079] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375089] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375091] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375101] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375103] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.375105] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.375106] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.375108] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.375109] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375111] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375113] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375117] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375127] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375129] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375140] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375142] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.375143] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.375145] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.375147] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.375148] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375150] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375152] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375156] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375166] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375168] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375179] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375180] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.375182] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.375184] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.375186] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.375187] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375189] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375191] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375195] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375205] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375207] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375218] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375220] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.375222] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.375224] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.375225] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.375227] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375229] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375231] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375235] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375245] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375247] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375257] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375259] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.375261] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.375262] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.375264] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.375266] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375268] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375269] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375274] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375284] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375285] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375297] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375299] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.375300] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.375302] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.375304] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.375305] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375307] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375309] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375313] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375323] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375325] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375336] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375338] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.375340] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.375342] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.375343] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.375345] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375347] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375349] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375353] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375363] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375365] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375376] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375378] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.375380] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.375382] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.375383] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.375385] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375387] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375389] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375393] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375403] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375405] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375423] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375425] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.375427] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.375429] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.375430] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.375432] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375434] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375436] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375441] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375451] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375453] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375465] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375467] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.375469] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.375471] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.375473] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.375474] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375476] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375478] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375482] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375493] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375495] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375507] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375509] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.375511] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.375513] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.375514] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.375516] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375518] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375520] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375524] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375534] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375536] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375547] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375549] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.375551] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.375553] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.375555] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.375556] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375558] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375560] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375564] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375574] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375576] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375588] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375590] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.375592] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.375594] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.375595] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.375597] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375599] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375601] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375605] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375615] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375617] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375629] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375631] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646d80 state to ffffa2a625bab800 [ 120.375633] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bab800 [ 120.375634] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646d80 to [CRTC:26:pipe A] [ 120.375636] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646d80 [ 120.375638] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375640] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375641] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375646] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375656] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375658] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 120.375685] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 120.375687] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628646a80 state to ffffa2a625bab800 [ 120.375689] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 120.375691] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628646a80 to [CRTC:26:pipe A] [ 120.375692] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628646a80 [ 120.375694] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 120.375696] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 120.375698] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 120.375702] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 120.375712] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 120.375714] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 121.361986] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf000 [ 121.361992] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625baf000 [ 121.361995] [drm:drm_atomic_check_only] checking ffffa2a625baf000 [ 121.361999] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 121.362002] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 121.362004] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baf000 [ 121.362008] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf7800 state to ffffa2a625baf000 [ 121.362011] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a62baf2840 state to ffffa2a625baf000 [ 121.362014] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62baf2300 state to ffffa2a625baf000 [ 121.362017] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baf000 [ 121.362020] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 121.362022] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 121.362029] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 121.362034] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 121.362042] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 121.362045] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 121.362047] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 121.362051] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ba9800 for pipe A [ 121.362053] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 121.362054] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 121.362057] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 121.362059] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 121.362061] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 121.362063] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 121.362065] [drm:intel_dump_pipe_config] requested mode: [ 121.362069] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 121.362070] [drm:intel_dump_pipe_config] adjusted mode: [ 121.362144] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 121.362148] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 121.362150] [drm:intel_dump_pipe_config] port clock: 540000 [ 121.362152] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 121.362154] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 121.362157] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 121.362159] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 121.362161] [drm:intel_dump_pipe_config] ips: 0 [ 121.362163] [drm:intel_dump_pipe_config] double wide: 0 [ 121.362165] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 121.362167] [drm:intel_dump_pipe_config] planes on this crtc [ 121.362170] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 121.362173] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 121.362176] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 121.362179] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 121.362182] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 121.362185] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2360x0+64+63 [ 121.362188] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 121.362194] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625baa800 state to ffffa2a625baf000 [ 121.362198] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625bac800 state to ffffa2a625baf000 [ 121.362201] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 121.362209] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 121.362212] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 121.362215] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 121.362219] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 121.362222] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 121.362227] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 121.362230] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 121.362234] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 121.362246] [drm:drm_atomic_commit] commiting ffffa2a625baf000 [ 121.363483] [drm:intel_edp_backlight_off.part.30] [ 121.565586] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 121.565644] [drm:intel_disable_pipe] disabling pipe A [ 121.574508] [drm:edp_panel_off] Turn eDP port A panel power off [ 121.574549] [drm:edp_panel_off] Wait for panel power off time [ 121.574627] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 121.575214] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 121.575219] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 121.575243] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 121.625381] [drm:wait_panel_status] Wait complete [ 121.625398] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 121.625419] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 121.625422] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 121.625452] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 121.625468] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 121.627031] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 121.627036] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 121.627040] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 121.627703] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 121.627709] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 121.627714] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 121.627720] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 121.627724] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 121.627727] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 121.627730] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 121.627733] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 121.627736] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 121.627739] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 121.627743] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 121.627746] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 121.627749] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 121.627752] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 121.627755] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 121.627760] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 121.627763] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 121.627766] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 121.627776] [drm:intel_power_well_disable] disabling DDI A/E power well [ 121.627781] [drm:skl_set_power_well] Disabling DDI A/E power well [ 121.627785] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 121.627790] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 121.627794] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 121.627804] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf000 [ 121.627811] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf000 [ 122.038380] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e0800 [ 122.038386] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62978ce40 state to ffffa2a6288e0800 [ 122.038390] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e2800 state to ffffa2a6288e0800 [ 122.038393] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62978ce40 to [NOCRTC] [ 122.038395] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62978ce40 [ 122.038398] [drm:drm_atomic_check_only] checking ffffa2a6288e0800 [ 122.038409] [drm:drm_atomic_commit] commiting ffffa2a6288e0800 [ 122.038419] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e0800 [ 122.038442] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e0800 [ 122.038454] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 122.038459] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 122.038462] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e0800 [ 122.038466] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e5000 state to ffffa2a6288e0800 [ 122.038468] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a62978c480 state to ffffa2a6288e0800 [ 122.038472] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e5000 [ 122.038474] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62978c480 to [CRTC:26:pipe A] [ 122.038476] [drm:drm_atomic_set_fb_for_plane] Set [FB:63] for plane state ffffa2a62978c480 [ 122.038479] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e0800 [ 122.038483] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9c00 state to ffffa2a6288e0800 [ 122.038486] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9c00 to [NOCRTC] [ 122.038489] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9c00 to [CRTC:26:pipe A] [ 122.038491] [drm:drm_atomic_check_only] checking ffffa2a6288e0800 [ 122.038496] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 122.038498] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 122.038501] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 122.038503] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 122.038505] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e0800 [ 122.038509] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e0800 [ 122.038512] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 122.038514] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 122.038522] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 122.038527] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 122.038536] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 122.038539] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 122.038542] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 122.038546] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e5000 for pipe A [ 122.038548] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 122.038550] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 122.038552] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 122.038555] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 122.038558] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 122.038560] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 122.038562] [drm:intel_dump_pipe_config] requested mode: [ 122.038566] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 122.038568] [drm:intel_dump_pipe_config] adjusted mode: [ 122.038572] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 122.038575] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 122.038577] [drm:intel_dump_pipe_config] port clock: 540000 [ 122.038579] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 122.038582] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 122.038584] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 122.038587] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 122.038588] [drm:intel_dump_pipe_config] ips: 0 [ 122.038590] [drm:intel_dump_pipe_config] double wide: 0 [ 122.038592] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 122.038594] [drm:intel_dump_pipe_config] planes on this crtc [ 122.038598] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 122.038601] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 122.038604] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 122.038606] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 122.038608] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 122.038614] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e7000 state to ffffa2a6288e0800 [ 122.038617] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e4800 state to ffffa2a6288e0800 [ 122.038619] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 122.038626] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 122.038629] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 122.038631] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 122.038635] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 122.038638] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 122.038642] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 122.038653] [drm:drm_atomic_commit] commiting ffffa2a6288e0800 [ 122.038663] [drm:intel_power_well_enable] enabling DDI A/E power well [ 122.038668] [drm:skl_set_power_well] Enabling DDI A/E power well [ 122.038675] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 122.043157] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 122.043163] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 122.043168] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 122.043174] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 122.043177] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 122.043180] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 122.043183] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 122.043187] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 122.043190] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 122.043193] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 122.043196] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 122.043200] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 122.043202] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 122.043205] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 122.043208] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 122.043213] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 122.043216] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 122.043219] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 122.043226] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 122.043229] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 122.229708] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 122.229729] [drm:wait_panel_status] Wait complete [ 122.229784] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 122.229798] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 122.279079] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 122.279084] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 122.279088] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 122.437995] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 122.438001] [drm:edp_panel_on] Turn eDP port A panel power on [ 122.438021] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 122.438103] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 122.438120] [drm:wait_panel_status] Wait complete [ 122.438154] [drm:edp_panel_on] Wait for panel power on [ 122.438230] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 122.638828] [drm:wait_panel_status] Wait complete [ 122.640701] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 122.640704] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 122.640705] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 122.640708] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 122.641376] [drm:intel_dp_start_link_train] clock recovery OK [ 122.641379] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 122.641381] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 122.642351] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 122.642353] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 122.642354] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 122.643313] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 122.643486] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e5000 [ 122.643584] [drm:intel_enable_pipe] enabling pipe A [ 122.643593] [drm:intel_edp_backlight_on.part.29] [ 122.643597] [drm:intel_panel_enable_backlight] pipe A [ 122.643678] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 122.643734] [drm:intel_psr_enable] PSR disable by flag [ 122.643736] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 122.660406] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 122.660415] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 122.660440] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 122.660449] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e0800 [ 122.660455] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e0800 [ 122.660848] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 122.660851] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 122.660856] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa800 state to ffffa2a625bac800 [ 122.660859] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 122.660868] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 122.677134] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 122.677140] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 122.677168] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 122.677171] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 122.677463] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 122.677469] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565780 state to ffffa2a625bac800 [ 122.677474] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bad800 state to ffffa2a625bac800 [ 122.677476] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565780 to [CRTC:26:pipe A] [ 122.677520] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625565780 [ 122.677522] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 122.677529] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 122.677532] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 122.677543] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 122.677572] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 122.677576] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 123.660028] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bae000 [ 123.660035] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab000 state to ffffa2a625bae000 [ 123.660038] [drm:drm_atomic_check_only] checking ffffa2a625bae000 [ 123.660044] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 123.660046] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 123.660050] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bae000 [ 123.660054] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf77e0 state to ffffa2a625bae000 [ 123.660060] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625565cc0 state to ffffa2a625bae000 [ 123.660063] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565e40 state to ffffa2a625bae000 [ 123.660068] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bae000 [ 123.660071] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 123.660074] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 123.660082] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 123.660089] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 123.660100] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 123.660104] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 123.660106] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 123.660110] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625bab000 for pipe A [ 123.660112] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 123.660114] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 123.660116] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 123.660119] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 123.660121] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 123.660123] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 123.660124] [drm:intel_dump_pipe_config] requested mode: [ 123.660129] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 123.660130] [drm:intel_dump_pipe_config] adjusted mode: [ 123.660133] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 123.660136] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 123.660138] [drm:intel_dump_pipe_config] port clock: 540000 [ 123.660139] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 123.660142] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 123.660145] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 123.660147] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 123.660148] [drm:intel_dump_pipe_config] ips: 0 [ 123.660150] [drm:intel_dump_pipe_config] double wide: 0 [ 123.660152] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 123.660153] [drm:intel_dump_pipe_config] planes on this crtc [ 123.660161] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 123.660163] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 123.660167] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 123.660169] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 123.660171] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 123.660174] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2360x0+64+63 [ 123.660177] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 123.660186] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ba9000 state to ffffa2a625bae000 [ 123.660189] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625baa000 state to ffffa2a625bae000 [ 123.660190] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 123.660197] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 123.660199] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 123.660202] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 123.660204] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 123.660206] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 123.660211] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 123.660213] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 123.660217] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 123.660225] [drm:drm_atomic_commit] commiting ffffa2a625bae000 [ 123.661503] [drm:intel_edp_backlight_off.part.30] [ 123.869514] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 123.869554] [drm:intel_disable_pipe] disabling pipe A [ 123.878495] [drm:edp_panel_off] Turn eDP port A panel power off [ 123.878535] [drm:edp_panel_off] Wait for panel power off time [ 123.878612] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000000 [ 123.879210] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 123.879215] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 123.879241] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 123.929325] [drm:wait_panel_status] Wait complete [ 123.929342] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 123.929347] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 123.929367] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 123.929408] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 123.929426] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 123.931036] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 123.931041] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 123.931044] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 123.933746] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 123.933752] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 123.933757] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 123.933762] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 123.933765] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 123.933768] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 123.933771] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 123.933774] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 123.933777] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 123.933780] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 123.933783] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 123.933786] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 123.933789] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 123.933791] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 123.933794] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 123.933799] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 123.933802] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 123.933805] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 123.933814] [drm:intel_power_well_disable] disabling DDI A/E power well [ 123.933818] [drm:skl_set_power_well] Disabling DDI A/E power well [ 123.933823] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 123.933827] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 123.933831] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 123.933840] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bae000 [ 123.933846] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bae000 [ 124.533736] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 124.533756] [drm:wait_panel_status] Wait complete [ 124.533812] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 124.533825] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 124.583107] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 124.583113] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 124.583116] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 124.742175] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 124.743271] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 126.012171] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 126.012178] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565a80 state to ffffa2a625bac800 [ 126.012182] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa800 state to ffffa2a625bac800 [ 126.012185] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565a80 to [NOCRTC] [ 126.012187] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a625565a80 [ 126.012190] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 126.012201] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 126.012211] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 126.012215] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 126.012226] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 126.012232] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 126.012235] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 126.012238] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab000 state to ffffa2a625bac800 [ 126.012241] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625565e40 state to ffffa2a625bac800 [ 126.012244] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625bab000 [ 126.012246] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565e40 to [CRTC:26:pipe A] [ 126.012249] [drm:drm_atomic_set_fb_for_plane] Set [FB:63] for plane state ffffa2a625565e40 [ 126.012252] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bac800 [ 126.012256] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf78a0 state to ffffa2a625bac800 [ 126.012259] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf78a0 to [NOCRTC] [ 126.012262] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf78a0 to [CRTC:26:pipe A] [ 126.012264] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 126.012269] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 126.012272] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 126.012274] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 126.012276] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 126.012279] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bac800 [ 126.012282] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bac800 [ 126.012286] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 126.012287] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 126.012296] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 126.012301] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 126.012310] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 126.012314] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 126.012316] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 126.012320] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625bab000 for pipe A [ 126.012323] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 126.012324] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 126.012327] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 126.012330] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 126.012333] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 126.012335] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 126.012336] [drm:intel_dump_pipe_config] requested mode: [ 126.012341] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 126.012343] [drm:intel_dump_pipe_config] adjusted mode: [ 126.012347] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 126.012351] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 126.012353] [drm:intel_dump_pipe_config] port clock: 540000 [ 126.012355] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 126.012357] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 126.012359] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 126.012362] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 126.012363] [drm:intel_dump_pipe_config] ips: 0 [ 126.012365] [drm:intel_dump_pipe_config] double wide: 0 [ 126.012367] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 126.012369] [drm:intel_dump_pipe_config] planes on this crtc [ 126.012373] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 126.012375] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 126.012379] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 126.012381] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 126.012383] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 126.012389] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ba9800 state to ffffa2a625bac800 [ 126.012392] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625baf800 state to ffffa2a625bac800 [ 126.012394] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 126.012401] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 126.012403] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 126.012406] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 126.012410] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 126.012413] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 126.012417] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 126.012429] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 126.012440] [drm:intel_power_well_enable] enabling DDI A/E power well [ 126.012445] [drm:skl_set_power_well] Enabling DDI A/E power well [ 126.012452] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 126.018498] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 126.018502] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 126.018506] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 126.018510] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 126.018513] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 126.018516] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 126.018519] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 126.018522] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 126.018524] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 126.018527] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 126.018530] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 126.018533] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 126.018535] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 126.018538] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 126.018541] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 126.018544] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 126.018547] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 126.018550] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 126.018555] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 126.018557] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 126.018570] [drm:edp_panel_on] Turn eDP port A panel power on [ 126.018589] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 126.018665] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 126.018683] [drm:wait_panel_status] Wait complete [ 126.018716] [drm:edp_panel_on] Wait for panel power on [ 126.018792] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 126.220337] [drm:wait_panel_status] Wait complete [ 126.221483] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 126.221485] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 126.221486] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 126.221489] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 126.222173] [drm:intel_dp_start_link_train] clock recovery OK [ 126.222175] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 126.222177] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 126.223147] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 126.223149] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 126.223150] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 126.224109] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 126.224281] [drm:skylake_pfit_enable] for crtc_state = ffffa2a625bab000 [ 126.224379] [drm:intel_enable_pipe] enabling pipe A [ 126.224389] [drm:intel_edp_backlight_on.part.29] [ 126.224392] [drm:intel_panel_enable_backlight] pipe A [ 126.224476] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 126.224532] [drm:intel_psr_enable] PSR disable by flag [ 126.224534] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 126.241324] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 126.241335] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 126.241355] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 126.241365] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 126.241370] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 126.241394] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 126.241399] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa000 state to ffffa2a625bac800 [ 126.241401] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 126.241411] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 126.257907] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 126.257912] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 126.257939] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 126.257942] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 126.258231] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 126.258237] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565cc0 state to ffffa2a625bac800 [ 126.258242] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab000 state to ffffa2a625bac800 [ 126.258245] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565cc0 to [CRTC:26:pipe A] [ 126.258248] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625565cc0 [ 126.258251] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 126.258260] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 126.258263] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 126.258276] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 126.258308] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 126.258312] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 126.258348] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 126.258353] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565a80 state to ffffa2a625bac800 [ 126.258359] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa000 state to ffffa2a625bac800 [ 126.258362] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565a80 to [CRTC:26:pipe A] [ 126.258365] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625565a80 [ 126.258367] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 126.258373] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 126.258376] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 126.258386] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 126.258404] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 126.258407] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 126.258432] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 126.258435] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565cc0 state to ffffa2a625bac800 [ 126.258438] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab000 state to ffffa2a625bac800 [ 126.258440] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565cc0 to [CRTC:26:pipe A] [ 126.258442] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625565cc0 [ 126.258444] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 126.258447] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 126.258449] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 126.258478] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 126.258493] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 126.258496] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 126.258536] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 126.258539] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565a80 state to ffffa2a625bac800 [ 126.258542] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa000 state to ffffa2a625bac800 [ 126.258544] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565a80 to [CRTC:26:pipe A] [ 126.258546] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625565a80 [ 126.258549] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 126.258553] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 126.258555] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 126.258562] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 126.258574] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 126.258577] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 126.258593] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 126.258596] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565cc0 state to ffffa2a625bac800 [ 126.258599] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab000 state to ffffa2a625bac800 [ 126.258601] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565cc0 to [CRTC:26:pipe A] [ 126.258603] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625565cc0 [ 126.258605] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 126.258608] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 126.258610] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 126.258617] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 126.258631] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 126.258633] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 126.258653] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 126.258655] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565a80 state to ffffa2a625bac800 [ 126.258659] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa000 state to ffffa2a625bac800 [ 126.258661] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565a80 to [CRTC:26:pipe A] [ 126.258663] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625565a80 [ 126.258665] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 126.258668] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 126.258670] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 126.258677] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 126.258689] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 126.258692] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 126.258712] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 126.258714] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565cc0 state to ffffa2a625bac800 [ 126.258717] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab000 state to ffffa2a625bac800 [ 126.258720] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565cc0 to [CRTC:26:pipe A] [ 126.258722] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625565cc0 [ 126.258724] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 126.258727] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 126.258729] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 126.258735] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 126.258749] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 126.258751] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 126.258770] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 126.258773] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565a80 state to ffffa2a625bac800 [ 126.258776] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa000 state to ffffa2a625bac800 [ 126.258777] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565a80 to [CRTC:26:pipe A] [ 126.258779] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625565a80 [ 126.258781] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 126.258785] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 126.258787] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 126.258793] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 126.258805] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 126.258807] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 126.258824] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 126.258827] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565cc0 state to ffffa2a625bac800 [ 126.258829] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab000 state to ffffa2a625bac800 [ 126.258831] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565cc0 to [CRTC:26:pipe A] [ 126.258832] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625565cc0 [ 126.258834] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 126.258840] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 126.258841] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 126.258847] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 126.258864] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 126.258866] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 126.258901] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 126.258903] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565a80 state to ffffa2a625bac800 [ 126.258906] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa000 state to ffffa2a625bac800 [ 126.258908] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565a80 to [CRTC:26:pipe A] [ 126.258910] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625565a80 [ 126.258912] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 126.258915] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 126.258917] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 126.258922] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 126.258936] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 126.258938] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 127.002179] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ba9000 [ 127.002184] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa800 state to ffffa2a625ba9000 [ 127.002187] [drm:drm_atomic_check_only] checking ffffa2a625ba9000 [ 127.002191] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 127.002193] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 127.002196] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ba9000 [ 127.002199] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf77e0 state to ffffa2a625ba9000 [ 127.002203] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625565cc0 state to ffffa2a625ba9000 [ 127.002219] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565480 state to ffffa2a625ba9000 [ 127.002222] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ba9000 [ 127.002227] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 127.002228] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 127.002236] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 127.002241] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 127.002249] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 127.002252] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 127.002255] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 127.002258] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625baa800 for pipe A [ 127.002260] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 127.002262] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 127.002265] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 127.002267] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 127.002270] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 127.002271] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 127.002273] [drm:intel_dump_pipe_config] requested mode: [ 127.002278] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 127.002280] [drm:intel_dump_pipe_config] adjusted mode: [ 127.002283] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 127.002287] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 127.002288] [drm:intel_dump_pipe_config] port clock: 540000 [ 127.002290] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 127.002292] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 127.002294] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 127.002296] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 127.002298] [drm:intel_dump_pipe_config] ips: 0 [ 127.002300] [drm:intel_dump_pipe_config] double wide: 0 [ 127.002302] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 127.002303] [drm:intel_dump_pipe_config] planes on this crtc [ 127.002306] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 127.002324] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 127.002327] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 127.002330] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 127.002332] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 127.002335] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 127.002337] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 127.002347] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625bab800 state to ffffa2a625ba9000 [ 127.002352] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625baf000 state to ffffa2a625ba9000 [ 127.002355] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 127.002368] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 127.002371] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 127.002374] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 127.002377] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 127.002380] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 127.002386] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 127.002389] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 127.002394] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 127.002404] [drm:drm_atomic_commit] commiting ffffa2a625ba9000 [ 127.003530] [drm:intel_edp_backlight_off.part.30] [ 127.205566] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 127.205624] [drm:intel_disable_pipe] disabling pipe A [ 127.210017] [drm:edp_panel_off] Turn eDP port A panel power off [ 127.210055] [drm:edp_panel_off] Wait for panel power off time [ 127.210132] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 127.210741] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 127.210746] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 127.210771] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 127.260826] [drm:wait_panel_status] Wait complete [ 127.260844] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 127.260864] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 127.260867] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 127.260884] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 127.260900] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 127.262493] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 127.262499] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 127.262503] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 127.263135] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 127.263142] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 127.263146] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 127.263152] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 127.263156] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 127.263159] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 127.263162] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 127.263165] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 127.263169] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 127.263172] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 127.263175] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 127.263178] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 127.263181] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 127.263184] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 127.263187] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 127.263192] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 127.263195] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 127.263198] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 127.263208] [drm:intel_power_well_disable] disabling DDI A/E power well [ 127.263212] [drm:skl_set_power_well] Disabling DDI A/E power well [ 127.263217] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 127.263221] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 127.263226] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 127.263236] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ba9000 [ 127.263242] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ba9000 [ 127.861756] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 127.861776] [drm:wait_panel_status] Wait complete [ 127.861831] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 127.861845] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 127.911122] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 127.911127] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 127.911131] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 128.070152] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 128.071252] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 128.529388] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e5800 [ 128.529395] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b2240 state to ffffa2a6288e5800 [ 128.529402] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e1000 state to ffffa2a6288e5800 [ 128.529406] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b2240 to [NOCRTC] [ 128.529409] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a6263b2240 [ 128.529412] [drm:drm_atomic_check_only] checking ffffa2a6288e5800 [ 128.529426] [drm:drm_atomic_commit] commiting ffffa2a6288e5800 [ 128.529438] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e5800 [ 128.529443] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e5800 [ 128.529458] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 128.529465] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 128.529469] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e5800 [ 128.529491] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e0000 state to ffffa2a6288e5800 [ 128.529494] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6263b2300 state to ffffa2a6288e5800 [ 128.529499] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e0000 [ 128.529502] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b2300 to [CRTC:26:pipe A] [ 128.529505] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a6263b2300 [ 128.529509] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e5800 [ 128.529514] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9b80 state to ffffa2a6288e5800 [ 128.529518] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9b80 to [NOCRTC] [ 128.529521] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9b80 to [CRTC:26:pipe A] [ 128.529524] [drm:drm_atomic_check_only] checking ffffa2a6288e5800 [ 128.529530] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 128.529534] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 128.529536] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 128.529539] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 128.529542] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e5800 [ 128.529547] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e5800 [ 128.529551] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 128.529554] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 128.529563] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 128.529570] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 128.529581] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 128.529585] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 128.529589] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 128.529593] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e0000 for pipe A [ 128.529596] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 128.529599] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 128.529602] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 128.529606] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 128.529610] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 128.529612] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 128.529615] [drm:intel_dump_pipe_config] requested mode: [ 128.529621] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 128.529623] [drm:intel_dump_pipe_config] adjusted mode: [ 128.529628] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 128.529632] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 128.529635] [drm:intel_dump_pipe_config] port clock: 540000 [ 128.529637] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 128.529640] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 128.529643] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 128.529646] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 128.529649] [drm:intel_dump_pipe_config] ips: 0 [ 128.529651] [drm:intel_dump_pipe_config] double wide: 0 [ 128.529654] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 128.529656] [drm:intel_dump_pipe_config] planes on this crtc [ 128.529660] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 128.529664] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 128.529668] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 128.529671] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 128.529674] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 128.529681] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e7800 state to ffffa2a6288e5800 [ 128.529686] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e7000 state to ffffa2a6288e5800 [ 128.529689] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 128.529697] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 128.529701] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 128.529704] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 128.529709] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 128.529712] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 128.529717] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 128.529731] [drm:drm_atomic_commit] commiting ffffa2a6288e5800 [ 128.529749] [drm:intel_power_well_enable] enabling DDI A/E power well [ 128.529755] [drm:skl_set_power_well] Enabling DDI A/E power well [ 128.529764] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 128.534286] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 128.534295] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 128.534301] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 128.534309] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 128.534313] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 128.534317] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 128.534321] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 128.534325] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 128.534329] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 128.534333] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 128.534337] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 128.534342] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 128.534345] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 128.534349] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 128.534354] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 128.534360] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 128.534364] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 128.534368] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 128.534377] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 128.534380] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 128.534402] [drm:edp_panel_on] Turn eDP port A panel power on [ 128.534420] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 128.534521] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 128.534541] [drm:wait_panel_status] Wait complete [ 128.534580] [drm:edp_panel_on] Wait for panel power on [ 128.534658] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 128.736901] [drm:wait_panel_status] Wait complete [ 128.738062] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 128.738065] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 128.738067] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 128.738071] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 128.738752] [drm:intel_dp_start_link_train] clock recovery OK [ 128.738756] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 128.738758] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 128.739738] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 128.739740] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 128.739741] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 128.740701] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 128.740867] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e0000 [ 128.740942] [drm:intel_enable_pipe] enabling pipe A [ 128.740948] [drm:intel_edp_backlight_on.part.29] [ 128.740950] [drm:intel_panel_enable_backlight] pipe A [ 128.741029] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 128.741083] [drm:intel_psr_enable] PSR disable by flag [ 128.741084] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 128.757867] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 128.757874] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 128.757887] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 128.757894] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e5800 [ 128.757898] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e5800 [ 128.757914] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e18800 [ 128.757917] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e19800 state to ffffa2a625e18800 [ 128.757918] [drm:drm_atomic_check_only] checking ffffa2a625e18800 [ 128.757925] [drm:drm_atomic_commit] commiting ffffa2a625e18800 [ 128.774656] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e18800 [ 128.774660] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e18800 [ 128.774681] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 128.774683] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 128.774843] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ba8800 [ 128.774847] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625565180 state to ffffa2a625ba8800 [ 128.774851] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf000 state to ffffa2a625ba8800 [ 128.774853] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625565180 to [CRTC:26:pipe A] [ 128.774854] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625565180 [ 128.774856] [drm:drm_atomic_check_only] checking ffffa2a625ba8800 [ 128.774863] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 128.774864] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 128.774873] [drm:drm_atomic_commit] commiting ffffa2a625ba8800 [ 128.774914] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ba8800 [ 128.774918] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ba8800 [ 130.344952] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1d000 [ 130.344960] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e1e000 state to ffffa2a625e1d000 [ 130.344964] [drm:drm_atomic_check_only] checking ffffa2a625e1d000 [ 130.344969] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 130.344972] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 130.344975] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1d000 [ 130.344979] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba6b60 state to ffffa2a625e1d000 [ 130.344983] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a62886dd80 state to ffffa2a625e1d000 [ 130.344986] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62886de40 state to ffffa2a625e1d000 [ 130.344990] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1d000 [ 130.344994] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 130.344996] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 130.345005] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 130.345011] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 130.345020] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 130.345024] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 130.345027] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 130.345031] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625e1e000 for pipe A [ 130.345034] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 130.345036] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 130.345039] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 130.345042] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 130.345045] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 130.345047] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 130.345048] [drm:intel_dump_pipe_config] requested mode: [ 130.345054] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 130.345056] [drm:intel_dump_pipe_config] adjusted mode: [ 130.345060] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 130.345064] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 130.345066] [drm:intel_dump_pipe_config] port clock: 540000 [ 130.345068] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 130.345070] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 130.345073] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 130.345076] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 130.345078] [drm:intel_dump_pipe_config] ips: 0 [ 130.345080] [drm:intel_dump_pipe_config] double wide: 0 [ 130.345082] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 130.345084] [drm:intel_dump_pipe_config] planes on this crtc [ 130.345087] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 130.345091] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 130.345094] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 130.345097] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 130.345100] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 130.345103] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 130.345105] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 130.345111] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625e1b800 state to ffffa2a625e1d000 [ 130.345116] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625e1b000 state to ffffa2a625e1d000 [ 130.345118] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 130.345126] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 130.345129] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 130.345131] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 130.345134] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 130.345137] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 130.345142] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 130.345145] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 130.345149] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 130.345159] [drm:drm_atomic_commit] commiting ffffa2a625e1d000 [ 130.346565] [drm:intel_edp_backlight_off.part.30] [ 130.549723] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 130.549780] [drm:intel_disable_pipe] disabling pipe A [ 130.558552] [drm:edp_panel_off] Turn eDP port A panel power off [ 130.558593] [drm:edp_panel_off] Wait for panel power off time [ 130.558671] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 130.559254] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 130.559260] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 130.559287] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 130.609491] [drm:wait_panel_status] Wait complete [ 130.609522] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 130.609544] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 130.609547] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 130.609567] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 130.609583] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 130.611057] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 130.611064] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 130.611068] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 130.614183] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 130.614190] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 130.614195] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 130.614201] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 130.614205] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 130.614209] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 130.614212] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 130.614215] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 130.614219] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 130.614222] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 130.614225] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 130.614229] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 130.614232] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 130.614235] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 130.614239] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 130.614244] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 130.614247] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 130.614251] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 130.614261] [drm:intel_power_well_disable] disabling DDI A/E power well [ 130.614266] [drm:skl_set_power_well] Disabling DDI A/E power well [ 130.614271] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 130.614276] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 130.614281] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 130.614291] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1d000 [ 130.614298] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1d000 [ 131.189747] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 131.189767] [drm:wait_panel_status] Wait complete [ 131.189822] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 131.189836] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 131.239121] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 131.239126] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 131.239129] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 131.277004] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e7800 [ 131.277010] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62978c300 state to ffffa2a6288e7800 [ 131.277014] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e6800 state to ffffa2a6288e7800 [ 131.277017] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62978c300 to [NOCRTC] [ 131.277019] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62978c300 [ 131.277021] [drm:drm_atomic_check_only] checking ffffa2a6288e7800 [ 131.277031] [drm:drm_atomic_commit] commiting ffffa2a6288e7800 [ 131.277041] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e7800 [ 131.277045] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e7800 [ 131.277056] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 131.277061] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 131.277064] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e7800 [ 131.277066] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e5000 state to ffffa2a6288e7800 [ 131.277069] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a62978cb40 state to ffffa2a6288e7800 [ 131.277072] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e5000 [ 131.277074] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62978cb40 to [CRTC:26:pipe A] [ 131.277077] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a62978cb40 [ 131.277079] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e7800 [ 131.277083] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9740 state to ffffa2a6288e7800 [ 131.277086] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9740 to [NOCRTC] [ 131.277089] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9740 to [CRTC:26:pipe A] [ 131.277091] [drm:drm_atomic_check_only] checking ffffa2a6288e7800 [ 131.277095] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 131.277098] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 131.277100] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 131.277102] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 131.277104] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e7800 [ 131.277107] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e7800 [ 131.277110] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 131.277112] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 131.277119] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 131.277124] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 131.277132] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 131.277135] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 131.277138] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 131.277141] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e5000 for pipe A [ 131.277144] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 131.277145] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 131.277148] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 131.277150] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 131.277153] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 131.277155] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 131.277156] [drm:intel_dump_pipe_config] requested mode: [ 131.277161] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 131.277162] [drm:intel_dump_pipe_config] adjusted mode: [ 131.277166] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 131.277169] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 131.277171] [drm:intel_dump_pipe_config] port clock: 540000 [ 131.277172] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 131.277175] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 131.277177] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 131.277179] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 131.277181] [drm:intel_dump_pipe_config] ips: 0 [ 131.277182] [drm:intel_dump_pipe_config] double wide: 0 [ 131.277184] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 131.277186] [drm:intel_dump_pipe_config] planes on this crtc [ 131.277189] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 131.277192] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 131.277195] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 131.277197] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 131.277199] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 131.277204] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e0800 state to ffffa2a6288e7800 [ 131.277206] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e2800 state to ffffa2a6288e7800 [ 131.277209] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 131.277215] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 131.277217] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 131.277220] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 131.277224] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 131.277226] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 131.277230] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 131.277240] [drm:drm_atomic_commit] commiting ffffa2a6288e7800 [ 131.277250] [drm:intel_power_well_enable] enabling DDI A/E power well [ 131.277255] [drm:skl_set_power_well] Enabling DDI A/E power well [ 131.277261] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 131.283996] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled [ 131.286149] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 131.286155] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 131.286160] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 131.286165] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 131.286169] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 131.286171] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 131.286174] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 131.286177] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 131.286180] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 131.286183] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 131.286186] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 131.286189] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 131.286192] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 131.286194] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 131.286198] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 131.286202] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 131.286205] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 131.286208] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 131.286214] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 131.286216] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 131.398143] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 131.398149] [drm:edp_panel_on] Turn eDP port A panel power on [ 131.398169] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 131.398251] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 131.398269] [drm:wait_panel_status] Wait complete [ 131.398302] [drm:edp_panel_on] Wait for panel power on [ 131.398378] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 131.598661] [drm:wait_panel_status] Wait complete [ 131.600445] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 131.600448] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 131.600450] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 131.600453] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 131.601127] [drm:intel_dp_start_link_train] clock recovery OK [ 131.601130] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 131.601132] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 131.602105] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 131.602108] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 131.602109] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 131.603064] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 131.603229] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e5000 [ 131.603303] [drm:intel_enable_pipe] enabling pipe A [ 131.603309] [drm:intel_edp_backlight_on.part.29] [ 131.603311] [drm:intel_panel_enable_backlight] pipe A [ 131.603390] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 131.603444] [drm:intel_psr_enable] PSR disable by flag [ 131.603445] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 131.620258] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 131.620265] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 131.620279] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 131.620285] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e7800 [ 131.620289] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e7800 [ 131.620697] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 131.620698] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa800 [ 131.620702] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9000 state to ffffa2a625baa800 [ 131.620703] [drm:drm_atomic_check_only] checking ffffa2a625baa800 [ 131.620710] [drm:drm_atomic_commit] commiting ffffa2a625baa800 [ 131.636922] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa800 [ 131.636927] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa800 [ 131.636949] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 131.636951] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 131.637117] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa800 [ 131.637136] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b26c0 state to ffffa2a625baa800 [ 131.637139] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf800 state to ffffa2a625baa800 [ 131.637140] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b26c0 to [CRTC:26:pipe A] [ 131.637142] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b26c0 [ 131.637144] [drm:drm_atomic_check_only] checking ffffa2a625baa800 [ 131.637150] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 131.637151] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 131.637161] [drm:drm_atomic_commit] commiting ffffa2a625baa800 [ 131.637186] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa800 [ 131.637189] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa800 [ 133.164949] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1d800 [ 133.164959] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e1c000 state to ffffa2a625e1d800 [ 133.164963] [drm:drm_atomic_check_only] checking ffffa2a625e1d800 [ 133.164967] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 133.164969] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 133.164972] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1d800 [ 133.164976] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba6340 state to ffffa2a625e1d800 [ 133.164980] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a626627540 state to ffffa2a625e1d800 [ 133.164982] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a626627840 state to ffffa2a625e1d800 [ 133.164986] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1d800 [ 133.164989] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 133.164990] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 133.164998] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 133.165003] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 133.165011] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 133.165014] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 133.165017] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 133.165020] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625e1c000 for pipe A [ 133.165022] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 133.165024] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 133.165027] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 133.165030] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 133.165032] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 133.165034] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 133.165035] [drm:intel_dump_pipe_config] requested mode: [ 133.165040] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 133.165042] [drm:intel_dump_pipe_config] adjusted mode: [ 133.165045] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 133.165048] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 133.165050] [drm:intel_dump_pipe_config] port clock: 540000 [ 133.165052] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 133.165054] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 133.165056] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 133.165058] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 133.165060] [drm:intel_dump_pipe_config] ips: 0 [ 133.165062] [drm:intel_dump_pipe_config] double wide: 0 [ 133.165064] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 133.165065] [drm:intel_dump_pipe_config] planes on this crtc [ 133.165068] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 133.165071] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 133.165074] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 133.165076] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 133.165078] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 133.165081] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 133.165083] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 133.165088] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625e1b000 state to ffffa2a625e1d800 [ 133.165091] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625e1b800 state to ffffa2a625e1d800 [ 133.165093] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 133.165099] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 133.165102] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 133.165104] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 133.165107] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 133.165109] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 133.165113] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 133.165116] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 133.165119] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 133.165128] [drm:drm_atomic_commit] commiting ffffa2a625e1d800 [ 133.166588] [drm:intel_edp_backlight_off.part.30] [ 133.373725] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 133.373765] [drm:intel_disable_pipe] disabling pipe A [ 133.388934] [drm:edp_panel_off] Turn eDP port A panel power off [ 133.388974] [drm:edp_panel_off] Wait for panel power off time [ 133.389052] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 133.389623] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 133.389629] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 133.389654] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 133.439712] [drm:wait_panel_status] Wait complete [ 133.439729] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 133.439748] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 133.439752] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 133.439769] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 133.439787] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 133.441387] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 133.441392] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 133.441396] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 133.441987] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 133.441994] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 133.441998] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 133.442004] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 133.442008] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 133.442011] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 133.442014] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 133.442017] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 133.442020] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 133.442023] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 133.442026] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 133.442030] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 133.442033] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 133.442036] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 133.442039] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 133.442044] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 133.442047] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 133.442050] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 133.442060] [drm:intel_power_well_disable] disabling DDI A/E power well [ 133.442065] [drm:skl_set_power_well] Disabling DDI A/E power well [ 133.442069] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 133.442074] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 133.442078] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 133.442089] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1d800 [ 133.442095] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1d800 [ 134.005599] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 134.005616] [drm:wait_panel_status] Wait complete [ 134.005669] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 134.005680] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 134.054998] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 134.055002] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 134.055003] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 134.214153] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 134.215253] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 134.611452] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e0800 [ 134.611458] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62549fcc0 state to ffffa2a6288e0800 [ 134.611463] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e2800 state to ffffa2a6288e0800 [ 134.611465] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62549fcc0 to [NOCRTC] [ 134.611467] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62549fcc0 [ 134.611469] [drm:drm_atomic_check_only] checking ffffa2a6288e0800 [ 134.611480] [drm:drm_atomic_commit] commiting ffffa2a6288e0800 [ 134.611490] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e0800 [ 134.611493] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e0800 [ 134.611504] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 134.611510] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 134.611513] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e0800 [ 134.611515] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e1800 state to ffffa2a6288e0800 [ 134.611518] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a62549fd80 state to ffffa2a6288e0800 [ 134.611538] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e1800 [ 134.611540] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62549fd80 to [CRTC:26:pipe A] [ 134.611542] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a62549fd80 [ 134.611545] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e0800 [ 134.611549] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9740 state to ffffa2a6288e0800 [ 134.611552] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9740 to [NOCRTC] [ 134.611554] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9740 to [CRTC:26:pipe A] [ 134.611556] [drm:drm_atomic_check_only] checking ffffa2a6288e0800 [ 134.611561] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 134.611563] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 134.611565] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 134.611567] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 134.611570] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e0800 [ 134.611573] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e0800 [ 134.611576] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 134.611578] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 134.611585] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 134.611590] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 134.611598] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 134.611601] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 134.611604] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 134.611607] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e1800 for pipe A [ 134.611609] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 134.611611] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 134.611614] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 134.611617] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 134.611619] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 134.611621] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 134.611622] [drm:intel_dump_pipe_config] requested mode: [ 134.611627] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 134.611628] [drm:intel_dump_pipe_config] adjusted mode: [ 134.611632] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 134.611635] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 134.611637] [drm:intel_dump_pipe_config] port clock: 540000 [ 134.611638] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 134.611641] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 134.611643] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 134.611645] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 134.611647] [drm:intel_dump_pipe_config] ips: 0 [ 134.611648] [drm:intel_dump_pipe_config] double wide: 0 [ 134.611650] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 134.611652] [drm:intel_dump_pipe_config] planes on this crtc [ 134.611655] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 134.611658] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 134.611661] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 134.611663] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 134.611665] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 134.611670] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e5000 state to ffffa2a6288e0800 [ 134.611673] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e7800 state to ffffa2a6288e0800 [ 134.611675] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 134.611682] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 134.611684] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 134.611686] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 134.611690] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 134.611693] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 134.611696] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 134.611707] [drm:drm_atomic_commit] commiting ffffa2a6288e0800 [ 134.611718] [drm:intel_power_well_enable] enabling DDI A/E power well [ 134.611722] [drm:skl_set_power_well] Enabling DDI A/E power well [ 134.611728] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 134.618431] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled [ 134.629395] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 134.629401] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 134.629405] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 134.629411] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 134.629415] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 134.629418] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 134.629421] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 134.629424] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 134.629427] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 134.629429] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 134.629432] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 134.629436] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 134.629438] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 134.629441] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 134.629444] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 134.629448] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 134.629451] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 134.629454] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 134.629461] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 134.629463] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 134.629478] [drm:edp_panel_on] Turn eDP port A panel power on [ 134.629497] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 134.629589] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 134.629607] [drm:wait_panel_status] Wait complete [ 134.629641] [drm:edp_panel_on] Wait for panel power on [ 134.629716] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 134.830604] [drm:wait_panel_status] Wait complete [ 134.831748] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 134.831751] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 134.831752] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 134.831755] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 134.832423] [drm:intel_dp_start_link_train] clock recovery OK [ 134.832426] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 134.832427] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 134.833397] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 134.833399] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 134.833400] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 134.834360] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 134.834533] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e1800 [ 134.834632] [drm:intel_enable_pipe] enabling pipe A [ 134.834641] [drm:intel_edp_backlight_on.part.29] [ 134.834645] [drm:intel_panel_enable_backlight] pipe A [ 134.834743] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 134.834796] [drm:intel_psr_enable] PSR disable by flag [ 134.834797] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 134.851611] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 134.851619] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 134.851632] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 134.851639] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e0800 [ 134.851643] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e0800 [ 134.851662] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ba9000 [ 134.851664] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625ba9000 [ 134.851666] [drm:drm_atomic_check_only] checking ffffa2a625ba9000 [ 134.851672] [drm:drm_atomic_commit] commiting ffffa2a625ba9000 [ 134.868182] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ba9000 [ 134.868187] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ba9000 [ 134.868208] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 134.868210] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 134.868365] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ba9000 [ 134.868368] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b2180 state to ffffa2a625ba9000 [ 134.868371] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa000 state to ffffa2a625ba9000 [ 134.868372] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b2180 to [CRTC:26:pipe A] [ 134.868374] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b2180 [ 134.868375] [drm:drm_atomic_check_only] checking ffffa2a625ba9000 [ 134.868381] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 134.868382] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 134.868405] [drm:drm_atomic_commit] commiting ffffa2a625ba9000 [ 134.868430] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ba9000 [ 134.868433] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ba9000 [ 135.880353] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ae4000 [ 135.880362] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ae3800 state to ffffa2a625ae4000 [ 135.880367] [drm:drm_atomic_check_only] checking ffffa2a625ae4000 [ 135.880373] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 135.880376] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 135.880381] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae4000 [ 135.880387] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62882f4c0 state to ffffa2a625ae4000 [ 135.880392] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625db8b40 state to ffffa2a625ae4000 [ 135.880401] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625db8cc0 state to ffffa2a625ae4000 [ 135.880406] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae4000 [ 135.880411] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 135.880414] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 135.880425] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 135.880433] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 135.880445] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 135.880450] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 135.880454] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 135.880459] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ae3800 for pipe A [ 135.880463] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 135.880466] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 135.880470] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 135.880474] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 135.880478] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 135.880480] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 135.880483] [drm:intel_dump_pipe_config] requested mode: [ 135.880490] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 135.880493] [drm:intel_dump_pipe_config] adjusted mode: [ 135.880498] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 135.880503] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 135.880506] [drm:intel_dump_pipe_config] port clock: 540000 [ 135.880508] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 135.880512] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 135.880516] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 135.880521] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 135.880525] [drm:intel_dump_pipe_config] ips: 0 [ 135.880528] [drm:intel_dump_pipe_config] double wide: 0 [ 135.880564] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 135.880567] [drm:intel_dump_pipe_config] planes on this crtc [ 135.880573] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 135.880578] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 135.880584] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 135.880590] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 135.880596] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 135.880602] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 135.880607] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 135.880618] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ae4800 state to ffffa2a625ae4000 [ 135.880623] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625ae0800 state to ffffa2a625ae4000 [ 135.880627] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 135.880640] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 135.880646] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 135.880651] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 135.880659] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 135.880664] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 135.880671] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 135.880675] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 135.880681] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 135.880695] [drm:drm_atomic_commit] commiting ffffa2a625ae4000 [ 135.882681] [drm:intel_edp_backlight_off.part.30] [ 136.085863] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 136.085922] [drm:intel_disable_pipe] disabling pipe A [ 136.103609] [drm:edp_panel_off] Turn eDP port A panel power off [ 136.103651] [drm:edp_panel_off] Wait for panel power off time [ 136.103734] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 136.104197] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 136.104204] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 136.104225] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 136.154570] [drm:wait_panel_status] Wait complete [ 136.154589] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 136.154608] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 136.154613] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 136.154634] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 136.154651] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 136.156119] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 136.156126] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 136.156130] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 136.156913] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 136.156920] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 136.156926] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 136.156933] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 136.156937] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 136.156941] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 136.156945] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 136.156949] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 136.156952] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 136.156956] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 136.156960] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 136.156964] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 136.156967] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 136.156970] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 136.156974] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 136.156980] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 136.156984] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 136.156987] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 136.156999] [drm:intel_power_well_disable] disabling DDI A/E power well [ 136.157004] [drm:skl_set_power_well] Disabling DDI A/E power well [ 136.157009] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 136.157014] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 136.157019] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 136.157030] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ae4000 [ 136.157038] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ae4000 [ 136.758084] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 136.758104] [drm:wait_panel_status] Wait complete [ 136.758159] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 136.758173] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 136.807473] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 136.807478] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 136.807481] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 136.966179] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 136.967297] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 137.489426] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e7000 [ 137.489432] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6296cad80 state to ffffa2a6288e7000 [ 137.489436] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e4800 state to ffffa2a6288e7000 [ 137.489439] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6296cad80 to [NOCRTC] [ 137.489441] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a6296cad80 [ 137.489443] [drm:drm_atomic_check_only] checking ffffa2a6288e7000 [ 137.489454] [drm:drm_atomic_commit] commiting ffffa2a6288e7000 [ 137.489463] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e7000 [ 137.489467] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e7000 [ 137.489478] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 137.489484] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 137.489486] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e7000 [ 137.489489] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e0000 state to ffffa2a6288e7000 [ 137.489492] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6296cae40 state to ffffa2a6288e7000 [ 137.489495] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e0000 [ 137.489497] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6296cae40 to [CRTC:26:pipe A] [ 137.489499] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a6296cae40 [ 137.489502] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e7000 [ 137.489506] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9740 state to ffffa2a6288e7000 [ 137.489509] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9740 to [NOCRTC] [ 137.489511] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9740 to [CRTC:26:pipe A] [ 137.489513] [drm:drm_atomic_check_only] checking ffffa2a6288e7000 [ 137.489518] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 137.489521] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 137.489523] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 137.489525] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 137.489527] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e7000 [ 137.489530] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e7000 [ 137.489534] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 137.489535] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 137.489543] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 137.489564] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 137.489572] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 137.489575] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 137.489578] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 137.489581] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e0000 for pipe A [ 137.489583] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 137.489585] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 137.489588] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 137.489590] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 137.489593] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 137.489595] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 137.489596] [drm:intel_dump_pipe_config] requested mode: [ 137.489601] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 137.489602] [drm:intel_dump_pipe_config] adjusted mode: [ 137.489606] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 137.489609] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 137.489611] [drm:intel_dump_pipe_config] port clock: 540000 [ 137.489613] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 137.489615] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 137.489617] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 137.489619] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 137.489621] [drm:intel_dump_pipe_config] ips: 0 [ 137.489622] [drm:intel_dump_pipe_config] double wide: 0 [ 137.489624] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 137.489626] [drm:intel_dump_pipe_config] planes on this crtc [ 137.489629] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 137.489632] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 137.489635] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 137.489637] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 137.489639] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 137.489644] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e5800 state to ffffa2a6288e7000 [ 137.489647] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e1000 state to ffffa2a6288e7000 [ 137.489649] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 137.489655] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 137.489657] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 137.489660] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 137.489664] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 137.489666] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 137.489670] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 137.489680] [drm:drm_atomic_commit] commiting ffffa2a6288e7000 [ 137.489692] [drm:intel_power_well_enable] enabling DDI A/E power well [ 137.489696] [drm:skl_set_power_well] Enabling DDI A/E power well [ 137.489702] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 137.494190] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 137.494196] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 137.494200] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 137.494205] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 137.494208] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 137.494211] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 137.494214] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 137.494217] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 137.494219] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 137.494222] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 137.494225] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 137.494228] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 137.494230] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 137.494232] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 137.494235] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 137.494239] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 137.494243] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 137.494245] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 137.494251] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 137.494253] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 137.494268] [drm:edp_panel_on] Turn eDP port A panel power on [ 137.494287] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 137.494363] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 137.494380] [drm:wait_panel_status] Wait complete [ 137.494414] [drm:edp_panel_on] Wait for panel power on [ 137.494508] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 137.696419] [drm:wait_panel_status] Wait complete [ 137.697564] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 137.697566] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 137.697568] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 137.697571] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 137.698239] [drm:intel_dp_start_link_train] clock recovery OK [ 137.698241] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 137.698243] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 137.699208] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 137.699208] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 137.699209] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 137.700152] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 137.700317] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e0000 [ 137.700390] [drm:intel_enable_pipe] enabling pipe A [ 137.700396] [drm:intel_edp_backlight_on.part.29] [ 137.700398] [drm:intel_panel_enable_backlight] pipe A [ 137.700476] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 137.700530] [drm:intel_psr_enable] PSR disable by flag [ 137.700530] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 137.717227] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 137.717233] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 137.717245] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 137.717250] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e7000 [ 137.717254] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e7000 [ 137.717270] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ba9800 [ 137.717272] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab000 state to ffffa2a625ba9800 [ 137.717273] [drm:drm_atomic_check_only] checking ffffa2a625ba9800 [ 137.717279] [drm:drm_atomic_commit] commiting ffffa2a625ba9800 [ 137.734009] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ba9800 [ 137.734013] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ba9800 [ 137.734034] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 137.734036] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 137.734206] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ba9800 [ 137.734210] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263b2600 state to ffffa2a625ba9800 [ 137.734214] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625ba9800 [ 137.734215] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263b2600 to [CRTC:26:pipe A] [ 137.734217] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263b2600 [ 137.734219] [drm:drm_atomic_check_only] checking ffffa2a625ba9800 [ 137.734226] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 137.734227] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 137.734237] [drm:drm_atomic_commit] commiting ffffa2a625ba9800 [ 137.734263] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ba9800 [ 137.734265] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ba9800 [ 138.282998] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1c000 [ 138.283005] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e1e000 state to ffffa2a625e1c000 [ 138.283008] [drm:drm_atomic_check_only] checking ffffa2a625e1c000 [ 138.283013] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 138.283015] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 138.283018] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1c000 [ 138.283021] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba6020 state to ffffa2a625e1c000 [ 138.283025] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625f2f780 state to ffffa2a625e1c000 [ 138.283027] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625f2f3c0 state to ffffa2a625e1c000 [ 138.283030] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1c000 [ 138.283034] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 138.283035] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 138.283043] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 138.283048] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 138.283056] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 138.283060] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 138.283062] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 138.283066] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625e1e000 for pipe A [ 138.283068] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 138.283070] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 138.283072] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 138.283075] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 138.283078] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 138.283080] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 138.283081] [drm:intel_dump_pipe_config] requested mode: [ 138.283086] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 138.283087] [drm:intel_dump_pipe_config] adjusted mode: [ 138.283091] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 138.283094] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 138.283096] [drm:intel_dump_pipe_config] port clock: 540000 [ 138.283098] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 138.283100] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 138.283102] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 138.283104] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 138.283106] [drm:intel_dump_pipe_config] ips: 0 [ 138.283107] [drm:intel_dump_pipe_config] double wide: 0 [ 138.283109] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 138.283111] [drm:intel_dump_pipe_config] planes on this crtc [ 138.283114] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 138.283117] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 138.283120] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 138.283122] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 138.283124] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 138.283127] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 138.283129] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 138.283134] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625e19800 state to ffffa2a625e1c000 [ 138.283136] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625e1d800 state to ffffa2a625e1c000 [ 138.283138] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 138.283145] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 138.283147] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 138.283150] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 138.283152] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 138.283154] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 138.283159] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 138.283162] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 138.283165] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 138.283174] [drm:drm_atomic_commit] commiting ffffa2a625e1c000 [ 138.284627] [drm:intel_edp_backlight_off.part.30] [ 138.493868] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 138.493927] [drm:intel_disable_pipe] disabling pipe A [ 138.502911] [drm:edp_panel_off] Turn eDP port A panel power off [ 138.502952] [drm:edp_panel_off] Wait for panel power off time [ 138.503029] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 138.503521] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 138.503526] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 138.503542] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 138.553579] [drm:wait_panel_status] Wait complete [ 138.553596] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 138.553617] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 138.553619] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 138.553637] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 138.553654] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 138.555395] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 138.555401] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 138.555404] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 138.557939] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 138.557946] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 138.557951] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 138.557957] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 138.557960] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 138.557963] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 138.557966] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 138.557970] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 138.557973] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 138.557976] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 138.557979] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 138.557982] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 138.557985] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 138.557988] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 138.557991] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 138.557996] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 138.557999] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 138.558002] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 138.558012] [drm:intel_power_well_disable] disabling DDI A/E power well [ 138.558017] [drm:skl_set_power_well] Disabling DDI A/E power well [ 138.558021] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 138.558026] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 138.558030] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 138.558040] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1c000 [ 138.558046] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1c000 [ 139.125959] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 139.125995] [drm:wait_panel_status] Wait complete [ 139.126056] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 139.126071] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 139.175465] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 139.175470] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 139.175474] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 139.335012] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 139.336074] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 140.914570] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ae7800 [ 140.914595] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625819840 state to ffffa2a625ae7800 [ 140.914599] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ae6800 state to ffffa2a625ae7800 [ 140.914602] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625819840 to [NOCRTC] [ 140.914605] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a625819840 [ 140.914607] [drm:drm_atomic_check_only] checking ffffa2a625ae7800 [ 140.914620] [drm:drm_atomic_commit] commiting ffffa2a625ae7800 [ 140.914631] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ae7800 [ 140.914636] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ae7800 [ 140.914647] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 140.914654] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 140.914657] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ae7800 [ 140.914660] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ae2000 state to ffffa2a625ae7800 [ 140.914663] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625819240 state to ffffa2a625ae7800 [ 140.914667] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625ae2000 [ 140.914670] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625819240 to [CRTC:26:pipe A] [ 140.914673] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a625819240 [ 140.914676] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae7800 [ 140.914680] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62882f1c0 state to ffffa2a625ae7800 [ 140.914683] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62882f1c0 to [NOCRTC] [ 140.914686] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62882f1c0 to [CRTC:26:pipe A] [ 140.914689] [drm:drm_atomic_check_only] checking ffffa2a625ae7800 [ 140.914694] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 140.914697] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 140.914699] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 140.914702] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 140.914704] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae7800 [ 140.914708] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae7800 [ 140.914712] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 140.914714] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 140.914723] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 140.914728] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 140.914738] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 140.914742] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 140.914745] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 140.914749] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ae2000 for pipe A [ 140.914751] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 140.914753] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 140.914756] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 140.914759] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 140.914762] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 140.914764] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 140.914766] [drm:intel_dump_pipe_config] requested mode: [ 140.914771] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 140.914773] [drm:intel_dump_pipe_config] adjusted mode: [ 140.914777] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 140.914781] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 140.914783] [drm:intel_dump_pipe_config] port clock: 540000 [ 140.914785] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 140.914787] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 140.914790] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 140.914793] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 140.914794] [drm:intel_dump_pipe_config] ips: 0 [ 140.914796] [drm:intel_dump_pipe_config] double wide: 0 [ 140.914799] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 140.914801] [drm:intel_dump_pipe_config] planes on this crtc [ 140.914804] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 140.914807] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 140.914811] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 140.914813] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 140.914815] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 140.914821] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ae0000 state to ffffa2a625ae7800 [ 140.914824] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625ae7000 state to ffffa2a625ae7800 [ 140.914826] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 140.914834] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 140.914837] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 140.914839] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 140.914845] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 140.914847] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 140.914852] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 140.914863] [drm:drm_atomic_commit] commiting ffffa2a625ae7800 [ 140.914875] [drm:intel_power_well_enable] enabling DDI A/E power well [ 140.914881] [drm:skl_set_power_well] Enabling DDI A/E power well [ 140.914889] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 140.921718] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 140.921725] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 140.921730] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 140.921737] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 140.921740] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 140.921744] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 140.921747] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 140.921751] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 140.921754] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 140.921757] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 140.921761] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 140.921764] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 140.921767] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 140.921770] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 140.921774] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 140.921779] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 140.921783] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 140.921786] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 140.921793] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 140.921796] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 140.921814] [drm:edp_panel_on] Turn eDP port A panel power on [ 140.921834] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 140.921912] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 140.921930] [drm:wait_panel_status] Wait complete [ 140.921964] [drm:edp_panel_on] Wait for panel power on [ 140.922040] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 141.122551] [drm:wait_panel_status] Wait complete [ 141.123770] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 141.123773] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 141.123775] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 141.123778] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 141.124456] [drm:intel_dp_start_link_train] clock recovery OK [ 141.124459] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 141.124461] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 141.125441] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 141.125443] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 141.125445] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 141.126410] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 141.126586] [drm:skylake_pfit_enable] for crtc_state = ffffa2a625ae2000 [ 141.126685] [drm:intel_enable_pipe] enabling pipe A [ 141.126692] [drm:intel_edp_backlight_on.part.29] [ 141.126694] [drm:intel_panel_enable_backlight] pipe A [ 141.126773] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 141.126827] [drm:intel_psr_enable] PSR disable by flag [ 141.126828] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 141.143657] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 141.143663] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 141.143677] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 141.143683] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ae7800 [ 141.143687] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ae7800 [ 141.143705] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bae000 [ 141.143707] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625bae000 [ 141.143708] [drm:drm_atomic_check_only] checking ffffa2a625bae000 [ 141.143714] [drm:drm_atomic_commit] commiting ffffa2a625bae000 [ 141.160272] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bae000 [ 141.160277] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bae000 [ 141.160297] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 141.160299] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 141.160467] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bae000 [ 141.160470] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6296ca0c0 state to ffffa2a625bae000 [ 141.160472] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab000 state to ffffa2a625bae000 [ 141.160474] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6296ca0c0 to [CRTC:26:pipe A] [ 141.160475] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6296ca0c0 [ 141.160476] [drm:drm_atomic_check_only] checking ffffa2a625bae000 [ 141.160482] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 141.160483] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 141.160491] [drm:drm_atomic_commit] commiting ffffa2a625bae000 [ 141.160514] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bae000 [ 141.160516] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bae000 [ 142.358248] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1b800 [ 142.358254] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e1d800 state to ffffa2a625e1b800 [ 142.358257] [drm:drm_atomic_check_only] checking ffffa2a625e1b800 [ 142.358262] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 142.358265] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 142.358267] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1b800 [ 142.358271] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba62c0 state to ffffa2a625e1b800 [ 142.358274] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6251ce480 state to ffffa2a625e1b800 [ 142.358276] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6251ce540 state to ffffa2a625e1b800 [ 142.358279] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1b800 [ 142.358283] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 142.358285] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 142.358292] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 142.358297] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 142.358304] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 142.358307] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 142.358310] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 142.358313] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625e1d800 for pipe A [ 142.358315] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 142.358317] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 142.358319] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 142.358322] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 142.358324] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 142.358326] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 142.358327] [drm:intel_dump_pipe_config] requested mode: [ 142.358332] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 142.358333] [drm:intel_dump_pipe_config] adjusted mode: [ 142.358337] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 142.358340] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 142.358341] [drm:intel_dump_pipe_config] port clock: 540000 [ 142.358343] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 142.358345] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 142.358347] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 142.358349] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 142.358351] [drm:intel_dump_pipe_config] ips: 0 [ 142.358352] [drm:intel_dump_pipe_config] double wide: 0 [ 142.358354] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 142.358356] [drm:intel_dump_pipe_config] planes on this crtc [ 142.358359] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 142.358362] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 142.358364] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 142.358367] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 142.358369] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 142.358371] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 142.358373] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 142.358377] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625e19800 state to ffffa2a625e1b800 [ 142.358380] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625e1e000 state to ffffa2a625e1b800 [ 142.358381] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 142.358388] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 142.358390] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 142.358392] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 142.358395] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 142.358397] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 142.358401] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 142.358403] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 142.358407] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 142.358423] [drm:drm_atomic_commit] commiting ffffa2a625e1b800 [ 142.359657] [drm:intel_edp_backlight_off.part.30] [ 142.565725] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 142.565764] [drm:intel_disable_pipe] disabling pipe A [ 142.579101] [drm:edp_panel_off] Turn eDP port A panel power off [ 142.579141] [drm:edp_panel_off] Wait for panel power off time [ 142.579218] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000000 [ 142.579812] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 142.579817] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 142.579842] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 142.630050] [drm:wait_panel_status] Wait complete [ 142.630067] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 142.630085] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 142.630089] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 142.630107] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 142.630122] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 142.631654] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 142.631661] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 142.631664] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 142.636724] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 142.636730] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 142.636734] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 142.636740] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 142.636743] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 142.636746] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 142.636763] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 142.636766] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 142.636769] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 142.636772] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 142.636775] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 142.636778] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 142.636780] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 142.636783] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 142.636786] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 142.636790] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 142.636793] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 142.636795] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 142.636804] [drm:intel_power_well_disable] disabling DDI A/E power well [ 142.636808] [drm:skl_set_power_well] Disabling DDI A/E power well [ 142.636812] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 142.636816] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 142.636820] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 142.636828] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1b800 [ 142.636834] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1b800 [ 143.221903] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000 [ 143.221924] [drm:wait_panel_status] Wait complete [ 143.221980] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 143.221995] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 143.271369] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 143.271374] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 143.271377] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 143.430135] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 143.431195] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 144.893768] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ae6000 [ 144.893774] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a626372f00 state to ffffa2a625ae6000 [ 144.893778] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ae7000 state to ffffa2a625ae6000 [ 144.893780] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626372f00 to [NOCRTC] [ 144.893783] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a626372f00 [ 144.893785] [drm:drm_atomic_check_only] checking ffffa2a625ae6000 [ 144.893797] [drm:drm_atomic_commit] commiting ffffa2a625ae6000 [ 144.893807] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ae6000 [ 144.893811] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ae6000 [ 144.893822] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 144.893828] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 144.893831] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ae6000 [ 144.893834] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ae0000 state to ffffa2a625ae6000 [ 144.893837] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a626372540 state to ffffa2a625ae6000 [ 144.893840] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625ae0000 [ 144.893842] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626372540 to [CRTC:26:pipe A] [ 144.893845] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a626372540 [ 144.893848] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae6000 [ 144.893852] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62882f0a0 state to ffffa2a625ae6000 [ 144.893855] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62882f0a0 to [NOCRTC] [ 144.893857] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62882f0a0 to [CRTC:26:pipe A] [ 144.893860] [drm:drm_atomic_check_only] checking ffffa2a625ae6000 [ 144.893864] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 144.893866] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 144.893869] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 144.893871] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 144.893873] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae6000 [ 144.893877] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae6000 [ 144.893880] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 144.893882] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 144.893890] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 144.893895] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 144.893905] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 144.893908] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 144.893911] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 144.893914] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ae0000 for pipe A [ 144.893917] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 144.893919] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 144.893921] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 144.893924] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 144.893927] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 144.893929] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 144.893930] [drm:intel_dump_pipe_config] requested mode: [ 144.893935] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 144.893937] [drm:intel_dump_pipe_config] adjusted mode: [ 144.893941] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 144.893944] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 144.893946] [drm:intel_dump_pipe_config] port clock: 540000 [ 144.893948] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 144.893950] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 144.893952] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 144.893954] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 144.893956] [drm:intel_dump_pipe_config] ips: 0 [ 144.893958] [drm:intel_dump_pipe_config] double wide: 0 [ 144.893960] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 144.893962] [drm:intel_dump_pipe_config] planes on this crtc [ 144.893965] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 144.893968] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 144.893971] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 144.893973] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 144.893975] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 144.893981] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ae2000 state to ffffa2a625ae6000 [ 144.893984] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625ae7800 state to ffffa2a625ae6000 [ 144.893986] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 144.893993] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 144.893995] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 144.893998] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 144.894002] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 144.894005] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 144.894009] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 144.894019] [drm:drm_atomic_commit] commiting ffffa2a625ae6000 [ 144.894031] [drm:intel_power_well_enable] enabling DDI A/E power well [ 144.894036] [drm:skl_set_power_well] Enabling DDI A/E power well [ 144.894042] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 144.898538] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 144.898545] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 144.898549] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 144.898554] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 144.898557] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 144.898560] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 144.898563] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 144.898566] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 144.898569] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 144.898572] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 144.898575] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 144.898578] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 144.898581] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 144.898584] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 144.898587] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 144.898591] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 144.898594] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 144.898608] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 144.898614] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 144.898617] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 144.898632] [drm:edp_panel_on] Turn eDP port A panel power on [ 144.898651] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 144.898728] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 144.898745] [drm:wait_panel_status] Wait complete [ 144.898779] [drm:edp_panel_on] Wait for panel power on [ 144.898854] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 145.100453] [drm:wait_panel_status] Wait complete [ 145.101623] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 145.101626] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 145.101627] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 145.101631] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 145.102304] [drm:intel_dp_start_link_train] clock recovery OK [ 145.102307] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 145.102309] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 145.103284] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 145.103286] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 145.103287] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 145.104251] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 145.104426] [drm:skylake_pfit_enable] for crtc_state = ffffa2a625ae0000 [ 145.104532] [drm:intel_enable_pipe] enabling pipe A [ 145.104542] [drm:intel_edp_backlight_on.part.29] [ 145.104546] [drm:intel_panel_enable_backlight] pipe A [ 145.104631] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 145.104688] [drm:intel_psr_enable] PSR disable by flag [ 145.104690] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 145.121353] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 145.121363] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 145.121382] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 145.121392] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ae6000 [ 145.121397] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ae6000 [ 145.121420] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 145.121425] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625bab800 [ 145.121427] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 145.121437] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 145.138118] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 145.138124] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 145.138151] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 145.138155] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 145.138343] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 145.138348] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6287a6c00 state to ffffa2a625bab800 [ 145.138353] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf000 state to ffffa2a625bab800 [ 145.138356] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6287a6c00 to [CRTC:26:pipe A] [ 145.138359] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6287a6c00 [ 145.138361] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 145.138401] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 145.138404] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 145.138415] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 145.138444] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 145.138447] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 146.744435] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa800 [ 146.744442] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf800 state to ffffa2a625baa800 [ 146.744445] [drm:drm_atomic_check_only] checking ffffa2a625baa800 [ 146.744449] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 146.744452] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 146.744455] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baa800 [ 146.744459] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf7920 state to ffffa2a625baa800 [ 146.744462] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6254ffe40 state to ffffa2a625baa800 [ 146.744465] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6254ffd80 state to ffffa2a625baa800 [ 146.744469] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baa800 [ 146.744472] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 146.744474] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 146.744482] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 146.744487] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 146.744496] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 146.744499] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 146.744502] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 146.744506] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625baf800 for pipe A [ 146.744508] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 146.744510] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 146.744512] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 146.744515] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 146.744518] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 146.744520] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 146.744522] [drm:intel_dump_pipe_config] requested mode: [ 146.744527] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 146.744529] [drm:intel_dump_pipe_config] adjusted mode: [ 146.744533] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 146.744536] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 146.744538] [drm:intel_dump_pipe_config] port clock: 540000 [ 146.744540] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 146.744542] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 146.744544] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 146.744547] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 146.744549] [drm:intel_dump_pipe_config] ips: 0 [ 146.744550] [drm:intel_dump_pipe_config] double wide: 0 [ 146.744553] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 146.744554] [drm:intel_dump_pipe_config] planes on this crtc [ 146.744558] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 146.744561] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 146.744564] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 146.744566] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 146.744569] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 146.744571] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 146.744574] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 146.744579] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ba9000 state to ffffa2a625baa800 [ 146.744582] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625baa000 state to ffffa2a625baa800 [ 146.744584] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 146.744590] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 146.744593] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 146.744595] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 146.744599] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 146.744601] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 146.744606] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 146.744609] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 146.744637] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 146.744655] [drm:drm_atomic_commit] commiting ffffa2a625baa800 [ 146.746687] [drm:intel_edp_backlight_off.part.30] [ 146.949842] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 146.949920] [drm:intel_disable_pipe] disabling pipe A [ 146.956558] [drm:edp_panel_off] Turn eDP port A panel power off [ 146.956599] [drm:edp_panel_off] Wait for panel power off time [ 146.956690] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 146.957272] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 146.957278] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 146.957305] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 147.007551] [drm:wait_panel_status] Wait complete [ 147.007570] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 147.007591] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 147.007594] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 147.007614] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 147.007647] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 147.009066] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 147.009073] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 147.009076] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 147.009972] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 147.009979] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 147.009984] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 147.009990] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 147.009994] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 147.009998] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 147.010001] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 147.010005] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 147.010008] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 147.010011] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 147.010015] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 147.010018] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 147.010021] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 147.010024] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 147.010028] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 147.010033] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 147.010036] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 147.010040] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 147.010050] [drm:intel_power_well_disable] disabling DDI A/E power well [ 147.010055] [drm:skl_set_power_well] Disabling DDI A/E power well [ 147.010060] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 147.010065] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 147.010070] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 147.010080] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa800 [ 147.010087] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa800 [ 147.573800] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000 [ 147.600210] [drm:wait_panel_status] Wait complete [ 147.600269] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 147.600283] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 147.608428] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e6800 [ 147.608433] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6266dbcc0 state to ffffa2a6288e6800 [ 147.608436] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e7000 state to ffffa2a6288e6800 [ 147.608438] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6266dbcc0 to [NOCRTC] [ 147.608440] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a6266dbcc0 [ 147.608442] [drm:drm_atomic_check_only] checking ffffa2a6288e6800 [ 147.608452] [drm:drm_atomic_commit] commiting ffffa2a6288e6800 [ 147.608460] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e6800 [ 147.608463] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e6800 [ 147.608472] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 147.608476] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 147.608479] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e6800 [ 147.608481] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e5000 state to ffffa2a6288e6800 [ 147.608483] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6266dbe40 state to ffffa2a6288e6800 [ 147.608486] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e5000 [ 147.608488] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6266dbe40 to [CRTC:26:pipe A] [ 147.608490] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a6266dbe40 [ 147.608492] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e6800 [ 147.608495] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9f60 state to ffffa2a6288e6800 [ 147.608498] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9f60 to [NOCRTC] [ 147.608500] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9f60 to [CRTC:26:pipe A] [ 147.608502] [drm:drm_atomic_check_only] checking ffffa2a6288e6800 [ 147.608506] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 147.608508] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 147.608510] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 147.608511] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 147.608513] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e6800 [ 147.608516] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e6800 [ 147.608519] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 147.608521] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 147.608527] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 147.608531] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 147.608539] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 147.608542] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 147.608544] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 147.608547] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e5000 for pipe A [ 147.608549] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 147.608550] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 147.608552] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 147.608555] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 147.608557] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 147.608558] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 147.608560] [drm:intel_dump_pipe_config] requested mode: [ 147.608564] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 147.608565] [drm:intel_dump_pipe_config] adjusted mode: [ 147.608568] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 147.608571] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 147.608572] [drm:intel_dump_pipe_config] port clock: 540000 [ 147.608574] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 147.608576] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 147.608578] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 147.608579] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 147.608581] [drm:intel_dump_pipe_config] ips: 0 [ 147.608582] [drm:intel_dump_pipe_config] double wide: 0 [ 147.608584] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 147.608585] [drm:intel_dump_pipe_config] planes on this crtc [ 147.608588] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 147.608590] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 147.608593] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 147.608595] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 147.608597] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 147.608601] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e4800 state to ffffa2a6288e6800 [ 147.608603] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e5800 state to ffffa2a6288e6800 [ 147.608605] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 147.608610] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 147.608612] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 147.608614] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 147.608628] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 147.608630] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 147.608634] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 147.608642] [drm:drm_atomic_commit] commiting ffffa2a6288e6800 [ 147.608651] [drm:intel_power_well_enable] enabling DDI A/E power well [ 147.608655] [drm:skl_set_power_well] Enabling DDI A/E power well [ 147.608660] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 147.615221] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 147.615225] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 147.615228] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 147.615232] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 147.615234] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 147.615237] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 147.615240] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 147.615242] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 147.615245] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 147.615247] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 147.615250] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 147.615252] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 147.615255] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 147.615257] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 147.615260] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 147.615263] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 147.615266] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 147.615269] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 147.615273] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 147.615275] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 147.649338] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 147.649341] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 147.649344] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 147.806296] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 147.806301] [drm:edp_panel_on] Turn eDP port A panel power on [ 147.806321] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 147.806398] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 147.806415] [drm:wait_panel_status] Wait complete [ 147.806449] [drm:edp_panel_on] Wait for panel power on [ 147.806524] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 148.006947] [drm:wait_panel_status] Wait complete [ 148.008808] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 148.008811] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 148.008813] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 148.008816] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 148.009485] [drm:intel_dp_start_link_train] clock recovery OK [ 148.009487] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 148.009489] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 148.010460] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 148.010462] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 148.010463] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 148.011422] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 148.011595] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e5000 [ 148.011703] [drm:intel_enable_pipe] enabling pipe A [ 148.011712] [drm:intel_edp_backlight_on.part.29] [ 148.011716] [drm:intel_panel_enable_backlight] pipe A [ 148.011797] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 148.011853] [drm:intel_psr_enable] PSR disable by flag [ 148.011855] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 148.028521] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 148.028530] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 148.028548] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 148.028557] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e6800 [ 148.028563] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e6800 [ 148.028958] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 148.028960] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 148.028966] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9000 state to ffffa2a625baa000 [ 148.028968] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 148.028978] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 148.045316] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 148.045323] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 148.045350] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 148.045353] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 148.045536] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 148.045541] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6288120c0 state to ffffa2a625baa000 [ 148.045545] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab000 state to ffffa2a625baa000 [ 148.045547] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6288120c0 to [CRTC:26:pipe A] [ 148.045550] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6288120c0 [ 148.045552] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 148.045560] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 148.045563] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 148.045574] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 148.045607] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 148.045610] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 149.145676] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 149.145684] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625bad800 [ 149.145688] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 149.145693] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 149.145696] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 149.145699] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bad800 [ 149.145703] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf78a0 state to ffffa2a625bad800 [ 149.145707] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625a726c0 state to ffffa2a625bad800 [ 149.145710] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625a72780 state to ffffa2a625bad800 [ 149.145713] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bad800 [ 149.145716] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 149.145718] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 149.145727] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 149.145732] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 149.145741] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 149.145744] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 149.145747] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 149.145751] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ba9800 for pipe A [ 149.145753] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 149.145755] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 149.145758] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 149.145761] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 149.145763] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 149.145765] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 149.145767] [drm:intel_dump_pipe_config] requested mode: [ 149.145772] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 149.145774] [drm:intel_dump_pipe_config] adjusted mode: [ 149.145778] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 149.145781] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 149.145783] [drm:intel_dump_pipe_config] port clock: 540000 [ 149.145785] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 149.145787] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 149.145790] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 149.145792] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 149.145794] [drm:intel_dump_pipe_config] ips: 0 [ 149.145796] [drm:intel_dump_pipe_config] double wide: 0 [ 149.145798] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 149.145799] [drm:intel_dump_pipe_config] planes on this crtc [ 149.145803] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 149.145806] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 149.145809] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 149.145812] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 149.145814] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 149.145817] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 149.145819] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 149.145825] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ba9000 state to ffffa2a625bad800 [ 149.145828] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625baf800 state to ffffa2a625bad800 [ 149.145830] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 149.145838] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 149.145840] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 149.145843] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 149.145846] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 149.145848] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 149.145853] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 149.145856] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 149.145860] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 149.145869] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 149.147706] [drm:intel_edp_backlight_off.part.30] [ 149.349863] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 149.349921] [drm:intel_disable_pipe] disabling pipe A [ 149.362930] [drm:edp_panel_off] Turn eDP port A panel power off [ 149.362970] [drm:edp_panel_off] Wait for panel power off time [ 149.363048] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 149.363603] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 149.363609] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 149.363633] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 149.413655] [drm:wait_panel_status] Wait complete [ 149.413673] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 149.413694] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 149.413697] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 149.413717] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 149.413734] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 149.415440] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 149.415446] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 149.415450] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 149.420493] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 149.420500] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 149.420505] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 149.420511] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 149.420515] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 149.420518] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 149.420522] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 149.420525] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 149.420529] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 149.420532] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 149.420535] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 149.420539] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 149.420542] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 149.420545] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 149.420549] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 149.420553] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 149.420557] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 149.420560] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 149.420571] [drm:intel_power_well_disable] disabling DDI A/E power well [ 149.420576] [drm:skl_set_power_well] Disabling DDI A/E power well [ 149.420581] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 149.420586] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 149.420591] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 149.420601] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 149.420608] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 150.005929] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000 [ 150.008185] [drm:wait_panel_status] Wait complete [ 150.008248] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 150.008261] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 150.057550] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 150.057555] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 150.057558] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 150.214313] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 150.215402] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 153.269998] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off [ 153.270060] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000000 [ 153.270065] [drm:intel_power_well_disable] disabling DC off [ 153.270071] [drm:skl_enable_dc6] Enabling DC6 [ 153.270074] [drm:gen9_set_dc_state] Setting DC state from 00 to 02 [ 153.270459] [drm:intel_power_well_disable] disabling always-on [ 153.273325] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 153.273331] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 153.273335] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 153.273361] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 157.417354] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e0800 [ 157.417360] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6288123c0 state to ffffa2a6288e0800 [ 157.417365] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e2800 state to ffffa2a6288e0800 [ 157.417367] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6288123c0 to [NOCRTC] [ 157.417370] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a6288123c0 [ 157.417373] [drm:drm_atomic_check_only] checking ffffa2a6288e0800 [ 157.417383] [drm:drm_atomic_commit] commiting ffffa2a6288e0800 [ 157.417393] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e0800 [ 157.417397] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e0800 [ 157.417646] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 157.417652] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 157.417655] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e0800 [ 157.417658] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e6000 state to ffffa2a6288e0800 [ 157.417660] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a628812300 state to ffffa2a6288e0800 [ 157.417664] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e6000 [ 157.417666] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628812300 to [CRTC:26:pipe A] [ 157.417668] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a628812300 [ 157.417671] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e0800 [ 157.417675] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b98c0 state to ffffa2a6288e0800 [ 157.417678] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b98c0 to [NOCRTC] [ 157.417681] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b98c0 to [CRTC:26:pipe A] [ 157.417683] [drm:drm_atomic_check_only] checking ffffa2a6288e0800 [ 157.417688] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 157.417691] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 157.417702] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 157.417705] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 157.417708] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e0800 [ 157.417711] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e0800 [ 157.417715] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 157.417717] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 157.417724] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 157.417729] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 157.417738] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 157.417742] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 157.417744] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 157.417748] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e6000 for pipe A [ 157.417750] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 157.417752] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 157.417755] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 157.417758] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 157.417760] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 157.417762] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 157.417764] [drm:intel_dump_pipe_config] requested mode: [ 157.417769] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 157.417771] [drm:intel_dump_pipe_config] adjusted mode: [ 157.417775] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 157.417778] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 157.417780] [drm:intel_dump_pipe_config] port clock: 540000 [ 157.417782] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 157.417784] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 157.417787] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 157.417789] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 157.417791] [drm:intel_dump_pipe_config] ips: 0 [ 157.417792] [drm:intel_dump_pipe_config] double wide: 0 [ 157.417795] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 157.417796] [drm:intel_dump_pipe_config] planes on this crtc [ 157.417799] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 157.417803] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 157.417806] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 157.417808] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 157.417810] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 157.417815] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e1800 state to ffffa2a6288e0800 [ 157.417818] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e7800 state to ffffa2a6288e0800 [ 157.417820] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 157.417827] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 157.417829] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 157.417832] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 157.417836] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 157.417839] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 157.417843] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 157.417854] [drm:drm_atomic_commit] commiting ffffa2a6288e0800 [ 157.417862] [drm:intel_power_well_enable] enabling always-on [ 157.417865] [drm:intel_power_well_enable] enabling DC off [ 157.418122] [drm:gen9_set_dc_state] Setting DC state from 02 to 00 [ 157.418131] [drm:intel_power_well_enable] enabling DDI A/E power well [ 157.418135] [drm:skl_set_power_well] Enabling DDI A/E power well [ 157.418142] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 157.419812] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 157.419817] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 157.419820] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 157.419825] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 157.419828] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 157.419831] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 157.419834] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 157.419838] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 157.419841] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 157.419844] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 157.419847] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 157.419850] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 157.419853] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 157.419855] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 157.419858] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 157.419863] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 157.419866] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 157.419869] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 157.419875] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 157.419877] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 157.419892] [drm:edp_panel_on] Turn eDP port A panel power on [ 157.419911] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 157.419988] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 157.420006] [drm:wait_panel_status] Wait complete [ 157.420040] [drm:edp_panel_on] Wait for panel power on [ 157.420116] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 00000003 [ 157.469429] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 157.469435] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 157.469438] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 157.469465] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 157.620547] [drm:wait_panel_status] Wait complete [ 157.620581] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 157.620652] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b [ 157.621782] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 157.621785] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 157.621786] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 157.621789] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 157.622460] [drm:intel_dp_start_link_train] clock recovery OK [ 157.622463] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 157.622464] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 157.623436] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 157.623438] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 157.623439] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 157.624400] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 157.624573] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e6000 [ 157.624662] [drm:intel_enable_pipe] enabling pipe A [ 157.624678] [drm:intel_edp_backlight_on.part.29] [ 157.624680] [drm:intel_panel_enable_backlight] pipe A [ 157.624760] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 157.624814] [drm:intel_psr_enable] PSR disable by flag [ 157.624815] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 157.641466] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 157.641473] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 157.641487] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 157.641494] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e0800 [ 157.641499] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e0800 [ 157.641524] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 157.641526] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9000 state to ffffa2a625baf800 [ 157.641527] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 157.641533] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 157.658217] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 157.658220] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 157.658247] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 157.658249] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 157.658386] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 157.658389] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625d8e900 state to ffffa2a625baf800 [ 157.658391] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab800 state to ffffa2a625baf800 [ 157.658393] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625d8e900 to [CRTC:26:pipe A] [ 157.658394] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625d8e900 [ 157.658395] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 157.658402] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 157.658403] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 157.658411] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 157.658435] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 157.658437] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 157.785113] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ae0800 [ 157.785118] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ae4800 state to ffffa2a625ae0800 [ 157.785120] [drm:drm_atomic_check_only] checking ffffa2a625ae0800 [ 157.785123] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 157.785125] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 157.785127] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae0800 [ 157.785129] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62882f460 state to ffffa2a625ae0800 [ 157.785131] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625f14000 state to ffffa2a625ae0800 [ 157.785133] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625f14cc0 state to ffffa2a625ae0800 [ 157.785135] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae0800 [ 157.785138] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 157.785139] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 157.785145] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 157.785148] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 157.785154] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 157.785156] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 157.785158] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 157.785160] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ae4800 for pipe A [ 157.785162] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 157.785163] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 157.785165] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 157.785167] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 157.785168] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 157.785170] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 157.785171] [drm:intel_dump_pipe_config] requested mode: [ 157.785174] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 157.785176] [drm:intel_dump_pipe_config] adjusted mode: [ 157.785178] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 157.785180] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 157.785181] [drm:intel_dump_pipe_config] port clock: 540000 [ 157.785183] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 157.785184] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 157.785186] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 157.785187] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 157.785189] [drm:intel_dump_pipe_config] ips: 0 [ 157.785190] [drm:intel_dump_pipe_config] double wide: 0 [ 157.785191] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 157.785192] [drm:intel_dump_pipe_config] planes on this crtc [ 157.785194] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 157.785196] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 157.785198] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 157.785200] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 157.785202] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 157.785203] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 157.785205] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 157.785208] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ae3800 state to ffffa2a625ae0800 [ 157.785210] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625ae4000 state to ffffa2a625ae0800 [ 157.785212] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 157.785216] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 157.785218] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 157.785220] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 157.785222] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 157.785223] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 157.785226] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 157.785228] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 157.785231] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 157.785237] [drm:drm_atomic_commit] commiting ffffa2a625ae0800 [ 157.786777] [drm:intel_edp_backlight_off.part.30] [ 157.989858] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 157.989946] [drm:intel_disable_pipe] disabling pipe A [ 157.992370] [drm:edp_panel_off] Turn eDP port A panel power off [ 157.992409] [drm:edp_panel_off] Wait for panel power off time [ 157.992486] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 157.992985] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 157.992989] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 157.993005] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 158.043031] [drm:wait_panel_status] Wait complete [ 158.043047] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 158.043066] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 158.043069] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 158.043086] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 158.043101] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 158.044813] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 158.044818] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 158.044821] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 158.045286] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 158.045292] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 158.045296] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 158.045302] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 158.045305] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 158.045308] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 158.045311] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 158.045314] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 158.045317] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 158.045320] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 158.045323] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 158.045326] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 158.045329] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 158.045332] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 158.045335] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 158.045339] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 158.045342] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 158.045345] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 158.045354] [drm:intel_power_well_disable] disabling DDI A/E power well [ 158.045359] [drm:skl_set_power_well] Disabling DDI A/E power well [ 158.045363] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 158.045368] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 158.045372] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 158.045381] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ae0800 [ 158.045387] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ae0800 [ 158.646002] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 158.646038] [drm:wait_panel_status] Wait complete [ 158.646100] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 158.646113] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 158.695414] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 158.695420] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 158.695423] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 158.854397] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 158.855493] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 160.050156] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e6800 [ 160.050162] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6287a6e40 state to ffffa2a6288e6800 [ 160.050167] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e5000 state to ffffa2a6288e6800 [ 160.050169] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6287a6e40 to [NOCRTC] [ 160.050172] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a6287a6e40 [ 160.050174] [drm:drm_atomic_check_only] checking ffffa2a6288e6800 [ 160.050185] [drm:drm_atomic_commit] commiting ffffa2a6288e6800 [ 160.050195] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e6800 [ 160.050199] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e6800 [ 160.050210] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 160.050215] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 160.050218] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e6800 [ 160.050221] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e4800 state to ffffa2a6288e6800 [ 160.050224] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6287a6f00 state to ffffa2a6288e6800 [ 160.050228] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e4800 [ 160.050230] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6287a6f00 to [CRTC:26:pipe A] [ 160.050232] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a6287a6f00 [ 160.050235] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e6800 [ 160.050239] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9740 state to ffffa2a6288e6800 [ 160.050242] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9740 to [NOCRTC] [ 160.050245] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9740 to [CRTC:26:pipe A] [ 160.050247] [drm:drm_atomic_check_only] checking ffffa2a6288e6800 [ 160.050252] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 160.050254] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 160.050256] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 160.050258] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 160.050261] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e6800 [ 160.050265] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e6800 [ 160.050268] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 160.050270] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 160.050277] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 160.050283] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 160.050292] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 160.050295] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 160.050298] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 160.050301] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e4800 for pipe A [ 160.050303] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 160.050305] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 160.050308] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 160.050311] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 160.050313] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 160.050315] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 160.050317] [drm:intel_dump_pipe_config] requested mode: [ 160.050322] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 160.050324] [drm:intel_dump_pipe_config] adjusted mode: [ 160.050328] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 160.050331] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 160.050333] [drm:intel_dump_pipe_config] port clock: 540000 [ 160.050335] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 160.050337] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 160.050339] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 160.050342] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 160.050343] [drm:intel_dump_pipe_config] ips: 0 [ 160.050345] [drm:intel_dump_pipe_config] double wide: 0 [ 160.050347] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 160.050349] [drm:intel_dump_pipe_config] planes on this crtc [ 160.050353] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 160.050356] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 160.050359] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 160.050361] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 160.050363] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 160.050368] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e0000 state to ffffa2a6288e6800 [ 160.050371] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e1000 state to ffffa2a6288e6800 [ 160.050373] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 160.050380] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 160.050382] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 160.050385] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 160.050389] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 160.050392] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 160.050396] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 160.050406] [drm:drm_atomic_commit] commiting ffffa2a6288e6800 [ 160.050417] [drm:intel_power_well_enable] enabling DDI A/E power well [ 160.050422] [drm:skl_set_power_well] Enabling DDI A/E power well [ 160.050428] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 160.053809] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 160.053813] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 160.053817] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 160.053822] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 160.053825] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 160.053827] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 160.053830] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 160.053833] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 160.053836] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 160.053839] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 160.053875] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 160.053878] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 160.053880] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 160.053883] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 160.053886] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 160.053890] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 160.053893] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 160.053896] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 160.053901] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 160.053903] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 160.053919] [drm:edp_panel_on] Turn eDP port A panel power on [ 160.053938] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 160.054015] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 160.054033] [drm:wait_panel_status] Wait complete [ 160.054067] [drm:edp_panel_on] Wait for panel power on [ 160.054142] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 160.256034] [drm:wait_panel_status] Wait complete [ 160.257171] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 160.257173] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 160.257174] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 160.257177] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 160.257844] [drm:intel_dp_start_link_train] clock recovery OK [ 160.257847] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 160.257848] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 160.258818] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 160.258819] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 160.258821] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 160.259779] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 160.259951] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e4800 [ 160.260046] [drm:intel_enable_pipe] enabling pipe A [ 160.260055] [drm:intel_edp_backlight_on.part.29] [ 160.260058] [drm:intel_panel_enable_backlight] pipe A [ 160.260139] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 160.260195] [drm:intel_psr_enable] PSR disable by flag [ 160.260196] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 160.276998] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 160.277008] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 160.277027] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 160.277035] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e6800 [ 160.277041] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e6800 [ 160.277072] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 160.277076] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf000 state to ffffa2a625baf800 [ 160.277078] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 160.277087] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 160.293660] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 160.293665] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 160.293700] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 160.293702] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 160.293855] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 160.293859] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6266dbe40 state to ffffa2a625baf800 [ 160.293863] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625baf800 [ 160.293865] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6266dbe40 to [CRTC:26:pipe A] [ 160.293867] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6266dbe40 [ 160.293870] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 160.293877] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 160.293879] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 160.293890] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 160.293920] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 160.293923] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 160.417830] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e1e000 [ 160.417834] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e19800 state to ffffa2a625e1e000 [ 160.417836] [drm:drm_atomic_check_only] checking ffffa2a625e1e000 [ 160.417839] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 160.417840] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 160.417841] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1e000 [ 160.417843] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba6a00 state to ffffa2a625e1e000 [ 160.417845] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a626360180 state to ffffa2a625e1e000 [ 160.417847] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263603c0 state to ffffa2a625e1e000 [ 160.417848] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e1e000 [ 160.417850] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 160.417851] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 160.417856] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 160.417859] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 160.417864] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 160.417865] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 160.417867] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 160.417869] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625e19800 for pipe A [ 160.417870] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 160.417871] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 160.417872] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 160.417873] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 160.417875] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 160.417876] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 160.417876] [drm:intel_dump_pipe_config] requested mode: [ 160.417879] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 160.417880] [drm:intel_dump_pipe_config] adjusted mode: [ 160.417881] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 160.417883] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 160.417884] [drm:intel_dump_pipe_config] port clock: 540000 [ 160.417885] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 160.417886] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 160.417887] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 160.417888] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 160.417889] [drm:intel_dump_pipe_config] ips: 0 [ 160.417889] [drm:intel_dump_pipe_config] double wide: 0 [ 160.417890] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 160.417891] [drm:intel_dump_pipe_config] planes on this crtc [ 160.417893] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 160.417894] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 160.417896] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 160.417897] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 160.417898] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 160.417899] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 160.417900] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 160.417903] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625e1d800 state to ffffa2a625e1e000 [ 160.417905] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625e1d000 state to ffffa2a625e1e000 [ 160.417906] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 160.417911] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 160.417912] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 160.417913] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 160.417914] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 160.417915] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 160.417918] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 160.417920] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 160.417921] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 160.417926] [drm:drm_atomic_commit] commiting ffffa2a625e1e000 [ 160.419818] [drm:intel_edp_backlight_off.part.30] [ 160.621873] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 160.621929] [drm:intel_disable_pipe] disabling pipe A [ 160.628588] [drm:edp_panel_off] Turn eDP port A panel power off [ 160.628627] [drm:edp_panel_off] Wait for panel power off time [ 160.628704] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 160.629281] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 160.629286] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 160.629311] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 160.679388] [drm:wait_panel_status] Wait complete [ 160.679403] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 160.679408] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 160.679427] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 160.679472] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 160.679490] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 160.681052] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 160.681057] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 160.681060] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 160.681776] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 160.681782] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 160.681786] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 160.681792] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 160.681795] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 160.681797] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 160.681800] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 160.681803] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 160.681806] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 160.681808] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 160.681811] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 160.681814] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 160.681816] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 160.681819] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 160.681822] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 160.681826] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 160.681829] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 160.681831] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 160.681839] [drm:intel_power_well_disable] disabling DDI A/E power well [ 160.681843] [drm:skl_set_power_well] Disabling DDI A/E power well [ 160.681847] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 160.681851] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 160.681855] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 160.681863] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e1e000 [ 160.681869] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e1e000 [ 161.269987] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 161.270007] [drm:wait_panel_status] Wait complete [ 161.270063] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 161.270077] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 161.319485] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 161.319491] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 161.319494] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 161.478371] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 161.479477] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 162.685779] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e18800 [ 162.685786] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625f2f0c0 state to ffffa2a625e18800 [ 162.685790] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e1b000 state to ffffa2a625e18800 [ 162.685793] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625f2f0c0 to [NOCRTC] [ 162.685795] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a625f2f0c0 [ 162.685798] [drm:drm_atomic_check_only] checking ffffa2a625e18800 [ 162.685809] [drm:drm_atomic_commit] commiting ffffa2a625e18800 [ 162.685818] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e18800 [ 162.685822] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e18800 [ 162.685833] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 162.685838] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 162.685841] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625e18800 [ 162.685844] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625e19800 state to ffffa2a625e18800 [ 162.685847] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625f2f540 state to ffffa2a625e18800 [ 162.685850] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625e19800 [ 162.685853] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625f2f540 to [CRTC:26:pipe A] [ 162.685855] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a625f2f540 [ 162.685858] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e18800 [ 162.685862] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba6fe0 state to ffffa2a625e18800 [ 162.685865] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a628ba6fe0 to [NOCRTC] [ 162.685868] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a628ba6fe0 to [CRTC:26:pipe A] [ 162.685870] [drm:drm_atomic_check_only] checking ffffa2a625e18800 [ 162.685874] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 162.685877] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 162.685879] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 162.685882] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 162.685884] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e18800 [ 162.685888] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625e18800 [ 162.685891] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 162.685893] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 162.685900] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 162.685905] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 162.685913] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 162.685917] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 162.685920] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 162.685924] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625e19800 for pipe A [ 162.685926] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 162.685928] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 162.685931] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 162.685934] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 162.685937] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 162.685939] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 162.685940] [drm:intel_dump_pipe_config] requested mode: [ 162.685945] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 162.685947] [drm:intel_dump_pipe_config] adjusted mode: [ 162.685951] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 162.685954] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 162.685956] [drm:intel_dump_pipe_config] port clock: 540000 [ 162.685958] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 162.685960] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 162.685963] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 162.685965] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 162.685967] [drm:intel_dump_pipe_config] ips: 0 [ 162.685968] [drm:intel_dump_pipe_config] double wide: 0 [ 162.685970] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 162.685972] [drm:intel_dump_pipe_config] planes on this crtc [ 162.685975] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 162.685979] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 162.685982] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 162.685984] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 162.685986] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 162.685991] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625e1e000 state to ffffa2a625e18800 [ 162.685995] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a62855f800 state to ffffa2a625e18800 [ 162.685997] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 162.686003] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 162.686006] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 162.686009] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 162.686013] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 162.686016] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 162.686020] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 162.686030] [drm:drm_atomic_commit] commiting ffffa2a625e18800 [ 162.686041] [drm:intel_power_well_enable] enabling DDI A/E power well [ 162.686046] [drm:skl_set_power_well] Enabling DDI A/E power well [ 162.686052] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 162.687772] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 162.687776] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 162.687779] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 162.687783] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 162.687786] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 162.687789] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 162.687792] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 162.687795] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 162.687798] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 162.687800] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 162.687803] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 162.687806] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 162.687809] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 162.687812] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 162.687815] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 162.687819] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 162.687822] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 162.687825] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 162.687830] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 162.687832] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 162.687845] [drm:edp_panel_on] Turn eDP port A panel power on [ 162.687864] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 162.687941] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 162.687959] [drm:wait_panel_status] Wait complete [ 162.687992] [drm:edp_panel_on] Wait for panel power on [ 162.688068] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 162.889152] [drm:wait_panel_status] Wait complete [ 162.890305] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 162.890307] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 162.890309] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 162.890312] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 162.890996] [drm:intel_dp_start_link_train] clock recovery OK [ 162.890998] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 162.891000] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 162.891986] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 162.891988] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 162.891989] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 162.892961] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 162.893137] [drm:skylake_pfit_enable] for crtc_state = ffffa2a625e19800 [ 162.893235] [drm:intel_enable_pipe] enabling pipe A [ 162.893245] [drm:intel_edp_backlight_on.part.29] [ 162.893249] [drm:intel_panel_enable_backlight] pipe A [ 162.893330] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 162.893385] [drm:intel_psr_enable] PSR disable by flag [ 162.893387] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 162.910193] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 162.910205] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 162.910225] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 162.910235] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625e18800 [ 162.910241] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625e18800 [ 162.910273] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 162.910277] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf000 state to ffffa2a625baf800 [ 162.910279] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 162.910289] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 162.926854] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 162.926860] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 162.926896] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 162.926899] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 162.927044] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 162.927049] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628812cc0 state to ffffa2a625baf800 [ 162.927052] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625baf800 [ 162.927055] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628812cc0 to [CRTC:26:pipe A] [ 162.927057] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a628812cc0 [ 162.927059] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 162.927067] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 162.927070] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 162.927081] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 162.927112] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 162.927130] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 163.051988] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf000 [ 163.051992] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab800 state to ffffa2a625baf000 [ 163.051994] [drm:drm_atomic_check_only] checking ffffa2a625baf000 [ 163.051998] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 163.051999] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 163.052001] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baf000 [ 163.052003] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf7520 state to ffffa2a625baf000 [ 163.052005] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a626be0840 state to ffffa2a625baf000 [ 163.052007] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a626be0300 state to ffffa2a625baf000 [ 163.052009] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baf000 [ 163.052011] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 163.052012] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 163.052018] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 163.052021] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 163.052026] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 163.052028] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 163.052030] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 163.052033] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625bab800 for pipe A [ 163.052039] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 163.052040] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 163.052042] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 163.052043] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 163.052045] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 163.052046] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 163.052047] [drm:intel_dump_pipe_config] requested mode: [ 163.052051] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 163.052054] [drm:intel_dump_pipe_config] adjusted mode: [ 163.052058] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 163.052060] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 163.052061] [drm:intel_dump_pipe_config] port clock: 540000 [ 163.052062] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 163.052064] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 163.052065] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 163.052067] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 163.052068] [drm:intel_dump_pipe_config] ips: 0 [ 163.052069] [drm:intel_dump_pipe_config] double wide: 0 [ 163.052070] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 163.052071] [drm:intel_dump_pipe_config] planes on this crtc [ 163.052076] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 163.052077] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 163.052079] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 163.052081] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 163.052082] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 163.052084] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 163.052085] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 163.052089] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ba9000 state to ffffa2a625baf000 [ 163.052090] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625ba9800 state to ffffa2a625baf000 [ 163.052091] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 163.052097] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 163.052098] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 163.052100] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 163.052101] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 163.052103] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 163.052106] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 163.052107] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 163.052110] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 163.052115] [drm:drm_atomic_commit] commiting ffffa2a625baf000 [ 163.053818] [drm:intel_edp_backlight_off.part.30] [ 163.261885] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 163.261960] [drm:intel_disable_pipe] disabling pipe A [ 163.277242] [drm:edp_panel_off] Turn eDP port A panel power off [ 163.277283] [drm:edp_panel_off] Wait for panel power off time [ 163.277360] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 163.277959] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 163.277965] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 163.277989] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 163.328138] [drm:wait_panel_status] Wait complete [ 163.328154] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 163.328174] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 163.328177] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 163.328194] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 163.328210] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 163.329764] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 163.329769] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 163.329773] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 163.332714] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 163.332720] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 163.332724] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 163.332730] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 163.332733] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 163.332736] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 163.332750] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 163.332753] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 163.332756] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 163.332759] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 163.332762] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 163.332765] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 163.332768] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 163.332771] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 163.332774] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 163.332778] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 163.332781] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 163.332784] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 163.332794] [drm:intel_power_well_disable] disabling DDI A/E power well [ 163.332798] [drm:skl_set_power_well] Disabling DDI A/E power well [ 163.332803] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 163.332807] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 163.332811] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 163.332821] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf000 [ 163.332827] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf000 [ 163.894030] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 163.894051] [drm:wait_panel_status] Wait complete [ 163.894106] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 163.894120] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 163.943421] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 163.943426] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 163.943429] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 164.102439] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 164.103535] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 165.337090] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e6000 [ 165.337097] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a629416840 state to ffffa2a6288e6000 [ 165.337101] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e0800 state to ffffa2a6288e6000 [ 165.337103] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a629416840 to [NOCRTC] [ 165.337106] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a629416840 [ 165.337108] [drm:drm_atomic_check_only] checking ffffa2a6288e6000 [ 165.337119] [drm:drm_atomic_commit] commiting ffffa2a6288e6000 [ 165.337129] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e6000 [ 165.337133] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e6000 [ 165.337142] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 165.337148] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 165.337151] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e6000 [ 165.337154] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e2800 state to ffffa2a6288e6000 [ 165.337156] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a629416900 state to ffffa2a6288e6000 [ 165.337160] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e2800 [ 165.337162] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a629416900 to [CRTC:26:pipe A] [ 165.337165] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a629416900 [ 165.337167] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e6000 [ 165.337171] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9e20 state to ffffa2a6288e6000 [ 165.337174] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9e20 to [NOCRTC] [ 165.337177] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9e20 to [CRTC:26:pipe A] [ 165.337179] [drm:drm_atomic_check_only] checking ffffa2a6288e6000 [ 165.337184] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 165.337187] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 165.337189] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 165.337191] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 165.337194] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e6000 [ 165.337197] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e6000 [ 165.337200] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 165.337202] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 165.337210] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 165.337215] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 165.337224] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 165.337227] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 165.337230] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 165.337234] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e2800 for pipe A [ 165.337236] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 165.337238] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 165.337241] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 165.337243] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 165.337246] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 165.337248] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 165.337250] [drm:intel_dump_pipe_config] requested mode: [ 165.337254] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 165.337256] [drm:intel_dump_pipe_config] adjusted mode: [ 165.337260] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 165.337263] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 165.337265] [drm:intel_dump_pipe_config] port clock: 540000 [ 165.337267] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 165.337269] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 165.337272] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 165.337274] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 165.337276] [drm:intel_dump_pipe_config] ips: 0 [ 165.337278] [drm:intel_dump_pipe_config] double wide: 0 [ 165.337280] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 165.337281] [drm:intel_dump_pipe_config] planes on this crtc [ 165.337285] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 165.337288] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 165.337291] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 165.337294] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 165.337296] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 165.337301] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e7800 state to ffffa2a6288e6000 [ 165.337304] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e5000 state to ffffa2a6288e6000 [ 165.337306] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 165.337312] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 165.337315] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 165.337317] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 165.337321] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 165.337324] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 165.337328] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 165.337339] [drm:drm_atomic_commit] commiting ffffa2a6288e6000 [ 165.337351] [drm:intel_power_well_enable] enabling DDI A/E power well [ 165.337356] [drm:skl_set_power_well] Enabling DDI A/E power well [ 165.337362] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 165.338795] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 165.338799] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 165.338802] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 165.338806] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 165.338809] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 165.338812] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 165.338815] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 165.338818] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 165.338820] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 165.338823] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 165.338826] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 165.338829] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 165.338831] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 165.338834] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 165.338837] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 165.338841] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 165.338844] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 165.338847] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 165.338852] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 165.338854] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 165.338867] [drm:edp_panel_on] Turn eDP port A panel power on [ 165.338886] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 165.338963] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 165.338980] [drm:wait_panel_status] Wait complete [ 165.339014] [drm:edp_panel_on] Wait for panel power on [ 165.339089] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 165.540602] [drm:wait_panel_status] Wait complete [ 165.541745] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 165.541748] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 165.541749] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 165.541752] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 165.542425] [drm:intel_dp_start_link_train] clock recovery OK [ 165.542428] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 165.542430] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 165.543402] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 165.543403] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 165.543405] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 165.544378] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 165.544544] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e2800 [ 165.544617] [drm:intel_enable_pipe] enabling pipe A [ 165.544623] [drm:intel_edp_backlight_on.part.29] [ 165.544625] [drm:intel_panel_enable_backlight] pipe A [ 165.544679] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 165.544719] [drm:intel_psr_enable] PSR disable by flag [ 165.544719] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 165.561570] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 165.561576] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 165.561590] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 165.561596] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e6000 [ 165.561600] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e6000 [ 165.561624] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ba9800 [ 165.561627] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9000 state to ffffa2a625ba9800 [ 165.561628] [drm:drm_atomic_check_only] checking ffffa2a625ba9800 [ 165.561635] [drm:drm_atomic_commit] commiting ffffa2a625ba9800 [ 165.578231] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ba9800 [ 165.578236] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ba9800 [ 165.578264] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 165.578265] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 165.578386] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ba9800 [ 165.578390] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6263abcc0 state to ffffa2a625ba9800 [ 165.578392] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa800 state to ffffa2a625ba9800 [ 165.578393] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6263abcc0 to [CRTC:26:pipe A] [ 165.578394] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6263abcc0 [ 165.578396] [drm:drm_atomic_check_only] checking ffffa2a625ba9800 [ 165.578401] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 165.578403] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 165.578410] [drm:drm_atomic_commit] commiting ffffa2a625ba9800 [ 165.578436] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ba9800 [ 165.578439] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ba9800 [ 165.702337] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ba9000 [ 165.702342] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625ba9000 [ 165.702344] [drm:drm_atomic_check_only] checking ffffa2a625ba9000 [ 165.702347] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 165.702349] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 165.702351] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ba9000 [ 165.702354] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf72e0 state to ffffa2a625ba9000 [ 165.702356] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a626385480 state to ffffa2a625ba9000 [ 165.702358] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a626385d80 state to ffffa2a625ba9000 [ 165.702360] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ba9000 [ 165.702362] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 165.702363] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 165.702368] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 165.702372] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 165.702377] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 165.702379] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 165.702381] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 165.702383] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625bac800 for pipe A [ 165.702385] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 165.702386] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 165.702387] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 165.702389] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 165.702390] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 165.702392] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 165.702393] [drm:intel_dump_pipe_config] requested mode: [ 165.702396] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 165.702397] [drm:intel_dump_pipe_config] adjusted mode: [ 165.702399] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 165.702401] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 165.702402] [drm:intel_dump_pipe_config] port clock: 540000 [ 165.702403] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 165.702404] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 165.702406] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 165.702407] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 165.702408] [drm:intel_dump_pipe_config] ips: 0 [ 165.702409] [drm:intel_dump_pipe_config] double wide: 0 [ 165.702410] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 165.702411] [drm:intel_dump_pipe_config] planes on this crtc [ 165.702413] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 165.702415] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 165.702417] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 165.702418] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 165.702420] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 165.702421] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 165.702423] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 165.702426] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625bae000 state to ffffa2a625ba9000 [ 165.702428] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625baa000 state to ffffa2a625ba9000 [ 165.702429] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 165.702434] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 165.702435] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 165.702437] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 165.702439] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 165.702440] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 165.702443] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 165.702445] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 165.702448] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 165.702454] [drm:drm_atomic_commit] commiting ffffa2a625ba9000 [ 165.703916] [drm:intel_edp_backlight_off.part.30] [ 165.909926] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 165.910014] [drm:intel_disable_pipe] disabling pipe A [ 165.912426] [drm:edp_panel_off] Turn eDP port A panel power off [ 165.912466] [drm:edp_panel_off] Wait for panel power off time [ 165.912543] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 165.913145] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 165.913150] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 165.913174] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 165.963084] [drm:wait_panel_status] Wait complete [ 165.963100] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 165.963111] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 165.963114] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 165.963124] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 165.963140] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 165.965369] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 165.965376] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 165.965379] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 165.969785] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled [ 165.969796] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 165.969801] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 165.969805] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 165.969810] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 165.969813] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 165.969816] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 165.969818] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 165.969821] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 165.969824] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 165.969827] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 165.969829] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 165.969832] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 165.969835] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 165.969837] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 165.969840] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 165.969844] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 165.969847] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 165.969850] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 165.969858] [drm:intel_power_well_disable] disabling DDI A/E power well [ 165.969862] [drm:skl_set_power_well] Disabling DDI A/E power well [ 165.969867] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 165.969871] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 165.969874] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 165.969883] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ba9000 [ 165.969889] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ba9000 [ 166.518057] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000 [ 166.540141] [drm:wait_panel_status] Wait complete [ 166.540203] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 166.540221] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 166.589315] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 166.589321] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 166.589324] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 166.742460] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 166.743555] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 167.974432] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ae2800 [ 167.974439] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a628bb8480 state to ffffa2a625ae2800 [ 167.974443] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ae3000 state to ffffa2a625ae2800 [ 167.974446] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628bb8480 to [NOCRTC] [ 167.974449] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a628bb8480 [ 167.974451] [drm:drm_atomic_check_only] checking ffffa2a625ae2800 [ 167.974462] [drm:drm_atomic_commit] commiting ffffa2a625ae2800 [ 167.974472] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ae2800 [ 167.974476] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ae2800 [ 167.974486] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 167.974491] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 167.974494] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ae2800 [ 167.974497] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ae1000 state to ffffa2a625ae2800 [ 167.974500] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a628bb8d80 state to ffffa2a625ae2800 [ 167.974504] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625ae1000 [ 167.974507] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a628bb8d80 to [CRTC:26:pipe A] [ 167.974509] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a628bb8d80 [ 167.974512] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae2800 [ 167.974515] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62882f520 state to ffffa2a625ae2800 [ 167.974518] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62882f520 to [NOCRTC] [ 167.974521] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62882f520 to [CRTC:26:pipe A] [ 167.974523] [drm:drm_atomic_check_only] checking ffffa2a625ae2800 [ 167.974528] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 167.974531] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 167.974533] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 167.974535] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 167.974538] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae2800 [ 167.974542] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae2800 [ 167.974545] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 167.974547] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 167.974555] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 167.974560] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 167.974569] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 167.974572] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 167.974575] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 167.974578] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ae1000 for pipe A [ 167.974581] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 167.974583] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 167.974585] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 167.974588] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 167.974591] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 167.974593] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 167.974595] [drm:intel_dump_pipe_config] requested mode: [ 167.974599] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 167.974601] [drm:intel_dump_pipe_config] adjusted mode: [ 167.974605] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 167.974608] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 167.974610] [drm:intel_dump_pipe_config] port clock: 540000 [ 167.974612] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 167.974614] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 167.974617] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 167.974619] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 167.974621] [drm:intel_dump_pipe_config] ips: 0 [ 167.974623] [drm:intel_dump_pipe_config] double wide: 0 [ 167.974625] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 167.974626] [drm:intel_dump_pipe_config] planes on this crtc [ 167.974630] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 167.974633] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 167.974636] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 167.974638] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 167.974640] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 167.974646] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ae4000 state to ffffa2a625ae2800 [ 167.974648] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625ae3800 state to ffffa2a625ae2800 [ 167.974651] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 167.974657] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 167.974659] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 167.974662] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 167.974666] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 167.974669] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 167.974673] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 167.974683] [drm:drm_atomic_commit] commiting ffffa2a625ae2800 [ 167.974694] [drm:intel_power_well_enable] enabling DDI A/E power well [ 167.974699] [drm:skl_set_power_well] Enabling DDI A/E power well [ 167.974705] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 167.975818] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 167.975822] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 167.975825] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 167.975829] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 167.975832] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 167.975835] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 167.975838] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 167.975841] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 167.975844] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 167.975846] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 167.975849] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 167.975852] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 167.975855] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 167.975857] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 167.975860] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 167.975864] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 167.975868] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 167.975871] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 167.975876] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 167.975878] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 167.975891] [drm:edp_panel_on] Turn eDP port A panel power on [ 167.975910] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 167.975986] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 167.976004] [drm:wait_panel_status] Wait complete [ 167.976038] [drm:edp_panel_on] Wait for panel power on [ 167.976113] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 168.177016] [drm:wait_panel_status] Wait complete [ 168.178169] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 168.178171] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 168.178173] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 168.178175] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 168.178859] [drm:intel_dp_start_link_train] clock recovery OK [ 168.178862] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 168.178864] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 168.179847] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 168.179849] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 168.179850] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 168.180821] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 168.180997] [drm:skylake_pfit_enable] for crtc_state = ffffa2a625ae1000 [ 168.181095] [drm:intel_enable_pipe] enabling pipe A [ 168.181104] [drm:intel_edp_backlight_on.part.29] [ 168.181108] [drm:intel_panel_enable_backlight] pipe A [ 168.181189] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 168.181245] [drm:intel_psr_enable] PSR disable by flag [ 168.181246] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 168.198056] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 168.198066] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 168.198086] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 168.198096] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ae2800 [ 168.198102] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ae2800 [ 168.198136] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 168.198140] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625baa000 [ 168.198143] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 168.198152] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 168.214656] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 168.214663] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 168.214701] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 168.214704] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 168.214864] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 168.214869] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6258196c0 state to ffffa2a625baa000 [ 168.214873] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bad800 state to ffffa2a625baa000 [ 168.214876] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6258196c0 to [CRTC:26:pipe A] [ 168.214879] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6258196c0 [ 168.214881] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 168.214890] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 168.214892] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 168.214934] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 168.214963] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 168.214967] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 168.341089] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bae000 [ 168.341093] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab000 state to ffffa2a625bae000 [ 168.341095] [drm:drm_atomic_check_only] checking ffffa2a625bae000 [ 168.341098] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 168.341100] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 168.341102] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bae000 [ 168.341104] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf7520 state to ffffa2a625bae000 [ 168.341106] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625819e40 state to ffffa2a625bae000 [ 168.341107] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625819d80 state to ffffa2a625bae000 [ 168.341109] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bae000 [ 168.341112] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 168.341112] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 168.341118] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 168.341122] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 168.341127] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 168.341129] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 168.341131] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 168.341133] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625bab000 for pipe A [ 168.341134] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 168.341135] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 168.341137] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 168.341139] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 168.341140] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 168.341141] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 168.341142] [drm:intel_dump_pipe_config] requested mode: [ 168.341146] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 168.341147] [drm:intel_dump_pipe_config] adjusted mode: [ 168.341149] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 168.341151] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 168.341152] [drm:intel_dump_pipe_config] port clock: 540000 [ 168.341153] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 168.341154] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 168.341155] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 168.341157] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 168.341158] [drm:intel_dump_pipe_config] ips: 0 [ 168.341159] [drm:intel_dump_pipe_config] double wide: 0 [ 168.341160] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 168.341161] [drm:intel_dump_pipe_config] planes on this crtc [ 168.341163] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 168.341164] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 168.341166] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 168.341168] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 168.341169] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 168.341171] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 168.341172] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 168.341176] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625baa000 state to ffffa2a625bae000 [ 168.341177] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625bac800 state to ffffa2a625bae000 [ 168.341179] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 168.341183] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 168.341185] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 168.341186] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 168.341188] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 168.341189] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 168.341192] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 168.341193] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 168.341196] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 168.341201] [drm:drm_atomic_commit] commiting ffffa2a625bae000 [ 168.342846] [drm:intel_edp_backlight_off.part.30] [ 168.549937] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 168.550030] [drm:intel_disable_pipe] disabling pipe A [ 168.565588] [drm:edp_panel_off] Turn eDP port A panel power off [ 168.565628] [drm:edp_panel_off] Wait for panel power off time [ 168.565705] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 168.566309] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 168.566314] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 168.566338] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 168.616373] [drm:wait_panel_status] Wait complete [ 168.616390] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 168.616410] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 168.616412] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 168.616430] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 168.616445] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 168.617905] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 168.617909] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 168.617911] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 168.618679] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 168.618683] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 168.618687] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 168.618690] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 168.618693] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 168.618696] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 168.618699] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 168.618702] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 168.618704] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 168.618707] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 168.618710] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 168.618713] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 168.618715] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 168.618718] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 168.618720] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 168.618724] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 168.618727] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 168.618729] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 168.618738] [drm:intel_power_well_disable] disabling DDI A/E power well [ 168.618741] [drm:skl_set_power_well] Disabling DDI A/E power well [ 168.618746] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 168.618749] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 168.618753] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 168.618761] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bae000 [ 168.618766] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bae000 [ 169.206085] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 169.206120] [drm:wait_panel_status] Wait complete [ 169.206181] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 169.206195] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 169.255497] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 169.255503] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 169.255506] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 169.414445] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 169.415542] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 170.623092] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e5800 [ 170.623099] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625f44b40 state to ffffa2a6288e5800 [ 170.623104] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e0000 state to ffffa2a6288e5800 [ 170.623106] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625f44b40 to [NOCRTC] [ 170.623109] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a625f44b40 [ 170.623112] [drm:drm_atomic_check_only] checking ffffa2a6288e5800 [ 170.623122] [drm:drm_atomic_commit] commiting ffffa2a6288e5800 [ 170.623132] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e5800 [ 170.623136] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e5800 [ 170.623146] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 170.623152] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 170.623155] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e5800 [ 170.623157] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e1000 state to ffffa2a6288e5800 [ 170.623160] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625f44cc0 state to ffffa2a6288e5800 [ 170.623164] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e1000 [ 170.623166] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625f44cc0 to [CRTC:26:pipe A] [ 170.623169] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a625f44cc0 [ 170.623171] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e5800 [ 170.623175] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9f20 state to ffffa2a6288e5800 [ 170.623178] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9f20 to [NOCRTC] [ 170.623181] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9f20 to [CRTC:26:pipe A] [ 170.623183] [drm:drm_atomic_check_only] checking ffffa2a6288e5800 [ 170.623188] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 170.623190] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 170.623192] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 170.623195] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 170.623197] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e5800 [ 170.623200] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e5800 [ 170.623204] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 170.623205] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 170.623213] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 170.623218] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 170.623227] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 170.623231] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 170.623233] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 170.623237] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e1000 for pipe A [ 170.623240] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 170.623242] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 170.623244] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 170.623247] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 170.623250] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 170.623252] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 170.623253] [drm:intel_dump_pipe_config] requested mode: [ 170.623258] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 170.623260] [drm:intel_dump_pipe_config] adjusted mode: [ 170.623264] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 170.623267] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 170.623269] [drm:intel_dump_pipe_config] port clock: 540000 [ 170.623271] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 170.623273] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 170.623276] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 170.623278] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 170.623280] [drm:intel_dump_pipe_config] ips: 0 [ 170.623281] [drm:intel_dump_pipe_config] double wide: 0 [ 170.623284] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 170.623285] [drm:intel_dump_pipe_config] planes on this crtc [ 170.623289] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 170.623292] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 170.623295] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 170.623297] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 170.623299] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 170.623304] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e7800 state to ffffa2a6288e5800 [ 170.623307] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e5000 state to ffffa2a6288e5800 [ 170.623309] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 170.623315] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 170.623318] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 170.623320] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 170.623325] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 170.623327] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 170.623331] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 170.623342] [drm:drm_atomic_commit] commiting ffffa2a6288e5800 [ 170.623353] [drm:intel_power_well_enable] enabling DDI A/E power well [ 170.623358] [drm:skl_set_power_well] Enabling DDI A/E power well [ 170.623364] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 170.624831] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 170.624835] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 170.624839] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 170.624842] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 170.624846] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 170.624848] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 170.624851] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 170.624854] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 170.624857] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 170.624860] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 170.624862] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 170.624865] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 170.624868] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 170.624871] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 170.624874] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 170.624878] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 170.624881] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 170.624884] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 170.624889] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 170.624891] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 170.624904] [drm:edp_panel_on] Turn eDP port A panel power on [ 170.624923] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 170.624999] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 170.625017] [drm:wait_panel_status] Wait complete [ 170.625051] [drm:edp_panel_on] Wait for panel power on [ 170.625126] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 170.826432] [drm:wait_panel_status] Wait complete [ 170.827574] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 170.827576] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 170.827578] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 170.827581] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 170.828242] [drm:intel_dp_start_link_train] clock recovery OK [ 170.828245] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 170.828247] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 170.829217] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 170.829218] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 170.829220] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 170.830178] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 170.830350] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e1000 [ 170.830438] [drm:intel_enable_pipe] enabling pipe A [ 170.830444] [drm:intel_edp_backlight_on.part.29] [ 170.830446] [drm:intel_panel_enable_backlight] pipe A [ 170.830525] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 170.830579] [drm:intel_psr_enable] PSR disable by flag [ 170.830579] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 170.847402] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 170.847409] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 170.847423] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 170.847430] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e5800 [ 170.847434] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e5800 [ 170.847459] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 170.847461] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa000 state to ffffa2a625bac800 [ 170.847462] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 170.847469] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 170.864018] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 170.864022] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 170.864050] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 170.864052] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 170.864172] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 170.864175] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625819900 state to ffffa2a625bac800 [ 170.864177] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9000 state to ffffa2a625bac800 [ 170.864179] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625819900 to [CRTC:26:pipe A] [ 170.864180] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625819900 [ 170.864181] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 170.864187] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 170.864188] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 170.864196] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 170.864221] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 170.864224] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 170.993996] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baa000 [ 170.994002] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa800 state to ffffa2a625baa000 [ 170.994004] [drm:drm_atomic_check_only] checking ffffa2a625baa000 [ 170.994009] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 170.994010] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 170.994013] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baa000 [ 170.994016] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf7520 state to ffffa2a625baa000 [ 170.994019] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6266bf000 state to ffffa2a625baa000 [ 170.994022] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6266bf540 state to ffffa2a625baa000 [ 170.994024] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baa000 [ 170.994028] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 170.994029] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 170.994036] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 170.994041] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 170.994048] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 170.994051] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 170.994053] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 170.994056] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625baa800 for pipe A [ 170.994058] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 170.994060] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 170.994062] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 170.994064] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 170.994066] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 170.994068] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 170.994069] [drm:intel_dump_pipe_config] requested mode: [ 170.994074] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 170.994075] [drm:intel_dump_pipe_config] adjusted mode: [ 170.994078] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 170.994081] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 170.994082] [drm:intel_dump_pipe_config] port clock: 540000 [ 170.994084] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 170.994086] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 170.994088] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 170.994090] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 170.994091] [drm:intel_dump_pipe_config] ips: 0 [ 170.994093] [drm:intel_dump_pipe_config] double wide: 0 [ 170.994094] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 170.994096] [drm:intel_dump_pipe_config] planes on this crtc [ 170.994098] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 170.994101] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 170.994104] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 170.994106] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 170.994108] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 170.994110] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 170.994112] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 170.994116] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ba9800 state to ffffa2a625baa000 [ 170.994119] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625bab800 state to ffffa2a625baa000 [ 170.994121] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 170.994126] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 170.994129] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 170.994131] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 170.994133] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 170.994135] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 170.994139] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 170.994141] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 170.994144] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 170.994152] [drm:drm_atomic_commit] commiting ffffa2a625baa000 [ 170.995879] [drm:intel_edp_backlight_off.part.30] [ 171.197997] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 171.198054] [drm:intel_disable_pipe] disabling pipe A [ 171.215801] [drm:edp_panel_off] Turn eDP port A panel power off [ 171.215852] [drm:edp_panel_off] Wait for panel power off time [ 171.215928] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 171.216518] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 171.216523] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 171.216545] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 171.266740] [drm:wait_panel_status] Wait complete [ 171.266755] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 171.266775] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 171.266777] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 171.266794] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 171.266819] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 171.268325] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 171.268330] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 171.268332] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 171.273432] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 171.273438] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 171.273442] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 171.273447] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 171.273450] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 171.273452] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 171.273455] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 171.273458] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 171.273460] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 171.273463] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 171.273465] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 171.273468] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 171.273470] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 171.273473] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 171.273475] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 171.273479] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 171.273482] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 171.273485] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 171.273493] [drm:intel_power_well_disable] disabling DDI A/E power well [ 171.273497] [drm:skl_set_power_well] Disabling DDI A/E power well [ 171.273501] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 171.273505] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 171.273508] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 171.273516] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baa000 [ 171.273522] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baa000 [ 171.830086] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 171.830106] [drm:wait_panel_status] Wait complete [ 171.830162] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 171.830176] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 171.879471] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 171.879476] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 171.879480] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 172.038496] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 172.039593] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 173.277454] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e4800 [ 173.277460] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62bbb9780 state to ffffa2a6288e4800 [ 173.277464] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e6800 state to ffffa2a6288e4800 [ 173.277467] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62bbb9780 to [NOCRTC] [ 173.277469] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a62bbb9780 [ 173.277472] [drm:drm_atomic_check_only] checking ffffa2a6288e4800 [ 173.277483] [drm:drm_atomic_commit] commiting ffffa2a6288e4800 [ 173.277493] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e4800 [ 173.277497] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e4800 [ 173.277507] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 173.277513] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 173.277516] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e4800 [ 173.277519] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e7000 state to ffffa2a6288e4800 [ 173.277522] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a62bbb9300 state to ffffa2a6288e4800 [ 173.277525] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e7000 [ 173.277528] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62bbb9300 to [CRTC:26:pipe A] [ 173.277530] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a62bbb9300 [ 173.277533] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e4800 [ 173.277536] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9d60 state to ffffa2a6288e4800 [ 173.277540] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9d60 to [NOCRTC] [ 173.277542] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9d60 to [CRTC:26:pipe A] [ 173.277544] [drm:drm_atomic_check_only] checking ffffa2a6288e4800 [ 173.277549] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 173.277552] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 173.277554] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 173.277556] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 173.277559] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e4800 [ 173.277562] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e4800 [ 173.277565] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 173.277567] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 173.277575] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 173.277580] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 173.277588] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 173.277592] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 173.277595] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 173.277599] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e7000 for pipe A [ 173.277601] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 173.277603] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 173.277606] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 173.277609] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 173.277611] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 173.277613] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 173.277615] [drm:intel_dump_pipe_config] requested mode: [ 173.277620] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 173.277622] [drm:intel_dump_pipe_config] adjusted mode: [ 173.277626] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 173.277629] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 173.277631] [drm:intel_dump_pipe_config] port clock: 540000 [ 173.277633] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 173.277635] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 173.277638] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 173.277640] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 173.277642] [drm:intel_dump_pipe_config] ips: 0 [ 173.277643] [drm:intel_dump_pipe_config] double wide: 0 [ 173.277646] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 173.277647] [drm:intel_dump_pipe_config] planes on this crtc [ 173.277651] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 173.277654] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 173.277657] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 173.277660] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 173.277662] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 173.277667] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e2800 state to ffffa2a6288e4800 [ 173.277670] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e6000 state to ffffa2a6288e4800 [ 173.277672] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 173.277678] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 173.277680] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 173.277683] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 173.277687] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 173.277690] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 173.277694] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 173.277705] [drm:drm_atomic_commit] commiting ffffa2a6288e4800 [ 173.277716] [drm:intel_power_well_enable] enabling DDI A/E power well [ 173.277720] [drm:skl_set_power_well] Enabling DDI A/E power well [ 173.277726] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 173.279852] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 173.279856] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 173.279859] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 173.279863] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 173.279866] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 173.279869] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 173.279872] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 173.279875] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 173.279877] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 173.279880] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 173.279883] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 173.279886] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 173.279889] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 173.279891] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 173.279894] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 173.279898] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 173.279901] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 173.279904] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 173.279909] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 173.279911] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 173.279924] [drm:edp_panel_on] Turn eDP port A panel power on [ 173.279943] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 173.280020] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 173.280038] [drm:wait_panel_status] Wait complete [ 173.280071] [drm:edp_panel_on] Wait for panel power on [ 173.280147] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 173.480897] [drm:wait_panel_status] Wait complete [ 173.482043] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 173.482045] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 173.482047] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 173.482050] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 173.482702] [drm:intel_dp_start_link_train] clock recovery OK [ 173.482705] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 173.482707] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 173.483641] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 173.483643] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 173.483645] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 173.484594] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 173.484767] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e7000 [ 173.484877] [drm:intel_enable_pipe] enabling pipe A [ 173.484888] [drm:intel_edp_backlight_on.part.29] [ 173.484892] [drm:intel_panel_enable_backlight] pipe A [ 173.484974] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 173.485044] [drm:intel_psr_enable] PSR disable by flag [ 173.485046] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 173.501821] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 173.501842] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 173.501862] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 173.501871] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e4800 [ 173.501877] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e4800 [ 173.501908] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 173.501912] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625bab800 [ 173.501915] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 173.501924] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 173.518432] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 173.518438] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 173.518474] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 173.518478] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 173.518626] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 173.518631] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625819300 state to ffffa2a625bab800 [ 173.518635] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf000 state to ffffa2a625bab800 [ 173.518637] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625819300 to [CRTC:26:pipe A] [ 173.518640] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625819300 [ 173.518642] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 173.518650] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 173.518653] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 173.518665] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 173.518697] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 173.518700] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 173.646182] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ba8800 [ 173.646186] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf800 state to ffffa2a625ba8800 [ 173.646188] [drm:drm_atomic_check_only] checking ffffa2a625ba8800 [ 173.646191] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 173.646192] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 173.646194] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ba8800 [ 173.646195] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf7920 state to ffffa2a625ba8800 [ 173.646201] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a626314a80 state to ffffa2a625ba8800 [ 173.646215] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a629416000 state to ffffa2a625ba8800 [ 173.646216] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ba8800 [ 173.646221] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 173.646221] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 173.646243] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 173.646246] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 173.646251] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 173.646252] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 173.646254] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 173.646257] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625baf800 for pipe A [ 173.646258] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 173.646259] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 173.646260] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 173.646261] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 173.646262] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 173.646263] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 173.646264] [drm:intel_dump_pipe_config] requested mode: [ 173.646267] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 173.646267] [drm:intel_dump_pipe_config] adjusted mode: [ 173.646269] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 173.646270] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 173.646271] [drm:intel_dump_pipe_config] port clock: 540000 [ 173.646272] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 173.646273] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 173.646274] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 173.646275] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 173.646276] [drm:intel_dump_pipe_config] ips: 0 [ 173.646277] [drm:intel_dump_pipe_config] double wide: 0 [ 173.646278] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 173.646279] [drm:intel_dump_pipe_config] planes on this crtc [ 173.646280] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 173.646282] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 173.646283] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 173.646284] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 173.646285] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 173.646287] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 173.646288] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 173.646305] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ba9800 state to ffffa2a625ba8800 [ 173.646306] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625bab800 state to ffffa2a625ba8800 [ 173.646307] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 173.646312] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 173.646313] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 173.646314] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 173.646316] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 173.646317] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 173.646320] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 173.646322] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 173.646324] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 173.646329] [drm:drm_atomic_commit] commiting ffffa2a625ba8800 [ 173.647902] [drm:intel_edp_backlight_off.part.30] [ 173.854044] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 173.854101] [drm:intel_disable_pipe] disabling pipe A [ 173.869649] [drm:edp_panel_off] Turn eDP port A panel power off [ 173.869689] [drm:edp_panel_off] Wait for panel power off time [ 173.869766] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 173.870370] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 173.870375] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 173.870398] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 173.919867] [drm:wait_panel_status] Wait complete [ 173.919882] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 173.919902] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 173.919905] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 173.919922] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 173.919937] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 173.922147] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 173.922153] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 173.922156] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 173.926539] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 173.926545] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 173.926549] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 173.926554] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 173.926557] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 173.926560] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 173.926563] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 173.926566] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 173.926568] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 173.926571] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 173.926574] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 173.926576] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 173.926579] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 173.926581] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 173.926584] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 173.926588] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 173.926591] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 173.926593] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 173.926602] [drm:intel_power_well_disable] disabling DDI A/E power well [ 173.926606] [drm:skl_set_power_well] Disabling DDI A/E power well [ 173.926610] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 173.926614] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 173.926618] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 173.926627] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ba8800 [ 173.926633] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ba8800 [ 174.518117] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 174.518137] [drm:wait_panel_status] Wait complete [ 174.518193] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 174.518207] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 174.567507] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 174.567513] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 174.567516] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 174.726514] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 174.727610] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 175.930876] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e2800 [ 175.930882] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625a47780 state to ffffa2a6288e2800 [ 175.930886] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e0800 state to ffffa2a6288e2800 [ 175.930889] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625a47780 to [NOCRTC] [ 175.930891] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a625a47780 [ 175.930894] [drm:drm_atomic_check_only] checking ffffa2a6288e2800 [ 175.930905] [drm:drm_atomic_commit] commiting ffffa2a6288e2800 [ 175.930915] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e2800 [ 175.930918] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e2800 [ 175.930928] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 175.930934] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 175.930937] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e2800 [ 175.930940] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e6000 state to ffffa2a6288e2800 [ 175.930943] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625a476c0 state to ffffa2a6288e2800 [ 175.930946] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e6000 [ 175.930949] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625a476c0 to [CRTC:26:pipe A] [ 175.930951] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a625a476c0 [ 175.930954] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e2800 [ 175.930957] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9a60 state to ffffa2a6288e2800 [ 175.930960] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9a60 to [NOCRTC] [ 175.930963] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9a60 to [CRTC:26:pipe A] [ 175.930965] [drm:drm_atomic_check_only] checking ffffa2a6288e2800 [ 175.930970] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 175.930973] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 175.930975] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 175.930977] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 175.930979] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e2800 [ 175.930983] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e2800 [ 175.930986] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 175.930988] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 175.930996] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 175.931001] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 175.931010] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 175.931013] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 175.931016] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 175.931020] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e6000 for pipe A [ 175.931022] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 175.931024] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 175.931027] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 175.931030] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 175.931032] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 175.931034] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 175.931036] [drm:intel_dump_pipe_config] requested mode: [ 175.931040] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 175.931042] [drm:intel_dump_pipe_config] adjusted mode: [ 175.931046] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 175.931050] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 175.931052] [drm:intel_dump_pipe_config] port clock: 540000 [ 175.931053] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 175.931056] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 175.931058] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 175.931060] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 175.931062] [drm:intel_dump_pipe_config] ips: 0 [ 175.931064] [drm:intel_dump_pipe_config] double wide: 0 [ 175.931066] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 175.931068] [drm:intel_dump_pipe_config] planes on this crtc [ 175.931071] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 175.931074] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 175.931077] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 175.931079] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 175.931081] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 175.931086] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e7800 state to ffffa2a6288e2800 [ 175.931089] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e7000 state to ffffa2a6288e2800 [ 175.931091] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 175.931097] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 175.931100] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 175.931102] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 175.931107] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 175.931110] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 175.931114] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 175.931125] [drm:drm_atomic_commit] commiting ffffa2a6288e2800 [ 175.931135] [drm:intel_power_well_enable] enabling DDI A/E power well [ 175.931140] [drm:skl_set_power_well] Enabling DDI A/E power well [ 175.931146] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 175.932870] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 175.932873] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 175.932877] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 175.932881] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 175.932884] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 175.932887] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 175.932889] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 175.932892] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 175.932895] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 175.932898] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 175.932901] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 175.932904] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 175.932907] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 175.932909] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 175.932912] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 175.932916] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 175.932919] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 175.932922] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 175.932927] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 175.932930] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 175.932943] [drm:edp_panel_on] Turn eDP port A panel power on [ 175.932962] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 175.933039] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 175.933056] [drm:wait_panel_status] Wait complete [ 175.933090] [drm:edp_panel_on] Wait for panel power on [ 175.933165] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 176.134543] [drm:wait_panel_status] Wait complete [ 176.135683] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 176.135685] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 176.135687] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 176.135689] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 176.136359] [drm:intel_dp_start_link_train] clock recovery OK [ 176.136362] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 176.136364] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 176.137334] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 176.137336] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 176.137337] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 176.138282] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 176.138447] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e6000 [ 176.138519] [drm:intel_enable_pipe] enabling pipe A [ 176.138526] [drm:intel_edp_backlight_on.part.29] [ 176.138527] [drm:intel_panel_enable_backlight] pipe A [ 176.138606] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 176.138660] [drm:intel_psr_enable] PSR disable by flag [ 176.138661] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 176.155568] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 176.155576] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 176.155589] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 176.155596] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e2800 [ 176.155601] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e2800 [ 176.155626] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 176.155629] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625bab800 [ 176.155630] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 176.155636] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 176.172238] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 176.172242] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 176.172269] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 176.172271] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 176.172405] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 176.172408] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a629416f00 state to ffffa2a625bab800 [ 176.172410] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa800 state to ffffa2a625bab800 [ 176.172412] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a629416f00 to [CRTC:26:pipe A] [ 176.172413] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a629416f00 [ 176.172415] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 176.172420] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 176.172421] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 176.172429] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 176.172455] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 176.172459] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 176.302012] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ba9800 [ 176.302016] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa000 state to ffffa2a625ba9800 [ 176.302017] [drm:drm_atomic_check_only] checking ffffa2a625ba9800 [ 176.302020] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 176.302021] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 176.302023] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ba9800 [ 176.302025] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf77a0 state to ffffa2a625ba9800 [ 176.302027] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625db86c0 state to ffffa2a625ba9800 [ 176.302029] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625db8780 state to ffffa2a625ba9800 [ 176.302030] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ba9800 [ 176.302033] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 176.302034] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 176.302038] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 176.302041] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 176.302046] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 176.302048] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 176.302049] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 176.302051] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625baa000 for pipe A [ 176.302053] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 176.302054] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 176.302055] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 176.302056] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 176.302057] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 176.302058] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 176.302059] [drm:intel_dump_pipe_config] requested mode: [ 176.302065] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 176.302066] [drm:intel_dump_pipe_config] adjusted mode: [ 176.302068] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 176.302069] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 176.302070] [drm:intel_dump_pipe_config] port clock: 540000 [ 176.302071] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 176.302073] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 176.302075] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 176.302076] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 176.302077] [drm:intel_dump_pipe_config] ips: 0 [ 176.302078] [drm:intel_dump_pipe_config] double wide: 0 [ 176.302079] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 176.302080] [drm:intel_dump_pipe_config] planes on this crtc [ 176.302083] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 176.302085] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 176.302087] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 176.302088] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 176.302089] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 176.302091] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 176.302092] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 176.302095] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ba9000 state to ffffa2a625ba9800 [ 176.302096] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625bac800 state to ffffa2a625ba9800 [ 176.302097] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 176.302102] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 176.302103] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 176.302104] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 176.302106] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 176.302107] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 176.302110] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 176.302111] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 176.302113] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 176.302118] [drm:drm_atomic_commit] commiting ffffa2a625ba9800 [ 176.303918] [drm:intel_edp_backlight_off.part.30] [ 176.510006] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 176.510100] [drm:intel_disable_pipe] disabling pipe A [ 176.523314] [drm:edp_panel_off] Turn eDP port A panel power off [ 176.523353] [drm:edp_panel_off] Wait for panel power off time [ 176.523429] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 176.524036] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 176.524041] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 176.524064] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 176.574199] [drm:wait_panel_status] Wait complete [ 176.574214] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 176.574235] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 176.574237] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 176.574254] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 176.574269] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 176.575764] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 176.575769] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 176.575772] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 176.576504] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 176.576510] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 176.576514] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 176.576519] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 176.576522] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 176.576525] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 176.576527] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 176.576530] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 176.576533] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 176.576536] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 176.576538] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 176.576541] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 176.576544] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 176.576546] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 176.576549] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 176.576553] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 176.576556] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 176.576559] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 176.576568] [drm:intel_power_well_disable] disabling DDI A/E power well [ 176.576572] [drm:skl_set_power_well] Disabling DDI A/E power well [ 176.576576] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 176.576580] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 176.576584] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 176.576592] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ba9800 [ 176.576598] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ba9800 [ 177.142094] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 177.142114] [drm:wait_panel_status] Wait complete [ 177.142170] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 177.142183] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 177.191485] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 177.191491] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 177.191494] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 177.350492] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 177.351605] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 178.580995] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e1800 [ 178.581001] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625975840 state to ffffa2a6288e1800 [ 178.581006] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e5000 state to ffffa2a6288e1800 [ 178.581008] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625975840 to [NOCRTC] [ 178.581011] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a625975840 [ 178.581013] [drm:drm_atomic_check_only] checking ffffa2a6288e1800 [ 178.581024] [drm:drm_atomic_commit] commiting ffffa2a6288e1800 [ 178.581034] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e1800 [ 178.581038] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e1800 [ 178.581048] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 178.581053] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 178.581056] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e1800 [ 178.581059] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e1000 state to ffffa2a6288e1800 [ 178.581062] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6259750c0 state to ffffa2a6288e1800 [ 178.581066] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e1000 [ 178.581069] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6259750c0 to [CRTC:26:pipe A] [ 178.581071] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a6259750c0 [ 178.581074] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e1800 [ 178.581077] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9d60 state to ffffa2a6288e1800 [ 178.581080] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9d60 to [NOCRTC] [ 178.581083] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9d60 to [CRTC:26:pipe A] [ 178.581085] [drm:drm_atomic_check_only] checking ffffa2a6288e1800 [ 178.581090] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 178.581093] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 178.581095] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 178.581097] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 178.581099] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e1800 [ 178.581103] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e1800 [ 178.581107] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 178.581108] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 178.581116] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 178.581121] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 178.581130] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 178.581133] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 178.581136] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 178.581140] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e1000 for pipe A [ 178.581142] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 178.581144] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 178.581147] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 178.581150] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 178.581152] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 178.581154] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 178.581156] [drm:intel_dump_pipe_config] requested mode: [ 178.581160] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 178.581162] [drm:intel_dump_pipe_config] adjusted mode: [ 178.581166] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 178.581169] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 178.581171] [drm:intel_dump_pipe_config] port clock: 540000 [ 178.581173] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 178.581175] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 178.581178] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 178.581180] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 178.581182] [drm:intel_dump_pipe_config] ips: 0 [ 178.581184] [drm:intel_dump_pipe_config] double wide: 0 [ 178.581186] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 178.581187] [drm:intel_dump_pipe_config] planes on this crtc [ 178.581191] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 178.581194] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 178.581197] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 178.581199] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 178.581201] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 178.581206] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e5800 state to ffffa2a6288e1800 [ 178.581209] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e0000 state to ffffa2a6288e1800 [ 178.581211] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 178.581218] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 178.581220] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 178.581223] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 178.581227] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 178.581230] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 178.581234] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 178.581245] [drm:drm_atomic_commit] commiting ffffa2a6288e1800 [ 178.581256] [drm:intel_power_well_enable] enabling DDI A/E power well [ 178.581261] [drm:skl_set_power_well] Enabling DDI A/E power well [ 178.581267] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 178.582896] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 178.582900] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 178.582903] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 178.582907] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 178.582910] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 178.582913] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 178.582916] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 178.582919] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 178.582921] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 178.582924] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 178.582927] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 178.582930] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 178.582933] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 178.582935] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 178.582938] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 178.582942] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 178.582945] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 178.582948] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 178.582953] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 178.582955] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 178.582968] [drm:edp_panel_on] Turn eDP port A panel power on [ 178.582987] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 178.583064] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 178.583082] [drm:wait_panel_status] Wait complete [ 178.583115] [drm:edp_panel_on] Wait for panel power on [ 178.583190] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 178.784815] [drm:wait_panel_status] Wait complete [ 178.785971] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 178.785973] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 178.785975] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 178.785977] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 178.786645] [drm:intel_dp_start_link_train] clock recovery OK [ 178.786648] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 178.786650] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 178.787620] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 178.787622] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 178.787623] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 178.788582] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 178.788754] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e1000 [ 178.788853] [drm:intel_enable_pipe] enabling pipe A [ 178.788865] [drm:intel_edp_backlight_on.part.29] [ 178.788869] [drm:intel_panel_enable_backlight] pipe A [ 178.788950] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 178.789006] [drm:intel_psr_enable] PSR disable by flag [ 178.789008] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 178.805811] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 178.805821] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 178.805841] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 178.805850] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e1800 [ 178.805856] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e1800 [ 178.805898] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 178.805902] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9000 state to ffffa2a625bac800 [ 178.805904] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 178.805913] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 178.822398] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 178.822404] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 178.822440] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 178.822444] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 178.822600] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 178.822605] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6287d7cc0 state to ffffa2a625bac800 [ 178.822609] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab000 state to ffffa2a625bac800 [ 178.822611] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6287d7cc0 to [CRTC:26:pipe A] [ 178.822613] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6287d7cc0 [ 178.822616] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 178.822623] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 178.822625] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 178.822637] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 178.822669] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 178.822673] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 178.952041] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ba9000 [ 178.952045] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625ba9000 [ 178.952047] [drm:drm_atomic_check_only] checking ffffa2a625ba9000 [ 178.952049] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 178.952051] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 178.952052] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ba9000 [ 178.952054] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf70c0 state to ffffa2a625ba9000 [ 178.952056] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625fec840 state to ffffa2a625ba9000 [ 178.952057] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625fec0c0 state to ffffa2a625ba9000 [ 178.952059] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ba9000 [ 178.952061] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 178.952062] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 178.952067] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 178.952070] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 178.952074] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 178.952076] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 178.952077] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 178.952079] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625bae000 for pipe A [ 178.952080] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 178.952081] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 178.952083] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 178.952084] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 178.952085] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 178.952086] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 178.952087] [drm:intel_dump_pipe_config] requested mode: [ 178.952089] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 178.952090] [drm:intel_dump_pipe_config] adjusted mode: [ 178.952092] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 178.952093] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 178.952094] [drm:intel_dump_pipe_config] port clock: 540000 [ 178.952095] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 178.952096] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 178.952097] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 178.952098] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 178.952099] [drm:intel_dump_pipe_config] ips: 0 [ 178.952100] [drm:intel_dump_pipe_config] double wide: 0 [ 178.952101] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 178.952102] [drm:intel_dump_pipe_config] planes on this crtc [ 178.952104] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 178.952105] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 178.952106] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 178.952108] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 178.952109] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 178.952110] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 178.952111] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 178.952114] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625bad800 state to ffffa2a625ba9000 [ 178.952115] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625bac800 state to ffffa2a625ba9000 [ 178.952116] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 178.952121] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 178.952122] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 178.952123] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 178.952124] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 178.952125] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 178.952128] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 178.952129] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 178.952131] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 178.952136] [drm:drm_atomic_commit] commiting ffffa2a625ba9000 [ 178.953936] [drm:intel_edp_backlight_off.part.30] [ 179.157929] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 179.158021] [drm:intel_disable_pipe] disabling pipe A [ 179.172798] [drm:edp_panel_off] Turn eDP port A panel power off [ 179.172835] [drm:edp_panel_off] Wait for panel power off time [ 179.172922] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 179.173495] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 179.173499] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 179.173523] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 179.223674] [drm:wait_panel_status] Wait complete [ 179.223688] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 179.223708] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 179.223710] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 179.223727] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 179.223741] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 179.225290] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 179.225295] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 179.225298] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 179.226028] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 179.226034] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 179.226038] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 179.226043] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 179.226045] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 179.226048] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 179.226050] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 179.226053] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 179.226056] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 179.226058] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 179.226061] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 179.226064] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 179.226066] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 179.226068] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 179.226071] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 179.226075] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 179.226078] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 179.226080] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 179.226089] [drm:intel_power_well_disable] disabling DDI A/E power well [ 179.226092] [drm:skl_set_power_well] Disabling DDI A/E power well [ 179.226097] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 179.226100] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 179.226104] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 179.226112] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ba9000 [ 179.226118] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ba9000 [ 179.830173] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 179.830193] [drm:wait_panel_status] Wait complete [ 179.830248] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 179.830261] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 179.879565] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 179.879570] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 179.879573] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 180.038557] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 180.039653] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 181.230184] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e1800 [ 181.230190] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625fe0480 state to ffffa2a6288e1800 [ 181.230195] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e5000 state to ffffa2a6288e1800 [ 181.230198] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625fe0480 to [NOCRTC] [ 181.230200] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a625fe0480 [ 181.230203] [drm:drm_atomic_check_only] checking ffffa2a6288e1800 [ 181.230213] [drm:drm_atomic_commit] commiting ffffa2a6288e1800 [ 181.230223] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e1800 [ 181.230227] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e1800 [ 181.230237] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 181.230243] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 181.230246] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e1800 [ 181.230249] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e6800 state to ffffa2a6288e1800 [ 181.230251] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625fe0540 state to ffffa2a6288e1800 [ 181.230255] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e6800 [ 181.230257] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625fe0540 to [CRTC:26:pipe A] [ 181.230260] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a625fe0540 [ 181.230263] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e1800 [ 181.230266] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9a20 state to ffffa2a6288e1800 [ 181.230269] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9a20 to [NOCRTC] [ 181.230272] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9a20 to [CRTC:26:pipe A] [ 181.230274] [drm:drm_atomic_check_only] checking ffffa2a6288e1800 [ 181.230279] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 181.230282] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 181.230284] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 181.230286] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 181.230288] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e1800 [ 181.230292] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e1800 [ 181.230295] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 181.230297] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 181.230304] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 181.230309] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 181.230318] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 181.230321] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 181.230324] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 181.230328] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e6800 for pipe A [ 181.230330] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 181.230332] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 181.230335] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 181.230338] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 181.230341] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 181.230343] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 181.230344] [drm:intel_dump_pipe_config] requested mode: [ 181.230349] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 181.230351] [drm:intel_dump_pipe_config] adjusted mode: [ 181.230355] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 181.230358] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 181.230360] [drm:intel_dump_pipe_config] port clock: 540000 [ 181.230362] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 181.230364] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 181.230366] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 181.230369] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 181.230370] [drm:intel_dump_pipe_config] ips: 0 [ 181.230372] [drm:intel_dump_pipe_config] double wide: 0 [ 181.230374] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 181.230376] [drm:intel_dump_pipe_config] planes on this crtc [ 181.230379] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 181.230382] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 181.230386] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 181.230388] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 181.230390] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 181.230395] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e7000 state to ffffa2a6288e1800 [ 181.230398] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e4800 state to ffffa2a6288e1800 [ 181.230400] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 181.230406] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 181.230409] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 181.230411] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 181.230415] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 181.230418] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 181.230422] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 181.230432] [drm:drm_atomic_commit] commiting ffffa2a6288e1800 [ 181.230443] [drm:intel_power_well_enable] enabling DDI A/E power well [ 181.230448] [drm:skl_set_power_well] Enabling DDI A/E power well [ 181.230454] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 181.231915] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 181.231919] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 181.231923] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 181.231927] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 181.231930] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 181.231933] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 181.231936] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 181.231939] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 181.231942] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 181.231945] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 181.231948] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 181.231951] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 181.231954] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 181.231957] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 181.231960] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 181.231964] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 181.231968] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 181.231971] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 181.231976] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 181.231978] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 181.231992] [drm:edp_panel_on] Turn eDP port A panel power on [ 181.232025] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 181.232107] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 181.232121] [drm:wait_panel_status] Wait complete [ 181.232155] [drm:edp_panel_on] Wait for panel power on [ 181.232230] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 181.433444] [drm:wait_panel_status] Wait complete [ 181.434565] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 181.434568] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 181.434569] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 181.434572] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 181.435231] [drm:intel_dp_start_link_train] clock recovery OK [ 181.435233] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 181.435235] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 181.436205] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 181.436207] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 181.436208] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 181.437169] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 181.437334] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e6800 [ 181.437408] [drm:intel_enable_pipe] enabling pipe A [ 181.437413] [drm:intel_edp_backlight_on.part.29] [ 181.437415] [drm:intel_panel_enable_backlight] pipe A [ 181.437494] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 181.437547] [drm:intel_psr_enable] PSR disable by flag [ 181.437548] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 181.454374] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 181.454381] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 181.454395] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 181.454402] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e1800 [ 181.454406] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e1800 [ 181.454431] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 181.454434] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bad800 state to ffffa2a625bac800 [ 181.454435] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 181.454442] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 181.470949] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 181.470953] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 181.470982] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 181.470984] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 181.471107] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 181.471111] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a626627600 state to ffffa2a625bac800 [ 181.471114] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa000 state to ffffa2a625bac800 [ 181.471115] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626627600 to [CRTC:26:pipe A] [ 181.471117] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a626627600 [ 181.471118] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 181.471124] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 181.471125] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 181.471133] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 181.471159] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 181.471164] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 181.599940] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62855f800 [ 181.599945] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62855e800 state to ffffa2a62855f800 [ 181.599948] [drm:drm_atomic_check_only] checking ffffa2a62855f800 [ 181.599951] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 181.599952] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 181.599955] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62855f800 [ 181.599957] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba6b60 state to ffffa2a62855f800 [ 181.599960] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6266fdd80 state to ffffa2a62855f800 [ 181.599962] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6266fdf00 state to ffffa2a62855f800 [ 181.599964] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62855f800 [ 181.599966] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 181.599967] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 181.599973] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 181.599980] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 181.599997] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 181.599999] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 181.600001] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 181.600003] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a62855e800 for pipe A [ 181.600005] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 181.600006] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 181.600008] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 181.600009] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 181.600011] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 181.600012] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 181.600014] [drm:intel_dump_pipe_config] requested mode: [ 181.600017] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 181.600018] [drm:intel_dump_pipe_config] adjusted mode: [ 181.600021] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 181.600023] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 181.600024] [drm:intel_dump_pipe_config] port clock: 540000 [ 181.600025] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 181.600027] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 181.600028] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 181.600030] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 181.600031] [drm:intel_dump_pipe_config] ips: 0 [ 181.600032] [drm:intel_dump_pipe_config] double wide: 0 [ 181.600034] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 181.600035] [drm:intel_dump_pipe_config] planes on this crtc [ 181.600037] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 181.600039] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 181.600041] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 181.600043] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 181.600044] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 181.600046] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 181.600048] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 181.600052] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a62bb4d000 state to ffffa2a62855f800 [ 181.600054] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a62bb4d800 state to ffffa2a62855f800 [ 181.600055] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 181.600061] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 181.600062] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 181.600064] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 181.600066] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 181.600067] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 181.600071] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 181.600073] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 181.600075] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 181.600081] [drm:drm_atomic_commit] commiting ffffa2a62855f800 [ 181.601959] [drm:intel_edp_backlight_off.part.30] [ 181.806045] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 181.806135] [drm:intel_disable_pipe] disabling pipe A [ 181.821689] [drm:edp_panel_off] Turn eDP port A panel power off [ 181.821727] [drm:edp_panel_off] Wait for panel power off time [ 181.821804] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000000 [ 181.822413] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 181.822418] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 181.822441] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 181.872429] [drm:wait_panel_status] Wait complete [ 181.872444] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 181.872449] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 181.872467] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 181.872508] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 181.872526] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 181.874019] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 181.874023] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 181.874025] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 181.874712] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 181.874717] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 181.874721] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 181.874725] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 181.874728] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 181.874731] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 181.874733] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 181.874736] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 181.874739] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 181.874742] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 181.874745] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 181.874748] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 181.874750] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 181.874752] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 181.874755] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 181.874759] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 181.874762] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 181.874765] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 181.874772] [drm:intel_power_well_disable] disabling DDI A/E power well [ 181.874776] [drm:skl_set_power_well] Disabling DDI A/E power well [ 181.874780] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 181.874784] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 181.874788] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 181.874795] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62855f800 [ 181.874801] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62855f800 [ 182.454288] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 182.454308] [drm:wait_panel_status] Wait complete [ 182.454363] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 182.454377] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 182.503779] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 182.503784] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 182.503787] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 182.662679] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 182.663784] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 183.879157] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e0800 [ 183.879164] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a626512b40 state to ffffa2a6288e0800 [ 183.879168] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e2800 state to ffffa2a6288e0800 [ 183.879171] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626512b40 to [NOCRTC] [ 183.879173] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a626512b40 [ 183.879176] [drm:drm_atomic_check_only] checking ffffa2a6288e0800 [ 183.879187] [drm:drm_atomic_commit] commiting ffffa2a6288e0800 [ 183.879197] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e0800 [ 183.879201] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e0800 [ 183.879211] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 183.879217] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 183.879220] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e0800 [ 183.879223] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e4800 state to ffffa2a6288e0800 [ 183.879225] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a626512cc0 state to ffffa2a6288e0800 [ 183.879229] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e4800 [ 183.879231] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626512cc0 to [CRTC:26:pipe A] [ 183.879234] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a626512cc0 [ 183.879236] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e0800 [ 183.879240] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9580 state to ffffa2a6288e0800 [ 183.879243] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9580 to [NOCRTC] [ 183.879246] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9580 to [CRTC:26:pipe A] [ 183.879248] [drm:drm_atomic_check_only] checking ffffa2a6288e0800 [ 183.879252] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 183.879255] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 183.879257] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 183.879259] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 183.879262] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e0800 [ 183.879265] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e0800 [ 183.879269] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 183.879270] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 183.879278] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 183.879283] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 183.879292] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 183.879295] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 183.879298] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 183.879302] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e4800 for pipe A [ 183.879304] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 183.879306] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 183.879308] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 183.879311] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 183.879314] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 183.879316] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 183.879317] [drm:intel_dump_pipe_config] requested mode: [ 183.879322] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 183.879324] [drm:intel_dump_pipe_config] adjusted mode: [ 183.879328] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 183.879331] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 183.879333] [drm:intel_dump_pipe_config] port clock: 540000 [ 183.879335] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 183.879337] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 183.879339] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 183.879342] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 183.879343] [drm:intel_dump_pipe_config] ips: 0 [ 183.879345] [drm:intel_dump_pipe_config] double wide: 0 [ 183.879347] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 183.879349] [drm:intel_dump_pipe_config] planes on this crtc [ 183.879352] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 183.879355] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 183.879358] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 183.879361] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 183.879363] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 183.879368] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e7000 state to ffffa2a6288e0800 [ 183.879370] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e6000 state to ffffa2a6288e0800 [ 183.879372] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 183.879379] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 183.879381] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 183.879384] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 183.879388] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 183.879391] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 183.879395] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 183.879405] [drm:drm_atomic_commit] commiting ffffa2a6288e0800 [ 183.879416] [drm:intel_power_well_enable] enabling DDI A/E power well [ 183.879421] [drm:skl_set_power_well] Enabling DDI A/E power well [ 183.879427] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 183.880933] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 183.880937] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 183.880941] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 183.880944] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 183.880947] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 183.880950] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 183.880953] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 183.880956] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 183.880959] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 183.880962] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 183.880964] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 183.880967] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 183.880970] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 183.880973] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 183.880976] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 183.880980] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 183.880983] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 183.880986] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 183.880991] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 183.880993] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 183.881006] [drm:edp_panel_on] Turn eDP port A panel power on [ 183.881025] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 183.881102] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 183.881119] [drm:wait_panel_status] Wait complete [ 183.881153] [drm:edp_panel_on] Wait for panel power on [ 183.881228] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 184.082530] [drm:wait_panel_status] Wait complete [ 184.083673] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 184.083676] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 184.083677] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 184.083680] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 184.084349] [drm:intel_dp_start_link_train] clock recovery OK [ 184.084351] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 184.084353] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 184.085323] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 184.085325] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 184.085327] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 184.086285] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 184.086457] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e4800 [ 184.086556] [drm:intel_enable_pipe] enabling pipe A [ 184.086565] [drm:intel_edp_backlight_on.part.29] [ 184.086569] [drm:intel_panel_enable_backlight] pipe A [ 184.086650] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 184.086706] [drm:intel_psr_enable] PSR disable by flag [ 184.086708] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 184.103616] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 184.103626] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 184.103646] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 184.103655] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e0800 [ 184.103661] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e0800 [ 184.103693] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 184.103697] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bad800 state to ffffa2a625bac800 [ 184.103699] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 184.103708] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 184.120189] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 184.120195] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 184.120232] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 184.120235] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 184.120378] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 184.120382] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625aad480 state to ffffa2a625bac800 [ 184.120386] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625bac800 [ 184.120389] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625aad480 to [CRTC:26:pipe A] [ 184.120391] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625aad480 [ 184.120393] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 184.120401] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 184.120403] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 184.120414] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 184.120481] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 184.120484] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 184.250669] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 184.250673] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa800 state to ffffa2a625bad800 [ 184.250675] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 184.250678] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 184.250680] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 184.250682] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bad800 [ 184.250685] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf78e0 state to ffffa2a625bad800 [ 184.250687] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625a07180 state to ffffa2a625bad800 [ 184.250688] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625a07a80 state to ffffa2a625bad800 [ 184.250690] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bad800 [ 184.250693] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 184.250694] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 184.250698] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 184.250702] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 184.250707] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 184.250709] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 184.250710] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 184.250712] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625baa800 for pipe A [ 184.250714] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 184.250715] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 184.250716] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 184.250718] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 184.250719] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 184.250720] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 184.250721] [drm:intel_dump_pipe_config] requested mode: [ 184.250724] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 184.250725] [drm:intel_dump_pipe_config] adjusted mode: [ 184.250727] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 184.250729] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 184.250730] [drm:intel_dump_pipe_config] port clock: 540000 [ 184.250731] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 184.250733] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 184.250734] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 184.250735] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 184.250736] [drm:intel_dump_pipe_config] ips: 0 [ 184.250737] [drm:intel_dump_pipe_config] double wide: 0 [ 184.250739] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 184.250740] [drm:intel_dump_pipe_config] planes on this crtc [ 184.250742] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 184.250743] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 184.250745] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 184.250747] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 184.250748] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 184.250750] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 184.250751] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 184.250754] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625bab800 state to ffffa2a625bad800 [ 184.250756] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625baf800 state to ffffa2a625bad800 [ 184.250757] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 184.250762] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 184.250763] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 184.250765] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 184.250767] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 184.250768] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 184.250771] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 184.250772] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 184.250774] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 184.250780] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 184.252042] [drm:intel_edp_backlight_off.part.30] [ 184.454074] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 184.454131] [drm:intel_disable_pipe] disabling pipe A [ 184.471265] [drm:edp_panel_off] Turn eDP port A panel power off [ 184.471305] [drm:edp_panel_off] Wait for panel power off time [ 184.471382] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 184.471886] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 184.471890] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 184.471914] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 184.521979] [drm:wait_panel_status] Wait complete [ 184.521995] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 184.522015] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 184.522017] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 184.522035] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 184.522050] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 184.523730] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 184.523736] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 184.523739] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 184.526461] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 184.526468] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 184.526472] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 184.526478] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 184.526481] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 184.526484] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 184.526487] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 184.526490] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 184.526493] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 184.526496] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 184.526499] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 184.526502] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 184.526504] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 184.526507] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 184.526510] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 184.526515] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 184.526518] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 184.526521] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 184.526530] [drm:intel_power_well_disable] disabling DDI A/E power well [ 184.526534] [drm:skl_set_power_well] Disabling DDI A/E power well [ 184.526539] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 184.526543] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 184.526547] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 184.526556] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 184.526562] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 185.078152] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000 [ 185.082603] [drm:wait_panel_status] Wait complete [ 185.082666] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 185.082683] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 185.132003] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 185.132008] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 185.132011] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 185.286442] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 185.287507] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 186.531217] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ae6000 [ 186.531224] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6266bfa80 state to ffffa2a625ae6000 [ 186.531228] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ae7000 state to ffffa2a625ae6000 [ 186.531231] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6266bfa80 to [NOCRTC] [ 186.531233] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a6266bfa80 [ 186.531236] [drm:drm_atomic_check_only] checking ffffa2a625ae6000 [ 186.531247] [drm:drm_atomic_commit] commiting ffffa2a625ae6000 [ 186.531256] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ae6000 [ 186.531260] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ae6000 [ 186.531271] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 186.531276] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 186.531279] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ae6000 [ 186.531282] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ae0000 state to ffffa2a625ae6000 [ 186.531285] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6266bff00 state to ffffa2a625ae6000 [ 186.531289] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625ae0000 [ 186.531291] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6266bff00 to [CRTC:26:pipe A] [ 186.531294] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffffa2a6266bff00 [ 186.531297] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae6000 [ 186.531300] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62882f440 state to ffffa2a625ae6000 [ 186.531304] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62882f440 to [NOCRTC] [ 186.531306] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62882f440 to [CRTC:26:pipe A] [ 186.531309] [drm:drm_atomic_check_only] checking ffffa2a625ae6000 [ 186.531313] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 186.531316] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 186.531318] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 186.531320] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 186.531323] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae6000 [ 186.531326] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae6000 [ 186.531330] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 186.531331] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 186.531340] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 186.531345] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 186.531354] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 186.531357] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 186.531360] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 186.531364] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ae0000 for pipe A [ 186.531366] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 186.531368] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 186.531371] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 186.531374] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 186.531376] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 186.531378] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 186.531380] [drm:intel_dump_pipe_config] requested mode: [ 186.531385] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 186.531387] [drm:intel_dump_pipe_config] adjusted mode: [ 186.531391] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 186.531394] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 186.531396] [drm:intel_dump_pipe_config] port clock: 540000 [ 186.531397] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 186.531400] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 186.531402] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 186.531404] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 186.531406] [drm:intel_dump_pipe_config] ips: 0 [ 186.531408] [drm:intel_dump_pipe_config] double wide: 0 [ 186.531410] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 186.531412] [drm:intel_dump_pipe_config] planes on this crtc [ 186.531415] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 186.531418] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 186.531421] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 186.531424] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 186.531426] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 186.531431] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ae2000 state to ffffa2a625ae6000 [ 186.531434] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625ae7800 state to ffffa2a625ae6000 [ 186.531436] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 186.531442] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 186.531444] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 186.531447] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 186.531451] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 186.531454] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 186.531458] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 186.531469] [drm:drm_atomic_commit] commiting ffffa2a625ae6000 [ 186.531479] [drm:intel_power_well_enable] enabling DDI A/E power well [ 186.531484] [drm:skl_set_power_well] Enabling DDI A/E power well [ 186.531491] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 186.532957] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 186.532961] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 186.532964] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 186.532968] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 186.532971] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 186.532974] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 186.532976] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 186.532979] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 186.532982] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 186.532985] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 186.532988] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 186.532991] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 186.532993] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 186.532996] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 186.532999] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 186.533003] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 186.533006] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 186.533009] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 186.533014] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 186.533016] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 186.533029] [drm:edp_panel_on] Turn eDP port A panel power on [ 186.533048] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 186.533125] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 186.533142] [drm:wait_panel_status] Wait complete [ 186.533176] [drm:edp_panel_on] Wait for panel power on [ 186.533251] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 186.735126] [drm:wait_panel_status] Wait complete [ 186.736299] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 186.736302] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 186.736304] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 186.736306] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 186.736977] [drm:intel_dp_start_link_train] clock recovery OK [ 186.736980] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 186.736981] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 186.737952] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 186.737954] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 186.737955] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 186.738913] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 186.739090] [drm:skylake_pfit_enable] for crtc_state = ffffa2a625ae0000 [ 186.739188] [drm:intel_enable_pipe] enabling pipe A [ 186.739198] [drm:intel_edp_backlight_on.part.29] [ 186.739201] [drm:intel_panel_enable_backlight] pipe A [ 186.739282] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 186.739338] [drm:intel_psr_enable] PSR disable by flag [ 186.739340] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 186.756193] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 186.756204] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 186.756224] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 186.756234] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ae6000 [ 186.756239] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ae6000 [ 186.756272] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 186.756276] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab800 state to ffffa2a625baf800 [ 186.756278] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 186.756287] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 186.772850] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 186.772856] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 186.772890] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 186.772893] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 186.773065] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 186.773069] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62662a6c0 state to ffffa2a625baf800 [ 186.773073] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625baf800 [ 186.773076] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62662a6c0 to [CRTC:26:pipe A] [ 186.773078] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a62662a6c0 [ 186.773080] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 186.773089] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 186.773091] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 186.773103] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 186.773137] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 186.773142] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 186.904389] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bab800 [ 186.904393] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf000 state to ffffa2a625bab800 [ 186.904395] [drm:drm_atomic_check_only] checking ffffa2a625bab800 [ 186.904397] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 186.904399] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 186.904400] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bab800 [ 186.904403] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf77e0 state to ffffa2a625bab800 [ 186.904405] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a62662ae40 state to ffffa2a625bab800 [ 186.904406] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62662ad80 state to ffffa2a625bab800 [ 186.904408] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bab800 [ 186.904410] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 186.904411] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 186.904416] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 186.904419] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 186.904424] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 186.904425] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 186.904427] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 186.904429] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625baf000 for pipe A [ 186.904430] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 186.904431] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 186.904432] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 186.904434] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 186.904435] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 186.904436] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 186.904437] [drm:intel_dump_pipe_config] requested mode: [ 186.904440] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 186.904441] [drm:intel_dump_pipe_config] adjusted mode: [ 186.904443] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 186.904444] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 186.904445] [drm:intel_dump_pipe_config] port clock: 540000 [ 186.904446] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 186.904447] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 186.904448] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 186.904450] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 186.904450] [drm:intel_dump_pipe_config] ips: 0 [ 186.904451] [drm:intel_dump_pipe_config] double wide: 0 [ 186.904452] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 186.904453] [drm:intel_dump_pipe_config] planes on this crtc [ 186.904455] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 186.904457] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 186.904458] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 186.904460] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 186.904461] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 186.904462] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 186.904463] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 186.904466] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625baf800 state to ffffa2a625bab800 [ 186.904468] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625baa800 state to ffffa2a625bab800 [ 186.904469] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 186.904473] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 186.904474] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61 [ 186.904476] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 186.904477] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 186.904478] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 186.904481] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 186.904483] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 186.904485] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 186.904490] [drm:drm_atomic_commit] commiting ffffa2a625bab800 [ 186.905998] [drm:intel_edp_backlight_off.part.30] [ 187.110137] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 187.110193] [drm:intel_disable_pipe] disabling pipe A [ 187.123553] [drm:edp_panel_off] Turn eDP port A panel power off [ 187.123593] [drm:edp_panel_off] Wait for panel power off time [ 187.123670] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 187.124272] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 187.124277] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 187.124300] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 187.174304] [drm:wait_panel_status] Wait complete [ 187.174320] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 187.174339] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 187.174342] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 187.174359] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 187.174374] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 187.176065] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 187.176070] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 187.176073] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 187.178785] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 187.178790] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 187.178795] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 187.178800] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 187.178803] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 187.178806] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 187.178809] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 187.178812] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 187.178814] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 187.178817] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 187.178820] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 187.178823] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 187.178825] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 187.178828] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 187.178831] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 187.178835] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 187.178838] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 187.178840] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 187.178850] [drm:intel_power_well_disable] disabling DDI A/E power well [ 187.178854] [drm:skl_set_power_well] Disabling DDI A/E power well [ 187.178858] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 187.178862] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 187.178865] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 187.178874] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bab800 [ 187.178879] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bab800 [ 187.766477] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 187.766497] [drm:wait_panel_status] Wait complete [ 187.766553] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 187.766566] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 187.815688] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 187.815694] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 187.815697] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 187.974721] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 187.975826] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 189.183168] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62bb4d000 [ 189.183174] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625a60900 state to ffffa2a62bb4d000 [ 189.183179] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62bb4d800 state to ffffa2a62bb4d000 [ 189.183181] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625a60900 to [NOCRTC] [ 189.183183] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a625a60900 [ 189.183186] [drm:drm_atomic_check_only] checking ffffa2a62bb4d000 [ 189.183197] [drm:drm_atomic_commit] commiting ffffa2a62bb4d000 [ 189.183207] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62bb4d000 [ 189.183211] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62bb4d000 [ 189.183221] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 189.183227] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 189.183230] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62bb4d000 [ 189.183233] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62855e800 state to ffffa2a62bb4d000 [ 189.183236] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625a60d80 state to ffffa2a62bb4d000 [ 189.183239] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a62855e800 [ 189.183242] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625a60d80 to [CRTC:26:pipe A] [ 189.183244] [drm:drm_atomic_set_fb_for_plane] Set [FB:63] for plane state ffffa2a625a60d80 [ 189.183247] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62bb4d000 [ 189.183251] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba66e0 state to ffffa2a62bb4d000 [ 189.183254] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a628ba66e0 to [NOCRTC] [ 189.183257] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a628ba66e0 to [CRTC:26:pipe A] [ 189.183259] [drm:drm_atomic_check_only] checking ffffa2a62bb4d000 [ 189.183264] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 189.183267] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 189.183269] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 189.183271] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 189.183274] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62bb4d000 [ 189.183277] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62bb4d000 [ 189.183281] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 189.183282] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 189.183290] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 189.183296] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 189.183305] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 189.183308] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 189.183311] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 189.183315] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a62855e800 for pipe A [ 189.183317] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 189.183319] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 189.183322] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 189.183325] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 189.183328] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 189.183330] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 189.183331] [drm:intel_dump_pipe_config] requested mode: [ 189.183336] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 189.183338] [drm:intel_dump_pipe_config] adjusted mode: [ 189.183342] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 189.183345] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 189.183347] [drm:intel_dump_pipe_config] port clock: 540000 [ 189.183349] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 189.183351] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 189.183354] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 189.183356] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 189.183358] [drm:intel_dump_pipe_config] ips: 0 [ 189.183360] [drm:intel_dump_pipe_config] double wide: 0 [ 189.183362] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 189.183363] [drm:intel_dump_pipe_config] planes on this crtc [ 189.183367] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 189.183370] [drm:intel_dump_pipe_config] FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 189.183373] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 189.183375] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 189.183377] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 189.183382] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a62855f800 state to ffffa2a62bb4d000 [ 189.183388] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625748000 state to ffffa2a62bb4d000 [ 189.183390] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 189.183396] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 189.183399] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 189.183401] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 189.183406] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 189.183408] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 189.183412] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 189.183423] [drm:drm_atomic_commit] commiting ffffa2a62bb4d000 [ 189.183436] [drm:intel_power_well_enable] enabling DDI A/E power well [ 189.183441] [drm:skl_set_power_well] Enabling DDI A/E power well [ 189.183448] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 189.184972] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 189.184976] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 189.184979] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 189.184983] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 189.184986] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 189.184989] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 189.184992] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 189.184995] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 189.184998] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 189.185000] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 189.185003] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 189.185006] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 189.185009] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 189.185012] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 189.185015] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 189.185019] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 189.185022] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 189.185025] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 189.185030] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 189.185032] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 189.185045] [drm:edp_panel_on] Turn eDP port A panel power on [ 189.185064] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 189.185141] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 189.185159] [drm:wait_panel_status] Wait complete [ 189.185192] [drm:edp_panel_on] Wait for panel power on [ 189.185268] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 189.387517] [drm:wait_panel_status] Wait complete [ 189.388671] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 189.388673] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 189.388675] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 189.388678] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 189.389347] [drm:intel_dp_start_link_train] clock recovery OK [ 189.389350] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 189.389351] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 189.390321] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 189.390323] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 189.390324] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 189.391286] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 189.391458] [drm:skylake_pfit_enable] for crtc_state = ffffa2a62855e800 [ 189.391557] [drm:intel_enable_pipe] enabling pipe A [ 189.391566] [drm:intel_edp_backlight_on.part.29] [ 189.391570] [drm:intel_panel_enable_backlight] pipe A [ 189.391651] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 189.391707] [drm:intel_psr_enable] PSR disable by flag [ 189.391708] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 189.408492] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 189.408503] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 189.408523] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 189.408534] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62bb4d000 [ 189.408540] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62bb4d000 [ 189.408573] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e1000 [ 189.408577] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e0000 state to ffffa2a6288e1000 [ 189.408580] [drm:drm_atomic_check_only] checking ffffa2a6288e1000 [ 189.408589] [drm:drm_atomic_commit] commiting ffffa2a6288e1000 [ 189.425066] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e1000 [ 189.425071] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e1000 [ 189.425103] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 189.425106] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 189.425240] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 189.425244] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a62669a3c0 state to ffffa2a625bac800 [ 189.425247] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa000 state to ffffa2a625bac800 [ 189.425250] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a62669a3c0 to [CRTC:26:pipe A] [ 189.425252] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a62669a3c0 [ 189.425254] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 189.425261] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 189.425263] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 189.425273] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 189.425299] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 189.425302] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 189.557130] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625749000 [ 189.557135] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625749800 state to ffffa2a625749000 [ 189.557138] [drm:drm_atomic_check_only] checking ffffa2a625749000 [ 189.557142] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 189.557144] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 189.557147] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625749000 [ 189.557150] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba6480 state to ffffa2a625749000 [ 189.557153] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625a60c00 state to ffffa2a625749000 [ 189.557155] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625a60a80 state to ffffa2a625749000 [ 189.557158] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625749000 [ 189.557161] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 189.557162] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 189.557169] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 189.557174] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 189.557181] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 189.557184] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 189.557186] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 189.557189] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625749800 for pipe A [ 189.557191] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 189.557192] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 189.557195] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 189.557197] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 189.557199] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 189.557201] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 189.557202] [drm:intel_dump_pipe_config] requested mode: [ 189.557206] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 189.557208] [drm:intel_dump_pipe_config] adjusted mode: [ 189.557211] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 189.557214] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 189.557215] [drm:intel_dump_pipe_config] port clock: 540000 [ 189.557217] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 189.557219] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 189.557221] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 189.557222] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 189.557224] [drm:intel_dump_pipe_config] ips: 0 [ 189.557225] [drm:intel_dump_pipe_config] double wide: 0 [ 189.557227] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 189.557228] [drm:intel_dump_pipe_config] planes on this crtc [ 189.557231] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 189.557234] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 189.557236] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 189.557238] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 189.557240] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 189.557243] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 189.557245] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 189.557249] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a62574a000 state to ffffa2a625749000 [ 189.557251] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a62574a800 state to ffffa2a625749000 [ 189.557253] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 189.557259] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 189.557261] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 189.557263] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 189.557266] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 189.557267] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 189.557272] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 189.557274] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 189.557277] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 189.557285] [drm:drm_atomic_commit] commiting ffffa2a625749000 [ 189.559010] [drm:intel_edp_backlight_off.part.30] [ 189.766152] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 189.766210] [drm:intel_disable_pipe] disabling pipe A [ 189.777195] [drm:edp_panel_off] Turn eDP port A panel power off [ 189.777235] [drm:edp_panel_off] Wait for panel power off time [ 189.777312] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 189.777887] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 189.777893] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 189.777917] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 189.829098] [drm:wait_panel_status] Wait complete [ 189.829114] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 189.829134] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 189.829136] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 189.829153] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 189.829168] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 189.829563] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 189.829567] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 189.829570] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 189.831276] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 189.831280] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 189.831284] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 189.831288] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 189.831291] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 189.831294] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 189.831296] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 189.831299] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 189.831302] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 189.831304] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 189.831307] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 189.831309] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 189.831312] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 189.831314] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 189.831317] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 189.831321] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 189.831324] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 189.831326] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 189.831334] [drm:intel_power_well_disable] disabling DDI A/E power well [ 189.831337] [drm:skl_set_power_well] Disabling DDI A/E power well [ 189.831341] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 189.831345] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 189.831348] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 189.831356] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625749000 [ 189.831361] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625749000 [ 190.390247] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 190.390267] [drm:wait_panel_status] Wait complete [ 190.390323] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 190.390336] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 190.439639] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 190.439645] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 190.439648] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 190.598638] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 190.599735] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 191.049859] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 191.049866] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625f92000 state to ffffa2a625bac800 [ 191.049870] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625bac800 [ 191.049872] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625f92000 to [NOCRTC] [ 191.049875] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a625f92000 [ 191.049877] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 191.049888] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 191.049898] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 191.049901] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 191.049912] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 191.049918] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 191.049921] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 191.049924] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9000 state to ffffa2a625bac800 [ 191.049926] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625f920c0 state to ffffa2a625bac800 [ 191.049930] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625ba9000 [ 191.049932] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625f920c0 to [CRTC:26:pipe A] [ 191.049934] [drm:drm_atomic_set_fb_for_plane] Set [FB:63] for plane state ffffa2a625f920c0 [ 191.049937] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bac800 [ 191.049941] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf78a0 state to ffffa2a625bac800 [ 191.049944] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf78a0 to [NOCRTC] [ 191.049947] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf78a0 to [CRTC:26:pipe A] [ 191.049949] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 191.049967] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 191.049970] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 191.049972] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 191.049974] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 191.049976] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bac800 [ 191.049979] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bac800 [ 191.049982] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 191.049984] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 191.049992] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 191.049997] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 191.050006] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 191.050009] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 191.050011] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 191.050015] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ba9000 for pipe A [ 191.050017] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 191.050019] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 191.050022] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 191.050024] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 191.050027] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 191.050029] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 191.050030] [drm:intel_dump_pipe_config] requested mode: [ 191.050035] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 191.050036] [drm:intel_dump_pipe_config] adjusted mode: [ 191.050040] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 191.050043] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 191.050044] [drm:intel_dump_pipe_config] port clock: 540000 [ 191.050046] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 191.050049] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 191.050051] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 191.050053] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 191.050055] [drm:intel_dump_pipe_config] ips: 0 [ 191.050056] [drm:intel_dump_pipe_config] double wide: 0 [ 191.050058] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 191.050060] [drm:intel_dump_pipe_config] planes on this crtc [ 191.050063] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 191.050066] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 191.050069] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 191.050071] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 191.050073] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 191.050079] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625bab000 state to ffffa2a625bac800 [ 191.050082] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625baa000 state to ffffa2a625bac800 [ 191.050084] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 191.050090] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 191.050092] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 191.050095] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 191.050099] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 191.050102] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 191.050106] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 191.050115] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 191.050126] [drm:intel_power_well_enable] enabling DDI A/E power well [ 191.050131] [drm:skl_set_power_well] Enabling DDI A/E power well [ 191.050137] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 191.056443] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 191.056448] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 191.056451] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 191.056456] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 191.056458] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 191.056461] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 191.056464] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 191.056467] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 191.056470] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 191.056472] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 191.056475] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 191.056478] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 191.056480] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 191.056483] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 191.056486] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 191.056490] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 191.056493] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 191.056496] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 191.056501] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 191.056503] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 191.056519] [drm:edp_panel_on] Turn eDP port A panel power on [ 191.056538] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 191.056614] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 191.056632] [drm:wait_panel_status] Wait complete [ 191.056665] [drm:edp_panel_on] Wait for panel power on [ 191.056741] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 191.258560] [drm:wait_panel_status] Wait complete [ 191.259706] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 191.259708] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 191.259710] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 191.259712] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 191.260381] [drm:intel_dp_start_link_train] clock recovery OK [ 191.260384] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 191.260385] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 191.261355] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 191.261357] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 191.261358] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 191.262334] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 191.262506] [drm:skylake_pfit_enable] for crtc_state = ffffa2a625ba9000 [ 191.262605] [drm:intel_enable_pipe] enabling pipe A [ 191.262614] [drm:intel_edp_backlight_on.part.29] [ 191.262618] [drm:intel_panel_enable_backlight] pipe A [ 191.262699] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 191.262755] [drm:intel_psr_enable] PSR disable by flag [ 191.262756] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 191.279433] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 191.279445] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 191.279464] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 191.279474] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 191.279480] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 191.279503] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 191.279507] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625bac800 [ 191.279509] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 191.279519] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 191.296128] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 191.296148] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 191.296174] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 191.296177] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 191.296616] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bac800 [ 191.296622] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625f92600 state to ffffa2a625bac800 [ 191.296626] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9000 state to ffffa2a625bac800 [ 191.296629] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625f92600 to [CRTC:26:pipe A] [ 191.296632] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625f92600 [ 191.296635] [drm:drm_atomic_check_only] checking ffffa2a625bac800 [ 191.296644] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 191.296647] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 191.296660] [drm:drm_atomic_commit] commiting ffffa2a625bac800 [ 191.296691] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bac800 [ 191.296695] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bac800 [ 191.967439] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bae000 [ 191.967445] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625bae000 [ 191.967448] [drm:drm_atomic_check_only] checking ffffa2a625bae000 [ 191.967453] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 191.967455] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 191.967457] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bae000 [ 191.967461] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf7080 state to ffffa2a625bae000 [ 191.967464] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625f92240 state to ffffa2a625bae000 [ 191.967466] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625f923c0 state to ffffa2a625bae000 [ 191.967469] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bae000 [ 191.967472] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 191.967474] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 191.967481] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 191.967486] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 191.967494] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 191.967497] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 191.967499] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 191.967503] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ba9800 for pipe A [ 191.967505] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 191.967506] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 191.967509] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 191.967511] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 191.967513] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 191.967515] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 191.967517] [drm:intel_dump_pipe_config] requested mode: [ 191.967521] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 191.967523] [drm:intel_dump_pipe_config] adjusted mode: [ 191.967526] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 191.967529] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 191.967531] [drm:intel_dump_pipe_config] port clock: 540000 [ 191.967532] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 191.967534] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 191.967536] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 191.967538] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 191.967540] [drm:intel_dump_pipe_config] ips: 0 [ 191.967541] [drm:intel_dump_pipe_config] double wide: 0 [ 191.967543] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 191.967545] [drm:intel_dump_pipe_config] planes on this crtc [ 191.967549] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 191.967552] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 191.967555] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 191.967557] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 191.967559] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 191.967562] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 191.967564] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 191.967570] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625baa800 state to ffffa2a625bae000 [ 191.967573] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625baf800 state to ffffa2a625bae000 [ 191.967574] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 191.967581] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 191.967583] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 191.967585] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 191.967588] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 191.967589] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 191.967594] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 191.967596] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 191.967600] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 191.967608] [drm:drm_atomic_commit] commiting ffffa2a625bae000 [ 191.969030] [drm:intel_edp_backlight_off.part.30] [ 192.174065] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 192.174123] [drm:intel_disable_pipe] disabling pipe A [ 192.180789] [drm:edp_panel_off] Turn eDP port A panel power off [ 192.180830] [drm:edp_panel_off] Wait for panel power off time [ 192.180907] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 192.181504] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 192.181509] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 192.181531] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 192.232287] [drm:wait_panel_status] Wait complete [ 192.232304] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 192.232308] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 192.232327] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 192.232371] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 192.232389] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 192.233066] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 192.233071] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 192.233075] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 192.234437] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 192.234442] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 192.234446] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 192.234452] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 192.234455] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 192.234458] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 192.234461] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 192.234464] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 192.234467] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 192.234470] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 192.234473] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 192.234476] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 192.234478] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 192.234481] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 192.234484] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 192.234488] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 192.234491] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 192.234494] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 192.234503] [drm:intel_power_well_disable] disabling DDI A/E power well [ 192.234507] [drm:skl_set_power_well] Disabling DDI A/E power well [ 192.234512] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 192.234516] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 192.234520] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 192.234529] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bae000 [ 192.234535] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bae000 [ 192.822131] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 192.822151] [drm:wait_panel_status] Wait complete [ 192.822207] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 192.822221] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 192.871418] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 192.871424] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 192.871427] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 193.030655] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 193.031753] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 193.536218] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bae000 [ 193.536224] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6266f06c0 state to ffffa2a625bae000 [ 193.536228] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baa000 state to ffffa2a625bae000 [ 193.536231] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6266f06c0 to [NOCRTC] [ 193.536233] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a6266f06c0 [ 193.536236] [drm:drm_atomic_check_only] checking ffffa2a625bae000 [ 193.536247] [drm:drm_atomic_commit] commiting ffffa2a625bae000 [ 193.536257] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bae000 [ 193.536261] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bae000 [ 193.536272] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 193.536279] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 193.536282] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bae000 [ 193.536285] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625bae000 [ 193.536288] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a6266f0600 state to ffffa2a625bae000 [ 193.536292] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625ba9800 [ 193.536294] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6266f0600 to [CRTC:26:pipe A] [ 193.536297] [drm:drm_atomic_set_fb_for_plane] Set [FB:63] for plane state ffffa2a6266f0600 [ 193.536299] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bae000 [ 193.536303] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf78a0 state to ffffa2a625bae000 [ 193.536307] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf78a0 to [NOCRTC] [ 193.536309] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62baf78a0 to [CRTC:26:pipe A] [ 193.536311] [drm:drm_atomic_check_only] checking ffffa2a625bae000 [ 193.536316] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 193.536319] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 193.536321] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 193.536323] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 193.536326] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bae000 [ 193.536329] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bae000 [ 193.536333] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 193.536334] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 193.536343] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 193.536348] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 193.536357] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 193.536360] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 193.536363] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 193.536367] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ba9800 for pipe A [ 193.536369] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 193.536371] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 193.536374] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 193.536377] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 193.536379] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 193.536381] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 193.536383] [drm:intel_dump_pipe_config] requested mode: [ 193.536388] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 193.536389] [drm:intel_dump_pipe_config] adjusted mode: [ 193.536393] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 193.536396] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 193.536398] [drm:intel_dump_pipe_config] port clock: 540000 [ 193.536400] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 193.536403] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 193.536405] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 193.536407] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 193.536409] [drm:intel_dump_pipe_config] ips: 0 [ 193.536411] [drm:intel_dump_pipe_config] double wide: 0 [ 193.536413] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 193.536415] [drm:intel_dump_pipe_config] planes on this crtc [ 193.536418] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 193.536421] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 193.536424] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 193.536427] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 193.536429] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 193.536435] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625bab000 state to ffffa2a625bae000 [ 193.536438] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625ba9000 state to ffffa2a625bae000 [ 193.536440] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 193.536447] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 193.536449] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 193.536452] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 193.536456] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 193.536459] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 193.536463] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 193.536474] [drm:drm_atomic_commit] commiting ffffa2a625bae000 [ 193.536486] [drm:intel_power_well_enable] enabling DDI A/E power well [ 193.536491] [drm:skl_set_power_well] Enabling DDI A/E power well [ 193.536497] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 193.542993] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled [ 193.545015] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 193.545020] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 193.545024] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 193.545028] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 193.545032] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 193.545035] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 193.545037] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 193.545041] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 193.545043] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 193.545046] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 193.545049] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 193.545052] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 193.545055] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 193.545057] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 193.545061] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 193.545065] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 193.545068] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 193.545071] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 193.545076] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 193.545078] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 193.545092] [drm:edp_panel_on] Turn eDP port A panel power on [ 193.545111] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 193.545188] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 193.545205] [drm:wait_panel_status] Wait complete [ 193.545239] [drm:edp_panel_on] Wait for panel power on [ 193.545314] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 193.746432] [drm:wait_panel_status] Wait complete [ 193.747579] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 193.747581] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 193.747583] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 193.747585] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 193.748255] [drm:intel_dp_start_link_train] clock recovery OK [ 193.748258] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 193.748260] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 193.749230] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 193.749232] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 193.749233] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 193.750207] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 193.750379] [drm:skylake_pfit_enable] for crtc_state = ffffa2a625ba9800 [ 193.750478] [drm:intel_enable_pipe] enabling pipe A [ 193.750488] [drm:intel_edp_backlight_on.part.29] [ 193.750491] [drm:intel_panel_enable_backlight] pipe A [ 193.750573] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 193.750628] [drm:intel_psr_enable] PSR disable by flag [ 193.750630] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 193.767421] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 193.767433] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 193.767452] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 193.767461] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bae000 [ 193.767467] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bae000 [ 193.767491] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bae000 [ 193.767495] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625baf800 state to ffffa2a625bae000 [ 193.767497] [drm:drm_atomic_check_only] checking ffffa2a625bae000 [ 193.767507] [drm:drm_atomic_commit] commiting ffffa2a625bae000 [ 193.783967] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bae000 [ 193.783984] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bae000 [ 193.784010] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 193.784013] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 193.784383] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bae000 [ 193.784390] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a6266f0300 state to ffffa2a625bae000 [ 193.784395] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba9800 state to ffffa2a625bae000 [ 193.784399] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a6266f0300 to [CRTC:26:pipe A] [ 193.784402] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a6266f0300 [ 193.784405] [drm:drm_atomic_check_only] checking ffffa2a625bae000 [ 193.784414] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 193.784418] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 193.784433] [drm:drm_atomic_commit] commiting ffffa2a625bae000 [ 193.784468] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bae000 [ 193.784473] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bae000 [ 194.372486] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625bad800 [ 194.372492] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab800 state to ffffa2a625bad800 [ 194.372495] [drm:drm_atomic_check_only] checking ffffa2a625bad800 [ 194.372499] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 194.372501] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 194.372504] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bad800 [ 194.372507] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf7560 state to ffffa2a625bad800 [ 194.372511] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625fec3c0 state to ffffa2a625bad800 [ 194.372513] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625fecd80 state to ffffa2a625bad800 [ 194.372516] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625bad800 [ 194.372519] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 194.372521] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 194.372529] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 194.372533] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 194.372541] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 194.372544] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 194.372546] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 194.372549] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625bab800 for pipe A [ 194.372552] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 194.372553] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 194.372555] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 194.372558] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 194.372560] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 194.372562] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 194.372563] [drm:intel_dump_pipe_config] requested mode: [ 194.372568] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 194.372570] [drm:intel_dump_pipe_config] adjusted mode: [ 194.372573] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 194.372576] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 194.372577] [drm:intel_dump_pipe_config] port clock: 540000 [ 194.372579] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 194.372581] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 194.372583] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 194.372585] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 194.372587] [drm:intel_dump_pipe_config] ips: 0 [ 194.372588] [drm:intel_dump_pipe_config] double wide: 0 [ 194.372590] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 194.372592] [drm:intel_dump_pipe_config] planes on this crtc [ 194.372595] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 194.372598] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 194.372600] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 194.372603] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 194.372605] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 194.372607] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 194.372609] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 194.372614] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ba8800 state to ffffa2a625bad800 [ 194.372617] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625baf000 state to ffffa2a625bad800 [ 194.372619] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 194.372625] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 194.372627] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 194.372629] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 194.372632] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 194.372634] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 194.372638] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 194.372640] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 194.372644] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 194.372657] [drm:drm_atomic_commit] commiting ffffa2a625bad800 [ 194.374055] [drm:intel_edp_backlight_off.part.30] [ 194.582073] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 194.582113] [drm:intel_disable_pipe] disabling pipe A [ 194.584422] [drm:edp_panel_off] Turn eDP port A panel power off [ 194.584462] [drm:edp_panel_off] Wait for panel power off time [ 194.584539] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 194.585138] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 194.585144] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 194.585210] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 194.635976] [drm:wait_panel_status] Wait complete [ 194.636000] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 194.636005] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 194.636023] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 194.636066] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 194.636084] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 194.636913] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 194.636919] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 194.636922] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 194.640380] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 194.640385] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 194.640389] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 194.640395] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 194.640398] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 194.640401] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 194.640403] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 194.640406] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 194.640409] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 194.640412] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 194.640414] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 194.640417] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 194.640420] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 194.640422] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 194.640425] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 194.640429] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 194.640432] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 194.640435] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 194.640444] [drm:intel_power_well_disable] disabling DDI A/E power well [ 194.640448] [drm:skl_set_power_well] Disabling DDI A/E power well [ 194.640452] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 194.640456] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 194.640459] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 194.640468] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625bad800 [ 194.640473] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625bad800 [ 195.190279] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 195.190314] [drm:wait_panel_status] Wait complete [ 195.190374] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 195.190388] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 195.239809] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 195.239815] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 195.239818] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 195.398773] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 195.399884] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 196.645031] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ae4800 [ 196.645037] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a626371300 state to ffffa2a625ae4800 [ 196.645041] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ae3800 state to ffffa2a625ae4800 [ 196.645044] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626371300 to [NOCRTC] [ 196.645046] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a626371300 [ 196.645049] [drm:drm_atomic_check_only] checking ffffa2a625ae4800 [ 196.645060] [drm:drm_atomic_commit] commiting ffffa2a625ae4800 [ 196.645070] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ae4800 [ 196.645074] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ae4800 [ 196.645084] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 196.645090] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 196.645093] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625ae4800 [ 196.645096] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ae4000 state to ffffa2a625ae4800 [ 196.645098] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a626371180 state to ffffa2a625ae4800 [ 196.645102] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a625ae4000 [ 196.645104] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a626371180 to [CRTC:26:pipe A] [ 196.645107] [drm:drm_atomic_set_fb_for_plane] Set [FB:63] for plane state ffffa2a626371180 [ 196.645110] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae4800 [ 196.645113] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62882f780 state to ffffa2a625ae4800 [ 196.645116] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62882f780 to [NOCRTC] [ 196.645119] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62882f780 to [CRTC:26:pipe A] [ 196.645121] [drm:drm_atomic_check_only] checking ffffa2a625ae4800 [ 196.645126] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 196.645128] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 196.645130] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 196.645133] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 196.645135] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae4800 [ 196.645139] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625ae4800 [ 196.645142] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 196.645144] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 196.645151] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 196.645156] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 196.645165] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 196.645168] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 196.645171] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 196.645174] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625ae4000 for pipe A [ 196.645177] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 196.645179] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 196.645182] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 196.645184] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 196.645187] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 196.645189] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 196.645191] [drm:intel_dump_pipe_config] requested mode: [ 196.645195] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 196.645197] [drm:intel_dump_pipe_config] adjusted mode: [ 196.645201] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 196.645204] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 196.645206] [drm:intel_dump_pipe_config] port clock: 540000 [ 196.645208] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 196.645210] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 196.645212] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 196.645215] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 196.645217] [drm:intel_dump_pipe_config] ips: 0 [ 196.645218] [drm:intel_dump_pipe_config] double wide: 0 [ 196.645221] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 196.645222] [drm:intel_dump_pipe_config] planes on this crtc [ 196.645226] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 196.645229] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 196.645232] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 196.645234] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 196.645236] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 196.645241] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625ae1000 state to ffffa2a625ae4800 [ 196.645244] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625ae2800 state to ffffa2a625ae4800 [ 196.645246] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 196.645252] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 196.645255] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 196.645257] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 196.645262] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 196.645265] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 196.645269] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 196.645279] [drm:drm_atomic_commit] commiting ffffa2a625ae4800 [ 196.645290] [drm:intel_power_well_enable] enabling DDI A/E power well [ 196.645294] [drm:skl_set_power_well] Enabling DDI A/E power well [ 196.645301] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 196.647008] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 196.647012] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 196.647015] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 196.647019] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 196.647022] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 196.647025] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 196.647028] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 196.647031] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 196.647033] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 196.647036] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 196.647039] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 196.647042] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 196.647045] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 196.647047] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 196.647050] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 196.647054] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 196.647057] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 196.647060] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 196.647065] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 196.647067] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 196.647081] [drm:edp_panel_on] Turn eDP port A panel power on [ 196.647100] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 196.647176] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 196.647194] [drm:wait_panel_status] Wait complete [ 196.647227] [drm:edp_panel_on] Wait for panel power on [ 196.647316] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 196.848437] [drm:wait_panel_status] Wait complete [ 196.849598] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 196.849601] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 196.849602] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 196.849605] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 196.850279] [drm:intel_dp_start_link_train] clock recovery OK [ 196.850282] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 196.850284] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 196.851256] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 196.851258] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 196.851260] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 196.852221] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 196.852393] [drm:skylake_pfit_enable] for crtc_state = ffffa2a625ae4000 [ 196.852496] [drm:intel_enable_pipe] enabling pipe A [ 196.852505] [drm:intel_edp_backlight_on.part.29] [ 196.852509] [drm:intel_panel_enable_backlight] pipe A [ 196.852591] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 196.852647] [drm:intel_psr_enable] PSR disable by flag [ 196.852649] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 196.869322] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 196.869332] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 196.869351] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 196.869361] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625ae4800 [ 196.869367] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625ae4800 [ 196.869399] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf000 [ 196.869403] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625ba8800 state to ffffa2a625baf000 [ 196.869406] [drm:drm_atomic_check_only] checking ffffa2a625baf000 [ 196.869415] [drm:drm_atomic_commit] commiting ffffa2a625baf000 [ 196.885953] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf000 [ 196.885957] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf000 [ 196.885982] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 196.885985] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 196.886125] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf000 [ 196.886129] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625db8600 state to ffffa2a625baf000 [ 196.886132] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625baf000 [ 196.886134] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625db8600 to [CRTC:26:pipe A] [ 196.886137] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625db8600 [ 196.886139] [drm:drm_atomic_check_only] checking ffffa2a625baf000 [ 196.886144] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 196.886147] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 196.886154] [drm:drm_atomic_commit] commiting ffffa2a625baf000 [ 196.886179] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf000 [ 196.886181] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf000 [ 197.018940] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a62574d800 [ 197.018943] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a62574e000 state to ffffa2a62574d800 [ 197.018945] [drm:drm_atomic_check_only] checking ffffa2a62574d800 [ 197.018947] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 197.018948] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 197.018949] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62574d800 [ 197.018951] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a628ba6fc0 state to ffffa2a62574d800 [ 197.018952] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625fcd9c0 state to ffffa2a62574d800 [ 197.018954] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625fcdb40 state to ffffa2a62574d800 [ 197.018955] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a62574d800 [ 197.018957] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 197.018958] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 197.018962] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 197.018965] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 197.018969] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 197.018970] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 197.018972] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 197.018973] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a62574e000 for pipe A [ 197.018974] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 197.018975] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 197.018990] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 197.018991] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 197.018992] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 197.018993] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 197.018994] [drm:intel_dump_pipe_config] requested mode: [ 197.019002] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 197.019003] [drm:intel_dump_pipe_config] adjusted mode: [ 197.019005] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 197.019006] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 197.019007] [drm:intel_dump_pipe_config] port clock: 540000 [ 197.019008] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 197.019009] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 197.019010] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 197.019011] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 197.019012] [drm:intel_dump_pipe_config] ips: 0 [ 197.019013] [drm:intel_dump_pipe_config] double wide: 0 [ 197.019014] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 197.019014] [drm:intel_dump_pipe_config] planes on this crtc [ 197.019016] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 197.019017] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 197.019019] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 197.019020] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 197.019021] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 197.019022] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 197.019023] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 197.019026] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a62574e800 state to ffffa2a62574d800 [ 197.019028] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a62574f000 state to ffffa2a62574d800 [ 197.019028] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 197.019033] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 197.019034] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 197.019035] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 197.019036] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 197.019037] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 197.019040] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 197.019041] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 197.019043] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 197.019048] [drm:drm_atomic_commit] commiting ffffa2a62574d800 [ 197.021095] [drm:intel_edp_backlight_off.part.30] [ 197.230230] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 197.230286] [drm:intel_disable_pipe] disabling pipe A [ 197.237095] [drm:edp_panel_off] Turn eDP port A panel power off [ 197.237133] [drm:edp_panel_off] Wait for panel power off time [ 197.237210] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000 [ 197.237810] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 197.237815] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 197.237837] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 197.287998] [drm:wait_panel_status] Wait complete [ 197.288025] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 197.288045] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 197.288047] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 197.288064] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 197.288079] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz) [ 197.289626] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 197.289631] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 197.289634] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 197.295014] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled [ 197.297035] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 197.297040] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 197.297044] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 197.297049] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 197.297052] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 197.297055] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 197.297058] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 197.297061] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 197.297064] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 197.297066] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 197.297069] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 197.297072] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 197.297075] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 197.297077] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 197.297080] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 197.297084] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 197.297087] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 197.297090] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 197.297098] [drm:intel_power_well_disable] disabling DDI A/E power well [ 197.297101] [drm:skl_set_power_well] Disabling DDI A/E power well [ 197.297105] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 197.297110] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 197.297114] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 197.297122] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a62574d800 [ 197.297128] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a62574d800 [ 197.313609] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e5000 [ 197.313615] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625a8f900 state to ffffa2a6288e5000 [ 197.313619] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e7000 state to ffffa2a6288e5000 [ 197.313621] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625a8f900 to [NOCRTC] [ 197.313623] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffffa2a625a8f900 [ 197.313625] [drm:drm_atomic_check_only] checking ffffa2a6288e5000 [ 197.313634] [drm:drm_atomic_commit] commiting ffffa2a6288e5000 [ 197.313642] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e5000 [ 197.313646] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e5000 [ 197.313655] [drm:drm_mode_setcrtc] [CRTC:26:pipe A] [ 197.313660] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1] [ 197.313662] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a6288e5000 [ 197.313665] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a6288e6000 state to ffffa2a6288e5000 [ 197.313667] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625a8f9c0 state to ffffa2a6288e5000 [ 197.313670] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffffa2a6288e6000 [ 197.313672] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625a8f9c0 to [CRTC:26:pipe A] [ 197.313674] [drm:drm_atomic_set_fb_for_plane] Set [FB:63] for plane state ffffa2a625a8f9c0 [ 197.313676] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e5000 [ 197.313680] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62b6b9be0 state to ffffa2a6288e5000 [ 197.313682] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9be0 to [NOCRTC] [ 197.313685] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffffa2a62b6b9be0 to [CRTC:26:pipe A] [ 197.313686] [drm:drm_atomic_check_only] checking ffffa2a6288e5000 [ 197.313690] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1] [ 197.313693] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A] [ 197.313694] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 197.313696] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y [ 197.313698] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e5000 [ 197.313701] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a6288e5000 [ 197.313704] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 197.313705] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 197.313726] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 197.313731] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 197.313739] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 197.313742] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 197.313744] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 197.313748] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a6288e6000 for pipe A [ 197.313750] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 197.313751] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 197.313754] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 197.313756] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 197.313758] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 197.313760] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 197.313762] [drm:intel_dump_pipe_config] requested mode: [ 197.313766] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 197.313767] [drm:intel_dump_pipe_config] adjusted mode: [ 197.313771] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 197.313773] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 197.313775] [drm:intel_dump_pipe_config] port clock: 540000 [ 197.313777] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 197.313779] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 197.313781] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 197.313783] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 197.313784] [drm:intel_dump_pipe_config] ips: 0 [ 197.313786] [drm:intel_dump_pipe_config] double wide: 0 [ 197.313788] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 197.313789] [drm:intel_dump_pipe_config] planes on this crtc [ 197.313792] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 197.313794] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 197.313797] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 197.313799] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1 [ 197.313801] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 197.313806] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a6288e1800 state to ffffa2a6288e5000 [ 197.313808] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a6288e6800 state to ffffa2a6288e5000 [ 197.313810] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000 [ 197.313816] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 197.313818] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 197.313820] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 197.313825] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 197.313827] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 197.313830] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 197.313839] [drm:drm_atomic_commit] commiting ffffa2a6288e5000 [ 197.313850] [drm:intel_power_well_enable] enabling DDI A/E power well [ 197.313854] [drm:skl_set_power_well] Enabling DDI A/E power well [ 197.313861] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz) [ 197.324932] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled [ 197.338202] [drm:skl_set_cdclk] *ERROR* Failed to inform PCU about cdclk change (-110) [ 197.338209] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 197.338213] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 197.338219] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 197.338223] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 197.338226] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 197.338228] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 197.338232] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 197.338234] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 197.338237] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 197.338240] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 197.338244] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 197.338246] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 197.338249] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 197.338252] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 197.338257] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 197.338260] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 197.338263] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 197.338270] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26 [ 197.338272] [drm:intel_enable_shared_dpll] enabling DPLL 0 [ 197.878247] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 197.878267] [drm:wait_panel_status] Wait complete [ 197.878323] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 197.878337] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 197.934183] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 197.934189] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 197.934192] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 198.086645] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 198.086652] [drm:edp_panel_on] Turn eDP port A panel power on [ 198.086673] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 198.086754] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008 [ 198.086772] [drm:wait_panel_status] Wait complete [ 198.086806] [drm:edp_panel_on] Wait for panel power on [ 198.086881] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b [ 198.287653] [drm:wait_panel_status] Wait complete [ 198.289515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 198.289518] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 198.289519] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 198.289522] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [ 198.290194] [drm:intel_dp_start_link_train] clock recovery OK [ 198.290197] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support [ 198.290199] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [ 198.291167] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 198.291169] [drm:intel_dp_set_signal_levels] Using vswing level 2 [ 198.291170] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 198.292129] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [ 198.292301] [drm:skylake_pfit_enable] for crtc_state = ffffa2a6288e6000 [ 198.292389] [drm:intel_enable_pipe] enabling pipe A [ 198.292398] [drm:intel_edp_backlight_on.part.29] [ 198.292402] [drm:intel_panel_enable_backlight] pipe A [ 198.292499] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 198.292552] [drm:intel_psr_enable] PSR disable by flag [ 198.292553] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [ 198.292996] [drm:intel_cpu_fifo_underrun_irq_handler] *ERROR* CPU pipe A FIFO underrun [ 198.309291] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 198.309297] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 198.309309] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 198.309315] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a6288e5000 [ 198.309318] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a6288e5000 [ 198.309699] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 198.309701] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf000 [ 198.309703] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bac800 state to ffffa2a625baf000 [ 198.309705] [drm:drm_atomic_check_only] checking ffffa2a625baf000 [ 198.309711] [drm:drm_atomic_commit] commiting ffffa2a625baf000 [ 198.325918] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf000 [ 198.325922] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf000 [ 198.325943] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937 [ 198.325945] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282 [ 198.326127] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf000 [ 198.326131] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625a14c00 state to ffffa2a625baf000 [ 198.326135] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bae000 state to ffffa2a625baf000 [ 198.326136] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffffa2a625a14c00 to [CRTC:26:pipe A] [ 198.326139] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffffa2a625a14c00 [ 198.326140] [drm:drm_atomic_check_only] checking ffffa2a625baf000 [ 198.326147] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 198.326149] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 198.326159] [drm:drm_atomic_commit] commiting ffffa2a625baf000 [ 198.326185] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf000 [ 198.326188] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf000 [ 199.433120] [drm:drm_atomic_state_init] Allocated atomic state ffffa2a625baf800 [ 199.433125] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffffa2a625bab800 state to ffffa2a625baf800 [ 199.433128] [drm:drm_atomic_check_only] checking ffffa2a625baf800 [ 199.433132] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed [ 199.433134] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n [ 199.433136] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baf800 [ 199.433139] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffffa2a62baf7560 state to ffffa2a625baf800 [ 199.433142] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffffa2a625f2f600 state to ffffa2a625baf800 [ 199.433144] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffffa2a625f2fa80 state to ffffa2a625baf800 [ 199.433147] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffffa2a625baf800 [ 199.433150] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains [ 199.433151] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24 [ 199.433159] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 199.433163] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz [ 199.433171] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24 [ 199.433173] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000 [ 199.433176] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 199.433179] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffffa2a625bab800 for pipe A [ 199.433181] [drm:intel_dump_pipe_config] cpu_transcoder: EDP [ 199.433182] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 199.433185] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 199.433187] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64 [ 199.433189] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 199.433191] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [ 199.433192] [drm:intel_dump_pipe_config] requested mode: [ 199.433196] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa [ 199.433198] [drm:intel_dump_pipe_config] adjusted mode: [ 199.433201] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa [ 199.433204] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa [ 199.433205] [drm:intel_dump_pipe_config] port clock: 540000 [ 199.433207] [drm:intel_dump_pipe_config] pipe src size: 3200x1800 [ 199.433209] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 199.433211] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 199.433212] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 199.433214] [drm:intel_dump_pipe_config] ips: 0 [ 199.433215] [drm:intel_dump_pipe_config] double wide: 0 [ 199.433217] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 199.433218] [drm:intel_dump_pipe_config] planes on this crtc [ 199.433221] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled [ 199.433224] [drm:intel_dump_pipe_config] FB:63, fb = 3200x1800 format = XR24 little-endian (0x34325258) [ 199.433226] [drm:intel_dump_pipe_config] scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800 [ 199.433228] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled [ 199.433231] [drm:intel_dump_pipe_config] FB:58, fb = 64x64 format = AR24 little-endian (0x34325241) [ 199.433233] [drm:intel_dump_pipe_config] scaler:-1 src 0x1+64+63 dst 2389x0+64+63 [ 199.433235] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1 [ 199.433238] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500 [ 199.433244] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0 [ 199.433246] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 63 [ 199.433248] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1 [ 199.433250] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 58 [ 199.433252] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1 [ 199.433257] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0 [ 199.433259] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A [ 199.433263] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31 [ 199.433268] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffffa2a625baa800 state to ffffa2a625baf800 [ 199.433270] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffffa2a625baa000 state to ffffa2a625baf800 [ 199.433275] [drm:drm_atomic_commit] commiting ffffa2a625baf800 [ 199.435086] [drm:intel_edp_backlight_off.part.30] [ 199.638089] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 199.638142] [drm:intel_disable_pipe] disabling pipe A [ 199.644548] [drm:edp_panel_off] Turn eDP port A panel power off [ 199.644585] [drm:edp_panel_off] Wait for panel power off time [ 199.644662] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000000 [ 199.645242] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010 [ 199.645247] [drm:intel_hpd_irq_handler] digital hpd port A - short [ 199.645269] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short [ 199.696015] [drm:wait_panel_status] Wait complete [ 199.696050] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26 [ 199.696067] [drm:intel_disable_shared_dpll] disabling DPLL 0 [ 199.696071] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [ 199.696088] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 199.696100] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A] [ 199.696104] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B] [ 199.696108] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A] [ 199.696111] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B] [ 199.696113] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C] [ 199.696116] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C] [ 199.696118] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A] [ 199.696121] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B] [ 199.696123] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C] [ 199.696126] [drm:verify_connector_state] [CONNECTOR:46:DP-1] [ 199.696129] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1] [ 199.696131] [drm:verify_connector_state] [CONNECTOR:53:DP-2] [ 199.696134] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2] [ 199.696136] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 199.696139] [drm:verify_single_dpll_state.isra.113] DPLL 1 [ 199.696142] [drm:verify_single_dpll_state.isra.113] DPLL 2 [ 199.696145] [drm:verify_single_dpll_state.isra.113] DPLL 3 [ 199.696152] [drm:intel_power_well_disable] disabling DDI A/E power well [ 199.696156] [drm:skl_set_power_well] Disabling DDI A/E power well [ 199.696160] [drm:verify_connector_state] [CONNECTOR:37:eDP-1] [ 199.696164] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A] [ 199.696167] [drm:verify_single_dpll_state.isra.113] DPLL 0 [ 199.696175] [drm:drm_atomic_state_default_clear] Clearing atomic state ffffa2a625baf800 [ 199.696180] [drm:drm_atomic_state_free] Freeing atomic state ffffa2a625baf800 [ 199.696896] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 199.696903] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 199.696907] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 200.310319] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [ 200.310339] [drm:wait_panel_status] Wait complete [ 200.310395] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008 [ 200.310408] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled [ 200.359745] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 200.359751] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 200.359754] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1 [ 200.518708] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00 [ 200.519798] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [ 203.574289] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off [ 203.574351] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000000 [ 203.574355] [drm:intel_power_well_disable] disabling DC off [ 203.574361] [drm:skl_enable_dc6] Enabling DC6 [ 203.574364] [drm:gen9_set_dc_state] Setting DC state from 00 to 02 [ 203.574748] [drm:intel_power_well_disable] disabling always-on [ 203.577593] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010 [ 203.577598] [drm:intel_hpd_irq_handler] digital hpd port A - long [ 203.577602] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0 [ 203.577626] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A