From 4a0df7c2075ccb1182f924c2bf7ea7832d8a3dc3 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Mon, 13 Feb 2017 16:28:06 +0100 Subject: [PATCH] Add some misc debug logging for 12bpc issues --- drivers/gpu/drm/i915/intel_display.c | 7 +++++++ drivers/gpu/drm/i915/intel_hdmi.c | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 45e587496886..66a0fdbe5a0e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8865,6 +8865,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, } } + WARN_ON(pipe_config->pipe_bpp > 24); + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) pipe_config->limited_color_range = true; @@ -9397,6 +9399,9 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc) BUG(); } + WARN_ON((val && PIPECONF_BPC_MASK) == PIPECONF_10BPC); + WARN_ON((val && PIPECONF_BPC_MASK) == PIPECONF_12BPC); + if (intel_crtc->config->dither) val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); @@ -9970,6 +9975,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, break; } + WARN_ON(pipe_config->pipe_bpp > 24); + if (tmp & PIPECONF_COLOR_RANGE_SELECT) pipe_config->limited_color_range = true; diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index ebae2bd83918..f65ea2398355 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1355,6 +1355,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, * outputs. We also need to check that the higher clock still fits * within limits. */ + DRM_DEBUG_KMS("pipe_config->pipe_bpp %d\n", pipe_config->pipe_bpp); if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK && hdmi_12bpc_possible(pipe_config)) { -- 2.9.3