From 00bc97bc08fdee13e325d3a0ff8943d0099af927 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 15 Feb 2017 08:19:50 +0000 Subject: [PATCH] sync-flush --- drivers/gpu/drm/i915/intel_ringbuffer.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 69c30a7..f4bc467 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1492,25 +1492,14 @@ static void gen6_seqno_barrier(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; + i915_reg_t reg = RING_INSTPM(engine->mmio_base); - /* Workaround to force correct ordering between irq and seqno writes on - * ivb (and maybe also on snb) by reading from a CS register (like - * ACTHD) before reading the status page. - * - * Note that this effectively stalls the read by the time it takes to - * do a memory transaction, which more or less ensures that the write - * from the GPU has sufficient time to invalidate the CPU cacheline. - * Alternatively we could delay the interrupt from the CS ring to give - * the write time to land, but that would incur a delay after every - * batch i.e. much more frequent than a delay when waiting for the - * interrupt (with the same net latency). - * - * Also note that to prevent whole machine hangs on gen7, we have to - * take the spinlock to guard against concurrent cacheline access. - */ - spin_lock_irq(&dev_priv->uncore.lock); - POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); - spin_unlock_irq(&dev_priv->uncore.lock); + intel_uncore_forcewake_get(dev_priv, engine->fw_domains); + I915_WRITE_FW(reg, _MASKED_BIT_ENABLE(INSTPM_SYNC_FLUSH)); + WARN_ON_ONCE(intel_wait_for_register_fw(dev_priv, + reg, INSTPM_SYNC_FLUSH, 0, + 10)); + intel_uncore_forcewake_put(dev_priv, engine->fw_domains); } static void @@ -2593,6 +2582,11 @@ static void intel_ring_init_irq(struct drm_i915_private *dev_priv, { engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; + engine->fw_domains = + intel_uncore_forcewake_for_reg(dev_priv, + RING_INSTPM(engine->mmio_base), + FW_REG_WRITE | FW_REG_READ); + if (INTEL_GEN(dev_priv) >= 8) { engine->irq_enable = gen8_irq_enable; engine->irq_disable = gen8_irq_disable; -- 2.7.4