(gdb) down
#15 0x000003613958ec7b in (anonymous namespace)::ExpandPostRA::runOnMachineFunction (this=0x214bd00, MF=...)
    at /home/admin/Software/r600/llvm-svn/src/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp:200
200           if (TII->expandPostRAPseudo(MI)) {
(gdb) print MI
$4 = <optimized out>
(gdb) print TII
$5 = (const llvm::TargetInstrInfo *) 0x200b0e0
(gdb) print *TII
$6 = {<llvm::MCInstrInfo> = {Desc = 0x3613bdf91c0 <llvm::AMDGPUInsts>, 
    InstrNameIndices = 0x3613b72e7a0 <llvm::AMDGPUInstrNameIndices>, 
    InstrNameData = 0x3613b735b40 <llvm::AMDGPUInstrNameData> "CF_TC_R600", 
    NumOpcodes = 7394}, 
  _vptr.TargetInstrInfo = 0x3613becc818 <vtable for llvm::R600InstrInfo+16>, 
  static CommuteAnyOperandIndex = 4294967295, 
  CallFrameSetupOpcode = 4294967295, CallFrameDestroyOpcode = 4294967295, 
  CatchRetOpcode = 4294967295, ReturnOpcode = 4294967295}
(gdb) down
#14 0x000003613a67af6a in llvm::R600InstrInfo::expandPostRAPseudo (
    this=0x200b0e0, MI=...)
    at /home/admin/Software/r600/llvm-svn/src/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp:1070
1070                          RI.getHWRegChan(MI.getOperand(1).getReg()));
(gdb) print MI
$7 = (
    llvm::MachineInstr &) @0x2cfb7a0: {<llvm::ilist_node_with_parent<llvm::MachineInstr, llvm::MachineBasicBlock, llvm::ilist_sentinel_tracking<true> >> = {<llvm::ilist_node<llvm::MachineInstr, llvm::ilist_sentinel_tracking<true> >> = {<llvm::ilist_node_impl<llvm::ilist_detail::node_options<llvm::MachineInstr, true, true, void> >> = {<llvm::ilist_node_base<true>> = {PrevAndSentinel = {
            Value = 37167248}, 
          Next = 0x21a7d60}, <No data fields>}, <No data fields>}, <No data fields>}, MCID = 0x3613be309c0 <llvm::AMDGPUInsts+227328>, Parent = 0x208a330, 
  Operands = 0x2213640, NumOperands = 3, CapOperands = {Index = 2 '\002'}, 
  Flags = 0 '\000', AsmPrinterFlags = 0 '\000', NumMemRefs = 0 '\000', 
  MemRefs = 0x0, debugLoc = {Loc = {Ref = {MD = 0x0}}}}
(gdb) print MI.Operands
$8 = (llvm::MachineOperand *) 0x2213640
(gdb) print *(MI.Operands)
$9 = {OpKind = llvm::MachineOperand::MO_Register, SubReg_TargetFlags = 0, 
  TiedTo = 0 '\000', IsDef = true, IsImp = false, IsKill = false, 
  IsDead = false, IsUndef = false, IsInternalRead = false, 
  IsEarlyClobber = false, IsDebug = false, SmallContents = {RegNo = 1611, 
    OffsetLo = 1611}, ParentMI = 0x2cfb7a0, Contents = {MBB = 0x2cfb860, 
    CFP = 0x2cfb860, CI = 0x2cfb860, ImmVal = 47167584, RegMask = 0x2cfb860, 
    MD = 0x2cfb860, Sym = 0x2cfb860, CFIIndex = 47167584, 
    IntrinsicID = 47167584, Pred = 47167584, Reg = {Prev = 0x2cfb860, 
      Next = 0x2231ba0}, OffsetedInfo = {Val = {Index = 47167584, 
        SymbolName = 0x2cfb860 "", GV = 0x2cfb860, BA = 0x2cfb860}, 
      OffsetHi = 35855264}}}
(gdb) print MI.Operands->dump
$10 = {void (const llvm::MachineOperand * const)} 0x3613967c300 <llvm::MachineOperand::dump() const>
(gdb) print MI.Operands->dump()

It was killed, but it output this before it died:
%physreg1611<def>

Running it again, I also did this:

(gdb) up
#8  0x000003c23dc07f6a in llvm::R600InstrInfo::expandPostRAPseudo (
    this=0x3c63de0, MI=...)
    at /home/admin/Software/r600/llvm-svn/src/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp:1070
1070                          RI.getHWRegChan(MI.getOperand(1).getReg()));
(gdb) l
1065      case AMDGPU::R600_EXTRACT_ELT_V2:
1066      case AMDGPU::R600_EXTRACT_ELT_V4:
1067        buildIndirectRead(MI.getParent(), MI, MI.getOperand(0).getReg(),
1068                          RI.getHWRegIndex(MI.getOperand(1).getReg()), //  Address
1069                          MI.getOperand(2).getReg(),
1070                          RI.getHWRegChan(MI.getOperand(1).getReg()));
1071        break;
1072      case AMDGPU::R600_INSERT_ELT_V2:
1073      case AMDGPU::R600_INSERT_ELT_V4:
1074        buildIndirectWrite(MI.getParent(), MI, MI.getOperand(2).getReg(), // Value
(gdb) print RI
$3 = {<llvm::AMDGPURegisterInfo> = {<llvm::AMDGPUGenRegisterInfo> = {<llvm::TargetRegisterInfo> = {<llvm::MCRegisterInfo> = {
          Desc = 0x3c23ec98ba0 <llvm::AMDGPURegDesc>, NumRegs = 3457, 
          RAReg = 0, PCReg = 0, 
          Classes = 0x3c23f384c80 <llvm::AMDGPUMCRegisterClasses>, 
          NumClasses = 62, NumRegUnits = 1730, 
          RegUnitRoots = 0x3c23ec97080 <llvm::AMDGPURegUnitRoots>, 
          DiffLists = 0x3c23ecb8c80 <llvm::AMDGPURegDiffLists>, 
          RegUnitMaskSequences = 0x3c23f48ee80 <llvm::AMDGPULaneMaskLists>, 
          RegStrings = 0x3c23ecacfc0 <llvm::AMDGPURegStrings> "SGPR100", 
          RegClassStrings = 0x3c23ec90be0 <llvm::AMDGPURegClassStrings> "R600_KC0", SubRegIndices = 0x3c23ecb8b20 <llvm::AMDGPUSubRegIdxLists>, 
          SubRegIdxRanges = 0x3c23ecb8a00 <llvm::AMDGPUSubRegIdxRanges>, 
          NumSubRegIndices = 68, 
          RegEncodingTable = 0x3c23ec8bfe0 <llvm::AMDGPURegEncodingTable>, 
          L2DwarfRegsSize = 395, EHL2DwarfRegsSize = 395, 
          Dwarf2LRegsSize = 384, EHDwarf2LRegsSize = 384, 
          L2DwarfRegs = 0x3c23ec8e760 <llvm::AMDGPUDwarfFlavour0L2Dwarf>, 
          EHL2DwarfRegs = 0x3c23ec8db00 <llvm::AMDGPUEHFlavour0L2Dwarf>, 
          Dwarf2LRegs = 0x3c23ec8ffe0 <llvm::AMDGPUDwarfFlavour0Dwarf2L>, 
          EHDwarf2LRegs = 0x3c23ec8f3c0 <llvm::AMDGPUEHFlavour0Dwarf2L>, 
          L2SEHRegs = {<llvm::DenseMapBase<llvm::DenseMap<unsigned int, int, llvm::DenseMapInfo<unsigned int>, llvm::detail::DenseMapPair<unsigned int, int> >, unsigned int, int, llvm::DenseMapInfo<unsigned int>, llvm::detail::DenseMapPair<unsigned int, int> >> = {<llvm::DebugEpochBase> = {
                Epoch = 0}, <No data fields>}, Buckets = 0x0, NumEntries = 0, 
            NumTombstones = 0, NumBuckets = 0}, 
          L2CVRegs = {<llvm::DenseMapBase<llvm::DenseMap<unsigned int, int, llvm::DenseMapInfo<unsigned int>, llvm::detail::DenseMapPair<unsigned int, int> >, unsigned int, int, llvm::DenseMapInfo<unsigned int>, llvm::detail::DenseMapPair<unsigned int, int> >> = {<llvm::DebugEpochBase> = {
                Epoch = 0}, <No data fields>}, Buckets = 0x0, NumEntries = 0, 
            NumTombstones = 0, NumBuckets = 0}}, 
        _vptr.TargetRegisterInfo = 0x3c23f45a3f0 <vtable for llvm::R600RegisterInfo+16>, InfoDesc = 0x3c23ebd3da0 <llvm::AMDGPURegInfoDesc>, 
        SubRegIndexNames = 0x3c23f384720 <_ZN4llvmL20SubRegIndexNameTableE>, 
        SubRegIndexLaneMasks = 0x3c23f48eba0 <_ZN4llvmL24SubRegIndexLaneMaskTableE>, 
        RegClassBegin = 0x3c23f457c00 <_ZN4llvm12_GLOBAL__N_1L15RegisterClassesE>, 
        RegClassEnd = 0x3c23f457df0, CoveringLanes = {static FormatStr = 
    <optimized out>, 
          Mask = 4294967280}}, <No data fields>}, <No data fields>}, RCW = {
    RegWeight = 0, WeightLimit = 0}}
(gdb) print MI->dump
$4 = {void (const llvm::MachineInstr * const)} 0x3c23cc0ec80 <llvm::MachineInstr::dump() const>
(gdb) print MI.dump()

And it died again, but managed to print:

%T1_Z<def> = R600_EXTRACT_ELT_V2 %V23_Z<kill>, %T11_Z<kill>