gfx@gfx-desktop:~$ dmesg -w | tee /home/gfx/logkms-flip.log [ 211.762241] Console: switching to colour dummy device 80x25 [ 211.762386] [IGT] kms_flip: executing [ 211.776088] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] [ 211.776138] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1] [ 211.777663] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 211.777697] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 211.779651] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 211.779660] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 211.781660] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 211.781694] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 211.783650] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 211.783659] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: (err -6) [ 211.783666] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected [ 211.783691] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] [ 211.783726] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1] [ 211.784270] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 00 15 01 83 02 00 00 00 00 00 04 [ 211.785261] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes [ 211.785311] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000 [ 211.785356] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 211.785396] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 211.785948] [drm:drm_dp_read_desc] DP branch: OUI 90-cc-24 dev-ID SYNA HW-rev 1.0 SW-rev 2.19 quirks 0x0000 [ 211.786401] [drm:intel_dp_detect [i915]] Sink is MST capable [ 211.786412] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] disconnected [ 211.786443] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] [ 211.786501] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2] [ 211.787666] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 211.787702] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 211.789649] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 211.789656] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [ 211.791664] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 211.791698] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 211.793790] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 211.793799] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: (err -6) [ 211.793805] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected [ 211.793825] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:DP-2] [ 211.795141] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 211.795177] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 211.795231] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 211.795823] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 211.797546] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 211.797580] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 211.798588] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 211.798624] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 211.798699] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 211.799271] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 211.801720] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 211.801749] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 211.802441] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 211.802470] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 211.802510] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 211.803083] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 211.805455] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 211.805478] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 211.806189] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 211.806215] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 211.806281] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 211.806846] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 211.809476] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 211.809493] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 211.810560] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 211.810579] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 211.810635] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 211.811168] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 211.813461] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 211.813478] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 211.814227] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 211.814246] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 211.814304] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 211.814834] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 211.817125] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 211.817142] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 211.817891] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 211.817912] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 211.817981] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 211.818505] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 211.820115] [drm:drm_detect_monitor_audio] Monitor has basic audio support [ 211.820389] [drm:drm_edid_to_eld] ELD monitor S277HK [ 211.820393] [drm:drm_edid_to_eld] ELD size 32, SAD count 1 [ 211.820514] [drm:drm_mode_debug_printmodeline] Modeline 70:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 211.820517] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE [ 211.820523] [drm:drm_mode_debug_printmodeline] Modeline 117:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 211.820526] [drm:drm_mode_prune_invalid] Not using 720x480i mode: NO_INTERLACE [ 211.820532] [drm:drm_mode_debug_printmodeline] Modeline 118:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 211.820534] [drm:drm_mode_prune_invalid] Not using 720x576i mode: NO_INTERLACE [ 211.820540] [drm:drm_mode_debug_printmodeline] Modeline 123:"1920x1080i" 0 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 211.820543] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE [ 211.820549] [drm:drm_mode_debug_printmodeline] Modeline 129:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 211.820551] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE [ 211.820590] [drm:drm_mode_debug_printmodeline] Modeline 137:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 211.820593] [drm:drm_mode_prune_invalid] Not using 720x480i mode: NO_INTERLACE [ 211.820604] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:DP-2] probed modes : [ 211.820608] [drm:drm_mode_debug_printmodeline] Modeline 68:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 211.820611] [drm:drm_mode_debug_printmodeline] Modeline 71:"3840x2160" 30 262790 3840 3888 3920 4000 2160 2165 2170 2191 0x40 0x5 [ 211.820615] [drm:drm_mode_debug_printmodeline] Modeline 72:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5 [ 211.820619] [drm:drm_mode_debug_printmodeline] Modeline 73:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 211.820622] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 211.820627] [drm:drm_mode_debug_printmodeline] Modeline 128:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 211.820630] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 211.820634] [drm:drm_mode_debug_printmodeline] Modeline 124:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 211.820638] [drm:drm_mode_debug_printmodeline] Modeline 139:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 211.820641] [drm:drm_mode_debug_printmodeline] Modeline 92:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6 [ 211.820646] [drm:drm_mode_debug_printmodeline] Modeline 101:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 211.820651] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 211.820655] [drm:drm_mode_debug_printmodeline] Modeline 85:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6 [ 211.820659] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 [ 211.820664] [drm:drm_mode_debug_printmodeline] Modeline 74:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 211.820669] [drm:drm_mode_debug_printmodeline] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 211.820673] [drm:drm_mode_debug_printmodeline] Modeline 130:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 211.820678] [drm:drm_mode_debug_printmodeline] Modeline 122:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 211.820682] [drm:drm_mode_debug_printmodeline] Modeline 86:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 211.820687] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 211.820691] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 211.820696] [drm:drm_mode_debug_printmodeline] Modeline 89:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa [ 211.820700] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 211.820704] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 211.820709] [drm:drm_mode_debug_printmodeline] Modeline 78:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 211.820714] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 211.820718] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 211.820722] [drm:drm_mode_debug_printmodeline] Modeline 116:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 211.820727] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 211.820731] [drm:drm_mode_debug_printmodeline] Modeline 80:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 211.820736] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 211.820740] [drm:drm_mode_debug_printmodeline] Modeline 82:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa [ 211.820744] [drm:drm_mode_debug_printmodeline] Modeline 112:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 211.820749] [drm:drm_mode_debug_printmodeline] Modeline 83:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 211.820754] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 211.820793] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:62:DP-3] [ 211.820809] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:62:DP-3] disconnected [ 211.820823] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-4] [ 211.820826] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-4] disconnected [ 211.821087] [IGT] kms_flip: starting subtest basic-flip-vs-dpms [ 211.821488] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 211.821515] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 211.821918] [drm:drm_mode_addfb2] [FB:70] [ 211.821939] [drm:drm_mode_addfb2] [FB:93] [ 211.912057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A] [ 211.912104] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=8, avail=63 [ 211.912139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 211.915215] [drm:intel_mst_disable_dp [i915]] 1 [ 211.915242] [drm:drm_dp_update_payload_part1] [ 211.916784] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 211.916810] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 211.916869] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 211.917411] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 211.919267] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 211.919290] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 211.919603] [drm:drm_dp_update_payload_part1] removing payload 0 [ 211.919632] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 211.919693] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 211.919906] [drm:intel_disable_pipe [i915]] disabling pipe A [ 211.930155] [drm:intel_mst_post_disable_dp [i915]] 1 [ 211.938904] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 211.939322] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 211.939392] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 211.939425] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 211.939459] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 211.939499] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 211.939525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 211.939549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 211.939582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 211.939649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 211.939689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 211.939728] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 211.939766] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 211.939930] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 211.939963] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 211.940000] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 211.940034] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 211.940067] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 211.940162] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 211.940268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B] [ 211.940396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C] [ 211.940477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A] [ 211.940496] [drm:drm_mode_setcrtc] [CONNECTOR:60:DP-2] [ 211.940570] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 211.940618] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 211.940632] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 211.940636] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 211.940664] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 211.940835] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 211.940861] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 211.940886] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 211.940908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 211.940932] [drm:intel_dump_pipe_config [i915]] requested mode: [ 211.940937] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 211.940960] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 211.940965] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 211.940989] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 211.941010] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 211.941032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 211.941055] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 211.941082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 211.941105] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 211.941128] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0 [ 211.941149] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 211.941172] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 211.941212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 211.941240] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 211.950313] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 211.950346] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 211.950365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 211.950382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 211.950398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 211.950413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 211.950428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 211.950444] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 211.950461] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 211.950477] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 211.950493] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 211.950512] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 211.950531] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 211.950552] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 211.950571] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 211.950643] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 211.952119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 211.952136] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 211.952151] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 211.952167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 211.969056] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 211.969074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 211.985948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 211.988001] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 211.988199] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 211.989329] [drm:intel_enable_pipe [i915]] enabling pipe A [ 211.989355] [drm:intel_mst_enable_dp [i915]] 1 [ 211.991766] [drm:drm_dp_update_payload_part2] payload 0 1 [ 211.993137] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 211.993158] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 211.993221] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 211.993767] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 211.994331] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 211.994356] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 211.994395] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 211.994497] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 211.994520] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 211.995017] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 211.995034] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.006241] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.006270] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.006312] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.039854] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.039882] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.039901] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.039906] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.039907] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.039926] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.039944] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.039962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.039982] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.040002] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.040021] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.040025] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.040045] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.040048] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.040068] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.040088] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.040107] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.040127] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.040147] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.040166] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.040186] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.040206] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.040227] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.040256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 212.040278] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.056499] [drm:intel_mst_disable_dp [i915]] 1 [ 212.056508] [drm:drm_dp_update_payload_part1] [ 212.058073] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.058138] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.058287] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.059318] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.061358] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.061432] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.061738] [drm:drm_dp_update_payload_part1] removing payload 0 [ 212.061825] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 212.061920] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 212.062047] [drm:intel_disable_pipe [i915]] disabling pipe A [ 212.073850] [drm:intel_mst_post_disable_dp [i915]] 1 [ 212.080944] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 212.081355] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 212.081388] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 212.081413] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 212.081443] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 212.081488] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.081518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.081548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.081578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.081656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.081694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.081734] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.081768] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.081794] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.081820] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.081842] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.081864] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.081904] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.081930] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.081956] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.082250] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.082304] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.082348] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.082357] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.082362] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.082401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.082431] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.082458] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.082485] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.082509] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.082533] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.082539] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.082562] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.082605] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.082644] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.082681] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.082717] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.082753] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.082795] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.082831] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.082869] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.082906] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.082944] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.083006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 212.083050] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.083154] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 212.083196] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.083223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.083250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.083276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.083300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.083324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.083350] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.083377] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.083404] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.083429] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.083453] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.083476] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.083505] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 212.083532] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 212.083584] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 212.085152] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 212.085183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 212.085209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 212.085237] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 212.102149] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 212.102166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 212.119035] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 212.121094] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 212.121290] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 212.122382] [drm:intel_enable_pipe [i915]] enabling pipe A [ 212.122409] [drm:intel_mst_enable_dp [i915]] 1 [ 212.124802] [drm:drm_dp_update_payload_part2] payload 0 1 [ 212.126170] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.126193] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.126245] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.126783] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.127351] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 212.127376] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 212.127408] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 212.127778] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 212.127807] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 212.127858] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.127884] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.127942] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.128269] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.128287] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.139402] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.139427] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.139447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.139452] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.139453] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.139475] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.139495] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.139514] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.139535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.139554] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.139613] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.139621] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.139648] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.139653] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.139677] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.139703] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.139728] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.139752] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.139779] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.139803] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.139829] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.139849] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.139865] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.139896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 212.139918] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.156066] [drm:intel_mst_disable_dp [i915]] 1 [ 212.156073] [drm:drm_dp_update_payload_part1] [ 212.157617] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.157660] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.157749] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.158373] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.160329] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.160376] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.160775] [drm:drm_dp_update_payload_part1] removing payload 0 [ 212.160834] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 212.160895] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 212.160978] [drm:intel_disable_pipe [i915]] disabling pipe A [ 212.173353] [drm:intel_mst_post_disable_dp [i915]] 1 [ 212.180277] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 212.180746] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 212.180809] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 212.180855] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 212.180897] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 212.180948] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.180982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.181016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.181046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.181076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.181106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.181136] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.181170] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.181201] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.181232] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.181261] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.181289] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.181339] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.181370] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.181404] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.181800] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.181862] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.181913] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.181924] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.181929] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.181968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.182001] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.182033] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.182064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.182093] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.182122] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.182131] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.182158] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.182165] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.182193] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.182221] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.182250] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.182277] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.182311] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.182341] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.182371] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.182399] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.182427] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.182474] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 212.182511] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.182662] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 212.182735] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.182782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.182833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.182880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.182926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.182972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.183021] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.183072] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.183121] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.183164] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.183195] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.183223] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.183258] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 212.183290] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 212.183343] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 212.184984] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 212.185020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 212.185051] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 212.185084] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 212.202025] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 212.202045] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 212.218945] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 212.221005] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 212.221200] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 212.222308] [drm:intel_enable_pipe [i915]] enabling pipe A [ 212.222336] [drm:intel_mst_enable_dp [i915]] 1 [ 212.224744] [drm:drm_dp_update_payload_part2] payload 0 1 [ 212.226118] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.226142] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.226191] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.226732] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.227301] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 212.227327] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 212.227358] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 212.227414] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 212.227438] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 212.227483] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.227508] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.227549] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.227994] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.228013] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.239352] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.239379] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.239401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.239405] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.239406] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.239426] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.239448] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.239470] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.239491] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.239513] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.239534] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.239538] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.239562] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.239600] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.239631] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.239661] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.239688] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.239712] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.239739] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.239766] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.239793] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.239820] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.239843] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.239883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 212.239912] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.255979] [drm:intel_mst_disable_dp [i915]] 1 [ 212.255986] [drm:drm_dp_update_payload_part1] [ 212.257538] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.257588] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.257711] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.258419] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.260370] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.260428] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.260744] [drm:drm_dp_update_payload_part1] removing payload 0 [ 212.260810] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 212.260882] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 212.260984] [drm:intel_disable_pipe [i915]] disabling pipe A [ 212.272908] [drm:intel_mst_post_disable_dp [i915]] 1 [ 212.279785] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 212.280220] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 212.280260] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 212.280291] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 212.280327] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 212.280376] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.280408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.280438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.280468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.280496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.280524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.280553] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.280648] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.280694] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.280744] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.280784] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.280825] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.280901] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.280948] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.280999] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.281321] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.281362] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.281392] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.281399] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.281402] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.281432] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.281463] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.281499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.281536] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.281575] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.281656] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.281671] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.281713] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.281723] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.281767] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.281809] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.281850] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.281890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.281937] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.281978] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.282021] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.282065] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.282106] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.282178] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 212.282230] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.282379] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 212.282426] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.282459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.282489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.282517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.282545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.282573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.282638] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.282684] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.282729] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.282772] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.282817] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.282857] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.282909] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 212.282956] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 212.283034] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 212.284645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 212.284695] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 212.284730] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 212.284762] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 212.301671] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 212.301688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 212.318555] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 212.320626] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 212.320831] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 212.321988] [drm:intel_enable_pipe [i915]] enabling pipe A [ 212.322014] [drm:intel_mst_enable_dp [i915]] 1 [ 212.324405] [drm:drm_dp_update_payload_part2] payload 0 1 [ 212.325778] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.325801] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.325855] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.326393] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.326983] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 212.327006] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 212.327035] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 212.327085] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 212.327107] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 212.327159] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.327181] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.327218] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.327756] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.327773] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.339064] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.339089] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.339108] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.339112] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.339114] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.339132] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.339150] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.339167] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.339184] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.339203] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.339223] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.339227] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.339246] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.339249] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.339270] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.339290] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.339310] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.339329] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.339349] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.339368] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.339388] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.339408] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.339428] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.339457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 212.339479] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.355737] [drm:intel_mst_disable_dp [i915]] 1 [ 212.355743] [drm:drm_dp_update_payload_part1] [ 212.357288] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.357333] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.357424] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.358056] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.360056] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.360104] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.360416] [drm:drm_dp_update_payload_part1] removing payload 0 [ 212.360463] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 212.360508] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 212.360577] [drm:intel_disable_pipe [i915]] disabling pipe A [ 212.372983] [drm:intel_mst_post_disable_dp [i915]] 1 [ 212.379374] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 212.379838] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 212.379875] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 212.379904] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 212.379937] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 212.379982] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.380011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.380038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.380063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.380088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.380112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.380138] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.380166] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.380192] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.380219] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.380243] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.380266] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.380309] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.380335] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.380363] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.380659] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.380718] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.380750] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.380759] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.380763] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.380795] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.380825] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.380854] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.380883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.380916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.380947] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.380954] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.380982] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.380988] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.381017] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.381044] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.381072] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.381102] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.381136] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.381167] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.381199] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.381229] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.381260] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.381309] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 212.381343] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.381452] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 212.381503] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.381536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.381568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.381619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.381650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.381678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.381708] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.381741] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.381775] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.381808] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.381839] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.381870] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.381904] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 212.381937] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 212.381995] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 212.383510] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 212.383533] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 212.383554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 212.383639] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 212.400569] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 212.400596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 212.417494] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 212.419563] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 212.419771] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 212.420914] [drm:intel_enable_pipe [i915]] enabling pipe A [ 212.420940] [drm:intel_mst_enable_dp [i915]] 1 [ 212.423334] [drm:drm_dp_update_payload_part2] payload 0 1 [ 212.424702] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.424724] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.424777] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.425314] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.425879] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 212.425902] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 212.425930] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 212.425981] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 212.426003] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 212.426055] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.426077] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.426114] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.426571] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.426614] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.438050] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.438087] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.438115] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.438120] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.438122] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.438148] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.438174] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.438198] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.438222] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.438244] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.438265] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.438270] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.438291] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.438295] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.438317] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.438338] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.438358] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.438378] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.438403] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.438424] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.438446] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.438466] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.438487] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.438521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 212.438548] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.454688] [drm:intel_mst_disable_dp [i915]] 1 [ 212.454694] [drm:drm_dp_update_payload_part1] [ 212.456222] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.456253] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.456328] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.456898] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.458711] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.458745] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.459047] [drm:drm_dp_update_payload_part1] removing payload 0 [ 212.459077] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 212.459108] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 212.459153] [drm:intel_disable_pipe [i915]] disabling pipe A [ 212.472825] [drm:intel_mst_post_disable_dp [i915]] 1 [ 212.478307] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 212.478772] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 212.478819] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 212.478856] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 212.478916] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 212.478970] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.479007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.479042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.479074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.479107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.479137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.479171] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.479207] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.479240] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.479273] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.479303] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.479332] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.479387] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.479420] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.479457] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.479923] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.479986] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.480037] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.480048] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.480054] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.480103] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.480153] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.480202] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.480250] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.480295] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.480340] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.480433] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.480478] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.480488] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.480534] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.480581] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.480660] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.480710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.480765] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.480813] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.480863] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.480912] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.480962] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.481040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 212.481096] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.481265] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 212.481339] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.481392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.481443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.481493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.481543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.481592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.481694] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.481751] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.481805] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.481860] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.481909] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.481957] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.482016] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 212.482069] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 212.482154] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 212.483713] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 212.483732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 212.483749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 212.483766] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 212.500664] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 212.500682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 212.517553] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 212.519627] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 212.519827] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 212.521035] [drm:intel_enable_pipe [i915]] enabling pipe A [ 212.521062] [drm:intel_mst_enable_dp [i915]] 1 [ 212.523493] [drm:drm_dp_update_payload_part2] payload 0 1 [ 212.524874] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.524897] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.524959] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.525489] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.526064] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 212.526089] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 212.526120] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 212.526176] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 212.526200] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 212.526246] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.526271] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.526311] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.526775] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.526806] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.538139] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.538175] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.538203] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.538208] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.538210] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.538236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.538265] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.538295] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.538324] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.538352] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.538380] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.538385] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.538413] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.538417] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.538446] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.538474] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.538502] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.538531] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.538560] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.538641] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.539005] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.539030] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.539061] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.539098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 212.539127] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.554734] [drm:intel_mst_disable_dp [i915]] 1 [ 212.554741] [drm:drm_dp_update_payload_part1] [ 212.556274] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.556313] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.556373] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.557071] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.559071] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.559131] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.559433] [drm:drm_dp_update_payload_part1] removing payload 0 [ 212.559488] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 212.559542] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 212.559695] [drm:intel_disable_pipe [i915]] disabling pipe A [ 212.571961] [drm:intel_mst_post_disable_dp [i915]] 1 [ 212.577983] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 212.578377] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 212.578405] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 212.578426] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 212.578452] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 212.578487] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.578510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.578531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.578550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.578633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.578664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.578696] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.578727] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.578757] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.578791] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.578821] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.578850] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.578901] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.578933] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.578969] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.579244] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.579284] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.579315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.579321] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.579324] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.579357] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.579390] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.579421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.579449] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.579480] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.579509] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.579516] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.579545] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.579576] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.579605] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.579637] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.579668] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.579699] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.579731] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.579759] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.579793] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.579824] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.579856] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.579906] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 212.579943] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.580051] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 212.580098] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.580127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.580160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.580190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.580221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.580249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.580277] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.580310] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.580342] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.580373] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.580400] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.580425] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.580460] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 212.580492] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 212.580543] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 212.582087] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 212.582111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 212.582131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 212.582152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 212.599048] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 212.599066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 212.615937] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 212.617997] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 212.618194] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 212.619358] [drm:intel_enable_pipe [i915]] enabling pipe A [ 212.619385] [drm:intel_mst_enable_dp [i915]] 1 [ 212.621774] [drm:drm_dp_update_payload_part2] payload 0 1 [ 212.623143] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.623165] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.623221] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.623765] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.624367] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 212.624392] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 212.624422] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 212.624476] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 212.624499] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 212.624551] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.624599] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.624640] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.625097] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.625115] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.636456] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.636483] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.636504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.636508] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.636510] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.636529] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.636550] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.636617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.636657] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.636694] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.636727] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.636736] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.636768] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.636777] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.636808] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.637008] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.637031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.637052] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.637077] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.637098] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.637120] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.637140] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.637160] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.637196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 212.637223] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.653136] [drm:intel_mst_disable_dp [i915]] 1 [ 212.653143] [drm:drm_dp_update_payload_part1] [ 212.654693] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.654732] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.654826] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.655452] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.657484] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.657546] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.658293] [drm:drm_dp_update_payload_part1] removing payload 0 [ 212.658344] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 212.658396] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 212.658475] [drm:intel_disable_pipe [i915]] disabling pipe A [ 212.669932] [drm:intel_mst_post_disable_dp [i915]] 1 [ 212.677257] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 212.677712] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 212.677770] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 212.677814] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 212.677850] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 212.677897] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.677928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.677957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.677985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.678012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.678038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.678072] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.678110] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.678146] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.678182] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.678216] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.678250] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.678305] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.678341] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.678380] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.678742] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.678802] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.678851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.678861] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.678866] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.678913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.678960] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.679004] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.679048] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.679091] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.679132] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.679142] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.679182] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.679190] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.679232] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.679273] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.679313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.679354] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.679399] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.679438] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.679481] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.679522] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.679562] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.679661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 212.679709] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.679837] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 212.679902] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.679947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.679991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.680033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.680074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.680115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.680157] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.680203] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.680246] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.680290] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.680330] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.680371] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.680418] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 212.680461] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 212.680535] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 212.682085] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 212.682111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 212.682136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 212.682160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 212.699060] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 212.699079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 212.715990] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 212.718050] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 212.718245] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 212.719374] [drm:intel_enable_pipe [i915]] enabling pipe A [ 212.719402] [drm:intel_mst_enable_dp [i915]] 1 [ 212.721796] [drm:drm_dp_update_payload_part2] payload 0 1 [ 212.723164] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.723186] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.723239] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.723778] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.724343] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 212.724368] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 212.724399] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 212.724453] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 212.724479] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 212.724545] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.724599] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.724643] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.725068] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.725085] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.736412] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.736446] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.736472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.736477] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.736479] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.736505] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.736529] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.736553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.736611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.736746] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.736778] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.736785] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.736817] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.736988] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.737025] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.737065] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.737094] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.737118] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.737148] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.737183] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.737219] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.737246] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.737268] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.737306] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 212.737333] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.753067] [drm:intel_mst_disable_dp [i915]] 1 [ 212.753074] [drm:drm_dp_update_payload_part1] [ 212.754638] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.754693] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.754797] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.755467] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.757556] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.757657] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.757908] [drm:drm_dp_update_payload_part1] removing payload 0 [ 212.757962] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 212.758015] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 212.758117] [drm:intel_disable_pipe [i915]] disabling pipe A [ 212.769601] [drm:intel_mst_post_disable_dp [i915]] 1 [ 212.777262] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 212.777712] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 212.777768] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 212.777813] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 212.777866] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 212.777926] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.777958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.777988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.778016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.778044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.778070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.778099] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.778128] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.778156] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.778185] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.778218] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.778252] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.778308] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.778345] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.778383] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.778745] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.778802] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.778846] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.778855] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.778860] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.778903] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.778946] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.778987] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.779028] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.779067] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.779104] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.779114] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.779151] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.779159] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.779197] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.779235] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.779273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.779380] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.779422] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.779460] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.779501] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.779537] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.779585] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.779680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 212.779731] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.779883] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 212.779946] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.779990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.780033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.780074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.780114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.780154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.780194] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.780239] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.780281] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.780323] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.780362] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.780401] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.780447] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 212.780489] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 212.780563] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 212.782121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 212.782148] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 212.782174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 212.782201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 212.799125] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 212.799143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 212.816041] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 212.818101] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 212.818296] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 212.819413] [drm:intel_enable_pipe [i915]] enabling pipe A [ 212.819440] [drm:intel_mst_enable_dp [i915]] 1 [ 212.821832] [drm:drm_dp_update_payload_part2] payload 0 1 [ 212.823201] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.823224] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.823270] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.823816] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.824395] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 212.824422] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 212.824456] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 212.824515] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 212.824540] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 212.824612] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.824641] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.824688] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.825815] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.825836] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.836483] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.836522] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.836555] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.836597] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.836602] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.836636] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.836680] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.836719] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.836758] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.836796] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.836823] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.836829] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.836851] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.836856] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.836878] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.836900] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.836921] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.836942] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.836972] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.837006] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.837044] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.837079] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.837113] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.837159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 212.837188] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.853096] [drm:intel_mst_disable_dp [i915]] 1 [ 212.853103] [drm:drm_dp_update_payload_part1] [ 212.854665] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.854717] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.854830] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.855522] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.857698] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.857758] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.858065] [drm:drm_dp_update_payload_part1] removing payload 0 [ 212.858117] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 212.858172] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 212.858274] [drm:intel_disable_pipe [i915]] disabling pipe A [ 212.870700] [drm:intel_mst_post_disable_dp [i915]] 1 [ 212.876964] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 212.877398] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 212.877438] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 212.877475] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 212.877516] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 212.877570] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.877663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.877714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.877761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.877806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.877848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.877893] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.877939] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.877983] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.878026] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.878066] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.878106] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.878177] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.878220] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.878266] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.878702] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.878748] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.878789] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.878795] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.878798] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.878828] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.878857] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.878886] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.878914] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.878941] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.878968] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.878974] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.878999] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.879005] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.879032] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.879060] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.879085] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.879103] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.879123] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.879140] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.879158] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.879176] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.879192] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.879221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 212.879243] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.879326] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 212.879370] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.879398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.879427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.879454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.879480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.879496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.879513] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.879532] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.879549] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.879597] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.879624] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.879651] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.879681] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 212.879708] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 212.879757] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 212.881264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 212.881285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 212.881304] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 212.881323] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 212.898233] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 212.898252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 212.915151] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 212.917212] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 212.917406] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 212.918512] [drm:intel_enable_pipe [i915]] enabling pipe A [ 212.918547] [drm:intel_mst_enable_dp [i915]] 1 [ 212.920984] [drm:drm_dp_update_payload_part2] payload 0 1 [ 212.922358] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.922381] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.922424] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.922961] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.923528] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 212.923555] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 212.923602] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 212.923662] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 212.923686] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 212.923736] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.923761] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.923801] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.924280] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.924297] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.935591] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.935629] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.935658] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.935664] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.935666] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.935693] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.935719] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.935746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.935777] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.935806] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.935836] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.935841] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.935870] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.935875] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.935905] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.935934] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.935964] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.935993] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.936023] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.936051] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.936082] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.936112] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.936142] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.936184] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 212.936217] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.952205] [drm:intel_mst_disable_dp [i915]] 1 [ 212.952211] [drm:drm_dp_update_payload_part1] [ 212.953735] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 212.953769] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 212.953847] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 212.954433] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 212.956286] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 212.956321] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 212.956635] [drm:drm_dp_update_payload_part1] removing payload 0 [ 212.956669] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 212.956702] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 212.956768] [drm:intel_disable_pipe [i915]] disabling pipe A [ 212.968740] [drm:intel_mst_post_disable_dp [i915]] 1 [ 212.975100] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 212.975554] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 212.975675] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 212.975761] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 212.975822] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 212.975880] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.975918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.975954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.975988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.976021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.976055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.976088] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.976124] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.976158] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.976192] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.976223] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.976255] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.976310] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 212.976362] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 212.976419] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.976934] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 212.977003] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 212.977055] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 212.977069] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 212.977075] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 212.977126] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 212.977176] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 212.977224] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 212.977274] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 212.977307] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 212.977339] [drm:intel_dump_pipe_config [i915]] requested mode: [ 212.977346] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.977376] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 212.977382] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 212.977413] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 212.977443] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 212.977472] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 212.977501] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 212.977537] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 212.977580] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 212.977670] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 212.977719] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 212.977767] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 212.977848] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 212.977891] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 212.978005] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 212.978057] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 212.978091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 212.978124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 212.978158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 212.978189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 212.978219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 212.978251] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 212.978285] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 212.978318] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 212.978352] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 212.978382] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 212.978412] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 212.978449] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 212.978483] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 212.978541] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 212.980101] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 212.980118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 212.980133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 212.980149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 212.997064] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 212.997082] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 213.013981] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 213.016034] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 213.016229] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 213.017316] [drm:intel_enable_pipe [i915]] enabling pipe A [ 213.017344] [drm:intel_mst_enable_dp [i915]] 1 [ 213.019738] [drm:drm_dp_update_payload_part2] payload 0 1 [ 213.021110] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.021134] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.021184] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.021732] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.022310] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 213.022339] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 213.022374] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 213.022434] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 213.022460] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 213.022507] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.022534] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.022776] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.023010] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.023031] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.034432] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.034470] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.034500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.034506] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.034508] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.034536] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.034563] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.034634] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.034674] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.034911] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.034952] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.034960] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.034998] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.035006] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.035045] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.035081] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.035105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.035128] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.035155] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.035178] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.035202] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.035224] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.035246] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.035287] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 213.035316] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.051034] [drm:intel_mst_disable_dp [i915]] 1 [ 213.051040] [drm:drm_dp_update_payload_part1] [ 213.052561] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.052594] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.052681] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.053262] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.055252] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.055316] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.055637] [drm:drm_dp_update_payload_part1] removing payload 0 [ 213.055704] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 213.055781] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 213.055905] [drm:intel_disable_pipe [i915]] disabling pipe A [ 213.068314] [drm:intel_mst_post_disable_dp [i915]] 1 [ 213.074297] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 213.074809] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 213.074850] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 213.074883] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 213.074920] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 213.074969] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.075002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.075033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.075063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.075091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.075119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.075149] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.075180] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.075210] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.075240] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.075267] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.075293] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.075340] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.075370] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.075402] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.075736] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.075780] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.075813] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.075821] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.075825] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.075858] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.075896] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.075934] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.075970] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.076004] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.076038] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.076045] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.076079] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.076086] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.076120] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.076154] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.076184] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.076214] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.076253] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.076283] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.076314] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.076343] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.076373] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.076428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 213.076466] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.076605] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 213.076660] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.076697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.076732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.076766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.076799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.076833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.076865] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.076900] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.076936] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.076974] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.077005] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.077035] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.077075] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 213.077111] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 213.077171] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 213.078712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 213.078740] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 213.078763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 213.078788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 213.095654] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 213.095673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 213.112585] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 213.114661] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 213.114860] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 213.116048] [drm:intel_enable_pipe [i915]] enabling pipe A [ 213.116075] [drm:intel_mst_enable_dp [i915]] 1 [ 213.118479] [drm:drm_dp_update_payload_part2] payload 0 1 [ 213.119826] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.119848] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.119909] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.120454] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.121032] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 213.121058] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 213.121090] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 213.121181] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 213.121219] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 213.121266] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.121292] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.121333] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.121749] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.121770] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.133114] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.133146] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.133170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.133175] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.133177] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.133201] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.133224] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.133245] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.133266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.133287] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.133306] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.133311] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.133330] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.133334] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.133353] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.133371] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.133390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.133408] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.133430] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.133449] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.133469] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.133488] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.133506] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.133539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 213.133603] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.149747] [drm:intel_mst_disable_dp [i915]] 1 [ 213.149753] [drm:drm_dp_update_payload_part1] [ 213.151281] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.151321] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.151401] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.152038] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.153911] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.153957] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.154267] [drm:drm_dp_update_payload_part1] removing payload 0 [ 213.154311] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 213.154356] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 213.154420] [drm:intel_disable_pipe [i915]] disabling pipe A [ 213.166777] [drm:intel_mst_post_disable_dp [i915]] 1 [ 213.173560] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 213.173953] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 213.173979] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 213.174000] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 213.174024] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 213.174062] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.174087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.174111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.174135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.174159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.174183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.174206] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.174232] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.174257] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.174282] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.174305] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.174328] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.174367] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.174392] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.174418] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.174957] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.175000] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.175034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.175041] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.175045] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.175079] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.175103] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.175123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.175143] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.175162] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.175180] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.175184] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.175202] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.175206] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.175224] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.175241] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.175258] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.175275] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.175296] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.175313] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.175332] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.175349] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.175366] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.175396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 213.175419] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.175487] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 213.175520] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.175539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.175589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.175621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.175651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.175680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.175710] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.175741] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.175771] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.175802] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.175831] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.175858] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.175890] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 213.175920] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 213.175971] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 213.177479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 213.177501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 213.177520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 213.177540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 213.194482] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 213.194501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 213.211403] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 213.213473] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 213.213672] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 213.214834] [drm:intel_enable_pipe [i915]] enabling pipe A [ 213.214862] [drm:intel_mst_enable_dp [i915]] 1 [ 213.217256] [drm:drm_dp_update_payload_part2] payload 0 1 [ 213.218631] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.218653] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.218708] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.219244] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.219822] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 213.219848] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 213.219879] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 213.219934] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 213.219957] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 213.220017] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.220042] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.220082] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.220503] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.220519] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.231950] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.231984] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.232009] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.232014] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.232016] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.232038] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.232060] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.232081] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.232102] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.232121] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.232139] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.232144] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.232162] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.232165] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.232184] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.232203] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.232220] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.232238] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.232258] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.232276] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.232295] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.232313] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.232330] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.232361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 213.232385] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.248638] [drm:intel_mst_disable_dp [i915]] 1 [ 213.248646] [drm:drm_dp_update_payload_part1] [ 213.250192] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.250234] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.250301] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.250913] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.252765] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.252810] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.253112] [drm:drm_dp_update_payload_part1] removing payload 0 [ 213.253155] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 213.253196] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 213.253257] [drm:intel_disable_pipe [i915]] disabling pipe A [ 213.266792] [drm:intel_mst_post_disable_dp [i915]] 1 [ 213.272582] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 213.273017] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 213.273058] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 213.273089] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 213.273126] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 213.273175] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.273208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.273238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.273268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.273296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.273323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.273352] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.273383] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.273413] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.273442] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.273469] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.273495] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.273544] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.273629] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.273682] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.274076] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.274116] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.274149] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.274155] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.274158] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.274189] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.274220] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.274250] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.274279] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.274307] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.274333] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.274340] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.274366] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.274371] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.274399] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.274425] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.274451] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.274476] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.274507] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.274533] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.274566] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.274655] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.274701] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.274772] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 213.274826] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.274989] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 213.275061] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.275111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.275160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.275203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.275235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.275264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.275295] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.275327] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.275358] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.275389] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.275418] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.275448] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.275482] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 213.275515] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 213.275569] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 213.277175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 213.277209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 213.277239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 213.277271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 213.294243] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 213.294262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 213.311164] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 213.313224] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 213.313420] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 213.314573] [drm:intel_enable_pipe [i915]] enabling pipe A [ 213.314600] [drm:intel_mst_enable_dp [i915]] 1 [ 213.317005] [drm:drm_dp_update_payload_part2] payload 0 1 [ 213.318376] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.318398] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.318452] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.318999] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.319584] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 213.319611] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 213.319646] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 213.319705] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 213.319732] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 213.319792] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.319819] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.319861] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.320315] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.320345] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.331732] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.331766] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.331794] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.331799] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.331801] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.331826] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.331851] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.331875] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.331897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.331919] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.331940] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.331945] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.331965] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.331969] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.331990] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.332011] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.332031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.332058] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.332096] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.332126] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.332148] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.332168] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.332187] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.332223] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 213.332250] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.348340] [drm:intel_mst_disable_dp [i915]] 1 [ 213.348346] [drm:drm_dp_update_payload_part1] [ 213.349880] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.349913] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.349990] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.350560] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.352546] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.352640] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.352914] [drm:drm_dp_update_payload_part1] removing payload 0 [ 213.352963] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 213.353013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 213.353107] [drm:intel_disable_pipe [i915]] disabling pipe A [ 213.365490] [drm:intel_mst_post_disable_dp [i915]] 1 [ 213.372407] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 213.372894] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 213.372951] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 213.372994] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 213.373041] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 213.373101] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.373143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.373185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.373227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.373268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.373310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.373351] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.373395] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.373438] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.373481] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.373522] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.373562] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.373723] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.373752] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.373783] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.374006] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.374029] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.374047] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.374051] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.374053] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.374070] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.374088] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.374104] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.374121] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.374136] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.374151] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.374155] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.374170] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.374173] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.374188] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.374203] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.374218] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.374233] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.374250] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.374265] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.374280] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.374294] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.374309] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.374334] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 213.374353] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.374402] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 213.374431] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.374448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.374463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.374478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.374493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.374508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.374523] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.374539] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.374581] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.374607] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.374631] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.374655] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.374683] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 213.374710] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 213.374754] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 213.376246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 213.376271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 213.376293] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 213.376319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 213.393287] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 213.393305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 213.410206] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 213.412277] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 213.412474] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 213.413579] [drm:intel_enable_pipe [i915]] enabling pipe A [ 213.413607] [drm:intel_mst_enable_dp [i915]] 1 [ 213.415984] [drm:drm_dp_update_payload_part2] payload 0 1 [ 213.417352] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.417374] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.417422] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.417965] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.418550] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 213.418609] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 213.418650] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 213.418719] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 213.418751] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 213.418801] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.418829] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.418881] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.419294] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.419316] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.430636] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.430665] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.430687] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.430691] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.430693] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.430713] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.430734] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.430753] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.430773] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.430790] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.430807] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.430811] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.430828] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.430832] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.430849] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.430866] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.430882] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.430899] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.430918] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.430935] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.430952] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.430969] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.430985] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.431012] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 213.431034] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.447260] [drm:intel_mst_disable_dp [i915]] 1 [ 213.447267] [drm:drm_dp_update_payload_part1] [ 213.448817] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.448865] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.448965] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.449769] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.451723] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.451778] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.452076] [drm:drm_dp_update_payload_part1] removing payload 0 [ 213.452123] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 213.452170] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 213.452258] [drm:intel_disable_pipe [i915]] disabling pipe A [ 213.463814] [drm:intel_mst_post_disable_dp [i915]] 1 [ 213.471186] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 213.471781] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 213.471809] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 213.471836] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 213.471864] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 213.471903] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.471929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.471954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.471979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.472004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.472029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.472054] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.472080] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.472106] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.472133] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.472157] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.472182] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.472221] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.472247] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.472275] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.472469] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.472499] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.472524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.472529] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.472531] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.472556] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.472613] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.472741] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.472775] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.472807] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.472834] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.472839] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.472863] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.472870] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.472901] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.472921] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.472940] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.472958] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.472980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.472999] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.473031] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.473061] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.473091] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.473128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 213.473153] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.473220] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 213.473262] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.473282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.473301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.473320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.473346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.473375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.473404] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.473425] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.473446] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.473476] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.473505] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.473533] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.473565] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 213.473614] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 213.473663] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 213.475304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 213.475327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 213.475348] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 213.475369] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 213.492233] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 213.492250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 213.509153] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 213.511206] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 213.511401] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 213.512491] [drm:intel_enable_pipe [i915]] enabling pipe A [ 213.512519] [drm:intel_mst_enable_dp [i915]] 1 [ 213.514930] [drm:drm_dp_update_payload_part2] payload 0 1 [ 213.516298] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.516320] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.516375] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.516934] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.517503] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 213.517529] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 213.517591] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 213.517649] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 213.517688] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 213.517739] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.517765] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.517808] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.518956] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.518975] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.529576] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.529606] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.529629] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.529633] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.529635] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.529657] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.529678] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.529698] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.529717] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.529735] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.529753] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.529757] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.529775] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.529778] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.529796] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.529814] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.529831] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.529848] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.529868] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.529885] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.529904] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.529921] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.529937] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.529967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 213.529989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.546221] [drm:intel_mst_disable_dp [i915]] 1 [ 213.546228] [drm:drm_dp_update_payload_part1] [ 213.547783] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.547834] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.547929] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.548577] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.550540] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.550625] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.550900] [drm:drm_dp_update_payload_part1] removing payload 0 [ 213.550945] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 213.550992] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 213.551085] [drm:intel_disable_pipe [i915]] disabling pipe A [ 213.563492] [drm:intel_mst_post_disable_dp [i915]] 1 [ 213.569843] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 213.570277] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 213.570317] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 213.570349] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 213.570386] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 213.570439] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.570476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.570513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.570550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.570636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.570800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.570833] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.570866] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.570897] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.570926] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.570953] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.570979] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.571027] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.571057] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.571088] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.571461] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.571520] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.571560] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.571632] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.571637] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.571684] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.571731] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.571776] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.571821] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.571864] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.571904] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.571914] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.571952] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.571961] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.572001] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.572041] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.572080] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.572119] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.572164] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.572204] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.572245] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.572285] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.572324] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.572393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 213.572441] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.572608] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 213.572658] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.572692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.572726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.572756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.572785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.572815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.572846] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.572878] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.572908] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.572938] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.572966] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.572993] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.573027] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 213.573057] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 213.573110] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 213.574599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 213.574616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 213.574631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 213.574646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 213.591574] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 213.591591] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 213.608486] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 213.610554] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 213.610764] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 213.611954] [drm:intel_enable_pipe [i915]] enabling pipe A [ 213.611979] [drm:intel_mst_enable_dp [i915]] 1 [ 213.614372] [drm:drm_dp_update_payload_part2] payload 0 1 [ 213.615741] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.615762] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.615815] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.616352] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.616923] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 213.616956] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 213.616984] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 213.617036] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 213.617057] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 213.617099] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.617122] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.617159] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.618219] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.618237] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.629017] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.629047] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.629071] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.629076] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.629078] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.629100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.629122] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.629143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.629164] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.629182] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.629201] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.629205] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.629223] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.629227] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.629246] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.629264] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.629282] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.629299] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.629320] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.629339] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.629358] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.629375] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.629393] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.629423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 213.629446] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.645643] [drm:intel_mst_disable_dp [i915]] 1 [ 213.645650] [drm:drm_dp_update_payload_part1] [ 213.647195] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.647239] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.647305] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.647925] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.649816] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.649866] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.650163] [drm:drm_dp_update_payload_part1] removing payload 0 [ 213.650208] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 213.650250] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 213.650315] [drm:intel_disable_pipe [i915]] disabling pipe A [ 213.664057] [drm:intel_mst_post_disable_dp [i915]] 1 [ 213.669485] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 213.669975] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 213.670022] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 213.670058] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 213.670100] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 213.670154] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.670191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.670226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.670259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.670291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.670323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.670356] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.670391] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.670424] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.670457] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.670487] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.670517] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.670644] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.670695] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.670755] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.671181] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.671227] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.671262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.671270] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.671273] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.671308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.671344] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.671377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.671409] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.671440] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.671470] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.671478] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.671507] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.671513] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.671543] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.671637] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.671679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.671719] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.671766] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.671806] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.671848] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.671889] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.671930] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.672000] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 213.672048] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.672204] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 213.672271] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.672303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.672332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.672360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.672387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.672419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.672458] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.672497] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.672536] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.672612] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.672656] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.672699] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.672746] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 213.672789] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 213.672866] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 213.674497] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 213.674548] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 213.674667] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 213.674717] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 213.691685] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 213.691703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 213.708602] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 213.710652] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 213.710850] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 213.712063] [drm:intel_enable_pipe [i915]] enabling pipe A [ 213.712088] [drm:intel_mst_enable_dp [i915]] 1 [ 213.714493] [drm:drm_dp_update_payload_part2] payload 0 1 [ 213.715869] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.715894] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.715950] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.716495] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.717083] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 213.717110] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 213.717143] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 213.717202] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 213.717229] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 213.717282] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.717310] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.717353] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.717792] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.717823] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.729133] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.729161] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.729183] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.729187] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.729189] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.729209] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.729230] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.729249] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.729267] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.729284] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.729301] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.729305] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.729322] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.729325] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.729342] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.729364] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.729387] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.729409] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.729432] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.729454] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.729477] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.729500] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.729523] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.729561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 213.729634] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.745707] [drm:intel_mst_disable_dp [i915]] 1 [ 213.745712] [drm:drm_dp_update_payload_part1] [ 213.747246] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.747287] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.747372] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.748013] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.749957] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.750004] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.750301] [drm:drm_dp_update_payload_part1] removing payload 0 [ 213.750339] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 213.750379] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 213.750439] [drm:intel_disable_pipe [i915]] disabling pipe A [ 213.762787] [drm:intel_mst_post_disable_dp [i915]] 1 [ 213.769063] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 213.769489] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 213.769529] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 213.769568] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 213.769667] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 213.769735] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.769781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.769825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.769868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.769911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.769951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.769994] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.770039] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.770083] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.770126] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.770167] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.770207] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.770278] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.770321] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.770368] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.770711] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.770771] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.770820] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.770830] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.770835] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.770879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.770911] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.770941] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.770970] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.771006] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.771042] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.771049] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.771085] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.771090] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.771128] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.771163] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.771199] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.771235] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.771272] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.771306] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.771344] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.771380] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.771416] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.771469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 213.771509] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.771683] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 213.771752] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.771799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.771843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.771888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.771930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.771970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.772014] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.772059] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.772103] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.772147] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.772187] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.772227] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.772273] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 213.772317] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 213.772391] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 213.773908] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 213.773930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 213.773948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 213.773967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 213.790889] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 213.790909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 213.807808] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 213.809878] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 213.810077] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 213.811207] [drm:intel_enable_pipe [i915]] enabling pipe A [ 213.811233] [drm:intel_mst_enable_dp [i915]] 1 [ 213.813626] [drm:drm_dp_update_payload_part2] payload 0 1 [ 213.814999] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.815021] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.815067] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.815606] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.816170] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 213.816193] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 213.816221] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 213.816273] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 213.816294] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 213.816347] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.816369] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.816407] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.816889] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.816913] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.828354] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.828388] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.828415] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.828421] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.828423] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.828448] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.828473] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.828497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.828521] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.828543] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.828620] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.828631] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.828664] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.828671] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.828703] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.828736] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.828769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.828793] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.828819] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.828840] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.828863] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.828884] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.828904] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.828941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 213.828968] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.844999] [drm:intel_mst_disable_dp [i915]] 1 [ 213.845006] [drm:drm_dp_update_payload_part1] [ 213.846556] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.846614] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.846717] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.847393] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.849452] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.849514] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.850283] [drm:drm_dp_update_payload_part1] removing payload 0 [ 213.850338] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 213.850392] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 213.850471] [drm:intel_disable_pipe [i915]] disabling pipe A [ 213.861778] [drm:intel_mst_post_disable_dp [i915]] 1 [ 213.868847] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 213.869281] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 213.869321] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 213.869353] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 213.869390] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 213.869439] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.869471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.869502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.869532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.869624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.869669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.869714] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.869764] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.869812] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.869860] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.869903] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.869946] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.870020] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.870418] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.870455] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.870770] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.870808] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.870840] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.870847] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.870850] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.870882] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.870914] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.870945] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.870976] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.871006] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.871037] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.871043] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.871073] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.871078] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.871109] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.871140] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.871171] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.871201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.871232] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.871261] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.871293] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.871324] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.871355] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.871401] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 213.871435] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.871530] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 213.871620] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.871666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.871708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.871748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.871785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.871824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.871864] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.871906] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.871944] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.871985] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.872022] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.872058] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.872102] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 213.872142] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 213.872209] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 213.874112] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 213.874141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 213.874167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 213.874193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 213.891132] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 213.891149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 213.908048] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 213.910117] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 213.910315] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 213.911392] [drm:intel_enable_pipe [i915]] enabling pipe A [ 213.911418] [drm:intel_mst_enable_dp [i915]] 1 [ 213.913814] [drm:drm_dp_update_payload_part2] payload 0 1 [ 213.915182] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.915203] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.915257] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.915794] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.916365] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 213.916388] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 213.916416] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 213.916467] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 213.916489] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 213.916531] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.916583] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.916624] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.917090] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.917108] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.928495] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.928535] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.928606] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.928620] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.928624] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.928665] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.928874] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.928913] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.928948] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.928985] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.929020] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.929029] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.929063] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.929071] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.929104] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.929136] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.929170] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.929205] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.929244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.929277] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.929310] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.929345] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.929380] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.929438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 213.929481] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.945112] [drm:intel_mst_disable_dp [i915]] 1 [ 213.945119] [drm:drm_dp_update_payload_part1] [ 213.946635] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 213.946674] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 213.946776] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 213.947391] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 213.949301] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 213.949346] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 213.949949] [drm:drm_dp_update_payload_part1] removing payload 0 [ 213.949989] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 213.950034] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 213.950099] [drm:intel_disable_pipe [i915]] disabling pipe A [ 213.961701] [drm:intel_mst_post_disable_dp [i915]] 1 [ 213.968787] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 213.969207] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 213.969243] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 213.969271] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 213.969305] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 213.969349] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.969379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.969406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.969432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.969457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.969481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.969507] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.969535] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.969621] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.969663] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.969702] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.969743] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.969809] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 213.969867] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 213.970245] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.970645] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 213.970684] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 213.970728] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 213.970740] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 213.970746] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 213.970790] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 213.970934] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 213.970962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 213.970989] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 213.971014] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 213.971038] [drm:intel_dump_pipe_config [i915]] requested mode: [ 213.971044] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.971068] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 213.971073] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 213.971097] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 213.971121] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 213.971144] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 213.971166] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 213.971195] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 213.971228] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 213.971262] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 213.971295] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 213.971327] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 213.971376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 213.971413] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 213.971512] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 213.971603] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 213.971649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 213.971689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 213.971727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 213.971766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 213.971803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 213.971841] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 213.971882] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 213.971925] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 213.971967] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 213.972010] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 213.972053] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 213.972100] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 213.972144] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 213.972216] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 213.973766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 213.973787] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 213.973805] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 213.973825] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 213.990744] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 213.990762] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 214.007661] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 214.009721] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 214.009917] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 214.011034] [drm:intel_enable_pipe [i915]] enabling pipe A [ 214.011059] [drm:intel_mst_enable_dp [i915]] 1 [ 214.013446] [drm:drm_dp_update_payload_part2] payload 0 1 [ 214.014816] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.014837] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.014876] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.015408] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.015990] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 214.016013] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 214.016041] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 214.016091] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 214.016112] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 214.016150] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.016173] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.016211] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.016690] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.016715] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.028128] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.028165] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.028195] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.028201] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.028204] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.028234] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.028265] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.028294] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.028324] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.028353] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.028382] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.028387] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.028416] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.028420] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.028450] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.028479] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.028508] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.028537] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.028627] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.028675] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.028718] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.028756] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.028792] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.028855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 214.028899] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.044732] [drm:intel_mst_disable_dp [i915]] 1 [ 214.044741] [drm:drm_dp_update_payload_part1] [ 214.046290] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.046343] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.046452] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.047338] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.049328] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.049388] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.049695] [drm:drm_dp_update_payload_part1] removing payload 0 [ 214.049773] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 214.049848] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 214.049951] [drm:intel_disable_pipe [i915]] disabling pipe A [ 214.061813] [drm:intel_mst_post_disable_dp [i915]] 1 [ 214.068573] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 214.069024] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 214.069069] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 214.069105] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 214.069147] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 214.069202] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.069239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.069273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.069306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.069338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.069369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.069402] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.069437] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.069470] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.069503] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.069533] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.069642] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.069728] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.069778] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.069837] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.070254] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.070296] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.070330] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.070337] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.070340] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.070373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.070407] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.070438] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.070467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.070495] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.070522] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.070529] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.070578] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.070585] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.070615] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.070644] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.070673] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.070702] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.070735] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.070765] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.070796] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.070825] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.070855] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.070903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 214.070938] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.071044] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 214.071092] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.071124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.071155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.071185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.071215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.071245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.071276] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.071308] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.071340] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.071372] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.071401] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.071430] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.071464] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 214.071496] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 214.071550] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 214.073072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 214.073097] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 214.073112] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 214.073127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 214.090043] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 214.090061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 214.106973] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 214.109032] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 214.109227] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 214.110361] [drm:intel_enable_pipe [i915]] enabling pipe A [ 214.110388] [drm:intel_mst_enable_dp [i915]] 1 [ 214.112782] [drm:drm_dp_update_payload_part2] payload 0 1 [ 214.114167] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.114190] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.114243] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.114782] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.115353] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 214.115378] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 214.115409] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 214.115464] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 214.115487] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 214.115546] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.116172] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.116221] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.116238] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.116255] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.127373] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.127403] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.127426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.127431] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.127433] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.127455] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.127477] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.127498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.127518] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.127537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.127592] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.127602] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.127632] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.127640] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.127670] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.127699] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.127727] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.127755] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.127788] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.127816] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.127846] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.127873] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.127899] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.127946] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 214.127978] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.144052] [drm:intel_mst_disable_dp [i915]] 1 [ 214.144059] [drm:drm_dp_update_payload_part1] [ 214.145614] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.145662] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.145778] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.146408] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.148528] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.148619] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.148898] [drm:drm_dp_update_payload_part1] removing payload 0 [ 214.148958] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 214.149015] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 214.149100] [drm:intel_disable_pipe [i915]] disabling pipe A [ 214.160721] [drm:intel_mst_post_disable_dp [i915]] 1 [ 214.167596] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 214.168049] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 214.168095] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 214.168131] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 214.168173] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 214.168227] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.168263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.168297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.168329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.168361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.168391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.168425] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.168460] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.168493] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.168526] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.168556] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.168654] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.168743] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.168796] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.168854] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.169191] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.169234] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.169268] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.169276] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.169279] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.169313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.169347] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.169380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.169412] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.169442] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.169471] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.169478] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.169507] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.169514] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.169545] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.169639] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.169686] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.169730] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.169783] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.169829] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.169877] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.169923] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.169969] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.170049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 214.170103] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.170278] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 214.170356] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.170410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.170457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.170489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.170521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.170561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.170618] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.170654] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.170687] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.170730] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.170753] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.170776] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.170803] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 214.170824] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 214.170852] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 214.172314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 214.172330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 214.172345] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 214.172359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 214.189216] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 214.189233] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 214.206133] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 214.208191] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 214.208386] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 214.209476] [drm:intel_enable_pipe [i915]] enabling pipe A [ 214.209503] [drm:intel_mst_enable_dp [i915]] 1 [ 214.211914] [drm:drm_dp_update_payload_part2] payload 0 1 [ 214.213284] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.213306] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.213346] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.213910] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.214478] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 214.214504] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 214.214536] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 214.214723] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 214.214751] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 214.214799] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.214837] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.214879] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.215182] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.215200] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.226622] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.226659] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.226687] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.226692] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.226694] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.226720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.226747] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.226772] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.226795] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.226818] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.226840] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.226845] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.226866] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.226871] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.226892] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.226914] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.226935] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.226955] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.226981] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.227002] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.227025] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.227046] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.227067] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.227102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 214.227130] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.243172] [drm:intel_mst_disable_dp [i915]] 1 [ 214.243180] [drm:drm_dp_update_payload_part1] [ 214.244716] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.244756] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.244855] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.245452] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.247459] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.247510] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.247868] [drm:drm_dp_update_payload_part1] removing payload 0 [ 214.247937] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 214.247996] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 214.248087] [drm:intel_disable_pipe [i915]] disabling pipe A [ 214.259796] [drm:intel_mst_post_disable_dp [i915]] 1 [ 214.267221] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 214.267670] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 214.267725] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 214.267771] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 214.267823] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 214.267888] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.267920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.267950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.267977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.268003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.268029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.268057] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.268088] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.268116] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.268143] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.268168] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.268193] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.268239] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.268267] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.268296] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.268594] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.268650] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.268691] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.268704] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.268709] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.268749] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.268792] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.268837] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.268879] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.268921] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.268961] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.268971] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.269010] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.269019] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.269061] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.269093] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.269119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.269144] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.269173] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.269198] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.269226] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.269251] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.269276] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.269318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 214.269351] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.269433] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 214.269476] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.269505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.269532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.269590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.269631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.269669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.269710] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.269753] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.269795] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.269837] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.269873] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.269910] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.269954] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 214.269995] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 214.270067] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 214.271585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 214.271604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 214.271621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 214.271638] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 214.288490] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 214.288506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 214.305336] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 214.307405] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 214.307604] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 214.308810] [drm:intel_enable_pipe [i915]] enabling pipe A [ 214.308835] [drm:intel_mst_enable_dp [i915]] 1 [ 214.311232] [drm:drm_dp_update_payload_part2] payload 0 1 [ 214.312587] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.312608] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.312662] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.313207] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.313774] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 214.313796] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 214.313824] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 214.313876] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 214.313898] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 214.313936] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.313959] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.313996] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.314463] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.314479] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.325815] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.325840] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.325860] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.325863] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.325865] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.325883] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.325901] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.325918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.325934] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.325949] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.325964] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.325968] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.325982] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.325985] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.326000] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.326014] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.326028] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.326042] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.326059] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.326074] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.326089] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.326103] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.326117] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.326141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 214.326160] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.342475] [drm:intel_mst_disable_dp [i915]] 1 [ 214.342482] [drm:drm_dp_update_payload_part1] [ 214.344012] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.344060] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.344168] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.344821] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.346780] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.346838] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.347127] [drm:drm_dp_update_payload_part1] removing payload 0 [ 214.347174] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 214.347220] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 214.347293] [drm:intel_disable_pipe [i915]] disabling pipe A [ 214.360888] [drm:intel_mst_post_disable_dp [i915]] 1 [ 214.365853] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 214.366312] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 214.366361] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 214.366398] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 214.366443] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 214.366500] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.366539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.366858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.366909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.366959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.367007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.367042] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.367080] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.367133] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.367187] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.367237] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.367286] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.367370] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.367424] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.367482] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.367962] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.368026] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.368080] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.368091] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.368096] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.368133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.368168] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.368206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.368246] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.368285] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.368323] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.368330] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.368368] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.368374] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.368414] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.368453] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.368492] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.368529] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.368613] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.368665] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.368715] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.368762] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.368809] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.368887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 214.368939] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.369491] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 214.369566] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.369656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.369705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.369752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.369795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.369839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.369888] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.370130] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.370164] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.370195] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.370225] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.370253] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.370288] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 214.370320] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 214.370373] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 214.372099] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 214.372118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 214.372134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 214.372151] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 214.389065] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 214.389082] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 214.405980] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 214.408048] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 214.408246] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 214.409337] [drm:intel_enable_pipe [i915]] enabling pipe A [ 214.409362] [drm:intel_mst_enable_dp [i915]] 1 [ 214.411755] [drm:drm_dp_update_payload_part2] payload 0 1 [ 214.413125] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.413146] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.413200] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.413750] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.414326] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 214.414354] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 214.414389] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 214.414450] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 214.414477] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 214.414547] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.414598] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.414782] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.415067] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.415089] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.426460] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.426501] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.426532] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.426697] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.426700] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.426733] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.426765] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.426794] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.426838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.426878] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.426918] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.426926] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.426965] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.426971] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.426997] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.427020] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.427044] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.427068] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.427095] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.427118] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.427143] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.427167] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.427189] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.427232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 214.427263] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.443042] [drm:intel_mst_disable_dp [i915]] 1 [ 214.443050] [drm:drm_dp_update_payload_part1] [ 214.444611] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.444657] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.444740] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.445472] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.447415] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.447465] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.447970] [drm:drm_dp_update_payload_part1] removing payload 0 [ 214.448042] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 214.448115] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 214.448232] [drm:intel_disable_pipe [i915]] disabling pipe A [ 214.460629] [drm:intel_mst_post_disable_dp [i915]] 1 [ 214.466518] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 214.467090] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 214.467128] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 214.467158] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 214.467193] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 214.467241] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.467272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.467301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.467329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.467357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.467383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.467411] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.467441] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.467469] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.467496] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.467521] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.467566] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.467669] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.467708] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.467751] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.468106] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.468157] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.468196] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.468205] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.468209] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.468250] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.468291] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.468331] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.468367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.468404] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.468442] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.468450] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.468486] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.468493] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.468527] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.468587] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.468622] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.468657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.468696] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.468730] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.468766] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.468801] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.468836] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.468896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 214.468937] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.469068] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 214.469125] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.469162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.469202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.469240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.469278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.469314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.469349] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.469391] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.469431] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.469471] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.469504] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.469537] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.469605] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 214.469643] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 214.469710] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 214.471315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 214.471356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 214.471397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 214.471438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 214.488444] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 214.488463] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 214.505365] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 214.507425] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 214.507621] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 214.508812] [drm:intel_enable_pipe [i915]] enabling pipe A [ 214.508837] [drm:intel_mst_enable_dp [i915]] 1 [ 214.511228] [drm:drm_dp_update_payload_part2] payload 0 1 [ 214.512574] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.512595] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.512648] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.513191] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.513762] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 214.513786] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 214.513815] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 214.513867] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 214.513889] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 214.513944] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.513968] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.514006] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.514447] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.514471] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.525933] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.525969] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.525998] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.526003] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.526005] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.526032] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.526058] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.526083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.526108] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.526131] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.526153] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.526158] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.526180] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.526185] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.526206] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.526228] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.526250] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.526271] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.526296] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.526318] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.526341] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.526362] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.526383] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.526419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 214.526446] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.542504] [drm:intel_mst_disable_dp [i915]] 1 [ 214.542511] [drm:drm_dp_update_payload_part1] [ 214.544212] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.544250] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.544320] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.545039] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.546994] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.547047] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.547350] [drm:drm_dp_update_payload_part1] removing payload 0 [ 214.547403] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 214.547450] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 214.547522] [drm:intel_disable_pipe [i915]] disabling pipe A [ 214.559648] [drm:intel_mst_post_disable_dp [i915]] 1 [ 214.566793] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 214.567269] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 214.567320] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 214.567361] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 214.567409] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 214.567470] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.567512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.567551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.567659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.568009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.568067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.568101] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.568131] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.568151] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.568171] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.568188] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.568206] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.568238] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.568258] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.568279] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.568463] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.568488] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.568507] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.568512] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.568514] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.568534] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.568592] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.568862] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.568895] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.568934] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.568962] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.568974] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.569002] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.569008] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.569037] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.569065] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.569091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.569119] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.569140] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.569158] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.569177] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.569194] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.569211] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.569242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 214.569265] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.569334] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 214.569367] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.569386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.569405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.569423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.569440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.569457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.569475] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.569494] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.569512] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.569531] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.569585] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.570041] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.570079] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 214.570116] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 214.570152] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 214.571630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 214.571648] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 214.571663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 214.571679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 214.588578] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 214.588596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 214.605495] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 214.607566] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 214.607765] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 214.608986] [drm:intel_enable_pipe [i915]] enabling pipe A [ 214.609013] [drm:intel_mst_enable_dp [i915]] 1 [ 214.611404] [drm:drm_dp_update_payload_part2] payload 0 1 [ 214.612780] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.612801] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.612854] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.613391] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.614015] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 214.614040] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 214.614071] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 214.614126] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 214.614153] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 214.614219] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.614245] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.614285] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.614714] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.614731] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.626050] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.626087] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.626116] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.626121] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.626123] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.626151] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.626178] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.626203] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.626227] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.626250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.626272] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.626278] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.626300] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.626304] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.626327] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.626349] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.626371] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.626392] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.626418] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.626440] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.626463] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.626485] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.626506] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.626550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 214.626618] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.642666] [drm:intel_mst_disable_dp [i915]] 1 [ 214.642673] [drm:drm_dp_update_payload_part1] [ 214.644212] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.644252] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.644320] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.644997] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.646974] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.647028] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.647338] [drm:drm_dp_update_payload_part1] removing payload 0 [ 214.647382] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 214.647430] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 214.647522] [drm:intel_disable_pipe [i915]] disabling pipe A [ 214.660218] [drm:intel_mst_post_disable_dp [i915]] 1 [ 214.666564] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 214.666991] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 214.667029] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 214.667059] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 214.667094] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 214.667141] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.667172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.667201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.667228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.667255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.667281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.667309] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.667338] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.667366] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.667393] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.667419] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.667444] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.667489] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.667517] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.667588] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.668184] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.668232] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.668273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.668281] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.668285] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.668323] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.668361] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.668398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.668433] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.668455] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.668475] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.668481] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.668501] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.668505] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.668525] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.668604] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.668928] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.668963] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.669000] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.669034] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.669071] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.669105] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.669138] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.669179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 214.669207] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.669286] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 214.669324] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.669348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.669370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.669392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.669412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.669433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.669454] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.669477] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.669499] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.669521] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.669546] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.669602] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.670010] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 214.670049] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 214.670110] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 214.671635] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 214.671662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 214.671685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 214.671708] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 214.688635] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 214.688653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 214.705566] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 214.707635] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 214.707831] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 214.709033] [drm:intel_enable_pipe [i915]] enabling pipe A [ 214.709060] [drm:intel_mst_enable_dp [i915]] 1 [ 214.711445] [drm:drm_dp_update_payload_part2] payload 0 1 [ 214.712819] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.712843] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.712896] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.713436] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.714095] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 214.714119] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 214.714150] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 214.714207] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 214.714229] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 214.714272] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.714294] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.714332] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.714789] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.714862] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.726101] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.726128] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.726150] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.726154] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.726155] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.726178] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.726199] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.726221] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.726242] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.726263] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.726284] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.726288] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.726308] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.726311] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.726333] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.726354] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.726375] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.726395] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.726417] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.726437] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.726459] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.726480] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.726501] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.726532] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 214.726583] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.742746] [drm:intel_mst_disable_dp [i915]] 1 [ 214.742754] [drm:drm_dp_update_payload_part1] [ 214.744298] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.744338] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.744419] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.745052] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.747011] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.747058] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.747379] [drm:drm_dp_update_payload_part1] removing payload 0 [ 214.747424] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 214.747472] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 214.747554] [drm:intel_disable_pipe [i915]] disabling pipe A [ 214.759739] [drm:intel_mst_post_disable_dp [i915]] 1 [ 214.766599] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 214.767006] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 214.767037] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 214.767062] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 214.767090] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 214.767129] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.767154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.767177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.767199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.767221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.767242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.767264] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.767288] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.767311] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.767333] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.767354] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.767374] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.767411] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.767434] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.767459] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.767770] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.767813] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.767847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.767855] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.767859] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.767894] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.767928] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.767961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.767994] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.768025] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.768055] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.768063] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.768092] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.768099] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.768129] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.768161] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.768191] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.768221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.768255] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.768285] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.768318] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.768348] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.768378] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.768429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 214.768466] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.768606] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 214.768661] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.768697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.768732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.768769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.768803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.768836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.768871] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.768908] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.768944] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.768969] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.768990] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.769010] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.769035] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 214.769058] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 214.769097] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 214.770636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 214.770674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 214.770708] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 214.770743] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 214.787695] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 214.787713] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 214.804584] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 214.806594] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 214.806791] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 214.807977] [drm:intel_enable_pipe [i915]] enabling pipe A [ 214.808003] [drm:intel_mst_enable_dp [i915]] 1 [ 214.809923] [drm:drm_dp_update_payload_part2] payload 0 1 [ 214.811306] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.811330] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.811380] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.811929] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.812499] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 214.812525] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 214.812584] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 214.812644] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 214.812672] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 214.812719] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.812747] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.812793] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.813227] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.813257] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.825013] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.825052] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.825081] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.825087] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.825089] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.825116] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.825144] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.825170] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.825195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.825219] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.825241] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.825247] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.825269] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.825273] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.825296] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.825319] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.825340] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.825362] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.825388] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.825410] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.825434] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.825455] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.825477] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.825514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 214.825543] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.841656] [drm:intel_mst_disable_dp [i915]] 1 [ 214.841664] [drm:drm_dp_update_payload_part1] [ 214.843216] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.843270] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.843385] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.844273] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.846279] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.846343] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.846664] [drm:drm_dp_update_payload_part1] removing payload 0 [ 214.846736] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 214.846816] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 214.846926] [drm:intel_disable_pipe [i915]] disabling pipe A [ 214.859245] [drm:intel_mst_post_disable_dp [i915]] 1 [ 214.865356] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 214.865835] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 214.865872] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 214.865901] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 214.865935] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 214.865981] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.866010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.866037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.866063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.866088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.866112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.866138] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.866166] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.866193] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.866219] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.866243] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.866265] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.866308] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.866333] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.866362] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.866696] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.866745] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.866786] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.866796] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.866801] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.866841] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.866880] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.866917] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.866955] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.866991] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.867026] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.867035] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.867069] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.867078] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.867114] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.867149] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.867185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.867221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.867260] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.867363] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.867400] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.867436] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.867471] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.867531] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 214.867618] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.867941] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 214.867988] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.868030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.868079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.868122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.868164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.868206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.868249] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.868292] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.868321] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.868362] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.868387] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.868412] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.868443] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 214.868471] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 214.868518] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 214.870419] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 214.870451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 214.870479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 214.870507] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 214.887459] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 214.887478] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 214.904352] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 214.906388] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 214.906585] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 214.907805] [drm:intel_enable_pipe [i915]] enabling pipe A [ 214.907829] [drm:intel_mst_enable_dp [i915]] 1 [ 214.910205] [drm:drm_dp_update_payload_part2] payload 0 1 [ 214.911569] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.911591] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.911654] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.912182] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.912864] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 214.912888] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 214.912922] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 214.912979] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 214.913001] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 214.913044] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.913069] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.913110] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.913440] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.913457] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.924880] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.924913] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.924938] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.924943] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.924945] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.924968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.924993] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.925015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.925037] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.925057] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.925077] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.925082] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.925101] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.925105] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.925125] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.925144] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.925164] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.925183] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.925205] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.925225] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.925245] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.925264] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.925283] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.925315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 214.925345] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.941565] [drm:intel_mst_disable_dp [i915]] 1 [ 214.941601] [drm:drm_dp_update_payload_part1] [ 214.943160] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 214.943208] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 214.943278] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 214.943906] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 214.945861] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 214.945913] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 214.946218] [drm:drm_dp_update_payload_part1] removing payload 0 [ 214.946260] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 214.946304] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 214.946370] [drm:intel_disable_pipe [i915]] disabling pipe A [ 214.959752] [drm:intel_mst_post_disable_dp [i915]] 1 [ 214.965078] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 214.965523] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 214.965666] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 214.965723] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 214.965786] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 214.965845] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.965884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.965921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.965955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.965987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.966019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.966054] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.966090] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.966127] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.966161] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.966192] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.966223] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.966280] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 214.966333] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 214.966382] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.966818] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 214.966885] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 214.966941] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 214.966952] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 214.966958] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 214.967012] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 214.967066] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 214.967114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 214.967150] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 214.967181] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 214.967212] [drm:intel_dump_pipe_config [i915]] requested mode: [ 214.967219] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.967256] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 214.967265] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 214.967296] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 214.967326] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 214.967356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 214.967385] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 214.967420] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 214.967450] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 214.967482] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 214.967511] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 214.967540] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 214.967654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 214.967713] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 214.967887] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 214.967963] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 214.968017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 214.968068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 214.968104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 214.968135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 214.968166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 214.968198] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 214.968233] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 214.968266] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 214.968300] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 214.968330] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 214.968359] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 214.968397] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 214.968431] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 214.968489] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 214.970138] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 214.970177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 214.970211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 214.970253] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 214.987199] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 214.987217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 215.004090] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 215.006150] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 215.006349] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 215.007462] [drm:intel_enable_pipe [i915]] enabling pipe A [ 215.007489] [drm:intel_mst_enable_dp [i915]] 1 [ 215.009877] [drm:drm_dp_update_payload_part2] payload 0 1 [ 215.011272] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.011294] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.011342] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.011896] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.012460] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 215.012486] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 215.012517] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 215.012724] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 215.012749] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 215.012796] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.012819] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.012857] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.013152] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.013168] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.024560] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.024594] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.024621] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.024626] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.024628] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.024655] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.024682] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.024708] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.024736] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.024762] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.024787] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.024793] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.024819] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.024823] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.024849] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.024875] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.024901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.024927] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.024954] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.024978] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.025005] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.025031] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.025058] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.025094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 215.025123] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.041138] [drm:intel_mst_disable_dp [i915]] 1 [ 215.041146] [drm:drm_dp_update_payload_part1] [ 215.042689] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.042728] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.042828] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.043411] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.045253] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.045297] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.045636] [drm:drm_dp_update_payload_part1] removing payload 0 [ 215.045697] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 215.045763] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 215.045871] [drm:intel_disable_pipe [i915]] disabling pipe A [ 215.058259] [drm:intel_mst_post_disable_dp [i915]] 1 [ 215.065111] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 215.065568] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 215.065674] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 215.065733] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 215.065797] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 215.065877] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.065935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.065989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.066042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.066093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.066144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.066198] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.066253] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.066308] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.066363] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.066412] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.066461] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.066544] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.066616] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.066643] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.066816] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.066847] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.066873] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.066880] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.066882] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.066908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.066935] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.066961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.066986] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.067010] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.067033] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.067039] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.067063] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.067068] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.067092] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.067116] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.067140] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.067163] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.067190] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.067213] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.067238] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.067261] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.067285] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.067324] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 215.067352] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.067437] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 215.067478] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.067505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.067529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.067570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.067595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.067619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.067643] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.067669] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.067694] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.067721] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.067745] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.067768] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.067795] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 215.067820] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 215.067864] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 215.069339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 215.069355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 215.069370] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 215.069385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 215.086301] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 215.086318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 215.103288] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 215.105347] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 215.105543] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 215.106691] [drm:intel_enable_pipe [i915]] enabling pipe A [ 215.106716] [drm:intel_mst_enable_dp [i915]] 1 [ 215.109121] [drm:drm_dp_update_payload_part2] payload 0 1 [ 215.110488] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.110510] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.110571] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.111109] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.111690] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 215.111727] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 215.111761] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 215.111818] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 215.111844] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 215.111893] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.111919] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.111962] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.112374] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.112392] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.123851] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.123890] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.123919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.123925] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.123927] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.123955] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.123983] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.124009] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.124034] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.124057] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.124080] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.124086] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.124108] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.124113] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.124136] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.124159] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.124189] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.124220] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.124251] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.124281] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.124313] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.124344] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.124375] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.124419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 215.124453] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.140455] [drm:intel_mst_disable_dp [i915]] 1 [ 215.140462] [drm:drm_dp_update_payload_part1] [ 215.142006] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.142057] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.142140] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.142868] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.144814] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.144870] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.145166] [drm:drm_dp_update_payload_part1] removing payload 0 [ 215.145220] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 215.145268] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 215.145343] [drm:intel_disable_pipe [i915]] disabling pipe A [ 215.157755] [drm:intel_mst_post_disable_dp [i915]] 1 [ 215.163826] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 215.164289] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 215.164343] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 215.164393] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 215.164445] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 215.164513] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.164570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.164686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.165022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.165087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.165143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.165207] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.165274] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.165337] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.165394] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.165446] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.165503] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.165893] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.165928] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.165969] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.166297] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.166343] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.166382] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.166390] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.166394] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.166428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.166461] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.166499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.166534] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.166593] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.166624] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.166633] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.166670] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.166679] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.166715] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.166749] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.166780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.166815] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.166854] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.166888] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.166921] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.166951] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.166985] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.167040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 215.167080] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.167199] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 215.167254] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.167293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.167330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.167361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.167392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.167427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.167461] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.167498] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.167531] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.167587] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.167623] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.167656] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.167694] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 215.167730] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 215.167791] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 215.169351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 215.169374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 215.169398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 215.169422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 215.186346] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 215.186364] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 215.203245] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 215.205314] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 215.205541] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 215.206688] [drm:intel_enable_pipe [i915]] enabling pipe A [ 215.206724] [drm:intel_mst_enable_dp [i915]] 1 [ 215.209118] [drm:drm_dp_update_payload_part2] payload 0 1 [ 215.210486] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.210508] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.210561] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.211106] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.211683] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 215.211706] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 215.211735] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 215.211785] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 215.211807] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 215.211859] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.211881] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.211918] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.212375] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.212392] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.223726] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.223752] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.223771] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.223775] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.223776] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.223794] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.223812] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.223829] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.223845] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.223861] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.223875] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.223879] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.223893] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.223896] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.223911] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.223926] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.223940] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.223954] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.223971] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.223985] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.224001] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.224015] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.224029] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.224053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 215.224072] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.240418] [drm:intel_mst_disable_dp [i915]] 1 [ 215.240426] [drm:drm_dp_update_payload_part1] [ 215.241970] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.242009] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.242069] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.242665] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.244519] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.244588] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.244877] [drm:drm_dp_update_payload_part1] removing payload 0 [ 215.244916] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 215.244958] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 215.245019] [drm:intel_disable_pipe [i915]] disabling pipe A [ 215.257330] [drm:intel_mst_post_disable_dp [i915]] 1 [ 215.263262] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 215.263748] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 215.263810] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 215.263871] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 215.263939] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 215.264011] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.264051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.264089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.264124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.264157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.264190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.264226] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.264264] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.264300] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.264335] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.264367] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.264399] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.264466] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.264513] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.264617] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.265118] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.265193] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.265253] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.265265] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.265270] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.265329] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.265374] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.265412] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.265448] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.265482] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.265514] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.265566] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.265614] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.265629] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.265679] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.265729] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.265778] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.265827] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.265884] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.265933] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.265985] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.266034] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.266088] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.266173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 215.266235] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.266420] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 215.266500] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.266557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.266649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.266705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.266759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.266813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.266867] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.266925] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.266979] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.267032] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.267085] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.267137] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.267197] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 215.267253] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 215.267345] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 215.268849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 215.268867] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 215.268884] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 215.268908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 215.285824] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 215.285843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 215.302741] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 215.304802] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 215.304996] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 215.306090] [drm:intel_enable_pipe [i915]] enabling pipe A [ 215.306117] [drm:intel_mst_enable_dp [i915]] 1 [ 215.308509] [drm:drm_dp_update_payload_part2] payload 0 1 [ 215.309911] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.309935] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.309991] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.310534] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.311133] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 215.311158] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 215.311190] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 215.311245] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 215.311269] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 215.311327] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.311351] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.311391] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.311836] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.311867] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.323180] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.323216] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.323244] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.323249] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.323251] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.323277] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.323304] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.323328] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.323352] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.323375] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.323397] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.323403] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.323424] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.323428] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.323450] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.323471] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.323492] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.323512] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.323548] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.323626] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.323661] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.323695] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.323728] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.323785] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 215.323820] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.339813] [drm:intel_mst_disable_dp [i915]] 1 [ 215.339821] [drm:drm_dp_update_payload_part1] [ 215.341378] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.341438] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.341576] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.342366] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.344376] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.344441] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.344841] [drm:drm_dp_update_payload_part1] removing payload 0 [ 215.344906] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 215.344965] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 215.345076] [drm:intel_disable_pipe [i915]] disabling pipe A [ 215.356839] [drm:intel_mst_post_disable_dp [i915]] 1 [ 215.364251] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 215.364720] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 215.364784] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 215.364828] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 215.364870] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 215.364920] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.364955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.364987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.365018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.365047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.365075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.365106] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.365139] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.365170] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.365201] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.365230] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.365258] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.365310] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.365341] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.365374] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.365714] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.365751] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.365781] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.365789] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.365792] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.365822] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.365852] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.365881] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.365911] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.365938] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.365965] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.365972] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.365998] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.366004] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.366031] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.366058] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.366085] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.366111] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.366142] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.366169] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.366198] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.366225] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.366251] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.366295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 215.366328] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.366433] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 215.366478] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.366508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.366538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.366589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.366619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.366649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.366680] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.366712] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.366744] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.366775] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.366804] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.366833] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.366866] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 215.366897] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 215.366949] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 215.368451] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 215.368474] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 215.368493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 215.368514] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 215.385392] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 215.385408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 215.402311] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 215.404375] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 215.404573] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 215.405737] [drm:intel_enable_pipe [i915]] enabling pipe A [ 215.405762] [drm:intel_mst_enable_dp [i915]] 1 [ 215.408170] [drm:drm_dp_update_payload_part2] payload 0 1 [ 215.409565] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.409590] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.409636] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.410179] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.410756] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 215.410783] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 215.410816] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 215.410873] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 215.410901] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 215.410967] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.410995] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.411038] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.411465] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.411486] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.422843] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.422879] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.422906] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.422911] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.422913] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.422939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.422965] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.422988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.423011] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.423033] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.423054] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.423059] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.423079] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.423084] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.423104] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.423125] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.423145] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.423165] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.423188] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.423209] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.423238] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.423266] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.423294] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.423334] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 215.423365] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.439502] [drm:intel_mst_disable_dp [i915]] 1 [ 215.439511] [drm:drm_dp_update_payload_part1] [ 215.441100] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.441145] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.441235] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.442063] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.444042] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.444092] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.444383] [drm:drm_dp_update_payload_part1] removing payload 0 [ 215.444425] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 215.444469] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 215.444551] [drm:intel_disable_pipe [i915]] disabling pipe A [ 215.456850] [drm:intel_mst_post_disable_dp [i915]] 1 [ 215.463940] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 215.464382] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 215.464428] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 215.464465] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 215.464507] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 215.464641] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.464799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.464993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.465029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.465067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.465104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.465143] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.465180] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.465215] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.465255] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.465291] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.465325] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.465385] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.465424] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.465465] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.466179] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.466230] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.466269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.466278] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.466281] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.466321] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.466361] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.466399] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.466432] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.466468] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.466504] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.466512] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.466571] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.466583] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.466622] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.466770] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.466805] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.466840] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.466876] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.467393] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.467429] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.467466] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.467501] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.467582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 215.467792] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.467879] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 215.467920] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.467945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.467970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.467995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.468019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.468042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.468064] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.468091] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.468116] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.468142] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.468163] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.468184] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.468212] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 215.468238] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 215.468279] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 215.469772] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 215.469795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 215.469818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 215.469842] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 215.486765] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 215.486784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 215.503682] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 215.505750] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 215.505948] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 215.507037] [drm:intel_enable_pipe [i915]] enabling pipe A [ 215.507063] [drm:intel_mst_enable_dp [i915]] 1 [ 215.509461] [drm:drm_dp_update_payload_part2] payload 0 1 [ 215.510837] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.510863] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.510938] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.511477] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.512072] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 215.512100] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 215.512135] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 215.512194] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 215.512224] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 215.512296] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.512323] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.512368] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.512987] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.513016] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.524139] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.524176] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.524205] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.524210] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.524212] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.524239] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.524266] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.524290] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.524314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.524337] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.524358] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.524364] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.524385] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.524389] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.524412] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.524433] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.524454] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.524475] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.524500] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.524522] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.524589] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.524748] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.525328] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.525395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 215.525441] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.540718] [drm:intel_mst_disable_dp [i915]] 1 [ 215.540726] [drm:drm_dp_update_payload_part1] [ 215.542282] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.542342] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.542478] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.543217] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.545361] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.545426] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.545773] [drm:drm_dp_update_payload_part1] removing payload 0 [ 215.545850] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 215.545937] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 215.546061] [drm:intel_disable_pipe [i915]] disabling pipe A [ 215.558402] [drm:intel_mst_post_disable_dp [i915]] 1 [ 215.564562] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 215.564980] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 215.565016] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 215.565044] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 215.565078] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 215.565123] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.565152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.565179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.565204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.565229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.565253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.565279] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.565307] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.565334] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.565360] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.565384] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.565407] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.565450] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.565476] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.565512] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.565917] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.565954] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.565982] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.565988] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.565991] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.566019] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.566047] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.566073] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.566099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.566123] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.566147] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.566153] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.566176] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.566181] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.566205] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.566228] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.566251] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.566273] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.566301] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.566324] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.566348] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.566371] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.566394] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.566434] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 215.566464] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.566590] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 215.566638] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.566670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.566702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.566731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.566763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.566793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.566824] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.566856] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.566885] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.566916] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.566943] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.566971] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.567003] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 215.567032] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 215.567084] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 215.568590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 215.568616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 215.568643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 215.568670] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 215.585544] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 215.585562] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 215.602396] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 215.603582] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 215.603775] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 215.604934] [drm:intel_enable_pipe [i915]] enabling pipe A [ 215.604958] [drm:intel_mst_enable_dp [i915]] 1 [ 215.606900] [drm:drm_dp_update_payload_part2] payload 0 1 [ 215.608275] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.608296] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.608340] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.608897] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.609464] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 215.609489] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 215.609520] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 215.609591] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 215.609617] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 215.609674] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.609709] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.609749] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.610803] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.610820] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.621957] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.621990] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.622016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.622020] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.622022] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.622046] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.622070] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.622092] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.622113] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.622134] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.622153] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.622158] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.622177] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.622181] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.622201] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.622221] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.622240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.622265] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.622292] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.622318] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.622345] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.622371] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.622398] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.622435] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 215.622464] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.638603] [drm:intel_mst_disable_dp [i915]] 1 [ 215.638609] [drm:drm_dp_update_payload_part1] [ 215.640150] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.640191] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.640263] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.640878] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.642700] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.642743] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.643052] [drm:drm_dp_update_payload_part1] removing payload 0 [ 215.643094] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 215.643133] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 215.643206] [drm:intel_disable_pipe [i915]] disabling pipe A [ 215.656851] [drm:intel_mst_post_disable_dp [i915]] 1 [ 215.662646] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 215.663068] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 215.663109] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 215.663144] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 215.663183] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 215.663234] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.663270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.663305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.663339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.663374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.663409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.663444] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.663480] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.663517] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.663614] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.663658] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.663705] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.663777] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.663825] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.663872] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.664323] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.664386] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.664434] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.664446] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.664451] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.664503] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.664555] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.664640] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.664685] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.664734] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.664780] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.664791] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.664836] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.664845] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.664888] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.664936] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.664981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.665026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.665075] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.665117] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.665167] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.665213] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.665258] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.665333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 215.665389] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.665551] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 215.665647] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.665693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.665744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.665791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.665837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.665881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.665924] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.665975] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.666024] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.666073] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.666116] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.666157] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.666212] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 215.666261] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 215.666342] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 215.667975] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 215.668023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 215.668072] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 215.668123] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 215.685074] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 215.685092] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 215.701991] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 215.704061] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 215.704258] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 215.705353] [drm:intel_enable_pipe [i915]] enabling pipe A [ 215.705381] [drm:intel_mst_enable_dp [i915]] 1 [ 215.707777] [drm:drm_dp_update_payload_part2] payload 0 1 [ 215.709155] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.709177] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.709229] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.709768] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.710335] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 215.710359] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 215.710389] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 215.710443] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 215.710466] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 215.710509] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.710570] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.710614] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.711059] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.711077] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.722452] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.722493] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.722529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.722586] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.722594] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.722638] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.722682] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.722723] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.722764] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.722803] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.722840] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.722848] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.722884] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.722892] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.722931] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.722969] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.723006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.723041] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.723078] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.723117] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.723156] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.723193] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.723227] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.723289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 215.723332] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.739044] [drm:intel_mst_disable_dp [i915]] 1 [ 215.739052] [drm:drm_dp_update_payload_part1] [ 215.740599] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.740645] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.740753] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.741496] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.743416] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.743465] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.743782] [drm:drm_dp_update_payload_part1] removing payload 0 [ 215.743840] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 215.743900] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 215.743966] [drm:intel_disable_pipe [i915]] disabling pipe A [ 215.756277] [drm:intel_mst_post_disable_dp [i915]] 1 [ 215.763385] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 215.763848] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 215.763880] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 215.763905] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 215.763934] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 215.763973] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.763998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.764021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.764044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.764065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.764087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.764109] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.764133] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.764156] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.764178] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.764199] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.764219] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.764255] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.764278] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.764303] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.764498] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.764527] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.764610] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.764621] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.764626] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.764663] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.764701] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.764735] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.764770] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.764801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.764834] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.764842] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.764871] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.764880] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.764911] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.764943] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.764974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.765004] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.765037] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.765068] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.765099] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.765129] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.765159] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.765210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 215.765247] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.765351] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 215.765401] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.765435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.765466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.765499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.765531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.765582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.765617] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.765654] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.765689] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.765724] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.765758] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.765791] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.765828] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 215.765861] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 215.765919] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 215.767421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 215.767440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 215.767456] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 215.767472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 215.784371] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 215.784390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 215.801264] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 215.803299] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 215.803497] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 215.804603] [drm:intel_enable_pipe [i915]] enabling pipe A [ 215.804627] [drm:intel_mst_enable_dp [i915]] 1 [ 215.806906] [drm:drm_dp_update_payload_part2] payload 0 1 [ 215.808274] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.808296] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.808343] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.808922] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.809502] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 215.809533] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 215.809585] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 215.809650] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 215.809680] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 215.809731] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.809762] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.809810] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.810199] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.810220] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.821715] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.821759] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.821792] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.821798] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.821801] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.821832] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.821865] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.821900] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.821935] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.821970] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.822004] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.822010] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.822044] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.822050] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.822085] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.822119] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.822154] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.822188] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.822222] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.822255] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.822291] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.822326] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.822361] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.822410] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 215.822447] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.838330] [drm:intel_mst_disable_dp [i915]] 1 [ 215.838339] [drm:drm_dp_update_payload_part1] [ 215.839891] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.839936] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.840046] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.840669] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.842619] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.842675] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.842942] [drm:drm_dp_update_payload_part1] removing payload 0 [ 215.842994] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 215.843044] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 215.843116] [drm:intel_disable_pipe [i915]] disabling pipe A [ 215.856863] [drm:intel_mst_post_disable_dp [i915]] 1 [ 215.861994] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 215.862465] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 215.862517] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 215.862637] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 215.862708] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 215.862794] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.862854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.862914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.862969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.863025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.863082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.863143] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.863208] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.863270] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.863330] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.863385] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.863442] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.863547] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.863609] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.863644] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.863922] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.863955] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.863976] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.863981] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.863982] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.864003] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.864024] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.864043] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.864062] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.864080] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.864098] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.864102] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.864119] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.864123] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.864140] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.864156] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.864173] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.864190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.864210] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.864227] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.864245] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.864261] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.864278] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.864307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 215.864334] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.864409] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 215.864447] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.864472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.864496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.864521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.864573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.864607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.864638] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.864669] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.864699] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.864729] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.864758] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.864788] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.864823] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 215.864855] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 215.864908] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 215.866415] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 215.866439] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 215.866462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 215.866487] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 215.883413] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 215.883432] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 215.900331] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 215.902390] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 215.902586] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 215.903776] [drm:intel_enable_pipe [i915]] enabling pipe A [ 215.903801] [drm:intel_mst_enable_dp [i915]] 1 [ 215.906194] [drm:drm_dp_update_payload_part2] payload 0 1 [ 215.907588] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.907610] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.907665] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.908223] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.908812] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 215.908842] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 215.908879] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 215.908942] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 215.908983] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 215.909036] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.909064] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.909112] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.909507] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.909563] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.920906] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.920945] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.920975] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.920980] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.920983] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.921010] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.921038] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.921064] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.921089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.921113] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.921137] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.921142] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.921165] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.921170] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.921193] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.921215] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.921238] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.921260] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.921287] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.921310] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.921333] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.921355] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.921376] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.921414] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 215.921442] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.937599] [drm:intel_mst_disable_dp [i915]] 1 [ 215.937609] [drm:drm_dp_update_payload_part1] [ 215.939192] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 215.939248] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 215.939360] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 215.940067] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 215.942034] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 215.942091] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 215.942390] [drm:drm_dp_update_payload_part1] removing payload 0 [ 215.942438] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 215.942487] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 215.942637] [drm:intel_disable_pipe [i915]] disabling pipe A [ 215.955001] [drm:intel_mst_post_disable_dp [i915]] 1 [ 215.961371] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 215.962008] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 215.962056] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 215.962092] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 215.962135] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 215.962189] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.962226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.962261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.962293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.962324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.962355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.962388] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.962423] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.962456] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.962488] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.962518] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.962619] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.962703] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 215.962752] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 215.962807] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.963286] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 215.963350] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 215.963402] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 215.963413] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 215.963419] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 215.963468] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.963523] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 215.963608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.963657] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 215.963703] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.963747] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.963765] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.963815] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.963828] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 215.963875] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 215.963923] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 215.963971] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.964019] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.964074] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 215.964123] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.964173] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 215.964221] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 215.964265] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 215.964341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 215.964396] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 215.964597] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 215.964664] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 215.964718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 215.964771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 215.964822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 215.964872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 215.964917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 215.964951] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 215.964987] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 215.965020] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 215.965052] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 215.965082] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 215.965111] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 215.965147] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 215.965181] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 215.965237] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 215.966740] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 215.966757] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 215.966772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 215.966788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 215.983704] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 215.983722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 216.000622] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 216.002691] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 216.002889] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 216.003996] [drm:intel_enable_pipe [i915]] enabling pipe A [ 216.004023] [drm:intel_mst_enable_dp [i915]] 1 [ 216.006420] [drm:drm_dp_update_payload_part2] payload 0 1 [ 216.007789] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.007812] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.007876] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.008423] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.009011] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 216.009039] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 216.009073] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 216.009153] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 216.009192] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 216.009241] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.009268] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.009313] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.009743] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.009767] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.021067] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.021101] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.021128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.021133] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.021135] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.021161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.021186] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.021210] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.021233] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.021260] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.021288] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.021293] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.021321] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.021325] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.021354] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.021382] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.021410] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.021437] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.021465] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.021491] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.021521] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.021604] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.021642] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.021701] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 216.021741] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.037645] [drm:intel_mst_disable_dp [i915]] 1 [ 216.037653] [drm:drm_dp_update_payload_part1] [ 216.039194] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.039239] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.039321] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.039967] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.041888] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.041937] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.042237] [drm:drm_dp_update_payload_part1] removing payload 0 [ 216.042285] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 216.042327] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 216.042410] [drm:intel_disable_pipe [i915]] disabling pipe A [ 216.055852] [drm:intel_mst_post_disable_dp [i915]] 1 [ 216.061779] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 216.062244] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 216.062293] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 216.062331] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 216.062376] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 216.062432] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.062472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.062509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.062623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.062681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.062731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.062792] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.062854] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.062912] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.062969] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.063006] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.063038] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.063100] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.063137] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.063177] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.063626] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.063699] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.063757] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.063789] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.063797] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.063854] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.063912] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.063964] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.064017] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.064068] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.064102] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.064110] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.064142] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.064148] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.064182] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.064214] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.064247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.064278] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.064316] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.064347] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.064381] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.064412] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.064443] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.064499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 216.064541] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.064669] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 216.064699] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.064720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.064742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.064762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.064784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.064806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.064826] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.064849] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.064871] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.064893] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.064914] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.064935] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.064957] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 216.064978] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 216.065010] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 216.066488] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 216.066510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 216.066558] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 216.066577] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 216.083470] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 216.083487] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 216.100367] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 216.102432] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 216.102630] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 216.103761] [drm:intel_enable_pipe [i915]] enabling pipe A [ 216.103792] [drm:intel_mst_enable_dp [i915]] 1 [ 216.106196] [drm:drm_dp_update_payload_part2] payload 0 1 [ 216.107556] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.107578] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.107611] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.108135] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.108745] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 216.108776] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 216.108805] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 216.108857] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 216.108879] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 216.108919] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.108941] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.108978] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.109390] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.109406] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.120881] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.120908] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.120928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.120933] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.120934] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.120953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.120972] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.120990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.121007] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.121023] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.121039] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.121043] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.121058] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.121061] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.121077] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.121093] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.121108] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.121123] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.121141] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.121156] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.121172] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.121188] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.121203] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.121229] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 216.121249] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.137523] [drm:intel_mst_disable_dp [i915]] 1 [ 216.137553] [drm:drm_dp_update_payload_part1] [ 216.139103] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.139145] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.139208] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.139814] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.141667] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.141713] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.142020] [drm:drm_dp_update_payload_part1] removing payload 0 [ 216.142057] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 216.142095] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 216.142171] [drm:intel_disable_pipe [i915]] disabling pipe A [ 216.155683] [drm:intel_mst_post_disable_dp [i915]] 1 [ 216.161575] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 216.162027] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 216.162072] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 216.162108] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 216.162150] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 216.162204] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.162241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.162275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.162308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.162339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.162371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.162403] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.162438] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.162470] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.162501] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.162531] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.162628] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.162713] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.162762] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.162820] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.163314] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.163380] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.163432] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.163444] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.163450] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.163500] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.163553] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.163684] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.163737] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.163788] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.163833] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.163844] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.163891] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.163901] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.163950] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.163999] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.164047] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.164095] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.164150] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.164199] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.164249] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.164297] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.164346] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.164425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 216.164481] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.164699] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 216.164775] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.164825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.164872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.164920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.164966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.165016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.165069] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.165112] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.165142] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.165172] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.165198] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.165224] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.165254] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 216.165282] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 216.165333] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 216.167006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 216.167028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 216.167048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 216.167069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 216.183990] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 216.184007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 216.200903] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 216.202962] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 216.203156] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 216.204258] [drm:intel_enable_pipe [i915]] enabling pipe A [ 216.204285] [drm:intel_mst_enable_dp [i915]] 1 [ 216.206690] [drm:drm_dp_update_payload_part2] payload 0 1 [ 216.208066] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.208087] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.208139] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.208681] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.209248] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 216.209273] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 216.209303] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 216.209358] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 216.209384] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 216.209446] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.209472] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.209518] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.210564] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.210581] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.221309] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.221340] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.221363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.221368] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.221370] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.221392] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.221414] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.221435] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.221456] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.221474] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.221493] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.221498] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.221516] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.222578] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.222604] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.222627] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.222647] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.222666] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.222689] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.222708] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.222729] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.222747] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.222766] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.222799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 216.222823] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.237939] [drm:intel_mst_disable_dp [i915]] 1 [ 216.237946] [drm:drm_dp_update_payload_part1] [ 216.239477] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.239512] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.239584] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.240164] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.241957] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.241997] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.242321] [drm:drm_dp_update_payload_part1] removing payload 0 [ 216.242372] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 216.242423] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 216.242524] [drm:intel_disable_pipe [i915]] disabling pipe A [ 216.254846] [drm:intel_mst_post_disable_dp [i915]] 1 [ 216.261211] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 216.261666] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 216.261715] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 216.261746] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 216.261782] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 216.261829] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.261860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.261889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.261923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.261958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.261993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.262028] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.262065] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.262102] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.262138] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.262172] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.262206] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.262260] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.262296] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.262335] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.262685] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.262737] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.262779] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.262788] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.262792] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.262834] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.262863] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.262888] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.262914] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.262937] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.262961] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.262967] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.262989] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.262993] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.263016] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.263037] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.263059] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.263080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.263107] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.263128] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.263151] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.263172] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.263202] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.263246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 216.263280] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.263398] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 216.263457] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.263493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.263557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.263595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.263628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.263662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.263698] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.263735] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.263772] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.263807] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.263840] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.263872] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.263910] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 216.263945] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 216.264009] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 216.265678] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 216.265705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 216.265730] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 216.265754] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 216.282659] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 216.282677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 216.299550] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 216.301627] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 216.301826] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 216.302927] [drm:intel_enable_pipe [i915]] enabling pipe A [ 216.302953] [drm:intel_mst_enable_dp [i915]] 1 [ 216.304894] [drm:drm_dp_update_payload_part2] payload 0 1 [ 216.306267] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.306291] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.306340] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.306899] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.307472] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 216.307500] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 216.307557] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 216.307619] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 216.307647] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 216.307694] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.307720] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.307763] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.308182] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.308202] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.319967] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.320000] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.320025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.320030] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.320032] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.320056] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.320080] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.320103] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.320125] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.320145] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.320165] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.320170] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.320190] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.320194] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.320214] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.320240] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.320267] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.320294] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.320321] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.320347] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.320375] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.320402] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.320429] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.320468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 216.320497] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.336639] [drm:intel_mst_disable_dp [i915]] 1 [ 216.336646] [drm:drm_dp_update_payload_part1] [ 216.338173] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.338209] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.338295] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.338886] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.340748] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.340796] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.341110] [drm:drm_dp_update_payload_part1] removing payload 0 [ 216.341154] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 216.341197] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 216.341259] [drm:intel_disable_pipe [i915]] disabling pipe A [ 216.354787] [drm:intel_mst_post_disable_dp [i915]] 1 [ 216.360070] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 216.360504] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 216.360634] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 216.360681] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 216.360733] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 216.360801] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.360847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.360892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.360934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.360976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.361017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.361061] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.361106] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.361149] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.361193] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.361233] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.361272] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.361336] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.361366] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.361398] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.361718] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.361757] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.361789] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.361795] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.361800] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.361829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.361860] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.361890] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.361918] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.361954] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.361989] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.361997] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.362032] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.362038] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.362074] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.362111] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.362147] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.362183] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.362220] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.362254] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.362291] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.362328] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.362364] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.362417] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 216.362458] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.362619] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 216.362691] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.362739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.362787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.362830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.362872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.362913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.362957] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.363004] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.363048] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.363092] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.363132] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.363173] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.363221] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 216.363265] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 216.363339] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 216.364875] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 216.364892] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 216.364907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 216.364922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 216.381836] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 216.381854] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 216.398751] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 216.400811] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 216.401009] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 216.402141] [drm:intel_enable_pipe [i915]] enabling pipe A [ 216.402168] [drm:intel_mst_enable_dp [i915]] 1 [ 216.404561] [drm:drm_dp_update_payload_part2] payload 0 1 [ 216.405931] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.405953] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.406007] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.406575] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.407151] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 216.407179] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 216.407213] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 216.407273] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 216.407299] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 216.407363] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.407390] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.407434] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.407943] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.407965] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.419202] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.419242] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.419273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.419279] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.419281] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.419310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.419339] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.419367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.419393] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.419418] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.419442] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.419448] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.419472] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.419477] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.419501] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.419880] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.419908] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.419933] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.419962] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.419988] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.420014] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.420037] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.420061] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.420102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 216.420133] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.435782] [drm:intel_mst_disable_dp [i915]] 1 [ 216.435790] [drm:drm_dp_update_payload_part1] [ 216.437320] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.437363] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.437459] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.438092] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.439999] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.440056] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.440355] [drm:drm_dp_update_payload_part1] removing payload 0 [ 216.440399] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 216.440443] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 216.440530] [drm:intel_disable_pipe [i915]] disabling pipe A [ 216.452773] [drm:intel_mst_post_disable_dp [i915]] 1 [ 216.459787] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 216.460251] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 216.460300] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 216.460338] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 216.460383] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 216.460441] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.460480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.460518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.460641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.460693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.460745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.460797] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.460854] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.460908] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.460961] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.461009] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.461058] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.461146] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.461198] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.461256] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.461867] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.461891] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.461909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.461913] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.461915] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.461933] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.461950] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.461967] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.461983] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.461998] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.462013] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.462017] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.462031] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.462034] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.462049] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.462063] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.462077] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.462091] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.462108] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.462122] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.462138] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.462152] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.462166] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.462191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 216.462210] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.462268] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 216.462296] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.462316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.462337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.462357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.462378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.462397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.462418] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.462439] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.462460] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.462481] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.462500] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.462524] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.462573] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 216.463069] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 216.463113] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 216.464585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 216.464602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 216.464617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 216.464633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 216.481479] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 216.481497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 216.498352] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 216.499566] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 216.499764] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 216.500942] [drm:intel_enable_pipe [i915]] enabling pipe A [ 216.500969] [drm:intel_mst_enable_dp [i915]] 1 [ 216.503369] [drm:drm_dp_update_payload_part2] payload 0 1 [ 216.504742] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.504766] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.504820] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.505361] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.505936] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 216.505961] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 216.505993] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 216.506048] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 216.506071] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 216.506131] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.506154] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.506195] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.506629] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.506647] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.518009] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.518037] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.518060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.518064] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.518066] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.518090] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.518112] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.518134] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.518157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.518178] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.518200] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.518204] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.518225] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.518229] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.518251] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.518273] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.518295] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.518317] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.518339] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.518359] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.518382] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.518404] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.518426] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.518459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 216.518483] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.534678] [drm:intel_mst_disable_dp [i915]] 1 [ 216.534685] [drm:drm_dp_update_payload_part1] [ 216.536218] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.536257] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.536325] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.536949] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.538849] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.538896] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.539196] [drm:drm_dp_update_payload_part1] removing payload 0 [ 216.539234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 216.539274] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 216.539351] [drm:intel_disable_pipe [i915]] disabling pipe A [ 216.552707] [drm:intel_mst_post_disable_dp [i915]] 1 [ 216.558279] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 216.558843] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 216.558887] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 216.558921] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 216.558961] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 216.559011] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.559046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.559078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.559108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.559138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.559167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.559198] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.559230] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.559261] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.559292] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.559320] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.559347] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.559398] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.559429] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.559462] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.559991] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.560063] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.560123] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.560135] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.560140] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.560201] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.560260] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.560318] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.560359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.560382] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.560404] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.560409] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.560431] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.560435] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.560457] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.560478] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.560500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.560555] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.560593] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.560626] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.560660] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.560694] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.560727] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.560787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 216.560826] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.560953] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 216.561009] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.561047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.561082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.561105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.561129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.561151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.561174] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.561199] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.561223] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.561246] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.561268] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.561290] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.561317] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 216.561341] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 216.561382] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 216.562895] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 216.562917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 216.562937] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 216.562957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 216.579880] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 216.579897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 216.596797] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 216.598859] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 216.599057] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 216.600155] [drm:intel_enable_pipe [i915]] enabling pipe A [ 216.600183] [drm:intel_mst_enable_dp [i915]] 1 [ 216.602576] [drm:drm_dp_update_payload_part2] payload 0 1 [ 216.603935] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.603957] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.604012] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.604568] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.605134] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 216.605159] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 216.605190] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 216.605245] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 216.605268] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 216.605327] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.605351] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.605391] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.605823] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.605841] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.617256] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.617299] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.617333] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.617339] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.617341] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.617373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.617404] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.617438] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.617473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.617508] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.617587] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.617599] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.617637] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.617648] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.617687] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.617725] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.617762] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.617799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.617843] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.617880] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.617924] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.617964] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.618003] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.618065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 216.618113] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.633878] [drm:intel_mst_disable_dp [i915]] 1 [ 216.633887] [drm:drm_dp_update_payload_part1] [ 216.635433] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.635481] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.635635] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.636532] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.638711] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.638779] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.639065] [drm:drm_dp_update_payload_part1] removing payload 0 [ 216.639118] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 216.639172] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 216.639279] [drm:intel_disable_pipe [i915]] disabling pipe A [ 216.650800] [drm:intel_mst_post_disable_dp [i915]] 1 [ 216.658422] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 216.658858] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 216.658893] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 216.658920] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 216.658951] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 216.658995] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.659022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.659048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.659073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.659096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.659119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.659144] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.659171] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.659195] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.659219] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.659242] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.659264] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.659305] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.659330] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.659356] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.659685] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.659730] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.659766] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.659775] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.659778] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.659814] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.659850] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.659885] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.659920] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.659953] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.659985] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.659992] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.660024] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.660030] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.660063] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.660095] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.660128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.660159] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.660195] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.660226] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.660260] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.660292] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.660324] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.660376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 216.660415] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.660564] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 216.660619] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.660657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.660695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.660731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.660767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.660802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.660839] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.660875] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.660911] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.660946] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.660978] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.661010] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.661048] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 216.661082] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 216.661143] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 216.662661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 216.662679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 216.662695] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 216.662712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 216.679601] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 216.679619] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 216.696492] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 216.698560] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 216.698757] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 216.699965] [drm:intel_enable_pipe [i915]] enabling pipe A [ 216.699991] [drm:intel_mst_enable_dp [i915]] 1 [ 216.702392] [drm:drm_dp_update_payload_part2] payload 0 1 [ 216.703775] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.703798] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.703834] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.704360] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.704946] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 216.704971] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 216.705002] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 216.705056] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 216.705080] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 216.705135] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.705159] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.705199] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.705659] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.705685] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.716999] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.717027] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.717048] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.717052] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.717053] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.717074] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.717093] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.717112] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.717130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.717147] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.717163] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.717167] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.717183] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.717187] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.717203] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.717219] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.717235] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.717250] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.717269] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.717285] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.717302] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.717318] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.717333] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.717361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 216.717382] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.733661] [drm:intel_mst_disable_dp [i915]] 1 [ 216.733669] [drm:drm_dp_update_payload_part1] [ 216.735207] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.735249] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.735350] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.736016] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.737882] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.737928] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.738232] [drm:drm_dp_update_payload_part1] removing payload 0 [ 216.738274] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 216.738316] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 216.738377] [drm:intel_disable_pipe [i915]] disabling pipe A [ 216.751737] [drm:intel_mst_post_disable_dp [i915]] 1 [ 216.757052] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 216.757492] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 216.757599] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 216.757648] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 216.757703] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 216.757773] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.757822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.757868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.757914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.757958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.758001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.758047] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.758094] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.758140] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.758185] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.758228] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.758269] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.758347] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.758411] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.758466] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.758872] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.758912] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.758940] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.758946] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.758948] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.758975] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.759002] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.759027] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.759053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.759076] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.759099] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.759104] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.759127] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.759131] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.759155] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.759177] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.759199] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.759221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.759252] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.759282] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.759314] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.759346] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.759377] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.759422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 216.759457] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.759588] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 216.759650] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.759693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.759733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.759768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.759806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.759842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.759879] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.759918] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.759954] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.759991] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.760025] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.760059] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.760099] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 216.760136] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 216.760200] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 216.761769] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 216.761797] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 216.761822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 216.761848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 216.778713] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 216.778730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 216.795560] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 216.797572] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 216.797768] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 216.798873] [drm:intel_enable_pipe [i915]] enabling pipe A [ 216.798900] [drm:intel_mst_enable_dp [i915]] 1 [ 216.800884] [drm:drm_dp_update_payload_part2] payload 0 1 [ 216.802246] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.802267] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.802320] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.802883] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.803451] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 216.803473] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 216.803501] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 216.803570] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 216.803593] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 216.803634] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.803658] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.803698] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.804214] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.804230] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.815912] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.815936] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.815957] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.815961] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.815962] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.815983] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.816003] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.816023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.816043] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.816063] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.816082] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.816086] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.816106] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.816109] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.816129] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.816149] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.816168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.816188] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.816208] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.816227] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.816248] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.816268] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.816287] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.816316] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 216.816338] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.832586] [drm:intel_mst_disable_dp [i915]] 1 [ 216.832592] [drm:drm_dp_update_payload_part1] [ 216.834110] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.834147] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.834223] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.834807] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.836622] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.836666] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.836966] [drm:drm_dp_update_payload_part1] removing payload 0 [ 216.837003] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 216.837041] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 216.837117] [drm:intel_disable_pipe [i915]] disabling pipe A [ 216.850730] [drm:intel_mst_post_disable_dp [i915]] 1 [ 216.855554] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 216.856003] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 216.856047] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 216.856082] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 216.856122] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 216.856177] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.856214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.856255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.856297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.856339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.856380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.856421] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.856465] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.856508] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.856607] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.856664] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.856713] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.856796] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.856835] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.856875] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.857174] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.857219] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.857256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.857264] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.857267] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.857303] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.857339] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.857373] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.857407] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.857441] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.857473] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.857480] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.857511] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.857586] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.857635] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.857682] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.857728] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.857773] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.857826] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.857873] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.857922] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.857969] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.858016] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.858095] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 216.858137] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.858248] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 216.858299] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.858334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.858367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.858409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.858452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.858494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.858536] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.858616] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.858671] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.858723] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.858769] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.858816] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.858869] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 216.858923] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 216.858988] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 216.860572] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 216.860608] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 216.860642] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 216.860683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 216.877623] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 216.877639] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 216.894532] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 216.896563] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 216.896754] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 216.897850] [drm:intel_enable_pipe [i915]] enabling pipe A [ 216.897875] [drm:intel_mst_enable_dp [i915]] 1 [ 216.900256] [drm:drm_dp_update_payload_part2] payload 0 1 [ 216.901600] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.901620] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.901662] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.902192] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.902764] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 216.902790] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 216.902821] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 216.902874] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 216.902898] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 216.902941] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.902966] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.903006] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.903446] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.903462] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.914941] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.914978] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.915006] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.915011] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.915014] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.915040] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.915067] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.915093] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.915118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.915141] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.915164] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.915169] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.915192] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.915196] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.915219] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.915241] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.915263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.915284] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.915310] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.915332] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.915355] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.915377] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.915398] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.915434] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 216.915462] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.931572] [drm:intel_mst_disable_dp [i915]] 1 [ 216.931579] [drm:drm_dp_update_payload_part1] [ 216.933104] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 216.933147] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 216.933223] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 216.933863] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 216.935733] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 216.935784] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 216.936086] [drm:drm_dp_update_payload_part1] removing payload 0 [ 216.936127] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 216.936170] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 216.936235] [drm:intel_disable_pipe [i915]] disabling pipe A [ 216.949727] [drm:intel_mst_post_disable_dp [i915]] 1 [ 216.954496] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 216.954948] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 216.954986] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 216.955016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 216.955053] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 216.955102] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.955134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.955164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.955194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.955222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.955249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.955278] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.955310] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.955340] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.955369] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.955395] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.955421] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.955467] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 216.955497] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 216.955619] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.956028] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 216.956088] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 216.956138] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 216.956147] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 216.956152] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 216.956199] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 216.956243] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 216.956289] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 216.956335] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 216.956379] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 216.956419] [drm:intel_dump_pipe_config [i915]] requested mode: [ 216.956428] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.956471] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 216.956479] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 216.956531] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 216.956614] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 216.956657] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 216.956700] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 216.956748] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 216.956793] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 216.956834] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 216.956874] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 216.956919] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 216.956987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 216.957034] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 216.957177] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 216.957236] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 216.957282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 216.957325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 216.957367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 216.957406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 216.957442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 216.957485] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 216.957530] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 216.957602] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 216.957646] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 216.957686] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 216.957731] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 216.957780] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 216.957825] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 216.957900] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 216.959478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 216.959519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 216.959633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 216.959677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 216.976633] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 216.976653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 216.993555] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 216.995609] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 216.995810] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 216.997013] [drm:intel_enable_pipe [i915]] enabling pipe A [ 216.997042] [drm:intel_mst_enable_dp [i915]] 1 [ 216.999435] [drm:drm_dp_update_payload_part2] payload 0 1 [ 217.000810] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.000834] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.000890] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.001431] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.002005] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 217.002030] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 217.002062] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 217.002137] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 217.002160] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 217.002228] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.002250] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.002288] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.002716] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.002742] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.014106] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.014140] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.014166] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.014171] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.014173] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.014197] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.014221] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.014243] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.014265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.014285] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.014304] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.014309] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.014329] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.014333] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.014353] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.014373] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.014400] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.014426] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.014453] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.014479] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.014507] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.014573] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.014990] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.015030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 217.015061] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.030690] [drm:intel_mst_disable_dp [i915]] 1 [ 217.030697] [drm:drm_dp_update_payload_part1] [ 217.032241] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.032281] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.032354] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.032968] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.034815] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.034856] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.035214] [drm:drm_dp_update_payload_part1] removing payload 0 [ 217.035252] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 217.035291] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 217.035352] [drm:intel_disable_pipe [i915]] disabling pipe A [ 217.047734] [drm:intel_mst_post_disable_dp [i915]] 1 [ 217.054258] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 217.054733] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 217.054808] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 217.054855] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 217.054910] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 217.054962] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.054998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.055031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.055062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.055091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.055121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.055153] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.055187] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.055218] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.055249] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.055277] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.055306] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.055357] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.055388] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.055422] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.055802] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.055845] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.055878] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.055885] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.055888] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.055920] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.055959] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.056008] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.056057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.056104] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.056150] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.056161] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.056206] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.056292] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.056340] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.056405] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.056487] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.056585] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.056656] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.056723] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.056791] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.056871] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.056936] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.057009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 217.057061] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.057222] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 217.057296] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.057346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.057394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.057442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.057536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.057615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.057685] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.057755] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.057822] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.057869] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.057912] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.057955] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.058009] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 217.058060] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 217.058142] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 217.059897] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 217.059915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 217.059930] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 217.059945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 217.076835] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 217.076853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 217.093729] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 217.095766] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 217.095965] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 217.097141] [drm:intel_enable_pipe [i915]] enabling pipe A [ 217.097167] [drm:intel_mst_enable_dp [i915]] 1 [ 217.099603] [drm:drm_dp_update_payload_part2] payload 0 1 [ 217.100972] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.100994] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.101039] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.101588] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.102158] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 217.102181] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 217.102209] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 217.102261] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 217.102283] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 217.102326] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.102348] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.102385] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.102871] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.102889] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.114230] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.114257] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.114278] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.114282] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.114284] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.114304] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.114324] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.114343] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.114361] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.114379] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.114395] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.114399] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.114416] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.114419] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.114435] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.114452] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.114467] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.114483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.114502] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.114563] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.114590] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.114615] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.114640] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.114682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 217.114711] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.130904] [drm:intel_mst_disable_dp [i915]] 1 [ 217.130911] [drm:drm_dp_update_payload_part1] [ 217.132435] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.132470] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.132581] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.133173] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.135017] [drm:drm_dp_update_payload_part1] removing payload 0 [ 217.135068] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 217.135119] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 217.135194] [drm:intel_disable_pipe [i915]] disabling pipe A [ 217.135399] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.135433] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.148722] [drm:intel_mst_post_disable_dp [i915]] 1 [ 217.153735] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 217.154179] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 217.154223] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 217.154259] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 217.154300] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 217.154355] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.154391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.154426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.154458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.154490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.154540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.154660] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.154722] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.154985] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.155039] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.155096] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.155149] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.155238] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.155291] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.155353] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.155905] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.155978] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.156038] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.156050] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.156056] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.156110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.156163] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.156219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.156275] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.156329] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.156377] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.156388] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.156441] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.156451] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.156504] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.156597] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.156648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.156701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.156760] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.156812] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.156867] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.156913] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.156968] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.157052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 217.157114] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.157304] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 217.157385] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.157442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.157497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.157570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.157618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.157673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.157727] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.157786] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.157840] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.157898] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.157950] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.158004] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.158061] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 217.158112] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 217.158207] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 217.159766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 217.159794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 217.159819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 217.159843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 217.176767] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 217.176785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 217.193684] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 217.195745] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 217.195942] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 217.197040] [drm:intel_enable_pipe [i915]] enabling pipe A [ 217.197068] [drm:intel_mst_enable_dp [i915]] 1 [ 217.199443] [drm:drm_dp_update_payload_part2] payload 0 1 [ 217.200816] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.200839] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.200894] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.201434] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.202039] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 217.202069] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 217.202105] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 217.202170] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 217.202201] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 217.202257] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.202289] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.202337] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.202750] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.202774] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.214115] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.214151] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.214179] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.214185] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.214187] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.214213] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.214239] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.214264] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.214288] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.214311] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.214334] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.214339] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.214361] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.214365] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.214387] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.214409] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.214430] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.214452] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.214477] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.214498] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.214579] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.214614] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.215137] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.215180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 217.215211] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.230797] [drm:intel_mst_disable_dp [i915]] 1 [ 217.230807] [drm:drm_dp_update_payload_part1] [ 217.232376] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.232431] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.232559] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.233316] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.235327] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.235386] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.235736] [drm:drm_dp_update_payload_part1] removing payload 0 [ 217.235792] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 217.235846] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 217.235927] [drm:intel_disable_pipe [i915]] disabling pipe A [ 217.248246] [drm:intel_mst_post_disable_dp [i915]] 1 [ 217.254783] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 217.255198] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 217.255233] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 217.255259] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 217.255291] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 217.255333] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.255361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.255387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.255412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.255436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.255460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.255485] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.255511] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.255813] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.255840] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.255864] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.255887] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.255930] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.255959] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.255994] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.256234] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.256272] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.256303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.256309] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.256312] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.256344] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.256375] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.256406] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.256438] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.256469] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.256499] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.256541] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.256587] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.257009] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.257043] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.257072] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.257100] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.257127] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.257157] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.257184] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.257212] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.257238] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.257263] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.257307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 217.257341] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.257436] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 217.257479] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.257508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.257571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.257840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.257860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.257879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.257900] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.257921] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.257940] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.257959] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.257976] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.257994] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.258016] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 217.258036] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 217.258069] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 217.259561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 217.259583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 217.259602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 217.259622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 217.276552] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 217.276570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 217.293465] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 217.295523] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 217.295717] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 217.296898] [drm:intel_enable_pipe [i915]] enabling pipe A [ 217.296924] [drm:intel_mst_enable_dp [i915]] 1 [ 217.299314] [drm:drm_dp_update_payload_part2] payload 0 1 [ 217.300681] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.300702] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.300741] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.301272] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.301842] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 217.301867] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 217.301898] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 217.301951] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 217.301975] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 217.302027] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.302052] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.302092] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.302544] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.302570] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.314034] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.314067] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.314093] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.314098] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.314100] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.314123] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.314148] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.314170] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.314192] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.314213] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.314233] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.314238] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.314257] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.314261] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.314281] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.314301] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.314320] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.314339] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.314362] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.314381] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.314401] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.314420] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.314439] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.314472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 217.314497] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.330587] [drm:intel_mst_disable_dp [i915]] 1 [ 217.330594] [drm:drm_dp_update_payload_part1] [ 217.332124] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.332156] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.332219] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.332802] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.334644] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.334690] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.334993] [drm:drm_dp_update_payload_part1] removing payload 0 [ 217.335033] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 217.335075] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 217.335133] [drm:intel_disable_pipe [i915]] disabling pipe A [ 217.348821] [drm:intel_mst_post_disable_dp [i915]] 1 [ 217.353822] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 217.354278] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 217.354327] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 217.354366] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 217.354411] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 217.354468] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.354513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.354608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.354674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.354733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.354793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.354852] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.354908] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.354969] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.355028] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.355081] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.355131] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.355224] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.355281] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.355343] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.355854] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.355927] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.355984] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.355997] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.356002] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.356061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.356120] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.356176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.356227] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.356280] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.356332] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.356344] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.356396] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.356407] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.356456] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.356504] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.356595] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.356653] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.356716] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.356768] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.356821] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.356881] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.356938] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.357024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 217.357082] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.357271] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 217.357352] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.357410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.357465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.357514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.357605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.357659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.357713] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.357766] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.357818] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.357874] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.357925] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.357980] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.358039] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 217.358094] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 217.358191] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 217.359845] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 217.359900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 217.359956] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 217.360013] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 217.376974] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 217.376993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 217.393892] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 217.395952] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 217.396147] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 217.397316] [drm:intel_enable_pipe [i915]] enabling pipe A [ 217.397342] [drm:intel_mst_enable_dp [i915]] 1 [ 217.399733] [drm:drm_dp_update_payload_part2] payload 0 1 [ 217.401101] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.401122] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.401175] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.401716] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.402288] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 217.402311] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 217.402340] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 217.402390] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 217.402412] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 217.402463] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.402485] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.402571] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.402996] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.403018] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.414463] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.414506] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.414588] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.414600] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.414603] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.414668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.414712] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.414752] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.414790] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.414826] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.414890] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.414898] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.414931] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.414938] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.414972] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.415004] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.415036] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.415070] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.415109] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.415144] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.415181] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.415215] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.415277] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.415336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 217.415378] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.431062] [drm:intel_mst_disable_dp [i915]] 1 [ 217.431069] [drm:drm_dp_update_payload_part1] [ 217.432610] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.432656] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.432768] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.433397] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.435291] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.435342] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.435877] [drm:drm_dp_update_payload_part1] removing payload 0 [ 217.435931] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 217.435976] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 217.436044] [drm:intel_disable_pipe [i915]] disabling pipe A [ 217.448610] [drm:intel_mst_post_disable_dp [i915]] 1 [ 217.454762] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 217.455236] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 217.455288] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 217.455330] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 217.455378] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 217.455441] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.455489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.455612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.455677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.455736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.456105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.456143] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.456182] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.456220] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.456244] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.456266] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.456287] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.456326] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.456350] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.456374] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.456702] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.456749] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.456787] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.456795] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.456799] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.456835] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.456877] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.456907] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.456938] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.456966] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.456989] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.456994] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.457011] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.457015] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.457033] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.457050] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.457074] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.457097] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.457122] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.457145] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.457170] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.457193] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.457217] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.457253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 217.457280] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.457355] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 217.457393] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.457417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.457441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.457466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.457490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.457541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.457575] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.457606] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.457636] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.457666] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.457694] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.457719] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.457751] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 217.457780] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 217.457833] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 217.459354] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 217.459372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 217.459388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 217.459412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 217.476329] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 217.476347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 217.493270] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 217.495329] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 217.495525] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 217.496663] [drm:intel_enable_pipe [i915]] enabling pipe A [ 217.496690] [drm:intel_mst_enable_dp [i915]] 1 [ 217.499086] [drm:drm_dp_update_payload_part2] payload 0 1 [ 217.500448] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.500470] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.500541] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.501094] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.501685] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 217.501714] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 217.501750] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 217.501811] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 217.501839] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 217.501906] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.501934] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.501982] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.502406] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.502426] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.513726] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.513763] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.513791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.513797] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.513799] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.513825] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.513852] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.513876] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.513901] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.513924] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.513946] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.513951] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.513972] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.513977] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.513998] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.514020] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.514041] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.514062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.514086] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.514108] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.514130] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.514151] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.514171] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.514206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 217.514233] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.530276] [drm:intel_mst_disable_dp [i915]] 1 [ 217.530282] [drm:drm_dp_update_payload_part1] [ 217.531808] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.531841] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.531892] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.532450] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.534226] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.534263] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.534982] [drm:drm_dp_update_payload_part1] removing payload 0 [ 217.535033] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 217.535083] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 217.535156] [drm:intel_disable_pipe [i915]] disabling pipe A [ 217.548585] [drm:intel_mst_post_disable_dp [i915]] 1 [ 217.553316] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 217.553844] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 217.553915] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 217.553963] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 217.554009] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 217.554066] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.554106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.554143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.554179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.554213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.554246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.554281] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.554318] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.554354] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.554390] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.554423] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.554455] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.554512] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.554624] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.554684] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.555195] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.555251] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.555291] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.555299] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.555302] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.555340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.555379] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.555416] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.555451] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.555484] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.555516] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.555572] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.555623] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.555636] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.555689] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.555742] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.555794] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.555844] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.555897] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.555944] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.555992] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.556038] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.556086] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.556174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 217.556234] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.556416] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 217.556496] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.556583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.556638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.556692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.556744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.556797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.556851] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.556906] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.556956] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.557013] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.557064] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.557111] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.557166] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 217.557219] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 217.557317] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 217.559086] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 217.559105] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 217.559125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 217.559146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 217.576007] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 217.576025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 217.592855] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 217.594914] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 217.595108] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 217.596189] [drm:intel_enable_pipe [i915]] enabling pipe A [ 217.596213] [drm:intel_mst_enable_dp [i915]] 1 [ 217.597878] [drm:drm_dp_update_payload_part2] payload 0 1 [ 217.599252] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.599275] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.599329] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.599882] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.600444] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 217.600468] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 217.600497] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 217.600567] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 217.600590] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 217.600631] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.600656] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.600699] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.601141] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.601157] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.613220] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.613245] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.613264] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.613268] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.613269] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.613287] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.613305] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.613321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.613337] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.613353] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.613367] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.613371] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.613390] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.613394] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.613414] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.613434] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.613454] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.613474] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.613494] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.613549] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.613576] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.613869] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.613893] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.613921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 217.613941] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.629886] [drm:intel_mst_disable_dp [i915]] 1 [ 217.629893] [drm:drm_dp_update_payload_part1] [ 217.631430] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.631476] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.631582] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.632256] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.634141] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.634191] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.634485] [drm:drm_dp_update_payload_part1] removing payload 0 [ 217.634655] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 217.634719] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 217.634812] [drm:intel_disable_pipe [i915]] disabling pipe A [ 217.647082] [drm:intel_mst_post_disable_dp [i915]] 1 [ 217.653025] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 217.653471] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 217.653525] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 217.653635] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 217.653700] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 217.653778] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.653830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.653887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.653939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.653991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.654043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.654084] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.654132] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.654178] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.654224] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.654263] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.654300] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.654374] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.654417] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.654465] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.654809] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.654854] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.654886] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.654893] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.654897] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.654932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.654968] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.655001] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.655032] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.655065] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.655097] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.655104] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.655135] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.655142] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.655172] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.655203] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.655235] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.655266] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.655299] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.655327] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.655360] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.655392] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.655423] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.655470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 217.655508] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.655648] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 217.655700] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.655733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.655765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.655799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.655831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.655864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.655896] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.655932] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.655967] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.656001] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.656031] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.656060] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.656098] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 217.656132] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 217.656191] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 217.657761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 217.657798] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 217.657831] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 217.657863] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 217.674797] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 217.674815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 217.691714] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 217.693776] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 217.693973] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 217.695140] [drm:intel_enable_pipe [i915]] enabling pipe A [ 217.695167] [drm:intel_mst_enable_dp [i915]] 1 [ 217.697554] [drm:drm_dp_update_payload_part2] payload 0 1 [ 217.698922] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.698943] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.698996] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.699570] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.700143] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 217.700168] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 217.700200] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 217.700254] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 217.700284] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 217.700340] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.700362] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.700398] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.700846] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.700865] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.712279] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.712314] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.712341] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.712346] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.712348] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.712373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.712399] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.712423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.712446] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.712467] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.712488] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.712526] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.712557] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.712571] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.712607] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.712643] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.712676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.712709] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.712743] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.712777] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.712813] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.712847] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.712878] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.712935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 217.712975] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.728855] [drm:intel_mst_disable_dp [i915]] 1 [ 217.728863] [drm:drm_dp_update_payload_part1] [ 217.730408] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.730448] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.730539] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.731260] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.733213] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.733270] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.733735] [drm:drm_dp_update_payload_part1] removing payload 0 [ 217.733797] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 217.733870] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 217.733977] [drm:intel_disable_pipe [i915]] disabling pipe A [ 217.745630] [drm:intel_mst_post_disable_dp [i915]] 1 [ 217.752891] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 217.753271] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 217.753295] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 217.753314] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 217.753336] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 217.753369] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.753388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.753405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.753422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.753438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.753454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.753471] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.753490] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.753546] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.753577] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.753604] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.753629] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.753675] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.753703] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.753733] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.753988] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.754023] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.754049] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.754056] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.754059] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.754088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.754117] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.754144] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.754169] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.754196] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.754221] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.754227] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.754252] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.754258] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.754281] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.754307] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.754332] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.754357] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.754384] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.754407] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.754435] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.754461] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.754486] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.754547] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 217.754578] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.754671] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 217.754712] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.754738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.754766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.754793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.754819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.754845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.754869] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.754898] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.754926] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.754953] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.754977] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.754999] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.755030] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 217.755057] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 217.755103] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 217.756842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 217.756870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 217.756895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 217.756924] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 217.773852] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 217.773870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 217.790770] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 217.792830] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 217.793028] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 217.794123] [drm:intel_enable_pipe [i915]] enabling pipe A [ 217.794148] [drm:intel_mst_enable_dp [i915]] 1 [ 217.796551] [drm:drm_dp_update_payload_part2] payload 0 1 [ 217.797925] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.797950] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.798005] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.798553] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.799129] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 217.799155] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 217.799186] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 217.799242] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 217.799267] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 217.799328] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.799353] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.799395] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.799830] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.799857] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.811228] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.811270] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.811310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.811316] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.811319] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.811353] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.811387] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.811420] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.811453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.811486] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.811807] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.811817] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.811856] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.811861] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.811889] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.811913] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.811937] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.811960] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.811987] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.812013] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.812038] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.812061] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.812083] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.812124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 217.812155] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.827818] [drm:intel_mst_disable_dp [i915]] 1 [ 217.827825] [drm:drm_dp_update_payload_part1] [ 217.829367] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.829407] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.829502] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.830298] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.832231] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.832283] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.832767] [drm:drm_dp_update_payload_part1] removing payload 0 [ 217.832835] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 217.832906] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 217.833002] [drm:intel_disable_pipe [i915]] disabling pipe A [ 217.845407] [drm:intel_mst_post_disable_dp [i915]] 1 [ 217.851725] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 217.852166] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 217.852211] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 217.852251] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 217.852294] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 217.852351] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.852391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.852430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.852469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.852508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.852604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.852638] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.852673] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.852705] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.852739] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.852768] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.852797] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.852848] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.852879] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.852913] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.853198] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.853237] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.853270] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.853276] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.853278] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.853299] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.853320] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.853340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.853359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.853377] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.853395] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.853399] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.853416] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.853420] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.853438] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.853455] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.853472] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.853489] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.853543] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.853573] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.853603] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.853632] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.853660] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.853706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 217.853741] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.853842] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 217.853890] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.853921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.853951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.853980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.854009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.854037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.854066] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.854098] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.854128] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.854158] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.854186] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.854213] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.854246] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 217.854277] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 217.854328] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 217.855846] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 217.855868] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 217.855887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 217.855906] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 217.872825] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 217.872843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 217.889740] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 217.891808] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 217.892007] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 217.893083] [drm:intel_enable_pipe [i915]] enabling pipe A [ 217.893108] [drm:intel_mst_enable_dp [i915]] 1 [ 217.895513] [drm:drm_dp_update_payload_part2] payload 0 1 [ 217.896883] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.896905] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.896960] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.897509] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.898111] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 217.898139] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 217.898173] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 217.898235] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 217.898261] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 217.898308] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.898335] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.898379] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.898816] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.898857] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.910163] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.910201] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.910230] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.910235] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.910238] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.910265] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.910293] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.910319] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.910344] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.910368] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.910391] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.910396] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.910419] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.910423] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.910446] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.910469] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.910493] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.910578] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.910624] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.910663] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.910703] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.910740] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.910781] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.910843] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 217.910885] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.926809] [drm:intel_mst_disable_dp [i915]] 1 [ 217.926817] [drm:drm_dp_update_payload_part1] [ 217.928361] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.928408] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.928491] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.929184] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.931205] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.931264] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 217.931580] [drm:drm_dp_update_payload_part1] removing payload 0 [ 217.931647] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 217.931722] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 217.931833] [drm:intel_disable_pipe [i915]] disabling pipe A [ 217.943778] [drm:intel_mst_post_disable_dp [i915]] 1 [ 217.950109] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 217.950593] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 217.950653] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 217.950702] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 217.950761] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 217.950816] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.950855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.950890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.950923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.950956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.950989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.951023] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.951059] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.951094] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.951129] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.951161] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.951193] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.951248] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.951282] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.951320] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.951635] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 217.951671] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 217.951700] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 217.951707] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 217.951712] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 217.951741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 217.951771] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 217.951799] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 217.951824] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 217.951851] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 217.951877] [drm:intel_dump_pipe_config [i915]] requested mode: [ 217.951884] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.951909] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 217.951915] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 217.951939] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 217.951962] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 217.951988] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 217.952014] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 217.952043] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 217.952067] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 217.952092] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 217.952118] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 217.952143] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 217.952186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 217.952218] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 217.952314] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 217.952359] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 217.952387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 217.952411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 217.952438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 217.952465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 217.952491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 217.952535] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 217.952565] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 217.952596] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 217.952625] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 217.952653] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 217.952680] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.952712] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 217.952741] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 217.952793] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 217.954323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 217.954351] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 217.954398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 217.954446] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 217.971352] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 217.971372] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 217.988274] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 217.990343] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 217.990542] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 217.991711] [drm:intel_enable_pipe [i915]] enabling pipe A [ 217.991751] [drm:intel_mst_enable_dp [i915]] 1 [ 217.994144] [drm:drm_dp_update_payload_part2] payload 0 1 [ 217.995518] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 217.995540] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 217.995610] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 217.996161] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 217.996753] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 217.996782] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 217.996818] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 217.996903] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 217.996943] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 217.996994] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 217.997022] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 217.997069] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 217.997510] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 217.997556] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.008806] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.008841] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.008868] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.008873] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.008874] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.008900] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.008925] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.008948] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.008970] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.008992] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.009012] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.009017] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.009037] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.009041] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.009062] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.009083] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.009103] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.009122] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.009145] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.009165] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.009186] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.009206] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.009233] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.009272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 218.009302] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.025423] [drm:intel_mst_disable_dp [i915]] 1 [ 218.025429] [drm:drm_dp_update_payload_part1] [ 218.026956] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.026985] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.027059] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.027624] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.029446] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.029480] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.029781] [drm:drm_dp_update_payload_part1] removing payload 0 [ 218.029815] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 218.029844] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 218.029900] [drm:intel_disable_pipe [i915]] disabling pipe A [ 218.043689] [drm:intel_mst_post_disable_dp [i915]] 1 [ 218.049033] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 218.049470] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 218.049510] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 218.049590] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 218.049782] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 218.049833] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.049865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.049896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.049925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.049952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.049980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.050016] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.050056] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.050095] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.050132] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.050169] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.050205] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.050263] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.050301] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.050343] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.050985] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.051030] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.051063] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.051070] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.051073] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.051105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.051137] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.051168] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.051199] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.051227] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.051254] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.051260] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.051287] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.051293] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.051321] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.051348] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.051374] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.051400] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.051431] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.051458] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.051486] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.051557] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.052065] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.052138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 218.052191] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.052321] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 218.052369] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.052401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.052430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.052458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.052486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.052552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.052857] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.052908] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.052958] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.053006] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.053050] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.053093] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.053144] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 218.053179] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 218.053230] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 218.054731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 218.054750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 218.054766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 218.054787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 218.071704] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 218.071722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 218.088622] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 218.090660] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 218.090858] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 218.091960] [drm:intel_enable_pipe [i915]] enabling pipe A [ 218.091987] [drm:intel_mst_enable_dp [i915]] 1 [ 218.094388] [drm:drm_dp_update_payload_part2] payload 0 1 [ 218.095767] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.095788] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.095856] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.096408] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.097008] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 218.097039] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 218.097076] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 218.097140] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 218.097181] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 218.097233] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.097263] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.097310] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.097716] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.097749] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.109055] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.109091] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.109118] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.109124] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.109126] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.109152] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.109179] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.109208] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.109238] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.109267] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.109296] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.109302] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.109330] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.109335] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.109365] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.109394] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.109424] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.109452] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.109482] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.109567] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.109609] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.109646] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.109682] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.109741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 218.109778] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.125656] [drm:intel_mst_disable_dp [i915]] 1 [ 218.125663] [drm:drm_dp_update_payload_part1] [ 218.127204] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.127252] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.127362] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.127996] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.129928] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.129981] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.130290] [drm:drm_dp_update_payload_part1] removing payload 0 [ 218.130333] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 218.130378] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 218.130443] [drm:intel_disable_pipe [i915]] disabling pipe A [ 218.143780] [drm:intel_mst_post_disable_dp [i915]] 1 [ 218.148790] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 218.149256] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 218.149309] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 218.149350] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 218.149398] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 218.149460] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.149511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.149603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.149633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.149663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.149705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.149751] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.149799] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.149845] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.149889] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.149916] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.149942] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.149990] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.150018] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.150048] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.150304] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.150340] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.150369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.150375] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.150378] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.150406] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.150434] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.150462] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.150490] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.150568] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.150596] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.150605] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.150632] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.150640] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.150669] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.150696] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.150722] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.150748] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.150779] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.150806] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.150836] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.150862] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.150888] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.150941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 218.150990] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.151140] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 218.151205] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.151249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.151284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.151311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.151336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.151361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.151387] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.151415] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.151442] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.151468] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.151492] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.151538] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.151575] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 218.151614] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 218.151667] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 218.154258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 218.154305] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 218.154347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 218.154392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 218.171346] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 218.171364] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 218.188244] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 218.190313] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 218.190509] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 218.191638] [drm:intel_enable_pipe [i915]] enabling pipe A [ 218.191674] [drm:intel_mst_enable_dp [i915]] 1 [ 218.194054] [drm:drm_dp_update_payload_part2] payload 0 1 [ 218.195430] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.195452] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.195510] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.196069] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.196639] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 218.196670] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 218.196699] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 218.196752] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 218.196775] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 218.196821] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.196846] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.196884] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.197342] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.197359] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.208666] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.208701] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.208727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.208732] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.208734] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.208759] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.208784] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.208807] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.208829] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.208854] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.208881] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.208885] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.208912] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.208916] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.208944] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.208971] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.208999] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.209025] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.209053] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.209079] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.209107] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.209134] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.209161] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.209200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 218.209229] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.225267] [drm:intel_mst_disable_dp [i915]] 1 [ 218.225275] [drm:drm_dp_update_payload_part1] [ 218.226826] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.226881] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.227004] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.227709] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.229702] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.229760] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.230072] [drm:drm_dp_update_payload_part1] removing payload 0 [ 218.230127] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 218.230182] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 218.230261] [drm:intel_disable_pipe [i915]] disabling pipe A [ 218.243796] [drm:intel_mst_post_disable_dp [i915]] 1 [ 218.249715] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 218.250153] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 218.250193] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 218.250225] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 218.250263] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 218.250311] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.250344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.250375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.250404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.250432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.250460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.250490] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.250582] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.250631] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.250677] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.250720] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.250779] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.250870] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.250926] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.250988] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.251546] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.251582] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.251612] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.251619] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.251622] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.251650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.251679] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.251707] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.251730] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.251747] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.251763] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.251767] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.251782] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.251786] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.251802] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.251818] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.251834] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.251854] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.251882] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.251908] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.251931] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.251947] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.251969] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.252008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 218.252029] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.252101] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 218.252136] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.252154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.252172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.252195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.252221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.252237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.252254] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.252271] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.252288] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.252311] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.252336] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.252352] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.252371] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 218.252389] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 218.252421] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 218.254072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 218.254093] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 218.254111] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 218.254130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 218.271049] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 218.271067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 218.287964] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 218.290024] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 218.290220] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 218.291317] [drm:intel_enable_pipe [i915]] enabling pipe A [ 218.291346] [drm:intel_mst_enable_dp [i915]] 1 [ 218.293737] [drm:drm_dp_update_payload_part2] payload 0 1 [ 218.295106] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.295127] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.295182] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.295737] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.296316] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 218.296345] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 218.296380] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 218.296443] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 218.296470] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 218.296574] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.296605] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.296653] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.297955] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.297977] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.308392] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.308426] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.308452] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.308457] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.308460] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.308485] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.308548] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.308584] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.308620] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.308653] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.308688] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.308696] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.308726] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.308734] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.308766] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.308798] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.308832] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.308865] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.308902] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.308936] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.308971] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.309001] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.309023] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.309059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 218.309086] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.325004] [drm:intel_mst_disable_dp [i915]] 1 [ 218.325012] [drm:drm_dp_update_payload_part1] [ 218.326562] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.326610] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.326711] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.327358] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.329346] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.329404] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.329762] [drm:drm_dp_update_payload_part1] removing payload 0 [ 218.329836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 218.329896] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 218.329983] [drm:intel_disable_pipe [i915]] disabling pipe A [ 218.341763] [drm:intel_mst_post_disable_dp [i915]] 1 [ 218.348296] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 218.348832] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 218.348882] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 218.348936] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 218.348982] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 218.349040] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.349079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.349118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.349154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.349199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.349244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.349288] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.349336] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.349383] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.349431] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.349474] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.349518] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.349669] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.349759] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.349824] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.350167] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.350224] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.350262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.350270] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.350274] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.350311] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.350347] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.350375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.350397] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.350418] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.350437] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.350442] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.350461] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.350465] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.350486] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.350540] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.350572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.350601] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.350634] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.350665] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.350698] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.350730] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.350765] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.350819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 218.350939] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.351068] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 218.351134] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.351170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.351204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.351238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.351268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.351298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.351329] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.351365] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.351401] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.351435] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.351467] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.351506] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.351580] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 218.351606] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 218.351658] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 218.353132] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 218.353149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 218.353165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 218.353181] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 218.370066] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 218.370084] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 218.386958] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 218.388553] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 218.388750] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 218.389903] [drm:intel_enable_pipe [i915]] enabling pipe A [ 218.389930] [drm:intel_mst_enable_dp [i915]] 1 [ 218.391870] [drm:drm_dp_update_payload_part2] payload 0 1 [ 218.393240] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.393262] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.393309] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.393875] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.394446] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 218.394469] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 218.394499] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 218.394566] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 218.394591] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 218.394636] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.394662] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.394703] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.395806] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.395823] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.406996] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.407023] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.407044] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.407048] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.407049] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.407069] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.407088] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.407106] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.407123] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.407140] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.407155] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.407159] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.407175] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.407178] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.407194] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.407209] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.407224] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.407239] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.407257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.407272] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.407289] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.407304] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.407318] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.407345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 218.407365] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.423607] [drm:intel_mst_disable_dp [i915]] 1 [ 218.423614] [drm:drm_dp_update_payload_part1] [ 218.425150] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.425195] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.425276] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.425938] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.427949] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.427997] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.428296] [drm:drm_dp_update_payload_part1] removing payload 0 [ 218.428337] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 218.428384] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 218.428453] [drm:intel_disable_pipe [i915]] disabling pipe A [ 218.441740] [drm:intel_mst_post_disable_dp [i915]] 1 [ 218.447292] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 218.447825] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 218.447859] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 218.447885] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 218.447915] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 218.447957] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.447984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.448009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.448033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.448056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.448078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.448101] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.448127] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.448151] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.448174] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.448195] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.448217] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.448257] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.448281] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.448307] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.448604] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.448649] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.448684] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.448692] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.448696] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.448732] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.448767] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.448802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.448836] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.448869] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.448901] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.448909] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.448940] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.448946] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.448979] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.449011] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.449043] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.449075] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.449110] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.449141] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.449175] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.449206] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.449237] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.449290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 218.449329] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.449455] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 218.449510] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.449567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.449605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.449639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.449675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.449710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.449747] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.449785] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.449823] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.449861] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.449896] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.449929] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.449968] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 218.450006] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 218.450069] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 218.451905] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 218.451924] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 218.451940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 218.451958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 218.468849] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 218.468867] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 218.485741] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 218.487557] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 218.487766] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 218.488945] [drm:intel_enable_pipe [i915]] enabling pipe A [ 218.488973] [drm:intel_mst_enable_dp [i915]] 1 [ 218.491368] [drm:drm_dp_update_payload_part2] payload 0 1 [ 218.492752] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.492776] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.492836] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.493381] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.494029] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 218.494054] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 218.494086] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 218.494140] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 218.494164] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 218.494209] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.494234] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.494274] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.494733] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.494760] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.506023] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.506053] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.506078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.506082] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.506084] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.506109] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.506133] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.506156] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.506180] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.506203] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.506226] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.506230] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.506254] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.506257] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.506281] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.506305] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.506328] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.506351] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.506375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.506397] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.506422] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.506445] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.506469] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.506555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 218.506604] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.522662] [drm:intel_mst_disable_dp [i915]] 1 [ 218.522669] [drm:drm_dp_update_payload_part1] [ 218.524202] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.524240] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.524308] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.524936] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.526819] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.526880] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.527186] [drm:drm_dp_update_payload_part1] removing payload 0 [ 218.527235] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 218.527287] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 218.527386] [drm:intel_disable_pipe [i915]] disabling pipe A [ 218.539724] [drm:intel_mst_post_disable_dp [i915]] 1 [ 218.546021] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 218.546456] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 218.546483] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 218.546547] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 218.546585] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 218.546635] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.546665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.546693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.546723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.546752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.546781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.546810] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.546843] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.546874] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.546905] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.546931] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.546957] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.547007] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.547037] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.547069] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.547354] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.547391] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.547419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.547426] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.547429] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.547461] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.547492] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.547548] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.547578] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.547610] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.547640] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.547649] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.547679] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.547688] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.547720] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.547750] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.547780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.547807] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.547838] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.547870] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.547901] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.547929] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.547957] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.548003] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 218.548037] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.548140] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 218.548186] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.548214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.548245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.548274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.548302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.548329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.548356] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.548388] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.548419] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.548449] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.548474] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.548500] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.548554] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 218.548587] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 218.548640] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 218.550158] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 218.550188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 218.550218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 218.550249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 218.567190] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 218.567208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 218.584112] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 218.586181] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 218.586381] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 218.587545] [drm:intel_enable_pipe [i915]] enabling pipe A [ 218.587570] [drm:intel_mst_enable_dp [i915]] 1 [ 218.589971] [drm:drm_dp_update_payload_part2] payload 0 1 [ 218.591353] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.591374] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.591427] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.591973] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.592600] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 218.592624] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 218.592655] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 218.592709] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 218.592732] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 218.592790] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.592815] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.592857] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.593283] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.593301] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.604669] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.604702] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.604727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.604732] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.604734] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.604758] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.604781] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.604803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.604825] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.604846] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.604865] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.604870] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.604889] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.604893] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.604913] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.604933] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.604952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.604971] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.604993] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.605012] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.605033] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.605052] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.605071] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.605104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 218.605129] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.621285] [drm:intel_mst_disable_dp [i915]] 1 [ 218.621293] [drm:drm_dp_update_payload_part1] [ 218.622841] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.622892] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.622997] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.623650] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.625633] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.625690] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.625992] [drm:drm_dp_update_payload_part1] removing payload 0 [ 218.626040] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 218.626088] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 218.626161] [drm:intel_disable_pipe [i915]] disabling pipe A [ 218.639813] [drm:intel_mst_post_disable_dp [i915]] 1 [ 218.644541] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 218.645043] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 218.645105] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 218.645154] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 218.645211] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 218.645281] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.645332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.645379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.645423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.645466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.645508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.645632] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.645714] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.645789] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.645863] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.645925] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.645986] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.646103] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.646158] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.646217] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.646755] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.646824] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.646899] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.646916] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.646920] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.646971] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.647019] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.647065] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.647129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.647194] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.647237] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.647249] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.647289] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.647298] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.647339] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.647381] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.647447] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.647513] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.647634] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.647701] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.647772] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.647839] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.647904] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.648013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 218.648091] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.648327] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 218.648429] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.648502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.648609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.648678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.648747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.648814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.648884] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.648961] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.649033] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.649105] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.649172] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.649239] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.649316] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 218.649387] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 218.649504] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 218.651143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 218.651161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 218.651177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 218.651194] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 218.668112] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 218.668129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 218.685026] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 218.687084] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 218.687279] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 218.688364] [drm:intel_enable_pipe [i915]] enabling pipe A [ 218.688390] [drm:intel_mst_enable_dp [i915]] 1 [ 218.690772] [drm:drm_dp_update_payload_part2] payload 0 1 [ 218.692149] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.692170] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.692223] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.692765] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.693332] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 218.693357] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 218.693388] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 218.693441] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 218.693465] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 218.693626] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.693651] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.693693] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.694167] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.694193] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.705474] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.705530] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.705560] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.705566] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.705568] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.705596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.705625] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 218.705651] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 218.705677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.705701] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.705724] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.705730] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.705753] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.705757] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.705781] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.705805] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.705828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.705850] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.705877] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.705900] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.705924] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:93, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.705947] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 218.705970] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 218.706009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 218.706038] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 218.722059] [drm:intel_mst_disable_dp [i915]] 1 [ 218.722067] [drm:drm_dp_update_payload_part1] [ 218.723610] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.723666] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.723791] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.724458] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.726440] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.726505] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.726871] [drm:drm_dp_update_payload_part1] removing payload 0 [ 218.726943] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 218.727013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 218.727092] [drm:intel_disable_pipe [i915]] disabling pipe A [ 218.738763] [drm:intel_mst_post_disable_dp [i915]] 1 [ 218.746238] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 218.746860] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 218.746897] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 1, on? 1) for crtc 32 [ 218.746926] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 218.746959] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 218.747004] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.747034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.747061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.747087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.747113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.747138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.747164] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.747192] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.747218] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.747244] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.747268] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.747292] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.747334] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.747360] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.747388] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.747897] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.747989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 218.748612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.748641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.748667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.748691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.748717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.748743] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.748769] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.748799] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.748825] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.748851] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.748875] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.748898] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.748946] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 218.749196] [drm:drm_mode_addfb2] [FB:66] [ 218.749232] [drm:drm_mode_addfb2] [FB:70] [ 218.817057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A] [ 218.817144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B] [ 218.817194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C] [ 218.817240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B] [ 218.817257] [drm:drm_mode_setcrtc] [CONNECTOR:60:DP-2] [ 218.817309] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.817326] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.817335] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.817337] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.817353] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.817370] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 218.817385] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 218.817400] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.817414] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.817428] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.817431] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.817445] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.817448] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.817461] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.817475] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.817518] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.817540] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.817564] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.817584] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.817605] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0 [ 218.817625] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 218.817646] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 218.817680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 218.817709] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 218.826888] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 218.826921] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.826939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.826957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.826973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.826992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.827011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.827031] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.827052] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.827073] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.827093] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.827112] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.827131] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.827152] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 218.827171] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 218.827233] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 218.828715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 218.828732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 218.828748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 218.828765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 218.845680] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 218.845697] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 218.862595] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 218.864664] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 218.864863] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 218.866023] [drm:intel_enable_pipe [i915]] enabling pipe B [ 218.866261] [drm:intel_mst_enable_dp [i915]] 1 [ 218.866616] [drm:drm_dp_update_payload_part2] payload 0 1 [ 218.867991] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.868013] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.868073] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.868620] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.869186] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 218.869209] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 218.869238] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 218.869935] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.869953] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.883023] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.883059] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 218.883110] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.916421] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.916449] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.916471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.916475] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.916509] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.916539] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.916571] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 218.916600] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 218.916626] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.916742] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.916764] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.916770] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.916794] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.916799] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.916824] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.916848] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.916870] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.916891] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.916918] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.916942] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.916966] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.916989] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 218.917010] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 218.917048] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 218.917077] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 218.933087] [drm:intel_mst_disable_dp [i915]] 1 [ 218.933094] [drm:drm_dp_update_payload_part1] [ 218.934626] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 218.934664] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 218.934734] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 218.935324] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 218.937167] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 218.937211] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 218.937521] [drm:drm_dp_update_payload_part1] removing payload 0 [ 218.937578] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 218.937639] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 218.937724] [drm:intel_disable_pipe [i915]] disabling pipe B [ 218.949658] [drm:intel_mst_post_disable_dp [i915]] 1 [ 218.956317] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 218.956861] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 218.956893] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 218.956927] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 218.956971] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.957000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.957026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.957052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.957077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.957102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.957129] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.957157] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.957184] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.957210] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.957235] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.957259] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.957302] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 218.957328] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 218.957357] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.957681] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 218.957733] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 218.957773] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 218.957784] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 218.957788] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 218.957830] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 218.957873] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 218.957911] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 218.957953] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 218.957993] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 218.958030] [drm:intel_dump_pipe_config [i915]] requested mode: [ 218.958040] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.958077] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 218.958086] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 218.958125] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 218.958160] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 218.958200] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 218.958237] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 218.958280] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 218.958317] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 218.958359] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 218.958396] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 218.958440] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 218.958502] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 218.958557] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 218.958665] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 218.958715] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 218.958748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 218.958780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 218.958810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 218.958842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 218.958872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 218.958904] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 218.958936] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 218.958969] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 218.959001] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 218.959031] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 218.959059] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 218.959095] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 218.959128] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 218.959183] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 218.961046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 218.961082] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 218.961114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 218.961150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 218.978087] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 218.978105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 218.995004] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 218.997072] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 218.997271] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 218.998366] [drm:intel_enable_pipe [i915]] enabling pipe B [ 218.998394] [drm:intel_mst_enable_dp [i915]] 1 [ 219.000787] [drm:drm_dp_update_payload_part2] payload 0 1 [ 219.002164] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.002186] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.002242] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.002795] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.003374] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 219.003402] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 219.003436] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 219.003541] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.003573] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.003622] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.004282] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.004311] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.015452] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.015491] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.015580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.015591] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.015595] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.015633] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.015670] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.015706] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.015741] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.015775] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.015808] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.015816] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.015847] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.015854] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.015888] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.015921] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.015953] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.015985] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.016021] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.016054] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.016088] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.016121] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.016153] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.016207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 219.016247] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.032071] [drm:intel_mst_disable_dp [i915]] 1 [ 219.032079] [drm:drm_dp_update_payload_part1] [ 219.033631] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.033674] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.033803] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.034449] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.036444] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.036506] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.037243] [drm:drm_dp_update_payload_part1] removing payload 0 [ 219.037299] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 219.037353] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 219.037435] [drm:intel_disable_pipe [i915]] disabling pipe B [ 219.048588] [drm:intel_mst_post_disable_dp [i915]] 1 [ 219.055262] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 219.055695] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 219.055726] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 219.055752] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 219.055788] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.055809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.055829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.055848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.055867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.055890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.055915] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.055941] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.055966] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.055991] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.056014] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.056037] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.056076] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.056101] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.056128] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.056312] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.056340] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.056364] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.056369] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.056371] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.056396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.056420] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.056443] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.056467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.056491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.056548] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.056903] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.056937] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.056943] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.056976] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.057008] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.057039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.057068] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.057092] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.057111] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.057130] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.057148] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.057165] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.057196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 219.057221] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.057290] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 219.057323] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.057343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.057362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.057380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.057397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.057415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.057433] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.057452] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.057471] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.057515] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.057867] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.057898] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.057933] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 219.057964] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 219.058011] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 219.059519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 219.059541] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 219.059560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 219.059580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 219.076516] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 219.076533] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 219.093428] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 219.095505] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 219.095704] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 219.096863] [drm:intel_enable_pipe [i915]] enabling pipe B [ 219.096888] [drm:intel_mst_enable_dp [i915]] 1 [ 219.099282] [drm:drm_dp_update_payload_part2] payload 0 1 [ 219.100664] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.100688] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.100743] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.101279] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.101848] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 219.101879] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 219.101908] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 219.101968] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.101990] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.102030] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.102542] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.102559] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.113966] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.114000] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.114026] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.114031] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.114033] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.114058] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.114083] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.114107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.114130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.114152] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.114173] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.114178] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.114198] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.114202] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.114223] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.114243] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.114263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.114283] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.114307] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.114327] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.114348] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.114368] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.114388] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.114427] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 219.114459] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.130593] [drm:intel_mst_disable_dp [i915]] 1 [ 219.130599] [drm:drm_dp_update_payload_part1] [ 219.132121] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.132153] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.132213] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.132786] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.134709] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.134768] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.135076] [drm:drm_dp_update_payload_part1] removing payload 0 [ 219.135124] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 219.135174] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 219.135250] [drm:intel_disable_pipe [i915]] disabling pipe B [ 219.148794] [drm:intel_mst_post_disable_dp [i915]] 1 [ 219.153829] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 219.154317] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 219.154365] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 219.154417] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 219.154482] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.154621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.154691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.154758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.154821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.154878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.154938] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.155011] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.155079] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.155147] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.155204] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.155260] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.155368] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.155435] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.155506] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.155890] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.155933] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.155968] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.155976] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.155979] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.156017] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.156055] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.156091] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.156124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.156159] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.156192] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.156199] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.156232] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.156239] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.156270] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.156300] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.156333] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.156366] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.156403] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.156434] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.156466] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.156500] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.156557] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.156613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 219.156658] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.156773] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 219.156814] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.156840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.156863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.156888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.156912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.156936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.156960] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.156987] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.157012] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.157038] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.157060] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.157081] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.157109] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 219.157134] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 219.157176] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 219.158655] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 219.158673] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 219.158689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 219.158704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 219.175604] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 219.175623] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 219.192523] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 219.194583] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 219.194780] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 219.195985] [drm:intel_enable_pipe [i915]] enabling pipe B [ 219.196009] [drm:intel_mst_enable_dp [i915]] 1 [ 219.198393] [drm:drm_dp_update_payload_part2] payload 0 1 [ 219.199765] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.199788] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.199841] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.200380] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.201029] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 219.201052] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 219.201080] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 219.201143] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.201166] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.201219] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.201712] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.201729] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.213102] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.213138] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.213166] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.213172] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.213174] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.213200] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.213227] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.213251] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.213275] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.213298] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.213320] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.213325] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.213347] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.213351] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.213374] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.213396] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.213417] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.213438] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.213463] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.213484] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.213555] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.213970] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.214009] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.214068] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 219.214102] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.229659] [drm:intel_mst_disable_dp [i915]] 1 [ 219.229666] [drm:drm_dp_update_payload_part1] [ 219.231201] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.231236] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.231320] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.232061] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.233930] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.233981] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.234292] [drm:drm_dp_update_payload_part1] removing payload 0 [ 219.234335] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 219.234377] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 219.234439] [drm:intel_disable_pipe [i915]] disabling pipe B [ 219.246754] [drm:intel_mst_post_disable_dp [i915]] 1 [ 219.253690] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 219.254121] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 219.254156] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 219.254193] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 219.254242] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.254275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.254306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.254336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.254364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.254391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.254421] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.254452] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.254486] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.254585] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.254634] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.254682] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.254758] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.254807] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.254859] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.255248] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.255307] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.255347] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.255355] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.255359] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.255398] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.255437] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.255475] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.255539] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.255576] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.255614] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.255624] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.255659] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.255670] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.255707] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.255741] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.255780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.255814] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.255855] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.255888] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.255921] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.255957] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.255991] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.256046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 219.256091] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.256210] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 219.256268] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.256307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.256343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.256376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.256411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.256447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.256483] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.256547] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.256590] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.256630] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.256668] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.256702] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.256741] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 219.256783] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 219.256847] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 219.258401] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 219.258438] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 219.258475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 219.258546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 219.275470] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 219.275501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 219.292399] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 219.294467] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 219.294679] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 219.295881] [drm:intel_enable_pipe [i915]] enabling pipe B [ 219.295906] [drm:intel_mst_enable_dp [i915]] 1 [ 219.298297] [drm:drm_dp_update_payload_part2] payload 0 1 [ 219.299670] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.299694] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.299748] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.300287] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.300867] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 219.300890] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 219.300918] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 219.300980] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.301003] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.301053] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.301603] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.301629] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.312929] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.312964] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.312990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.312995] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.312997] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.313021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.313046] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.313069] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.313092] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.313113] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.313134] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.313139] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.313159] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.313163] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.313184] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.313205] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.313226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.313245] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.313269] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.313289] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.313310] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.313330] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.313350] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.313388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 219.313419] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.329587] [drm:intel_mst_disable_dp [i915]] 1 [ 219.329594] [drm:drm_dp_update_payload_part1] [ 219.331143] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.331190] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.331265] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.331933] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.333854] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.333904] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.334214] [drm:drm_dp_update_payload_part1] removing payload 0 [ 219.334267] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 219.334314] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 219.334382] [drm:intel_disable_pipe [i915]] disabling pipe B [ 219.347862] [drm:intel_mst_post_disable_dp [i915]] 1 [ 219.353263] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 219.353801] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 219.353840] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 219.353883] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 219.353939] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.353979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.354019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.354058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.354097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.354136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.354174] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.354215] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.354255] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.354296] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.354334] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.354372] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.354433] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.354473] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.354582] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.354955] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.355021] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.355075] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.355086] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.355090] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.355144] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.355197] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.355234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.355266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.355296] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.355324] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.355330] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.355358] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.355364] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.355392] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.355420] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.355448] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.355475] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.355555] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.355599] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.355645] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.355690] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.355732] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.355806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 219.355864] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.356024] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 219.356096] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.356147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.356194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.356224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.356254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.356284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.356316] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.356348] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.356379] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.356409] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.356437] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.356467] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.356537] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 219.356586] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 219.356669] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 219.358224] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 219.358243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 219.358259] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 219.358276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 219.375276] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 219.375294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 219.392127] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 219.394195] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 219.394398] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 219.395488] [drm:intel_enable_pipe [i915]] enabling pipe B [ 219.395528] [drm:intel_mst_enable_dp [i915]] 1 [ 219.397936] [drm:drm_dp_update_payload_part2] payload 0 1 [ 219.399312] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.399335] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.399390] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.399934] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.400509] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 219.400538] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 219.400572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 219.400646] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.400671] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.400731] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.401228] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.401245] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.412573] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.412608] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.412634] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.412639] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.412641] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.412666] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.412692] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.412715] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.412738] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.412759] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.412780] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.412785] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.412805] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.412809] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.412830] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.412851] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.412871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.412890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.412914] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.412935] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.412957] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.412977] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.412996] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.413030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 219.413057] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.429172] [drm:intel_mst_disable_dp [i915]] 1 [ 219.429179] [drm:drm_dp_update_payload_part1] [ 219.430703] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.430735] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.430816] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.431444] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.433456] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.433514] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.433829] [drm:drm_dp_update_payload_part1] removing payload 0 [ 219.433891] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 219.433943] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 219.434038] [drm:intel_disable_pipe [i915]] disabling pipe B [ 219.445870] [drm:intel_mst_post_disable_dp [i915]] 1 [ 219.453267] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 219.453729] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 219.453758] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 219.453789] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 219.453830] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.453857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.453882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.453905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.453928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.453951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.453975] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.454000] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.454024] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.454048] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.454069] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.454090] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.454129] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.454153] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.454179] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.454389] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.454419] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.454443] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.454448] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.454450] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.454477] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.454558] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.454597] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.454635] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.454669] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.454703] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.454715] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.454751] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.454761] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.454799] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.454835] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.454867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.454919] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.454961] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.454997] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.455065] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.455127] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.455160] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.455218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 219.455266] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.455386] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 219.455440] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.455476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.455560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.455610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.455644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.455677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.455739] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.455797] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.455835] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.455870] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.455903] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.455934] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.455992] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 219.456053] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 219.456114] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 219.457733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 219.457772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 219.457807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 219.457841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 219.474778] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 219.474798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 219.491697] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 219.493765] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 219.493963] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 219.495095] [drm:intel_enable_pipe [i915]] enabling pipe B [ 219.495120] [drm:intel_mst_enable_dp [i915]] 1 [ 219.497513] [drm:drm_dp_update_payload_part2] payload 0 1 [ 219.498889] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.498910] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.498971] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.499541] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.500108] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 219.500131] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 219.500159] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 219.500222] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.500244] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.500295] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.500802] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.500820] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.512223] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.512257] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.512284] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.512289] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.512291] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.512316] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.512341] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.512365] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.512388] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.512409] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.512430] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.512435] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.512455] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.512459] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.512480] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.512554] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.512588] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.512620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.512656] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.512688] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.512721] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.512755] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.512787] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.512841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 219.512883] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.528897] [drm:intel_mst_disable_dp [i915]] 1 [ 219.528904] [drm:drm_dp_update_payload_part1] [ 219.530436] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.530473] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.530554] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.531171] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.533048] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.533107] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.533411] [drm:drm_dp_update_payload_part1] removing payload 0 [ 219.533468] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 219.533587] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 219.533705] [drm:intel_disable_pipe [i915]] disabling pipe B [ 219.545645] [drm:intel_mst_post_disable_dp [i915]] 1 [ 219.551930] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 219.552358] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 219.552390] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 219.552425] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 219.552472] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.552549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.552596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.552641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.552682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.552726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.552771] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.552819] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.552864] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.552906] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.552945] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.552983] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.553052] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.553093] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.553137] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.553546] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.553587] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.553620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.553628] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.553631] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.553663] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.553696] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.553727] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.553758] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.553788] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.553817] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.553826] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.553856] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.553864] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.553894] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.553923] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.553953] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.553981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.554014] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.554043] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.554074] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.554104] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.554133] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.554182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 219.554219] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.554325] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 219.554374] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.554406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.554437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.554467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.554520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.554548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.554578] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.554611] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.554643] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.554673] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.554702] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.554731] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.554765] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 219.554796] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 219.554849] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 219.556357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 219.556379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 219.556400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 219.556420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 219.573366] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 219.573382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 219.590279] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 219.592348] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 219.592547] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 219.593757] [drm:intel_enable_pipe [i915]] enabling pipe B [ 219.593784] [drm:intel_mst_enable_dp [i915]] 1 [ 219.596175] [drm:drm_dp_update_payload_part2] payload 0 1 [ 219.597559] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.597582] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.597636] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.598177] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.598752] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 219.598777] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 219.598809] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 219.598883] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.598906] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.598961] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.599450] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.599467] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.610830] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.610864] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.610890] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.610895] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.610897] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.610921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.610945] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.610970] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.610998] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.611025] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.611051] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.611056] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.611082] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.611086] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.611113] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.611140] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.611167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.611193] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.611220] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.611245] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.611273] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.611300] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.611327] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.611365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 219.611396] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.627485] [drm:intel_mst_disable_dp [i915]] 1 [ 219.627529] [drm:drm_dp_update_payload_part1] [ 219.629082] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.629137] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.629237] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.629955] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.632029] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.632088] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.632401] [drm:drm_dp_update_payload_part1] removing payload 0 [ 219.632459] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 219.632576] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 219.632694] [drm:intel_disable_pipe [i915]] disabling pipe B [ 219.644718] [drm:intel_mst_post_disable_dp [i915]] 1 [ 219.651844] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 219.652281] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 219.652317] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 219.652354] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 219.652403] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.652436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.652466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.652563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.652614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.652663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.652719] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.652759] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.652805] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.652848] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.652886] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.652922] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.652990] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.653032] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.653077] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.653449] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.653502] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.653576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.653589] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.653595] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.653642] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.653689] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.653731] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.653768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.653809] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.653848] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.653857] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.653894] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.653902] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.653938] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.653973] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.654013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.654050] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.654093] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.654130] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.654167] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.654207] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.654245] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.654306] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 219.654355] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.654488] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 219.654578] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.654624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.654668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.654706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.654748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.654790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.654834] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.654875] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.654920] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.654961] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.655002] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.655037] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.655077] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 219.655119] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 219.655188] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 219.656709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 219.656734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 219.656760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 219.656786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 219.673711] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 219.673729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 219.690627] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 219.692695] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 219.692893] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 219.694006] [drm:intel_enable_pipe [i915]] enabling pipe B [ 219.694033] [drm:intel_mst_enable_dp [i915]] 1 [ 219.696421] [drm:drm_dp_update_payload_part2] payload 0 1 [ 219.697790] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.697812] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.697874] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.698416] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.698990] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 219.699014] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 219.699042] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 219.699105] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.699128] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.699170] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.699689] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.699715] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.711021] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.711051] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.711073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.711078] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.711080] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.711100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.711121] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.711141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.711160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.711178] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.711195] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.711199] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.711216] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.711220] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.711238] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.711255] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.711273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.711290] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.711310] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.711327] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.711345] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.711362] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.711380] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.711408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 219.711431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.727674] [drm:intel_mst_disable_dp [i915]] 1 [ 219.727680] [drm:drm_dp_update_payload_part1] [ 219.729220] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.729259] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.729342] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.730065] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.731954] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.732003] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.732314] [drm:drm_dp_update_payload_part1] removing payload 0 [ 219.732361] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 219.732405] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 219.732469] [drm:intel_disable_pipe [i915]] disabling pipe B [ 219.744907] [drm:intel_mst_post_disable_dp [i915]] 1 [ 219.751693] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 219.752129] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 219.752164] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 219.752201] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 219.752250] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.752283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.752313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.752342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.752370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.752398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.752427] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.752458] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.752488] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.752580] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.752623] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.752664] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.752741] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.752788] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.752840] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.753207] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.753268] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.753317] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.753327] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.753332] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.753378] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.753402] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.753424] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.753445] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.753466] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.753517] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.753527] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.753556] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.753564] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.753593] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.753623] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.753654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.753682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.753716] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.753746] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.753778] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.753811] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.753843] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.753896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 219.753936] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.754046] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 219.754084] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.754107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.754129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.754150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.754171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.754192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.754213] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.754235] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.754257] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.754278] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.754299] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.754319] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.754343] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 219.754365] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 219.754402] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 219.756061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 219.756081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 219.756099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 219.756117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 219.773037] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 219.773054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 219.789954] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 219.792023] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 219.792221] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 219.793307] [drm:intel_enable_pipe [i915]] enabling pipe B [ 219.793335] [drm:intel_mst_enable_dp [i915]] 1 [ 219.795741] [drm:drm_dp_update_payload_part2] payload 0 1 [ 219.797124] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.797147] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.797190] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.797735] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.798302] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 219.798328] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 219.798359] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 219.798426] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.798450] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.799025] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.799043] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.799167] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.810381] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.810419] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.810447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.810452] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.810455] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.810482] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.810548] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.810587] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.810622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.810655] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.810686] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.810695] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.810728] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.810736] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.810767] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.810798] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.810829] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.810863] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.810899] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.810934] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.810969] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.811002] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.811034] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.811073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 219.811102] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.827007] [drm:intel_mst_disable_dp [i915]] 1 [ 219.827014] [drm:drm_dp_update_payload_part1] [ 219.828546] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.828584] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.828673] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.829292] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.831201] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.831250] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.831562] [drm:drm_dp_update_payload_part1] removing payload 0 [ 219.831627] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 219.831694] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 219.831779] [drm:intel_disable_pipe [i915]] disabling pipe B [ 219.845482] [drm:intel_mst_post_disable_dp [i915]] 1 [ 219.850544] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 219.850986] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 219.851015] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 219.851047] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 219.851091] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.851119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.851146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.851170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.851194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.851218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.851243] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.851270] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.851295] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.851321] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.851344] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.851367] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.851408] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.851434] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.851461] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.852043] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.852078] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.852106] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.852112] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.852114] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.852140] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.852167] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.852192] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.852216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.852239] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.852262] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.852267] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.852289] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.852294] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.852317] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.852339] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.852361] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.852382] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.852408] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.852431] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.852454] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.852476] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.852546] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.852971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 219.853005] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.853090] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 219.853130] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.853155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.853179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.853202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.853224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.853245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.853268] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.853292] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.853316] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.853339] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.853360] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.853381] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.853407] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 219.853431] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 219.853476] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 219.855057] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 219.855085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 219.855110] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 219.855135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 219.872036] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 219.872055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 219.888929] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 219.890997] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 219.891202] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 219.892298] [drm:intel_enable_pipe [i915]] enabling pipe B [ 219.892325] [drm:intel_mst_enable_dp [i915]] 1 [ 219.894727] [drm:drm_dp_update_payload_part2] payload 0 1 [ 219.896099] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.896120] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.896152] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.896690] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.897258] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 219.897283] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 219.897314] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 219.897381] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.897406] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.897463] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.897963] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.897979] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.909303] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.909332] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.909357] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.909361] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.909363] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.909388] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.909411] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.909435] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.909459] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.909482] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.909536] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.909546] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.909575] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.909582] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.909610] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.909638] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.909664] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.909690] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.909720] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.909746] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.909772] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.909798] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.909822] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.909866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 219.909899] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.925940] [drm:intel_mst_disable_dp [i915]] 1 [ 219.925947] [drm:drm_dp_update_payload_part1] [ 219.927476] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.927514] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.927586] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.928186] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.930079] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.930134] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 219.930415] [drm:drm_dp_update_payload_part1] removing payload 0 [ 219.930461] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 219.930567] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 219.930671] [drm:intel_disable_pipe [i915]] disabling pipe B [ 219.942904] [drm:intel_mst_post_disable_dp [i915]] 1 [ 219.949097] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 219.949597] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 219.949647] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 219.949701] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 219.949770] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.949818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.949862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.949891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.949918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.949944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.949972] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.950002] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.950030] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.950058] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.950084] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.950110] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.950157] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.950185] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.950215] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.950462] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 219.950549] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 219.950588] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 219.950597] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 219.950601] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 219.950640] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 219.950679] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 219.950719] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 219.950759] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 219.950799] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 219.950837] [drm:intel_dump_pipe_config [i915]] requested mode: [ 219.950848] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.950885] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 219.950894] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 219.950932] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 219.950969] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 219.951004] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 219.951043] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 219.951087] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 219.951124] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 219.951161] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 219.951198] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 219.951233] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 219.951293] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 219.951341] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 219.951472] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 219.951563] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 219.951603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 219.951642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 219.951680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 219.951717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 219.951754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 219.951793] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 219.951833] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 219.951871] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 219.951910] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 219.951947] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 219.951983] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.952026] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 219.952061] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 219.952127] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 219.954570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 219.954600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 219.954626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 219.954653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 219.971584] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 219.971602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 219.988502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 219.990570] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 219.990769] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 219.991999] [drm:intel_enable_pipe [i915]] enabling pipe B [ 219.992024] [drm:intel_mst_enable_dp [i915]] 1 [ 219.994425] [drm:drm_dp_update_payload_part2] payload 0 1 [ 219.995801] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 219.995825] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 219.995878] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 219.996421] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 219.996995] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 219.997025] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 219.997053] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 219.997116] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 219.997138] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 219.997192] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 219.997735] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 219.997760] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.009073] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.009112] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.009142] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.009147] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.009150] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.009178] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.009206] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.009232] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.009258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.009283] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.009306] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.009312] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.009335] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.009339] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.009364] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.009387] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.009410] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.009433] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.009459] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.009491] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.009590] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.009628] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.009666] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.009727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 220.009773] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.025654] [drm:intel_mst_disable_dp [i915]] 1 [ 220.025661] [drm:drm_dp_update_payload_part1] [ 220.027203] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.027250] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.027363] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.028153] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.030135] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.030187] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.030521] [drm:drm_dp_update_payload_part1] removing payload 0 [ 220.030581] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 220.030653] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 220.030755] [drm:intel_disable_pipe [i915]] disabling pipe B [ 220.043151] [drm:intel_mst_post_disable_dp [i915]] 1 [ 220.049990] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 220.050432] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 220.050469] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 220.050572] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 220.050648] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.050701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.050753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.050801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.050849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.050897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.050948] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.050999] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.051050] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.051101] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.051148] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.051193] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.051274] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.051323] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.051377] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.051850] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.051909] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.051959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.051969] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.051974] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.052020] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.052069] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.052114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.052158] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.052201] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.052243] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.052255] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.052297] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.052306] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.052349] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.052391] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.052433] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.052474] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.052536] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.052559] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.052585] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.052610] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.052634] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.052675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 220.052704] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.052791] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 220.052831] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.052855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.052879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.052902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.052926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.052948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.052971] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.052997] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.053021] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.053045] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.053067] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.053089] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.053115] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 220.053140] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 220.053183] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 220.054686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 220.054703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 220.054717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 220.054732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 220.071646] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 220.071664] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 220.088563] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 220.090610] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 220.090805] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 220.091949] [drm:intel_enable_pipe [i915]] enabling pipe B [ 220.091975] [drm:intel_mst_enable_dp [i915]] 1 [ 220.094369] [drm:drm_dp_update_payload_part2] payload 0 1 [ 220.095738] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.095759] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.095811] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.096344] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.096916] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 220.096939] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 220.096967] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 220.097051] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.097074] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.097126] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.097631] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.097650] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.108992] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.109027] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.109055] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.109060] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.109062] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.109088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.109114] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.109138] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.109162] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.109184] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.109206] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.109210] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.109232] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.109236] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.109264] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.109293] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.109322] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.109351] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.109379] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.109406] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.109436] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.109465] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.109543] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.109603] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 220.109646] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.125623] [drm:intel_mst_disable_dp [i915]] 1 [ 220.125631] [drm:drm_dp_update_payload_part1] [ 220.127175] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.127217] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.127317] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.128058] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.129922] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.129967] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.130290] [drm:drm_dp_update_payload_part1] removing payload 0 [ 220.130334] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 220.130375] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 220.130436] [drm:intel_disable_pipe [i915]] disabling pipe B [ 220.143795] [drm:intel_mst_post_disable_dp [i915]] 1 [ 220.149729] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 220.150182] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 220.150221] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 220.150264] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 220.150318] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.150356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.150391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.150424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.150456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.150487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.150589] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.150684] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.150742] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.150783] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.150820] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.150856] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.150919] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.150956] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.150996] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.151339] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.151391] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.151434] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.151442] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.151446] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.151487] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.151555] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.151597] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.151635] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.151671] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.151707] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.151717] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.151752] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.151761] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.151796] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.151833] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.151870] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.151905] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.151945] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.151982] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.152021] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.152070] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.152109] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.152169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 220.152216] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.152346] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 220.152406] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.152445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.152483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.152541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.152578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.152616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.152685] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.152726] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.152765] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.152805] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.152840] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.152875] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.152914] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 220.152951] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 220.153015] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 220.154531] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 220.154550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 220.154566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 220.154583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 220.171499] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 220.171517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 220.188416] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 220.190476] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 220.190680] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 220.191879] [drm:intel_enable_pipe [i915]] enabling pipe B [ 220.191904] [drm:intel_mst_enable_dp [i915]] 1 [ 220.194297] [drm:drm_dp_update_payload_part2] payload 0 1 [ 220.195667] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.195688] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.195754] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.196296] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.196912] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 220.196941] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 220.196977] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 220.197051] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.197080] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.197128] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.197654] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.197687] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.208991] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.209031] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.209062] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.209068] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.209070] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.209099] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.209129] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.209156] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.209182] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.209207] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.209231] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.209237] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.209260] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.209265] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.209289] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.209312] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.209336] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.209367] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.209401] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.209432] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.209466] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.209540] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.209586] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.209653] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 220.209699] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.225591] [drm:intel_mst_disable_dp [i915]] 1 [ 220.225598] [drm:drm_dp_update_payload_part1] [ 220.227140] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.227178] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.227261] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.227897] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.229772] [drm:drm_dp_update_payload_part1] removing payload 0 [ 220.229843] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 220.229914] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 220.230016] [drm:intel_disable_pipe [i915]] disabling pipe B [ 220.230181] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.230215] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.243652] [drm:intel_mst_post_disable_dp [i915]] 1 [ 220.248749] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 220.249229] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 220.249274] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 220.249325] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 220.249387] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.249430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.249470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.249591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.249647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.249702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.249758] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.249819] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.249878] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.249935] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.249988] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.250040] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.250137] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.250193] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.250254] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.250748] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.250801] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.250843] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.250872] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.250879] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.250923] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.250969] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.251011] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.251052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.251091] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.251128] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.251141] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.251196] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.251213] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.251273] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.251330] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.251386] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.251442] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.251504] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.251606] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.251665] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.251721] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.251774] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.251861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 220.251927] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.252123] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 220.252202] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.252259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.252314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.252470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.252529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.252554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.252580] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.252607] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.252633] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.252657] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.252679] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.252701] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.252728] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 220.252752] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 220.252795] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 220.254295] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 220.254325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 220.254349] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 220.254377] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 220.271279] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 220.271297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 220.288172] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 220.290234] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 220.290431] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 220.291585] [drm:intel_enable_pipe [i915]] enabling pipe B [ 220.291612] [drm:intel_mst_enable_dp [i915]] 1 [ 220.294006] [drm:drm_dp_update_payload_part2] payload 0 1 [ 220.295374] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.295396] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.295440] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.295977] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.296608] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 220.296633] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 220.296664] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 220.296733] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.296764] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.296801] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.297244] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.297262] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.308668] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.308693] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.308711] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.308715] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.308717] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.308734] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.308752] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.308769] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.308785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.308801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.308815] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.308819] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.308834] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.308836] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.308851] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.308866] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.308880] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.308894] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.308911] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.308925] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.308940] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.308954] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.308968] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.308992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 220.309012] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.325331] [drm:intel_mst_disable_dp [i915]] 1 [ 220.325338] [drm:drm_dp_update_payload_part1] [ 220.326873] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.326910] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.326996] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.327636] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.329740] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.329800] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.330115] [drm:drm_dp_update_payload_part1] removing payload 0 [ 220.330159] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 220.330205] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 220.330278] [drm:intel_disable_pipe [i915]] disabling pipe B [ 220.342711] [drm:intel_mst_post_disable_dp [i915]] 1 [ 220.349271] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 220.349770] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 220.349795] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 220.349821] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 220.349857] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.349880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.349901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.349921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.349940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.349959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.349979] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.350000] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.350020] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.350040] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.350058] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.350076] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.350110] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.350130] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.350152] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.350335] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.350360] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.350380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.350384] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.350386] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.350406] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.350427] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.350451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.350477] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.350535] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.350565] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.350959] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.350993] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.351000] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.351034] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.351067] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.351099] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.351126] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.351148] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.351167] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.351193] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.351218] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.351243] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.351281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 220.351310] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.351385] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 220.351425] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.351451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.351476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.351536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.351888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.351923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.351957] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.351992] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.352020] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.352042] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.352061] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.352080] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.352103] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 220.352123] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 220.352158] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 220.353660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 220.353683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 220.353704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 220.353725] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 220.370649] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 220.370667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 220.387567] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 220.389629] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 220.389825] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 220.390956] [drm:intel_enable_pipe [i915]] enabling pipe B [ 220.390982] [drm:intel_mst_enable_dp [i915]] 1 [ 220.393384] [drm:drm_dp_update_payload_part2] payload 0 1 [ 220.394769] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.394793] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.394836] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.395376] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.395947] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 220.395971] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 220.396001] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 220.396067] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.396091] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.396148] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.396661] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.396687] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.407993] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.408029] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.408056] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.408062] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.408064] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.408090] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.408115] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.408139] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.408163] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.408185] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.408206] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.408211] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.408233] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.408238] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.408260] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.408282] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.408303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.408323] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.408348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.408370] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.408392] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.408413] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.408434] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.408469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 220.408538] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.424613] [drm:intel_mst_disable_dp [i915]] 1 [ 220.424620] [drm:drm_dp_update_payload_part1] [ 220.426150] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.426187] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.426276] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.426896] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.429037] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.429103] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.429405] [drm:drm_dp_update_payload_part1] removing payload 0 [ 220.429468] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 220.429590] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 220.429713] [drm:intel_disable_pipe [i915]] disabling pipe B [ 220.441744] [drm:intel_mst_post_disable_dp [i915]] 1 [ 220.447931] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 220.448359] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 220.448395] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 220.448433] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 220.448485] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.448580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.448628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.448674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.448718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.448761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.448805] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.448852] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.448897] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.448943] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.448984] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.449025] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.449095] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.449140] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.449188] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.449622] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.449676] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.449709] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.449716] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.449719] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.449748] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.449777] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.449808] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.449839] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.449868] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.449895] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.449901] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.449929] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.449935] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.449964] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.449992] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.450018] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.450043] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.450075] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.450103] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.450133] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.450159] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.450184] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.450229] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 220.450266] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.450367] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 220.450412] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.450440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.450469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.450520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.450553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.450584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.450616] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.450649] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.450681] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.450713] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.450744] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.450774] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.450808] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 220.450841] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 220.450894] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 220.452417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 220.452448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 220.452476] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 220.452536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 220.469467] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 220.469497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 220.486395] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 220.488455] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 220.488661] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 220.489849] [drm:intel_enable_pipe [i915]] enabling pipe B [ 220.489874] [drm:intel_mst_enable_dp [i915]] 1 [ 220.492266] [drm:drm_dp_update_payload_part2] payload 0 1 [ 220.493620] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.493641] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.493694] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.494238] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.494803] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 220.494826] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 220.494854] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 220.494917] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.494940] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.494991] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.495501] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.495531] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.506953] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.506989] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.507017] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.507022] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.507024] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.507051] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.507078] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.507103] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.507127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.507150] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.507172] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.507177] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.507198] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.507203] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.507225] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.507254] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.507283] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.507313] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.507342] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.507371] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.507401] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.507431] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.507460] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.507567] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 220.507614] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.523588] [drm:intel_mst_disable_dp [i915]] 1 [ 220.523595] [drm:drm_dp_update_payload_part1] [ 220.525122] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.525156] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.525230] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.525815] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.527779] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.527835] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.528137] [drm:drm_dp_update_payload_part1] removing payload 0 [ 220.528189] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 220.528239] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 220.528312] [drm:intel_disable_pipe [i915]] disabling pipe B [ 220.541807] [drm:intel_mst_post_disable_dp [i915]] 1 [ 220.546769] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 220.547236] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 220.547279] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 220.547325] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 220.547383] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.547423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.547461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.547564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.547624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.547679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.547735] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.547795] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.547855] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.547913] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.547966] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.548019] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.548120] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.548158] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.548198] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.548566] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.548603] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.548631] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.548637] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.548639] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.548669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.548696] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.548723] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.548751] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.548776] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.548802] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.548809] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.548833] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.548840] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.548865] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.548890] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.548914] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.548938] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.548978] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.549015] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.549056] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.549093] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.549129] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.549189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 220.549236] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.549331] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 220.549377] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.549409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.549440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.549474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.549546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.549587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.549627] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.549669] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.549708] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.549748] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.549785] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.549821] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.549864] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 220.549904] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 220.549968] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 220.551477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 220.551510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 220.551526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 220.551544] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 220.568460] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 220.568489] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 220.585385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 220.587454] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 220.587663] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 220.588846] [drm:intel_enable_pipe [i915]] enabling pipe B [ 220.588871] [drm:intel_mst_enable_dp [i915]] 1 [ 220.591274] [drm:drm_dp_update_payload_part2] payload 0 1 [ 220.592644] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.592666] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.592722] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.593268] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.593854] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 220.593884] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 220.593920] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 220.593998] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.594041] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.594089] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.594575] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.594607] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.605969] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.606009] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.606040] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.606046] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.606049] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.606078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.606107] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.606134] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.606160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.606185] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.606209] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.606215] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.606238] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.606243] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.606267] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.606291] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.606314] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.606337] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.606365] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.606389] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.606413] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.606436] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.606458] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.606549] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 220.606599] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.622609] [drm:intel_mst_disable_dp [i915]] 1 [ 220.622623] [drm:drm_dp_update_payload_part1] [ 220.624189] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.624239] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.624367] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.625030] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.627211] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.627271] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.627612] [drm:drm_dp_update_payload_part1] removing payload 0 [ 220.627691] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 220.627761] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 220.627857] [drm:intel_disable_pipe [i915]] disabling pipe B [ 220.640203] [drm:intel_mst_post_disable_dp [i915]] 1 [ 220.646408] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 220.646889] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 220.646930] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 220.646973] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 220.647027] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.647065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.647100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.647133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.647165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.647196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.647229] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.647264] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.647298] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.647330] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.647360] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.647390] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.647445] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.647492] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.647598] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.647940] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.647985] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.648021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.648028] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.648031] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.648065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.648101] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.648135] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.648168] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.648198] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.648228] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.648235] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.648265] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.648272] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.648303] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.648333] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.648362] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.648391] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.648426] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.648456] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.648524] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.648547] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.648570] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.648609] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 220.648640] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.648705] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 220.648734] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.648751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.648768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.648784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.648804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.648825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.648845] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.648867] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.648889] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.648910] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.648930] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.648950] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.648971] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 220.648993] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 220.649024] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 220.650492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 220.650510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 220.650525] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 220.650540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 220.667454] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 220.667482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 220.684379] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 220.686438] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 220.686633] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 220.687757] [drm:intel_enable_pipe [i915]] enabling pipe B [ 220.687783] [drm:intel_mst_enable_dp [i915]] 1 [ 220.690175] [drm:drm_dp_update_payload_part2] payload 0 1 [ 220.691552] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.691573] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.691641] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.692192] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.692772] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 220.692800] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 220.692834] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 220.692909] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.692949] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.692994] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.693481] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.693524] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.704822] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.704861] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.704892] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.704898] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.704900] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.704929] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.704959] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.704986] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.705013] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.705038] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.705062] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.705068] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.705092] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.705097] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.705121] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.705145] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.705169] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.705191] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.705219] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.705244] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.705268] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.705291] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.705314] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.705353] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 220.705385] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.721432] [drm:intel_mst_disable_dp [i915]] 1 [ 220.721439] [drm:drm_dp_update_payload_part1] [ 220.723291] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.723328] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.723411] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.724054] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.725877] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.725920] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.726222] [drm:drm_dp_update_payload_part1] removing payload 0 [ 220.726260] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 220.726299] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 220.726356] [drm:intel_disable_pipe [i915]] disabling pipe B [ 220.739784] [drm:intel_mst_post_disable_dp [i915]] 1 [ 220.745706] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 220.746157] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 220.746197] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 220.746239] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 220.746292] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.746328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.746362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.746394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.746426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.746458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.746577] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.746636] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.746693] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.746744] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.746789] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.746840] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.746926] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.746978] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.747054] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.747752] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.747831] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.747894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.747906] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.747912] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.747970] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.748036] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.748135] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.748215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.748269] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.748324] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.748337] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.748393] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.748438] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.748496] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.748589] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.748649] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.748710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.748776] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.748833] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.748899] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.748962] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.749023] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.749116] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 220.749182] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.749379] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 220.749464] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.749608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.749665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.749766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.749823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.749879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.749934] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.749998] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.750093] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.750203] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.750256] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.750307] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.750371] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 220.750467] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 220.750551] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 220.752178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 220.752203] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 220.752227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 220.752251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 220.769202] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 220.769220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 220.786195] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 220.788255] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 220.788451] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 220.789602] [drm:intel_enable_pipe [i915]] enabling pipe B [ 220.789635] [drm:intel_mst_enable_dp [i915]] 1 [ 220.792029] [drm:drm_dp_update_payload_part2] payload 0 1 [ 220.793397] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.793419] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.793458] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.794018] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.794593] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 220.794620] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 220.794655] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 220.794726] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.794758] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.794814] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.795311] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.795354] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.806727] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.806758] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.806782] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.806786] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.806788] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.806811] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.806833] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.806853] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.806873] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.806892] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.806910] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.806915] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.806933] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.806937] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.806955] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.806974] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.806991] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.807009] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.807030] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.807048] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.807067] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.807085] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.807102] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.807133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 220.807157] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.823329] [drm:intel_mst_disable_dp [i915]] 1 [ 220.823335] [drm:drm_dp_update_payload_part1] [ 220.824862] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.824892] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.824995] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.825630] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.827594] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.827651] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.827957] [drm:drm_dp_update_payload_part1] removing payload 0 [ 220.828008] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 220.828057] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 220.828131] [drm:intel_disable_pipe [i915]] disabling pipe B [ 220.840573] [drm:intel_mst_post_disable_dp [i915]] 1 [ 220.847246] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 220.847650] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 220.847675] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 220.847701] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 220.847738] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.847760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.847782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.847802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.847821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.847839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.847859] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.847880] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.847900] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.847920] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.847938] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.847955] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.847989] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.848009] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.848036] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.848218] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.848247] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.848272] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.848277] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.848279] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.848304] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.848329] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.848354] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.848379] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.848404] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.848428] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.848432] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.848456] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.848500] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.848538] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.848571] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.848603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.848634] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.848668] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.848698] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.848730] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.848760] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.848791] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.848839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 220.848873] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.848963] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 220.849009] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.849039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.849067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.849095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.849122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.849149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.849178] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.849208] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.849237] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.849267] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.849293] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.849320] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.849352] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 220.849381] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 220.849431] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 220.850949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 220.850969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 220.850986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 220.851004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 220.868102] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 220.868120] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 220.885020] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 220.887088] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 220.887286] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 220.888489] [drm:intel_enable_pipe [i915]] enabling pipe B [ 220.888516] [drm:intel_mst_enable_dp [i915]] 1 [ 220.890895] [drm:drm_dp_update_payload_part2] payload 0 1 [ 220.892264] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.892285] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.892338] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.892883] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.893481] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 220.893528] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 220.893563] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 220.893795] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.893832] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.893870] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.894171] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.894188] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.905610] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.905643] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.905669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.905674] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.905676] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.905700] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.905724] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.905746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.905768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.905789] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.905808] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.905813] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.905832] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.905836] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.905857] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.905877] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.905896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.905915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.905937] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.905957] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.905978] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.905997] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.906016] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.906048] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 220.906074] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.922190] [drm:intel_mst_disable_dp [i915]] 1 [ 220.922197] [drm:drm_dp_update_payload_part1] [ 220.923745] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.923787] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.923890] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.924544] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.926584] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.926640] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 220.926945] [drm:drm_dp_update_payload_part1] removing payload 0 [ 220.926995] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 220.927045] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 220.927119] [drm:intel_disable_pipe [i915]] disabling pipe B [ 220.939441] [drm:intel_mst_post_disable_dp [i915]] 1 [ 220.945881] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 220.946329] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 220.946369] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 220.946412] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 220.946474] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.946579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.946639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.946692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.946741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.946788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.946843] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.946901] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.946956] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.947005] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.947049] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.947099] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.947184] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.947236] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.947293] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.947743] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 220.947796] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 220.947838] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 220.947848] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 220.947852] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 220.947892] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.947932] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 220.947973] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 220.948012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 220.948050] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.948085] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.948093] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.948129] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.948137] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 220.948175] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 220.948211] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 220.948246] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.948278] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.948318] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 220.948355] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.948394] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 220.948428] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 220.948460] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 220.948545] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 220.948594] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 220.948726] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 220.948781] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 220.948818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 220.948858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 220.948895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 220.948932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 220.948968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 220.949003] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 220.949044] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 220.949084] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 220.949123] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 220.949156] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 220.949188] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.949232] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 220.949272] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 220.949335] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 220.950999] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 220.951037] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 220.951076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 220.951116] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 220.968059] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 220.968077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 220.984975] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 220.987032] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 220.987230] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 220.988321] [drm:intel_enable_pipe [i915]] enabling pipe B [ 220.988349] [drm:intel_mst_enable_dp [i915]] 1 [ 220.990751] [drm:drm_dp_update_payload_part2] payload 0 1 [ 220.992121] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 220.992143] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 220.992196] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 220.992743] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 220.993313] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 220.993338] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 220.993369] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 220.993436] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 220.993461] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 220.993529] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 220.994212] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 220.994230] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.005423] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.005465] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.005552] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.005683] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.005687] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.005730] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.005772] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.005809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.005844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.005881] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.005916] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.005924] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.005959] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.005966] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.005998] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.006030] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.006065] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.006099] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.006139] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.006172] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.006205] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.006240] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.006274] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.006331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 221.006375] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.022015] [drm:intel_mst_disable_dp [i915]] 1 [ 221.022022] [drm:drm_dp_update_payload_part1] [ 221.023536] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.023578] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.023671] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.024308] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.026190] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.026239] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.026619] [drm:drm_dp_update_payload_part1] removing payload 0 [ 221.026678] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 221.026744] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 221.026842] [drm:intel_disable_pipe [i915]] disabling pipe B [ 221.038789] [drm:intel_mst_post_disable_dp [i915]] 1 [ 221.045697] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 221.046136] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 221.046171] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 221.046211] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 221.046265] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.046303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.046340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.046377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.046413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.046450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.046552] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.046747] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.047124] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.047170] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.047217] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.047263] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.047340] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.047384] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.047437] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.048107] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.048170] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.048215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.048225] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.048230] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.048279] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.048329] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.048375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.048417] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.048461] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.048539] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.048941] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.048989] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.048997] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.049044] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.049087] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.049128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.049175] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.049228] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.049273] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.049316] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.049355] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.049400] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.049472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 221.049559] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.049932] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 221.050178] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.050228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.050274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.050316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.050360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.050405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.050451] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.050532] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.050704] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.050747] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.050791] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.050833] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.050884] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 221.050928] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 221.051006] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 221.052542] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 221.052569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 221.052593] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 221.052616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 221.069540] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 221.069558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 221.086484] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 221.088526] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 221.088724] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 221.089947] [drm:intel_enable_pipe [i915]] enabling pipe B [ 221.089972] [drm:intel_mst_enable_dp [i915]] 1 [ 221.092373] [drm:drm_dp_update_payload_part2] payload 0 1 [ 221.093748] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.093771] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.093846] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.094397] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.094998] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 221.095027] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 221.095062] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 221.095138] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.095170] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.095220] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.095701] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.095724] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.107058] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.107097] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.107128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.107133] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.107136] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.107164] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.107193] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.107220] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.107246] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.107270] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.107293] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.107299] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.107328] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.107333] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.107365] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.107397] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.107428] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.107461] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.107550] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.107591] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.107632] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.107669] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.107706] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.107765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 221.107812] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.123640] [drm:intel_mst_disable_dp [i915]] 1 [ 221.123648] [drm:drm_dp_update_payload_part1] [ 221.125200] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.125255] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.125367] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.126047] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.128046] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.128108] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.128406] [drm:drm_dp_update_payload_part1] removing payload 0 [ 221.128460] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 221.128574] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 221.128696] [drm:intel_disable_pipe [i915]] disabling pipe B [ 221.140655] [drm:intel_mst_post_disable_dp [i915]] 1 [ 221.147539] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 221.147995] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 221.148035] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 221.148078] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 221.148131] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.148168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.148204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.148236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.148269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.148300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.148333] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.148368] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.148401] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.148444] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.148485] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.148576] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.148674] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.148733] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.148792] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.149235] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.149303] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.149356] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.149368] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.149373] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.149429] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.149484] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.149563] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.149590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.149618] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.149645] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.149654] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.149679] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.149686] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.149712] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.149739] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.149764] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.149788] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.149813] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.149838] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.149865] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.149891] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.149914] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.149954] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 221.149986] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.150078] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 221.150118] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.150143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.150170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.150196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.150221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.150247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.150270] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.150299] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.150326] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.150353] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.150376] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.150398] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.150428] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 221.150455] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 221.150526] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 221.152107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 221.152136] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 221.152160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 221.152188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 221.169098] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 221.169115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 221.185988] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 221.188049] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 221.188246] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 221.189326] [drm:intel_enable_pipe [i915]] enabling pipe B [ 221.189353] [drm:intel_mst_enable_dp [i915]] 1 [ 221.191754] [drm:drm_dp_update_payload_part2] payload 0 1 [ 221.193133] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.193155] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.193195] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.193734] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.194298] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 221.194322] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 221.194351] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 221.194418] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.194442] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.194530] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.195028] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.195054] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.206365] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.206392] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.206413] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.206418] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.206419] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.206439] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.206458] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.206519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.206552] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.206582] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.206609] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.206618] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.206646] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.206651] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.206680] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.206708] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.206732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.206756] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.206786] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.206813] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.206840] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.206865] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.206888] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.206932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 221.206965] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.223026] [drm:intel_mst_disable_dp [i915]] 1 [ 221.223033] [drm:drm_dp_update_payload_part1] [ 221.224558] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.224606] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.224711] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.225368] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.227382] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.227439] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.227816] [drm:drm_dp_update_payload_part1] removing payload 0 [ 221.227867] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 221.227916] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 221.228012] [drm:intel_disable_pipe [i915]] disabling pipe B [ 221.240417] [drm:intel_mst_post_disable_dp [i915]] 1 [ 221.246195] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 221.246652] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 221.246689] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 221.246726] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 221.246778] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.246812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.246842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.246871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.246899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.246927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.246956] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.246987] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.247016] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.247045] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.247072] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.247098] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.247156] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.247195] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.247236] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.247586] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.247649] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.247689] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.247697] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.247701] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.247740] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.247777] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.247814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.247851] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.247886] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.247919] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.247927] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.247960] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.247967] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.248001] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.248035] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.248068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.248101] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.248139] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.248172] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.248207] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.248241] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.248273] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.248328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 221.248370] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.248504] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 221.248558] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.248593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.248627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.248659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.248691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.248723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.248756] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.248794] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.248828] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.248865] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.248899] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.248932] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.248971] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 221.249007] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 221.249069] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 221.250614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 221.250640] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 221.250663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 221.250686] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 221.267613] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 221.267630] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 221.284528] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 221.286584] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 221.286779] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 221.287898] [drm:intel_enable_pipe [i915]] enabling pipe B [ 221.287923] [drm:intel_mst_enable_dp [i915]] 1 [ 221.290312] [drm:drm_dp_update_payload_part2] payload 0 1 [ 221.291687] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.291709] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.291747] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.292302] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.292876] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 221.292899] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 221.292928] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 221.292989] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.293011] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.293054] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.293565] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.293582] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.304958] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.304998] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.305028] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.305033] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.305035] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.305064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.305092] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.305119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.305144] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.305169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.305192] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.305197] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.305221] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.305225] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.305249] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.305273] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.305295] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.305318] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.305344] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.305367] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.305392] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.305415] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.305438] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.305518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 221.305567] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.321596] [drm:intel_mst_disable_dp [i915]] 1 [ 221.321603] [drm:drm_dp_update_payload_part1] [ 221.323133] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.323170] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.323243] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.323867] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.325972] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.326030] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.326332] [drm:drm_dp_update_payload_part1] removing payload 0 [ 221.326381] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 221.326430] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 221.326568] [drm:intel_disable_pipe [i915]] disabling pipe B [ 221.338628] [drm:intel_mst_post_disable_dp [i915]] 1 [ 221.345026] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 221.345490] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 221.345608] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 221.345678] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 221.345763] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.345819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.345877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.345934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.345987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.346043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.346100] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.346160] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.346215] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.346267] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.346322] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.346375] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.346458] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.346519] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.346560] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.346905] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.346953] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.346993] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.347001] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.347005] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.347043] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.347079] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.347116] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.347154] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.347189] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.347222] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.347229] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.347264] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.347272] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.347308] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.347343] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.347375] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.347406] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.347445] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.347509] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.347537] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.347560] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.347585] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.347623] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 221.347652] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.347745] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 221.347785] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.347812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.347837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.347859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.347885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.347910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.347934] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.347959] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.347986] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.348011] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.348035] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.348057] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.348082] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 221.348108] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 221.348153] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 221.349769] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 221.349795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 221.349817] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 221.349841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 221.366763] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 221.366782] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 221.383680] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 221.385715] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 221.385910] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 221.386996] [drm:intel_enable_pipe [i915]] enabling pipe B [ 221.387021] [drm:intel_mst_enable_dp [i915]] 1 [ 221.389423] [drm:drm_dp_update_payload_part2] payload 0 1 [ 221.390798] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.390821] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.390893] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.391439] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.392058] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 221.392086] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 221.392119] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 221.392194] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.392245] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.392293] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.392771] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.392792] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.404119] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.404159] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.404189] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.404194] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.404197] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.404225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.404253] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.404279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.404305] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.404329] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.404353] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.404358] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.404381] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.404385] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.404410] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.404433] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.404456] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.404519] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.404565] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.404605] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.404645] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.404682] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.404717] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.404777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 221.404821] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.420759] [drm:intel_mst_disable_dp [i915]] 1 [ 221.420767] [drm:drm_dp_update_payload_part1] [ 221.422315] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.422366] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.422492] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.423194] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.425346] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.425417] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.425832] [drm:drm_dp_update_payload_part1] removing payload 0 [ 221.425918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 221.426013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 221.426147] [drm:intel_disable_pipe [i915]] disabling pipe B [ 221.437762] [drm:intel_mst_post_disable_dp [i915]] 1 [ 221.444680] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 221.445122] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 221.445159] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 221.445199] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 221.445251] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.445286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.445319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.445350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.445380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.445409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.445440] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.445472] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.445565] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.445616] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.445668] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.445695] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.445748] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.445777] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.445809] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.446077] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.446117] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.446146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.446151] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.446152] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.446174] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.446196] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.446216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.446236] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.446261] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.446285] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.446290] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.446314] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.446318] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.446343] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.446368] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.446393] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.446418] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.446442] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.446470] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.446531] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.446560] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.446586] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.446625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 221.446655] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.446742] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 221.446781] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.446806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.446829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.446853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.446875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.446897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.446922] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.446957] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.446981] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.447004] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.447026] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.447047] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.447071] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 221.447093] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 221.447132] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 221.448604] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 221.448621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 221.448635] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 221.448651] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 221.465565] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 221.465582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 221.482493] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 221.484571] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 221.484770] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 221.485926] [drm:intel_enable_pipe [i915]] enabling pipe B [ 221.485951] [drm:intel_mst_enable_dp [i915]] 1 [ 221.488352] [drm:drm_dp_update_payload_part2] payload 0 1 [ 221.489721] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.489744] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.489787] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.490325] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.491002] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 221.491029] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 221.491062] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 221.491133] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.491159] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.491220] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.491724] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.491754] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.503025] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.503059] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.503085] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.503091] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.503093] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.503117] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.503141] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.503163] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.503185] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.503205] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.503225] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.503230] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.503249] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.503253] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.503273] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.503293] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.503312] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.503331] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.503354] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.503373] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.503394] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.503413] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.503432] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.503465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 221.504096] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.519656] [drm:intel_mst_disable_dp [i915]] 1 [ 221.519664] [drm:drm_dp_update_payload_part1] [ 221.521212] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.521260] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.521371] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.522014] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.524141] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.524203] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.524530] [drm:drm_dp_update_payload_part1] removing payload 0 [ 221.524599] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 221.524677] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 221.524773] [drm:intel_disable_pipe [i915]] disabling pipe B [ 221.536612] [drm:intel_mst_post_disable_dp [i915]] 1 [ 221.543467] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 221.543885] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 221.543915] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 221.543947] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 221.543989] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.544017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.544044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.544070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.544094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.544117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.544142] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.544169] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.544194] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.544219] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.544242] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.544265] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.544306] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.544331] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.544358] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.544691] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.544737] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.544778] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.544786] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.544790] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.544829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.544867] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.544904] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.544940] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.544974] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.545009] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.545018] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.545051] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.545058] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.545092] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.545126] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.545159] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.545192] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.545231] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.545265] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.545300] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.545342] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.545367] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.545410] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 221.545444] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.545557] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 221.545602] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.545631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.545659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.545686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.545717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.545747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.545776] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.545807] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.545837] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.545867] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.545894] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.545921] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.545953] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 221.545983] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 221.546035] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 221.547538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 221.547564] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 221.547594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 221.547622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 221.564516] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 221.564533] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 221.581402] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 221.582516] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 221.582714] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 221.583867] [drm:intel_enable_pipe [i915]] enabling pipe B [ 221.583892] [drm:intel_mst_enable_dp [i915]] 1 [ 221.585810] [drm:drm_dp_update_payload_part2] payload 0 1 [ 221.587199] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.587220] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.587252] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.587781] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.588343] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 221.588369] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 221.588400] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 221.588466] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.588921] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.588959] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.589116] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.589134] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.600992] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.601029] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.601058] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.601063] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.601065] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.601092] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.601119] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.601145] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.601170] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.601193] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.601216] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.601221] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.601243] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.601247] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.601270] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.601292] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.601314] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.601335] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.601361] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.601390] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.601421] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.601451] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.601519] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.601682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 221.601725] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.617574] [drm:intel_mst_disable_dp [i915]] 1 [ 221.617581] [drm:drm_dp_update_payload_part1] [ 221.619123] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.619174] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.619290] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.620038] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.622078] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.622139] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.622447] [drm:drm_dp_update_payload_part1] removing payload 0 [ 221.622563] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 221.622828] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 221.622946] [drm:intel_disable_pipe [i915]] disabling pipe B [ 221.635304] [drm:intel_mst_post_disable_dp [i915]] 1 [ 221.641592] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 221.642029] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 221.642063] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 221.642101] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 221.642150] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.642183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.642214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.642243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.642271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.642298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.642327] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.642357] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.642387] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.642416] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.642443] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.642531] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.642609] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.642654] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.642704] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.643041] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.643071] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.643094] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.643099] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.643101] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.643124] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.643147] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.643168] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.643190] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.643211] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.643230] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.643235] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.643254] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.643258] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.643277] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.643297] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.643316] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.643334] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.643357] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.643376] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.643397] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.643416] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.643435] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.643504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 221.643538] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.643633] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 221.643676] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.643704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.643730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.643755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.643780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.643805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.643830] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.643857] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.643883] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.643910] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.643934] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.643957] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.643985] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 221.644012] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 221.644058] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 221.645545] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 221.645566] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 221.645584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 221.645602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 221.662494] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 221.662511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 221.679381] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 221.681442] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 221.681654] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 221.682801] [drm:intel_enable_pipe [i915]] enabling pipe B [ 221.682827] [drm:intel_mst_enable_dp [i915]] 1 [ 221.684847] [drm:drm_dp_update_payload_part2] payload 0 1 [ 221.686224] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.686245] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.686289] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.686845] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.687411] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 221.687436] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 221.687523] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 221.687601] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.687632] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.687681] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.688148] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.688168] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.699887] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.699914] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.699935] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.699939] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.699941] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.699961] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.699980] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.699999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.700017] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.700034] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.700051] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.700055] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.700071] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.700074] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.700090] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.700106] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.700122] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.700138] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.700157] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.700178] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.700201] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.700224] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.700246] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.700279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 221.700305] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.716567] [drm:intel_mst_disable_dp [i915]] 1 [ 221.716574] [drm:drm_dp_update_payload_part1] [ 221.718118] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.718163] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.718244] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.718911] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.720798] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.720846] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.721153] [drm:drm_dp_update_payload_part1] removing payload 0 [ 221.721192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 221.721233] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 221.721297] [drm:intel_disable_pipe [i915]] disabling pipe B [ 221.733646] [drm:intel_mst_post_disable_dp [i915]] 1 [ 221.740440] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 221.740846] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 221.740868] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 221.740893] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 221.740929] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.740951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.740971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.740989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.741007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.741025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.741044] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.741065] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.741084] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.741103] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.741120] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.741137] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.741170] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.741189] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.741210] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.741387] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.741411] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.741430] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.741434] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.741436] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.741461] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.741522] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.741572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.741613] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.741651] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.741689] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.741706] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.741732] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.741756] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.741783] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.741820] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.741845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.741887] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.741928] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.741965] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.742003] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.742031] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.742057] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.742100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 221.742133] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.742229] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 221.742273] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.742302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.742329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.742357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.742384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.742409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.742437] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.742467] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.742508] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.742535] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.742561] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.742586] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.742616] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 221.742645] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 221.742694] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 221.744197] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 221.744220] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 221.744240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 221.744261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 221.761190] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 221.761208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 221.778127] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 221.780187] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 221.780383] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 221.781480] [drm:intel_enable_pipe [i915]] enabling pipe B [ 221.781505] [drm:intel_mst_enable_dp [i915]] 1 [ 221.783869] [drm:drm_dp_update_payload_part2] payload 0 1 [ 221.785237] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.785258] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.785310] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.785853] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.786418] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 221.786443] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 221.786506] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 221.786573] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.786607] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.786645] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.787120] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.787137] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.798589] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.798622] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.798648] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.798653] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.798655] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.798679] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.798702] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.798724] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.798746] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.798766] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.798786] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.798791] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.798811] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.798815] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.798835] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.798855] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.798875] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.798894] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.798917] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.798936] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.798957] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.798976] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.798995] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.799029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 221.799055] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.815131] [drm:intel_mst_disable_dp [i915]] 1 [ 221.815136] [drm:drm_dp_update_payload_part1] [ 221.816626] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.816654] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.816705] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.817267] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.819158] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.819212] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.819515] [drm:drm_dp_update_payload_part1] removing payload 0 [ 221.819581] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 221.819651] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 221.819751] [drm:intel_disable_pipe [i915]] disabling pipe B [ 221.833704] [drm:intel_mst_post_disable_dp [i915]] 1 [ 221.838262] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 221.838799] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 221.838847] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 221.838899] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 221.838965] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.839011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.839054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.839096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.839137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.839177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.839218] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.839263] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.839305] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.839346] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.839385] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.839422] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.839577] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.839652] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.839731] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.840287] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.840371] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.840438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.840494] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.840499] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.840545] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.840598] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.840644] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.840687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.840731] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.840772] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.840781] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.840822] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.840830] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.840868] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.840910] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.840950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.840990] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.841033] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.841069] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.841113] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.841153] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.841193] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.841254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 221.841305] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.841442] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 221.841537] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.841583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.841626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.841665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.841708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.841751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.841794] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.841837] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.841877] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.841920] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.841960] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.841999] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.842043] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 221.842083] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 221.842156] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 221.843677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 221.843702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 221.843726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 221.843749] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 221.860671] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 221.860688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 221.877587] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 221.879621] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 221.879814] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 221.880927] [drm:intel_enable_pipe [i915]] enabling pipe B [ 221.880953] [drm:intel_mst_enable_dp [i915]] 1 [ 221.883334] [drm:drm_dp_update_payload_part2] payload 0 1 [ 221.884707] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.884728] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.884763] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.885293] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.885900] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 221.885931] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 221.885968] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 221.886045] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.886076] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.886124] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.886593] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.886627] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.898015] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.898051] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.898079] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.898084] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.898086] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.898113] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.898140] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.898164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.898188] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.898210] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.898232] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.898237] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.898259] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.898263] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.898285] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.898306] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.898327] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.898356] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.898386] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.898414] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.898445] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.898509] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.898554] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.898615] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 221.898661] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.914658] [drm:intel_mst_disable_dp [i915]] 1 [ 221.914665] [drm:drm_dp_update_payload_part1] [ 221.916196] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.916239] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.916352] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.916977] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.918969] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.919034] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.919333] [drm:drm_dp_update_payload_part1] removing payload 0 [ 221.919384] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 221.919438] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 221.919665] [drm:intel_disable_pipe [i915]] disabling pipe B [ 221.931639] [drm:intel_mst_post_disable_dp [i915]] 1 [ 221.938051] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 221.938559] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 221.938600] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 221.938644] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 221.938701] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.938742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.938780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.938815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.938850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.938884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.938920] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.938959] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.938994] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.939030] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.939063] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.939096] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.939154] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.939190] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.939229] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.939622] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.939663] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.939697] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.939705] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.939708] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.939740] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.939774] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.939806] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.939837] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.939866] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.939895] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.939904] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.939931] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.939938] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.939966] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.939995] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.940023] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.940050] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.940083] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.940113] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.940144] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.940182] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.940222] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.940277] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 221.940324] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 221.940435] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 221.940522] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 221.940557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 221.940590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 221.940620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 221.940651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 221.940680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 221.940711] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 221.940744] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 221.940776] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 221.940810] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 221.940840] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 221.940868] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.940901] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 221.940925] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 221.940960] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 221.942446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 221.942477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 221.942492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 221.942506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 221.959418] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 221.959436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 221.976352] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 221.978408] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 221.978600] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 221.979694] [drm:intel_enable_pipe [i915]] enabling pipe B [ 221.979719] [drm:intel_mst_enable_dp [i915]] 1 [ 221.982083] [drm:drm_dp_update_payload_part2] payload 0 1 [ 221.983460] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 221.983480] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 221.983518] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 221.984048] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 221.985285] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 221.985354] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 221.985378] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 221.985518] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 221.985555] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 221.985627] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 221.985653] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 221.985695] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 221.996798] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 221.996832] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 221.996859] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 221.996864] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 221.996866] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 221.996890] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 221.996915] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 221.996937] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 221.996958] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 221.996984] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 221.997011] [drm:intel_dump_pipe_config [i915]] requested mode: [ 221.997016] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.997042] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 221.997047] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 221.997074] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 221.997101] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 221.997128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 221.997154] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 221.997181] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 221.997206] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 221.997235] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 221.997262] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 221.997288] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 221.997327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 221.997358] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.013358] [drm:intel_mst_disable_dp [i915]] 1 [ 222.013365] [drm:drm_dp_update_payload_part1] [ 222.014906] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.014937] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.014995] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.015649] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.017722] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.017779] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.018079] [drm:drm_dp_update_payload_part1] removing payload 0 [ 222.018125] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 222.018172] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 222.018246] [drm:intel_disable_pipe [i915]] disabling pipe B [ 222.030601] [drm:intel_mst_post_disable_dp [i915]] 1 [ 222.036515] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 222.036975] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 222.037017] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 222.037064] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 222.037121] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.037161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.037198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.037234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.037267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.037301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.037337] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.037374] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.037420] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.037474] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.037574] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.037608] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.037661] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.037691] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.037726] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.038017] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.038054] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.038088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.038094] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.038098] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.038130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.038163] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.038192] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.038224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.038254] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.038283] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.038290] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.038317] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.038322] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.038353] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.038382] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.038411] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.038438] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.038498] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.038527] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.038557] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.038588] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.038621] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.038669] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 222.038707] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.038813] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 222.038862] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.038894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.038925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.038952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.038982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.039011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.039042] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.039072] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.039101] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.039133] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.039162] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.039191] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.039223] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 222.039252] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 222.039305] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 222.040809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 222.040836] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 222.040859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 222.040885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 222.057742] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 222.057759] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 222.074590] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 222.076504] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 222.076700] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 222.077917] [drm:intel_enable_pipe [i915]] enabling pipe B [ 222.077944] [drm:intel_mst_enable_dp [i915]] 1 [ 222.079814] [drm:drm_dp_update_payload_part2] payload 0 1 [ 222.081189] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.081210] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.081273] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.081839] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.082403] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 222.082426] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 222.082456] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 222.082634] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.082657] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.082695] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.083103] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.083124] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.094966] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.094991] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.095010] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.095014] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.095015] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.095033] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.095050] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.095067] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.095083] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.095098] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.095113] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.095116] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.095136] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.095139] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.095159] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.095179] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.095199] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.095219] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.095239] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.095258] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.095278] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.095298] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.095318] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.095347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 222.095370] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.111648] [drm:intel_mst_disable_dp [i915]] 1 [ 222.111655] [drm:drm_dp_update_payload_part1] [ 222.113186] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.113225] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.113318] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.113943] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.115818] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.115866] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.116167] [drm:drm_dp_update_payload_part1] removing payload 0 [ 222.116206] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 222.116245] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 222.116309] [drm:intel_disable_pipe [i915]] disabling pipe B [ 222.129826] [drm:intel_mst_post_disable_dp [i915]] 1 [ 222.135213] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 222.135756] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 222.135786] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 222.135818] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 222.135859] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.135886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.135911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.135936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.135959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.135982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.136006] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.136032] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.136056] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.136080] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.136103] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.136124] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.136164] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.136188] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.136215] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.136427] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.136464] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.136528] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.136538] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.136544] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.136583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.136621] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.136658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.136695] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.136731] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.136765] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.136774] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.136807] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.136816] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.136851] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.136884] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.136916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.136949] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.136986] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.137018] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.137052] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.137084] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.137116] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.137169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 222.137211] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.137318] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 222.137370] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.137406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.137441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.137495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.137528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.137561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.137595] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.137633] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.137667] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.137702] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.137737] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.137769] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.137808] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 222.137845] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 222.137905] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 222.139441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 222.139490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 222.139516] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 222.139541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 222.156483] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 222.156500] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 222.173398] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 222.175476] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 222.175676] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 222.176899] [drm:intel_enable_pipe [i915]] enabling pipe B [ 222.176924] [drm:intel_mst_enable_dp [i915]] 1 [ 222.179319] [drm:drm_dp_update_payload_part2] payload 0 1 [ 222.180688] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.180709] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.180748] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.181282] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.181882] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 222.181905] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 222.181933] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 222.181996] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.182018] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.182073] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.182579] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.182604] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.193956] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.193993] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.194022] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.194027] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.194029] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.194056] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.194083] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.194107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.194135] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.194164] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.194193] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.194199] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.194228] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.194233] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.194263] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.194293] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.194323] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.194352] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.194382] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.194410] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.194441] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.194526] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.194570] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.194628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 222.194670] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.210599] [drm:intel_mst_disable_dp [i915]] 1 [ 222.210607] [drm:drm_dp_update_payload_part1] [ 222.212127] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.212164] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.212233] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.212891] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.214821] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.214872] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.215169] [drm:drm_dp_update_payload_part1] removing payload 0 [ 222.215211] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 222.215254] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 222.215318] [drm:intel_disable_pipe [i915]] disabling pipe B [ 222.228808] [drm:intel_mst_post_disable_dp [i915]] 1 [ 222.234351] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 222.234910] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 222.234951] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 222.234994] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 222.235049] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.235087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.235121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.235155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.235187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.235217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.235250] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.235284] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.235318] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.235351] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.235381] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.235411] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.235465] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.235554] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.236032] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.236488] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.236651] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.236686] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.236694] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.236697] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.236727] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.236758] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.236786] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.236815] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.236841] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.236867] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.236873] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.236898] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.236903] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.236929] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.236955] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.236979] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.237003] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.237032] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.237057] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.237083] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.237108] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.237133] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.237176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 222.237210] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.237308] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 222.237360] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.237395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.237430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.237471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.237545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.238172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.238207] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.238245] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.238281] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.238317] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.238354] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.238389] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.238426] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 222.238467] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 222.238567] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 222.240196] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 222.240214] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 222.240231] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 222.240249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 222.257227] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 222.257245] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 222.274190] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 222.276248] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 222.276455] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 222.277630] [drm:intel_enable_pipe [i915]] enabling pipe B [ 222.277657] [drm:intel_mst_enable_dp [i915]] 1 [ 222.280051] [drm:drm_dp_update_payload_part2] payload 0 1 [ 222.281421] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.281442] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.281483] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.282027] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.282609] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 222.282639] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 222.282680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 222.282761] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.282803] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.282852] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.283323] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.283344] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.294758] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.294788] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.294810] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.294815] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.294817] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.294838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.294859] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.294878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.294898] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.294915] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.294933] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.294937] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.294954] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.294958] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.294976] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.294993] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.295009] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.295025] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.295045] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.295062] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.295080] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.295097] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.295114] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.295147] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 222.295174] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.311361] [drm:intel_mst_disable_dp [i915]] 1 [ 222.311368] [drm:drm_dp_update_payload_part1] [ 222.312910] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.312952] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.313012] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.313649] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.315564] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.315611] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.315910] [drm:drm_dp_update_payload_part1] removing payload 0 [ 222.315951] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 222.315992] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 222.316069] [drm:intel_disable_pipe [i915]] disabling pipe B [ 222.329774] [drm:intel_mst_post_disable_dp [i915]] 1 [ 222.335188] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 222.335686] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 222.335738] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 222.335816] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 222.335893] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.335942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.335987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.336036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.336084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.336131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.336177] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.336231] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.336282] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.336332] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.336376] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.336418] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.336555] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.336609] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.336664] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.337155] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.337213] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.337259] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.337270] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.337275] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.337326] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.337377] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.337426] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.337470] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.337553] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.337604] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.337620] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.337667] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.337680] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.337730] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.337778] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.337827] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.337868] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.337917] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.337964] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.338012] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.338058] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.338101] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.338175] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 222.338233] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.338408] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 222.338478] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.338576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.338629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.338761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.338808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.338850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.338911] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.338962] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.339011] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.339080] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.339105] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.339130] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.339158] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 222.339193] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 222.339254] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 222.340779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 222.340803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 222.340824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 222.340848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 222.357745] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 222.357763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 222.374638] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 222.376707] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 222.376906] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 222.378074] [drm:intel_enable_pipe [i915]] enabling pipe B [ 222.378100] [drm:intel_mst_enable_dp [i915]] 1 [ 222.380496] [drm:drm_dp_update_payload_part2] payload 0 1 [ 222.381864] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.381886] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.381934] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.382499] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.383062] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 222.383085] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 222.383114] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 222.383212] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.383236] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.383273] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.383752] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.383770] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.395164] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.395194] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.395217] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.395222] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.395224] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.395246] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.395269] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.395289] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.395309] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.395328] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.395346] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.395351] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.395369] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.395373] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.395391] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.395409] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.395427] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.395445] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.395795] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.395830] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.395864] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.395895] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.395916] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.395952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 222.395981] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.411796] [drm:intel_mst_disable_dp [i915]] 1 [ 222.411802] [drm:drm_dp_update_payload_part1] [ 222.413348] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.413396] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.413485] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.414177] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.416068] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.416120] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.416420] [drm:drm_dp_update_payload_part1] removing payload 0 [ 222.416471] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 222.416562] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 222.416673] [drm:intel_disable_pipe [i915]] disabling pipe B [ 222.428717] [drm:intel_mst_post_disable_dp [i915]] 1 [ 222.435689] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 222.436123] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 222.436156] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 222.436193] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 222.436241] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.436271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.436301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.436329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.436356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.436382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.436410] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.436439] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.436530] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.436583] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.436610] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.436637] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.436688] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.436719] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.436753] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.436954] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.436992] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.437023] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.437029] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.437033] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.437063] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.437094] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.437119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.437139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.437156] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.437173] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.437178] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.437194] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.437198] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.437215] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.437232] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.437248] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.437264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.437284] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.437301] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.437319] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.437336] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.437352] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.437381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 222.437405] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.437509] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 222.437556] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.437587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.437616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.437643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.437672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.437700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.437729] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.437760] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.437791] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.437821] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.437849] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.437876] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.437906] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 222.437928] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 222.437962] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 222.439439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 222.439468] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 222.439483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 222.439499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 222.456396] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 222.456415] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 222.473322] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 222.475401] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 222.475600] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 222.476739] [drm:intel_enable_pipe [i915]] enabling pipe B [ 222.476776] [drm:intel_mst_enable_dp [i915]] 1 [ 222.479168] [drm:drm_dp_update_payload_part2] payload 0 1 [ 222.480548] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.480572] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.480615] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.481153] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.481720] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 222.481746] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 222.481776] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 222.481845] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.481876] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.481930] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.482413] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.482429] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.493849] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.493882] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.493907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.493912] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.493914] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.493938] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.493964] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.493991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.494018] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.494044] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.494070] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.494074] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.494100] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.494104] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.494131] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.494157] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.494183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.494209] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.494236] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.494260] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.494288] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.494314] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.494340] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.494378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 222.494408] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.510501] [drm:intel_mst_disable_dp [i915]] 1 [ 222.510508] [drm:drm_dp_update_payload_part1] [ 222.512040] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.512074] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.512163] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.512750] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.514591] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.514630] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.514928] [drm:drm_dp_update_payload_part1] removing payload 0 [ 222.514962] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 222.514996] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 222.515046] [drm:intel_disable_pipe [i915]] disabling pipe B [ 222.528619] [drm:intel_mst_post_disable_dp [i915]] 1 [ 222.534307] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 222.534765] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 222.534804] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 222.534844] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 222.534895] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.534930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.534963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.534994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.535023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.535053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.535084] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.535116] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.535148] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.535179] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.535207] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.535235] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.535285] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.535316] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.535350] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.535793] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.535855] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.535903] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.535915] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.535921] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.535972] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.536024] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.536073] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.536118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.536166] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.536213] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.536223] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.536269] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.536278] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.536321] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.536369] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.536414] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.536458] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.536537] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.536582] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.536635] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.536684] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.536733] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.536809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 222.536869] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.537007] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 222.537078] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.537125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.537168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.537215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.537261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.537306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.537352] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.537404] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.537453] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.537536] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.537582] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.537625] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.537683] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 222.537736] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 222.537818] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 222.539423] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 222.539460] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 222.539556] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 222.539605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 222.556504] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 222.556523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 222.573421] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 222.575484] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 222.575679] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 222.576886] [drm:intel_enable_pipe [i915]] enabling pipe B [ 222.576911] [drm:intel_mst_enable_dp [i915]] 1 [ 222.579305] [drm:drm_dp_update_payload_part2] payload 0 1 [ 222.580687] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.580710] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.580765] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.581304] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.581879] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 222.581904] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 222.581935] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 222.582009] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.582032] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.582086] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.582586] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.582612] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.593980] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.594017] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.594046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.594051] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.594053] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.594080] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.594107] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.594132] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.594156] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.594178] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.594200] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.594205] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.594227] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.594231] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.594253] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.594274] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.594295] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.594316] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.594341] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.594362] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.594385] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.594407] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.594428] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.594524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 222.594566] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.610589] [drm:intel_mst_disable_dp [i915]] 1 [ 222.610596] [drm:drm_dp_update_payload_part1] [ 222.612156] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.612216] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.612352] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.613255] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.615304] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.615368] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.615764] [drm:drm_dp_update_payload_part1] removing payload 0 [ 222.615829] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 222.615889] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 222.616002] [drm:intel_disable_pipe [i915]] disabling pipe B [ 222.627555] [drm:intel_mst_post_disable_dp [i915]] 1 [ 222.634227] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 222.634790] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 222.634824] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 222.634860] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 222.634906] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.634937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.634966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.634993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.635018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.635044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.635071] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.635101] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.635128] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.635156] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.635181] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.635206] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.635252] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.635281] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.635310] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.636030] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.636089] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.636137] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.636147] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.636152] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.636199] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.636246] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.636291] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.636333] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.636361] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.636386] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.636392] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.636417] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.636422] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.636451] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.636528] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.636945] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.636990] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.637038] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.637082] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.637127] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.637169] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.637211] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.637278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 222.637319] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.637415] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 222.637501] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.637806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.637851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.637894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.637938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.637981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.638025] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.638072] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.638118] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.638162] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.638190] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.638215] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.638246] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 222.638274] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 222.638321] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 222.640091] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 222.640122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 222.640149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 222.640178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 222.657132] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 222.657150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 222.674053] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 222.676122] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 222.676321] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 222.677416] [drm:intel_enable_pipe [i915]] enabling pipe B [ 222.677444] [drm:intel_mst_enable_dp [i915]] 1 [ 222.679928] [drm:drm_dp_update_payload_part2] payload 0 1 [ 222.681299] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.681321] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.681360] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.681897] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.682481] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 222.682580] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 222.682615] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 222.682706] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.682734] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.682778] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.683189] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.683207] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.694515] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.694550] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.694576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.694582] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.694584] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.694609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.694634] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.694657] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.694680] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.694701] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.694722] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.694727] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.694747] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.694751] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.694772] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.694792] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.694812] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.694832] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.694855] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.694875] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.694904] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.694932] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.694960] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.694999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 222.695032] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.711087] [drm:intel_mst_disable_dp [i915]] 1 [ 222.711094] [drm:drm_dp_update_payload_part1] [ 222.712640] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.712682] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.712783] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.713453] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.715347] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.715392] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.715705] [drm:drm_dp_update_payload_part1] removing payload 0 [ 222.715762] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 222.715825] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 222.715917] [drm:intel_disable_pipe [i915]] disabling pipe B [ 222.727735] [drm:intel_mst_post_disable_dp [i915]] 1 [ 222.734679] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 222.735132] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 222.735174] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 222.735220] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 222.735277] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.735317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.735353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.735388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.735422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.735475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.735551] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.735786] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.735819] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.735855] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.735887] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.735920] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.735977] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.736012] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.736050] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.736351] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.736395] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.736427] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.736459] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.736465] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.736503] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.736762] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.736798] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.736830] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.736863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.736895] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.736903] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.736934] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.736941] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.736971] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.737003] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.737035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.737067] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.737100] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.737128] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.737162] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.737194] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.737225] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.737273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 222.737313] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.737422] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 222.737495] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.737889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.737924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.737954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.737987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.738020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.738055] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.738089] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.738121] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.738156] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.738189] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.738221] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.738256] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 222.738287] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 222.738345] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 222.740016] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 222.740053] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 222.740087] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 222.740122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 222.756995] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 222.757013] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 222.773911] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 222.775980] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 222.776178] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 222.777267] [drm:intel_enable_pipe [i915]] enabling pipe B [ 222.777292] [drm:intel_mst_enable_dp [i915]] 1 [ 222.779704] [drm:drm_dp_update_payload_part2] payload 0 1 [ 222.781075] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.781097] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.781151] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.781696] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.782266] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 222.782292] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 222.782324] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 222.782394] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.782419] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.782509] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.783049] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.783076] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.794356] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.794397] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.794429] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.794472] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.794479] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.794523] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.794566] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.794604] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.794640] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.794675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.794711] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.794719] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.794752] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.794759] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.794794] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.794829] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.794863] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.794896] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.794934] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.794968] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.795004] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.795038] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.795071] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.795128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 222.795170] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.811008] [drm:intel_mst_disable_dp [i915]] 1 [ 222.811017] [drm:drm_dp_update_payload_part1] [ 222.812561] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.812606] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.812706] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.813341] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.815332] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.815383] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.815866] [drm:drm_dp_update_payload_part1] removing payload 0 [ 222.815912] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 222.815957] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 222.816023] [drm:intel_disable_pipe [i915]] disabling pipe B [ 222.828402] [drm:intel_mst_post_disable_dp [i915]] 1 [ 222.835127] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 222.835643] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 222.835677] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 222.835712] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 222.835760] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.835790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.835819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.835846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.835873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.835898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.835925] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.835955] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.835983] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.836011] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.836036] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.836061] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.836107] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.836142] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.836181] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.836474] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.836529] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.836949] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.836956] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.836958] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.836989] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.837020] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.837050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.837077] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.837103] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.837129] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.837135] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.837160] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.837165] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.837191] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.837218] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.837249] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.837288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.837334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.837380] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.837426] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.837495] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.837537] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.837605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 222.837656] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.837800] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 222.837862] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.837905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.837945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.837988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.838029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.838068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.838110] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.838156] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.838199] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.838241] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.838280] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.838317] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.838363] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 222.838404] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 222.838490] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 222.840294] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 222.840311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 222.840327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 222.840343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 222.857243] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 222.857261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 222.874282] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 222.876350] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 222.876549] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 222.877735] [drm:intel_enable_pipe [i915]] enabling pipe B [ 222.877762] [drm:intel_mst_enable_dp [i915]] 1 [ 222.880156] [drm:drm_dp_update_payload_part2] payload 0 1 [ 222.881539] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.881562] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.881618] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.882176] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.882747] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 222.882772] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 222.882803] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 222.882872] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.882896] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.882951] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.883467] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.883513] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.894848] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.894887] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.894919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.894925] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.894927] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.894959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.894990] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.895021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.895052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.895083] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.895113] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.895119] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.895149] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.895154] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.895185] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.895216] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.895246] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.895277] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.895308] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.895337] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.895369] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.895400] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.895431] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.895526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 222.895573] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.911537] [drm:intel_mst_disable_dp [i915]] 1 [ 222.911547] [drm:drm_dp_update_payload_part1] [ 222.913127] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.913183] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.913301] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.914094] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.916222] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.916282] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.916711] [drm:drm_dp_update_payload_part1] removing payload 0 [ 222.916791] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 222.916873] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 222.917002] [drm:intel_disable_pipe [i915]] disabling pipe B [ 222.928674] [drm:intel_mst_post_disable_dp [i915]] 1 [ 222.935381] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 222.936002] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 222.936028] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 222.936055] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 222.936092] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.936115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.936137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.936158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.936178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.936197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.936218] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.936240] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.936262] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.936282] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.936301] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.936320] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.936355] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.936376] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.936398] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.936722] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.936766] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.936802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.936809] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.936812] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.936847] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.936879] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.936912] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.936945] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.936977] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.937006] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.937013] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.937043] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.937050] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.937081] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.937112] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.937141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.937168] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.937253] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.937283] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.937313] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.937343] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.937374] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.937423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 222.937485] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 222.937595] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 222.937647] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 222.937680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 222.937709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 222.937741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 222.937772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 222.937804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 222.937834] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 222.937864] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 222.937898] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 222.937931] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 222.937961] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 222.937989] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.938021] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 222.938055] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 222.938111] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 222.939621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 222.939641] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 222.939659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 222.939679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 222.956601] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 222.956620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 222.973518] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 222.975578] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 222.975774] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 222.976908] [drm:intel_enable_pipe [i915]] enabling pipe B [ 222.976935] [drm:intel_mst_enable_dp [i915]] 1 [ 222.979329] [drm:drm_dp_update_payload_part2] payload 0 1 [ 222.980696] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 222.980718] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 222.980772] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 222.981308] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 222.981888] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 222.981914] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 222.981945] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 222.982016] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 222.982041] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 222.982100] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 222.982601] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 222.982627] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 222.993970] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 222.994006] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 222.994034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 222.994039] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 222.994041] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 222.994067] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 222.994093] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 222.994117] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 222.994141] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 222.994163] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 222.994184] [drm:intel_dump_pipe_config [i915]] requested mode: [ 222.994190] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.994211] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 222.994215] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 222.994237] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 222.994259] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 222.994279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 222.994300] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 222.994325] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 222.994353] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 222.994384] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 222.994413] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 222.994443] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 222.994533] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 222.994578] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.010534] [drm:intel_mst_disable_dp [i915]] 1 [ 223.010541] [drm:drm_dp_update_payload_part1] [ 223.012085] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.012137] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.012225] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.012960] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.014967] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.015031] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.015337] [drm:drm_dp_update_payload_part1] removing payload 0 [ 223.015389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 223.015453] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 223.015626] [drm:intel_disable_pipe [i915]] disabling pipe B [ 223.028021] [drm:intel_mst_post_disable_dp [i915]] 1 [ 223.034711] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 223.035140] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 223.035178] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 223.035218] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 223.035272] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.035310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.035346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.035384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.035420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.035464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.035551] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.035606] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.035657] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.035702] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.035746] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.035793] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.035870] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.035917] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.035970] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.036390] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.036448] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.036530] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.036537] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.036540] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.036569] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.036599] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.036630] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.036661] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.036690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.036717] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.036723] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.036751] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.036757] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.036787] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.036816] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.036842] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.036867] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.036899] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.036927] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.036956] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.036982] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.037008] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.037055] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 223.037091] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.037190] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 223.037235] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.037263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.037294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.037324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.037352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.037379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.037405] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.037438] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.037486] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.037517] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.037543] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.037568] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.037602] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 223.037633] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 223.037683] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 223.039513] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 223.039547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 223.039576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 223.039606] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 223.056538] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 223.056557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 223.073470] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 223.075535] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 223.075730] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 223.076926] [drm:intel_enable_pipe [i915]] enabling pipe B [ 223.076953] [drm:intel_mst_enable_dp [i915]] 1 [ 223.079353] [drm:drm_dp_update_payload_part2] payload 0 1 [ 223.080723] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.080745] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.080805] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.081344] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.081947] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 223.081972] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 223.082004] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 223.082072] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.082097] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.082145] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.082639] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.082657] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.094035] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.094074] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.094104] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.094109] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.094112] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.094140] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.094168] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.094195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.094221] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.094245] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.094275] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.094281] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.094312] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.094317] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.094348] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.094380] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.094411] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.094447] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.094542] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.094589] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.094634] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.094677] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.094720] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.094784] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 223.094832] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.110676] [drm:intel_mst_disable_dp [i915]] 1 [ 223.110686] [drm:drm_dp_update_payload_part1] [ 223.112257] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.112312] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.112439] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.113160] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.115154] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.115215] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.115526] [drm:drm_dp_update_payload_part1] removing payload 0 [ 223.115596] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 223.115674] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 223.115787] [drm:intel_disable_pipe [i915]] disabling pipe B [ 223.128130] [drm:intel_mst_post_disable_dp [i915]] 1 [ 223.134357] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 223.134903] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 223.134958] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 223.135016] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 223.135091] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.135142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.135189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.135233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.135277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.135319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.135363] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.135410] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.135455] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.135585] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.135652] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.135714] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.135830] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.135880] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.135946] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.136409] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.136566] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.136641] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.136659] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.136667] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.136736] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.136809] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.136879] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.136927] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.136973] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.137015] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.137026] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.137067] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.137076] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.137118] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.137160] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.137201] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.137243] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.137294] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.137337] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.137380] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.137421] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.137469] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.137529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 223.137562] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.137623] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 223.137655] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.137682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.137708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.137725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.137741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.137756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.137772] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.137790] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.137807] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.137824] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.137839] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.137854] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.137873] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 223.137890] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 223.137920] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 223.139392] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 223.139410] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 223.139427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 223.139476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 223.156328] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 223.156345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 223.173175] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 223.175233] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 223.175427] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 223.176546] [drm:intel_enable_pipe [i915]] enabling pipe B [ 223.176576] [drm:intel_mst_enable_dp [i915]] 1 [ 223.178967] [drm:drm_dp_update_payload_part2] payload 0 1 [ 223.180337] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.180359] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.180406] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.180951] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.181547] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 223.181571] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 223.181604] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 223.181672] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.181710] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.181752] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.182229] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.182246] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.193612] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.193646] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.193672] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.193677] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.193679] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.193703] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.193727] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.193749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.193771] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.193792] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.193811] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.193816] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.193835] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.193839] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.193859] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.193879] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.193899] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.193917] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.193940] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.193960] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.193988] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.194015] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.194042] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.194081] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 223.194111] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.210285] [drm:intel_mst_disable_dp [i915]] 1 [ 223.210295] [drm:drm_dp_update_payload_part1] [ 223.211848] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.211899] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.212024] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.212678] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.214618] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.214675] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.214978] [drm:drm_dp_update_payload_part1] removing payload 0 [ 223.215026] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 223.215080] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 223.215158] [drm:intel_disable_pipe [i915]] disabling pipe B [ 223.227482] [drm:intel_mst_post_disable_dp [i915]] 1 [ 223.234270] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 223.234706] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 223.234733] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 223.234762] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 223.234803] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.234831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.234859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.234886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.234914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.234941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.234967] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.234996] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.235025] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.235053] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.235079] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.235106] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.235149] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.235177] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.235207] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.235411] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.235443] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.235508] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.235517] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.235521] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.235559] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.235597] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.235631] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.235665] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.235694] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.235723] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.235731] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.235760] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.235768] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.235800] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.235832] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.235864] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.235893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.235925] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.235954] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.235986] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.236018] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.236049] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.236098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 223.236136] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.236249] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 223.236299] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.236331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.236365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.236398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.236431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.236483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.236517] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.236552] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.236587] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.236619] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.236647] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.236675] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.236713] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 223.236748] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 223.236806] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 223.239189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 223.239209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 223.239226] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 223.239243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 223.256211] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 223.256229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 223.273139] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 223.275208] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 223.275406] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 223.276506] [drm:intel_enable_pipe [i915]] enabling pipe B [ 223.276534] [drm:intel_mst_enable_dp [i915]] 1 [ 223.278935] [drm:drm_dp_update_payload_part2] payload 0 1 [ 223.280305] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.280327] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.280365] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.280913] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.281543] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 223.281570] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 223.281604] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 223.281691] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.281719] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.281762] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.282201] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.282218] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.293592] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.293627] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.293653] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.293658] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.293660] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.293685] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.293713] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.293741] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.293770] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.293797] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.293825] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.293830] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.293857] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.293862] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.293890] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.293918] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.293945] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.293973] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.294001] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.294027] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.294057] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.294084] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.294112] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.294154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 223.294186] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.310207] [drm:intel_mst_disable_dp [i915]] 1 [ 223.310214] [drm:drm_dp_update_payload_part1] [ 223.311751] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.311788] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.311914] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.312664] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.314648] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.314710] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.315002] [drm:drm_dp_update_payload_part1] removing payload 0 [ 223.315053] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 223.315105] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 223.315182] [drm:intel_disable_pipe [i915]] disabling pipe B [ 223.327557] [drm:intel_mst_post_disable_dp [i915]] 1 [ 223.334350] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 223.334764] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 223.334788] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 223.334813] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 223.334847] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.334869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.334889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.334907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.334925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.334943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.334962] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.334983] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.335002] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.335021] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.335038] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.335056] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.335088] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.335107] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.335128] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.335304] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.335329] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.335348] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.335352] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.335354] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.335373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.335392] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.335410] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.335431] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.335491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.335521] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.335530] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.335556] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.335563] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.335591] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.335618] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.335645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.335673] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.335704] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.335731] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.335760] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.335788] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.335816] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.335861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 223.335895] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.335983] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 223.336027] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.336055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.336082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.336108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.336135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.336161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.336188] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.336217] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.336245] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.336273] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.336299] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.336325] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.336355] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 223.336383] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 223.336433] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 223.337958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 223.337980] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 223.338000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 223.338020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 223.354923] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 223.354942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 223.371865] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 223.373933] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 223.374132] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 223.375264] [drm:intel_enable_pipe [i915]] enabling pipe B [ 223.375288] [drm:intel_mst_enable_dp [i915]] 1 [ 223.377671] [drm:drm_dp_update_payload_part2] payload 0 1 [ 223.379039] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.379060] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.379113] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.379653] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.380226] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 223.380249] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 223.380277] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 223.380341] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.380364] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.380415] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.380952] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.380969] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.392386] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.392418] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.392451] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.392486] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.392490] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.392524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.392692] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.392726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.392760] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.392792] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.392812] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.392817] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.392836] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.392840] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.392860] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.392878] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.392897] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.392915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.392937] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.392956] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.392975] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.392993] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.393011] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.393044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 223.393070] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.409030] [drm:intel_mst_disable_dp [i915]] 1 [ 223.409037] [drm:drm_dp_update_payload_part1] [ 223.410592] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.410643] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.410746] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.411558] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.413630] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.413688] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.413992] [drm:drm_dp_update_payload_part1] removing payload 0 [ 223.414040] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 223.414089] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 223.414163] [drm:intel_disable_pipe [i915]] disabling pipe B [ 223.426490] [drm:intel_mst_post_disable_dp [i915]] 1 [ 223.432783] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 223.433207] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 223.433238] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 223.433272] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 223.433318] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.433347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.433375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.433401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.433426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.433506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.433551] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.433595] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.433638] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.433681] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.433709] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.433734] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.433778] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.433805] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.433833] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.434066] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.434099] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.434125] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.434131] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.434134] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.434160] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.434187] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.434212] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.434237] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.434261] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.434284] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.434290] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.434313] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.434317] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.434341] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.434364] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.434386] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.434409] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.434436] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.434499] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.434539] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.434575] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.434613] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.434672] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 223.434719] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.434856] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 223.434917] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.434960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.435000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.435040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.435079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.435115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.435141] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.435169] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.435195] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.435221] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.435245] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.435267] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.435296] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 223.435323] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 223.435368] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 223.437093] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 223.437124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 223.437152] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 223.437179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 223.454128] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 223.454146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 223.471054] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 223.473114] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 223.473310] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 223.474461] [drm:intel_enable_pipe [i915]] enabling pipe B [ 223.474487] [drm:intel_mst_enable_dp [i915]] 1 [ 223.476902] [drm:drm_dp_update_payload_part2] payload 0 1 [ 223.478275] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.478299] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.478343] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.478902] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.479519] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 223.479547] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 223.479582] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 223.479657] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.479688] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.479741] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.480226] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.480247] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.491643] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.491681] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.491711] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.491716] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.491718] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.491746] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.491773] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.491799] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.491823] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.491846] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.491869] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.491874] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.491896] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.491901] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.491924] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.491947] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.491969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.491999] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.492030] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.492060] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.492092] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.492124] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.492155] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.492199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 223.492236] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.508226] [drm:intel_mst_disable_dp [i915]] 1 [ 223.508233] [drm:drm_dp_update_payload_part1] [ 223.509767] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.509808] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.509885] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.510537] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.512431] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.512506] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.512773] [drm:drm_dp_update_payload_part1] removing payload 0 [ 223.512818] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 223.512861] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 223.512924] [drm:intel_disable_pipe [i915]] disabling pipe B [ 223.525273] [drm:intel_mst_post_disable_dp [i915]] 1 [ 223.531651] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 223.532081] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 223.532114] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 223.532150] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 223.532197] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.532228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.532257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.532285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.532311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.532337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.532364] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.532393] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.532422] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.532512] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.532558] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.532602] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.532670] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.532711] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.532759] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.533153] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.533210] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.533256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.533265] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.533269] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.533313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.533355] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.533398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.533441] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.533520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.533561] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.533575] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.533617] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.533630] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.533674] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.533717] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.533756] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.533798] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.533846] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.533886] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.533927] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.533963] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.534003] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.534067] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 223.534117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.534262] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 223.534326] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.534372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.534414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.534453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.534521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.534567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.534613] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.534658] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.534707] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.534753] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.534793] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.534832] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.534876] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 223.534920] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 223.534993] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 223.536718] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 223.536765] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 223.536806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 223.536852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 223.553801] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 223.553820] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 223.570720] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 223.572789] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 223.572987] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 223.574093] [drm:intel_enable_pipe [i915]] enabling pipe B [ 223.574121] [drm:intel_mst_enable_dp [i915]] 1 [ 223.576524] [drm:drm_dp_update_payload_part2] payload 0 1 [ 223.577899] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.577922] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.577977] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.578519] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.579093] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 223.579117] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 223.579148] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 223.579218] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.579242] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.579299] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.579799] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.579822] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.591175] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.591210] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.591237] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.591242] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.591244] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.591269] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.591294] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.591318] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.591341] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.591362] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.591383] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.591388] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.591409] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.591413] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.591434] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.591499] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.591532] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.591563] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.591599] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.591631] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.591663] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.591693] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.591722] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.591775] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 223.591815] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.607742] [drm:intel_mst_disable_dp [i915]] 1 [ 223.607748] [drm:drm_dp_update_payload_part1] [ 223.609287] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.609331] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.609428] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.610262] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.612200] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.612247] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.612562] [drm:drm_dp_update_payload_part1] removing payload 0 [ 223.612627] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 223.612690] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 223.612789] [drm:intel_disable_pipe [i915]] disabling pipe B [ 223.624637] [drm:intel_mst_post_disable_dp [i915]] 1 [ 223.631966] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 223.632407] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 223.632451] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 223.632561] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 223.632637] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.632690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.632724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.632756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.632788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.632817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.632849] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.632883] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.632914] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.632946] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.632975] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.633004] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.633057] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.633089] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.633123] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.633414] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.633492] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.633528] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.633538] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.633543] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.633578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.633612] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.633646] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.633680] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.633712] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.633744] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.633753] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.633785] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.633792] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.633825] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.633857] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.633888] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.633921] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.633958] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.633991] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.634027] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.634060] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.634093] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.634143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 223.634173] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.634253] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 223.634289] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.634312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.634334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.634355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.634375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.634396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.634417] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.634475] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.634510] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.634544] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.634576] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.634607] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.634643] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 223.634676] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 223.634737] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 223.636227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 223.636245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 223.636260] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 223.636276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 223.653144] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 223.653162] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 223.670061] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 223.672120] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 223.672315] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 223.673449] [drm:intel_enable_pipe [i915]] enabling pipe B [ 223.673475] [drm:intel_mst_enable_dp [i915]] 1 [ 223.675879] [drm:drm_dp_update_payload_part2] payload 0 1 [ 223.677264] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.677288] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.677330] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.677869] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.678430] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 223.678466] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 223.678563] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 223.678645] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.678668] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.678706] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.679121] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.679137] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.690507] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.690538] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.690562] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.690567] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.690568] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.690591] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.690614] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.690634] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.690655] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.690673] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.690692] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.690696] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.690714] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.690718] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.690737] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.690754] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.690772] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.690790] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.690811] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.690829] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.690848] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.690866] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.690883] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.690913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 223.690937] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.707090] [drm:intel_mst_disable_dp [i915]] 1 [ 223.707098] [drm:drm_dp_update_payload_part1] [ 223.708638] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.708679] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.708742] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.709321] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.711357] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.711415] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.711770] [drm:drm_dp_update_payload_part1] removing payload 0 [ 223.711833] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 223.711887] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 223.711981] [drm:intel_disable_pipe [i915]] disabling pipe B [ 223.724346] [drm:intel_mst_post_disable_dp [i915]] 1 [ 223.730666] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 223.731063] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 223.731086] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 223.731112] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 223.731148] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.731170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.731191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.731210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.731229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.731248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.731268] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.731289] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.731309] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.731329] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.731347] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.731364] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.731398] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.731418] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.731484] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.731758] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.731800] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.731834] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.731842] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.731845] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.731877] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.731907] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.731938] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.731968] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.731999] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.732027] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.732034] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.732061] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.732068] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.732098] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.732127] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.732156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.732184] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.732214] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.732242] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.732273] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.732301] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.732330] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.732377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 223.732414] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.732549] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 223.732599] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.732628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.732662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.732693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.732745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.732787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.732819] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.732852] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.732901] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.732929] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.732959] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.733005] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.733039] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 223.733068] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 223.733139] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 223.734776] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 223.734809] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 223.734839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 223.734872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 223.751785] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 223.751804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 223.768706] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 223.770767] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 223.770964] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 223.772061] [drm:intel_enable_pipe [i915]] enabling pipe B [ 223.772089] [drm:intel_mst_enable_dp [i915]] 1 [ 223.774485] [drm:drm_dp_update_payload_part2] payload 0 1 [ 223.775849] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.775872] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.775912] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.776478] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.777052] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 223.777078] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 223.777109] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 223.777183] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.777210] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.777273] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.777763] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.777781] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.789165] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.789206] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.789237] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.789243] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.789245] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.789275] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.789305] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.789334] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.789361] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.789386] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.789412] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.789417] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.789488] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.789500] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.789536] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.789573] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.789608] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.789642] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.789682] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.789716] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.789752] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.789791] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.789826] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.789887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 223.789933] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.805759] [drm:intel_mst_disable_dp [i915]] 1 [ 223.805766] [drm:drm_dp_update_payload_part1] [ 223.807306] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.807344] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.807433] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.808312] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.810440] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.810535] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.810818] [drm:drm_dp_update_payload_part1] removing payload 0 [ 223.810874] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 223.810929] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 223.811036] [drm:intel_disable_pipe [i915]] disabling pipe B [ 223.822679] [drm:intel_mst_post_disable_dp [i915]] 1 [ 223.829640] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 223.830084] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 223.830124] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 223.830167] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 223.830224] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.830263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.830303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.830342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.830381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.830420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.830514] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.830721] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.830777] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.830830] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.830878] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.830924] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.831004] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.831052] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.831105] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.831569] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.831613] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.831647] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.831654] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.831659] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.831691] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.831725] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.831757] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.831788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.831817] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.831848] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.831858] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.831889] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.831898] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.831930] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.831960] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.831991] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.832021] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.832055] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.832085] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.832119] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.832149] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.832179] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.832231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 223.832289] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.832452] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 223.832561] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.832612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.832662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.832710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.832755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.832801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.832849] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.832897] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.832946] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.832993] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.833035] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.833077] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.833126] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 223.833173] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 223.833252] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 223.834833] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 223.834850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 223.834865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 223.834884] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 223.851800] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 223.851817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 223.868714] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 223.870783] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 223.870982] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 223.872073] [drm:intel_enable_pipe [i915]] enabling pipe B [ 223.872109] [drm:intel_mst_enable_dp [i915]] 1 [ 223.874490] [drm:drm_dp_update_payload_part2] payload 0 1 [ 223.875874] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.875897] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.875940] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.876484] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.877049] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 223.877074] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 223.877105] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 223.877181] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.877206] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.877262] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.877773] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.877794] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.889166] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.889205] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.889237] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.889243] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.889245] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.889278] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.889310] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.889341] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.889373] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.889404] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.889434] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.889492] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.889532] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.889541] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.889582] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.889618] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.889653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.889691] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.889732] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.889769] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.889807] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.889840] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.889863] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.889902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 223.889933] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.905780] [drm:intel_mst_disable_dp [i915]] 1 [ 223.905786] [drm:drm_dp_update_payload_part1] [ 223.907335] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.907389] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.907533] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.908271] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.910259] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.910319] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.910727] [drm:drm_dp_update_payload_part1] removing payload 0 [ 223.910808] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 223.910873] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 223.910956] [drm:intel_disable_pipe [i915]] disabling pipe B [ 223.922705] [drm:intel_mst_post_disable_dp [i915]] 1 [ 223.928956] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 223.929383] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 223.929416] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 223.929497] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 223.929707] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.929752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.929799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.929844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.929887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.929927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.929967] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.930017] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.930062] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.930107] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.930146] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.930183] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.930255] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.930301] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.930347] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.930767] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.930821] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.930861] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.930873] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.930877] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.930920] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.930965] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.931006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.931044] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.931084] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.931122] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.931130] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.931168] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.931177] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.931214] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.931251] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.931291] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.931330] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.931374] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.931411] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.931450] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.931508] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.931546] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.931606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 223.931655] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 223.931791] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 223.931854] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 223.931896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 223.931936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 223.931974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 223.932009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 223.932050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 223.932090] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 223.932136] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 223.932176] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 223.932222] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 223.932263] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 223.932303] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.932346] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 223.932384] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 223.932454] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 223.934001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 223.934027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 223.934052] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 223.934079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 223.951002] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 223.951021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 223.967920] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 223.969971] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 223.970167] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 223.971262] [drm:intel_enable_pipe [i915]] enabling pipe B [ 223.971287] [drm:intel_mst_enable_dp [i915]] 1 [ 223.973682] [drm:drm_dp_update_payload_part2] payload 0 1 [ 223.975051] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 223.975072] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 223.975138] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 223.975695] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 223.976268] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 223.976294] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 223.976326] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 223.976395] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 223.976424] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 223.976544] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 223.977141] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 223.977161] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 223.988368] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 223.988403] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 223.988430] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 223.988851] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 223.988854] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 223.988884] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 223.988912] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 223.988937] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 223.988960] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 223.988982] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 223.989003] [drm:intel_dump_pipe_config [i915]] requested mode: [ 223.989008] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.989028] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 223.989032] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 223.989053] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 223.989074] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 223.989094] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 223.989114] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 223.989139] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 223.989159] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 223.989180] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 223.989200] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 223.989220] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 223.989257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 223.989286] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.004929] [drm:intel_mst_disable_dp [i915]] 1 [ 224.004935] [drm:drm_dp_update_payload_part1] [ 224.006470] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.006503] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.006561] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.007114] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.008922] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.008964] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.009259] [drm:drm_dp_update_payload_part1] removing payload 0 [ 224.009293] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 224.009328] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 224.009402] [drm:intel_disable_pipe [i915]] disabling pipe B [ 224.022595] [drm:intel_mst_post_disable_dp [i915]] 1 [ 224.028046] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 224.028586] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 224.028629] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 224.028677] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 224.028736] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.028776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.028814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.028850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.028885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.028918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.028956] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.028995] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.029031] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.029066] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.029099] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.029131] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.029193] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.029229] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.029266] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.029662] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.029709] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.029746] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.029754] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.029757] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.029793] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.029831] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.029866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.029901] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.029932] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.029963] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.029970] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.030002] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.030008] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.030039] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.030070] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.030101] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.030131] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.030168] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.030199] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.030232] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.030263] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.030293] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.030346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 224.030391] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.030591] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 224.030662] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.030699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.030734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.030767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.030799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.030831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.030866] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.030902] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.030936] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.030969] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.031002] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.031033] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.031073] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 224.031119] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 224.031186] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 224.032757] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 224.032777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 224.032794] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 224.032815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 224.049706] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 224.049723] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 224.066597] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 224.068489] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 224.068687] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 224.069836] [drm:intel_enable_pipe [i915]] enabling pipe B [ 224.069871] [drm:intel_mst_enable_dp [i915]] 1 [ 224.071809] [drm:drm_dp_update_payload_part2] payload 0 1 [ 224.073179] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.073201] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.073248] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.073813] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.074379] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 224.074403] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 224.074436] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 224.074655] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.074681] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.074773] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.075073] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.075090] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.086908] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.086945] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.086973] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.086978] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.086980] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.087006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.087033] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.087058] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.087082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.087104] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.087126] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.087131] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.087153] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.087157] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.087179] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.087201] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.087222] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.087243] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.087268] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.087290] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.087312] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.087333] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.087354] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.087390] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 224.087419] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.103506] [drm:intel_mst_disable_dp [i915]] 1 [ 224.103512] [drm:drm_dp_update_payload_part1] [ 224.105039] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.105074] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.105137] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.105718] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.107551] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.107588] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.107910] [drm:drm_dp_update_payload_part1] removing payload 0 [ 224.107957] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 224.108004] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 224.108092] [drm:intel_disable_pipe [i915]] disabling pipe B [ 224.121650] [drm:intel_mst_post_disable_dp [i915]] 1 [ 224.126597] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 224.127066] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 224.127113] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 224.127163] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 224.127227] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.127272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.127317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.127362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.127405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.127450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.127555] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.127619] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.127676] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.127738] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.127788] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.127837] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.127931] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.127972] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.128015] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.128373] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.128408] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.128446] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.128495] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.128498] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.128531] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.128556] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.128577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.128596] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.128615] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.128633] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.128639] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.128659] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.128665] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.128695] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.128724] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.128753] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.128782] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.128815] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.128839] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.128859] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.128876] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.128894] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.128925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 224.128952] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.129057] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 224.129105] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.129137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.129168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.129196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.129216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.129234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.129253] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.129274] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.129293] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.129313] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.129341] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.129370] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.129405] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 224.129431] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 224.129501] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 224.131143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 224.131166] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 224.131186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 224.131207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 224.148057] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 224.148074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 224.164906] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 224.166488] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 224.166684] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 224.167852] [drm:intel_enable_pipe [i915]] enabling pipe B [ 224.167877] [drm:intel_mst_enable_dp [i915]] 1 [ 224.169805] [drm:drm_dp_update_payload_part2] payload 0 1 [ 224.171185] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.171207] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.171261] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.171819] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.172386] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 224.172411] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 224.172465] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 224.172536] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.172562] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.172606] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.173083] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.173100] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.184992] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.185030] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.185060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.185066] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.185068] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.185095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.185122] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.185147] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.185172] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.185195] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.185218] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.185223] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.185246] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.185250] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.185273] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.185296] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.185319] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.185340] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.185366] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.185388] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.185412] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.185434] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.185541] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.185604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 224.185650] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.201595] [drm:intel_mst_disable_dp [i915]] 1 [ 224.201601] [drm:drm_dp_update_payload_part1] [ 224.203151] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.203199] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.203297] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.203940] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.205967] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.206018] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.206316] [drm:drm_dp_update_payload_part1] removing payload 0 [ 224.206365] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 224.206411] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 224.206563] [drm:intel_disable_pipe [i915]] disabling pipe B [ 224.218967] [drm:intel_mst_post_disable_dp [i915]] 1 [ 224.225661] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 224.226145] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 224.226192] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 224.226242] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 224.226304] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.226348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.226387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.226426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.226534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.226776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.226837] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.227138] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.227205] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.227271] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.227347] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.227401] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.227758] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.227820] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.228081] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.228579] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.228616] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.228642] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.228646] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.228648] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.228673] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.228692] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.228710] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.228727] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.228743] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.228759] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.228763] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.228779] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.228782] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.228798] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.228814] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.228829] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.228844] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.228862] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.228878] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.228895] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.228910] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.228925] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.228952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 224.228974] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.229036] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 224.229066] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.229084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.229101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.229117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.229132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.229147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.229164] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.229243] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.229260] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.229277] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.229292] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.229307] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.229326] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 224.229343] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 224.229373] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 224.231252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 224.231270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 224.231285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 224.231300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 224.248205] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 224.248222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 224.265107] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 224.266487] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 224.266683] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 224.267786] [drm:intel_enable_pipe [i915]] enabling pipe B [ 224.267811] [drm:intel_mst_enable_dp [i915]] 1 [ 224.269825] [drm:drm_dp_update_payload_part2] payload 0 1 [ 224.271198] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.271219] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.271263] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.271818] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.272395] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 224.272424] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 224.272477] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 224.272555] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.272586] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.272635] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.273092] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.273111] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.284928] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.284962] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.284988] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.284993] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.284995] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.285018] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.285043] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.285065] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.285086] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.285107] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.285127] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.285132] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.285151] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.285155] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.285176] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.285196] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.285215] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.285234] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.285257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.285277] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.285298] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.285317] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.285336] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.285369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 224.285395] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.301556] [drm:intel_mst_disable_dp [i915]] 1 [ 224.301565] [drm:drm_dp_update_payload_part1] [ 224.303122] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.303173] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.303292] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.303959] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.305916] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.305973] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.306278] [drm:drm_dp_update_payload_part1] removing payload 0 [ 224.306327] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 224.306377] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 224.306458] [drm:intel_disable_pipe [i915]] disabling pipe B [ 224.318776] [drm:intel_mst_post_disable_dp [i915]] 1 [ 224.325289] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 224.325835] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 224.325889] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 224.325943] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 224.326009] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.326056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.326098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.326138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.326177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.326216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.326257] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.326301] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.326343] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.326384] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.326426] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.326549] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.326660] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.326728] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.326802] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.327363] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.327447] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.327597] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.327611] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.327619] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.327688] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.327757] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.327823] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.327883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.327939] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.328001] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.328015] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.328075] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.328088] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.328151] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.328209] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.328263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.328324] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.328393] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.328454] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.328554] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.328615] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.328684] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.328786] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 224.328864] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.329342] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 224.329383] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.329407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.329431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.329474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.329501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.329615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.329638] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.329666] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.329692] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.329718] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.329741] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.329762] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.329790] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 224.329816] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 224.329858] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 224.331348] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 224.331371] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 224.331394] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 224.331418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 224.348330] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 224.348347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 224.365253] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 224.367313] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 224.367521] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 224.368669] [drm:intel_enable_pipe [i915]] enabling pipe B [ 224.368696] [drm:intel_mst_enable_dp [i915]] 1 [ 224.371097] [drm:drm_dp_update_payload_part2] payload 0 1 [ 224.372476] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.372499] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.372553] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.373101] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.373670] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 224.373696] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 224.373727] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 224.373796] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.373821] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.373880] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.374367] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.374385] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.385770] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.385803] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.385829] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.385834] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.385836] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.385860] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.385885] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.385908] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.385930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.385951] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.385971] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.385976] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.385995] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.385999] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.386020] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.386040] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.386060] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.386079] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.386102] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.386121] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.386142] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.386162] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.386181] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.386213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 224.386240] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.402422] [drm:intel_mst_disable_dp [i915]] 1 [ 224.402448] [drm:drm_dp_update_payload_part1] [ 224.403989] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.404023] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.404105] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.404693] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.406598] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.406650] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.406950] [drm:drm_dp_update_payload_part1] removing payload 0 [ 224.406998] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 224.407044] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 224.407112] [drm:intel_disable_pipe [i915]] disabling pipe B [ 224.419403] [drm:intel_mst_post_disable_dp [i915]] 1 [ 224.426167] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 224.426659] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 224.426696] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 224.426735] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 224.426784] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.426817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.426848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.426878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.426905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.426932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.426968] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.427008] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.427046] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.427084] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.427121] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.427156] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.427214] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.427252] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.427293] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.427908] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.427942] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.427970] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.427976] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.427978] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.428004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.428029] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.428053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.428076] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.428098] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.428120] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.428126] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.428146] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.428151] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.428171] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.428192] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.428213] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.428233] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.428257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.428278] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.428300] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.428320] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.428340] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.428375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 224.428403] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.428632] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 224.428674] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.428698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.428722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.428744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.428766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.428788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.428810] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.428833] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.428856] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.428878] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.428901] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.428934] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.428973] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 224.429010] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 224.429069] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 224.430602] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 224.430624] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 224.430643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 224.430664] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 224.447583] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 224.447600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 224.464499] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 224.466559] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 224.466758] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 224.467885] [drm:intel_enable_pipe [i915]] enabling pipe B [ 224.467910] [drm:intel_mst_enable_dp [i915]] 1 [ 224.470304] [drm:drm_dp_update_payload_part2] payload 0 1 [ 224.471688] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.471711] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.471765] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.472303] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.472884] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 224.472907] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 224.472936] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 224.473000] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.473023] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.473074] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.473579] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.473604] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.484953] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.484989] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.485016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.485021] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.485023] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.485049] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.485074] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.485098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.485121] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.485142] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.485162] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.485167] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.485187] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.485191] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.485212] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.485233] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.485253] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.485272] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.485296] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.485316] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.485337] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.485357] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.485376] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.485412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 224.485485] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.501532] [drm:intel_mst_disable_dp [i915]] 1 [ 224.501539] [drm:drm_dp_update_payload_part1] [ 224.503069] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.503103] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.503165] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.503788] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.505779] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.505841] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.506129] [drm:drm_dp_update_payload_part1] removing payload 0 [ 224.506183] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 224.506241] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 224.506322] [drm:intel_disable_pipe [i915]] disabling pipe B [ 224.519741] [drm:intel_mst_post_disable_dp [i915]] 1 [ 224.524952] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 224.525371] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 224.525402] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 224.525443] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 224.525551] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.525594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.525633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.525671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.525709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.525747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.525785] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.525825] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.525864] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.525903] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.525938] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.525974] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.526040] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.526078] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.526119] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.526369] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.526403] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.526437] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.526476] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.526483] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.526525] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.526568] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.526608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.526649] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.526687] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.526725] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.526736] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.526771] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.526782] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.526821] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.526858] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.526895] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.526932] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.526972] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.527011] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.527050] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.527086] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.527120] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.527180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 224.527226] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.527353] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 224.527396] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.527428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.527492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.527532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.527570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.527609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.527650] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.527691] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.527730] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.527770] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.527806] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.527840] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.527881] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 224.527920] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 224.527986] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 224.529540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 224.529572] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 224.529599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 224.529628] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 224.546560] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 224.546580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 224.563479] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 224.565552] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 224.565751] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 224.566879] [drm:intel_enable_pipe [i915]] enabling pipe B [ 224.566904] [drm:intel_mst_enable_dp [i915]] 1 [ 224.569298] [drm:drm_dp_update_payload_part2] payload 0 1 [ 224.570677] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.570699] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.570738] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.571273] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.571844] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 224.571867] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 224.571896] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 224.571961] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.571987] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.572035] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.572531] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.572554] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.584038] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.584078] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.584108] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.584113] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.584116] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.584146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.584178] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.584209] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.584241] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.584272] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.584303] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.584308] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.584339] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.584343] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.584375] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.584406] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.584437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.584504] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.584548] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.584708] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.584746] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.584784] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.584822] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.585503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 224.585554] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.600638] [drm:intel_mst_disable_dp [i915]] 1 [ 224.600645] [drm:drm_dp_update_payload_part1] [ 224.602180] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.602231] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.602349] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.602999] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.604969] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.605031] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.605323] [drm:drm_dp_update_payload_part1] removing payload 0 [ 224.605375] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 224.605435] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 224.605577] [drm:intel_disable_pipe [i915]] disabling pipe B [ 224.617578] [drm:intel_mst_post_disable_dp [i915]] 1 [ 224.623822] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 224.624252] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 224.624284] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 224.624320] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 224.624367] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.624399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.624427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.624501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.624542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.624583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.624629] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.624677] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.624723] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.624768] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.624809] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.624839] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.624889] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.624918] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.624948] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.625294] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.625349] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.625381] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.625388] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.625390] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.625420] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.625495] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.625538] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.625579] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.625619] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.625657] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.625667] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.625704] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.625713] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.625751] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.625790] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.625827] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.625864] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.625908] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.625945] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.625989] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.626029] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.626072] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.626139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 224.626190] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.626335] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 224.626381] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.626410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.626482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.626524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.626563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.626604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.626648] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.626694] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.626738] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.626780] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.626808] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.626833] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.626864] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 224.626893] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 224.626942] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 224.628497] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 224.628516] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 224.628533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 224.628550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 224.645466] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 224.645484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 224.662382] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 224.664444] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 224.664640] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 224.665785] [drm:intel_enable_pipe [i915]] enabling pipe B [ 224.665810] [drm:intel_mst_enable_dp [i915]] 1 [ 224.668202] [drm:drm_dp_update_payload_part2] payload 0 1 [ 224.669576] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.669599] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.669643] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.670184] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.670756] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 224.670779] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 224.670807] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 224.670869] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.670891] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.670933] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.671450] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.671475] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.682934] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.682970] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.682999] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.683004] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.683007] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.683033] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.683059] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.683084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.683108] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.683131] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.683152] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.683158] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.683179] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.683183] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.683206] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.683228] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.683249] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.683270] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.683295] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.683316] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.683339] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.683360] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.683381] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.683416] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 224.683487] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.699570] [drm:intel_mst_disable_dp [i915]] 1 [ 224.699576] [drm:drm_dp_update_payload_part1] [ 224.701128] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.701179] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.701297] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.702090] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.704002] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.704059] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.704355] [drm:drm_dp_update_payload_part1] removing payload 0 [ 224.704401] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 224.704520] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 224.704628] [drm:intel_disable_pipe [i915]] disabling pipe B [ 224.716629] [drm:intel_mst_post_disable_dp [i915]] 1 [ 224.723362] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 224.723768] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 224.723793] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 224.723819] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 224.723856] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.723879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.723899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.723919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.723938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.723956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.723976] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.723997] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.724017] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.724042] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.724066] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.724091] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.724132] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.724158] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.724185] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.724371] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.724401] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.724431] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.724468] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.724570] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.724604] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.724636] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.724983] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.725016] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.725049] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.725080] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.725087] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.725116] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.725122] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.725151] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.725181] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.725210] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.725239] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.725270] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.725297] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.725328] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.725357] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.725386] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.725432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 224.725500] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.725692] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 224.725742] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.725776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.725807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.725835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.725865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.725895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.725926] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.725957] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.725986] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.726019] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.726048] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.726077] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.726109] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 224.726138] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 224.726191] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 224.727753] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 224.727788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 224.727820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 224.727870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 224.744839] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 224.744857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 224.761758] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 224.763827] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 224.764025] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 224.765115] [drm:intel_enable_pipe [i915]] enabling pipe B [ 224.765142] [drm:intel_mst_enable_dp [i915]] 1 [ 224.767546] [drm:drm_dp_update_payload_part2] payload 0 1 [ 224.768931] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.768955] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.769011] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.769563] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.770136] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 224.770162] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 224.770194] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 224.770266] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.770294] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.770386] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.770822] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.770841] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.782203] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.782240] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.782268] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.782274] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.782276] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.782303] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.782330] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.782355] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.782379] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.782402] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.782432] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.782486] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.782520] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.782527] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.782561] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.782593] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.782624] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.782655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.782692] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.782723] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.782756] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.782788] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.782821] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.782875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 224.782917] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.798806] [drm:intel_mst_disable_dp [i915]] 1 [ 224.798814] [drm:drm_dp_update_payload_part1] [ 224.800362] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.800412] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.800513] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.801284] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.803209] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.803271] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.803571] [drm:drm_dp_update_payload_part1] removing payload 0 [ 224.803641] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 224.803714] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 224.803815] [drm:intel_disable_pipe [i915]] disabling pipe B [ 224.816213] [drm:intel_mst_post_disable_dp [i915]] 1 [ 224.822126] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 224.822671] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 224.822745] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 224.822826] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 224.822926] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.822996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.823057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.823122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.823186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.823248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.823309] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.823381] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.823449] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.823580] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.823643] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.823702] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.823813] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.823881] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.823951] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.824526] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.824565] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.824594] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.824601] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.824604] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.824635] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.824667] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.824698] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.824725] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.824754] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.824782] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.824789] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.824817] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.824822] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.824848] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.824873] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.824901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.824928] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.824960] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.824986] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.825012] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.825040] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.825068] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.825112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 224.825148] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.825246] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 224.825293] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.825324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.825353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.825380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.825409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.825461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.825493] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.825526] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.825556] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.825589] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.825619] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.825648] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.825680] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 224.825711] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 224.825764] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 224.827268] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 224.827294] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 224.827320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 224.827347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 224.844242] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 224.844259] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 224.861097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 224.863166] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 224.863364] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 224.864527] [drm:intel_enable_pipe [i915]] enabling pipe B [ 224.864552] [drm:intel_mst_enable_dp [i915]] 1 [ 224.866953] [drm:drm_dp_update_payload_part2] payload 0 1 [ 224.868322] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.868344] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.868384] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.868938] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.869575] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 224.869606] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 224.869653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 224.869734] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.869810] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.869858] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.870236] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.870258] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.881626] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.881657] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.881682] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.881687] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.881688] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.881711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.881734] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.881755] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.881776] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.881796] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.881815] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.881820] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.881839] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.881842] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.881862] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.881880] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.881899] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.881917] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.881939] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.881958] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.881977] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.881996] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.882014] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.882044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 224.882070] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.898278] [drm:intel_mst_disable_dp [i915]] 1 [ 224.898286] [drm:drm_dp_update_payload_part1] [ 224.899836] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.899881] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.899990] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.900633] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.902549] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.902596] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.902895] [drm:drm_dp_update_payload_part1] removing payload 0 [ 224.902938] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 224.902981] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 224.903046] [drm:intel_disable_pipe [i915]] disabling pipe B [ 224.915418] [drm:intel_mst_post_disable_dp [i915]] 1 [ 224.922313] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 224.922793] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 224.922839] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 224.922873] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 224.922917] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.922947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.922974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.923007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.923040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.923073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.923105] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.923140] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.923174] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.923209] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.923241] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.923272] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.923326] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.923359] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.923395] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.923817] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.923866] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.923897] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.923904] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.923906] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.923935] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.923964] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.923992] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.924031] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.924055] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.924127] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.924133] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.924158] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.924163] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.924187] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.924211] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.924234] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.924257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.924285] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.924308] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.924333] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.924357] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.924379] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.924425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 224.924488] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.924578] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 224.924619] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 224.924647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 224.924687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 224.924727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 224.924755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 224.924779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 224.924804] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 224.924830] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 224.924857] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 224.924911] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 224.924936] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 224.924959] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.924988] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 224.925015] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 224.925097] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 224.926688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 224.926719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 224.926747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 224.926775] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 224.943694] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 224.943713] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 224.960613] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 224.962681] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 224.962880] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 224.964044] [drm:intel_enable_pipe [i915]] enabling pipe B [ 224.964072] [drm:intel_mst_enable_dp [i915]] 1 [ 224.966471] [drm:drm_dp_update_payload_part2] payload 0 1 [ 224.967859] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.967882] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.967935] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 224.968481] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 224.969051] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 224.969077] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 224.969108] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 224.969175] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 224.969200] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 224.969281] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 224.969744] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 224.969770] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 224.981163] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 224.981198] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 224.981225] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 224.981230] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 224.981233] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 224.981258] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 224.981283] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 224.981307] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 224.981330] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 224.981351] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 224.981372] [drm:intel_dump_pipe_config [i915]] requested mode: [ 224.981377] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.981397] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 224.981401] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 224.981422] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 224.981498] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 224.981536] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 224.981569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 224.981607] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 224.981640] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 224.981675] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 224.981709] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 224.981743] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 224.981799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 224.981841] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 224.997811] [drm:intel_mst_disable_dp [i915]] 1 [ 224.997818] [drm:drm_dp_update_payload_part1] [ 224.999354] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 224.999404] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 224.999516] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.000173] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.002187] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.002246] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.002556] [drm:drm_dp_update_payload_part1] removing payload 0 [ 225.002629] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 225.002710] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 225.002824] [drm:intel_disable_pipe [i915]] disabling pipe B [ 225.014648] [drm:intel_mst_post_disable_dp [i915]] 1 [ 225.020821] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 225.021244] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 225.021277] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 225.021313] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 225.021360] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.021391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.021427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.021513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.021561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.021607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.021652] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.021695] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.021774] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.021820] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.021860] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.021897] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.021969] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.022055] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.022104] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.022545] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.022589] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.022623] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.022630] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.022634] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.022668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.022723] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 225.022777] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 225.022810] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.022841] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.022871] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.022878] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.022932] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.022938] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.022970] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.022999] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.023028] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.023076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.023110] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.023140] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.023170] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.023222] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 225.023253] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 225.023300] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 225.023340] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 225.023490] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 225.023543] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.023575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.023610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.023643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.023676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.023706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.023736] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.023772] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.023806] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.023839] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.023868] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.023896] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.023932] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 225.023985] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 225.024038] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 225.025579] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 225.025605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 225.025636] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 225.025661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 225.042583] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 225.042602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 225.059502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 225.061571] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 225.061770] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 225.062932] [drm:intel_enable_pipe [i915]] enabling pipe B [ 225.062959] [drm:intel_mst_enable_dp [i915]] 1 [ 225.065350] [drm:drm_dp_update_payload_part2] payload 0 1 [ 225.066724] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.066747] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.066822] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.067376] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.067973] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 225.068002] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 225.068037] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 225.068111] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.068140] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.068188] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.068682] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.068703] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.080075] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.080114] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.080144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.080149] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.080152] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.080180] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.080208] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 225.080235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 225.080261] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.080285] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.080308] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.080314] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.080337] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.080341] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.080366] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.080389] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.080412] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.080492] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.080532] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.080565] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.080600] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.080634] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 225.080668] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 225.080725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 225.080765] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 225.096717] [drm:intel_mst_disable_dp [i915]] 1 [ 225.096726] [drm:drm_dp_update_payload_part1] [ 225.098269] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.098310] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.098404] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.099192] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.101078] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.101126] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.101468] [drm:drm_dp_update_payload_part1] removing payload 0 [ 225.101538] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 225.101620] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 225.101732] [drm:intel_disable_pipe [i915]] disabling pipe B [ 225.113653] [drm:intel_mst_post_disable_dp [i915]] 1 [ 225.120857] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 225.121293] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 225.121327] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 225.121364] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 225.121413] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.121506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.121712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.121759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.121804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.121839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.121870] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.121902] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.121931] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.121960] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.121987] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.122014] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.122062] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.122092] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.122123] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.122398] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.122468] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.122677] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.122683] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.122686] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.122717] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.122748] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 225.122776] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 225.122795] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.122812] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.122829] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.122833] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.122849] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.122853] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.122870] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.122886] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.122909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.122931] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.122955] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.122977] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.123001] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.123024] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 225.123047] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 225.123082] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 225.123108] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 225.123178] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 225.123215] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.123238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.123261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.123285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.123308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.123331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.123354] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.123378] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.123402] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.123454] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.123923] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.123943] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.123966] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 225.123987] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 225.124019] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 225.125507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 225.125527] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 225.125546] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 225.125565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 225.142484] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 225.142501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 225.159397] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 225.161500] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 225.161698] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 225.162887] [drm:intel_enable_pipe [i915]] enabling pipe B [ 225.162914] [drm:intel_mst_enable_dp [i915]] 1 [ 225.165307] [drm:drm_dp_update_payload_part2] payload 0 1 [ 225.166683] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.166706] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.166765] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.167305] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.167906] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 225.167932] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 225.167963] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 225.168034] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.168062] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.168125] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.168620] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.168644] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.179972] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.180012] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.180042] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.180047] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.180050] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.180079] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.180107] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 225.180134] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 225.180160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.180184] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.180207] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.180213] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.180236] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.180240] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.180264] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.180288] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.180311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.180333] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.180360] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.180383] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.180407] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.180488] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 225.180528] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 225.180586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 225.180629] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 225.196553] [drm:intel_mst_disable_dp [i915]] 1 [ 225.196559] [drm:drm_dp_update_payload_part1] [ 225.198118] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.198172] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.198273] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.199070] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.201054] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.201117] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.201395] [drm:drm_dp_update_payload_part1] removing payload 0 [ 225.201456] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 225.201602] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 225.201719] [drm:intel_disable_pipe [i915]] disabling pipe B [ 225.213864] [drm:intel_mst_post_disable_dp [i915]] 1 [ 225.220309] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 225.220792] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 225.220832] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 225.220873] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 225.220925] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.220960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.220993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.221024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.221054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.221084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.221115] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.221148] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.221180] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.221210] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.221239] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.221267] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.221318] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.221349] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.221382] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.221866] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.221915] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.221956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.221966] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.221970] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.222009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.222048] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 225.222086] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 225.222124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.222150] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.222172] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.222178] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.222199] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.222204] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.222225] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.222246] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.222268] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.222288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.222313] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.222334] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.222357] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.222377] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 225.222398] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 225.222488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 225.222526] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 225.222625] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 225.222666] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.222692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.222717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.222741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.222766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.222789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.222814] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.222841] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.222866] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.222891] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.222913] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.222937] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.222965] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 225.222990] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 225.223035] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 225.224585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 225.224604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 225.224622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 225.224640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 225.241541] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 225.241560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 225.258460] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 225.260524] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 225.260720] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 225.261852] [drm:intel_enable_pipe [i915]] enabling pipe B [ 225.261878] [drm:intel_mst_enable_dp [i915]] 1 [ 225.264282] [drm:drm_dp_update_payload_part2] payload 0 1 [ 225.265654] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.265676] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.265715] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.266251] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.266836] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 225.266861] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 225.266892] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 225.266962] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.266987] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.267044] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.267557] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.267582] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.278899] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.278935] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.278963] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.278968] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.278970] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.278996] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.279023] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 225.279048] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 225.279078] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.279107] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.279136] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.279141] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.279170] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.279175] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.279205] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.279235] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.279264] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.279293] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.279322] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.279350] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.279381] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.279410] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 225.279480] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 225.279549] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 225.279599] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 225.295540] [drm:intel_mst_disable_dp [i915]] 1 [ 225.295547] [drm:drm_dp_update_payload_part1] [ 225.297085] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.297123] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.297209] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.297857] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.299769] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.299820] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.300116] [drm:drm_dp_update_payload_part1] removing payload 0 [ 225.300159] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 225.300203] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 225.300266] [drm:intel_disable_pipe [i915]] disabling pipe B [ 225.313812] [drm:intel_mst_post_disable_dp [i915]] 1 [ 225.319368] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 225.319862] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 225.319906] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 225.319951] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 225.320009] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.320049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.320086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.320121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.320155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.320188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.320223] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.320261] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.320297] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.320332] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.320365] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.320397] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.320545] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.320599] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.320661] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.321174] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.321249] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.321308] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.321321] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.321327] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.321376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.321420] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 225.321513] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 225.321573] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.321629] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.321681] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.321698] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.321749] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.321763] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.321814] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.321862] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.321914] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.321964] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.322017] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.322064] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.322115] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.322163] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 225.322212] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 225.322295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 225.322356] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 225.322505] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 225.322543] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.322567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.322591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.322613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.322636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.322657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.322680] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.322704] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.322728] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.322751] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.322772] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.322793] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.322819] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 225.322843] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 225.322885] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 225.324406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 225.324445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 225.324460] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 225.324476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 225.341390] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 225.341408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 225.358332] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 225.360401] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 225.360610] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 225.361832] [drm:intel_enable_pipe [i915]] enabling pipe B [ 225.361860] [drm:intel_mst_enable_dp [i915]] 1 [ 225.364259] [drm:drm_dp_update_payload_part2] payload 0 1 [ 225.365630] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.365651] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.365706] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.366251] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.366840] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 225.366870] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 225.366905] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 225.366981] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.367022] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.367068] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.367552] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.367581] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.378932] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.378979] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.379014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.379020] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.379023] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.379056] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.379089] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 225.379120] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 225.379150] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.379178] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.379206] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.379212] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.379239] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.379244] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.379272] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.379300] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.379327] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.379353] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.379384] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.379411] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.379487] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.379536] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 225.379580] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 225.379649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 225.379699] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 225.395499] [drm:intel_mst_disable_dp [i915]] 1 [ 225.395507] [drm:drm_dp_update_payload_part1] [ 225.397045] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.397087] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.397191] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.397884] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.400113] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.400181] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.400491] [drm:drm_dp_update_payload_part1] removing payload 0 [ 225.400564] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 225.400642] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 225.400757] [drm:intel_disable_pipe [i915]] disabling pipe B [ 225.412577] [drm:intel_mst_post_disable_dp [i915]] 1 [ 225.419331] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 225.419858] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 225.419894] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 225.419933] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 225.419981] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.420015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.420046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.420076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.420105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.420132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.420162] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.420193] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.420223] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.420252] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.420279] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.420305] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.420354] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.420383] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.420424] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.421158] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.421209] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.421249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.421257] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.421261] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.421301] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.421341] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 225.421379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 225.421413] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.421476] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.421664] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.421671] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.421699] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.421704] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.421733] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.421761] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.421786] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.421810] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.421841] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.421868] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.421897] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.421922] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 225.421946] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 225.421990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 225.422025] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 225.422121] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 225.422164] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.422190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.422219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.422247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.422275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.422301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.422326] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.422356] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.422385] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.422414] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.422462] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.422882] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.422911] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 225.422941] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 225.422991] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 225.424507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 225.424533] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 225.424564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 225.424586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 225.441511] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 225.441529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 225.458443] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 225.460485] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 225.460684] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 225.461834] [drm:intel_enable_pipe [i915]] enabling pipe B [ 225.461860] [drm:intel_mst_enable_dp [i915]] 1 [ 225.464252] [drm:drm_dp_update_payload_part2] payload 0 1 [ 225.465620] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.465642] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.465710] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.466260] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.466851] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 225.466880] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 225.466915] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 225.466992] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.467033] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.467080] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.467577] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.467610] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.478897] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.478936] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.478969] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.478974] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.478977] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.479010] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.479042] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 225.479073] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 225.479105] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.479136] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.479167] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.479173] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.479203] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.479208] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.479240] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.479271] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.479302] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.479333] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.479365] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.479394] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.479426] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.479513] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 225.479557] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 225.479617] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 225.479661] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 225.495595] [drm:intel_mst_disable_dp [i915]] 1 [ 225.495605] [drm:drm_dp_update_payload_part1] [ 225.497162] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.497214] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.497306] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.498081] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.500030] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.500090] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.500387] [drm:drm_dp_update_payload_part1] removing payload 0 [ 225.500451] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 225.500554] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 225.500668] [drm:intel_disable_pipe [i915]] disabling pipe B [ 225.512608] [drm:intel_mst_post_disable_dp [i915]] 1 [ 225.519461] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 225.519900] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 225.519937] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 225.519977] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 225.520028] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.520062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.520096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.520127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.520157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.520186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.520217] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.520250] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.520282] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.520313] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.520342] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.520370] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.520432] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.520521] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.520989] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.521597] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.521665] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.521720] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.521730] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.521735] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.521788] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.521841] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 225.521891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 225.521936] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.521979] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.522025] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.522035] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.522081] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.522090] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.522138] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.522180] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.522226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.522271] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.522323] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.522366] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.522409] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.522486] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 225.522537] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 225.522755] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 225.522810] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 225.522970] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 225.523042] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.523093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.523142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.523186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.523228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.523273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.523321] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.523371] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.523418] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.523494] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.523543] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.523596] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.523636] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 2, on? 0) for crtc 39 [ 225.523671] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 225.523736] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 225.525290] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 225.525319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 225.525344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 225.525370] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 225.542264] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 225.542283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 225.559169] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 225.561230] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 225.561427] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 225.562531] [drm:intel_enable_pipe [i915]] enabling pipe B [ 225.562556] [drm:intel_mst_enable_dp [i915]] 1 [ 225.564947] [drm:drm_dp_update_payload_part2] payload 0 1 [ 225.566316] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.566337] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.566367] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.566895] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.567548] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:55:DP-MST B] [ 225.567573] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD [ 225.567602] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 225.567675] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.567698] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.567735] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.568177] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.568193] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.579680] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.579705] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.579724] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.579728] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.579729] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.579748] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.579766] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset] [ 225.579783] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 225.579799] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.579815] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.579829] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.579833] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.579847] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.579850] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.579865] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.579880] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.579894] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.579909] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.579926] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.579945] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.579966] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.579986] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0 [ 225.580006] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0 [ 225.580036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 225.580059] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe B [ 225.596142] [drm:intel_mst_disable_dp [i915]] 1 [ 225.596147] [drm:drm_dp_update_payload_part1] [ 225.597656] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.597679] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.597742] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.598275] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.600056] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.600096] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.600428] [drm:drm_dp_update_payload_part1] removing payload 0 [ 225.600482] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B [ 225.600541] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 225.600619] [drm:intel_disable_pipe [i915]] disabling pipe B [ 225.612973] [drm:intel_mst_post_disable_dp [i915]] 1 [ 225.619155] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 225.619595] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 2, on? 1) for crtc 39 [ 225.619626] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 225.619661] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 225.619713] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.619741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.619768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.619793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.619817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.619841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.619866] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.619894] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.619920] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.619945] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.619969] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.619991] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.620034] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.620060] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.620087] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.620288] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.620332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 225.620393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.620418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.620499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.620536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.620571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.620609] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.620647] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.620685] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.620726] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.620764] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.620804] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.620840] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.620891] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B] [ 225.621815] [drm:drm_mode_addfb2] [FB:66] [ 225.621851] [drm:drm_mode_addfb2] [FB:70] [ 225.693080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A] [ 225.693163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B] [ 225.693211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C] [ 225.693257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C] [ 225.693274] [drm:drm_mode_setcrtc] [CONNECTOR:60:DP-2] [ 225.693329] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.693350] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.693359] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.693360] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.693380] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.693399] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 225.693454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 225.693482] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.693508] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.693531] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.693537] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.693559] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.693564] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.693586] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.693609] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.693630] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.693650] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.693676] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.693697] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.693718] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0 [ 225.693739] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 225.693759] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 225.693795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 225.693822] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 225.702645] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 225.702677] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.702694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.702710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.702725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.702739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.702753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.702769] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.702785] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.702801] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.702821] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.702839] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.702857] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.702877] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 225.702895] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 225.702925] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 225.704413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 225.704454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 225.704476] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 225.704501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 225.721438] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 225.721456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 225.738354] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 225.740434] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 225.740633] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 225.741865] [drm:intel_enable_pipe [i915]] enabling pipe C [ 225.742022] [drm:intel_mst_enable_dp [i915]] 1 [ 225.742372] [drm:drm_dp_update_payload_part2] payload 0 1 [ 225.743746] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.743769] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.743830] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.744411] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.745059] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 225.745084] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 225.745116] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 225.745741] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.745758] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.758770] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.758801] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 225.758845] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.792237] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.792285] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.792326] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.792333] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.792336] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.792376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.792416] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 225.792513] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 225.792573] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.792624] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.792672] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.792686] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.792730] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.792739] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.792785] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.792834] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.792879] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.792919] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.792964] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.793009] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.793055] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.793098] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 225.793138] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 225.793210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 225.793266] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 225.808859] [drm:intel_mst_disable_dp [i915]] 1 [ 225.808868] [drm:drm_dp_update_payload_part1] [ 225.875592] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.875657] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.875806] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.876639] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.879031] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.879130] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.879504] [drm:drm_dp_update_payload_part1] removing payload 0 [ 225.880038] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 225.880167] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 225.880392] [drm:intel_disable_pipe [i915]] disabling pipe C [ 225.892897] [drm:intel_mst_post_disable_dp [i915]] 1 [ 225.898523] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 225.898941] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 225.898971] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 225.899006] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 225.899050] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.899080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.899107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.899134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.899159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.899183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.899210] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.899237] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.899264] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.899289] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.899313] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.899336] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.899380] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.899414] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 225.899493] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.900342] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.900397] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.900484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.900698] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.900701] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.900740] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.900781] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 225.900820] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 225.900859] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.900892] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.900924] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.900932] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.900967] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.900974] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.901011] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.901046] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.901077] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.901108] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.901147] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.901182] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.901220] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.901253] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 225.901284] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 225.901341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 225.901386] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 225.902068] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 225.902129] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.902170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.902208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.902243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 225.902279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 225.902315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 225.902352] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 225.902390] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 225.902452] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 225.902495] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 225.902814] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 225.902850] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.902889] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 225.902928] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 225.902993] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 225.904561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 225.904602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 225.904638] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 225.904673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 225.921613] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 225.921631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 225.938530] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 225.940567] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 225.940765] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 225.941897] [drm:intel_enable_pipe [i915]] enabling pipe C [ 225.941922] [drm:intel_mst_enable_dp [i915]] 1 [ 225.944313] [drm:drm_dp_update_payload_part2] payload 0 1 [ 225.945688] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.945711] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.945757] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.946296] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.946864] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 225.946889] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 225.946918] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 225.946985] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 225.947008] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 225.947064] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 225.947652] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.947669] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.958967] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 225.959005] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 225.959034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 225.959039] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 225.959042] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 225.959068] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.959095] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 225.959121] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 225.959146] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 225.959169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.959192] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.959197] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.959219] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.959223] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 225.959246] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 225.959268] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 225.959290] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.959311] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.959337] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 225.959359] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.959382] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 225.959403] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 225.959465] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 225.959520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 225.959561] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 225.975575] [drm:intel_mst_disable_dp [i915]] 1 [ 225.975582] [drm:drm_dp_update_payload_part1] [ 225.977140] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 225.977196] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 225.977320] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 225.978003] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 225.980006] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 225.980068] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 225.980367] [drm:drm_dp_update_payload_part1] removing payload 0 [ 225.980419] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 225.980560] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 225.980662] [drm:intel_disable_pipe [i915]] disabling pipe C [ 225.992688] [drm:intel_mst_post_disable_dp [i915]] 1 [ 225.999328] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 225.999802] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 225.999834] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 225.999867] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 225.999913] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 225.999941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 225.999968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 225.999994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.000018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.000042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.000068] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.000095] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.000122] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.000147] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.000171] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.000194] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.000238] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.000265] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.000292] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.000936] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.000980] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.001014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.001021] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.001025] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.001058] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.001091] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.001123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.001145] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.001164] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.001183] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.001188] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.001206] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.001210] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.001230] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.001249] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.001267] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.001285] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.001307] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.001326] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.001352] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.001378] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.001404] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.001589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 226.001632] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.002188] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 226.002236] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.002261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.002283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.002304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.002324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.002344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.002364] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.002386] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.002409] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.002462] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.002493] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.002604] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.002628] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 226.002651] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 226.002689] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 226.004368] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 226.004391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 226.004413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 226.004546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 226.021412] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 226.021435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 226.038333] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 226.040401] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 226.040610] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 226.041729] [drm:intel_enable_pipe [i915]] enabling pipe C [ 226.041754] [drm:intel_mst_enable_dp [i915]] 1 [ 226.044155] [drm:drm_dp_update_payload_part2] payload 0 1 [ 226.045525] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.045547] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.045586] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.046119] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.046682] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 226.046704] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 226.046733] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 226.046799] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.046824] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.046878] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.047375] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.047393] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.058755] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.058793] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.058822] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.058827] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.058829] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.058856] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.058883] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.058909] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.058934] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.058957] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.058980] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.058985] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.059007] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.059011] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.059034] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.059057] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.059078] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.059100] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.059126] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.059147] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.059170] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.059192] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.059213] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.059248] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 226.059278] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.075357] [drm:intel_mst_disable_dp [i915]] 1 [ 226.075364] [drm:drm_dp_update_payload_part1] [ 226.076890] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.076922] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.076998] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.077601] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.079486] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.079531] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.079837] [drm:drm_dp_update_payload_part1] removing payload 0 [ 226.079875] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 226.079914] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 226.079992] [drm:intel_disable_pipe [i915]] disabling pipe C [ 226.092344] [drm:intel_mst_post_disable_dp [i915]] 1 [ 226.098145] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 226.098613] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 226.098652] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 226.098692] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 226.098746] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.098782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.098814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.098844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.098875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.098905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.098936] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.098969] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.099000] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.099031] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.099059] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.099087] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.099139] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.099174] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.099218] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.099569] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.099606] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.099636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.099643] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.099646] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.099676] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.099705] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.099733] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.099762] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.099790] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.099816] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.099822] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.099848] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.099854] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.099880] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.099906] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.099933] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.099958] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.099987] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.100013] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.100040] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.100066] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.100092] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.100135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 226.100169] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.100266] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 226.100310] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.100339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.100366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.100393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.100440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.100469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.100498] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.100529] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.100558] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.100588] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.100615] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.100642] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.100675] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 226.100705] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 226.100756] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 226.102259] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 226.102281] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 226.102300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 226.102320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 226.119245] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 226.119262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 226.136250] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 226.138319] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 226.138518] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 226.139698] [drm:intel_enable_pipe [i915]] enabling pipe C [ 226.139724] [drm:intel_mst_enable_dp [i915]] 1 [ 226.142131] [drm:drm_dp_update_payload_part2] payload 0 1 [ 226.143478] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.143501] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.143548] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.144090] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.144670] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 226.144697] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 226.144731] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 226.144807] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.144834] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.144878] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.145358] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.145378] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.156831] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.156873] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.156908] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.156914] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.156917] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.156952] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.156985] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.157019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.157052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.157085] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.157117] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.157124] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.157157] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.157162] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.157195] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.157228] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.157261] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.157293] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.157326] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.157357] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.157391] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.157500] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.157545] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.157615] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 226.157662] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.173396] [drm:intel_mst_disable_dp [i915]] 1 [ 226.173419] [drm:drm_dp_update_payload_part1] [ 226.174982] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.175032] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.175149] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.175796] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.177925] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.177992] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.178289] [drm:drm_dp_update_payload_part1] removing payload 0 [ 226.178348] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 226.178406] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 226.178586] [drm:intel_disable_pipe [i915]] disabling pipe C [ 226.190819] [drm:intel_mst_post_disable_dp [i915]] 1 [ 226.197148] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 226.197631] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 226.197686] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 226.197750] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 226.197847] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.197899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.197948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.198000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.198051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.198101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.198151] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.198209] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.198263] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.198317] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.198365] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.198408] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.198535] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.198592] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.198649] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.199208] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.199277] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.199334] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.199451] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.199456] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.199514] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.199575] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.199626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.199681] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.199731] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.199780] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.199792] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.199837] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.199846] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.199897] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.199947] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.199997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.200043] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.200092] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.200142] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.200194] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.200243] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.200289] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.200369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 226.200437] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.200555] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 226.200601] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.200629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.200696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.200737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.200763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.200813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.200844] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.200882] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.200910] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.200948] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.200976] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.201030] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.201060] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 226.201103] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 226.201161] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 226.202679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 226.202698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 226.202713] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 226.202730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 226.219644] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 226.219662] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 226.236561] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 226.238597] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 226.238792] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 226.239886] [drm:intel_enable_pipe [i915]] enabling pipe C [ 226.239914] [drm:intel_mst_enable_dp [i915]] 1 [ 226.242306] [drm:drm_dp_update_payload_part2] payload 0 1 [ 226.243659] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.243680] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.243719] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.244254] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.244867] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 226.244898] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 226.244934] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 226.245012] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.245042] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.245090] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.245574] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.245598] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.257013] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.257043] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.257068] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.257073] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.257075] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.257101] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.257125] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.257149] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.257173] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.257196] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.257220] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.257224] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.257247] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.257251] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.257275] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.257298] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.257322] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.257345] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.257369] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.257391] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.257464] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.257498] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.257530] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.257578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 226.257614] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.273575] [drm:intel_mst_disable_dp [i915]] 1 [ 226.273582] [drm:drm_dp_update_payload_part1] [ 226.275131] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.275186] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.275313] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.276161] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.278121] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.278182] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.278485] [drm:drm_dp_update_payload_part1] removing payload 0 [ 226.278559] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 226.278638] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 226.278747] [drm:intel_disable_pipe [i915]] disabling pipe C [ 226.291111] [drm:intel_mst_post_disable_dp [i915]] 1 [ 226.297034] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 226.297748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 226.297817] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 226.297874] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 226.297943] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.297988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.298036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.298083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.298128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.298169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.298212] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.298261] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.298309] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.298357] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.298397] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.298494] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.298575] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.298913] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.298969] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.299443] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.299485] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.299610] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.299617] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.299620] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.299649] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.299677] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.299744] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.299782] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.299808] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.299835] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.299841] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.299868] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.299873] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.299901] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.299925] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.299950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.299976] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.300006] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.300033] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.300060] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.300084] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.300111] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.300155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 226.300189] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.300334] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 226.300380] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.300407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.300453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.300486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.300516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.300544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.300572] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.300605] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.300635] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.300667] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.300694] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.300719] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.300753] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 226.300785] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 226.300971] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 226.302999] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 226.303017] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 226.303033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 226.303049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 226.322227] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 226.322247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 226.341376] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 226.343464] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 226.343941] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 226.347784] [drm:intel_enable_pipe [i915]] enabling pipe C [ 226.347813] [drm:intel_mst_enable_dp [i915]] 1 [ 226.352368] [drm:drm_dp_update_payload_part2] payload 0 1 [ 226.353738] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.353761] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.353815] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.356461] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.359129] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 226.359159] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 226.359196] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 226.359280] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.359313] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.359366] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.362198] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.362220] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.364833] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.364869] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.364896] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.364901] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.364903] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.364928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.364954] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.364979] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.365002] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.365030] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.365058] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.365064] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.365092] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.365096] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.365125] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.365154] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.365182] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.365211] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.365240] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.365266] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.365296] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.365324] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.365353] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.365396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 226.365465] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.381475] [drm:intel_mst_disable_dp [i915]] 1 [ 226.381481] [drm:drm_dp_update_payload_part1] [ 226.383005] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.383038] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.383119] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.385858] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.392937] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.392989] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.395419] [drm:drm_dp_update_payload_part1] removing payload 0 [ 226.395446] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 226.395472] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 226.395514] [drm:intel_disable_pipe [i915]] disabling pipe C [ 226.399511] [drm:intel_mst_post_disable_dp [i915]] 1 [ 226.412495] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 226.413601] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 226.413626] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 226.413652] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 226.413689] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.413713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.413736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.413760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.413783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.413806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.413829] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.413854] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.413878] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.413902] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.413925] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.413947] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.413986] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.414010] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.414035] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.414216] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.414243] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.414267] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.414271] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.414273] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.414297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.414320] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.414343] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.414366] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.414389] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.414450] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.414545] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.414577] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.414784] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.414815] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.414857] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.414892] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.414925] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.414959] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.414989] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.415024] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.415057] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.415089] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.415143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 226.415185] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.415301] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 226.415355] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.415388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.415447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.415481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.415514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.415544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.415575] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.415612] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.415646] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.415681] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.415711] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.415740] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.415778] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 226.415813] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 226.415869] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 226.417710] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 226.417745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 226.417780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 226.417817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 226.434764] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 226.434784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 226.451683] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 226.453746] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 226.453941] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 226.455035] [drm:intel_enable_pipe [i915]] enabling pipe C [ 226.455062] [drm:intel_mst_enable_dp [i915]] 1 [ 226.457454] [drm:drm_dp_update_payload_part2] payload 0 1 [ 226.458828] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.458851] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.458907] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.459455] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.460023] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 226.460049] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 226.460080] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 226.460151] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.460179] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.460239] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.460730] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.460748] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.472083] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.472116] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.472142] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.472147] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.472149] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.472173] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.472198] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.472220] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.472242] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.472263] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.472284] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.472289] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.472309] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.472313] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.472334] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.472353] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.472380] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.472409] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.472484] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.472517] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.472550] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.472581] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.472611] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.472664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 226.472704] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.488776] [drm:intel_mst_disable_dp [i915]] 1 [ 226.488785] [drm:drm_dp_update_payload_part1] [ 226.490343] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.490391] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.490514] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.491152] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.493110] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.493166] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.493584] [drm:drm_dp_update_payload_part1] removing payload 0 [ 226.493632] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 226.493684] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 226.493780] [drm:intel_disable_pipe [i915]] disabling pipe C [ 226.505630] [drm:intel_mst_post_disable_dp [i915]] 1 [ 226.512627] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 226.513071] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 226.513108] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 226.513147] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 226.513199] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.513234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.513266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.513297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.513327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.513356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.513387] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.513484] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.513535] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.513584] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.513902] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.513933] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.513988] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.514021] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.514055] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.514343] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.514384] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.514424] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.514469] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.514476] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.514526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.514577] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.514625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.514673] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.514935] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.514964] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.514971] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.515000] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.515006] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.515035] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.515064] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.515092] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.515120] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.515153] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.515181] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.515211] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.515239] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.515267] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.515314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 226.515360] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.515518] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 226.515580] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.515619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.515658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.515697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.515733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.515769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.515807] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.515847] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.515885] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.515923] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.515959] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.515994] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.516035] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 226.516074] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 226.516141] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 226.517756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 226.517811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 226.517854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 226.517897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 226.534845] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 226.534864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 226.551763] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 226.553822] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 226.554016] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 226.555134] [drm:intel_enable_pipe [i915]] enabling pipe C [ 226.555162] [drm:intel_mst_enable_dp [i915]] 1 [ 226.557593] [drm:drm_dp_update_payload_part2] payload 0 1 [ 226.558978] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.559003] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.559058] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.559602] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.560176] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 226.560203] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 226.560235] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 226.560310] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.560350] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.560396] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.560868] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.560887] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.572235] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.572278] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.572311] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.572317] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.572320] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.572351] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.572383] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.572412] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.572487] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.572737] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.572778] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.572787] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.572827] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.572835] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.572875] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.572916] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.572954] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.572990] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.573034] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.573073] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.573115] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.573154] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.573190] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.573254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 226.573304] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.588841] [drm:intel_mst_disable_dp [i915]] 1 [ 226.588848] [drm:drm_dp_update_payload_part1] [ 226.590381] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.590429] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.590526] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.591147] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.593087] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.593143] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.593450] [drm:drm_dp_update_payload_part1] removing payload 0 [ 226.593698] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 226.593748] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 226.593842] [drm:intel_disable_pipe [i915]] disabling pipe C [ 226.605564] [drm:intel_mst_post_disable_dp [i915]] 1 [ 226.612366] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 226.612894] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 226.612936] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 226.612979] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 226.613034] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.613071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.613105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.613138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.613170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.613201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.613241] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.613285] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.613328] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.613371] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.613411] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.613519] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.614153] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.614215] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.614274] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.614770] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.614818] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.614855] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.614862] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.614865] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.614901] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.614938] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.614971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.615005] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.615036] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.615067] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.615074] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.615104] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.615110] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.615141] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.615172] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.615202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.615230] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.615265] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.615295] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.615327] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.615356] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.615385] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.615488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 226.615762] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.615873] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 226.615944] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.615999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.616048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.616081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.616112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.616161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.616213] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.616262] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.616296] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.616329] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.616369] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.616424] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.616464] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 226.616488] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 226.616532] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 226.618378] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 226.618395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 226.618437] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 226.618463] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 226.635479] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 226.635496] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 226.652394] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 226.654467] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 226.654670] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 226.655863] [drm:intel_enable_pipe [i915]] enabling pipe C [ 226.655891] [drm:intel_mst_enable_dp [i915]] 1 [ 226.658303] [drm:drm_dp_update_payload_part2] payload 0 1 [ 226.659680] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.659703] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.659777] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.660329] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.660920] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 226.660949] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 226.660984] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 226.661061] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.661091] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.661138] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.661743] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.661766] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.672955] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.672983] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.673005] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.673009] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.673011] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.673031] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.673051] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.673071] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.673089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.673107] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.673124] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.673128] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.673145] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.673148] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.673166] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.673188] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.673211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.673234] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.673258] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.673280] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.673304] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.673327] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.673350] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.673383] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 226.673439] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.689537] [drm:intel_mst_disable_dp [i915]] 1 [ 226.689542] [drm:drm_dp_update_payload_part1] [ 226.691072] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.691115] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.691203] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.691829] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.693757] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.693806] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.694128] [drm:drm_dp_update_payload_part1] removing payload 0 [ 226.694172] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 226.694220] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 226.694288] [drm:intel_disable_pipe [i915]] disabling pipe C [ 226.707752] [drm:intel_mst_post_disable_dp [i915]] 1 [ 226.713112] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 226.713599] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 226.713661] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 226.713721] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 226.713801] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.713857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.713911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.713958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.714009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.714059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.714111] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.714164] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.714213] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.714267] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.714316] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.714365] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.714496] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.714551] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.714609] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.715058] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.715125] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.715179] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.715191] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.715196] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.715250] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.715304] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.715356] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.715403] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.715491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.715542] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.715556] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.715604] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.715614] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.715660] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.715709] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.715759] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.715810] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.715866] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.715911] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.715966] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.716016] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.716064] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.716138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 226.716204] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.716368] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 226.716464] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.716518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.716569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.716615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.716666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.716715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.716766] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.716818] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.716876] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.716930] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.716978] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.717023] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.717074] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 226.717128] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 226.717214] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 226.718875] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 226.718955] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 226.719029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 226.719103] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 226.736048] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 226.736066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 226.752965] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 226.755025] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 226.755221] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 226.756406] [drm:intel_enable_pipe [i915]] enabling pipe C [ 226.756441] [drm:intel_mst_enable_dp [i915]] 1 [ 226.758821] [drm:drm_dp_update_payload_part2] payload 0 1 [ 226.760191] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.760213] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.760266] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.760813] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.761383] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 226.761436] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 226.761470] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 226.761544] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.761591] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.761633] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.762097] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.762114] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.773530] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.773565] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.773592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.773597] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.773600] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.773625] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.773650] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.773673] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.773695] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.773717] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.773737] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.773742] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.773763] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.773767] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.773788] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.773810] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.773830] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.773850] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.773874] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.773895] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.773917] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.773937] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.773956] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.773990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 226.774018] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.790129] [drm:intel_mst_disable_dp [i915]] 1 [ 226.790136] [drm:drm_dp_update_payload_part1] [ 226.791677] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.791714] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.791805] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.792442] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.794398] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.794498] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.794753] [drm:drm_dp_update_payload_part1] removing payload 0 [ 226.794799] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 226.794846] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 226.794934] [drm:intel_disable_pipe [i915]] disabling pipe C [ 226.808578] [drm:intel_mst_post_disable_dp [i915]] 1 [ 226.813933] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 226.814382] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 226.814471] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 226.814538] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 226.814612] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.814665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.814715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.814764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.814811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.814856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.814904] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.814956] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.815005] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.815054] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.815099] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.815143] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.815214] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.815248] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.815284] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.815649] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.815693] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.815729] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.815736] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.815739] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.815773] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.815808] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.815841] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.815873] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.815904] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.815934] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.815942] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.815972] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.815978] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.816008] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.816038] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.816067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.816096] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.816131] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.816161] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.816193] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.816223] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.816252] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.816302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 226.816343] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.816518] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 226.816593] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.816645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.816686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.816725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.816765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.816803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.816842] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.816884] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.816924] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.816965] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.817003] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.817040] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.817083] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 226.817124] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 226.817194] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 226.818773] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 226.818802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 226.818829] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 226.818856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 226.835785] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 226.835802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 226.852694] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 226.854725] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 226.854919] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 226.856000] [drm:intel_enable_pipe [i915]] enabling pipe C [ 226.856025] [drm:intel_mst_enable_dp [i915]] 1 [ 226.858406] [drm:drm_dp_update_payload_part2] payload 0 1 [ 226.859781] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.859804] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.859864] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.860404] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.860992] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 226.861017] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 226.861048] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 226.861117] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.861144] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.861204] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.861687] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.861702] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.873126] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.873164] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.873193] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.873198] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.873200] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.873228] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.873255] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.873281] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.873306] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.873330] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.873353] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.873358] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.873381] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.873385] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.873453] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.873497] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.873538] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.873577] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.873620] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.873657] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.873700] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.873741] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.873779] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.873840] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 226.873887] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.889733] [drm:intel_mst_disable_dp [i915]] 1 [ 226.889739] [drm:drm_dp_update_payload_part1] [ 226.891260] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.891295] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.891389] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.892016] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.893975] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.894038] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.894332] [drm:drm_dp_update_payload_part1] removing payload 0 [ 226.894389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 226.894512] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 226.894624] [drm:intel_disable_pipe [i915]] disabling pipe C [ 226.906549] [drm:intel_mst_post_disable_dp [i915]] 1 [ 226.913861] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 226.914288] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 226.914320] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 226.914354] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 226.914400] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.914476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.914521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.914564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.914593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.914619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.914648] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.914678] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.914707] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.914736] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.914762] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.914788] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.914835] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.914863] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.914894] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.915141] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.915175] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.915204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.915209] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.915212] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.915240] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.915268] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.915294] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.915319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.915344] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.915368] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.915374] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.915397] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.915449] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.915475] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.915501] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.915526] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.915551] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.915581] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.915605] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.915632] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.915657] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.915683] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.915727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 226.915759] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.915828] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 226.915859] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 226.915879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 226.915897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 226.915915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 226.915933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 226.915950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 226.915967] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 226.915986] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 226.916004] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 226.916022] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 226.916039] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 226.916055] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.916075] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 226.916094] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 226.916125] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 226.917624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 226.917644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 226.917663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 226.917681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 226.934596] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 226.934612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 226.951505] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 226.953537] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 226.953727] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 226.954803] [drm:intel_enable_pipe [i915]] enabling pipe C [ 226.954828] [drm:intel_mst_enable_dp [i915]] 1 [ 226.957210] [drm:drm_dp_update_payload_part2] payload 0 1 [ 226.958584] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.958603] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.958658] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.959193] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.959756] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 226.959781] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 226.959811] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 226.959879] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 226.959906] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 226.959966] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 226.960454] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.960477] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.971920] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 226.971956] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 226.971986] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 226.971992] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 226.971994] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 226.972025] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 226.972054] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 226.972084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 226.972113] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 226.972142] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 226.972170] [drm:intel_dump_pipe_config [i915]] requested mode: [ 226.972175] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.972204] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 226.972209] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 226.972239] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 226.972268] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 226.972297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 226.972326] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 226.972355] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 226.972383] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 226.972459] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 226.972499] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 226.972537] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 226.972596] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 226.972638] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 226.988577] [drm:intel_mst_disable_dp [i915]] 1 [ 226.988586] [drm:drm_dp_update_payload_part1] [ 226.990123] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 226.990169] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 226.990252] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 226.990874] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 226.992778] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 226.992828] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 226.993120] [drm:drm_dp_update_payload_part1] removing payload 0 [ 226.993164] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 226.993206] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 226.993288] [drm:intel_disable_pipe [i915]] disabling pipe C [ 227.006674] [drm:intel_mst_post_disable_dp [i915]] 1 [ 227.011460] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 227.011891] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 227.011925] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 227.011960] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 227.012007] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.012039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.012068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.012095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.012121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.012147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.012175] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.012205] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.012240] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.012277] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.012311] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.012344] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.012401] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.012496] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.012547] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.012912] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.012970] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.013018] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.013028] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.013032] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.013078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.013125] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.013155] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.013184] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.013210] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.013236] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.013241] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.013267] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.013273] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.013298] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.013324] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.013349] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.013374] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.013405] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.013562] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.013604] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.013646] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.013689] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.013757] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 227.013810] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.013953] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 227.014015] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.014057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.014097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.014135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.014173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.014213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.014253] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.014295] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.014335] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.014376] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.014416] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.014477] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.014521] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 227.014561] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 227.014633] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 227.016490] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 227.016523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 227.016551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 227.016579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 227.035740] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 227.035760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 227.054889] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 227.056950] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 227.057423] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 227.061247] [drm:intel_enable_pipe [i915]] enabling pipe C [ 227.061276] [drm:intel_mst_enable_dp [i915]] 1 [ 227.065865] [drm:drm_dp_update_payload_part2] payload 0 1 [ 227.067258] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.067288] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.067354] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.070004] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.072699] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 227.072732] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 227.072772] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 227.072858] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.072889] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.072941] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.075705] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.075730] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.078365] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.078407] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.078490] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.078503] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.078507] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.078543] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.078581] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.078618] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.078652] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.078684] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.078717] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.078725] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.078755] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.078761] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.078794] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.078825] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.078856] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.078887] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.078921] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.078952] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.078986] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.079017] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.079047] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.079099] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 227.079138] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.094978] [drm:intel_mst_disable_dp [i915]] 1 [ 227.094984] [drm:drm_dp_update_payload_part1] [ 227.096513] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.096545] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.096628] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.099481] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.106546] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.106579] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.109017] [drm:drm_dp_update_payload_part1] removing payload 0 [ 227.109044] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 227.109071] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 227.109122] [drm:intel_disable_pipe [i915]] disabling pipe C [ 227.112473] [drm:intel_mst_post_disable_dp [i915]] 1 [ 227.125511] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 227.126497] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 227.126533] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 227.126572] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 227.126616] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.126638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.126659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.126678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.126698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.126716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.126736] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.126757] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.126777] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.126797] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.126815] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.126832] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.126866] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.126886] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.126907] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.127096] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.127121] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.127142] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.127146] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.127148] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.127168] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.127193] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.127219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.127244] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.127268] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.127292] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.127297] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.127321] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.127325] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.127350] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.127374] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.127405] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.127486] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.127524] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.127559] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.127595] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.127630] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.127661] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.127713] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 227.127753] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.127852] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 227.127903] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.127937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.127971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.128003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.128035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.128069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.128101] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.128135] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.128169] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.128204] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.128236] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.128268] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.128303] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 227.128337] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 227.128396] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 227.130482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 227.130502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 227.130519] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 227.130536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 227.147383] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 227.147411] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 227.164246] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 227.166305] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 227.166501] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 227.167648] [drm:intel_enable_pipe [i915]] enabling pipe C [ 227.167674] [drm:intel_mst_enable_dp [i915]] 1 [ 227.169775] [drm:drm_dp_update_payload_part2] payload 0 1 [ 227.171145] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.171166] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.171204] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.171768] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.172329] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 227.172352] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 227.172380] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 227.172488] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.172525] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.172567] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.173048] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.173069] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.184755] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.184782] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.184802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.184806] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.184808] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.184827] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.184846] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.184864] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.184881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.184897] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.184913] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.184916] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.184932] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.184935] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.184951] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.184966] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.184982] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.184996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.185014] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.185029] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.185045] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.185061] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.185075] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.185101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 227.185122] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.201454] [drm:intel_mst_disable_dp [i915]] 1 [ 227.201462] [drm:drm_dp_update_payload_part1] [ 227.203023] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.203069] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.203175] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.203844] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.205776] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.205825] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.206124] [drm:drm_dp_update_payload_part1] removing payload 0 [ 227.206167] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 227.206210] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 227.206292] [drm:intel_disable_pipe [i915]] disabling pipe C [ 227.218634] [drm:intel_mst_post_disable_dp [i915]] 1 [ 227.224978] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 227.225506] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 227.225568] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 227.225632] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 227.225712] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.225769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.225805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.225839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.225873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.225904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.225938] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.225973] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.226006] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.226039] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.226070] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.226099] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.226156] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.226189] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.226226] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.226652] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.226720] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.226774] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.226785] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.226791] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.226843] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.226898] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.226950] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.227002] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.227051] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.227099] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.227111] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.227158] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.227168] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.227217] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.227266] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.227315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.227362] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.227416] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.227487] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.227523] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.227556] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.227589] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.227646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 227.227689] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.227813] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 227.227869] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.227907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.227944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.227980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.228015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.228050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.228087] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.228125] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.228163] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.228200] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.228234] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.228269] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.228310] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 227.228347] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 227.228414] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 227.229909] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 227.229925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 227.229940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 227.229955] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 227.246823] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 227.246840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 227.263741] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 227.265809] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 227.266007] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 227.267116] [drm:intel_enable_pipe [i915]] enabling pipe C [ 227.267144] [drm:intel_mst_enable_dp [i915]] 1 [ 227.269536] [drm:drm_dp_update_payload_part2] payload 0 1 [ 227.270904] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.270925] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.270963] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.271506] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.272078] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 227.272104] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 227.272135] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 227.272206] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.272234] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.272302] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.272794] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.272811] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.284194] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.284235] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.284267] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.284273] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.284275] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.284305] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.284335] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.284363] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.284395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.284460] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.284502] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.284514] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.284553] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.284564] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.284603] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.284641] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.284677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.284715] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.284758] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.284796] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.284833] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.284866] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.284903] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.284963] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 227.285009] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.300800] [drm:intel_mst_disable_dp [i915]] 1 [ 227.300807] [drm:drm_dp_update_payload_part1] [ 227.302361] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.302422] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.302540] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.303525] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.305477] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.305533] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.305839] [drm:drm_dp_update_payload_part1] removing payload 0 [ 227.305884] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 227.305931] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 227.306023] [drm:intel_disable_pipe [i915]] disabling pipe C [ 227.318398] [drm:intel_mst_post_disable_dp [i915]] 1 [ 227.324743] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 227.325173] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 227.325206] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 227.325240] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 227.325287] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.325318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.325347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.325374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.325400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.325485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.325664] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.325712] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.325758] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.325803] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.325843] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.325883] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.325955] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.325997] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.326042] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.326453] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.326485] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.326510] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.326515] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.326518] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.326543] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.326568] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.326592] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.326622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.326652] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.326682] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.326690] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.326719] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.326726] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.326756] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.326785] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.326816] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.326846] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.326876] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.326906] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.326936] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.326966] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.326997] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.327047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 227.327093] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.327218] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 227.327276] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.327316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.327353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.327378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.327437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.327471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.327504] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.327543] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.327578] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.327614] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.327645] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.327675] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.327713] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 227.327748] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 227.327806] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 227.329366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 227.329392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 227.329458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 227.329495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 227.346426] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 227.346442] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 227.363338] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 227.365411] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 227.365610] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 227.366812] [drm:intel_enable_pipe [i915]] enabling pipe C [ 227.366839] [drm:intel_mst_enable_dp [i915]] 1 [ 227.369231] [drm:drm_dp_update_payload_part2] payload 0 1 [ 227.370600] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.370621] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.370661] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.371196] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.371764] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 227.371789] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 227.371820] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 227.371890] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.371918] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.371977] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.372477] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.372495] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.383869] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.383904] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.383931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.383936] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.383938] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.383964] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.383991] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.384019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.384047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.384074] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.384101] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.384105] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.384132] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.384136] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.384164] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.384191] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.384218] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.384246] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.384273] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.384299] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.384327] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.384355] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.384382] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.384485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 227.384528] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.400493] [drm:intel_mst_disable_dp [i915]] 1 [ 227.400500] [drm:drm_dp_update_payload_part1] [ 227.402054] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.402106] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.402229] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.402914] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.404593] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.404650] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.405193] [drm:drm_dp_update_payload_part1] removing payload 0 [ 227.405243] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 227.405293] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 227.405368] [drm:intel_disable_pipe [i915]] disabling pipe C [ 227.417780] [drm:intel_mst_post_disable_dp [i915]] 1 [ 227.424506] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 227.424934] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 227.424966] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 227.425000] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 227.425047] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.425078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.425106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.425133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.425160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.425186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.425213] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.425243] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.425271] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.425299] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.425324] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.425349] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.425404] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.425494] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.425541] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.425894] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.425931] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.425959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.425965] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.425967] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.425995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.426024] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.426051] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.426076] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.426101] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.426124] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.426130] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.426154] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.426158] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.426191] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.426223] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.426256] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.426288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.426321] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.426352] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.426388] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.426463] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.426504] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.426565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 227.426614] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.426751] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 227.426814] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.426857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.426898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.426933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.426959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.426991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.427025] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.427060] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.427096] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.427131] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.427163] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.427196] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.427231] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 227.427265] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 227.427316] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 227.428821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 227.428841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 227.428858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 227.428876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 227.445765] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 227.445782] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 227.462655] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 227.464718] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 227.464917] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 227.466039] [drm:intel_enable_pipe [i915]] enabling pipe C [ 227.466067] [drm:intel_mst_enable_dp [i915]] 1 [ 227.468458] [drm:drm_dp_update_payload_part2] payload 0 1 [ 227.469840] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.469864] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.469915] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.470456] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.471023] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 227.471048] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 227.471079] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 227.471145] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.471170] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.471217] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.471708] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.471725] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.483129] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.483165] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.483193] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.483199] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.483201] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.483227] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.483253] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.483277] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.483301] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.483323] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.483345] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.483350] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.483371] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.483376] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.483442] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.483477] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.483512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.483544] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.483582] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.483614] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.483648] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.483681] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.483715] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.483771] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 227.483811] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.499756] [drm:intel_mst_disable_dp [i915]] 1 [ 227.499765] [drm:drm_dp_update_payload_part1] [ 227.501303] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.501348] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.501520] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.502196] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.504416] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.504519] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.504787] [drm:drm_dp_update_payload_part1] removing payload 0 [ 227.504841] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 227.504895] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 227.504978] [drm:intel_disable_pipe [i915]] disabling pipe C [ 227.517363] [drm:intel_mst_post_disable_dp [i915]] 1 [ 227.523283] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 227.523819] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 227.523860] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 227.523903] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 227.523960] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.523999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.524038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.524077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.524116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.524155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.524193] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.524234] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.524274] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.524315] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.524352] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.524395] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.524667] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.524719] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.524779] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.525333] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.525386] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.525462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.525471] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.525475] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.525516] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.525554] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.525596] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.525636] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.525673] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.525707] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.525715] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.525752] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.525759] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.525797] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.525834] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.525868] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.525900] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.525942] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.525978] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.526017] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.526051] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.526084] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.526143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 227.526190] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.526317] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 227.526372] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.526433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.526477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.526517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.526554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.526592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.526627] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.526669] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.526710] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.526751] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.526785] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.526818] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.526860] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 227.526900] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 227.526966] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 227.528478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 227.528496] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 227.528511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 227.528527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 227.545443] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 227.545460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 227.562358] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 227.564420] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 227.564616] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 227.565820] [drm:intel_enable_pipe [i915]] enabling pipe C [ 227.565847] [drm:intel_mst_enable_dp [i915]] 1 [ 227.568250] [drm:drm_dp_update_payload_part2] payload 0 1 [ 227.569627] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.569649] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.569709] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.570251] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.570834] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 227.570861] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 227.570893] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 227.570965] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.570994] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.571054] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.571566] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.571596] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.582939] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.582978] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.583007] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.583013] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.583015] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.583042] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.583070] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.583096] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.583121] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.583145] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.583168] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.583173] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.583196] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.583200] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.583223] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.583246] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.583268] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.583290] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.583317] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.583339] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.583362] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.583385] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.583465] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.583528] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 227.583575] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.599507] [drm:intel_mst_disable_dp [i915]] 1 [ 227.599514] [drm:drm_dp_update_payload_part1] [ 227.601047] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.601088] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.601161] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.601807] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.603668] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.603712] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.604038] [drm:drm_dp_update_payload_part1] removing payload 0 [ 227.604083] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 227.604129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 227.604221] [drm:intel_disable_pipe [i915]] disabling pipe C [ 227.616554] [drm:intel_mst_post_disable_dp [i915]] 1 [ 227.622913] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 227.623343] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 227.623378] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 227.623475] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 227.623551] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.623600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.623645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.623692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.623737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.623782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.623828] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.623880] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.623928] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.623976] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.624017] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.624055] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.624133] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.624181] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.624229] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.624670] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.624730] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.624775] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.624785] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.624790] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.624837] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.624886] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.624932] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.624974] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.625020] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.625063] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.625073] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.625116] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.625125] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.625165] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.625209] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.625252] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.625295] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.625340] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.625379] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.625472] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.625520] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.625567] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.625640] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 227.625696] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.625848] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 227.625916] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.625959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.626005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.626050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.626094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.626135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.626175] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.626224] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.626271] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.626317] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.626358] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.626397] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.626472] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 227.626521] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 227.626599] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 227.628131] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 227.628158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 227.628189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 227.628211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 227.645115] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 227.645133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 227.662045] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 227.664113] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 227.664311] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 227.665441] [drm:intel_enable_pipe [i915]] enabling pipe C [ 227.665468] [drm:intel_mst_enable_dp [i915]] 1 [ 227.667880] [drm:drm_dp_update_payload_part2] payload 0 1 [ 227.669258] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.669281] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.669335] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.669887] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.670511] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 227.670539] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 227.670574] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 227.670649] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.670676] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.670722] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.671166] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.671185] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.682602] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.682641] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.682671] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.682677] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.682679] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.682707] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.682736] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.682763] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.682793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.682825] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.682856] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.682861] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.682892] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.682897] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.682928] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.682959] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.682990] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.683021] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.683053] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.683082] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.683114] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.683146] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.683177] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.683222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 227.683258] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.699210] [drm:intel_mst_disable_dp [i915]] 1 [ 227.699217] [drm:drm_dp_update_payload_part1] [ 227.700766] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.700820] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.700901] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.701577] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.703624] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.703691] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.703989] [drm:drm_dp_update_payload_part1] removing payload 0 [ 227.704042] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 227.704096] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 227.704178] [drm:intel_disable_pipe [i915]] disabling pipe C [ 227.717781] [drm:intel_mst_post_disable_dp [i915]] 1 [ 227.722698] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 227.723162] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 227.723204] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 227.723250] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 227.723307] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.723347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.723384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.723482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.723546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.723600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.723657] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.723716] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.723769] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.723826] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.723874] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.723922] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.724010] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.724062] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.724119] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.724570] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.724638] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.724679] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.724686] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.724690] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.724725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.724760] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.724794] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.724827] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.724859] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.724890] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.724897] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.724927] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.724933] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.724965] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.724996] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.725026] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.725055] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.725090] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.725120] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.725152] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.725181] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.725210] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.725260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 227.725302] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.725426] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 227.725469] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.725497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.725523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.725548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.725574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.725600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.725626] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.725654] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.725682] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.725710] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.725734] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.725757] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.725785] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 227.725810] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 227.725854] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 227.727339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 227.727358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 227.727375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 227.727419] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 227.744343] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 227.744360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 227.761257] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 227.763326] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 227.763525] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 227.764763] [drm:intel_enable_pipe [i915]] enabling pipe C [ 227.764791] [drm:intel_mst_enable_dp [i915]] 1 [ 227.767198] [drm:drm_dp_update_payload_part2] payload 0 1 [ 227.768574] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.768599] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.768645] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.769187] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.769764] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 227.769791] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 227.769824] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 227.769897] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.769924] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.769984] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.770499] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.770531] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.781831] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.781868] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.781898] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.781904] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.781906] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.781937] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.781967] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.781997] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.782027] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.782056] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.782085] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.782090] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.782119] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.782124] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.782153] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.782182] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.782211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.782240] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.782269] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.782296] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.782328] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.782357] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.782387] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.782481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 227.782531] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.798404] [drm:intel_mst_disable_dp [i915]] 1 [ 227.798435] [drm:drm_dp_update_payload_part1] [ 227.799970] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.800011] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.800119] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.800743] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.802635] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.802687] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.802988] [drm:drm_dp_update_payload_part1] removing payload 0 [ 227.803033] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 227.803078] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 227.803147] [drm:intel_disable_pipe [i915]] disabling pipe C [ 227.816687] [drm:intel_mst_post_disable_dp [i915]] 1 [ 227.822176] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 227.822706] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 227.822741] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 227.822779] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 227.822830] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.822866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.822901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.822936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.822971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.823005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.823039] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.823076] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.823112] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.823147] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.823181] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.823215] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.823270] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.823305] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.823344] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.823754] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.823795] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.823827] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.823833] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.823836] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.823867] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.823898] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.823927] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.823955] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.823982] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.824008] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.824015] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.824040] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.824045] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.824072] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.824097] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.824121] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.824146] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.824175] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.824199] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.824225] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.824249] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.824273] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.824314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 227.824349] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.824476] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 227.824520] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.824546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.824571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.824594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.824618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.824643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.824667] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.824693] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.824718] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.824742] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.824765] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.824788] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.824815] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 227.824841] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 227.824885] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 227.826381] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 227.826427] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 227.826446] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 227.826464] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 227.843353] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 227.843370] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 227.860265] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 227.861445] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 227.861643] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 227.862830] [drm:intel_enable_pipe [i915]] enabling pipe C [ 227.862855] [drm:intel_mst_enable_dp [i915]] 1 [ 227.864762] [drm:drm_dp_update_payload_part2] payload 0 1 [ 227.866141] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.866163] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.866215] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.866785] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.867349] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 227.867373] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 227.867429] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 227.867502] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.867529] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.867574] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.868155] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.868173] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.879933] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.879961] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.879983] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.879987] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.879989] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.880009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.880030] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.880049] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.880068] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.880086] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.880103] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.880107] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.880123] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.880127] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.880144] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.880161] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.880178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.880195] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.880214] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.880231] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.880249] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.880265] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.880282] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.880310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 227.880333] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.896553] [drm:intel_mst_disable_dp [i915]] 1 [ 227.896562] [drm:drm_dp_update_payload_part1] [ 227.898113] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.898158] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.898254] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.898891] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.900864] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.900912] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.901214] [drm:drm_dp_update_payload_part1] removing payload 0 [ 227.901261] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 227.901305] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 227.901369] [drm:intel_disable_pipe [i915]] disabling pipe C [ 227.913658] [drm:intel_mst_post_disable_dp [i915]] 1 [ 227.920284] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 227.920756] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 227.920794] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 227.920834] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 227.920885] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.920920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.920953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.920983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.921013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.921042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.921073] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.921105] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.921136] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.921167] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.921195] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.921222] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.921272] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.921304] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.921337] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.921823] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.921886] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.921938] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.921949] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.921953] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.922004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.922057] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.922107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.922210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.922240] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.922277] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.922296] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.922335] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.922341] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.922380] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.922478] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.922526] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.922570] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.922619] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.922664] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.922710] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.922753] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.922796] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.922867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 227.922920] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.923022] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 227.923065] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 227.923092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 227.923118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 227.923143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 227.923168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 227.923192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 227.923217] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 227.923244] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 227.923270] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 227.923295] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 227.923319] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 227.923342] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.923370] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 227.923413] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 227.923461] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 227.924946] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 227.924962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 227.924977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 227.924992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 227.941881] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 227.941898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 227.958778] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 227.960449] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 227.960645] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 227.961809] [drm:intel_enable_pipe [i915]] enabling pipe C [ 227.961835] [drm:intel_mst_enable_dp [i915]] 1 [ 227.963761] [drm:drm_dp_update_payload_part2] payload 0 1 [ 227.965130] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.965151] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.965195] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.965763] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.966334] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 227.966361] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 227.966417] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 227.966497] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 227.966539] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 227.966583] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 227.967067] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.967095] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.978802] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 227.978829] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 227.978849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 227.978853] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 227.978855] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 227.978873] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 227.978892] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 227.978910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 227.978927] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 227.978944] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 227.978959] [drm:intel_dump_pipe_config [i915]] requested mode: [ 227.978963] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.978978] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 227.978982] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 227.978998] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 227.979013] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 227.979029] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 227.979044] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 227.979062] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 227.979078] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 227.979094] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 227.979110] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 227.979125] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 227.979151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 227.979172] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 227.995470] [drm:intel_mst_disable_dp [i915]] 1 [ 227.995478] [drm:drm_dp_update_payload_part1] [ 227.997015] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 227.997057] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 227.997135] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 227.997763] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 227.999624] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 227.999673] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 227.999973] [drm:drm_dp_update_payload_part1] removing payload 0 [ 228.000012] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 228.000053] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 228.000116] [drm:intel_disable_pipe [i915]] disabling pipe C [ 228.013711] [drm:intel_mst_post_disable_dp [i915]] 1 [ 228.019139] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 228.019721] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 228.019755] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 228.019791] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 228.019839] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.019870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.019900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.019926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.019952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.019978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.020006] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.020035] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.020062] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.020090] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.020115] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.020140] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.020186] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.020214] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.020244] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.020612] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.020668] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.020714] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.020724] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.020728] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.020776] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.020822] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.020866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.020910] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.020967] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.021009] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.021018] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.021060] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.021068] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.021110] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.021151] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.021205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.021245] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.021291] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.021333] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.021376] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.021443] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.021481] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.021552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 228.021600] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.021728] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 228.021787] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.021839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.021877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.021915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.021953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.021990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.022029] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.022070] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.022110] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.022161] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.022198] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.022235] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.022279] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 228.022318] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 228.022396] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 228.024045] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 228.024090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 228.024130] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 228.024168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 228.041269] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 228.041287] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 228.058163] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 228.060232] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 228.060430] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 228.061590] [drm:intel_enable_pipe [i915]] enabling pipe C [ 228.061617] [drm:intel_mst_enable_dp [i915]] 1 [ 228.064024] [drm:drm_dp_update_payload_part2] payload 0 1 [ 228.065400] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.065423] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.065466] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.066010] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.066586] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 228.066614] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 228.066647] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 228.066718] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.066747] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.066796] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.067268] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.067287] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.078658] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.078685] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.078706] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.078710] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.078711] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.078731] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.078750] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.078768] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.078786] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.078807] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.078828] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.078832] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.078853] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.078856] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.078878] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.078900] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.078921] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.078942] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.078963] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.078983] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.079006] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.079027] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.079048] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.079078] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 228.079103] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.095269] [drm:intel_mst_disable_dp [i915]] 1 [ 228.095274] [drm:drm_dp_update_payload_part1] [ 228.096807] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.096847] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.096956] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.097568] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.099403] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.099467] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.099752] [drm:drm_dp_update_payload_part1] removing payload 0 [ 228.099794] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 228.099835] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 228.099895] [drm:intel_disable_pipe [i915]] disabling pipe C [ 228.112243] [drm:intel_mst_post_disable_dp [i915]] 1 [ 228.118678] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 228.119092] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 228.119115] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 228.119140] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 228.119175] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.119197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.119216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.119235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.119254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.119271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.119290] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.119311] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.119330] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.119349] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.119366] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.119384] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.119535] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.119556] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.119579] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.119761] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.119790] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.119821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.119828] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.119832] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.119862] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.119893] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.119923] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.119948] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.119967] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.119984] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.119989] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.120006] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.120009] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.120027] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.120044] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.120063] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.120090] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.120122] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.120150] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.120180] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.120208] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.120235] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.120269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 228.120293] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.120363] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 228.120435] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.120467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.120496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.120526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.120555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.120583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.120610] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.120639] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.120667] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.120697] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.120723] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.120751] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.120784] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 228.120814] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 228.120866] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 228.122560] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 228.122582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 228.122602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 228.122622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 228.139544] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 228.139561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 228.156459] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 228.158528] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 228.158726] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 228.159860] [drm:intel_enable_pipe [i915]] enabling pipe C [ 228.159886] [drm:intel_mst_enable_dp [i915]] 1 [ 228.162308] [drm:drm_dp_update_payload_part2] payload 0 1 [ 228.163685] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.163709] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.163754] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.164304] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.164880] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 228.164906] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 228.164938] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 228.165031] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.165069] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.165111] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.165599] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.165649] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.177027] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.177066] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.177096] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.177102] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.177104] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.177132] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.177160] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.177187] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.177212] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.177236] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.177259] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.177265] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.177288] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.177293] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.177316] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.177340] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.177363] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.177386] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.177454] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.177496] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.177537] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.177575] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.177613] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.177672] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 228.177719] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.193638] [drm:intel_mst_disable_dp [i915]] 1 [ 228.193644] [drm:drm_dp_update_payload_part1] [ 228.195184] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.195218] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.195295] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.195958] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.197909] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.197969] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.198270] [drm:drm_dp_update_payload_part1] removing payload 0 [ 228.198318] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 228.198370] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 228.198749] [drm:intel_disable_pipe [i915]] disabling pipe C [ 228.210560] [drm:intel_mst_post_disable_dp [i915]] 1 [ 228.217410] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 228.217855] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 228.217892] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 228.217932] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 228.217983] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.218018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.218051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.218082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.218112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.218142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.218174] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.218206] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.218238] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.218269] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.218297] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.218325] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.218377] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.218466] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.218936] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.219163] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.219196] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.219223] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.219228] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.219231] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.219256] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.219282] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.219306] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.219330] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.219354] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.219375] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.219410] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.219448] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.219828] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.219855] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.219880] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.219904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.219927] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.219952] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.219975] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.219998] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.220021] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.220043] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.220080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 228.220110] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.220190] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 228.220228] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.220253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.220276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.220298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.220320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.220341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.220363] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.220394] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.220438] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.220896] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.220912] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.220928] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.220947] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 228.220964] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 228.220992] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 228.222458] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 228.222474] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 228.222489] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 228.222505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 228.239418] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 228.239435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 228.256329] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 228.258399] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 228.258597] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 228.259802] [drm:intel_enable_pipe [i915]] enabling pipe C [ 228.259827] [drm:intel_mst_enable_dp [i915]] 1 [ 228.262222] [drm:drm_dp_update_payload_part2] payload 0 1 [ 228.263590] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.263612] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.263675] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.264220] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.264894] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 228.264925] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 228.264961] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 228.265040] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.265070] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.265118] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.265601] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.265634] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.276907] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.276951] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.276984] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.276990] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.276992] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.277024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.277055] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.277085] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.277114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.277141] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.277167] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.277174] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.277203] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.277209] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.277243] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.277278] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.277313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.277347] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.277382] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.277463] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.277645] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.277689] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.277731] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.277796] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 228.277847] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.293521] [drm:intel_mst_disable_dp [i915]] 1 [ 228.293529] [drm:drm_dp_update_payload_part1] [ 228.295079] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.295122] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.295223] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.295968] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.298196] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.298256] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.298573] [drm:drm_dp_update_payload_part1] removing payload 0 [ 228.298644] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 228.298712] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 228.298815] [drm:intel_disable_pipe [i915]] disabling pipe C [ 228.310679] [drm:intel_mst_post_disable_dp [i915]] 1 [ 228.317250] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 228.317713] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 228.317751] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 228.317790] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 228.317841] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.317876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.317911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.317946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.317980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.318015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.318049] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.318086] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.318123] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.318158] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.318192] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.318226] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.318282] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.318318] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.318356] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.319141] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.319200] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.319245] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.319254] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.319259] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.319307] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.319354] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.319399] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.319481] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.319744] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.319782] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.319791] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.319833] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.319842] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.319885] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.319927] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.319965] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.320006] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.320052] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.320094] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.320135] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.320171] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.320212] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.320278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 228.320330] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.320870] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 228.320938] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.320985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.321029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.321069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.321112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.321153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.321197] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.321241] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.321281] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.321325] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.321365] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.321433] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.321480] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 228.321854] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 228.321929] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 228.323527] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 228.323570] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 228.323614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 228.323658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 228.340606] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 228.340624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 228.357556] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 228.359617] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 228.359814] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 228.360921] [drm:intel_enable_pipe [i915]] enabling pipe C [ 228.360947] [drm:intel_mst_enable_dp [i915]] 1 [ 228.363358] [drm:drm_dp_update_payload_part2] payload 0 1 [ 228.364768] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.364791] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.364854] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.365397] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.365994] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 228.366020] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 228.366053] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 228.366125] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.366154] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.366207] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.366695] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.366735] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.377957] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.377984] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.378004] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.378008] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.378010] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.378028] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.378048] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.378066] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.378083] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.378099] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.378115] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.378119] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.378134] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.378138] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.378153] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.378169] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.378184] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.378199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.378217] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.378233] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.378249] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.378265] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.378280] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.378305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 228.378327] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.394610] [drm:intel_mst_disable_dp [i915]] 1 [ 228.394618] [drm:drm_dp_update_payload_part1] [ 228.396161] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.396209] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.396325] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.396997] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.399010] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.399064] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.399362] [drm:drm_dp_update_payload_part1] removing payload 0 [ 228.399465] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 228.399537] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 228.399640] [drm:intel_disable_pipe [i915]] disabling pipe C [ 228.411984] [drm:intel_mst_post_disable_dp [i915]] 1 [ 228.418321] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 228.418817] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 228.418863] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 228.418913] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 228.418976] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.419020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.419060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.419099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.419142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.419190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.419238] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.419289] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.419339] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.419389] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.419512] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.419573] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.419673] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.419732] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.419795] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.420286] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.420367] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.420472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.420485] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.420491] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.420551] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.420613] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.420670] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.420732] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.420790] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.420846] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.420859] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.420915] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.420926] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.420984] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.421038] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.421090] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.421145] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.421207] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.421261] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.421322] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.421378] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.421476] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.421568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 228.421640] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.421834] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 228.421926] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.421991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.422030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.422054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.422078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.422101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.422126] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.422154] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.422180] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.422205] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.422227] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.422250] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.422277] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 228.422303] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 228.422347] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 228.424060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 228.424078] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 228.424094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 228.424109] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 228.441030] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 228.441049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 228.457950] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 228.460011] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 228.460206] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 228.461384] [drm:intel_enable_pipe [i915]] enabling pipe C [ 228.461420] [drm:intel_mst_enable_dp [i915]] 1 [ 228.463823] [drm:drm_dp_update_payload_part2] payload 0 1 [ 228.465199] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.465223] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.465277] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.465823] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.466413] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 228.466517] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 228.466548] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 228.466633] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.466658] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.466699] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.467099] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.467115] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.478558] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.478600] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.478631] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.478637] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.478639] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.478669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.478699] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.478726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.478753] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.478779] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.478803] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.478810] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.478833] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.478838] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.478863] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.478888] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.478912] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.478935] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.478968] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.479000] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.479035] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.479067] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.479100] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.479146] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 228.479185] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.495164] [drm:intel_mst_disable_dp [i915]] 1 [ 228.495173] [drm:drm_dp_update_payload_part1] [ 228.496735] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.496786] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.496880] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.497544] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.499543] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.499599] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.499901] [drm:drm_dp_update_payload_part1] removing payload 0 [ 228.499952] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 228.500002] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 228.500095] [drm:intel_disable_pipe [i915]] disabling pipe C [ 228.511655] [drm:intel_mst_post_disable_dp [i915]] 1 [ 228.519120] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 228.519750] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 228.519795] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 228.519841] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 228.519899] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.519939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.519976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.520012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.520047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.520080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.520116] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.520154] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.520189] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.520224] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.520256] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.520289] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.520348] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.520393] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.520517] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.520995] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.521040] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.521075] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.521085] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.521089] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.521129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.521169] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.521206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.521240] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.521277] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.521311] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.521320] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.521354] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.521361] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.521392] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.521447] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.521486] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.521520] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.521562] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.521597] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.521632] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.521670] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.521707] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.521764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 228.521809] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.521930] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 228.521989] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.522028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.522065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.522098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.522134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.522168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.522205] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.522241] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.522275] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.522313] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.522348] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.522382] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.522441] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 228.522475] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 228.522540] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 228.524097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 228.524125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 228.524149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 228.524172] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 228.541132] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 228.541149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 228.558071] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 228.560107] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 228.560305] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 228.561412] [drm:intel_enable_pipe [i915]] enabling pipe C [ 228.561440] [drm:intel_mst_enable_dp [i915]] 1 [ 228.563842] [drm:drm_dp_update_payload_part2] payload 0 1 [ 228.565213] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.565235] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.565290] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.565848] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.566465] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 228.566497] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 228.566538] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 228.566619] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.566659] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.566706] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.567152] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.567173] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.578507] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.578542] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.578571] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.578576] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.578578] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.578607] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.578635] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.578662] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.578690] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.578717] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.578744] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.578749] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.578775] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.578780] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.578807] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.578834] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.578862] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.578889] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.578917] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.578943] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.578971] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.578999] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.579026] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.579066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 228.579098] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.595154] [drm:intel_mst_disable_dp [i915]] 1 [ 228.595162] [drm:drm_dp_update_payload_part1] [ 228.596711] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.596753] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.596855] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.597510] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.599381] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.599459] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.599760] [drm:drm_dp_update_payload_part1] removing payload 0 [ 228.599807] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 228.599856] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 228.599947] [drm:intel_disable_pipe [i915]] disabling pipe C [ 228.613664] [drm:intel_mst_post_disable_dp [i915]] 1 [ 228.618686] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 228.619157] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 228.619200] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 228.619246] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 228.619304] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.619344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.619381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.619505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.619544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.619579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.619615] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.619654] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.619691] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.619728] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.619762] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.619794] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.619856] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.619892] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.619931] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.620276] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.620329] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.620371] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.620426] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.620433] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.620474] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.620516] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.620554] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.620594] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.620631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.620667] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.620677] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.620715] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.620723] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.620762] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.620800] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.620838] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.620863] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.620891] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.620916] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.620941] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.620965] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.620989] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.621030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 228.621066] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.621157] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 228.621200] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.621228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.621253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.621278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.621303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.621326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.621352] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.621381] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.621445] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.621485] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.621522] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.621560] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.621606] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 228.621649] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 228.621718] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 228.623236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 228.623266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 228.623291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 228.623316] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 228.640264] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 228.640282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 228.657200] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 228.659249] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 228.659445] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 228.660662] [drm:intel_enable_pipe [i915]] enabling pipe C [ 228.660687] [drm:intel_mst_enable_dp [i915]] 1 [ 228.663067] [drm:drm_dp_update_payload_part2] payload 0 1 [ 228.664444] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.664465] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.664519] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.665062] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.665631] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 228.665656] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 228.665694] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 228.665760] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.665785] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.665844] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.666332] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.666349] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.677765] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.677802] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.677832] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.677837] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.677840] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.677868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.677895] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.677921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.677945] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.677968] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.677991] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.677996] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.678019] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.678023] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.678047] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.678069] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.678091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.678113] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.678139] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.678161] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.678185] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.678207] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.678229] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.678265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 228.678296] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.694390] [drm:intel_mst_disable_dp [i915]] 1 [ 228.694421] [drm:drm_dp_update_payload_part1] [ 228.695933] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.695984] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.696074] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.696744] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.698881] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.698940] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.699244] [drm:drm_dp_update_payload_part1] removing payload 0 [ 228.699297] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 228.699350] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 228.699691] [drm:intel_disable_pipe [i915]] disabling pipe C [ 228.711514] [drm:intel_mst_post_disable_dp [i915]] 1 [ 228.718721] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 228.719151] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 228.719185] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 228.719221] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 228.719268] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.719299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.719328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.719357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.719383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.719470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.719835] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.719870] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.719901] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.719931] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.719959] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.719985] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.720035] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.720066] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.720098] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.720405] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.720654] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.720678] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.720684] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.720686] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.720710] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.720733] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.720755] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.720777] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.720798] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.720818] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.720822] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.720842] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.720846] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.720865] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.720885] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.720904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.720923] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.720946] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.720965] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.720985] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.721005] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.721023] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.721056] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 228.721084] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.721156] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 228.721197] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.721225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.721252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.721279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.721306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.721333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.721360] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.721422] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.722188] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.722215] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.722238] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.722259] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.722284] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 228.722307] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 228.722345] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 228.723884] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 228.723909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 228.723931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 228.723953] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 228.740810] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 228.740829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 228.757660] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 228.759434] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 228.759637] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 228.760809] [drm:intel_enable_pipe [i915]] enabling pipe C [ 228.760834] [drm:intel_mst_enable_dp [i915]] 1 [ 228.763220] [drm:drm_dp_update_payload_part2] payload 0 1 [ 228.764594] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.764618] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.764672] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.765216] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.765805] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 228.765833] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 228.765866] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 228.765938] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.765967] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.766016] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.766514] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.766537] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.777861] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.777898] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.777926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.777932] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.777934] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.777961] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.777987] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.778012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.778037] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.778060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.778082] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.778087] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.778109] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.778113] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.778136] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.778159] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.778180] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.778202] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.778227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.778256] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.778288] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.778318] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.778347] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.778390] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 228.778478] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.794513] [drm:intel_mst_disable_dp [i915]] 1 [ 228.794520] [drm:drm_dp_update_payload_part1] [ 228.796066] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.796108] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.796206] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.796952] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.798961] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.799021] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.799322] [drm:drm_dp_update_payload_part1] removing payload 0 [ 228.799373] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 228.799488] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 228.799600] [drm:intel_disable_pipe [i915]] disabling pipe C [ 228.811677] [drm:intel_mst_post_disable_dp [i915]] 1 [ 228.818073] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 228.818540] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 228.818586] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 228.818635] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 228.818694] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.818722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.818749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.818774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.818798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.818822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.818847] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.818874] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.818900] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.818926] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.818949] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.818971] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.819015] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.819040] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.819066] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.819301] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.819333] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.819358] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.819405] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.819412] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.819450] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.819517] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.819599] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.819637] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.819675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.819757] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.819765] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.819799] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.819818] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.819854] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.819889] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.819923] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.819955] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.820023] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.820091] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.820129] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.820195] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.820241] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.820343] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 228.820390] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.820520] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 228.820565] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.820595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.820623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.820650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.820675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.820718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.820763] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.820789] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.820815] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.820849] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.820873] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.820896] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.820924] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 228.820950] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 228.820996] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 228.822560] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 228.822590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 228.822619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 228.822648] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 228.839575] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 228.839593] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 228.856492] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 228.858529] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 228.858725] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 228.859888] [drm:intel_enable_pipe [i915]] enabling pipe C [ 228.859913] [drm:intel_mst_enable_dp [i915]] 1 [ 228.862319] [drm:drm_dp_update_payload_part2] payload 0 1 [ 228.863696] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.863720] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.863784] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.864334] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.864914] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 228.864941] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 228.864974] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 228.865048] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.865086] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.865130] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.865612] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.865633] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.877042] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.877083] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.877115] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.877121] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.877123] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.877153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.877183] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.877211] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.877239] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.877265] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.877290] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.877295] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.877319] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.877324] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.877349] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.877382] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.877468] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.877504] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.877544] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.877578] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.877615] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.877650] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.877689] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.877746] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 228.877794] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.893664] [drm:intel_mst_disable_dp [i915]] 1 [ 228.893672] [drm:drm_dp_update_payload_part1] [ 228.895224] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.895278] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.895390] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.896087] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.898080] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.898143] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.898459] [drm:drm_dp_update_payload_part1] removing payload 0 [ 228.898533] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 228.898612] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 228.898721] [drm:intel_disable_pipe [i915]] disabling pipe C [ 228.910682] [drm:intel_mst_post_disable_dp [i915]] 1 [ 228.917142] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 228.917660] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 228.917713] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 228.917773] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 228.917849] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.917902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.917948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.917997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.918045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.918092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.918138] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.918191] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.918241] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.918290] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.918333] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.918374] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.918498] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.918547] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.918599] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.919021] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.919082] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.919130] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.919142] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.919147] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.919197] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.919249] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.919298] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.919343] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.919390] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.919475] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.919491] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.919538] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.919552] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.919603] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.919651] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.919702] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.919746] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.919796] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.919847] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.919897] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.919944] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.919988] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.920062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 228.920121] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.920644] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 228.920718] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 228.920766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 228.920819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 228.920869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 228.920916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 228.920961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 228.921005] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 228.921057] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 228.921107] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 228.921156] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 228.921198] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 228.921238] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.921291] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 228.921341] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 228.921445] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 228.923087] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 228.923111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 228.923133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 228.923157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 228.940101] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 228.940119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 228.957007] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 228.959068] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 228.959264] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 228.960419] [drm:intel_enable_pipe [i915]] enabling pipe C [ 228.960446] [drm:intel_mst_enable_dp [i915]] 1 [ 228.962837] [drm:drm_dp_update_payload_part2] payload 0 1 [ 228.964195] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.964216] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.964265] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.964815] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.965394] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 228.965448] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 228.965490] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 228.965591] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 228.965624] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 228.965678] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 228.966106] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.966138] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.977517] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 228.977547] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 228.977569] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 228.977573] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 228.977575] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 228.977596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 228.977617] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 228.977637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 228.977656] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 228.977675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 228.977692] [drm:intel_dump_pipe_config [i915]] requested mode: [ 228.977697] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.977714] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 228.977717] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 228.977735] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 228.977758] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 228.977782] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 228.977806] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 228.977830] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 228.977852] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 228.977877] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 228.977901] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 228.977924] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 228.977959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 228.977986] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 228.994183] [drm:intel_mst_disable_dp [i915]] 1 [ 228.994190] [drm:drm_dp_update_payload_part1] [ 228.995744] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 228.995795] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 228.995890] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 228.996535] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 228.998515] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 228.998573] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 228.998870] [drm:drm_dp_update_payload_part1] removing payload 0 [ 228.998920] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 228.998970] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 228.999041] [drm:intel_disable_pipe [i915]] disabling pipe C [ 229.011385] [drm:intel_mst_post_disable_dp [i915]] 1 [ 229.018085] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 229.018670] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 229.018707] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 229.018744] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 229.018794] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.018827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.018857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.018886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.018914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.018941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.018971] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.019003] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.019033] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.019062] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.019089] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.019115] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.019163] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.019193] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.019224] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.019602] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.019657] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.019704] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.019710] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.019713] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.019745] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.019776] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.019805] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.019836] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.019863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.019889] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.019896] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.019922] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.019927] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.019954] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.019997] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.020039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.020066] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.020097] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.020124] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.020151] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.020177] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.020212] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.020276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 229.020314] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.020454] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 229.020524] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.020571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.020613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.020657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.020697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.020736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.020776] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.020826] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.020869] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.020910] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.020948] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.020989] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.021036] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 229.021081] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 229.021157] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 229.023291] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 229.023331] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 229.023362] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 229.023433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 229.040323] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 229.040341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 229.057171] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 229.059239] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 229.059442] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 229.060644] [drm:intel_enable_pipe [i915]] enabling pipe C [ 229.060670] [drm:intel_mst_enable_dp [i915]] 1 [ 229.063071] [drm:drm_dp_update_payload_part2] payload 0 1 [ 229.064457] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.064480] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.064535] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.065083] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.065661] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 229.065685] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 229.065714] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 229.065779] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.065801] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.065855] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.066348] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.066368] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.077665] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.077690] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.077708] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.077712] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.077714] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.077731] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.077749] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.077766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.077782] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.077797] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.077812] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.077815] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.077830] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.077833] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.077848] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.077862] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.077876] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.077890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.077907] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.077921] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.077937] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.077951] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.077965] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.077990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 229.078010] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.094308] [drm:intel_mst_disable_dp [i915]] 1 [ 229.094313] [drm:drm_dp_update_payload_part1] [ 229.095827] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.095863] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.095930] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.096533] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.098468] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.098512] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.098816] [drm:drm_dp_update_payload_part1] removing payload 0 [ 229.098855] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 229.098895] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 229.098957] [drm:intel_disable_pipe [i915]] disabling pipe C [ 229.111324] [drm:intel_mst_post_disable_dp [i915]] 1 [ 229.117781] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 229.118235] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 229.118276] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 229.118318] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 229.118373] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.118474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.118536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.118591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.118643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.118693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.118742] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.118793] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.118848] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.118902] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.118951] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.118998] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.119086] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.119141] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.119198] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.119612] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.119655] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.119688] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.119696] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.119699] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.119735] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.119772] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.119806] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.119838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.119867] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.119899] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.119906] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.119937] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.119944] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.119977] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.120006] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.120034] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.120066] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.120101] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.120132] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.120164] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.120192] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.120224] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.120275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 229.120315] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.120448] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 229.120502] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.120538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.120574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.120604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.120637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.120669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.120703] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.120736] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.120767] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.120802] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.120834] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.120865] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.120900] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 229.120931] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 229.120989] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 229.122528] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 229.122554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 229.122577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 229.122599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 229.139514] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 229.139533] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 229.156432] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 229.158482] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 229.158680] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 229.159820] [drm:intel_enable_pipe [i915]] enabling pipe C [ 229.159846] [drm:intel_mst_enable_dp [i915]] 1 [ 229.162251] [drm:drm_dp_update_payload_part2] payload 0 1 [ 229.163627] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.163650] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.163703] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.164239] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.164810] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 229.164834] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 229.164862] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 229.164926] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.164949] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.165004] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.165503] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.165528] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.176867] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.176903] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.176930] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.176935] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.176937] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.176963] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.176990] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.177014] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.177038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.177060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.177082] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.177087] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.177108] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.177112] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.177135] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.177156] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.177177] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.177198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.177222] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.177243] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.177266] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.177287] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.177307] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.177342] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 229.177370] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.193486] [drm:intel_mst_disable_dp [i915]] 1 [ 229.193491] [drm:drm_dp_update_payload_part1] [ 229.195021] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.195068] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.195184] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.195864] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.197858] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.197914] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.198215] [drm:drm_dp_update_payload_part1] removing payload 0 [ 229.198269] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 229.198320] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 229.198400] [drm:intel_disable_pipe [i915]] disabling pipe C [ 229.210583] [drm:intel_mst_post_disable_dp [i915]] 1 [ 229.217405] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 229.217851] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 229.217887] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 229.217927] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 229.217979] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.218013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.218046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.218078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.218109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.218139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.218170] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.218203] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.218235] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.218265] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.218303] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.218342] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.218461] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.218513] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.218569] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.218922] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.218950] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.218971] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.218976] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.218978] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.219009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.219042] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.219074] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.219105] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.219134] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.219155] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.219160] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.219178] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.219182] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.219200] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.219218] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.219235] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.219253] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.219274] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.219292] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.219311] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.219328] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.219346] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.219408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 229.219446] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.219553] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 229.219600] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.219630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.219660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.219688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.219716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.219745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.219773] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.219802] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.219831] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.219861] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.219891] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.219920] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.219953] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 229.219985] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 229.220036] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 229.221547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 229.221569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 229.221589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 229.221610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 229.238533] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 229.238550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 229.255450] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 229.257518] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 229.257717] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 229.258860] [drm:intel_enable_pipe [i915]] enabling pipe C [ 229.258887] [drm:intel_mst_enable_dp [i915]] 1 [ 229.261289] [drm:drm_dp_update_payload_part2] payload 0 1 [ 229.262666] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.262689] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.262732] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.263269] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.263846] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 229.263871] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 229.263901] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 229.263970] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.263995] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.264053] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.264561] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.264586] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.275992] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.276028] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.276056] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.276061] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.276063] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.276088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.276114] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.276139] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.276162] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.276185] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.276206] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.276211] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.276233] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.276237] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.276259] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.276280] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.276301] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.276321] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.276346] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.276367] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.276427] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.276465] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.276500] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.276555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 229.276594] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.292638] [drm:intel_mst_disable_dp [i915]] 1 [ 229.292645] [drm:drm_dp_update_payload_part1] [ 229.294182] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.294219] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.294291] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.294895] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.296812] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.296851] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.297178] [drm:drm_dp_update_payload_part1] removing payload 0 [ 229.297226] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 229.297271] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 229.297339] [drm:intel_disable_pipe [i915]] disabling pipe C [ 229.310681] [drm:intel_mst_post_disable_dp [i915]] 1 [ 229.316612] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 229.317040] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 229.317072] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 229.317108] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 229.317155] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.317186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.317215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.317242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.317268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.317293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.317320] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.317349] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.317377] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.317463] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.317639] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.317682] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.317755] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.317788] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.317839] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.318160] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.318198] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.318228] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.318234] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.318237] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.318266] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.318295] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.318322] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.318359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.318433] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.318472] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.318481] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.318518] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.318526] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.318566] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.318605] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.318643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.318680] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.318723] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.318760] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.318801] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.318843] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.318882] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.318949] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 229.319001] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.319142] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 229.319207] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.319251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.319294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.319336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.319377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.319443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.319485] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.319529] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.319574] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.319615] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.319658] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.319698] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.319746] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 229.319790] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 229.319864] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 229.321852] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 229.321897] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 229.321944] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 229.321991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 229.338911] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 229.338929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 229.355802] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 229.357860] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 229.358068] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 229.359297] [drm:intel_enable_pipe [i915]] enabling pipe C [ 229.359325] [drm:intel_mst_enable_dp [i915]] 1 [ 229.361728] [drm:drm_dp_update_payload_part2] payload 0 1 [ 229.363103] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.363126] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.363175] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.363749] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.364326] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 229.364353] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 229.364421] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 229.364502] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.364533] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.364581] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.365613] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.365633] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.376311] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.376340] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.376362] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.376393] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.376396] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.376425] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.376454] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.376483] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.376503] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.376520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.376537] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.376542] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.376558] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.376561] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.376578] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.376594] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.376611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.376626] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.376645] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.376662] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.376679] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.376695] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.376711] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.376742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 229.376764] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.392996] [drm:intel_mst_disable_dp [i915]] 1 [ 229.393004] [drm:drm_dp_update_payload_part1] [ 229.394552] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.394595] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.394695] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.395314] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.397327] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.397373] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.397686] [drm:drm_dp_update_payload_part1] removing payload 0 [ 229.397743] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 229.397806] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 229.397898] [drm:intel_disable_pipe [i915]] disabling pipe C [ 229.409634] [drm:intel_mst_post_disable_dp [i915]] 1 [ 229.416536] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 229.416983] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 229.417007] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 229.417034] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 229.417070] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.417092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.417113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.417133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.417152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.417170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.417190] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.417211] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.417231] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.417251] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.417269] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.417287] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.417323] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.417348] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.417376] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.417883] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.417913] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.417937] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.417942] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.417944] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.417966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.417988] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.418008] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.418029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.418047] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.418066] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.418070] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.418088] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.418092] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.418111] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.418129] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.418147] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.418164] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.418186] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.418204] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.418224] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.418242] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.418259] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.418290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 229.418316] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.418787] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 229.418837] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.418869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.418899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.418929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.418960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.418990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.419021] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.419049] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.419070] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.419090] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.419108] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.419126] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.419148] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 229.419169] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 229.419203] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 229.420924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 229.420940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 229.420955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 229.420970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 229.437883] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 229.437900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 229.454800] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 229.456858] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 229.457052] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 229.458182] [drm:intel_enable_pipe [i915]] enabling pipe C [ 229.458209] [drm:intel_mst_enable_dp [i915]] 1 [ 229.460601] [drm:drm_dp_update_payload_part2] payload 0 1 [ 229.461978] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.462000] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.462064] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.462610] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.463190] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 229.463219] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 229.463253] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 229.463330] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.463371] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.463442] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.463928] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.463951] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.475256] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.475293] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.475321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.475327] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.475329] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.475355] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.475429] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.475471] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.475511] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.475547] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.475581] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.475591] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.475622] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.475629] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.475664] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.475698] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.475733] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.475764] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.475800] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.475834] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.475867] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.475899] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.475931] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.475986] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 229.476027] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.491830] [drm:intel_mst_disable_dp [i915]] 1 [ 229.491837] [drm:drm_dp_update_payload_part1] [ 229.493381] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.493429] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.493517] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.494162] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.496196] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.496261] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.496612] [drm:drm_dp_update_payload_part1] removing payload 0 [ 229.496687] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 229.496765] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 229.496881] [drm:intel_disable_pipe [i915]] disabling pipe C [ 229.508529] [drm:intel_mst_post_disable_dp [i915]] 1 [ 229.515202] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 229.515737] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 229.515788] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 229.515841] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 229.515908] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.515955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.516000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.516041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.516082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.516122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.516164] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.516218] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.516272] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.516326] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.516378] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.516494] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.516606] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.516662] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.516713] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.517084] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.517122] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.517153] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.517159] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.517162] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.517191] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.517221] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.517249] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.517280] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.517315] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.517348] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.517355] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.517425] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.517439] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.517482] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.517524] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.517564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.517603] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.517646] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.517687] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.517730] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.517772] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.517814] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.517882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 229.517936] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.518081] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 229.518146] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.518188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.518229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.518269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.518308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.518346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.518387] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.518444] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.518469] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.518494] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.518518] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.518540] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.518570] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 229.518595] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 229.518640] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 229.520118] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 229.520135] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 229.520150] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 229.520165] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 229.537016] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 229.537033] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 229.553864] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 229.555426] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 229.555630] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 229.556840] [drm:intel_enable_pipe [i915]] enabling pipe C [ 229.556865] [drm:intel_mst_enable_dp [i915]] 1 [ 229.559260] [drm:drm_dp_update_payload_part2] payload 0 1 [ 229.560642] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.560665] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.560706] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.561259] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.561836] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 229.561860] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 229.561890] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 229.561955] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.561979] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.562023] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.562529] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.562554] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.573868] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.573893] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.573912] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.573916] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.573917] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.573935] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.573953] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.573969] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.573989] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.574009] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.574029] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.574032] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.574052] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.574055] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.574075] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.574095] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.574115] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.574135] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.574155] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.574173] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.574194] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.574214] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.574234] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.574262] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 229.574285] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.590551] [drm:intel_mst_disable_dp [i915]] 1 [ 229.590557] [drm:drm_dp_update_payload_part1] [ 229.592093] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.592135] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.592222] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.592838] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.594699] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.594747] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.595039] [drm:drm_dp_update_payload_part1] removing payload 0 [ 229.595077] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 229.595116] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 229.595175] [drm:intel_disable_pipe [i915]] disabling pipe C [ 229.608615] [drm:intel_mst_post_disable_dp [i915]] 1 [ 229.613837] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 229.614262] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 229.614298] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 229.614336] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 229.614451] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.614490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.614526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.614562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.614598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.614633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.614668] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.614706] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.614743] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.614779] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.614814] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.614848] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.614907] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.614943] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.614982] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.615240] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.615280] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.615315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.615321] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.615324] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.615362] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.615449] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.615493] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.615535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.615575] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.615613] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.615623] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.615660] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.615671] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.615709] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.615747] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.615784] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.615821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.615863] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.615901] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.615940] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.615976] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.616012] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.616077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 229.616127] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.616268] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 229.616328] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.616371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.616443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.616488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.616528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.616569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.616610] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.616652] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.616694] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.616734] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.616771] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.616810] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.616853] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 229.616894] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 229.616963] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 229.618896] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 229.618933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 229.618964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 229.619000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 229.635920] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 229.635939] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 229.652838] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 229.654891] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 229.655086] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 229.656182] [drm:intel_enable_pipe [i915]] enabling pipe C [ 229.656209] [drm:intel_mst_enable_dp [i915]] 1 [ 229.658612] [drm:drm_dp_update_payload_part2] payload 0 1 [ 229.659987] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.660011] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.660055] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.660600] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.661167] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 229.661193] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 229.661224] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 229.661296] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.661321] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.661409] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.661905] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.661925] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.673266] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.673301] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.673328] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.673333] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.673335] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.673359] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.673436] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.673470] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.673504] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.673535] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.673564] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.673571] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.673602] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.673608] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.673640] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.673670] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.673698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.673726] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.673760] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.673791] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.673823] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.673853] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.673880] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.673929] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 229.673968] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.689915] [drm:intel_mst_disable_dp [i915]] 1 [ 229.689922] [drm:drm_dp_update_payload_part1] [ 229.691461] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.691514] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.691641] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.692305] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.694315] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.694376] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.694864] [drm:drm_dp_update_payload_part1] removing payload 0 [ 229.694914] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 229.694966] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 229.695045] [drm:intel_disable_pipe [i915]] disabling pipe C [ 229.707454] [drm:intel_mst_post_disable_dp [i915]] 1 [ 229.713874] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 229.714309] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 229.714344] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 229.714381] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 229.714678] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.714730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.714780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.714828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.714872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.714901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.714931] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.714964] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.714993] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.715022] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.715049] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.715075] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.715124] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.715154] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.715186] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.716047] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.716102] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.716149] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.716158] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.716163] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.716208] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.716252] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.716295] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.716331] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.716356] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.716421] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.716432] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.716469] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.716594] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.716636] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.716676] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.716704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.716727] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.716755] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.716780] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.716820] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.716857] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.716881] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.716922] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 229.716956] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.717073] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 229.717131] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.717173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.717214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.717251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.717287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.717323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.717361] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.717434] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.717476] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.717517] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.717555] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.717592] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.717637] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 229.717679] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 229.717747] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 229.719328] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 229.719375] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 229.719477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 229.719519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 229.736583] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 229.736602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 229.753501] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 229.755570] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 229.755769] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 229.756905] [drm:intel_enable_pipe [i915]] enabling pipe C [ 229.756933] [drm:intel_mst_enable_dp [i915]] 1 [ 229.759343] [drm:drm_dp_update_payload_part2] payload 0 1 [ 229.760849] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.760872] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.760934] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.761476] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.762039] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 229.762064] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 229.762094] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 229.762163] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.762188] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.762246] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.762748] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.762767] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.774086] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.774122] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.774150] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.774155] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.774158] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.774184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.774211] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.774235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.774259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.774281] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.774303] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.774308] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.774329] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.774333] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.774356] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.774424] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.774459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.774493] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.774531] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.774564] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.774599] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.774632] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.774665] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.774725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 229.774910] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.790661] [drm:intel_mst_disable_dp [i915]] 1 [ 229.790670] [drm:drm_dp_update_payload_part1] [ 229.792206] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.792244] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.792312] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.792948] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.794904] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.794961] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.795257] [drm:drm_dp_update_payload_part1] removing payload 0 [ 229.795306] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 229.795355] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 229.795523] [drm:intel_disable_pipe [i915]] disabling pipe C [ 229.807924] [drm:intel_mst_post_disable_dp [i915]] 1 [ 229.814607] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 229.815032] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 229.815068] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 229.815106] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 229.815158] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.815194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.815229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.815264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.815298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.815333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.815374] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.815456] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.815509] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.815559] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.815603] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.815643] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.815993] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.816041] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.816095] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.816535] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.816591] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.816636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.816645] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.816649] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.816693] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.816737] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.816778] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.816816] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.816856] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.816893] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.816902] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.816940] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.816948] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.816984] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.817019] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.817058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.817096] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.817139] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.817175] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.817211] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.817250] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.817288] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.817348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 229.817452] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.817590] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 229.817652] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.817691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.817728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.817767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.817806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.817845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.817883] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.817922] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.817964] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.818005] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.818042] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.818078] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.818118] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 229.818161] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 229.818231] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 229.819851] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 229.819876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 229.819903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 229.819929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 229.836854] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 229.836872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 229.853784] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 229.855852] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 229.856050] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 229.857144] [drm:intel_enable_pipe [i915]] enabling pipe C [ 229.857172] [drm:intel_mst_enable_dp [i915]] 1 [ 229.859575] [drm:drm_dp_update_payload_part2] payload 0 1 [ 229.860960] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.860982] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.861027] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.861571] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.862140] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 229.862166] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 229.862197] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 229.862265] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.862290] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.862335] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.862856] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.862873] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.874208] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.874243] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.874269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.874274] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.874276] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.874301] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.874326] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.874350] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.874426] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.874465] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.874500] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.874509] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.874541] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.874549] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.874581] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.874614] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.874647] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.874678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.874713] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.874745] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.874780] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.874811] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.874841] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.874893] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 229.874932] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.890852] [drm:intel_mst_disable_dp [i915]] 1 [ 229.890859] [drm:drm_dp_update_payload_part1] [ 229.892396] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.892436] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.892533] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.893287] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.895140] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.895183] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.895502] [drm:drm_dp_update_payload_part1] removing payload 0 [ 229.895555] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 229.895607] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 229.895691] [drm:intel_disable_pipe [i915]] disabling pipe C [ 229.907782] [drm:intel_mst_post_disable_dp [i915]] 1 [ 229.914250] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 229.914720] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 229.914759] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 229.914799] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 229.914851] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.914886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.914919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.914951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.914981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.915010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.915041] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.915074] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.915106] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.915137] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.915165] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.915193] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.915244] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.915276] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.915309] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.915962] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.916012] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.916047] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.916053] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.916057] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.916083] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.916109] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.916133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.916157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.916180] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.916202] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.916208] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.916229] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.916234] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.916256] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.916278] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.916299] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.916319] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.916345] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.916370] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.916431] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.916468] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.916504] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.916560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 229.916605] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.916726] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 229.916784] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 229.916822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 229.916859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 229.916896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 229.916932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 229.916968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 229.917004] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 229.917043] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 229.917081] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 229.917119] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 229.917154] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 229.917188] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.917228] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 229.917266] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 229.917329] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 229.919201] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 229.919244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 229.919282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 229.919318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 229.938446] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 229.938465] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 229.957569] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 229.959421] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 229.959896] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 229.963738] [drm:intel_enable_pipe [i915]] enabling pipe C [ 229.963766] [drm:intel_mst_enable_dp [i915]] 1 [ 229.968319] [drm:drm_dp_update_payload_part2] payload 0 1 [ 229.969702] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.969729] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.969791] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 229.972464] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 229.975155] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 229.975188] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 229.975228] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 229.975312] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 229.975344] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 229.975433] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 229.978228] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 229.978254] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 229.980791] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 229.980823] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 229.980848] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 229.980852] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 229.980855] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 229.980877] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 229.980900] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 229.980921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 229.980947] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 229.980972] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 229.980997] [drm:intel_dump_pipe_config [i915]] requested mode: [ 229.981002] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.981027] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 229.981031] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 229.981057] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 229.981083] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 229.981108] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 229.981134] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 229.981159] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 229.981184] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 229.981211] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 229.981236] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 229.981262] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 229.981299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 229.981329] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 229.997434] [drm:intel_mst_disable_dp [i915]] 1 [ 229.997441] [drm:drm_dp_update_payload_part1] [ 229.998980] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 229.999016] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 229.999105] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.001847] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.008862] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.008900] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.011402] [drm:drm_dp_update_payload_part1] removing payload 0 [ 230.011428] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 230.011456] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 230.011496] [drm:intel_disable_pipe [i915]] disabling pipe C [ 230.015614] [drm:intel_mst_post_disable_dp [i915]] 1 [ 230.028648] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 230.029624] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 230.029650] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 230.029677] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 230.029714] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.029737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.029759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.029780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.029800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.029819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.029839] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.029861] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.029882] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.029902] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.029921] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.029940] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.029975] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.029995] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.030018] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.030214] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.030241] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.030262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.030266] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.030268] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.030289] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.030311] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.030331] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.030350] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.030409] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.030441] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.030451] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.030480] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.030488] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.030518] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.030548] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.030579] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.030609] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.030642] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.030672] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.030703] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.030734] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.030764] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.030813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 230.030850] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.030956] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 230.031003] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.031034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.031064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.031093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.031122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.031150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.031179] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.031210] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.031240] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.031271] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.031299] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.031410] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.031445] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 230.031477] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 230.031532] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 230.033361] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 230.033416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 230.033451] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 230.033485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 230.050422] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 230.050440] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 230.067338] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 230.069401] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 230.069597] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 230.070815] [drm:intel_enable_pipe [i915]] enabling pipe C [ 230.070843] [drm:intel_mst_enable_dp [i915]] 1 [ 230.073246] [drm:drm_dp_update_payload_part2] payload 0 1 [ 230.074615] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.074637] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.074683] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.075231] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.075836] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 230.075862] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 230.075894] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 230.075969] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.075995] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.076042] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.076541] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.076571] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.087829] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.087855] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.087874] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.087878] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.087880] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.087898] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.087917] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.087934] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.087950] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.087966] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.087981] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.087985] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.088005] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.088008] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.088029] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.088050] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.088071] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.088091] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.088112] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.088131] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.088153] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.088174] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.088194] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.088224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 230.088248] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.104481] [drm:intel_mst_disable_dp [i915]] 1 [ 230.104487] [drm:drm_dp_update_payload_part1] [ 230.106013] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.106048] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.106131] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.106788] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.108677] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.108723] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.109029] [drm:drm_dp_update_payload_part1] removing payload 0 [ 230.109069] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 230.109113] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 230.109176] [drm:intel_disable_pipe [i915]] disabling pipe C [ 230.121557] [drm:intel_mst_post_disable_dp [i915]] 1 [ 230.127404] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 230.127841] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 230.127876] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 230.127914] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 230.127968] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.128006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.128043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.128080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.128116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.128153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.128189] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.128228] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.128267] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.128305] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.128341] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.128383] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.128505] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.128560] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.128615] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.129053] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.129118] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.129186] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.129209] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.129214] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.129267] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.129316] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.129379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.129481] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.129527] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.129586] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.129597] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.129658] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.129667] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.129714] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.129773] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.129819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.129878] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.129925] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.130029] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.130092] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.130135] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.130182] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.130255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 230.130314] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.130502] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 230.130575] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.130627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.130675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.130719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.130761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.130809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.130857] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.130908] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.130956] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.131001] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.131049] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.131095] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.131148] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 230.131195] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 230.131276] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 230.132838] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 230.132856] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 230.132872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 230.132888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 230.149805] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 230.149823] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 230.166725] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 230.168794] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 230.168993] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 230.170093] [drm:intel_enable_pipe [i915]] enabling pipe C [ 230.170121] [drm:intel_mst_enable_dp [i915]] 1 [ 230.172506] [drm:drm_dp_update_payload_part2] payload 0 1 [ 230.173882] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.173905] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.173960] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.174503] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.175073] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 230.175099] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 230.175130] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 230.175200] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.175225] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.175279] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.175893] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.175911] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.187184] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.187223] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.187253] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.187258] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.187261] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.187288] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.187316] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.187342] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.187367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.187435] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.187471] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.187482] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.187516] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.187524] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.187559] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.187594] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.187628] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.187665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.187704] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.187743] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.187783] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.187819] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.187856] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.187907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 230.187939] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.203763] [drm:intel_mst_disable_dp [i915]] 1 [ 230.203771] [drm:drm_dp_update_payload_part1] [ 230.205329] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.205380] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.205486] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.206160] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.208138] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.208193] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.208521] [drm:drm_dp_update_payload_part1] removing payload 0 [ 230.208596] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 230.208670] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 230.208791] [drm:intel_disable_pipe [i915]] disabling pipe C [ 230.220557] [drm:intel_mst_post_disable_dp [i915]] 1 [ 230.227337] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 230.227788] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 230.227814] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 230.227840] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 230.227877] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.227901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.227922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.227943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.227963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.227982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.228003] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.228025] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.228046] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.228067] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.228086] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.228104] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.228140] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.228161] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.228183] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.228428] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.228467] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.228501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.228510] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.228513] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.228547] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.228581] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.228613] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.228644] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.228673] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.228702] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.228709] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.228739] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.228745] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.228775] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.228804] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.228834] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.228863] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.228895] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.228924] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.228955] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.228983] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.229012] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.229061] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 230.229100] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.229193] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 230.229240] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.229273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.229304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.229406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.229437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.229468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.229498] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.229531] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.229564] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.229596] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.229626] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.229656] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.229689] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 230.229721] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 230.229774] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 230.231709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 230.231733] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 230.231755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 230.231777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 230.248682] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 230.248700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 230.265602] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 230.267663] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 230.267861] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 230.268952] [drm:intel_enable_pipe [i915]] enabling pipe C [ 230.268979] [drm:intel_mst_enable_dp [i915]] 1 [ 230.271370] [drm:drm_dp_update_payload_part2] payload 0 1 [ 230.272750] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.272772] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.272825] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.273367] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.273976] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 230.274005] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 230.274040] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 230.274119] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.274161] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.274208] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.274694] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.274716] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.286087] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.286128] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.286159] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.286165] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.286168] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.286197] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.286225] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.286252] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.286278] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.286302] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.286326] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.286332] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.286355] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.286419] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.286457] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.286500] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.286537] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.286578] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.286609] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.286634] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.286660] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.286685] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.286709] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.286752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 230.286786] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.302643] [drm:intel_mst_disable_dp [i915]] 1 [ 230.302650] [drm:drm_dp_update_payload_part1] [ 230.304178] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.304219] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.304317] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.304988] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.306887] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.306941] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.307236] [drm:drm_dp_update_payload_part1] removing payload 0 [ 230.307284] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 230.307329] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 230.307452] [drm:intel_disable_pipe [i915]] disabling pipe C [ 230.319530] [drm:intel_mst_post_disable_dp [i915]] 1 [ 230.325893] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 230.326355] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 230.326467] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 230.326537] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 230.326616] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.326672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.326725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.326777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.326829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.326879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.326931] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.326985] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.327038] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.327090] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.327139] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.327187] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.327260] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.327285] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.327310] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.327613] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.327641] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.327663] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.327668] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.327670] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.327690] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.327712] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.327732] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.327752] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.327770] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.327788] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.327792] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.327810] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.327814] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.327832] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.327850] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.327868] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.327886] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.327906] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.327924] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.327943] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.327961] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.327978] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.328008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 230.328033] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.328101] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 230.328135] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.328155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.328175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.328194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.328212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.328230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.328249] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.328269] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.328288] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.328308] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.328325] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.328342] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.328404] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 230.328437] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 230.328490] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 230.329993] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 230.330016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 230.330035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 230.330056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 230.346988] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 230.347005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 230.363905] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 230.365975] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 230.366173] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 230.367355] [drm:intel_enable_pipe [i915]] enabling pipe C [ 230.367390] [drm:intel_mst_enable_dp [i915]] 1 [ 230.369798] [drm:drm_dp_update_payload_part2] payload 0 1 [ 230.371171] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.371193] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.371259] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.371814] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.372453] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 230.372485] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 230.372525] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 230.372616] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.372649] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.372699] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.373154] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.373176] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.384498] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.384537] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.384568] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.384573] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.384575] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.384603] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.384631] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.384658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.384684] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.384709] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.384732] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.384738] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.384761] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.384766] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.384790] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.384814] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.384837] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.384859] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.384890] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.384921] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.384954] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.384985] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.385016] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.385060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 230.385096] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.401079] [drm:intel_mst_disable_dp [i915]] 1 [ 230.401086] [drm:drm_dp_update_payload_part1] [ 230.402620] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.402655] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.402730] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.403348] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.405299] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.405355] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.405705] [drm:drm_dp_update_payload_part1] removing payload 0 [ 230.405752] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 230.405800] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 230.405896] [drm:intel_disable_pipe [i915]] disabling pipe C [ 230.419659] [drm:intel_mst_post_disable_dp [i915]] 1 [ 230.424812] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 230.425317] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 230.425375] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 230.425532] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 230.425649] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.425729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.425804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.425878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.425949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.426019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.426090] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.426167] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.426241] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.426316] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.426384] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.426499] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.426620] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.426693] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.426772] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.427439] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.427503] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.427552] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.427562] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.427567] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.427615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.427666] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.427711] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.427755] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.427797] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.427838] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.427848] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.427887] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.427896] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.427937] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.427979] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.428019] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.428057] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.428105] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.428145] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.428189] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.428228] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.428266] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.428333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 230.428448] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.428677] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 230.428773] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.428848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.428920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.428990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.429039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.429064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.429091] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.429122] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.429151] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.429179] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.429207] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.429233] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.429265] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 230.429295] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 230.429344] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 230.430832] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 230.430849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 230.430864] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 230.430879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 230.447798] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 230.447815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 230.464715] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 230.466778] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 230.466976] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 230.468157] [drm:intel_enable_pipe [i915]] enabling pipe C [ 230.468184] [drm:intel_mst_enable_dp [i915]] 1 [ 230.470579] [drm:drm_dp_update_payload_part2] payload 0 1 [ 230.471947] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.471969] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.472037] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.472594] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.473177] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 230.473206] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 230.473243] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 230.473322] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.473365] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.473434] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.473923] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.473945] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.485270] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.485306] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.485334] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.485340] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.485342] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.485413] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.485456] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.485497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.485535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.485568] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.485603] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.485611] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.485643] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.485650] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.485683] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.485716] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.485748] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.485779] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.485817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.485849] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.485884] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.485917] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.485950] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.486005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 230.486046] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.501920] [drm:intel_mst_disable_dp [i915]] 1 [ 230.501928] [drm:drm_dp_update_payload_part1] [ 230.503504] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.503564] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.503687] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.504378] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.506410] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.506505] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.506842] [drm:drm_dp_update_payload_part1] removing payload 0 [ 230.506895] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 230.506950] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 230.507032] [drm:intel_disable_pipe [i915]] disabling pipe C [ 230.519418] [drm:intel_mst_post_disable_dp [i915]] 1 [ 230.525570] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 230.525992] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 230.526022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 230.526057] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 230.526102] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.526132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.526159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.526186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.526211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.526236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.526262] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.526290] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.526316] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.526342] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.526411] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.526451] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.526520] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.526562] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.526608] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.526947] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.527001] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.527045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.527055] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.527059] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.527102] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.527146] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.527189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.527230] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.527270] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.527309] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.527318] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.527355] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.527394] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.527428] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.527462] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.527493] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.527524] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.527560] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.527592] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.527625] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.527657] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.527689] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.527744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 230.527784] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.527904] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 230.527958] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.527995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.528030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.528064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.528096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.528128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.528163] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.528199] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.528225] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.528248] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.528269] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.528300] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.528339] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 230.528373] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 230.528456] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 230.530087] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 230.530112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 230.530136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 230.530159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 230.547025] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 230.547043] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 230.563943] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 230.566013] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 230.566211] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 230.567374] [drm:intel_enable_pipe [i915]] enabling pipe C [ 230.567400] [drm:intel_mst_enable_dp [i915]] 1 [ 230.569792] [drm:drm_dp_update_payload_part2] payload 0 1 [ 230.571168] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.571190] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.571229] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.571769] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.572330] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 230.572356] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 230.572404] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 230.572478] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.572517] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.572557] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.573047] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.573073] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.584513] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.584550] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.584577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.584583] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.584585] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.584611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.584637] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.584662] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.584686] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.584708] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.584730] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.584735] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.584756] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.584761] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.584783] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.584804] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.584825] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.584845] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.584870] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.584891] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.584914] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.584935] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.584955] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.584990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 230.585019] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.601059] [drm:intel_mst_disable_dp [i915]] 1 [ 230.601066] [drm:drm_dp_update_payload_part1] [ 230.602586] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.602622] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.602683] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.603315] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.605246] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.605297] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.605644] [drm:drm_dp_update_payload_part1] removing payload 0 [ 230.605709] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 230.605777] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 230.605879] [drm:intel_disable_pipe [i915]] disabling pipe C [ 230.618275] [drm:intel_mst_post_disable_dp [i915]] 1 [ 230.624637] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 230.625095] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 230.625135] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 230.625178] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 230.625233] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.625272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.625306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.625338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.625369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.625477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.625531] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.625585] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.625635] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.625725] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.625771] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.625817] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.625899] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.625984] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.626038] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.626490] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.626538] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.626578] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.626586] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.626590] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.626627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.626664] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.626700] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.626737] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.626771] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.626805] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.626813] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.626844] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.626851] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.626883] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.626916] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.626960] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.626992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.627028] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.627060] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.627117] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.627177] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.627210] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.627265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 230.627305] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.627462] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 230.627540] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.627600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.627636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.627671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.627705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.627736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.627793] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.627841] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.627874] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.627907] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.627938] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.627970] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.628010] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 230.628045] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 230.628103] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 230.629679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 230.629698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 230.629715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 230.629732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 230.646649] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 230.646667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 230.663566] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 230.665635] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 230.665835] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 230.667003] [drm:intel_enable_pipe [i915]] enabling pipe C [ 230.667030] [drm:intel_mst_enable_dp [i915]] 1 [ 230.669436] [drm:drm_dp_update_payload_part2] payload 0 1 [ 230.670821] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.670844] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.670886] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.671428] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.671986] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 230.672009] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 230.672037] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 230.672104] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.672129] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.672186] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.672696] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.672718] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.684135] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.684174] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.684205] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.684210] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.684212] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.684241] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.684269] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.684296] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.684322] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.684346] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.684427] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.684439] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.684471] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.684480] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.684515] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.684546] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.684579] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.684611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.684651] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.684685] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.684723] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.684757] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.684792] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.684849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 230.684894] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.700772] [drm:intel_mst_disable_dp [i915]] 1 [ 230.700780] [drm:drm_dp_update_payload_part1] [ 230.702315] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.702354] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.702450] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.703227] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.705162] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.705218] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.705530] [drm:drm_dp_update_payload_part1] removing payload 0 [ 230.705602] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 230.705676] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 230.705787] [drm:intel_disable_pipe [i915]] disabling pipe C [ 230.717619] [drm:intel_mst_post_disable_dp [i915]] 1 [ 230.724073] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 230.724581] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 230.724629] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 230.724659] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 230.724699] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.724725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.724750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.724773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.724796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.724817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.724840] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.724865] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.724888] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.724910] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.724931] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.724951] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.724990] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.725012] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.725036] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.725244] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.725273] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.725297] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.725302] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.725304] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.725326] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.725349] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.725410] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.726033] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.726069] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.726103] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.726111] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.726145] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.726152] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.726187] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.726211] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.726233] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.726253] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.726277] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.726298] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.726319] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.726339] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.726391] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.726722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 230.726766] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.726884] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 230.726940] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.726965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.726988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.727010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.727032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.727053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.727075] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.727099] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.727121] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.727143] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.727163] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.727183] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.727209] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 230.727232] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 230.727270] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 230.728821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 230.728841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 230.728858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 230.728874] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 230.745796] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 230.745816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 230.762718] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 230.764780] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 230.764979] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 230.766153] [drm:intel_enable_pipe [i915]] enabling pipe C [ 230.766180] [drm:intel_mst_enable_dp [i915]] 1 [ 230.768581] [drm:drm_dp_update_payload_part2] payload 0 1 [ 230.769958] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.769982] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.770031] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.770570] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.771162] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 230.771192] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 230.771228] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 230.771307] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.771336] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.771422] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.771890] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.771912] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.783281] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.783317] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.783344] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.783395] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.783400] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.783438] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.783477] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.783512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.783545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.783576] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.783610] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.783617] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.783649] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.783656] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.783689] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.783718] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.783751] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.783782] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.783818] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.783848] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.783878] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.783911] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.783942] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.783994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 230.784035] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.799918] [drm:intel_mst_disable_dp [i915]] 1 [ 230.799927] [drm:drm_dp_update_payload_part1] [ 230.801480] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.801532] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.801656] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.802499] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.804514] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.804573] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.804878] [drm:drm_dp_update_payload_part1] removing payload 0 [ 230.804932] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 230.804985] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 230.805085] [drm:intel_disable_pipe [i915]] disabling pipe C [ 230.816531] [drm:intel_mst_post_disable_dp [i915]] 1 [ 230.824087] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 230.824541] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 230.824590] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 230.824641] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 230.824690] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.824720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.824748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.824774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.824799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.824823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.824850] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.824878] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.824905] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.824931] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.824955] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.824979] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.825023] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.825049] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.825077] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.825306] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.825339] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.825412] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.825424] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.825430] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.825470] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.825510] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.825548] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.825587] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.825624] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.825659] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.825669] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.825703] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.825712] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.825748] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.825784] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.825823] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.825860] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.825900] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.825937] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.825978] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.826016] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.826053] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.826114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 230.826164] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.826281] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 230.826343] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.826410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.826452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.826491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.826528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.826566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.826605] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.826645] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.826684] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.826727] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.826762] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.826796] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.826840] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 230.826880] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 230.826949] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 230.828456] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 230.828474] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 230.828491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 230.828508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 230.845397] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 230.845414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 230.862284] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 230.864343] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 230.864549] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 230.865701] [drm:intel_enable_pipe [i915]] enabling pipe C [ 230.865727] [drm:intel_mst_enable_dp [i915]] 1 [ 230.868121] [drm:drm_dp_update_payload_part2] payload 0 1 [ 230.869497] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.869518] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.869581] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.870111] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.870686] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 230.870719] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 230.870751] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 230.870817] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.870842] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.870887] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.871385] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.871410] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.882754] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.882778] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.882797] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.882801] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.882802] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.882820] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.882838] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.882855] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.882874] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.882894] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.882913] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.882917] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.882937] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.882940] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.882960] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.882980] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.882999] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.883019] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.883039] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.883058] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.883078] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.883098] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.883118] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.883146] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 230.883169] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.899434] [drm:intel_mst_disable_dp [i915]] 1 [ 230.899442] [drm:drm_dp_update_payload_part1] [ 230.900975] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.901014] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.901087] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.901703] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.903536] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.903580] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.903888] [drm:drm_dp_update_payload_part1] removing payload 0 [ 230.903927] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 230.903966] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 230.904023] [drm:intel_disable_pipe [i915]] disabling pipe C [ 230.916280] [drm:intel_mst_post_disable_dp [i915]] 1 [ 230.922799] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 230.923253] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 230.923293] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 230.923335] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 230.923462] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.923520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.923575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.923624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.923673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.923720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.923769] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.923820] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.923870] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.923919] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.923965] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.924009] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.924091] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.924140] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.924192] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.924543] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.924586] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.924621] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.924628] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.924631] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.924659] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.924682] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.924703] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.924724] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.924743] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.924762] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.924766] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.924785] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.924789] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.924807] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.924826] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.924844] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.924862] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.924884] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.924903] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.924923] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.924941] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.924959] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.924989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 230.925016] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.925086] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 230.925120] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 230.925141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 230.925161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 230.925180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 230.925198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 230.925217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 230.925237] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 230.925258] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 230.925277] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 230.925297] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 230.925315] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 230.925333] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.925356] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 230.925411] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 230.925467] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 230.926984] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 230.927012] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 230.927039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 230.927067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 230.943982] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 230.944001] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 230.960900] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 230.962960] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 230.963156] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 230.964262] [drm:intel_enable_pipe [i915]] enabling pipe C [ 230.964289] [drm:intel_mst_enable_dp [i915]] 1 [ 230.966680] [drm:drm_dp_update_payload_part2] payload 0 1 [ 230.968060] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.968084] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.968138] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 230.968676] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 230.969245] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 230.969271] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 230.969302] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 230.969785] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 230.969809] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 230.969847] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 230.969929] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 230.969946] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 230.981315] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 230.981347] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 230.981424] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 230.981435] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 230.981439] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 230.981483] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 230.981526] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 230.981557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 230.981583] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 230.981607] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 230.981630] [drm:intel_dump_pipe_config [i915]] requested mode: [ 230.981638] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.981660] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 230.981665] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 230.981689] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 230.981712] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 230.981735] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 230.981757] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 230.981784] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 230.981808] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 230.981833] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 230.981855] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 230.981878] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 230.981917] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 230.981953] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 230.997924] [drm:intel_mst_disable_dp [i915]] 1 [ 230.997931] [drm:drm_dp_update_payload_part1] [ 230.999473] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 230.999528] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 230.999641] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.000367] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.002364] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.002448] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.002736] [drm:drm_dp_update_payload_part1] removing payload 0 [ 231.002791] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 231.002847] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 231.002928] [drm:intel_disable_pipe [i915]] disabling pipe C [ 231.016438] [drm:intel_mst_post_disable_dp [i915]] 1 [ 231.021197] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 231.021758] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 231.021798] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 231.021841] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 231.021897] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.021934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.021969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.022002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.022043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.022085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.022126] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.022171] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.022214] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.022257] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.022298] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.022338] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.022826] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.022869] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.022919] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.023318] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.023376] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.023445] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.023553] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.023557] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.023599] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.023640] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.023931] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.023957] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.023982] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.024005] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.024010] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.024032] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.024036] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.024059] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.024080] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.024102] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.024123] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.024149] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.024170] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.024193] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.024214] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.024234] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.024272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 231.024303] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.024926] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 231.024968] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.024994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.025019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.025053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.025090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.025128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.025168] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.025208] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.025246] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.025284] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.025319] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.025353] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.025417] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 231.025561] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 231.025625] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 231.027481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 231.027508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 231.027531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 231.027555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 231.044485] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 231.044503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 231.061404] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 231.063473] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 231.063671] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 231.064848] [drm:intel_enable_pipe [i915]] enabling pipe C [ 231.064874] [drm:intel_mst_enable_dp [i915]] 1 [ 231.067265] [drm:drm_dp_update_payload_part2] payload 0 1 [ 231.068639] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.068663] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.068705] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.069243] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.069869] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 231.069900] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 231.069928] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 231.070010] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.070044] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.070081] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.070572] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.070592] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.081944] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.081979] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.082007] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.082012] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.082014] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.082043] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.082071] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.082098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.082126] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.082153] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.082180] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.082185] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.082212] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.082216] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.082243] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.082271] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.082298] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.082325] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.082352] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.082414] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.082458] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.082844] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.082879] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.082931] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 231.082972] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.098531] [drm:intel_mst_disable_dp [i915]] 1 [ 231.098538] [drm:drm_dp_update_payload_part1] [ 231.100079] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.100117] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.100202] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.100841] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.102798] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.102846] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.103149] [drm:drm_dp_update_payload_part1] removing payload 0 [ 231.103194] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 231.103238] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 231.103302] [drm:intel_disable_pipe [i915]] disabling pipe C [ 231.115626] [drm:intel_mst_post_disable_dp [i915]] 1 [ 231.122168] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 231.122765] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 231.122795] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 231.122828] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 231.122871] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.122898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.122924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.122949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.122973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.122996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.123021] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.123047] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.123072] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.123096] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.123119] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.123141] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.123182] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.123208] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.123234] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.123575] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.123626] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.123669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.123678] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.123682] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.123723] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.123764] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.123803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.123843] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.123882] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.123919] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.123927] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.123962] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.123970] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.124007] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.124044] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.124080] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.124117] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.124158] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.124195] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.124233] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.124270] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.124307] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.124371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 231.124435] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.124549] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 231.124600] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.124634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.124669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.124702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.124734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.124766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.124800] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.124835] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.124870] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.124904] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.124936] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.124967] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.125004] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 231.125038] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 231.125096] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 231.126619] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 231.126644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 231.126667] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 231.126689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 231.143615] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 231.143633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 231.160532] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 231.162593] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 231.162788] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 231.163892] [drm:intel_enable_pipe [i915]] enabling pipe C [ 231.163918] [drm:intel_mst_enable_dp [i915]] 1 [ 231.166310] [drm:drm_dp_update_payload_part2] payload 0 1 [ 231.167690] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.167713] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.167764] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.168302] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.168868] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 231.168892] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 231.168921] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 231.168988] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.169011] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.169064] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.169564] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.169590] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.180955] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.180990] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.181018] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.181023] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.181025] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.181051] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.181077] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.181101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.181125] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.181147] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.181168] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.181173] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.181194] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.181198] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.181220] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.181241] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.181261] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.181281] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.181305] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.181326] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.181348] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.181420] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.181456] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.181509] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 231.181549] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.197572] [drm:intel_mst_disable_dp [i915]] 1 [ 231.197578] [drm:drm_dp_update_payload_part1] [ 231.199114] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.199162] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.199250] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.199900] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.201804] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.201856] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.202167] [drm:drm_dp_update_payload_part1] removing payload 0 [ 231.202217] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 231.202264] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 231.202333] [drm:intel_disable_pipe [i915]] disabling pipe C [ 231.214731] [drm:intel_mst_post_disable_dp [i915]] 1 [ 231.221062] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 231.221512] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 231.221561] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 231.221609] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 231.221681] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.221730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.221773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.221812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.221855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.221897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.221941] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.221985] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.222025] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.222070] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.222111] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.222152] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.222222] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.222267] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.222315] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.222700] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.222741] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.222771] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.222778] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.222781] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.222814] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.222848] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.222880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.222908] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.222935] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.222965] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.222972] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.223001] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.223007] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.223037] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.223063] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.223093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.223122] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.223155] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.223182] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.223210] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.223239] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.223267] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.223315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 231.223353] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.223479] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 231.223528] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.223559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.223588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.223620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.223650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.223680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.223709] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.223738] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.223771] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.223803] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.223833] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.223860] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.223891] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 231.223923] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 231.223977] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 231.225504] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 231.225537] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 231.225567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 231.225597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 231.242529] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 231.242546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 231.259444] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 231.261485] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 231.261685] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 231.262832] [drm:intel_enable_pipe [i915]] enabling pipe C [ 231.262858] [drm:intel_mst_enable_dp [i915]] 1 [ 231.265267] [drm:drm_dp_update_payload_part2] payload 0 1 [ 231.266641] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.266664] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.266718] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.267258] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.267845] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 231.267867] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 231.267895] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 231.267959] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.267981] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.268033] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.268548] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.268566] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.279884] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.279921] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.279950] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.279956] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.279958] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.279984] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.280011] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.280041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.280071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.280101] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.280130] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.280135] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.280164] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.280169] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.280199] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.280229] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.280258] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.280287] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.280318] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.280346] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.280421] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.280463] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.280501] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.280558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 231.280601] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.296530] [drm:intel_mst_disable_dp [i915]] 1 [ 231.296537] [drm:drm_dp_update_payload_part1] [ 231.298069] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.298109] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.298201] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.298837] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.300727] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.300777] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.301075] [drm:drm_dp_update_payload_part1] removing payload 0 [ 231.301119] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 231.301162] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 231.301225] [drm:intel_disable_pipe [i915]] disabling pipe C [ 231.314660] [drm:intel_mst_post_disable_dp [i915]] 1 [ 231.319548] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 231.319976] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 231.320009] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 231.320044] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 231.320090] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.320121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.320150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.320176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.320202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.320227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.320255] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.320284] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.320311] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.320339] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.320421] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.320589] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.320663] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.320709] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.320757] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.321153] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.321206] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.321249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.321258] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.321263] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.321306] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.321350] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.321415] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.321455] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.321494] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.321531] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.321544] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.321583] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.321593] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.321633] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.321672] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.321712] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.321752] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.321797] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.321837] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.321879] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.321921] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.321960] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.322023] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 231.322074] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.322213] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 231.322274] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.322315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.322356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.322417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.322456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.322496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.322537] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.322582] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.322625] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.322668] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.322705] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.322741] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.322784] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 231.322824] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 231.322896] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 231.324969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 231.325004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 231.325039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 231.325074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 231.342050] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 231.342069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 231.358969] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 231.361027] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 231.361220] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 231.362388] [drm:intel_enable_pipe [i915]] enabling pipe C [ 231.362416] [drm:intel_mst_enable_dp [i915]] 1 [ 231.364817] [drm:drm_dp_update_payload_part2] payload 0 1 [ 231.366202] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.366225] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.366267] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.366810] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.367489] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 231.367514] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 231.367545] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 231.367628] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.367653] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.367693] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.368091] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.368108] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.379556] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.379591] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.379620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.379626] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.379628] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.379658] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.379686] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.379715] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.379743] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.379771] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.379799] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.379804] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.379831] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.379835] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.379864] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.379892] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.379920] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.379947] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.379975] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.380002] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.380031] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.380059] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.380087] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.380127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 231.380161] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.396101] [drm:intel_mst_disable_dp [i915]] 1 [ 231.396107] [drm:drm_dp_update_payload_part1] [ 231.397646] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.397694] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.397809] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.398492] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.400475] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.400527] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.400830] [drm:drm_dp_update_payload_part1] removing payload 0 [ 231.400876] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 231.400923] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 231.400993] [drm:intel_disable_pipe [i915]] disabling pipe C [ 231.413361] [drm:intel_mst_post_disable_dp [i915]] 1 [ 231.419251] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 231.419864] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 231.419903] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 231.419944] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 231.419995] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.420030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.420063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.420093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.420124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.420152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.420184] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.420217] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.420249] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.420280] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.420309] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.420337] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.420468] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.420516] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.420566] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.420931] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.420973] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.421006] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.421013] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.421016] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.421048] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.421080] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.421112] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.421142] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.421171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.421199] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.421207] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.421234] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.421240] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.421269] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.421307] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.421346] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.421422] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.421476] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.421523] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.421573] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.421620] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.421667] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.421740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 231.421799] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.421956] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 231.422025] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.422071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.422115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.422158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.422202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.422245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.422289] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.422336] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.422410] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.422460] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.422506] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.422551] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.422603] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 231.422651] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 231.422732] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 231.424314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 231.424350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 231.424437] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 231.424486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 231.441369] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 231.441387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 231.458217] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 231.459404] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 231.459600] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 231.460757] [drm:intel_enable_pipe [i915]] enabling pipe C [ 231.460782] [drm:intel_mst_enable_dp [i915]] 1 [ 231.462721] [drm:drm_dp_update_payload_part2] payload 0 1 [ 231.464095] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.464118] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.464172] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.464734] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.465302] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 231.465328] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 231.465382] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 231.465456] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.465483] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.465528] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.465997] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.466021] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.477759] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.477788] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.477811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.477815] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.477817] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.477838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.477859] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.477879] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.477898] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.477916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.477933] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.477937] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.477955] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.477958] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.477976] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.477993] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.478011] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.478027] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.478047] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.478065] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.478083] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.478100] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.478117] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.478146] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 231.478169] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.494420] [drm:intel_mst_disable_dp [i915]] 1 [ 231.494426] [drm:drm_dp_update_payload_part1] [ 231.495965] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.496000] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.496088] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.496708] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.498697] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.498745] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.499055] [drm:drm_dp_update_payload_part1] removing payload 0 [ 231.499100] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 231.499144] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 231.499207] [drm:intel_disable_pipe [i915]] disabling pipe C [ 231.512707] [drm:intel_mst_post_disable_dp [i915]] 1 [ 231.518084] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 231.518528] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 231.518565] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 231.518613] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 231.518660] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.518691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.518720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.518747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.518787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.518812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.518840] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.518870] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.518899] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.518928] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.518954] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.518979] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.519026] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.519054] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.519084] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.519325] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.519409] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.519456] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.519468] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.519474] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.519518] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.519563] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.519606] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.519649] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.519689] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.519729] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.519741] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.519779] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.519789] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.519828] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.519868] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.519906] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.519944] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.519988] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.520027] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.520066] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.520103] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.520141] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.520203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 231.520252] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.520396] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 231.520460] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.520502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.520542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.520581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.520620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.520659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.520698] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.520740] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.520780] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.520821] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.520860] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.520897] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.520940] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 231.520981] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 231.521051] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 231.522656] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 231.522706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 231.522748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 231.522794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 231.539756] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 231.539775] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 231.556673] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 231.558735] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 231.558932] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 231.560046] [drm:intel_enable_pipe [i915]] enabling pipe C [ 231.560071] [drm:intel_mst_enable_dp [i915]] 1 [ 231.562472] [drm:drm_dp_update_payload_part2] payload 0 1 [ 231.563855] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.563879] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.563932] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.564473] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.565052] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 231.565076] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 231.565105] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 231.565170] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.565192] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.565244] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.565741] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.565758] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.577136] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.577173] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.577201] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.577206] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.577209] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.577235] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.577261] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.577286] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.577310] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.577332] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.577412] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.577625] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.577765] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.577770] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.577794] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.577817] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.577840] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.577862] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.577887] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.577909] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.577935] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.577958] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.577981] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.578019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 231.578048] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.593704] [drm:intel_mst_disable_dp [i915]] 1 [ 231.593710] [drm:drm_dp_update_payload_part1] [ 231.595243] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.595280] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.595350] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.595982] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.597866] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.597914] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.598212] [drm:drm_dp_update_payload_part1] removing payload 0 [ 231.598253] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 231.598293] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 231.598354] [drm:intel_disable_pipe [i915]] disabling pipe C [ 231.610668] [drm:intel_mst_post_disable_dp [i915]] 1 [ 231.616589] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 231.617050] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 231.617093] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 231.617137] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 231.617195] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.617234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.617271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.617306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.617340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.617450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.617507] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.617565] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.617618] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.617675] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.617726] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.617774] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.617862] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.617921] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.617975] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.618460] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.618520] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.618557] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.618565] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.618568] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.618604] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.618640] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.618674] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.618707] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.618738] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.618768] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.618775] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.618805] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.618811] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.618841] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.618872] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.618902] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.618931] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.618966] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.618996] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.619027] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.619057] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.619086] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.619136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 231.619178] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.619289] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 231.619339] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.619435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.619486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.619534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.619582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.619627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.619676] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.619726] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.619775] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.619827] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.619874] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.619918] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.619970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 231.620019] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 231.620105] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 231.621676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 231.621694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 231.621711] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 231.621727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 231.638643] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 231.638661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 231.655560] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 231.657620] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 231.657817] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 231.658970] [drm:intel_enable_pipe [i915]] enabling pipe C [ 231.658995] [drm:intel_mst_enable_dp [i915]] 1 [ 231.661388] [drm:drm_dp_update_payload_part2] payload 0 1 [ 231.662761] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.662784] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.662827] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.663394] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.663953] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 231.663976] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 231.664004] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 231.664067] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.664089] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.664139] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.664650] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.664670] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.676099] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.676134] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.676160] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.676165] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.676167] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.676192] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.676217] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.676240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.676263] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.676284] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.676305] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.676310] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.676330] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.676380] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.676418] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.676455] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.676491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.676524] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.676561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.676600] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.676637] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.676674] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.676706] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.676762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 231.676807] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.692765] [drm:intel_mst_disable_dp [i915]] 1 [ 231.692773] [drm:drm_dp_update_payload_part1] [ 231.694317] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.694365] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.694462] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.695102] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.697053] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.697108] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.697422] [drm:drm_dp_update_payload_part1] removing payload 0 [ 231.697486] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 231.697558] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 231.697656] [drm:intel_disable_pipe [i915]] disabling pipe C [ 231.710029] [drm:intel_mst_post_disable_dp [i915]] 1 [ 231.716714] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 231.717192] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 231.717238] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 231.717287] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 231.717349] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.717483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.717545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.717608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.717668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.717724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.717781] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.717841] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.717900] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.717955] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.718007] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.718060] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.718155] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.718212] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.718273] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.718655] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.718687] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.718711] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.718716] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.718718] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.718741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.718765] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.718787] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.718809] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.718829] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.718850] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.718854] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.718874] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.718878] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.718898] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.718918] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.718937] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.718955] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.718978] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.718997] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.719018] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.719037] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.719056] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.719094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 231.719127] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.719207] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 231.719249] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.719277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.719304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.719331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.719392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.719429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.719466] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.719504] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.719539] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.719574] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.719607] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.719640] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.719677] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 231.719712] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 231.719772] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 231.721294] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 231.721312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 231.721328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 231.721373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 231.738277] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 231.738297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 231.755207] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 231.757260] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 231.757456] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 231.758704] [drm:intel_enable_pipe [i915]] enabling pipe C [ 231.758730] [drm:intel_mst_enable_dp [i915]] 1 [ 231.761123] [drm:drm_dp_update_payload_part2] payload 0 1 [ 231.762499] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.762523] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.762566] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.763105] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.763677] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 231.763703] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 231.763734] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 231.763807] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.763830] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.763872] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.764385] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.764403] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.775732] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.775758] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.775777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.775780] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.775782] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.775800] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.775818] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.775835] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.775851] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.775866] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.775881] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.775884] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.775899] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.775902] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.775916] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.775931] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.775945] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.775959] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.775976] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.775991] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.776006] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.776021] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.776035] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.776059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 231.776079] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.792338] [drm:intel_mst_disable_dp [i915]] 1 [ 231.792358] [drm:drm_dp_update_payload_part1] [ 231.793897] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.793937] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.794022] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.794632] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.796447] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.796490] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.796796] [drm:drm_dp_update_payload_part1] removing payload 0 [ 231.796838] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 231.796880] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 231.796939] [drm:intel_disable_pipe [i915]] disabling pipe C [ 231.810742] [drm:intel_mst_post_disable_dp [i915]] 1 [ 231.815118] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 231.815648] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 231.815690] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 231.815735] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 231.815793] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.815833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.815871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.815907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.815941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.815975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.816010] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.816048] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.816083] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.816118] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.816151] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.816183] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.816242] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.816277] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.816314] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.816730] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.816778] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.816817] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.816827] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.816831] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.816868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.816907] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.816943] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.816978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.817013] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.817046] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.817056] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.817088] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.817095] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.817127] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.817160] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.817192] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.817224] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.817262] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.817296] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.817330] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.817395] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.817424] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.817470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 231.817506] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.817595] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 231.817630] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.817650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.817670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.817689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.817707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.817725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.817744] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.817764] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.817783] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.817802] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.817820] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.817836] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.817858] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 231.817878] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 231.817912] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 231.819407] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 231.819428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 231.819448] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 231.819468] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 231.836390] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 231.836407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 231.853300] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 231.855369] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 231.855567] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 231.856694] [drm:intel_enable_pipe [i915]] enabling pipe C [ 231.856718] [drm:intel_mst_enable_dp [i915]] 1 [ 231.859109] [drm:drm_dp_update_payload_part2] payload 0 1 [ 231.860478] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.860499] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.860600] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.861136] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.861721] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 231.861748] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 231.861782] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 231.861851] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.861878] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.861927] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.862423] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.862452] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.873674] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.873702] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.873722] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.873726] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.873728] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.873748] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.873767] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.873786] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.873804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.873821] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.873837] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.873841] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.873862] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.873866] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.873888] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.873910] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.873932] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.873954] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.873976] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.873997] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.874020] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.874042] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.874064] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.874096] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 231.874121] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.890325] [drm:intel_mst_disable_dp [i915]] 1 [ 231.890359] [drm:drm_dp_update_payload_part1] [ 231.891892] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.891931] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.891984] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.892567] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.894410] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.894453] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.894772] [drm:drm_dp_update_payload_part1] removing payload 0 [ 231.894820] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 231.894864] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 231.894925] [drm:intel_disable_pipe [i915]] disabling pipe C [ 231.908607] [drm:intel_mst_post_disable_dp [i915]] 1 [ 231.913384] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 231.913821] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 231.913857] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 231.913896] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 231.913948] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.913984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.914017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.914048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.914078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.914107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.914138] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.914171] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.914201] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.914232] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.914260] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.914287] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.914343] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.914453] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.914507] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.914898] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.914934] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.914964] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.914969] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.914972] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.915001] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.915031] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.915059] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.915086] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.915112] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.915136] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.915142] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.915167] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.915172] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.915197] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.915221] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.915246] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.915270] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.915299] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.915324] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.915402] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.915445] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.915486] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.915550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 231.915601] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.915741] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 231.915801] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 231.915843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 231.915883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 231.915922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 231.915960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 231.915998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 231.916037] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 231.916079] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 231.916119] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 231.916160] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 231.916197] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 231.916235] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.916278] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 231.916319] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 231.916411] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 231.917975] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 231.918005] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 231.918035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 231.918071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 231.935045] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 231.935062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 231.951960] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 231.954017] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 231.954210] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 231.955296] [drm:intel_enable_pipe [i915]] enabling pipe C [ 231.955322] [drm:intel_mst_enable_dp [i915]] 1 [ 231.957729] [drm:drm_dp_update_payload_part2] payload 0 1 [ 231.959131] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.959154] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.959204] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.959753] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.960333] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 231.960379] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 231.960420] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 231.960495] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 231.960526] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 231.960572] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 231.961037] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.961058] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.972415] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 231.972451] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 231.972479] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 231.972484] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 231.972486] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 231.972513] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.972541] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 231.972566] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 231.972592] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 231.972616] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.972639] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.972644] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.972667] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.972672] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 231.972695] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 231.972717] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 231.972739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.972761] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.972787] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 231.972809] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.972833] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 231.972855] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 231.972877] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 231.972914] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 231.972945] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 231.989022] [drm:intel_mst_disable_dp [i915]] 1 [ 231.989030] [drm:drm_dp_update_payload_part1] [ 231.990586] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 231.990645] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 231.990763] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 231.991477] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 231.993511] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 231.993576] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 231.993877] [drm:drm_dp_update_payload_part1] removing payload 0 [ 231.993929] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 231.993982] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 231.994062] [drm:intel_disable_pipe [i915]] disabling pipe C [ 232.007517] [drm:intel_mst_post_disable_dp [i915]] 1 [ 232.013038] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 232.013462] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 232.013491] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 232.013533] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 232.013596] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 232.013638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 232.013672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 232.013697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 232.013721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 232.013743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 232.013768] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 232.013794] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 232.013818] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 232.013842] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 232.013864] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 232.013885] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.013926] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 232.013950] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 232.013975] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.014190] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 232.014220] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 232.014244] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 232.014250] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 232.014252] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 232.014275] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 232.014305] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 232.014334] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 232.014425] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 232.014463] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 232.014498] [drm:intel_dump_pipe_config [i915]] requested mode: [ 232.014510] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.014543] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 232.014551] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.014585] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 232.014619] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 232.014653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 232.014687] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 232.014726] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 232.014760] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 232.014796] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 232.014832] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 232.014866] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 232.014921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 232.014963] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 232.015070] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 232.015123] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 232.015157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 232.015190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 232.015223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 232.015256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 232.015289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 232.015323] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 232.015391] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 232.015426] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 232.015460] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 232.015493] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 232.015524] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.015560] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 232.015594] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 232.015656] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 232.017474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 232.017502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 232.017526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 232.017550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 232.036667] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 232.036686] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 232.055787] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 232.057840] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 232.058311] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 232.062109] [drm:intel_enable_pipe [i915]] enabling pipe C [ 232.062136] [drm:intel_mst_enable_dp [i915]] 1 [ 232.066685] [drm:drm_dp_update_payload_part2] payload 0 1 [ 232.068053] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 232.068075] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 232.068107] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 232.070766] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 232.073458] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 232.073489] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 232.073525] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 232.073631] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 232.073661] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 232.073708] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.076551] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 232.076574] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 232.079216] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 232.079248] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 232.079270] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 232.079275] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 232.079277] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 232.079298] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 232.079320] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 232.079340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 232.079395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 232.079424] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 232.079452] [drm:intel_dump_pipe_config [i915]] requested mode: [ 232.079460] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.079488] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 232.079494] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.079521] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 232.079548] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 232.079574] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 232.079602] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 232.079623] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 232.079641] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 232.079661] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 232.079678] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 232.079695] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 232.079727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 232.079751] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 232.095846] [drm:intel_mst_disable_dp [i915]] 1 [ 232.095852] [drm:drm_dp_update_payload_part1] [ 232.097376] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 232.097405] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 232.097482] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 232.100249] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 232.107151] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 232.107190] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 232.109718] [drm:drm_dp_update_payload_part1] removing payload 0 [ 232.109759] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 232.109802] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 232.109864] [drm:intel_disable_pipe [i915]] disabling pipe C [ 232.113984] [drm:intel_mst_post_disable_dp [i915]] 1 [ 232.127078] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 232.128081] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 232.128112] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 232.128143] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 232.128187] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 232.128215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 232.128241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 232.128266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 232.128290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 232.128313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 232.128338] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 232.128433] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 232.128471] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 232.128509] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 232.128543] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 232.128576] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.128639] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 232.128676] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 232.128718] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.128995] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 232.129027] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 232.129053] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 232.129059] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 232.129061] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 232.129087] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 232.129114] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 232.129139] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 232.129164] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 232.129191] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 232.129222] [drm:intel_dump_pipe_config [i915]] requested mode: [ 232.129228] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.129258] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 232.129263] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.129294] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 232.129325] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 232.129395] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 232.129435] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 232.129474] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 232.129510] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 232.129549] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 232.129584] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 232.129618] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 232.129675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 232.129720] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 232.129846] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 232.129901] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 232.129939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 232.129974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 232.130009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 232.130044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 232.130080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 232.130116] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 232.130154] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 232.130190] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 232.130227] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 232.130262] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 232.130294] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.130333] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 232.130388] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 232.130453] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 232.132263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 232.132283] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 232.132300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 232.132318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 232.149272] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 232.149289] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 232.166191] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 232.168266] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 232.168466] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 232.169650] [drm:intel_enable_pipe [i915]] enabling pipe C [ 232.169677] [drm:intel_mst_enable_dp [i915]] 1 [ 232.172068] [drm:drm_dp_update_payload_part2] payload 0 1 [ 232.173447] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 232.173468] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 232.173526] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 232.174073] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 232.174660] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 232.174690] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 232.174726] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 232.174807] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 232.174849] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 232.174898] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.175383] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 232.175416] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 232.186730] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 232.186763] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 232.186789] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 232.186794] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 232.186797] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 232.186821] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 232.186846] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 232.186869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 232.186892] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 232.186914] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 232.186935] [drm:intel_dump_pipe_config [i915]] requested mode: [ 232.186940] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.186961] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 232.186966] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.186987] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 232.187007] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 232.187027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 232.187047] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 232.187072] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 232.187092] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 232.187113] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 232.187134] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 232.187154] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 232.187188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 232.187217] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 232.203348] [drm:intel_mst_disable_dp [i915]] 1 [ 232.203379] [drm:drm_dp_update_payload_part1] [ 232.204907] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 232.204943] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 232.205030] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 232.205663] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 232.207787] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 232.207842] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 232.208150] [drm:drm_dp_update_payload_part1] removing payload 0 [ 232.208199] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 232.208248] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 232.208321] [drm:intel_disable_pipe [i915]] disabling pipe C [ 232.220765] [drm:intel_mst_post_disable_dp [i915]] 1 [ 232.226564] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 232.226992] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 232.227025] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 232.227061] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 232.227108] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 232.227139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 232.227168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 232.227195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 232.227222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 232.227247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 232.227275] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 232.227304] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 232.227331] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 232.227412] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 232.227454] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 232.227493] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.227567] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 232.227613] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 232.227661] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.227956] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 232.227992] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 232.228021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 232.228027] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 232.228030] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 232.228058] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 232.228086] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 232.228113] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 232.228140] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 232.228166] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 232.228190] [drm:intel_dump_pipe_config [i915]] requested mode: [ 232.228196] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.228220] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 232.228226] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.228251] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 232.228276] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 232.228300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 232.228324] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 232.228393] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 232.228423] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 232.228455] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 232.228486] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 232.228516] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 232.228566] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 232.228608] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 232.228721] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 232.228774] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 232.228809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 232.228842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 232.228869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 232.228891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 232.228911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 232.228933] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 232.228955] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 232.228977] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 232.228999] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 232.229021] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 232.229040] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.229064] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 232.229086] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 232.229124] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 232.230652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 232.230676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 232.230697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 232.230719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 232.247642] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 232.247659] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 232.264557] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 232.266625] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 232.266824] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 232.267985] [drm:intel_enable_pipe [i915]] enabling pipe C [ 232.268010] [drm:intel_mst_enable_dp [i915]] 1 [ 232.270413] [drm:drm_dp_update_payload_part2] payload 0 1 [ 232.271782] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 232.271804] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 232.271858] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 232.272396] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 232.272968] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 232.272991] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 232.273020] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 232.273084] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 232.273106] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 232.273157] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.273658] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 232.273675] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 232.285073] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 232.285106] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 232.285131] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 232.285136] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 232.285138] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 232.285162] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 232.285185] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 232.285208] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 232.285229] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 232.285250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 232.285269] [drm:intel_dump_pipe_config [i915]] requested mode: [ 232.285274] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.285294] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 232.285298] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.285319] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 232.285338] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 232.285407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 232.285437] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 232.285472] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 232.285502] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 232.285536] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 232.285569] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 232.285601] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 232.285652] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 232.285681] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 232.301770] [drm:intel_mst_disable_dp [i915]] 1 [ 232.301779] [drm:drm_dp_update_payload_part1] [ 232.303330] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 232.303383] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 232.303489] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 232.304258] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 232.306278] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 232.306337] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 232.306651] [drm:drm_dp_update_payload_part1] removing payload 0 [ 232.306711] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 232.306764] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 232.306838] [drm:intel_disable_pipe [i915]] disabling pipe C [ 232.319245] [drm:intel_mst_post_disable_dp [i915]] 1 [ 232.325630] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 232.326083] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 232.326123] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 232.326166] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 232.326221] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 232.326258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 232.326293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 232.326326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 232.326437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 232.326490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 232.326544] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 232.326600] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 232.326654] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 232.326718] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 232.326756] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 232.326793] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.326859] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 232.326899] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 232.326943] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.327303] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 232.327354] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 232.327424] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 232.327434] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 232.327438] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 232.327480] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 232.327521] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 232.327560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 232.327599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 232.327637] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 232.327673] [drm:intel_dump_pipe_config [i915]] requested mode: [ 232.327681] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.327717] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 232.327725] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.327761] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 232.327794] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 232.327826] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 232.327858] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 232.327896] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 232.327930] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 232.327970] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 232.328006] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 232.328041] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 232.328100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 232.328146] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 232.328274] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 232.328332] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 232.328398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 232.328437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 232.328475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 232.328512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 232.328549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 232.328588] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 232.328629] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 232.328668] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 232.328708] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 232.328744] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 232.328779] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.328820] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 232.328861] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 232.328925] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 232.330547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 232.330565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 232.330581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 232.330598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 232.347514] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 232.347532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 232.364431] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 232.366501] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 232.366699] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 232.367851] [drm:intel_enable_pipe [i915]] enabling pipe C [ 232.367877] [drm:intel_mst_enable_dp [i915]] 1 [ 232.370283] [drm:drm_dp_update_payload_part2] payload 0 1 [ 232.371681] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 232.371704] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 232.371735] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 232.372266] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 232.372837] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 232.372860] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 232.372889] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 232.372956] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 232.372978] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 232.373030] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.373536] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 232.373559] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 232.384981] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 232.385013] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 232.385039] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 232.385044] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 232.385046] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 232.385073] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 232.385099] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 232.385125] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 232.385151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 232.385177] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 232.385202] [drm:intel_dump_pipe_config [i915]] requested mode: [ 232.385206] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.385232] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 232.385236] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.385262] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 232.385288] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 232.385313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 232.385339] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 232.385404] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 232.385439] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 232.385473] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 232.385506] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 232.385539] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 232.385589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 232.385629] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 232.401553] [drm:intel_mst_disable_dp [i915]] 1 [ 232.401559] [drm:drm_dp_update_payload_part1] [ 232.403085] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 232.403119] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 232.403202] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 232.403865] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 232.405848] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 232.405905] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 232.406196] [drm:drm_dp_update_payload_part1] removing payload 0 [ 232.406247] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 232.406296] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 232.407116] [drm:intel_disable_pipe [i915]] disabling pipe C [ 232.418439] [drm:intel_mst_post_disable_dp [i915]] 1 [ 232.425730] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 232.426181] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 232.426220] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 232.426263] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 232.426318] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 232.426411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 232.426469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 232.426521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 232.426568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 232.426615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 232.426664] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 232.426717] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 232.426767] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 232.426817] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 232.426862] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 232.426908] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.426992] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 232.427041] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 232.427095] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.427510] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 232.427559] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 232.427599] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 232.427609] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 232.427615] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 232.427652] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 232.427690] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 232.427726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 232.427763] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 232.427796] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 232.427828] [drm:intel_dump_pipe_config [i915]] requested mode: [ 232.427838] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.427871] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 232.427880] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.427913] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 232.427944] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 232.427977] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 232.428007] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 232.428042] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 232.428071] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 232.428102] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:70, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 232.428132] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 232.428161] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 232.428211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 232.428253] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 232.428396] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 0 kHz, ref 0 kHz [ 232.428440] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz [ 232.428467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 232.428495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 232.428521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 232.428546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 232.428572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 232.428599] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 232.428626] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 232.428653] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 232.428680] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 232.428705] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 232.428729] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.428759] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 4, on? 0) for crtc 46 [ 232.428786] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 232.428833] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 232.430309] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 232.430325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 232.430371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 232.430393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 232.447316] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 232.447334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 232.464258] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 232.466327] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 232.466539] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=1908 slots=48 [ 232.467750] [drm:intel_enable_pipe [i915]] enabling pipe C [ 232.467776] [drm:intel_mst_enable_dp [i915]] 1 [ 232.470169] [drm:drm_dp_update_payload_part2] payload 0 1 [ 232.471539] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 232.471560] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 232.471618] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 232.472170] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 232.472768] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:56:DP-MST C] [ 232.472798] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD [ 232.472834] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 232.472914] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 232.472956] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 232.473004] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.473497] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 232.473533] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 232.484781] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 232.484813] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 232.484837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 232.484842] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=48, avail=63 [ 232.484843] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=15 [ 232.484867] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 232.484890] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset] [ 232.484911] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 [ 232.484932] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 48 [ 232.484951] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 232.484970] [drm:intel_dump_pipe_config [i915]] requested mode: [ 232.484974] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.484993] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 232.484997] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 [ 232.485016] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 232.485034] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 232.485053] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 232.485071] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 232.485092] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 232.485117] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 232.485144] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:66, fb = 3840x2160 format = XR24 little-endian (0x34325258) [ 232.485170] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0 [ 232.485195] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0 [ 232.485233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz [ 232.485263] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe C [ 232.501477] [drm:intel_mst_disable_dp [i915]] 1 [ 232.501485] [drm:drm_dp_update_payload_part1] [ 232.503042] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 232.503093] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 232.503201] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 232.503937] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 232.506050] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 232.506105] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 232.506414] [drm:drm_dp_update_payload_part1] removing payload 0 [ 232.506488] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C [ 232.506564] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 232.506671] [drm:intel_disable_pipe [i915]] disabling pipe C [ 232.518400] [drm:intel_mst_post_disable_dp [i915]] 1 [ 232.525099] [drm:drm_dp_mst_put_payload_id.part.5] putting payload 1 [ 232.525677] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 2700 (active 4, on? 1) for crtc 46 [ 232.525714] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 2700 [ 232.525751] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz [ 232.525801] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz [ 232.525835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 232.525866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 232.525895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 232.525924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 232.525952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 232.525981] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 232.526012] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 232.526041] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 232.526070] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 232.526096] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 232.526122] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.526170] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 232.526199] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 232.526231] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.526934] [drm:drm_dp_atomic_release_vcpi_slots] vcpi slots released=48, avail=63 [ 232.527019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 232.527135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 232.527185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 232.527229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 232.527275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 232.527321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 232.527407] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 232.527453] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 232.527506] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 232.527554] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 232.527602] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 232.527644] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 232.527686] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.527751] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C] [ 232.532284] [IGT] kms_flip: exiting, ret=0 [ 232.565274] [drm:intel_atomic_check [i915]] [CONNECTOR:60:DP-2] checking for sink bpp constrains [ 232.565309] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 [ 232.565342] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots req=8, avail=63 [ 232.565344] [drm:drm_dp_atomic_find_vcpi_slots] vcpi slots avail=55 [ 232.565374] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 232.565402] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset] [ 232.565430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 232.565455] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 917504, gmch_n: 8388608, link_m: 152917, link_n: 1048576, tu: 8 [ 232.565481] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 232.565508] [drm:intel_dump_pipe_config [i915]] requested mode: [ 232.565512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 232.565538] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 232.565541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 232.565568] [drm:intel_dump_pipe_config [i915]] crtc timings: 78750 1024 1040 1136 1312 768 769 772 800, type: 0x40 flags: 0x5 [ 232.565594] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 1024x768, pixel rate 78750 [ 232.565620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 232.565645] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0 [ 232.565670] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 232.565695] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 232.565721] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0 [ 232.565746] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0 [ 232.565772] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0 [ 232.565803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 450000 kHz, actual 450000 kHz [ 232.565832] [drm:intel_reference_shared_dpll [i915]] using LCPLL 2700 for pipe A [ 232.566319] [drm:intel_set_cdclk [i915]] Changing CDCLK to 450000 kHz, VCO 0 kHz, ref 0 kHz [ 232.566391] [drm:intel_update_cdclk [i915]] Current CD clock rate: 450000 kHz, VCO: 0 kHz, ref: 0 kHz [ 232.566414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B] [ 232.566435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C] [ 232.566454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A] [ 232.566472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B] [ 232.566490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C] [ 232.566513] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 1 [ 232.566539] [drm:verify_single_dpll_state.isra.76 [i915]] WRPLL 2 [ 232.566563] [drm:verify_single_dpll_state.isra.76 [i915]] SPLL [ 232.566588] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 810 [ 232.566611] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 1350 [ 232.566635] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.566668] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 2700 (active 1, on? 0) for crtc 32 [ 232.566695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 2700 [ 232.566739] [drm:intel_mst_pre_enable_dp [i915]] 0 [ 232.568427] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 232.568449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 232.568468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 232.568488] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 232.585412] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 232.585428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 232.602325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 232.604411] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 232.604617] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=282 slots=8 [ 232.605788] [drm:intel_enable_pipe [i915]] enabling pipe A [ 232.605833] [drm:intel_mst_enable_dp [i915]] 1 [ 232.608244] [drm:drm_dp_update_payload_part2] payload 0 1 [ 232.609645] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040 [ 232.609669] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short [ 232.609743] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short [ 232.610284] [drm:intel_dp_check_mst_status [i915]] got esi 01 10 00 [ 232.610878] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:60:DP-2], [ENCODER:54:DP-MST A] [ 232.610904] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD [ 232.610953] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 232.611200] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1 [ 232.611253] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 232.611584] [drm:intel_dp_check_mst_status [i915]] got esi2 01 00 00 [ 232.611602] [drm:intel_dp_check_mst_status [i915]] got esi 01 00 00 [ 232.619433] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:DP-2] [ 232.619466] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A] [ 232.619520] [drm:verify_single_dpll_state.isra.76 [i915]] LCPLL 2700 [ 232.619706] Console: switching to colour frame buffer device 128x48 [ 248.278212] Console: switching to colour dummy device 80x25 [ 248.278304] [IGT] kms_flip: executing [ 248.278823] ------------[ cut here ]------------ [ 248.278844] kernel BUG at drivers/gpu/drm/i915/intel_lrc.c:604! [ 248.278864] invalid opcode: 0000 [#1] PREEMPT SMP