diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 9f36d98..dd2cfaa 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1951,10 +1951,13 @@ VkResult radv_BeginCommandBuffer( default: break; } } + cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH; + si_emit_cache_flush(cmd_buffer); + if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) { cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer); cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass); struct radv_subpass *subpass = @@ -2901,10 +2904,13 @@ void radv_CmdDispatch( radeon_emit(cmd_buffer->cs, y); radeon_emit(cmd_buffer->cs, z); radeon_emit(cmd_buffer->cs, 1); assert(cmd_buffer->cs->cdw <= cdw_max); + + cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH; + si_emit_cache_flush(cmd_buffer); radv_cmd_buffer_trace_emit(cmd_buffer); } void radv_CmdDispatchIndirect( VkCommandBuffer commandBuffer, @@ -2954,10 +2960,13 @@ void radv_CmdDispatchIndirect( radeon_emit(cmd_buffer->cs, 0); radeon_emit(cmd_buffer->cs, 1); } assert(cmd_buffer->cs->cdw <= cdw_max); + + cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH; + si_emit_cache_flush(cmd_buffer); radv_cmd_buffer_trace_emit(cmd_buffer); } void radv_unaligned_dispatch( struct radv_cmd_buffer *cmd_buffer, @@ -3011,10 +3020,13 @@ void radv_unaligned_dispatch( radeon_emit(cmd_buffer->cs, blocks[2]); radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) | S_00B800_PARTIAL_TG_EN(1)); assert(cmd_buffer->cs->cdw <= cdw_max); + + cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH; + si_emit_cache_flush(cmd_buffer); radv_cmd_buffer_trace_emit(cmd_buffer); } void radv_CmdEndRenderPass( VkCommandBuffer commandBuffer)