From 0dd679410847efed18072c456689d88630675f65 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 23 Jun 2017 20:14:10 +0300 Subject: [PATCH] drm/i915: Drop the IER tricks from pre-gen5 irq handlers --- drivers/gpu/drm/i915/i915_irq.c | 39 +++------------------------------------ 1 file changed, 3 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 293609384b38..f1f4e7b1a492 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3773,7 +3773,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; u32 pipe_stats[I915_MAX_PIPES] = {}; - u16 iir, ier; + u16 iir; iir = I915_READ16(IIR); if ((iir & ~flip_mask) == 0) @@ -3781,23 +3781,12 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) ret = IRQ_HANDLED; - /* - * Clear IER while we clear the IIR bits to make - * sure we get another edge if not all IIR bits - * end up cleared. - */ - ier = I915_READ16(IER); - I915_WRITE16(IER, 0); - /* Call regardless, as some status bits might not be * signalled in iir */ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); I915_WRITE16(IIR, (iir & ~flip_mask)); - I915_WRITE16(IER, ier); - POSTING_READ16(IER); - if (iir & I915_USER_INTERRUPT) notify_ring(dev_priv->engine[RCS]); @@ -3889,7 +3878,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; u32 pipe_stats[I915_MAX_PIPES] = {}; u32 hotplug_status = 0; - u32 iir, ier; + u32 iir; iir = I915_READ(IIR); if ((iir & ~flip_mask) == 0) @@ -3897,14 +3886,6 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) ret = IRQ_HANDLED; - /* - * Clear IER while we clear the IIR bits to make - * sure we get another edge if not all IIR bits - * end up cleared. - */ - ier = I915_READ(IER); - I915_WRITE(IER, 0); - if (I915_HAS_HOTPLUG(dev_priv) && iir & I915_DISPLAY_PORT_INTERRUPT) hotplug_status = i9xx_hpd_irq_ack(dev_priv); @@ -3915,9 +3896,6 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) I915_WRITE(IIR, iir & ~flip_mask); - I915_WRITE(IER, ier); - POSTING_READ(IER); - if (iir & I915_USER_INTERRUPT) notify_ring(dev_priv->engine[RCS]); @@ -4049,7 +4027,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; u32 pipe_stats[I915_MAX_PIPES] = {}; u32 hotplug_status = 0; - u32 iir, ier; + u32 iir; iir = I915_READ(IIR); if ((iir & ~flip_mask) == 0) @@ -4057,14 +4035,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) ret = IRQ_HANDLED; - /* - * Clear IER while we clear the IIR bits to make - * sure we get another edge if not all IIR bits - * end up cleared. - */ - ier = I915_READ(IER); - I915_WRITE(IER, 0); - if (iir & I915_DISPLAY_PORT_INTERRUPT) hotplug_status = i9xx_hpd_irq_ack(dev_priv); @@ -4074,9 +4044,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) I915_WRITE(IIR, iir & ~flip_mask); - I915_WRITE(IER, ier); - POSTING_READ(IER); - if (iir & I915_USER_INTERRUPT) notify_ring(dev_priv->engine[RCS]); -- 2.13.0