(05:09 AM) [gfx@gfx-desktop] [~]$ : dmesg -w
[  378.833388] Console: switching to colour dummy device 80x25
[  378.833512] [IGT] kms_fbcon_fbt: executing
[  378.846748] [IGT] kms_fbcon_fbt: starting subtest fbc
[  378.847854] Setting dangerous option enable_fbc - tainting kernel
[  378.848182] Setting dangerous option enable_psr - tainting kernel
[  378.848296] Setting dangerous option enable_fbc - tainting kernel
[  378.848344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
[  378.848673] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
[  378.848845] [drm:intel_disable_pipe [i915]] disabling pipe A
[  379.092248] [drm:intel_disable_shared_dpll [i915]] disable PCH DPLL A (active 1, on? 1) for crtc 32
[  379.092389] [drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL A
[  379.092691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:LVDS]
[  379.092771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:CRT]
[  379.092842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:HDMI B]
[  379.092912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP B]
[  379.092980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:HDMI C]
[  379.093230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:HDMI D]
[  379.093360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP C]
[  379.093497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP D]
[  379.093618] [drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:47:LVDS-1]
[  379.093775] [drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
[  379.093904] [drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
[  379.094363] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
[  379.094652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
[  379.096157] [drm:intel_disable_pipe [i915]] disabling pipe B
[  379.106901] [drm:intel_dp_link_down [i915]]
[  379.123087] [drm:intel_disable_shared_dpll [i915]] disable PCH DPLL B (active 2, on? 1) for crtc 39
[  379.123173] [drm:intel_disable_shared_dpll [i915]] disabling PCH DPLL B
[  379.123466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:LVDS]
[  379.123533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:CRT]
[  379.123597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:HDMI B]
[  379.123659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP B]
[  379.123729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:HDMI C]
[  379.123790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:HDMI D]
[  379.123851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP C]
[  379.123910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP D]
[  379.123974] [drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:62:DP-1]
[  379.124212] [drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
[  379.124349] [drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
[  379.124624] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
[  379.124809] [drm:intel_power_well_disable [i915]] disabling always-on
[  379.125353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
[  384.132993] [drm:drm_mode_addfb2] [FB:71]
[  384.135556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
[  384.135588] [drm:drm_mode_setcrtc] [CONNECTOR:47:LVDS-1]
[  384.135684] [drm:intel_atomic_check [i915]] [CONNECTOR:47:LVDS-1] checking for sink bpp constrains
[  384.135716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 18
[  384.135748] [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 1
[  384.135778] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 18, dithering: 1
[  384.135808] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
[  384.135838] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 18, dithering: 1
[  384.135868] [drm:intel_dump_pipe_config [i915]] fdi: lanes: 1; gmch_m: 3844778, gmch_n: 4194304, link_m: 213598, link_n: 524288, tu: 64
[  384.135897] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
[  384.135925] [drm:intel_dump_pipe_config [i915]] requested mode:
[  384.135929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 110000 1600 1664 1706 2010 900 903 906 912 0x48 0xa
[  384.135956] [drm:intel_dump_pipe_config [i915]] adjusted mode:
[  384.135998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60 110000 1600 1664 1706 2010 900 903 906 912 0x48 0xa
[  384.136040] [drm:intel_dump_pipe_config [i915]] crtc timings: 110000 1600 1664 1706 2010 900 903 906 912, type: 0x48 flags: 0xa
[  384.136084] [drm:intel_dump_pipe_config [i915]] port clock: 110000, pipe src size: 1600x900, pixel rate 110000
[  384.136126] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  384.136168] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
[  384.136214] [drm:ibx_dump_hw_state [i915]] dpll_hw_state: dpll: 0x89086008, dpll_md: 0x0, fp0: 0x21106, fp1: 0x21106
[  384.136256] [drm:intel_dump_pipe_config [i915]] planes on this crtc
[  384.136534] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
[  384.136575] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
[  384.136614] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
[  384.136673] [drm:ironlake_crtc_compute_clock [i915]] using SSC reference clock of 120000 kHz
[  384.136750] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated PCH DPLL A
[  384.136791] [drm:intel_reference_shared_dpll [i915]] using PCH DPLL A for pipe A
[  384.138705] [drm:intel_power_well_enable [i915]] enabling always-on
[  384.138743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:LVDS]
[  384.138772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:CRT]
[  384.138801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:HDMI B]
[  384.138828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP B]
[  384.138856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:HDMI C]
[  384.138883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:HDMI D]
[  384.138909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP C]
[  384.138936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP D]
[  384.139003] [drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
[  384.139054] [drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
[  384.139117] [drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL A
[  384.139834] [drm:intel_enable_pipe [i915]] enabling pipe A
[  384.140064] [drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x10
[  384.140115] [drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x110
[  384.140145] [drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
[  384.140180] [drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
[  384.140209] [drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
[  384.140235] [drm:ivb_manual_fdi_link_train [i915]] FDI train done.
[  384.140268] [drm:intel_enable_shared_dpll [i915]] enable PCH DPLL A (active 1, on? 0) for crtc 32
[  384.140297] [drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL A
[  384.143829] [drm:intel_panel_enable_backlight [i915]] pipe A
[  384.143860] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 4438
[  384.175305] [drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:47:LVDS-1]
[  384.175391] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
[  384.175498] [drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
[  389.199528] [IGT] kms_fbcon_fbt: exiting, ret=99
[  389.199669] Setting dangerous option enable_psr - tainting kernel
[  389.199746] Setting dangerous option enable_fbc - tainting kernel
[  389.223399] [drm:intel_atomic_check [i915]] [CONNECTOR:62:DP-1] checking for sink bpp constrains
[  389.223475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
[  389.223542] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
[  389.223608] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
[  389.223668] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
[  389.223730] [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2
[  389.223789] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
[  389.223850] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
[  389.223908] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
[  389.223974] [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
[  389.224038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
[  389.224082] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
[  389.224126] [drm:intel_dump_pipe_config [i915]] requested mode:
[  389.224133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[  389.224177] [drm:intel_dump_pipe_config [i915]] adjusted mode:
[  389.224182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[  389.224227] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
[  389.224271] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
[  389.224315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  389.224357] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
[  389.224430] [drm:ibx_dump_hw_state [i915]] dpll_hw_state: dpll: 0xc4020002, dpll_md: 0x0, fp0: 0x10c09, fp1: 0x10c09
[  389.224484] [drm:intel_dump_pipe_config [i915]] planes on this crtc
[  389.224539] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
[  389.224592] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
[  389.224645] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
[  389.224726] [drm:intel_find_shared_dpll [i915]] [CRTC:39:pipe B] allocated PCH DPLL B
[  389.224785] [drm:intel_reference_shared_dpll [i915]] using PCH DPLL B for pipe B
[  389.225589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:LVDS]
[  389.225652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:CRT]
[  389.225712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:HDMI B]
[  389.225771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP B]
[  389.225828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:HDMI C]
[  389.225885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:HDMI D]
[  389.225942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP C]
[  389.226024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP D]
[  389.226082] [drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL A
[  389.226159] [drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
[  389.226418] [drm:intel_prepare_shared_dpll [i915]] setting up PCH DPLL B
[  389.227290] [drm:intel_enable_pipe [i915]] enabling pipe B
[  389.227523] [drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR before link train 0x10
[  389.227596] [drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x110
[  389.227653] [drm:ivb_manual_fdi_link_train [i915]] FDI train 1 done, level 0.
[  389.227717] [drm:ivb_manual_fdi_link_train [i915]] FDI_RX_IIR 0x600
[  389.227773] [drm:ivb_manual_fdi_link_train [i915]] FDI train 2 done, level 0.
[  389.227826] [drm:ivb_manual_fdi_link_train [i915]] FDI train done.
[  389.227891] [drm:intel_enable_shared_dpll [i915]] enable PCH DPLL B (active 2, on? 0) for crtc 39
[  389.227948] [drm:intel_enable_shared_dpll [i915]] enabling PCH DPLL B
[  389.229488] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
[  389.232311] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
[  389.232374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
[  389.232433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
[  389.232496] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
[  389.235207] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
[  389.235233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
[  389.235256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
[  389.238038] [drm:intel_dp_start_link_train [i915]] clock recovery OK
[  389.238071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
[  389.241185] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
[  389.241219] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:62:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
[  389.274902] [drm:verify_connector_state.isra.69 [i915]] [CONNECTOR:62:DP-1]
[  389.274942] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
[  389.275037] [drm:verify_single_dpll_state.isra.70 [i915]] PCH DPLL B
[  389.279702] Console: switching to colour frame buffer device 200x56