From c18c9d5593c44c37d75301e57c01eefe350079ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 30 Jul 2017 03:37:21 +0200 Subject: [PATCH] radeonsi: add back initialization of constant VGT registers Ported from Vulkan. This would be an issue if there was another UMD that changes the values to something else. --- src/gallium/drivers/radeonsi/si_state.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 534bf7e..48bf895 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -4565,6 +4565,13 @@ static void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0); si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0); si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0); + } else { + /* These registers, when written, also overwrite + * the CLEAR_STATE context, so we can't rely on it. + */ + si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); + si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); + si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0); } if (sctx->b.chip_class >= CIK) { -- 2.7.4