[  155.809190] Console: switching to colour dummy device 80x25
[  155.809242] [IGT] kms_frontbuffer_tracking: executing
[  155.827057] [drm:drm_mode_addfb2] [FB:92]
[  155.827157] [drm:drm_mode_addfb2] [FB:95]
[  155.827250] [drm:drm_mode_addfb2] [FB:96]
[  155.830742] [drm:drm_mode_addfb2] [FB:97]
[  155.847085] [drm:drm_mode_addfb2] [FB:98]
[  155.847791] [IGT] kms_frontbuffer_tracking: starting subtest basic
[  155.853324] [drm:drm_mode_addfb2] [FB:92]
[  155.853401] [drm:drm_mode_addfb2] [FB:95]
[  155.853463] [drm:drm_mode_addfb2] [FB:96]
[  155.855929] [drm:drm_mode_addfb2] [FB:97]
[  155.872621] [drm:drm_mode_addfb2] [FB:98]
[  155.872636] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
[  155.872670] [drm:intel_atomic_check] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
[  155.872714] [drm:intel_dsi_disable]
[  155.872717] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 7 - MIPI_SEQ_BACKLIGHT_OFF
[  155.872719] [drm:mipi_exec_gpio]
[  155.872731] [drm:mipi_exec_delay]
[  155.873875] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
[  155.903767] [drm:intel_dsi_post_disable]
[  155.908992] [drm:intel_disable_dsi_pll]
[  155.909004] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 11 - MIPI_SEQ_POWER_OFF
[  155.909048] [drm:mipi_exec_gpio]
[  155.909067] [drm:__intel_fbc_disable] Disabling FBC on pipe A
[  155.909095] [drm:intel_set_cdclk] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
[  155.909135] [drm:intel_update_cdclk] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
[  155.909141] [drm:intel_atomic_commit_tail] [ENCODER:75:DDI B]
[  155.909145] [drm:intel_atomic_commit_tail] [ENCODER:77:DP-MST A]
[  155.909155] [drm:intel_atomic_commit_tail] [ENCODER:78:DP-MST B]
[  155.909163] [drm:intel_atomic_commit_tail] [ENCODER:79:DP-MST C]
[  155.909166] [drm:intel_atomic_commit_tail] [ENCODER:84:DDI C]
[  155.909169] [drm:intel_atomic_commit_tail] [ENCODER:86:DSI A]
[  155.909174] [drm:intel_dsi_get_hw_state]
[  155.909187] [drm:verify_connector_state.isra.105] [CONNECTOR:87:DSI-1]
[  155.909191] [drm:intel_dsi_get_hw_state]
[  155.909196] [drm:verify_single_dpll_state.isra.106] PORT PLL A
[  155.909201] [drm:verify_single_dpll_state.isra.106] PORT PLL B
[  155.909205] [drm:verify_single_dpll_state.isra.106] PORT PLL C
[  155.909224] [drm:intel_atomic_commit_tail] [CRTC:42:pipe A]
[  155.909316] [drm:drm_mode_setcrtc] [CRTC:58:pipe B]
[  155.909375] [drm:drm_mode_setcrtc] [CRTC:74:pipe C]
[  155.917815] [drm:drm_mode_addfb2] [FB:94]
[  155.925111] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
[  155.925128] [drm:drm_mode_setcrtc] [CONNECTOR:87:DSI-1]
[  155.925173] [drm:intel_modeset_pipe_config] [CONNECTOR:87:DSI-1] checking for sink bpp constrains
[  155.925174] [drm:intel_modeset_pipe_config] clamping display bpp (was 36) to default limit of 24
[  155.925179] [drm:intel_dsi_compute_config]
[  155.925182] [drm:intel_compute_dsi_pll] DSI PLL calculation is Done!!
[  155.925185] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
[  155.925188] [drm:intel_dump_pipe_config] [CRTC:42:pipe A][modeset]
[  155.925190] [drm:intel_dump_pipe_config] cpu_transcoder: DSI A, pipe bpp: 24, dithering: 0
[  155.925192] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[  155.925193] [drm:intel_dump_pipe_config] requested mode:
[  155.925197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 157100 1920 2000 2080 2160 1200 1204 1208 1212 0x8 0xa
[  155.925198] [drm:intel_dump_pipe_config] adjusted mode:
[  155.925201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 0 157100 1920 2000 2080 2160 1200 1204 1208 1212 0x8 0x0
[  155.925204] [drm:intel_dump_pipe_config] crtc timings: 157100 1920 2000 2080 2160 1200 1204 1208 1212, type: 0x8 flags: 0x0
[  155.925206] [drm:intel_dump_pipe_config] port clock: 157100, pipe src size: 1920x1200, pixel rate 157100
[  155.925208] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
[  155.925210] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  155.925212] [drm:intel_dump_pipe_config] ips: 0, double wide: 0
[  155.925217] [drm:bxt_dump_hw_state] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
[  155.925218] [drm:intel_dump_pipe_config] planes on this crtc
[  155.925220] [drm:intel_dump_pipe_config] [PLANE:27:plane 1A] disabled, scaler_id = -1
[  155.925222] [drm:intel_dump_pipe_config] [PLANE:30:plane 2A] disabled, scaler_id = -1
[  155.925224] [drm:intel_dump_pipe_config] [PLANE:33:plane 3A] disabled, scaler_id = -1
[  155.925226] [drm:intel_dump_pipe_config] [PLANE:36:plane 4A] disabled, scaler_id = -1
[  155.925228] [drm:intel_dump_pipe_config] [PLANE:39:cursor A] disabled, scaler_id = -1
[  155.925235] [drm:intel_atomic_check] New cdclk calculated to be logical 158400 kHz, actual 158400 kHz
[  155.925468] [drm:intel_set_cdclk] Changing CDCLK to 158400 kHz, VCO 633600 kHz, ref 19200 kHz
[  155.925503] [drm:intel_update_cdclk] Current CD clock rate: 158400 kHz, VCO: 633600 kHz, ref: 19200 kHz
[  155.925505] [drm:intel_atomic_commit_tail] [ENCODER:75:DDI B]
[  155.925507] [drm:intel_atomic_commit_tail] [ENCODER:77:DP-MST A]
[  155.925509] [drm:intel_atomic_commit_tail] [ENCODER:78:DP-MST B]
[  155.925511] [drm:intel_atomic_commit_tail] [ENCODER:79:DP-MST C]
[  155.925512] [drm:intel_atomic_commit_tail] [ENCODER:84:DDI C]
[  155.925514] [drm:intel_atomic_commit_tail] [ENCODER:86:DSI A]
[  155.925517] [drm:verify_single_dpll_state.isra.106] PORT PLL A
[  155.925520] [drm:verify_single_dpll_state.isra.106] PORT PLL B
[  155.925523] [drm:verify_single_dpll_state.isra.106] PORT PLL C
[  155.925531] [drm:intel_dsi_pre_enable]
[  155.925533] [drm:intel_disable_dsi_pll]
[  155.925537] [drm:intel_enable_dsi_pll]
[  155.927606] [drm:intel_enable_dsi_pll] DSI PLL locked
[  155.927612] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 10 - MIPI_SEQ_POWER_ON
[  155.927615] [drm:mipi_exec_gpio]
[  155.927626] [drm:mipi_exec_delay]
[  155.932861] [drm:intel_dsi_prepare] pipe A
[  155.954265] [drm:intel_panel_enable_backlight] pipe A
[  155.954276] [drm:intel_panel_actually_set_backlight] set backlight PWM = 28800
[  155.954285] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 6 - MIPI_SEQ_BACKLIGHT_ON
[  155.954289] [drm:mipi_exec_gpio]
[  155.954303] [drm:mipi_exec_delay]
[  155.957169] [drm:intel_dsi_enable_nop]
[  155.957186] [drm:intel_fbc_enable] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
[  155.957189] [drm:intel_fbc_enable] Enabling FBC on pipe A
[  155.971560] [drm:verify_connector_state.isra.105] [CONNECTOR:87:DSI-1]
[  155.971570] [drm:intel_dsi_get_hw_state]
[  155.971582] [drm:intel_atomic_commit_tail] [CRTC:42:pipe A]
[  155.971597] [drm:intel_dsi_get_hw_state]
[  155.971605] [drm:intel_dsi_get_config]
[  155.971619] [drm:intel_dsi_get_pclk] Calculated pclk=158400
[  156.005855] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
[  156.005914] [drm:intel_atomic_check] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
[  156.005985] [drm:intel_dsi_disable]
[  156.005993] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 7 - MIPI_SEQ_BACKLIGHT_OFF
[  156.005997] [drm:mipi_exec_gpio]
[  156.006073] [drm:mipi_exec_delay]
[  156.007169] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
[  156.033765] [drm:intel_dsi_post_disable]
[  156.038221] [drm:intel_disable_dsi_pll]
[  156.038236] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 11 - MIPI_SEQ_POWER_OFF
[  156.038240] [drm:mipi_exec_gpio]
[  156.038261] [drm:__intel_fbc_disable] Disabling FBC on pipe A
[  156.038299] [drm:intel_set_cdclk] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
[  156.038337] [drm:intel_update_cdclk] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
[  156.038344] [drm:intel_atomic_commit_tail] [ENCODER:75:DDI B]
[  156.038350] [drm:intel_atomic_commit_tail] [ENCODER:77:DP-MST A]
[  156.038355] [drm:intel_atomic_commit_tail] [ENCODER:78:DP-MST B]
[  156.038360] [drm:intel_atomic_commit_tail] [ENCODER:79:DP-MST C]
[  156.038364] [drm:intel_atomic_commit_tail] [ENCODER:84:DDI C]
[  156.038369] [drm:intel_atomic_commit_tail] [ENCODER:86:DSI A]
[  156.038375] [drm:intel_dsi_get_hw_state]
[  156.038385] [drm:verify_connector_state.isra.105] [CONNECTOR:87:DSI-1]
[  156.038390] [drm:intel_dsi_get_hw_state]
[  156.038397] [drm:verify_single_dpll_state.isra.106] PORT PLL A
[  156.038403] [drm:verify_single_dpll_state.isra.106] PORT PLL B
[  156.038408] [drm:verify_single_dpll_state.isra.106] PORT PLL C
[  156.038432] [drm:intel_atomic_commit_tail] [CRTC:42:pipe A]
[  156.038550] [drm:drm_mode_setcrtc] [CRTC:58:pipe B]
[  156.038626] [drm:drm_mode_setcrtc] [CRTC:74:pipe C]
[  156.047709] [drm:drm_mode_addfb2] [FB:94]
[  156.055149] [drm:drm_mode_addfb2] [FB:99]
[  156.061891] [drm:drm_mode_addfb2] [FB:100]
[  156.067286] [drm:drm_mode_addfb2] [FB:101]
[  156.256773] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
[  156.256787] [drm:drm_mode_setcrtc] [CONNECTOR:87:DSI-1]
[  156.256812] [drm:intel_modeset_pipe_config] [CONNECTOR:87:DSI-1] checking for sink bpp constrains
[  156.256814] [drm:intel_modeset_pipe_config] clamping display bpp (was 36) to default limit of 24
[  156.256818] [drm:intel_dsi_compute_config]
[  156.256821] [drm:intel_compute_dsi_pll] DSI PLL calculation is Done!!
[  156.256824] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
[  156.256827] [drm:intel_dump_pipe_config] [CRTC:42:pipe A][modeset]
[  156.256829] [drm:intel_dump_pipe_config] cpu_transcoder: DSI A, pipe bpp: 24, dithering: 0
[  156.256831] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[  156.256832] [drm:intel_dump_pipe_config] requested mode:
[  156.256836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 157100 1920 2000 2080 2160 1200 1204 1208 1212 0x8 0xa
[  156.256837] [drm:intel_dump_pipe_config] adjusted mode:
[  156.256840] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 0 157100 1920 2000 2080 2160 1200 1204 1208 1212 0x8 0x0
[  156.256843] [drm:intel_dump_pipe_config] crtc timings: 157100 1920 2000 2080 2160 1200 1204 1208 1212, type: 0x8 flags: 0x0
[  156.256845] [drm:intel_dump_pipe_config] port clock: 157100, pipe src size: 1920x1200, pixel rate 157100
[  156.256847] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
[  156.256849] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  156.256851] [drm:intel_dump_pipe_config] ips: 0, double wide: 0
[  156.256856] [drm:bxt_dump_hw_state] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
[  156.256857] [drm:intel_dump_pipe_config] planes on this crtc
[  156.256859] [drm:intel_dump_pipe_config] [PLANE:27:plane 1A] disabled, scaler_id = -1
[  156.256861] [drm:intel_dump_pipe_config] [PLANE:30:plane 2A] disabled, scaler_id = -1
[  156.256863] [drm:intel_dump_pipe_config] [PLANE:33:plane 3A] disabled, scaler_id = -1
[  156.256865] [drm:intel_dump_pipe_config] [PLANE:36:plane 4A] disabled, scaler_id = -1
[  156.256867] [drm:intel_dump_pipe_config] [PLANE:39:cursor A] disabled, scaler_id = -1
[  156.256874] [drm:intel_atomic_check] New cdclk calculated to be logical 158400 kHz, actual 158400 kHz
[  156.257133] [drm:intel_set_cdclk] Changing CDCLK to 158400 kHz, VCO 633600 kHz, ref 19200 kHz
[  156.257177] [drm:intel_update_cdclk] Current CD clock rate: 158400 kHz, VCO: 633600 kHz, ref: 19200 kHz
[  156.257180] [drm:intel_atomic_commit_tail] [ENCODER:75:DDI B]
[  156.257182] [drm:intel_atomic_commit_tail] [ENCODER:77:DP-MST A]
[  156.257184] [drm:intel_atomic_commit_tail] [ENCODER:78:DP-MST B]
[  156.257186] [drm:intel_atomic_commit_tail] [ENCODER:79:DP-MST C]
[  156.257187] [drm:intel_atomic_commit_tail] [ENCODER:84:DDI C]
[  156.257189] [drm:intel_atomic_commit_tail] [ENCODER:86:DSI A]
[  156.257191] [drm:verify_single_dpll_state.isra.106] PORT PLL A
[  156.257195] [drm:verify_single_dpll_state.isra.106] PORT PLL B
[  156.257198] [drm:verify_single_dpll_state.isra.106] PORT PLL C
[  156.257206] [drm:intel_dsi_pre_enable]
[  156.257208] [drm:intel_disable_dsi_pll]
[  156.257213] [drm:intel_enable_dsi_pll]
[  156.259306] [drm:intel_enable_dsi_pll] DSI PLL locked
[  156.259330] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 10 - MIPI_SEQ_POWER_ON
[  156.259333] [drm:mipi_exec_gpio]
[  156.259346] [drm:mipi_exec_delay]
[  156.264476] [drm:intel_dsi_prepare] pipe A
[  156.286253] [drm:intel_panel_enable_backlight] pipe A
[  156.286263] [drm:intel_panel_actually_set_backlight] set backlight PWM = 28800
[  156.286272] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 6 - MIPI_SEQ_BACKLIGHT_ON
[  156.286276] [drm:mipi_exec_gpio]
[  156.286289] [drm:mipi_exec_delay]
[  156.289065] [drm:intel_dsi_enable_nop]
[  156.289079] [drm:intel_fbc_enable] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
[  156.289082] [drm:intel_fbc_enable] Enabling FBC on pipe A
[  156.303500] [drm:verify_connector_state.isra.105] [CONNECTOR:87:DSI-1]
[  156.303511] [drm:intel_dsi_get_hw_state]
[  156.303523] [drm:intel_atomic_commit_tail] [CRTC:42:pipe A]
[  156.303539] [drm:intel_dsi_get_hw_state]
[  156.303547] [drm:intel_dsi_get_config]
[  156.303562] [drm:intel_dsi_get_pclk] Calculated pclk=158400
[  156.337779] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
[  156.337805] [drm:drm_mode_setcrtc] [CONNECTOR:87:DSI-1]
[  156.387252] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
[  156.387283] [drm:drm_mode_setcrtc] [CONNECTOR:87:DSI-1]
[  156.437086] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
[  156.437118] [drm:drm_mode_setcrtc] [CONNECTOR:87:DSI-1]
[  156.486723] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
[  156.486788] [drm:intel_atomic_check] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
[  156.486874] [drm:intel_dsi_disable]
[  156.486883] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 7 - MIPI_SEQ_BACKLIGHT_OFF
[  156.486889] [drm:mipi_exec_gpio]
[  156.486905] [drm:mipi_exec_delay]
[  156.487944] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
[  156.513835] [drm:intel_dsi_post_disable]
[  156.518228] [drm:intel_disable_dsi_pll]
[  156.518243] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 11 - MIPI_SEQ_POWER_OFF
[  156.518248] [drm:mipi_exec_gpio]
[  156.518270] [drm:__intel_fbc_disable] Disabling FBC on pipe A
[  156.518311] [drm:intel_set_cdclk] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
[  156.518369] [drm:intel_update_cdclk] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
[  156.518378] [drm:intel_atomic_commit_tail] [ENCODER:75:DDI B]
[  156.518384] [drm:intel_atomic_commit_tail] [ENCODER:77:DP-MST A]
[  156.518390] [drm:intel_atomic_commit_tail] [ENCODER:78:DP-MST B]
[  156.518395] [drm:intel_atomic_commit_tail] [ENCODER:79:DP-MST C]
[  156.518400] [drm:intel_atomic_commit_tail] [ENCODER:84:DDI C]
[  156.518405] [drm:intel_atomic_commit_tail] [ENCODER:86:DSI A]
[  156.518411] [drm:intel_dsi_get_hw_state]
[  156.518422] [drm:verify_connector_state.isra.105] [CONNECTOR:87:DSI-1]
[  156.518428] [drm:intel_dsi_get_hw_state]
[  156.518436] [drm:verify_single_dpll_state.isra.106] PORT PLL A
[  156.518443] [drm:verify_single_dpll_state.isra.106] PORT PLL B
[  156.518449] [drm:verify_single_dpll_state.isra.106] PORT PLL C
[  156.518474] [drm:intel_atomic_commit_tail] [CRTC:42:pipe A]
[  156.518599] [drm:drm_mode_setcrtc] [CRTC:58:pipe B]
[  156.518681] [drm:drm_mode_setcrtc] [CRTC:74:pipe C]
[  156.519755] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
[  156.519773] [drm:drm_mode_setcrtc] [CONNECTOR:87:DSI-1]
[  156.519811] [drm:intel_modeset_pipe_config] [CONNECTOR:87:DSI-1] checking for sink bpp constrains
[  156.519817] [drm:intel_modeset_pipe_config] clamping display bpp (was 36) to default limit of 24
[  156.519824] [drm:intel_dsi_compute_config]
[  156.519830] [drm:intel_compute_dsi_pll] DSI PLL calculation is Done!!
[  156.519837] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
[  156.519843] [drm:intel_dump_pipe_config] [CRTC:42:pipe A][modeset]
[  156.519849] [drm:intel_dump_pipe_config] cpu_transcoder: DSI A, pipe bpp: 24, dithering: 0
[  156.519853] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[  156.519857] [drm:intel_dump_pipe_config] requested mode:
[  156.519867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 157100 1920 2000 2080 2160 1200 1204 1208 1212 0x8 0xa
[  156.519872] [drm:intel_dump_pipe_config] adjusted mode:
[  156.519880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 0 157100 1920 2000 2080 2160 1200 1204 1208 1212 0x8 0x0
[  156.519892] [drm:intel_dump_pipe_config] crtc timings: 157100 1920 2000 2080 2160 1200 1204 1208 1212, type: 0x8 flags: 0x0
[  156.519897] [drm:intel_dump_pipe_config] port clock: 157100, pipe src size: 1920x1200, pixel rate 157100
[  156.519903] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
[  156.519908] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  156.519913] [drm:intel_dump_pipe_config] ips: 0, double wide: 0
[  156.519923] [drm:bxt_dump_hw_state] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
[  156.519927] [drm:intel_dump_pipe_config] planes on this crtc
[  156.519932] [drm:intel_dump_pipe_config] [PLANE:27:plane 1A] disabled, scaler_id = -1
[  156.519937] [drm:intel_dump_pipe_config] [PLANE:30:plane 2A] disabled, scaler_id = -1
[  156.519942] [drm:intel_dump_pipe_config] [PLANE:33:plane 3A] disabled, scaler_id = -1
[  156.519946] [drm:intel_dump_pipe_config] [PLANE:36:plane 4A] disabled, scaler_id = -1
[  156.519951] [drm:intel_dump_pipe_config] [PLANE:39:cursor A] disabled, scaler_id = -1
[  156.519964] [drm:intel_atomic_check] New cdclk calculated to be logical 158400 kHz, actual 158400 kHz
[  156.523490] [drm:intel_set_cdclk] Changing CDCLK to 158400 kHz, VCO 633600 kHz, ref 19200 kHz
[  156.523529] [drm:intel_update_cdclk] Current CD clock rate: 158400 kHz, VCO: 633600 kHz, ref: 19200 kHz
[  156.523535] [drm:intel_atomic_commit_tail] [ENCODER:75:DDI B]
[  156.523540] [drm:intel_atomic_commit_tail] [ENCODER:77:DP-MST A]
[  156.523544] [drm:intel_atomic_commit_tail] [ENCODER:78:DP-MST B]
[  156.523551] [drm:intel_atomic_commit_tail] [ENCODER:79:DP-MST C]
[  156.523555] [drm:intel_atomic_commit_tail] [ENCODER:84:DDI C]
[  156.523559] [drm:intel_atomic_commit_tail] [ENCODER:86:DSI A]
[  156.523563] [drm:verify_single_dpll_state.isra.106] PORT PLL A
[  156.523569] [drm:verify_single_dpll_state.isra.106] PORT PLL B
[  156.523574] [drm:verify_single_dpll_state.isra.106] PORT PLL C
[  156.523589] [drm:intel_dsi_pre_enable]
[  156.523593] [drm:intel_disable_dsi_pll]
[  156.523600] [drm:intel_enable_dsi_pll]
[  156.525066] [drm:intel_enable_dsi_pll] DSI PLL locked
[  156.525073] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 10 - MIPI_SEQ_POWER_ON
[  156.525078] [drm:mipi_exec_gpio]
[  156.525090] [drm:mipi_exec_delay]
[  156.530217] [drm:intel_dsi_prepare] pipe A
[  156.552270] [drm:intel_panel_enable_backlight] pipe A
[  156.552278] [drm:intel_panel_actually_set_backlight] set backlight PWM = 28800
[  156.552284] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 6 - MIPI_SEQ_BACKLIGHT_ON
[  156.552287] [drm:mipi_exec_gpio]
[  156.552299] [drm:mipi_exec_delay]
[  156.555052] [drm:intel_dsi_enable_nop]
[  156.555063] [drm:intel_fbc_enable] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
[  156.555065] [drm:intel_fbc_enable] Enabling FBC on pipe A
[  156.569489] [drm:verify_connector_state.isra.105] [CONNECTOR:87:DSI-1]
[  156.569497] [drm:intel_dsi_get_hw_state]
[  156.569506] [drm:intel_atomic_commit_tail] [CRTC:42:pipe A]
[  156.569519] [drm:intel_dsi_get_hw_state]
[  156.569525] [drm:intel_dsi_get_config]
[  156.569537] [drm:intel_dsi_get_pclk] Calculated pclk=158400
[  156.641221] [drm:intel_atomic_check] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
[  156.641278] [drm:intel_dsi_disable]
[  156.641286] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 7 - MIPI_SEQ_BACKLIGHT_OFF
[  156.641291] [drm:mipi_exec_gpio]
[  156.641307] [drm:mipi_exec_delay]
[  156.642718] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
[  156.664601] [drm:intel_dsi_post_disable]
[  156.669229] [drm:intel_disable_dsi_pll]
[  156.669241] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 11 - MIPI_SEQ_POWER_OFF
[  156.669246] [drm:mipi_exec_gpio]
[  156.669265] [drm:__intel_fbc_disable] Disabling FBC on pipe A
[  156.669298] [drm:intel_set_cdclk] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
[  156.669335] [drm:intel_update_cdclk] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
[  156.669341] [drm:intel_atomic_commit_tail] [ENCODER:75:DDI B]
[  156.669346] [drm:intel_atomic_commit_tail] [ENCODER:77:DP-MST A]
[  156.669350] [drm:intel_atomic_commit_tail] [ENCODER:78:DP-MST B]
[  156.669354] [drm:intel_atomic_commit_tail] [ENCODER:79:DP-MST C]
[  156.669357] [drm:intel_atomic_commit_tail] [ENCODER:84:DDI C]
[  156.669361] [drm:intel_atomic_commit_tail] [ENCODER:86:DSI A]
[  156.669366] [drm:intel_dsi_get_hw_state]
[  156.669375] [drm:verify_connector_state.isra.105] [CONNECTOR:87:DSI-1]
[  156.669379] [drm:intel_dsi_get_hw_state]
[  156.669385] [drm:verify_single_dpll_state.isra.106] PORT PLL A
[  156.669391] [drm:verify_single_dpll_state.isra.106] PORT PLL B
[  156.669395] [drm:verify_single_dpll_state.isra.106] PORT PLL C
[  156.669416] [drm:intel_atomic_commit_tail] [CRTC:42:pipe A]
[  156.669727] [IGT] kms_frontbuffer_tracking: exiting, ret=99
[  156.703418] [drm:intel_modeset_pipe_config] [CONNECTOR:87:DSI-1] checking for sink bpp constrains
[  156.703425] [drm:intel_modeset_pipe_config] clamping display bpp (was 36) to default limit of 24
[  156.703431] [drm:intel_dsi_compute_config]
[  156.703436] [drm:intel_compute_dsi_pll] DSI PLL calculation is Done!!
[  156.703441] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
[  156.703447] [drm:intel_dump_pipe_config] [CRTC:42:pipe A][modeset]
[  156.703450] [drm:intel_dump_pipe_config] cpu_transcoder: DSI A, pipe bpp: 24, dithering: 0
[  156.703453] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[  156.703456] [drm:intel_dump_pipe_config] requested mode:
[  156.703464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 157100 1920 2000 2080 2160 1200 1204 1208 1212 0x8 0xa
[  156.703466] [drm:intel_dump_pipe_config] adjusted mode:
[  156.703471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 0 157100 1920 2000 2080 2160 1200 1204 1208 1212 0x8 0x0
[  156.703476] [drm:intel_dump_pipe_config] crtc timings: 157100 1920 2000 2080 2160 1200 1204 1208 1212, type: 0x8 flags: 0x0
[  156.703479] [drm:intel_dump_pipe_config] port clock: 157100, pipe src size: 1920x1200, pixel rate 157100
[  156.703483] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
[  156.703486] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  156.703489] [drm:intel_dump_pipe_config] ips: 0, double wide: 0
[  156.703496] [drm:bxt_dump_hw_state] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
[  156.703499] [drm:intel_dump_pipe_config] planes on this crtc
[  156.703502] [drm:intel_dump_pipe_config] [PLANE:27:plane 1A] disabled, scaler_id = -1
[  156.703505] [drm:intel_dump_pipe_config] [PLANE:30:plane 2A] disabled, scaler_id = -1
[  156.703508] [drm:intel_dump_pipe_config] [PLANE:33:plane 3A] disabled, scaler_id = -1
[  156.703511] [drm:intel_dump_pipe_config] [PLANE:36:plane 4A] disabled, scaler_id = -1
[  156.703514] [drm:intel_dump_pipe_config] [PLANE:39:cursor A] disabled, scaler_id = -1
[  156.703521] [drm:intel_atomic_check] New cdclk calculated to be logical 158400 kHz, actual 158400 kHz
[  156.703591] [drm:intel_set_cdclk] Changing CDCLK to 158400 kHz, VCO 633600 kHz, ref 19200 kHz
[  156.703628] [drm:intel_update_cdclk] Current CD clock rate: 158400 kHz, VCO: 633600 kHz, ref: 19200 kHz
[  156.703633] [drm:intel_atomic_commit_tail] [ENCODER:75:DDI B]
[  156.703636] [drm:intel_atomic_commit_tail] [ENCODER:77:DP-MST A]
[  156.703640] [drm:intel_atomic_commit_tail] [ENCODER:78:DP-MST B]
[  156.703643] [drm:intel_atomic_commit_tail] [ENCODER:79:DP-MST C]
[  156.703645] [drm:intel_atomic_commit_tail] [ENCODER:84:DDI C]
[  156.703648] [drm:intel_atomic_commit_tail] [ENCODER:86:DSI A]
[  156.703653] [drm:verify_single_dpll_state.isra.106] PORT PLL A
[  156.703658] [drm:verify_single_dpll_state.isra.106] PORT PLL B
[  156.703662] [drm:verify_single_dpll_state.isra.106] PORT PLL C
[  156.703674] [drm:intel_dsi_pre_enable]
[  156.703678] [drm:intel_disable_dsi_pll]
[  156.703684] [drm:intel_enable_dsi_pll]
[  156.705080] [drm:intel_enable_dsi_pll] DSI PLL locked
[  156.705089] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 10 - MIPI_SEQ_POWER_ON
[  156.705093] [drm:mipi_exec_gpio]
[  156.705106] [drm:mipi_exec_delay]
[  156.710236] [drm:intel_dsi_prepare] pipe A
[  156.732252] [drm:intel_panel_enable_backlight] pipe A
[  156.732263] [drm:intel_panel_actually_set_backlight] set backlight PWM = 28800
[  156.732272] [drm:intel_dsi_vbt_exec_sequence] Starting MIPI sequence 6 - MIPI_SEQ_BACKLIGHT_ON
[  156.732276] [drm:mipi_exec_gpio]
[  156.732290] [drm:mipi_exec_delay]
[  156.735122] [drm:intel_dsi_enable_nop]
[  156.735138] [drm:intel_fbc_enable] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
[  156.735141] [drm:intel_fbc_enable] Enabling FBC on pipe A
[  156.749513] [drm:verify_connector_state.isra.105] [CONNECTOR:87:DSI-1]
[  156.749523] [drm:intel_dsi_get_hw_state]
[  156.749534] [drm:intel_atomic_commit_tail] [CRTC:42:pipe A]
[  156.749549] [drm:intel_dsi_get_hw_state]
[  156.749556] [drm:intel_dsi_get_config]
[  156.749570] [drm:intel_dsi_get_pclk] Calculated pclk=158400
[  156.798258] Console: switching to colour frame buffer device 240x75