CI [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-varying-size [drm:drm_mode_addfb2] [FB:98] [drm:drm_mode_addfb2] [FB:100] [drm:drm_mode_addfb2] [FB:101] [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [IGT] kms_cursor_legacy: exiting, ret=0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL Console: switching to colour frame buffer device 240x75 Console: switching to colour dummy device 80x25 [IGT] kms_cursor_legacy: executing [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] [drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1 [drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1 [drm:intel_crt_detect [i915]] CRT detected via hotplug [drm:drm_edid_to_eld] ELD monitor LEN LT2452pwC [drm:drm_edid_to_eld] ELD size 36 SAD count 0 [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes : [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:drm_mode_debug_printmodeline] Modeline 78:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1111 0x40 0x9 [drm:drm_mode_debug_printmodeline] Modeline 85:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 84:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6 [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 72 132840 1280 1368 1504 1728 1024 1025 1028 1067 0x0 0x6 [drm:drm_mode_debug_printmodeline] Modeline 80:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 83:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6 [drm:drm_mode_debug_printmodeline] Modeline 82:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6 [drm:drm_mode_debug_printmodeline] Modeline 92:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 93:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 95:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 96:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 86:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 87:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 88:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 66 26885 640 664 728 816 480 481 484 499 0x0 0x6 [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 89:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 90:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:DP-1] [drm:intel_dp_detect [i915]] [CONNECTOR:60:DP-1] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:DP-1] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:66:HDMI-A-1] [drm:intel_hdmi_detect [i915]] [CONNECTOR:66:HDMI-A-1] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 50 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 50 w(1) [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 40 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 40 w(1) [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: (err -6) [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:66:HDMI-A-1] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:69:DP-2] [drm:intel_dp_detect [i915]] [CONNECTOR:69:DP-2] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110 [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:69:DP-2] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:73:HDMI-A-2] [drm:intel_hdmi_detect [i915]] [CONNECTOR:73:HDMI-A-2] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 50 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 50 w(1) [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 40 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 40 w(1) [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: (err -6) [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:73:HDMI-A-2] disconnected [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-atomic [drm:drm_mode_addfb2] [FB:74] [drm:drm_mode_addfb2] [FB:100] [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [IGT] kms_cursor_legacy: exiting, ret=0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL Console: switching to colour frame buffer device 240x75 Console: switching to colour dummy device 80x25 [IGT] kms_cursor_legacy: executing [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] [drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1 [drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1 [drm:intel_crt_detect [i915]] CRT detected via hotplug [drm:drm_edid_to_eld] ELD monitor LEN LT2452pwC [drm:drm_edid_to_eld] ELD size 36 SAD count 0 [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes : [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:drm_mode_debug_printmodeline] Modeline 78:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1111 0x40 0x9 [drm:drm_mode_debug_printmodeline] Modeline 85:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 84:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6 [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 72 132840 1280 1368 1504 1728 1024 1025 1028 1067 0x0 0x6 [drm:drm_mode_debug_printmodeline] Modeline 80:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 83:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6 [drm:drm_mode_debug_printmodeline] Modeline 82:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6 [drm:drm_mode_debug_printmodeline] Modeline 92:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 93:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 95:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 96:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 86:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 87:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 88:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 66 26885 640 664 728 816 480 481 484 499 0x0 0x6 [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 89:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 90:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:DP-1] [drm:intel_dp_detect [i915]] [CONNECTOR:60:DP-1] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:DP-1] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:66:HDMI-A-1] [drm:intel_hdmi_detect [i915]] [CONNECTOR:66:HDMI-A-1] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 50 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 50 w(1) [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 40 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 40 w(1) [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: (err -6) [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:66:HDMI-A-1] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:69:DP-2] [drm:intel_dp_detect [i915]] [CONNECTOR:69:DP-2] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110 [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:69:DP-2] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:73:HDMI-A-2] [drm:intel_hdmi_detect [i915]] [CONNECTOR:73:HDMI-A-2] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 50 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 50 w(1) [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 40 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 40 w(1) [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: (err -6) [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:73:HDMI-A-2] disconnected [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-legacy [drm:drm_mode_addfb2] [FB:98] [drm:drm_mode_addfb2] [FB:100] [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [IGT] kms_cursor_legacy: exiting, ret=0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL Console: switching to colour frame buffer device 240x75 Console: switching to colour dummy device 80x25 [IGT] kms_cursor_legacy: executing [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] [drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1 [drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1 [drm:intel_crt_detect [i915]] CRT detected via hotplug [drm:drm_edid_to_eld] ELD monitor LEN LT2452pwC [drm:drm_edid_to_eld] ELD size 36 SAD count 0 [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes : [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:drm_mode_debug_printmodeline] Modeline 78:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1111 0x40 0x9 [drm:drm_mode_debug_printmodeline] Modeline 85:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 84:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6 [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 72 132840 1280 1368 1504 1728 1024 1025 1028 1067 0x0 0x6 [drm:drm_mode_debug_printmodeline] Modeline 80:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 83:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6 [drm:drm_mode_debug_printmodeline] Modeline 82:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6 [drm:drm_mode_debug_printmodeline] Modeline 92:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 93:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 95:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 96:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 86:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 87:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 88:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 66 26885 640 664 728 816 480 481 484 499 0x0 0x6 [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 89:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 90:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:DP-1] [drm:intel_dp_detect [i915]] [CONNECTOR:60:DP-1] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:DP-1] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:66:HDMI-A-1] [drm:intel_hdmi_detect [i915]] [CONNECTOR:66:HDMI-A-1] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 50 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 50 w(1) [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 40 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 40 w(1) [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: (err -6) [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:66:HDMI-A-1] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:69:DP-2] [drm:intel_dp_detect [i915]] [CONNECTOR:69:DP-2] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110 [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:69:DP-2] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:73:HDMI-A-2] [drm:intel_hdmi_detect [i915]] [CONNECTOR:73:HDMI-A-2] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 50 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 50 w(1) [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 40 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 40 w(1) [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: (err -6) [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:73:HDMI-A-2] disconnected [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-varying-size [drm:drm_mode_addfb2] [FB:74] [drm:drm_mode_addfb2] [FB:100] [drm:drm_mode_addfb2] [FB:101] [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [IGT] kms_cursor_legacy: exiting, ret=0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL Console: switching to colour frame buffer device 240x75 Console: switching to colour dummy device 80x25 [IGT] kms_flip: executing [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] [drm:intel_crt_detect [i915]] [CONNECTOR:57:VGA-1] force=1 [drm:intel_crt_detect [i915]] ironlake hotplug adpa=0x83f40008, result 1 [drm:intel_crt_detect [i915]] CRT detected via hotplug [drm:drm_edid_to_eld] ELD monitor LEN LT2452pwC [drm:drm_edid_to_eld] ELD size 36 SAD count 0 [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:VGA-1] probed modes : [drm:drm_mode_debug_printmodeline] Modeline 77:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:drm_mode_debug_printmodeline] Modeline 78:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1111 0x40 0x9 [drm:drm_mode_debug_printmodeline] Modeline 85:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 84:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6 [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 72 132840 1280 1368 1504 1728 1024 1025 1028 1067 0x0 0x6 [drm:drm_mode_debug_printmodeline] Modeline 80:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 83:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6 [drm:drm_mode_debug_printmodeline] Modeline 82:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6 [drm:drm_mode_debug_printmodeline] Modeline 92:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 93:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 95:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 96:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 86:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [drm:drm_mode_debug_printmodeline] Modeline 87:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 88:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 66 26885 640 664 728 816 480 481 484 499 0x0 0x6 [drm:drm_mode_debug_printmodeline] Modeline 97:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 89:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [drm:drm_mode_debug_printmodeline] Modeline 90:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:DP-1] [drm:intel_dp_detect [i915]] [CONNECTOR:60:DP-1] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:DP-1] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:66:HDMI-A-1] [drm:intel_hdmi_detect [i915]] [CONNECTOR:66:HDMI-A-1] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 50 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 50 w(1) [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 40 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 40 w(1) [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: (err -6) [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:66:HDMI-A-1] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:69:DP-2] [drm:intel_dp_detect [i915]] [CONNECTOR:69:DP-2] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x71450048 [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110 [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:69:DP-2] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:73:HDMI-A-2] [drm:intel_hdmi_detect [i915]] [CONNECTOR:73:HDMI-A-2] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 50 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 50 w(1) [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 40 w(1) [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 40 w(1) [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: (err -6) [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:73:HDMI-A-2] disconnected [IGT] kms_flip: starting subtest basic-flip-vs-dpms [drm:drm_mode_addfb2] [FB:98] [drm:drm_mode_addfb2] [FB:100] [drm:drm_mode_setcrtc] [CRTC:36:pipe A] [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:drm_mode_setcrtc] [CRTC:46:pipe B] [drm:drm_mode_setcrtc] [CRTC:56:pipe C] [drm:drm_mode_setcrtc] [CRTC:36:pipe A] [drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1] [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:100, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 1 on? 0) for crtc 36 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe A [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe A, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:27:primary A] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:30:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe A [drm:intel_disable_pipe [i915]] disabling pipe A [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 1 on? 1) for crtc 36 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A] [drm:drm_mode_addfb2] [FB:98] [drm:drm_mode_addfb2] [FB:99] [drm:drm_mode_setcrtc] [CRTC:36:pipe A] [drm:drm_mode_setcrtc] [CRTC:46:pipe B] [drm:drm_mode_setcrtc] [CRTC:56:pipe C] [drm:drm_mode_setcrtc] [CRTC:46:pipe B] [drm:drm_mode_setcrtc] [CONNECTOR:57:VGA-1] [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:99, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:intel_enable_shared_dpll [i915]] enable SPLL (active 2 on? 0) for crtc 46 [drm:intel_enable_shared_dpll [i915]] enabling SPLL [drm:hsw_fdi_link_train [i915]] FDI link training done on step 0 [drm:intel_enable_pipe [i915]] enabling pipe B [drm:haswell_crtc_enable [i915]] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B] [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:intel_atomic_check [i915]] [CONNECTOR:57:VGA-1] checking for sink bpp constrains [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 [drm:intel_atomic_check [i915]] checking fdi config on pipe B, lanes 2 [drm:intel_atomic_check [i915]] hw max bpp: 36 pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24 dithering: 0 [drm:intel_dump_pipe_config [i915]] fdi: lanes: 2; gmch_m: 7176920 gmch_n: 8388608 link_m: 299038 link_n: 524288 tu: 64 [drm:intel_dump_pipe_config [i915]] audio: 0 infoframes: 0 [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235 type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config [i915]] port clock: 270000 pipe src size: 1920x1200, pixel rate 154000 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config [i915]] ips: 0 double wide: 0 [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x94000000 [drm:intel_dump_pipe_config [i915]] planes on this crtc [drm:intel_dump_pipe_config [i915]] [PLANE:37:primary B] FB:98, fb = 1920x1200 format = XR24 little-endian (0x34325258) [drm:intel_dump_pipe_config [i915]] [PLANE:40:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = 0 [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated SPLL [drm:intel_reference_shared_dpll [i915]] using SPLL for pipe B [drm:intel_disable_pipe [i915]] disabling pipe B [drm:intel_disable_shared_dpll [i915]] disable SPLL (active 2 on? 1) for crtc 46 [drm:intel_disable_shared_dpll [i915]] disabling SPLL [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:CRT] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DDI C] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST A] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST B] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DP-MST C] [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 1 [drm:verify_single_dpll_state.isra.72 [i915]] WRPLL 2 [drm:verify_single_dpll_state.isra.72 [i915]] SPLL [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 810 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 1350 [drm:verify_single_dpll_state.isra.72 [i915]] LCPLL 2700 [drm:verify_connector_state.isra.71 [i915]] [CONNECTOR:57:VGA-1]