[ 102.566204] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 102.566279] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 102.567496] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 102.567575] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 102.567700] [drm:intel_disable_pipe [i915]] disabling pipe A [ 102.578859] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 102.578900] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 102.578939] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 102.578975] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 102.579015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 102.579049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 102.579081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 102.579112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 102.579143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 102.579172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 102.579201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 102.579231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 102.579262] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 102.579294] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 102.579326] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 102.579356] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 102.579391] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 102.579423] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 102.579536] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 102.580115] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 102.581352] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 102.582586] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 102.583814] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 102.585031] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 102.585866] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 102.586800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 102.586835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 102.586868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 102.586902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 102.605626] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 102.605651] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 102.624337] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 102.624664] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 [ 102.625094] [drm:intel_enable_pipe [i915]] enabling pipe A [ 102.625117] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 102.625134] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 102.625150] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 102.625169] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 102.625198] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 [ 102.625213] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 102.642071] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 102.642094] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 102.642125] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 107.648181] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 107.699954] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 107.699963] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 107.699994] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 107.700011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 107.700045] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148352KHz [ 107.700070] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 107.700088] [drm:intel_dp_compute_config [i915]] DP link bw required 445056 available 648000 [ 107.700105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 107.700122] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 107.700138] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 107.700153] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 107.700167] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5761420, gmch_n: 8388608, link_m: 240059, link_n: 262144, tu: 64 [ 107.700182] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 107.700195] [drm:intel_dump_pipe_config [i915]] requested mode: [ 107.700203] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 107.700217] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 107.700224] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 107.700239] [drm:intel_dump_pipe_config [i915]] crtc timings: 148352 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5 [ 107.700254] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148352 [ 107.700268] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 107.700281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 107.700295] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 107.700308] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 107.700321] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 107.700336] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 107.700349] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 [ 107.700363] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 107.700376] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 107.700392] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 107.700407] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 107.700426] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 107.700441] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 107.700692] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 107.700711] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 107.700743] [drm:intel_disable_pipe [i915]] disabling pipe A [ 107.711085] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 107.711106] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 107.711125] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 107.711143] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 107.711163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 107.711179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 107.711195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 107.711210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 107.711225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 107.711239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 107.711254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 107.711268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 107.711283] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 107.711298] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 107.711313] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 107.711328] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 107.711345] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 107.711360] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 107.711532] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 107.712097] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 107.713350] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 107.714599] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 107.715840] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 107.717087] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 107.717928] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 107.718834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 107.718850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 107.718866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 107.718882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 107.737596] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 107.737614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 107.755354] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 107.755682] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 [ 107.756119] [drm:intel_enable_pipe [i915]] enabling pipe A [ 107.756142] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 107.756160] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 107.756176] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 107.756194] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 107.756222] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 [ 107.756238] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 107.773095] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 107.773119] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 107.773149] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 112.779169] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 112.831664] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 112.831674] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 112.831707] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 112.831725] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 112.831744] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74250KHz [ 112.831764] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 112.831780] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000 [ 112.831798] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 112.831815] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 112.831832] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 112.831848] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 112.831864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64 [ 112.831879] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 112.831893] [drm:intel_dump_pipe_config [i915]] requested mode: [ 112.831901] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 112.831917] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 112.831924] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 112.831940] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2008 2052 2200 1080 1084 1094 1125, type: 0x40 flags: 0x15 [ 112.831955] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250 [ 112.831970] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 112.831984] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 112.831998] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 112.832029] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 112.832046] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 112.832062] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 112.832079] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 [ 112.832096] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 112.832112] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 112.832131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 112.832149] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 112.832171] [drm:intel_plane_atomic_check_with_state [i915]] Y/Yf tiling not supported in IF-ID mode [ 112.833261] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 112.881871] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 112.881881] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 112.881911] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 112.881928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 112.881948] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74176KHz [ 112.881965] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 112.881981] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000 [ 112.881998] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 112.882015] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 112.882030] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 112.882046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 112.882061] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64 [ 112.882075] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 112.882089] [drm:intel_dump_pipe_config [i915]] requested mode: [ 112.882097] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 112.882111] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 112.882118] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 112.882133] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1920 2008 2052 2200 1080 1084 1094 1125, type: 0x40 flags: 0x15 [ 112.882147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74176 [ 112.882161] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 112.882175] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 112.882188] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 112.882202] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 112.882215] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 112.882229] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 112.882243] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 [ 112.882256] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 112.882269] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 112.882285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 112.882300] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 112.882317] [drm:intel_plane_atomic_check_with_state [i915]] Y/Yf tiling not supported in IF-ID mode [ 112.883380] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 112.931769] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 112.931779] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 112.931815] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 112.931833] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 112.931851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz [ 112.931871] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 112.931888] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 [ 112.931906] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 112.931923] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 112.931940] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 112.931955] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 112.931972] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 [ 112.931987] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 112.932001] [drm:intel_dump_pipe_config [i915]] requested mode: [ 112.932027] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 112.932046] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 112.932056] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 112.932074] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2448 2492 2640 1080 1084 1089 1125, type: 0x40 flags: 0x5 [ 112.932091] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 [ 112.932109] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 112.932123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 112.932137] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 112.932151] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 112.932163] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 112.932177] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 112.932191] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 [ 112.932204] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 112.932217] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 112.932234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 112.932248] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 112.932267] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 112.932282] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 112.932533] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 112.932550] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 112.932579] [drm:intel_disable_pipe [i915]] disabling pipe A [ 112.945831] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 112.945852] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 112.945872] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 112.945889] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 112.945910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 112.945926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 112.945941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 112.945956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 112.945970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 112.945985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 112.945999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 112.946013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 112.946028] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 112.946043] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 112.946058] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 112.946072] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 112.946089] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 112.946104] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 112.946276] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 112.946835] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 112.948085] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 112.949333] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 112.950572] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 112.951820] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 112.952660] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 112.953566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 112.953583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 112.953598] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 112.953614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 112.972392] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 112.972417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 112.990107] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 112.990433] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 [ 112.990858] [drm:intel_enable_pipe [i915]] enabling pipe A [ 112.990879] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 112.990896] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 112.990911] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 112.990930] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 112.990961] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 [ 112.990982] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 113.011135] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 113.011158] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 113.011189] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 118.017183] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 118.074941] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 118.074952] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 118.074983] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 118.075000] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 118.075018] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74250KHz [ 118.075036] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 118.075052] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000 [ 118.075071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 118.075087] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 118.075103] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 118.075118] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 118.075133] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64 [ 118.075147] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 118.075161] [drm:intel_dump_pipe_config [i915]] requested mode: [ 118.075169] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 118.075183] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 118.075189] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 118.075204] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2448 2492 2640 1080 1084 1094 1125, type: 0x40 flags: 0x15 [ 118.075218] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250 [ 118.075232] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 118.075245] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 118.075258] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 118.075272] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 118.075285] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 118.075299] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 118.075312] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 [ 118.075325] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 118.075339] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 118.075355] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 118.075370] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 118.075387] [drm:intel_plane_atomic_check_with_state [i915]] Y/Yf tiling not supported in IF-ID mode [ 118.076557] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 118.125151] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 118.125161] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 118.125192] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 118.125209] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 118.125227] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74250KHz [ 118.125245] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 118.125261] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000 [ 118.125277] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 118.125294] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 118.125309] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 118.125324] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 118.125339] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64 [ 118.125353] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 118.125367] [drm:intel_dump_pipe_config [i915]] requested mode: [ 118.125375] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 118.125388] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 118.125395] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 118.125410] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5 [ 118.125423] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250 [ 118.125437] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 118.125450] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 118.125463] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 118.125477] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 118.125490] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 118.125503] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 118.125517] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 [ 118.125530] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 118.125543] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 118.125559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 118.125574] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 118.125593] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 118.125607] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 118.125857] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 118.125878] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 118.125910] [drm:intel_disable_pipe [i915]] disabling pipe A [ 118.132331] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 118.132351] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 118.132370] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 118.132387] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 118.132407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 118.132423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 118.132438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 118.132453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 118.132468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 118.132482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 118.132496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 118.132510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 118.132525] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 118.132541] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 118.132555] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 118.132569] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 118.132586] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 118.132601] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 118.132689] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 118.133245] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 118.134484] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 118.135759] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 118.136905] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 118.138152] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 118.138989] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 118.139895] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 118.139911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 118.139927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 118.139943] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 118.158606] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 118.158624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 118.177301] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 118.177629] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 118.178062] [drm:intel_enable_pipe [i915]] enabling pipe A [ 118.178085] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 118.178102] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 118.178118] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 118.178137] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 118.178164] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 [ 118.178180] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 118.211747] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 118.211773] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 118.211805] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 123.217180] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 123.267681] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 123.267691] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 123.267722] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 123.267739] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 123.267757] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74176KHz [ 123.267775] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 123.267792] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000 [ 123.267809] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 123.267826] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 123.267841] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 123.267856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 123.267871] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64 [ 123.267885] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 123.267899] [drm:intel_dump_pipe_config [i915]] requested mode: [ 123.267906] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 123.267920] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 123.267927] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 123.267942] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5 [ 123.267956] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74176 [ 123.267969] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 123.267983] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 123.267996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 123.268024] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 123.268044] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 123.268063] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 123.268080] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 [ 123.268100] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 123.268116] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 123.268138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 123.268156] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 123.268180] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 123.268197] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 123.268462] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 123.268483] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 123.268512] [drm:intel_disable_pipe [i915]] disabling pipe A [ 123.279084] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 123.279110] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 123.279130] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 123.279148] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 123.279169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 123.279185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 123.279201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 123.279216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 123.279231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 123.279245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 123.279259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 123.279273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 123.279289] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 123.279304] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 123.279319] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 123.279333] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 123.279350] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 123.279365] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 123.279456] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 123.280025] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 123.281282] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 123.282530] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 123.283772] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 123.285022] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 123.285861] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 123.286768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 123.286784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 123.286799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 123.286816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 123.305490] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 123.305507] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 123.323540] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 123.323867] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 123.324297] [drm:intel_enable_pipe [i915]] enabling pipe A [ 123.324321] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 123.324338] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 123.324354] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 123.324373] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 123.324406] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 [ 123.324426] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 123.357969] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 123.357995] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 123.358027] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 128.364167] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 128.422130] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 128.422165] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 128.422265] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 128.422337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 128.422410] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74250KHz [ 128.422485] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 128.422550] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000 [ 128.422619] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 128.422688] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 128.422752] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 128.422814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 128.422877] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64 [ 128.422937] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 128.422995] [drm:intel_dump_pipe_config [i915]] requested mode: [ 128.423026] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 128.423084] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 128.423113] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 128.423173] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2558 2602 2750 1080 1084 1089 1125, type: 0x40 flags: 0x5 [ 128.423234] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250 [ 128.423292] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 128.423349] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 128.423404] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 128.423460] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 128.423515] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 128.423573] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 128.423630] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 [ 128.423685] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 128.423739] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 128.423806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 128.423867] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 128.423940] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 128.424004] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 128.425289] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 128.425367] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 128.425476] [drm:intel_disable_pipe [i915]] disabling pipe A [ 128.431073] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 128.431115] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 128.431155] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 128.431190] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 128.431230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 128.431264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 128.431296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 128.431327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 128.431358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 128.431387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 128.431417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 128.431446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 128.431478] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 128.431509] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 128.431539] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 128.431570] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 128.431604] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 128.431636] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 128.431745] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 128.432321] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 128.433503] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 128.434737] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 128.435973] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 128.437203] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 128.438033] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 128.438957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 128.438984] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 128.439011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 128.439037] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 128.457590] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 128.457607] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 128.475633] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 128.475960] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 128.476385] [drm:intel_enable_pipe [i915]] enabling pipe A [ 128.476407] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 128.476423] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 128.476439] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 128.476458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 128.476485] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 [ 128.476500] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 128.518341] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 128.518369] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 128.518404] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 133.524226] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 133.578200] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 133.578210] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 133.578243] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 133.578267] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 133.578289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74176KHz [ 133.578309] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 133.578324] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000 [ 133.578341] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 133.578358] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 133.578373] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 133.578388] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 133.578403] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64 [ 133.578417] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 133.578430] [drm:intel_dump_pipe_config [i915]] requested mode: [ 133.578438] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 133.578452] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 133.578459] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 133.578473] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1920 2558 2602 2750 1080 1084 1089 1125, type: 0x40 flags: 0x5 [ 133.578487] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74176 [ 133.578500] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 133.578514] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 133.578527] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 133.578540] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 133.578553] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 133.578567] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 133.578580] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 [ 133.578594] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 133.578607] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 133.578622] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 133.578637] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 133.578656] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 133.578671] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 133.578922] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 133.578944] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 133.578974] [drm:intel_disable_pipe [i915]] disabling pipe A [ 133.603961] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 133.603981] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 133.604001] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 133.604040] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 133.604074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 133.604097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 133.604116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 133.604137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 133.604155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 133.604175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 133.604192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 133.604211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 133.604228] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 133.604249] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 133.604266] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 133.604286] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 133.604308] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 133.604326] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 133.604426] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 133.604990] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 133.606238] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 133.607494] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 133.608683] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 133.609931] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 133.610767] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 133.611673] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 133.611689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 133.611705] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 133.611720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 133.630356] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 133.630373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 133.647997] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 133.648327] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 133.648752] [drm:intel_enable_pipe [i915]] enabling pipe A [ 133.648774] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 133.648791] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 133.648806] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 133.648825] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 133.648853] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 [ 133.648868] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 133.690725] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 133.690752] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 133.690801] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 138.695245] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 138.742696] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 138.742707] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 138.742738] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 138.742755] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 138.742773] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 119000KHz [ 138.742793] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 138.742809] [drm:intel_dp_compute_config [i915]] DP link bw required 357000 available 648000 [ 138.742826] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 138.742842] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 138.742858] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 138.742873] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 138.742888] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 4621501, gmch_n: 8388608, link_m: 192562, link_n: 262144, tu: 64 [ 138.742902] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 138.742916] [drm:intel_dump_pipe_config [i915]] requested mode: [ 138.742924] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 [ 138.742938] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 138.742945] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 [ 138.742959] [drm:intel_dump_pipe_config [i915]] crtc timings: 119000 1680 1728 1760 1840 1050 1053 1059 1080, type: 0x40 flags: 0x9 [ 138.742973] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1680x1050, pixel rate 119000 [ 138.742987] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 138.743001] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 138.743014] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 138.743027] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 138.743040] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 138.743054] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 1920x1080 format = XR24 little-endian (0x34325258) [ 138.743067] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 [ 138.743080] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 138.743093] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 138.743109] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 138.743124] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 138.743143] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 138.743158] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 138.743381] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 138.743404] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 138.743434] [drm:intel_disable_pipe [i915]] disabling pipe A [ 138.780747] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 138.780771] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 138.780795] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 138.780831] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 138.780858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 138.780880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 138.780901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 138.780921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 138.780941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 138.780960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 138.780979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 138.780997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 138.781017] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 138.781038] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 138.781057] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 138.781076] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 138.781099] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 138.781120] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 138.781219] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 138.781785] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 138.783016] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 138.784249] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 138.785476] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 138.786705] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 138.787533] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 138.788455] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 138.788480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 138.788504] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 138.788528] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 138.807185] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 138.807212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 138.824913] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 138.825242] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 [ 138.825677] [drm:intel_enable_pipe [i915]] enabling pipe A [ 138.825700] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 138.825719] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 138.825737] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 138.825758] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 138.825799] [drm:intel_fbc_enable [i915]] reserved 14246400 bytes of contiguous stolen space for FBC, threshold: 1 [ 138.825814] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 138.842686] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 138.842709] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 138.842739] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 143.847411] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 143.895154] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 143.895165] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 143.895198] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 143.895216] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 143.895235] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 135000KHz [ 143.895257] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 [ 143.895273] [drm:intel_dp_compute_config [i915]] DP link bw required 405000 available 648000 [ 143.895291] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 143.895308] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 143.895324] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 143.895340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 143.895356] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5242880, gmch_n: 8388608, link_m: 218453, link_n: 262144, tu: 64 [ 143.895371] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 143.895385] [drm:intel_dump_pipe_config [i915]] requested mode: [ 143.895393] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 143.895409] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 143.895416] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 143.895432] [drm:intel_dump_pipe_config [i915]] crtc timings: 135000 1280 1296 1440 1688 1024 1025 1028 1066, type: 0x40 flags: 0x5 [ 143.895447] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x1024, pixel rate 135000 [ 143.895462] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 143.895476] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 143.895490] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 143.895504] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 143.895518] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 143.895533] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 1680x1050 format = XR24 little-endian (0x34325258) [ 143.895547] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1680+1050 dst 0x0+1680+1050 [ 143.895561] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 143.895575] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 143.895591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 143.895607] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 143.895627] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 143.895643] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 143.895817] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 143.895839] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 143.895865] [drm:intel_disable_pipe [i915]] disabling pipe A [ 143.903073] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 143.903093] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 143.903113] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 143.903130] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 143.903149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 143.903165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 143.903180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 143.903195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 143.903210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 143.903224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 143.903238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 143.903252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 143.903268] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 143.903283] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 143.903297] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 143.903312] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 143.903328] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 143.903343] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 143.903512] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 143.904072] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 143.905311] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 143.906552] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 143.907795] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 143.909044] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 143.909882] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 143.910789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 143.910805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 143.910821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 143.910836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 143.929541] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 143.929558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 143.947514] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 143.947841] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 [ 143.948274] [drm:intel_enable_pipe [i915]] enabling pipe A [ 143.948295] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 143.948312] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 143.948328] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 143.948347] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 143.948374] [drm:intel_fbc_enable [i915]] reserved 10485760 bytes of contiguous stolen space for FBC, threshold: 1 [ 143.948390] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 143.961911] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 143.961934] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 143.961965] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 148.966154] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 149.019382] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 149.019393] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 149.019424] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 149.019441] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 149.019459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 108000KHz [ 149.019480] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 149.019496] [drm:intel_dp_compute_config [i915]] DP link bw required 324000 available 324000 [ 149.019513] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 149.019529] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 149.019545] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 149.019560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 149.019574] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4194304, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64 [ 149.019589] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 149.019603] [drm:intel_dump_pipe_config [i915]] requested mode: [ 149.019610] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 149.019624] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 149.019631] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 149.019646] [drm:intel_dump_pipe_config [i915]] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x40 flags: 0x5 [ 149.019660] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x1024, pixel rate 108000 [ 149.019673] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 149.019686] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 149.019699] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 149.019713] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 149.019726] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 149.019740] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 1280x1024 format = XR24 little-endian (0x34325258) [ 149.019753] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1280+1024 dst 0x0+1280+1024 [ 149.019766] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 149.019779] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 149.019794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 149.019810] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 149.019829] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 149.019844] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 149.020013] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 149.020041] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 149.020070] [drm:intel_disable_pipe [i915]] disabling pipe A [ 149.028344] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 149.028364] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 149.028383] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 149.028400] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 149.028420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 149.028436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 149.028451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 149.028466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 149.028480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 149.028494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 149.028508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 149.028522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 149.028537] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 149.028552] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 149.028567] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 149.028581] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 149.028598] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 149.028613] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 149.028782] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 149.029338] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 149.030580] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 149.031830] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 149.033069] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 149.034316] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 149.035153] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 149.036063] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 149.036082] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 149.036102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 149.036119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 149.054780] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 149.054798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 149.072466] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 149.072792] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 149.073217] [drm:intel_enable_pipe [i915]] enabling pipe A [ 149.073239] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 149.073255] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 149.073271] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 149.073289] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 149.073317] [drm:intel_fbc_enable [i915]] reserved 10485760 bytes of contiguous stolen space for FBC, threshold: 1 [ 149.073332] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 149.090149] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 149.090172] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 149.090203] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 154.094982] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 154.145766] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 154.145776] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 154.145807] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 154.145824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 154.145842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 88750KHz [ 154.145863] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 154.145879] [drm:intel_dp_compute_config [i915]] DP link bw required 266250 available 324000 [ 154.145896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 154.145912] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 154.145928] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 154.145943] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 154.145958] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3446708, gmch_n: 4194304, link_m: 143612, link_n: 262144, tu: 64 [ 154.145972] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 154.145986] [drm:intel_dump_pipe_config [i915]] requested mode: [ 154.145993] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 [ 154.146007] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 154.146015] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 [ 154.146029] [drm:intel_dump_pipe_config [i915]] crtc timings: 88750 1440 1488 1520 1600 900 903 909 926, type: 0x40 flags: 0x9 [ 154.146043] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1440x900, pixel rate 88750 [ 154.146057] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 154.146071] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 154.146084] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 154.146098] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 154.146110] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 154.146124] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 1280x1024 format = XR24 little-endian (0x34325258) [ 154.146138] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1280+1024 dst 0x0+1280+1024 [ 154.146151] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 154.146164] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 154.146180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 154.146194] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 154.146214] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 154.146229] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 154.146405] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 154.146429] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 154.146460] [drm:intel_disable_pipe [i915]] disabling pipe A [ 154.157657] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 154.157678] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 154.157698] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 154.157715] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 154.157735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 154.157752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 154.157768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 154.157783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 154.157798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 154.157812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 154.157826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 154.157840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 154.157855] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 154.157871] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 154.157885] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 154.157900] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 154.157917] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 154.157932] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 154.158023] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 154.158583] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 154.159832] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 154.161089] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 154.162333] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 154.163582] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 154.164337] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 154.165246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 154.165262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 154.165278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 154.165293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 154.183951] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 154.183968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 154.201636] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 154.201963] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 154.202388] [drm:intel_enable_pipe [i915]] enabling pipe A [ 154.202410] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 154.202427] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 154.202443] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 154.202462] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 154.202490] [drm:intel_fbc_enable [i915]] reserved 10368000 bytes of contiguous stolen space for FBC, threshold: 1 [ 154.202506] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 154.219357] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 154.219380] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 154.219410] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 159.223353] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 159.299511] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 159.299546] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 159.299648] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 159.299719] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 159.299792] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 108000KHz [ 159.299878] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 159.299943] [drm:intel_dp_compute_config [i915]] DP link bw required 324000 available 324000 [ 159.300011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 159.300147] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 159.300248] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 159.300329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 159.300420] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4194304, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64 [ 159.300498] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 159.300584] [drm:intel_dump_pipe_config [i915]] requested mode: [ 159.300621] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 [ 159.300707] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 159.300747] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 [ 159.300832] [drm:intel_dump_pipe_config [i915]] crtc timings: 108000 1280 1376 1488 1800 960 961 964 1000, type: 0x40 flags: 0x5 [ 159.300901] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x960, pixel rate 108000 [ 159.300982] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 159.301050] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 159.301128] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 159.301197] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 159.301274] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 159.301343] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 1440x900 format = XR24 little-endian (0x34325258) [ 159.301422] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1440+900 dst 0x0+1440+900 [ 159.301488] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 159.301566] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 159.301644] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 159.301728] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 159.301826] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 159.301903] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 159.302724] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 159.302788] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 159.302864] [drm:intel_disable_pipe [i915]] disabling pipe A [ 159.311103] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 159.311145] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 159.311185] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 159.311221] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 159.311262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 159.311296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 159.311328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 159.311360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 159.311392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 159.311422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 159.311453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 159.311484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 159.311517] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 159.311549] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 159.311580] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 159.311611] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 159.311646] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 159.311679] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 159.311793] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 159.312370] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 159.313547] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 159.314778] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 159.316002] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 159.317248] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 159.318076] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 159.318999] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 159.319026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 159.319052] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 159.319078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 159.337567] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 159.337585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 159.355253] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 159.355580] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 159.356006] [drm:intel_enable_pipe [i915]] enabling pipe A [ 159.356033] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 159.356051] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 159.356069] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 159.356096] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 159.356127] [drm:intel_fbc_enable [i915]] reserved 9830400 bytes of contiguous stolen space for FBC, threshold: 1 [ 159.356143] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 159.372968] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 159.372991] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 159.373022] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 164.376750] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 164.426276] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 164.426286] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 164.426319] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 164.426337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 164.426356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 108000KHz [ 164.426378] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 164.426395] [drm:intel_dp_compute_config [i915]] DP link bw required 324000 available 324000 [ 164.426412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 164.426429] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 164.426446] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 164.426461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 164.426477] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4194304, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64 [ 164.426492] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 164.426506] [drm:intel_dump_pipe_config [i915]] requested mode: [ 164.426514] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 164.426529] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 164.426536] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 164.426553] [drm:intel_dump_pipe_config [i915]] crtc timings: 108000 1152 1216 1344 1600 864 865 868 900, type: 0x40 flags: 0x5 [ 164.426567] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1152x864, pixel rate 108000 [ 164.426582] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 164.426596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 164.426611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 164.426626] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 164.426640] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 164.426655] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 1280x960 format = XR24 little-endian (0x34325258) [ 164.426669] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1280+960 dst 0x0+1280+960 [ 164.426683] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 164.426697] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 164.426714] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 164.426730] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 164.426749] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 164.426765] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 164.426908] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 164.426931] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 164.426962] [drm:intel_disable_pipe [i915]] disabling pipe A [ 164.440369] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 164.440389] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 164.440409] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 164.440427] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 164.440447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 164.440463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 164.440478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 164.440493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 164.440508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 164.440523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 164.440537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 164.440551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 164.440566] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 164.440582] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 164.440596] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 164.440611] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 164.440628] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 164.440643] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 164.440734] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 164.441294] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 164.442542] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 164.443802] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 164.444954] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 164.446209] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 164.447048] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 164.447956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 164.447972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 164.447987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 164.448005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 164.466895] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 164.466912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 164.485556] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 164.485883] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 164.486309] [drm:intel_enable_pipe [i915]] enabling pipe A [ 164.486332] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 164.486348] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 164.486364] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 164.486383] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 164.486410] [drm:intel_fbc_enable [i915]] reserved 7962624 bytes of contiguous stolen space for FBC, threshold: 1 [ 164.486426] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 164.499923] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 164.499946] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 164.499977] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 169.503506] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 169.556531] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 169.556541] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 169.556574] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 169.556592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 169.556611] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74250KHz [ 169.556630] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 169.556646] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000 [ 169.556664] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 169.556681] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 169.556698] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 169.556714] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 169.556730] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64 [ 169.556745] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 169.556760] [drm:intel_dump_pipe_config [i915]] requested mode: [ 169.556768] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 169.556783] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 169.556790] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 169.556806] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1280 1390 1430 1650 720 725 730 750, type: 0x40 flags: 0x5 [ 169.556821] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x720, pixel rate 74250 [ 169.556835] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 169.556850] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 169.556864] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 169.556879] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 169.556892] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 169.556907] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 1152x864 format = XR24 little-endian (0x34325258) [ 169.556921] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1152+864 dst 0x0+1152+864 [ 169.556935] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 169.556949] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 169.556967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 169.556982] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 169.557002] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 169.557018] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 169.557157] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 169.557179] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 169.557206] [drm:intel_disable_pipe [i915]] disabling pipe A [ 169.566997] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 169.567018] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 169.567038] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 169.567055] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 169.567075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 169.567091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 169.567106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 169.567121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 169.567135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 169.567149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 169.567163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 169.567177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 169.567192] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 169.567207] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 169.567222] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 169.567236] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 169.567253] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 169.567268] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 169.567360] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 169.567919] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 169.569178] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 169.570426] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 169.571669] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 169.572825] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 169.573662] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 169.574568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 169.574585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 169.574600] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 169.574616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 169.593267] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 169.593284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 169.611925] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 169.612254] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 169.612679] [drm:intel_enable_pipe [i915]] enabling pipe A [ 169.612700] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 169.612717] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 169.612733] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 169.612752] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 169.612779] [drm:intel_fbc_enable [i915]] reserved 7372800 bytes of contiguous stolen space for FBC, threshold: 1 [ 169.612795] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 169.629609] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 169.629633] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 169.629663] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 174.633183] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 174.682003] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 174.682013] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 174.682044] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 174.682061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 174.682079] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74176KHz [ 174.682096] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 174.682112] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000 [ 174.682129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 174.682145] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 174.682161] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 174.682175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 174.682190] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64 [ 174.682204] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 174.682218] [drm:intel_dump_pipe_config [i915]] requested mode: [ 174.682225] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 174.682240] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 174.682247] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 174.682261] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1280 1390 1430 1650 720 725 730 750, type: 0x40 flags: 0x5 [ 174.682275] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x720, pixel rate 74176 [ 174.682289] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 174.682302] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 174.682316] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 174.682329] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 174.682342] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 174.682356] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 1280x720 format = XR24 little-endian (0x34325258) [ 174.682370] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1280+720 dst 0x0+1280+720 [ 174.682383] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 174.682396] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 174.682412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 174.682427] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 174.682446] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 174.682461] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 174.682599] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 174.682621] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 174.682652] [drm:intel_disable_pipe [i915]] disabling pipe A [ 174.696386] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 174.696406] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 174.696425] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 174.696443] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 174.696463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 174.696479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 174.696495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 174.696510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 174.696525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 174.696539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 174.696553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 174.696567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 174.696582] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 174.696598] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 174.696613] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 174.696628] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 174.696645] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 174.696660] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 174.696751] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 174.697312] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 174.698561] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 174.699810] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 174.700962] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 174.702209] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 174.703042] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 174.703949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 174.703965] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 174.703981] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 174.703997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 174.722697] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 174.722714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 174.741361] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 174.741688] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 174.742114] [drm:intel_enable_pipe [i915]] enabling pipe A [ 174.742137] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 174.742153] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 174.742169] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 174.742188] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 174.742216] [drm:intel_fbc_enable [i915]] reserved 7372800 bytes of contiguous stolen space for FBC, threshold: 1 [ 174.742231] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 174.759066] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 174.759089] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 174.759120] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 179.762469] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 179.816495] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 179.816532] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 179.816640] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 179.816716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 179.816795] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74250KHz [ 179.816874] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 179.816945] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000 [ 179.817021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 179.817094] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 179.817164] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 179.817231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 179.817300] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64 [ 179.817364] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 179.817426] [drm:intel_dump_pipe_config [i915]] requested mode: [ 179.817459] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 179.817523] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 179.817553] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 179.817620] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1280 1720 1760 1980 720 725 730 750, type: 0x40 flags: 0x5 [ 179.817682] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x720, pixel rate 74250 [ 179.817744] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 179.817804] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 179.817864] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 179.817925] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 179.817984] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 179.818046] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 1280x720 format = XR24 little-endian (0x34325258) [ 179.818107] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1280+720 dst 0x0+1280+720 [ 179.818166] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 179.818226] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 179.818297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 179.818362] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 179.818440] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 179.818532] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 179.819170] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 179.819272] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 179.819382] [drm:intel_disable_pipe [i915]] disabling pipe A [ 179.832358] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 179.832400] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 179.832440] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 179.832476] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 179.832517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 179.832551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 179.832584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 179.832615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 179.832646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 179.832676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 179.832706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 179.832735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 179.832768] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 179.832801] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 179.832832] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 179.832862] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 179.832898] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 179.832930] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 179.833045] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 179.833619] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 179.834853] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 179.836102] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 179.837325] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 179.838560] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 179.839399] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 179.840349] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 179.840384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 179.840417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 179.840449] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 179.859081] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 179.859106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 179.877572] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 179.877898] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 179.878323] [drm:intel_enable_pipe [i915]] enabling pipe A [ 179.878344] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 179.878361] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 179.878377] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 179.878395] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 179.878422] [drm:intel_fbc_enable [i915]] reserved 7372800 bytes of contiguous stolen space for FBC, threshold: 1 [ 179.878437] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 179.898594] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 179.898618] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 179.898648] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 184.901867] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 184.949297] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 184.949307] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 184.949338] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 184.949355] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 184.949373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 54000KHz [ 184.949391] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 184.949408] [drm:intel_dp_compute_config [i915]] DP link bw required 162000 available 162000 [ 184.949425] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 184.949442] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 184.949457] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 184.949472] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 184.949488] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 2097152, gmch_n: 2097152, link_m: 87381, link_n: 262144, tu: 64 [ 184.949502] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 184.949515] [drm:intel_dump_pipe_config [i915]] requested mode: [ 184.949523] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa [ 184.949537] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 184.949544] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa [ 184.949559] [drm:intel_dump_pipe_config [i915]] crtc timings: 54000 1440 1464 1592 1728 576 581 586 625, type: 0x40 flags: 0xa [ 184.949573] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1440x576, pixel rate 54000 [ 184.949587] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 184.949600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 184.949613] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 184.949627] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 184.949640] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 184.949654] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 1280x720 format = XR24 little-endian (0x34325258) [ 184.949667] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1280+720 dst 0x0+1280+720 [ 184.949681] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 184.949694] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 184.949710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 184.949724] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 184.949743] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 184.949758] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 184.949884] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 184.949906] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 184.949936] [drm:intel_disable_pipe [i915]] disabling pipe A [ 184.959071] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 184.959091] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 184.959110] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 184.959127] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 184.959147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 184.959163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 184.959179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 184.959194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 184.959208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 184.959222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 184.959236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 184.959251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 184.959266] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 184.959281] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 184.959296] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 184.959310] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 184.959327] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 184.959342] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 184.959430] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 184.959987] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 184.961236] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 184.962485] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 184.963725] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 184.964965] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 184.965802] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 184.966709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 184.966725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 184.966740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 184.966756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 184.985537] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 184.985555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 185.003108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 185.003435] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 185.003859] [drm:intel_enable_pipe [i915]] enabling pipe A [ 185.003881] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 185.003897] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 185.003913] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 185.003932] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 185.003959] [drm:intel_fbc_enable [i915]] reserved 6635520 bytes of contiguous stolen space for FBC, threshold: 1 [ 185.003975] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 185.024097] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 185.024118] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 185.024148] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 190.027200] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 190.102978] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 190.103012] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 190.103113] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 190.103185] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 190.103259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 78750KHz [ 190.103345] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 190.103411] [drm:intel_dp_compute_config [i915]] DP link bw required 236250 available 324000 [ 190.103480] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 190.103549] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 190.103613] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 190.103674] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 190.103736] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3058346, gmch_n: 4194304, link_m: 127431, link_n: 262144, tu: 64 [ 190.103797] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 190.103855] [drm:intel_dump_pipe_config [i915]] requested mode: [ 190.103886] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 190.103945] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 190.103974] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 190.104036] [drm:intel_dump_pipe_config [i915]] crtc timings: 78750 1024 1040 1136 1312 768 769 772 800, type: 0x40 flags: 0x5 [ 190.104156] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 78750 [ 190.104232] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 190.104324] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 190.104393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 190.104466] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 190.104549] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 190.104622] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 1440x576 format = XR24 little-endian (0x34325258) [ 190.104706] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1440+576 dst 0x0+1440+576 [ 190.104774] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 190.104829] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 190.104893] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 190.104942] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 190.105013] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 190.105063] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 190.105432] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 190.105495] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 190.105572] [drm:intel_disable_pipe [i915]] disabling pipe A [ 190.124372] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 190.124406] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 190.124438] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 190.124467] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 190.124500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 190.124527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 190.124552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 190.124577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 190.124601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 190.124625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 190.124649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 190.124673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 190.124698] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 190.124724] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 190.124748] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 190.124772] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 190.124801] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 190.124826] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 190.124932] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 190.125500] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 190.126737] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 190.127970] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 190.129193] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 190.130424] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 190.131251] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 190.132191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 190.132219] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 190.132245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 190.132271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 190.150878] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 190.150899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 190.168525] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 190.168852] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 190.169276] [drm:intel_enable_pipe [i915]] enabling pipe A [ 190.169297] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 190.169314] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 190.169330] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 190.169348] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 190.169376] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1 [ 190.169392] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 190.182878] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 190.182902] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 190.182932] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 195.185796] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 195.232952] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 195.232962] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 195.232997] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 195.233015] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 195.233034] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 75000KHz [ 195.233056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 195.233073] [drm:intel_dp_compute_config [i915]] DP link bw required 225000 available 324000 [ 195.233091] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 195.233109] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 195.233125] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 195.233141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 195.233157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2912711, gmch_n: 4194304, link_m: 121362, link_n: 262144, tu: 64 [ 195.233172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 195.233186] [drm:intel_dump_pipe_config [i915]] requested mode: [ 195.233194] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 195.233209] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 195.233217] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 195.233232] [drm:intel_dump_pipe_config [i915]] crtc timings: 75000 1024 1048 1184 1328 768 771 777 806, type: 0x40 flags: 0xa [ 195.233247] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 75000 [ 195.233262] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 195.233276] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 195.233290] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 195.233305] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 195.233319] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 195.233333] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 1024x768 format = XR24 little-endian (0x34325258) [ 195.233348] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1024+768 dst 0x0+1024+768 [ 195.233362] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 195.233376] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 195.233393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 195.233408] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 195.233429] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 195.233444] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 195.233563] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 195.233586] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 195.233613] [drm:intel_disable_pipe [i915]] disabling pipe A [ 195.234488] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 195.234507] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 195.234526] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 195.234543] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 195.234561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 195.234578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 195.234593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 195.234608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 195.234623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 195.234638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 195.234652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 195.234665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 195.234680] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 195.234695] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 195.234710] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 195.234724] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 195.234741] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 195.234756] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 195.234842] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 195.235399] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 195.236648] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 195.237888] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 195.239119] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 195.240361] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 195.241190] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 195.242094] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 195.242111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 195.242126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 195.242141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 195.260686] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 195.260703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 195.278336] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 195.278663] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 195.279087] [drm:intel_enable_pipe [i915]] enabling pipe A [ 195.279108] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 195.279125] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 195.279141] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 195.279159] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 195.279183] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1 [ 195.279198] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 195.293615] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 195.293639] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 195.293669] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 200.296768] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 200.343893] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 200.343903] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 200.343934] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 200.343951] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 200.343969] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 65000KHz [ 200.343990] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 200.344006] [drm:intel_dp_compute_config [i915]] DP link bw required 195000 available 324000 [ 200.344034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 200.344053] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 200.344076] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 200.344095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 200.344114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2524349, gmch_n: 4194304, link_m: 105181, link_n: 262144, tu: 64 [ 200.344134] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 200.344151] [drm:intel_dump_pipe_config [i915]] requested mode: [ 200.344162] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 200.344180] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 200.344191] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 200.344207] [drm:intel_dump_pipe_config [i915]] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa [ 200.344224] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 65000 [ 200.344243] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 200.344258] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 200.344276] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 200.344292] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 200.344310] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 200.344327] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 1024x768 format = XR24 little-endian (0x34325258) [ 200.344345] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1024+768 dst 0x0+1024+768 [ 200.344360] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 200.344377] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 200.344396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 200.344415] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 200.344438] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 200.344456] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 200.344585] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 200.344607] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 200.344636] [drm:intel_disable_pipe [i915]] disabling pipe A [ 200.346240] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 200.346259] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 200.346278] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 200.346295] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 200.346314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 200.346329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 200.346345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 200.346359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 200.346374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 200.346388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 200.346402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 200.346416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 200.346431] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 200.346446] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 200.346461] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 200.346475] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 200.346492] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 200.346507] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 200.346593] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 200.347147] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 200.348388] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 200.349629] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 200.350864] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 200.352105] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 200.352936] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 200.353841] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 200.353857] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 200.353872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 200.353888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 200.372463] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 200.372481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 200.391136] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 200.391462] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 200.391886] [drm:intel_enable_pipe [i915]] enabling pipe A [ 200.391907] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 200.391923] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 200.391939] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 200.391958] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 200.391981] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1 [ 200.391997] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 200.408795] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 200.408818] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 200.408848] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 205.411054] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 205.480266] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 205.480275] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 205.480307] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 205.480324] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 205.480342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 54054KHz [ 205.480360] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 205.480376] [drm:intel_dp_compute_config [i915]] DP link bw required 162162 available 324000 [ 205.480393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 205.480410] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 205.480425] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 205.480440] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 205.480456] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2099249, gmch_n: 4194304, link_m: 87468, link_n: 262144, tu: 64 [ 205.480470] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 205.480484] [drm:intel_dump_pipe_config [i915]] requested mode: [ 205.480492] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa [ 205.480506] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 205.480513] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa [ 205.480528] [drm:intel_dump_pipe_config [i915]] crtc timings: 54054 1440 1472 1596 1716 480 489 495 525, type: 0x40 flags: 0xa [ 205.480542] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1440x480, pixel rate 54054 [ 205.480555] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 205.480569] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 205.480583] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 205.480596] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 205.480609] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 205.480623] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 1024x768 format = XR24 little-endian (0x34325258) [ 205.480637] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1024+768 dst 0x0+1024+768 [ 205.480650] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 205.480664] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 205.480680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 205.480695] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 205.480713] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 205.480728] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 205.480837] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 205.480860] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 205.480890] [drm:intel_disable_pipe [i915]] disabling pipe A [ 205.493637] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 205.493658] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 205.493677] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 205.493694] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 205.493715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 205.493731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 205.493747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 205.493761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 205.493775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 205.493790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 205.493804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 205.493817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 205.493833] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 205.493848] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 205.493863] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 205.493877] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 205.493894] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 205.493909] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 205.494000] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 205.494560] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 205.495809] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 205.497068] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 205.498309] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 205.499556] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 205.500250] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 205.501167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 205.501185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 205.501200] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 205.501216] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 205.519859] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 205.519876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 205.538516] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 205.538843] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 205.539268] [drm:intel_enable_pipe [i915]] enabling pipe A [ 205.539290] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 205.539307] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 205.539323] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 205.539341] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 205.539369] [drm:intel_fbc_enable [i915]] reserved 5529600 bytes of contiguous stolen space for FBC, threshold: 1 [ 205.539385] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 205.556217] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 205.556240] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 205.556271] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 210.559032] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 210.596830] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 210.596864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 210.596965] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 210.597037] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 210.597111] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 54000KHz [ 210.597186] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 210.597252] [drm:intel_dp_compute_config [i915]] DP link bw required 162000 available 162000 [ 210.597323] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 210.597391] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 210.597457] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 210.597520] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 210.597584] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 2097152, gmch_n: 2097152, link_m: 87381, link_n: 262144, tu: 64 [ 210.597645] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 210.597705] [drm:intel_dump_pipe_config [i915]] requested mode: [ 210.597736] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa [ 210.597796] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 210.597825] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa [ 210.597887] [drm:intel_dump_pipe_config [i915]] crtc timings: 54000 1440 1472 1596 1716 480 489 495 525, type: 0x40 flags: 0xa [ 210.597946] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1440x480, pixel rate 54000 [ 210.598004] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 210.598061] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 210.598117] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 210.598174] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 210.598229] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 210.598288] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 1440x480 format = XR24 little-endian (0x34325258) [ 210.598369] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1440+480 dst 0x0+1440+480 [ 210.598426] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 210.598483] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 210.598551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 210.598613] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 210.598690] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 210.598755] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 210.599267] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 210.599370] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 210.599482] [drm:intel_disable_pipe [i915]] disabling pipe A [ 210.607089] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 210.607144] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 210.607196] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 210.607244] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 210.607298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 210.607343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 210.607386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 210.607429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 210.607469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 210.607509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 210.607549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 210.607587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 210.607631] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 210.607673] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 210.607715] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 210.607755] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 210.607803] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 210.607846] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 210.607973] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 210.608575] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 210.609823] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 210.611071] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 210.612312] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 210.613557] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 210.614415] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 210.615369] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 210.615415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 210.615458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 210.615503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 210.634354] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 210.634384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 210.651947] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 210.652265] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 210.652696] [drm:intel_enable_pipe [i915]] enabling pipe A [ 210.652719] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 210.652737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 210.652753] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 210.652772] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 210.652799] [drm:intel_fbc_enable [i915]] reserved 5529600 bytes of contiguous stolen space for FBC, threshold: 1 [ 210.652815] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 210.669642] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 210.669665] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 210.669696] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 215.671210] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 215.710080] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 215.710090] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 215.710121] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 215.710138] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 215.710156] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 57284KHz [ 215.710177] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 [ 215.710192] [drm:intel_dp_compute_config [i915]] DP link bw required 171852 available 324000 [ 215.710209] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 215.710226] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 215.710241] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 215.710255] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 215.710270] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2224689, gmch_n: 4194304, link_m: 92695, link_n: 262144, tu: 64 [ 215.710284] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 215.710297] [drm:intel_dump_pipe_config [i915]] requested mode: [ 215.710304] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa [ 215.710318] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 215.710325] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa [ 215.710340] [drm:intel_dump_pipe_config [i915]] crtc timings: 57284 832 864 928 1152 624 625 628 667, type: 0x40 flags: 0xa [ 215.710353] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 832x624, pixel rate 57284 [ 215.710366] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 215.710379] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 215.710392] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 215.710405] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 215.710418] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 215.710432] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 1440x480 format = XR24 little-endian (0x34325258) [ 215.710445] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1440+480 dst 0x0+1440+480 [ 215.710459] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 215.710472] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 215.710488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 215.710503] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 215.710521] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 215.710536] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 215.710632] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 215.710656] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 215.710685] [drm:intel_disable_pipe [i915]] disabling pipe A [ 215.727155] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 215.727176] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 215.727195] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 215.727213] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 215.727233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 215.727249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 215.727264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 215.727279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 215.727294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 215.727308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 215.727322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 215.727336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 215.727352] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 215.727367] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 215.727382] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 215.727397] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 215.727414] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 215.727429] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 215.727520] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 215.728087] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 215.729341] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 215.730590] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 215.731829] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 215.733081] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 215.733923] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 215.734830] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 215.734846] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 215.734861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 215.734877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 215.753580] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 215.753598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 215.772337] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 215.772663] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 2 [ 215.773088] [drm:intel_enable_pipe [i915]] enabling pipe A [ 215.773110] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 215.773127] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 215.773142] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 215.773161] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 215.773189] [drm:intel_fbc_enable [i915]] reserved 4153344 bytes of contiguous stolen space for FBC, threshold: 1 [ 215.773205] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 215.786770] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 215.786793] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 215.786824] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 220.789036] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 220.824469] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 220.824479] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 220.824513] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 220.824530] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 220.824549] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 49500KHz [ 220.824570] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 220.824585] [drm:intel_dp_compute_config [i915]] DP link bw required 148500 available 162000 [ 220.824602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 220.824618] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 220.824634] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 220.824649] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 220.824664] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1922389, gmch_n: 2097152, link_m: 80099, link_n: 262144, tu: 64 [ 220.824679] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 220.824692] [drm:intel_dump_pipe_config [i915]] requested mode: [ 220.824700] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 220.824714] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 220.824721] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 220.824735] [drm:intel_dump_pipe_config [i915]] crtc timings: 49500 800 816 896 1056 600 601 604 625, type: 0x40 flags: 0x5 [ 220.824749] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 800x600, pixel rate 49500 [ 220.824763] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 220.824776] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 220.824789] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 220.824802] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 220.824815] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 220.824829] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 832x624 format = XR24 little-endian (0x34325258) [ 220.824843] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+832+624 dst 0x0+832+624 [ 220.824856] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 220.824869] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 220.824885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 220.824900] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 220.824918] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 220.824933] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 220.825025] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 220.825048] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 220.825107] [drm:intel_disable_pipe [i915]] disabling pipe A [ 220.830996] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 220.831016] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 220.831035] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 220.831052] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 220.831072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 220.831088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 220.831103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 220.831118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 220.831132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 220.831147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 220.831161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 220.831175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 220.831190] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 220.831205] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 220.831220] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 220.831234] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 220.831251] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 220.831266] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 220.831353] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 220.831909] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 220.833147] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 220.834387] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 220.835621] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 220.836777] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 220.837613] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 220.838520] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 220.838536] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 220.838552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 220.838567] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 220.857184] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 220.857201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 220.874864] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 220.875191] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 220.875614] [drm:intel_enable_pipe [i915]] enabling pipe A [ 220.875636] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 220.875653] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 220.875668] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 220.875687] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 220.875715] [drm:intel_fbc_enable [i915]] reserved 3840000 bytes of contiguous stolen space for FBC, threshold: 1 [ 220.875730] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 220.889198] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 220.889221] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 220.889252] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 225.890900] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 225.926988] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 225.926998] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 225.927033] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 225.927084] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 225.927102] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 50000KHz [ 225.927122] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 225.927138] [drm:intel_dp_compute_config [i915]] DP link bw required 150000 available 162000 [ 225.927155] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 225.927171] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 225.927187] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 225.927202] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 225.927217] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1941807, gmch_n: 2097152, link_m: 80908, link_n: 262144, tu: 64 [ 225.927231] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 225.927244] [drm:intel_dump_pipe_config [i915]] requested mode: [ 225.927252] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 225.927265] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 225.927272] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 225.927287] [drm:intel_dump_pipe_config [i915]] crtc timings: 50000 800 856 976 1040 600 637 643 666, type: 0x40 flags: 0x5 [ 225.927300] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 800x600, pixel rate 50000 [ 225.927314] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 225.927327] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 225.927340] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 225.927353] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 225.927366] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 225.927380] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 800x600 format = XR24 little-endian (0x34325258) [ 225.927393] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+800+600 dst 0x0+800+600 [ 225.927406] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 225.927419] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 225.927435] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 225.927449] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 225.927468] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 225.927483] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 225.927574] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 225.927597] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 225.927626] [drm:intel_disable_pipe [i915]] disabling pipe A [ 225.929326] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 225.929345] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 225.929363] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 225.929380] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 225.929398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 225.929415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 225.929430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 225.929445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 225.929460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 225.929474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 225.929488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 225.929502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 225.929517] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 225.929532] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 225.929547] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 225.929561] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 225.929578] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 225.929593] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 225.929761] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 225.930316] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 225.931556] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 225.932639] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 225.933869] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 225.935107] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 225.935936] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 225.936840] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 225.936857] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 225.936873] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 225.936888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 225.955505] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 225.955522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 225.973081] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 225.973408] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 225.973832] [drm:intel_enable_pipe [i915]] enabling pipe A [ 225.973853] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 225.973870] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 225.973886] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 225.973904] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 225.973928] [drm:intel_fbc_enable [i915]] reserved 3840000 bytes of contiguous stolen space for FBC, threshold: 1 [ 225.973944] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 225.987966] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 225.987989] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 225.988038] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 230.990228] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 231.024531] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 231.024541] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 231.024575] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 231.024593] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 231.024611] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 40000KHz [ 231.024633] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 231.024649] [drm:intel_dp_compute_config [i915]] DP link bw required 120000 available 162000 [ 231.024666] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 231.024683] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 231.024699] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 231.024714] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 231.024729] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1553445, gmch_n: 2097152, link_m: 64726, link_n: 262144, tu: 64 [ 231.024744] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 231.024758] [drm:intel_dump_pipe_config [i915]] requested mode: [ 231.024766] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 231.024780] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 231.024787] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 231.024802] [drm:intel_dump_pipe_config [i915]] crtc timings: 40000 800 840 968 1056 600 601 605 628, type: 0x40 flags: 0x5 [ 231.024817] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 800x600, pixel rate 40000 [ 231.024831] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 231.024844] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 231.024858] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 231.024873] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 231.024886] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 231.024900] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 800x600 format = XR24 little-endian (0x34325258) [ 231.024914] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+800+600 dst 0x0+800+600 [ 231.024928] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 231.024941] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 231.024958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 231.024973] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 231.025022] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 231.025038] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 231.025132] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 231.025155] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 231.025184] [drm:intel_disable_pipe [i915]] disabling pipe A [ 231.031078] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 231.031098] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 231.031117] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 231.031135] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 231.031155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 231.031171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 231.031186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 231.031201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 231.031215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 231.031230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 231.031244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 231.031258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 231.031273] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 231.031288] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 231.031303] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 231.031317] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 231.031334] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 231.031349] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 231.031518] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 231.032077] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 231.033314] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 231.034551] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 231.035781] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 231.037027] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 231.037873] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 231.038779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 231.038796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 231.038811] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 231.038827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 231.057458] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 231.057476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 231.075147] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 231.075473] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 231.075898] [drm:intel_enable_pipe [i915]] enabling pipe A [ 231.075919] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 231.075936] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 231.075952] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 231.075970] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 231.075997] [drm:intel_fbc_enable [i915]] reserved 3840000 bytes of contiguous stolen space for FBC, threshold: 1 [ 231.076021] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 231.092716] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 231.092739] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 231.092769] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 236.094751] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 236.128716] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 236.128726] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 236.128761] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 236.128784] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 236.128806] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 36000KHz [ 236.128829] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 236.128845] [drm:intel_dp_compute_config [i915]] DP link bw required 108000 available 162000 [ 236.128862] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 236.128878] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 236.128893] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 236.128908] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 236.128923] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1398101, gmch_n: 2097152, link_m: 58254, link_n: 262144, tu: 64 [ 236.128937] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 236.128951] [drm:intel_dump_pipe_config [i915]] requested mode: [ 236.128959] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 236.128973] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 236.128980] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 236.128994] [drm:intel_dump_pipe_config [i915]] crtc timings: 36000 800 824 896 1024 600 601 603 625, type: 0x40 flags: 0x5 [ 236.129008] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 800x600, pixel rate 36000 [ 236.129022] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 236.129035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 236.129048] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 236.129062] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 236.129075] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 236.129089] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 800x600 format = XR24 little-endian (0x34325258) [ 236.129102] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+800+600 dst 0x0+800+600 [ 236.129145] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 236.129159] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 236.129175] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 236.129189] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 236.129208] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 236.129223] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 236.129314] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 236.129337] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 236.129366] [drm:intel_disable_pipe [i915]] disabling pipe A [ 236.135078] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 236.135098] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 236.135117] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 236.135134] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 236.135154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 236.135170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 236.135186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 236.135201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 236.135215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 236.135230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 236.135244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 236.135258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 236.135273] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 236.135288] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 236.135302] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 236.135317] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 236.135334] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 236.135349] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 236.135517] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 236.136075] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 236.137315] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 236.138551] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 236.139791] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 236.141039] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 236.141875] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 236.142781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 236.142797] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 236.142812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 236.142828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 236.161447] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 236.161465] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 236.179042] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 236.179369] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 236.179793] [drm:intel_enable_pipe [i915]] enabling pipe A [ 236.179814] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 236.179831] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 236.179847] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 236.179866] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 236.179893] [drm:intel_fbc_enable [i915]] reserved 3840000 bytes of contiguous stolen space for FBC, threshold: 1 [ 236.179909] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 236.197830] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 236.197853] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 236.197884] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 241.199880] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 241.232045] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 241.232058] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 241.232104] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 241.232130] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 241.232153] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 27000KHz [ 241.232171] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 241.232222] [drm:intel_dp_compute_config [i915]] DP link bw required 81000 available 162000 [ 241.232240] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 241.232256] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 241.232272] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 241.232288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 241.232303] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1048576, gmch_n: 2097152, link_m: 43690, link_n: 262144, tu: 64 [ 241.232318] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 241.232332] [drm:intel_dump_pipe_config [i915]] requested mode: [ 241.232340] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 241.232354] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 241.232361] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 241.232376] [drm:intel_dump_pipe_config [i915]] crtc timings: 27000 720 732 796 864 576 581 586 625, type: 0x40 flags: 0xa [ 241.232390] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x576, pixel rate 27000 [ 241.232404] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 241.232418] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 241.232432] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 241.232446] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 241.232459] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 241.232473] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 800x600 format = XR24 little-endian (0x34325258) [ 241.232487] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+800+600 dst 0x0+800+600 [ 241.232500] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 241.232514] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 241.232530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 241.232545] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 241.232565] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 241.232580] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 241.232702] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 241.232725] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 241.232760] [drm:intel_disable_pipe [i915]] disabling pipe A [ 241.248456] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 241.248477] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 241.248497] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 241.248514] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 241.248535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 241.248552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 241.248567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 241.248583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 241.248597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 241.248612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 241.248627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 241.248641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 241.248657] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 241.248673] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 241.248688] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 241.248702] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 241.248720] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 241.248735] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 241.248828] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 241.249390] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 241.250635] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 241.251879] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 241.253105] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 241.254352] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 241.255187] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 241.256094] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 241.256111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 241.256126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 241.256143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 241.274750] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 241.274768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 241.292334] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 241.292661] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 241.293085] [drm:intel_enable_pipe [i915]] enabling pipe A [ 241.293107] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 241.293124] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 241.293140] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 241.293158] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 241.293189] [drm:intel_fbc_enable [i915]] reserved 3391488 bytes of contiguous stolen space for FBC, threshold: 1 [ 241.293210] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 241.313343] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 241.313367] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 241.313397] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 246.314511] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 246.341532] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 246.341545] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 246.341588] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 246.341611] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 246.341630] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 27027KHz [ 246.341649] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 246.341666] [drm:intel_dp_compute_config [i915]] DP link bw required 81081 available 162000 [ 246.341685] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 246.341703] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 246.341720] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 246.341736] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 246.341752] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1049624, gmch_n: 2097152, link_m: 43734, link_n: 262144, tu: 64 [ 246.341768] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 246.341783] [drm:intel_dump_pipe_config [i915]] requested mode: [ 246.341791] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 246.341807] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 246.341814] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 246.341830] [drm:intel_dump_pipe_config [i915]] crtc timings: 27027 720 736 798 858 480 489 495 525, type: 0x40 flags: 0xa [ 246.341846] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x480, pixel rate 27027 [ 246.341861] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 246.341875] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 246.341890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 246.341905] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 246.341919] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 246.341934] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 720x576 format = XR24 little-endian (0x34325258) [ 246.341949] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+720+576 dst 0x0+720+576 [ 246.341963] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 246.341978] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 246.342025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 246.342041] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 246.342061] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 246.342078] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 246.342165] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 246.342191] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 246.342223] [drm:intel_disable_pipe [i915]] disabling pipe A [ 246.355126] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 246.355148] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 246.355170] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 246.355189] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 246.355211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 246.355229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 246.355246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 246.355262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 246.355278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 246.355294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 246.355310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 246.355325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 246.355342] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 246.355359] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 246.355375] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 246.355390] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 246.355409] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 246.355425] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 246.355517] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 246.356086] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 246.357262] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 246.358514] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 246.359746] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 246.360978] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 246.361813] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 246.362722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 246.362740] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 246.362757] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 246.362774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 246.381386] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 246.381404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 246.399044] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 246.399371] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 246.399796] [drm:intel_enable_pipe [i915]] enabling pipe A [ 246.399818] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 246.399835] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 246.399851] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 246.399870] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 246.399898] [drm:intel_fbc_enable [i915]] reserved 2826240 bytes of contiguous stolen space for FBC, threshold: 1 [ 246.399913] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 246.416701] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 246.416725] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 246.416756] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 251.418517] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 251.444279] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 251.444289] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 251.444327] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 251.444351] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 251.444376] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 27000KHz [ 251.444397] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 251.444414] [drm:intel_dp_compute_config [i915]] DP link bw required 81000 available 162000 [ 251.444433] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 251.444451] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 251.444468] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 251.444485] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 251.444501] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1048576, gmch_n: 2097152, link_m: 43690, link_n: 262144, tu: 64 [ 251.444517] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 251.444532] [drm:intel_dump_pipe_config [i915]] requested mode: [ 251.444540] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 251.444555] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 251.444563] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 251.444579] [drm:intel_dump_pipe_config [i915]] crtc timings: 27000 720 736 798 858 480 489 495 525, type: 0x40 flags: 0xa [ 251.444594] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x480, pixel rate 27000 [ 251.444609] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 251.444624] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 251.444638] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 251.444653] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 251.444667] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 251.444683] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 720x480 format = XR24 little-endian (0x34325258) [ 251.444697] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+720+480 dst 0x0+720+480 [ 251.444712] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 251.444727] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 251.444745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 251.444761] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 251.444781] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 251.444798] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 251.444889] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 251.444915] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 251.444946] [drm:intel_disable_pipe [i915]] disabling pipe A [ 251.450825] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 251.450846] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 251.450867] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 251.450887] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 251.450908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 251.450926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 251.450943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 251.450959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 251.450975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 251.450991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 251.451006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 251.451021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 251.451038] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 251.451055] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 251.451071] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 251.451086] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 251.451105] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 251.451122] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 251.451210] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 251.451768] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 251.452922] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 251.454153] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 251.455379] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 251.456626] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 251.457464] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 251.458373] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 251.458391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 251.458408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 251.458426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 251.477075] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 251.477093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 251.494646] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 251.494973] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 251.495397] [drm:intel_enable_pipe [i915]] enabling pipe A [ 251.495418] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 251.495435] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 251.495451] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 251.495469] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 251.495497] [drm:intel_fbc_enable [i915]] reserved 2826240 bytes of contiguous stolen space for FBC, threshold: 1 [ 251.495512] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 251.512265] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 251.512289] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 251.512319] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 256.513742] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 256.540423] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 256.540434] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 256.540470] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 256.540494] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 256.540518] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 31500KHz [ 256.540544] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 256.540560] [drm:intel_dp_compute_config [i915]] DP link bw required 94500 available 162000 [ 256.540578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 256.540596] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 256.540612] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 256.540628] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 256.540644] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1223338, gmch_n: 2097152, link_m: 50972, link_n: 262144, tu: 64 [ 256.540659] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 256.540674] [drm:intel_dump_pipe_config [i915]] requested mode: [ 256.540682] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 256.540697] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 256.540705] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 256.540720] [drm:intel_dump_pipe_config [i915]] crtc timings: 31500 640 656 720 840 480 481 484 500, type: 0x40 flags: 0xa [ 256.540736] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 31500 [ 256.540751] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 256.540765] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 256.540779] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 256.540794] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 256.540807] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 256.540822] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 720x480 format = XR24 little-endian (0x34325258) [ 256.540836] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+720+480 dst 0x0+720+480 [ 256.540850] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 256.540864] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 256.540881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 256.540897] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 256.540917] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 256.540963] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 256.541039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 256.541064] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 256.541094] [drm:intel_disable_pipe [i915]] disabling pipe A [ 256.551063] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 256.551085] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 256.551105] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 256.551123] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 256.551144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 256.551162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 256.551178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 256.551194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 256.551209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 256.551225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 256.551240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 256.551255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 256.551271] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 256.551287] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 256.551303] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 256.551318] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 256.551337] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 256.551352] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 256.551445] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 256.552016] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 256.553266] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 256.554508] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 256.555743] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 256.556972] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 256.557804] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 256.558712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 256.558730] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 256.558746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 256.558763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 256.577373] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 256.577391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 256.595025] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 256.595352] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 256.595777] [drm:intel_enable_pipe [i915]] enabling pipe A [ 256.595799] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 256.595815] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 256.595831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 256.595850] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 256.595877] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1 [ 256.595892] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 256.609364] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 256.609387] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 256.609417] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 261.611072] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 261.638763] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 261.638774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 261.638812] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 261.638832] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 261.638853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 31500KHz [ 261.638877] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 261.638895] [drm:intel_dp_compute_config [i915]] DP link bw required 94500 available 162000 [ 261.638915] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 261.638934] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 261.638952] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 261.638970] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 261.638987] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1223338, gmch_n: 2097152, link_m: 50972, link_n: 262144, tu: 64 [ 261.639003] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 261.639020] [drm:intel_dump_pipe_config [i915]] requested mode: [ 261.639028] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 261.639045] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 261.639053] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 261.639071] [drm:intel_dump_pipe_config [i915]] crtc timings: 31500 640 664 704 832 480 489 492 520, type: 0x40 flags: 0xa [ 261.639087] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 31500 [ 261.639103] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 261.639119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 261.639134] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 261.639180] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 261.639195] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 261.639211] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 640x480 format = XR24 little-endian (0x34325258) [ 261.639227] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+640+480 dst 0x0+640+480 [ 261.639242] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 261.639258] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 261.639277] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 261.639294] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 261.639316] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 261.639334] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 261.639423] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 261.639450] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 261.639482] [drm:intel_disable_pipe [i915]] disabling pipe A [ 261.649814] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 261.649838] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 261.649860] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 261.649880] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 261.649903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 261.649922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 261.649940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 261.649958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 261.649974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 261.649991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 261.650007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 261.650023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 261.650041] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 261.650059] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 261.650077] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 261.650093] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 261.650113] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 261.650131] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 261.650225] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 261.650788] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 261.652029] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 261.653272] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 261.654503] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 261.655742] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 261.656558] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 261.657469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 261.657488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 261.657506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 261.657524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 261.676140] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 261.676160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 261.693720] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 261.694047] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 261.694471] [drm:intel_enable_pipe [i915]] enabling pipe A [ 261.694493] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 261.694510] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 261.694525] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 261.694544] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 261.694571] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1 [ 261.694587] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 261.708344] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 261.708367] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 261.708397] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 266.710062] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 266.737106] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 266.737117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 266.737149] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 266.737168] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 266.737188] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 30240KHz [ 266.737211] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 266.737228] [drm:intel_dp_compute_config [i915]] DP link bw required 90720 available 162000 [ 266.737246] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 266.737264] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 266.737281] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 266.737298] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 266.737314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1174405, gmch_n: 2097152, link_m: 48933, link_n: 262144, tu: 64 [ 266.737330] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 266.737345] [drm:intel_dump_pipe_config [i915]] requested mode: [ 266.737353] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa [ 266.737368] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 266.737376] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa [ 266.737392] [drm:intel_dump_pipe_config [i915]] crtc timings: 30240 640 704 768 864 480 483 486 525, type: 0x40 flags: 0xa [ 266.737408] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 30240 [ 266.737423] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 266.737437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 266.737452] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 266.737467] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 266.737481] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 266.737495] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 640x480 format = XR24 little-endian (0x34325258) [ 266.737510] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+640+480 dst 0x0+640+480 [ 266.737524] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 266.737538] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 266.737556] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 266.737572] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 266.737592] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 266.737608] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 266.737687] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 266.737713] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 266.737743] [drm:intel_disable_pipe [i915]] disabling pipe A [ 266.749815] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 266.749838] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 266.749859] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 266.749878] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 266.749900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 266.749918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 266.749934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 266.749950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 266.749966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 266.749982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 266.749997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 266.750012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 266.750029] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 266.750046] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 266.750062] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 266.750078] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 266.750096] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 266.750113] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 266.750206] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 266.750768] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 266.752016] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 266.753272] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 266.754504] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 266.755751] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 266.756579] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 266.757490] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 266.757508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 266.757525] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 266.757542] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 266.776199] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 266.776219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 266.793778] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 266.794105] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 266.794530] [drm:intel_enable_pipe [i915]] enabling pipe A [ 266.794552] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 266.794569] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 266.794586] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 266.794604] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 266.794632] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1 [ 266.794648] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 266.809694] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 266.809718] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 266.809748] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 271.811328] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 271.838961] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 271.838972] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 271.839011] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 271.839038] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 271.839064] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 25200KHz [ 271.839087] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 271.839105] [drm:intel_dp_compute_config [i915]] DP link bw required 75600 available 162000 [ 271.839125] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 271.839145] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 271.839163] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 271.839180] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 271.839198] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 978670, gmch_n: 2097152, link_m: 40777, link_n: 262144, tu: 64 [ 271.839215] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 271.839231] [drm:intel_dump_pipe_config [i915]] requested mode: [ 271.839240] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 271.839286] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 271.839294] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 271.839311] [drm:intel_dump_pipe_config [i915]] crtc timings: 25200 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa [ 271.839328] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 25200 [ 271.839345] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 271.839361] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 271.839377] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 271.839393] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 271.839408] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 271.839425] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 640x480 format = XR24 little-endian (0x34325258) [ 271.839440] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+640+480 dst 0x0+640+480 [ 271.839456] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 271.839471] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 271.839490] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 271.839507] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 271.839529] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 271.839546] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 271.839635] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 271.839663] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 271.839695] [drm:intel_disable_pipe [i915]] disabling pipe A [ 271.849808] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 271.849831] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 271.849855] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 271.849875] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 271.849898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 271.849917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 271.849935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 271.849953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 271.849970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 271.849987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 271.850003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 271.850020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 271.850037] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 271.850055] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 271.850072] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 271.850089] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 271.850109] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 271.850127] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 271.850222] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 271.850784] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 271.852026] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 271.853268] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 271.854498] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 271.855736] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 271.856553] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 271.857463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 271.857483] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 271.857501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 271.857519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 271.876127] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 271.876145] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 271.893704] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 271.894031] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 271.894455] [drm:intel_enable_pipe [i915]] enabling pipe A [ 271.894476] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 271.894493] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 271.894509] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 271.894527] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 271.894555] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1 [ 271.894571] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 271.911393] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 271.911416] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 271.911446] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 276.912493] [drm:drm_mode_addfb2 [drm]] [FB:103] [ 276.936848] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 276.936858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 276.936892] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 276.936909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 276.936927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 25175KHz [ 276.936944] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 276.936960] [drm:intel_dp_compute_config [i915]] DP link bw required 75525 available 162000 [ 276.936976] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 276.936993] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 276.937008] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 276.937023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 276.937038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 977700, gmch_n: 2097152, link_m: 40737, link_n: 262144, tu: 64 [ 276.937052] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 276.937066] [drm:intel_dump_pipe_config [i915]] requested mode: [ 276.937074] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 276.937088] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 276.937095] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 276.937110] [drm:intel_dump_pipe_config [i915]] crtc timings: 25175 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa [ 276.937124] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 25175 [ 276.937137] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 276.937151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 276.937165] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 276.937208] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 276.937221] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 276.937235] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:100, fb = 640x480 format = XR24 little-endian (0x34325258) [ 276.937249] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+640+480 dst 0x0+640+480 [ 276.937262] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 276.937275] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 276.937291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 276.937306] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 276.937324] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 276.937340] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 276.937413] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 276.937437] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 276.937466] [drm:intel_disable_pipe [i915]] disabling pipe A [ 276.945791] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 276.945811] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 276.945830] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 276.945847] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 276.945866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 276.945883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 276.945898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 276.945913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 276.945927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 276.945941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 276.945956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 276.945970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 276.945985] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 276.946000] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 276.946015] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 276.946029] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 276.946046] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 276.946061] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 276.946148] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 276.946704] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 276.947956] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 276.949204] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 276.950443] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 276.951692] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 276.952523] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 276.953429] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 276.953445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 276.953460] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 276.953476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 276.972109] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 276.972126] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 276.989726] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 276.990053] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 276.990477] [drm:intel_enable_pipe [i915]] enabling pipe A [ 276.990499] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 276.990516] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 276.990531] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 276.990550] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 276.990577] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1 [ 276.990593] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 277.007434] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 277.007457] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 277.007487] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 282.009180] [drm:drm_mode_addfb2 [drm]] [FB:100] [ 282.034165] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A] [ 282.034176] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:59:DP-1] [ 282.034214] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 282.034234] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 282.034255] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 28320KHz [ 282.034280] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24 [ 282.034299] [drm:intel_dp_compute_config [i915]] DP link bw required 84960 available 162000 [ 282.034318] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 282.034338] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 282.034356] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 282.034374] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 282.034392] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1099839, gmch_n: 2097152, link_m: 45826, link_n: 262144, tu: 64 [ 282.034409] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 282.034425] [drm:intel_dump_pipe_config [i915]] requested mode: [ 282.034434] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 282.034451] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 282.034459] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 282.034476] [drm:intel_dump_pipe_config [i915]] crtc timings: 28320 720 738 846 900 400 412 414 449, type: 0x40 flags: 0x6 [ 282.034492] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x400, pixel rate 28320 [ 282.034508] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 282.034524] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 282.034540] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 282.034556] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 282.034571] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 282.034587] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:103, fb = 640x480 format = XR24 little-endian (0x34325258) [ 282.034603] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+640+480 dst 0x0+640+480 [ 282.034619] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 282.034634] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 282.034653] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 282.034670] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 282.034692] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 282.034710] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 282.034797] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 282.034825] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 282.034858] [drm:intel_disable_pipe [i915]] disabling pipe A [ 282.045809] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 282.045834] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 282.045856] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 282.045876] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 282.045900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 282.045918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 282.045936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 282.045954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 282.045970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 282.045987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 282.046003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 282.046020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 282.046037] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 282.046055] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 282.046073] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 282.046089] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 282.046109] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 282.046127] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 282.046221] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 282.046784] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 282.048023] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 282.049272] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 282.050499] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 282.051736] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 282.052559] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 282.053468] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 282.053488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 282.053506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 282.053525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 282.072089] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 282.072107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 282.089703] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 282.090030] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 1 [ 282.090454] [drm:intel_enable_pipe [i915]] enabling pipe A [ 282.090476] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 282.090493] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 282.090508] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 282.090527] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 282.090554] [drm:intel_fbc_enable [i915]] reserved 2355200 bytes of contiguous stolen space for FBC, threshold: 1 [ 282.090570] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 282.104970] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 282.104992] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 282.105021] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 287.114229] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains [ 287.114347] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 [ 287.114471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz [ 287.114591] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24 [ 287.114678] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000 [ 287.114774] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 [ 287.114867] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset] [ 287.114954] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) [ 287.115038] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 287.115120] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64 [ 287.115200] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 [ 287.115277] [drm:intel_dump_pipe_config [i915]] requested mode: [ 287.115322] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9 [ 287.115401] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 287.115440] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9 [ 287.115522] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9 [ 287.115601] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000 [ 287.115679] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 287.115755] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 287.115829] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 287.115905] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0 [ 287.115978] [drm:intel_dump_pipe_config [i915]] planes on this crtc [ 287.116054] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 [ 287.116179] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 [ 287.116253] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1 [ 287.116347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz [ 287.116431] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 [ 287.116532] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1 [ 287.116617] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A [ 287.116767] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A [ 287.116860] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 287.117004] [drm:intel_disable_pipe [i915]] disabling pipe A [ 287.129976] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 287.130084] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A [ 287.130188] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37 [ 287.130283] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 287.130391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B] [ 287.130481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] [ 287.130568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] [ 287.130652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] [ 287.130734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C] [ 287.130815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A] [ 287.130894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B] [ 287.130972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C] [ 287.131058] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 0 [ 287.131145] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1 [ 287.131227] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 2 [ 287.131308] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 3 [ 287.131401] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37 [ 287.131486] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 287.131682] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 287.132312] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 287.133612] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 287.134910] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 287.136204] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 287.137500] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer [ 287.138438] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON [ 287.139472] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 287.139565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 287.139650] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 287.139736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 287.158467] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 287.158484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 287.176183] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 287.176511] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 [ 287.176935] [drm:intel_enable_pipe [i915]] enabling pipe A [ 287.176956] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 287.176973] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B] [ 287.176989] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD [ 287.177007] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 287.177034] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1 [ 287.177049] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A [ 287.210524] [drm:verify_connector_state.isra.113 [i915]] [CONNECTOR:59:DP-1] [ 287.210548] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A] [ 287.210580] [drm:verify_single_dpll_state.isra.114 [i915]] DPLL 1