Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.4560] NetworkManager (version 1.2.6) is starting... Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.4643] Read config: /etc/NetworkManager/NetworkManager.conf (etc: default-wifi-powersave-on.conf) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.4799] manager[0x55f7015e8200]: monitoring kernel firmware directory '/lib/firmware'. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.4804] monitoring ifupdown state file '/run/network/ifstate'. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.4959] dns-mgr[0x55f7015c6150]: init: dns=dnsmasq, rc-manager=resolvconf, plugin=dnsmasq Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8694] init! Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8700] guessed connection type (enp1s0) = 802-3-ethernet Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8701] update_connection_setting_from_if_block: name:enp1s0, type:802-3-ethernet, id:Ifupdown (enp1s0), uuid: d4f520cc-fe82-d7ba-f35b-8e9bb7ffe98b Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8702] addresses count: 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8703] adding enp1s0 to connections Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8703] adding iface enp1s0 to eni_ifaces Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8703] autoconnect Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8703] management mode: unmanaged Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8709] devices added (path: /sys/devices/pci0000:00/0000:00:13.0/0000:01:00.0/net/enp1s0, iface: enp1s0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8710] locking wired connection setting Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8710] devices added (path: /sys/devices/virtual/net/lo, iface: lo) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8710] device added (path: /sys/devices/virtual/net/lo, iface: lo): no ifupdown configuration found. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8711] end _init. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8711] settings: loaded plugin ifupdown: (C) 2008 Canonical Ltd. To report bugs please use the NetworkManager mailing list. (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-settings-plugin-ifupdown.so) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8711] settings: loaded plugin keyfile: (c) 2007 - 2015 Red Hat, Inc. To report bugs please use the NetworkManager mailing list. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8772] SettingsPlugin-Ofono: init! Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8774] SettingsPlugin-Ofono: file doesn't exist: /var/lib/ofono Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8774] SettingsPlugin-Ofono: end _init. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8774] settings: loaded plugin ofono: (C) 2013-2016 Canonical Ltd. To report bugs please use the NetworkManager mailing list. (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-settings-plugin-ofono.so) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8774] (23090224) ... get_connections. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8775] (23090224) ... get_connections (managed=false): return empty list. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8792] SettingsPlugin-Ofono: (23090544) ... get_connections. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8792] SettingsPlugin-Ofono: (23090544) connections count: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883605.8813] get unmanaged devices count: 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1703] settings: hostname: using hostnamed Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1703] settings: hostname changed from (none) to "GLK-2-GLKRVP1DDR405" Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1706] Using DHCP client 'dhclient' Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1706] manager: WiFi enabled by radio killswitch; enabled by state file Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1707] manager: WWAN enabled by radio killswitch; enabled by state file Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1707] manager: Networking is enabled by state file Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1708] Loaded device plugin: NMVxlanFactory (internal) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1708] Loaded device plugin: NMVlanFactory (internal) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1709] Loaded device plugin: NMVethFactory (internal) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1709] Loaded device plugin: NMTunFactory (internal) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1709] Loaded device plugin: NMMacvlanFactory (internal) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1710] Loaded device plugin: NMIPTunnelFactory (internal) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1710] Loaded device plugin: NMInfinibandFactory (internal) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1710] Loaded device plugin: NMEthernetFactory (internal) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1711] Loaded device plugin: NMBridgeFactory (internal) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1711] Loaded device plugin: NMBondFactory (internal) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1776] Loaded device plugin: NMWwanFactory (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-device-plugin-wwan.so) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1799] Loaded device plugin: NMAtmManager (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-device-plugin-adsl.so) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1819] Loaded device plugin: NMWifiFactory (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-device-plugin-wifi.so) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1846] Loaded device plugin: NMBluezManager (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-device-plugin-bluetooth.so) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1872] manager: (enp1s0): new Ethernet device (/org/freedesktop/NetworkManager/Devices/0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: nm_device_get_device_type: assertion 'NM_IS_DEVICE (self)' failed Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1886] device (lo): link connected Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.1894] manager: (lo): new Generic device (/org/freedesktop/NetworkManager/Devices/1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.2000] manager: startup complete Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.2001] manager: NetworkManager state is now CONNECTED_GLOBAL Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.2059] urfkill disappeared from the bus Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.2245] ModemManager available in the bus Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.2248] ofono is now available Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883606.2253] failed to enumerate oFono devices: GDBus.Error:org.freedesktop.DBus.Error.ServiceUnknown: The name org.ofono was not provided by any .service files Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883609.0258] device (enp1s0): link connected Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883610.1146] devices added (path: /sys/devices/virtual/net/lo, iface: lo) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883610.1146] device added (path: /sys/devices/virtual/net/lo, iface: lo): no ifupdown configuration found. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 content-hub-pee[1182]: Error parsing manifest for package 'com.ubuntu.gallery': com.ubuntu.gallery does not exist in any database for user gfx Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 content-hub-pee[1182]: Unable to get snap information for 'com.ubuntu.gallery': Status code is: 404 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 content-hub-pee[1182]: Error parsing manifest for package 'com.ubuntu.gallery': com.ubuntu.gallery does not exist in any database for user gfx Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 content-hub-pee[1182]: Unable to get snap information for 'com.ubuntu.gallery': Status code is: 404 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 click[1159]: hooks.vala:1216: User-level hook push-helper failed: Hook command '/usr/lib/ubuntu-push-client/click-hook-wrapper' failed: Child process exited with code 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883615.6281] manager: WiFi hardware radio set enabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 NetworkManager[615]: [1480883615.6283] manager: WWAN hardware radio set enabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Linux version 4.15.0-rc6-drm-intel-qa-ww1-commit-cb4a985+ (gfx@bifrost) (gcc version 5.4.0 20160609 (Ubuntu 5.4.0-6ubuntu1~16.04.4)) #1 SMP Tue Jan 2 08:38:40 CST 2018 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-4.15.0-rc6-drm-intel-qa-ww1-commit-cb4a985+ root=UUID=2a8388ef-fcb0-4ae0-964a-bd124748729c ro quiet intel_iommu=igfx_off auto i915.enable_guc=-1 panic=1 nmi_watchdog=panic drm.debug=0xe log_buf_len=4M i915.alpha_support=1 resume=/dev/sda3 fastboot Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] KERNEL supported cpus: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Intel GenuineIntel Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] AMD AuthenticAMD Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Centaur CentaurHauls Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers' Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers' Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers' Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR' Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] x86/fpu: xstate_offset[3]: 576, xstate_sizes[3]: 64 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] x86/fpu: xstate_offset[4]: 640, xstate_sizes[4]: 64 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] x86/fpu: Enabled xstate features 0x1b, context size is 704 bytes, using 'compacted' format. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] e820: BIOS-provided physical RAM map: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000059fff] reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x000000000005a000-0x000000000009dfff] usable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x000000000009e000-0x00000000000fffff] reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000000fffffff] usable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000010000000-0x0000000012151fff] reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000012152000-0x0000000076baefff] usable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000076baf000-0x0000000076e95fff] reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000076e96000-0x0000000076f85fff] type 20 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000076f86000-0x0000000079985fff] reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079986000-0x00000000799e5fff] ACPI NVS Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000799e6000-0x0000000079a25fff] ACPI data Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079a26000-0x000000007abfffff] usable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x000000007ac00000-0x000000007fffffff] reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000d3709000-0x00000000d3709fff] reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000e3ffffff] reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000fed01000-0x00000000fed01fff] reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000027fffffff] usable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] NX (Execute Disable) protection: active Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] efi: EFI v2.60 by EDK II Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] efi: SMBIOS=0x76e92000 SMBIOS 3.0=0x76e90000 ACPI=0x79a25000 ACPI 2.0=0x79a25014 ESRT=0x79955000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] random: fast init done Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] SMBIOS 3.1.1 present. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] DMI: Intel Corp. Geminilake/GLK RVP1 DDR4 (05), BIOS GELKRVPA.X64.0069.B31.1710111133 10/11/2017 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] e820: last_pfn = 0x280000 max_arch_pfn = 0x400000000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] MTRR default type: uncachable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] MTRR fixed ranges enabled: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] 00000-9FFFF write-back Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] A0000-BFFFF uncachable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] C0000-FFFFF write-protect Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] MTRR variable ranges enabled: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] 0 base 00FF800000 mask 7FFF800000 write-protect Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] 1 base 0000000000 mask 7F80000000 write-back Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] 2 base 007B000000 mask 7FFF000000 uncachable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] 3 base 007C000000 mask 7FFC000000 uncachable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] 4 base 0100000000 mask 7F00000000 write-back Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] 5 base 0200000000 mask 7F80000000 write-back Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] 6 disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] 7 disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] 8 disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] 9 disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] e820: last_pfn = 0x7ac00 max_arch_pfn = 0x400000000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] esrt: ESRT header is not in the memory map. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Scanning 1 areas for low memory corruption Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Base memory trampoline at [ (ptrval)] 98000 size 24576 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Using GB pages for direct mapping Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BRK [0x1fd269000, 0x1fd269fff] PGTABLE Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BRK [0x1fd26a000, 0x1fd26afff] PGTABLE Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BRK [0x1fd26b000, 0x1fd26bfff] PGTABLE Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BRK [0x1fd26c000, 0x1fd26cfff] PGTABLE Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BRK [0x1fd26d000, 0x1fd26dfff] PGTABLE Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BRK [0x1fd26e000, 0x1fd26efff] PGTABLE Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BRK [0x1fd26f000, 0x1fd26ffff] PGTABLE Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] BRK [0x1fd270000, 0x1fd270fff] PGTABLE Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] log_buf_len: 4194304 bytes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] early log buf free: 257220(98%) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Secure boot could not be determined Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] RAMDISK: [mem 0x331c0000-0x358d7fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: Early table checksum verification disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: RSDP 0x0000000079A25014 000024 (v02 INTEL ) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: XSDT 0x00000000799F2188 0000FC (v01 INTEL GLK-SOC 00000003 BRXT 01000013) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: FACP 0x0000000079A1D000 00010C (v05 INTEL GLK-SOC 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: DSDT 0x0000000079A03000 012046 (v02 INTEL GLK-SOC 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: FACS 0x00000000799D3000 000040 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: UEFI 0x00000000799DC000 000042 (v01 INTEL EDK2 00000002 BRXT 01000013) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: SSDT 0x0000000079A23000 000420 (v02 INTEL Tpm2Tabl 00001000 INTL 20160527) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: TPM2 0x0000000079A22000 000034 (v04 00000000 00000000) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: BDAT 0x0000000079A21000 000030 (v02 00000000 00000000) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: HPET 0x0000000079A1C000 000038 (v01 INTEL GLK-SOC 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: LPIT 0x0000000079A1B000 00005C (v01 INTEL GLK-SOC 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: APIC 0x0000000079A1A000 000084 (v03 INTEL GLK-SOC 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: MCFG 0x0000000079A19000 00003C (v01 INTEL GLK-SOC 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: NPKT 0x0000000079A18000 000065 (v01 INTEL GLK-SOC 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: PRAM 0x0000000079A17000 000030 (v01 INTEL GLK-SOC 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: WSMT 0x0000000079A16000 000028 (v01 INTEL GLK-SOC 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: SSDT 0x00000000799FF000 003EAE (v02 INTEL DptfTab 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: SSDT 0x00000000799F9000 0055D6 (v02 INTEL RVPRtd3 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: SSDT 0x00000000799F7000 0010B3 (v02 INTEL UsbCTabl 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: SSDT 0x00000000799F5000 00153E (v01 Intel_ Platform 00001000 INTL 20160527) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: SSDT 0x00000000799F4000 0000B1 (v01 Intel_ ADebTabl 00001000 INTL 20160527) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: SSDT 0x00000000799F3000 000472 (v02 PmRef Cpu0Ist 00003000 INTL 20160527) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: SSDT 0x0000000079A24000 000775 (v02 CpuRef CpuSsdt 00003000 INTL 20160527) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: SSDT 0x00000000799F1000 000388 (v02 PmRef Cpu0Tst 00003000 INTL 20160527) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: SSDT 0x00000000799F0000 0001E6 (v02 PmRef ApTst 00003000 INTL 20160527) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: SSDT 0x00000000799ED000 002939 (v02 SaSsdt SaSsdt 00003000 INTL 20160527) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: FPDT 0x00000000799EC000 000044 (v01 INTEL EDK2 00000002 BRXT 01000013) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: DBGP 0x0000000079A1F000 000034 (v01 INTEL GLK-SOC 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: DBG2 0x0000000079A20000 000072 (v00 INTEL GLK-SOC 00000003 BRXT 0100000D) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: WDAT 0x0000000079A1E000 000104 (v01 00000000 00000000) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: NHLT 0x00000000799EA000 001A50 (v00 INTEL EDK2 00000002 BRXT 01000013) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: Local APIC address 0xfee00000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] No NUMA configuration found Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Faking a node at [mem 0x0000000000000000-0x000000027fffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] NODE_DATA(0) allocated [mem 0x27fbfb000-0x27fbfffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] tsc: Using PIT calibration value Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Zone ranges: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] DMA [mem 0x0000000000001000-0x0000000000ffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] DMA32 [mem 0x0000000001000000-0x00000000ffffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Normal [mem 0x0000000100000000-0x000000027fffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Device empty Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Movable zone start for each node Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Early memory node ranges Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] node 0: [mem 0x0000000000001000-0x0000000000057fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] node 0: [mem 0x000000000005a000-0x000000000009dfff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] node 0: [mem 0x0000000000100000-0x000000000fffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] node 0: [mem 0x0000000012152000-0x0000000076baefff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] node 0: [mem 0x0000000079a26000-0x000000007abfffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] node 0: [mem 0x0000000100000000-0x000000027fffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000027fffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] On node 0 totalpages: 2055122 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] DMA zone: 64 pages used for memmap Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] DMA zone: 23 pages reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] DMA zone: 3995 pages, LIFO batch:0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] DMA32 zone: 7473 pages used for memmap Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] DMA32 zone: 478263 pages, LIFO batch:31 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Normal zone: 24576 pages used for memmap Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Normal zone: 1572864 pages, LIFO batch:31 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Reserved but unavailable: 98 pages Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Reserving Intel graphics memory at [mem 0x7c000000-0x7fffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: PM-Timer IO Port: 0x408 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: Local APIC address 0xfee00000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high level lint[0x1]) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high level lint[0x1]) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high level lint[0x1]) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high level lint[0x1]) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-119 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: IRQ0 used by override. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: IRQ9 used by override. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Using ACPI (MADT) for SMP configuration information Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] smpboot: Allowing 4 CPUs, 2 hotplug CPUs Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x00058000-0x00059fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x000fffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x10000000-0x12151fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x76baf000-0x76e95fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x76e96000-0x76f85fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x76f86000-0x79985fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x79986000-0x799e5fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x799e6000-0x79a25fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x7ac00000-0x7fffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x80000000-0xd3708fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xd3709000-0xd3709fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xd370a000-0xdfffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xe0000000-0xe3ffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xe4000000-0xfed00fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfed01000-0xfed01fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfed02000-0xffffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] e820: [mem 0x80000000-0xd3708fff] available for PCI devices Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Booting paravirtualized kernel on bare hardware Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:4 nr_node_ids:1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] percpu: Embedded 46 pages/cpu @ (ptrval) s150104 r8192 d30120 u524288 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] pcpu-alloc: s150104 r8192 d30120 u524288 alloc=1*2097152 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] pcpu-alloc: [0] 0 1 2 3 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2022986 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Policy zone: Normal Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-4.15.0-rc6-drm-intel-qa-ww1-commit-cb4a985+ root=UUID=2a8388ef-fcb0-4ae0-964a-bd124748729c ro quiet intel_iommu=igfx_off auto i915.enable_guc=-1 panic=1 nmi_watchdog=panic drm.debug=0xe log_buf_len=4M i915.alpha_support=1 resume=/dev/sda3 fastboot Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] DMAR: Disable GFX device mapping Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Calgary: detecting Calgary via BIOS EBDA area Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing! Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Memory: 7908196K/8220488K available (12300K kernel code, 1498K rwdata, 3860K rodata, 2300K init, 1164K bss, 312292K reserved, 0K cma-reserved) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ftrace: allocating 37703 entries in 148 pages Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Hierarchical RCU implementation. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=4. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Tasks RCU enabled. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] NR_IRQS: 16640, nr_irqs: 1024, preallocated irqs: 16 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] Console: colour dummy device 80x25 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] console [tty0] enabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: Core revision 20170831 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] ACPI: 12 ACPI AML tables successfully acquired and loaded Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 99544814920 ns Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.000000] hpet clockevent registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.004000] APIC: Switch to symmetric I/O mode setup Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.004000] x2apic: IRQ remapping doesn't support X2APIC mode Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.008000] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.032000] tsc: PIT calibration matches HPET. 1 loops Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.032000] tsc: Detected 1094.330 MHz processor Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.032000] Calibrating delay loop (skipped), value calculated using timer frequency.. 2188.80 BogoMIPS (lpj=4377600) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.032000] pid_max: default: 32768 minimum: 301 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.032000] Security Framework initialized Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.032000] Yama: becoming mindful. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.036080] AppArmor: AppArmor initialized Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.039121] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.040624] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.040804] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.040869] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.042134] CPU: Physical Processor ID: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.042136] CPU: Processor Core ID: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.042150] x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.042163] mce: CPU supports 7 MCE banks Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.042213] CPU0: Thermal monitoring enabled (TM1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.042271] process: using mwait in idle threads Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.042275] Last level iTLB entries: 4KB 0, 2MB 0, 4MB 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.042276] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.045270] Freeing SMP alternatives memory: 36K Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.050259] TSC deadline timer enabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.050269] smpboot: CPU0: Genuine Intel(R) CPU @ 1.10GHz (family: 0x6, model: 0x7a, stepping: 0x1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.050650] Performance Events: PEBS fmt3+, Goldmont plus events, 32-deep LBR, full-width counters, Intel PMU driver. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.050703] ... version: 4 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.050704] ... bit width: 48 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.050705] ... generic registers: 4 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.050707] ... value mask: 0000ffffffffffff Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.050709] ... max period: 00007fffffffffff Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.050710] ... fixed-purpose events: 3 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.050711] ... event mask: 000000070000000f Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.050864] Hierarchical SRCU implementation. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.052000] smp: Bringing up secondary CPUs ... Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.052000] x86: Booting SMP configuration: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.052000] .... node #0, CPUs: #1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.004000] x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.053593] smp: Brought up 1 node, 2 CPUs Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.053593] smpboot: Max logical packages: 2 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.053593] smpboot: Total of 2 processors activated (4377.60 BogoMIPS) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.067478] NMI watchdog: Enabled. Permanently consumes one hw-PMU counter. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.067510] devtmpfs: initialized Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.068284] x86/mm: Memory block size: 128MB Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.076451] evm: security.selinux Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.076453] evm: security.SMACK64 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.076454] evm: security.SMACK64EXEC Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.076455] evm: security.SMACK64TRANSMUTE Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.076456] evm: security.SMACK64MMAP Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.076457] evm: security.apparmor Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.076459] evm: security.ima Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.076460] evm: security.capability Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.076575] PM: Registering ACPI NVS region [mem 0x79986000-0x799e5fff] (393216 bytes) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.076722] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.076722] futex hash table entries: 1024 (order: 4, 65536 bytes) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.076722] pinctrl core: initialized pinctrl subsystem Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.077203] RTC time: 9:58:25, date: 11/12/16 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.082633] NET: Registered protocol family 16 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.083401] audit: initializing netlink subsys (disabled) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.083436] audit: type=2000 audit(1478944705.080:1): state=initialized audit_enabled=0 res=1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.084507] cpuidle: using governor ladder Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.084507] cpuidle: using governor menu Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.084507] ACPI: bus type PCI registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.084507] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.084821] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.084836] PCI: MMCONFIG at [mem 0xe0000000-0xe3ffffff] reserved in E820 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.084836] PCI: Using configuration type 1 for base access Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.097974] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.097974] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.100210] ACPI: Added _OSI(Module Device) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.100212] ACPI: Added _OSI(Processor Device) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.100214] ACPI: Added _OSI(3.0 _SCP Extensions) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.100215] ACPI: Added _OSI(Processor Aggregator Device) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.104916] ACPI: Executed 16 blocks of module-level executable AML code Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.222011] ACPI: Dynamic OEM Table Load: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.222032] ACPI: SSDT 0xFFFF90A2359B4000 0001A5 (v02 PmRef Cpu0Cst 00003001 INTL 20160527) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.222887] ACPI: Executed 1 blocks of module-level executable AML code Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.226944] ACPI: Dynamic OEM Table Load: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.226961] ACPI: SSDT 0xFFFF90A2359B4200 0001E6 (v02 PmRef ApIst 00003000 INTL 20160527) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.232912] ACPI: Executed 1 blocks of module-level executable AML code Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.233848] ACPI: Dynamic OEM Table Load: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.233866] ACPI: SSDT 0xFFFF90A2359BF100 0000C9 (v02 PmRef ApCst 00003000 INTL 20160527) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.234658] ACPI: Executed 1 blocks of module-level executable AML code Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.246541] ACPI: EC: EC started Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.246543] ACPI: EC: interrupt blocked Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.416557] ACPI: \_SB_.PCI0.LPCB.H_EC: Used as first EC Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.416566] ACPI: \_SB_.PCI0.LPCB.H_EC: GPE=0x25, EC_CMD/EC_SC=0x66, EC_DATA=0x62 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.416574] ACPI: \_SB_.PCI0.LPCB.H_EC: Used as boot DSDT EC to handle transactions Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.416576] ACPI: Interpreter enabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.416700] ACPI: (supports S0 S3 S4 S5) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.416704] ACPI: Using IOAPIC for interrupt routing Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.416943] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.428899] ACPI: GPE 0x0F active on init Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.428957] ACPI: Enabled 10 GPEs in block 00 to 7F Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.453150] ACPI: Power Resource [PXP] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.619243] ACPI: Power Resource [PXP] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.783108] ACPI: Power Resource [PXP] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.945753] ACPI: Power Resource [PXP] (off) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 0.962406] ACPI: Power Resource [PXP] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.002318] ACPI: Power Resource [PXP] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.163753] ACPI: Power Resource [SPPR] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.191542] ACPI: Power Resource [SPPR] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.196369] ACPI: Power Resource [UPPR] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.201287] ACPI: Power Resource [BTPR] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.205631] ACPI: Power Resource [UPPR] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.212389] ACPI: Power Resource [UPPR] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.218996] ACPI: Power Resource [PX03] (off) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.230511] ACPI: Power Resource [BTPR] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.235014] ACPI: Power Resource [UPPR] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.242306] ACPI: Power Resource [UPPR] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.249115] ACPI: Power Resource [UPPR] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.254921] ACPI: Power Resource [USBC] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.256220] ACPI: Power Resource [SDPR] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.286019] ACPI: Power Resource [LSPR] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.465649] ACPI: Power Resource [PAUD] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.523290] ACPI: Power Resource [FN00] (on) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.565605] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.565633] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.574828] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.574925] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581424] PCI host bridge to bus 0000:00 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581434] pci_bus 0000:00: root bus resource [io 0x0070-0x0077] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581442] pci_bus 0000:00: root bus resource [io 0x0000-0x006f window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581449] pci_bus 0000:00: root bus resource [io 0x0078-0x0cf7 window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581456] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581462] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581473] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581480] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000fffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581487] pci_bus 0000:00: root bus resource [mem 0x7c000001-0x7fffffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581493] pci_bus 0000:00: root bus resource [mem 0x80000000-0xbfffffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581500] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xefffffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581506] pci_bus 0000:00: root bus resource [mem 0xfea00000-0xfeafffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581513] pci_bus 0000:00: root bus resource [mem 0xfed00000-0xfed003ff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581519] pci_bus 0000:00: root bus resource [mem 0xfed01000-0xfed01fff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581526] pci_bus 0000:00: root bus resource [mem 0xfed03000-0xfed03fff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581535] pci_bus 0000:00: root bus resource [mem 0xfed06000-0xfed06fff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581543] pci_bus 0000:00: root bus resource [mem 0xfed08000-0xfed09fff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581552] pci_bus 0000:00: root bus resource [mem 0xfed80000-0xfedbffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581564] pci_bus 0000:00: root bus resource [mem 0xfed1c000-0xfed1cfff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581571] pci_bus 0000:00: root bus resource [mem 0xfee00000-0xfeefffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581580] pci_bus 0000:00: root bus resource [bus 00-ff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.581609] pci 0000:00:00.0: [8086:31f0] type 00 class 0x060000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.583951] pci 0000:00:00.1: [8086:318c] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.583995] pci 0000:00:00.1: reg 0x10: [mem 0x80000000-0x80007fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.586359] pci 0000:00:00.3: [8086:3190] type 00 class 0x088000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.586388] pci 0000:00:00.3: reg 0x10: [mem 0xa1218000-0xa1218fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.588619] pci 0000:00:02.0: [8086:3185] type 00 class 0x030000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.588640] pci 0000:00:02.0: reg 0x10: [mem 0xa0000000-0xa0ffffff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.588651] pci 0000:00:02.0: reg 0x18: [mem 0x90000000-0x9fffffff 64bit pref] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.588659] pci 0000:00:02.0: reg 0x20: [io 0x2000-0x203f] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.588707] pci 0000:00:02.0: BAR 2: assigned to efifb Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.591242] pci 0000:00:0e.0: [8086:3198] type 00 class 0x040100 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.591275] pci 0000:00:0e.0: reg 0x10: [mem 0xa1210000-0xa1213fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.591313] pci 0000:00:0e.0: reg 0x20: [mem 0xa1000000-0xa10fffff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.591440] pci 0000:00:0e.0: PME# supported from D0 D3hot D3cold Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.595727] pci 0000:00:0f.0: [8086:319a] type 00 class 0x078000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.595800] pci 0000:00:0f.0: reg 0x10: [mem 0xa1219000-0xa1219fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.595969] pci 0000:00:0f.0: PME# supported from D3hot Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.598181] pci 0000:00:11.0: [8086:31a2] type 00 class 0x005007 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.598223] pci 0000:00:11.0: reg 0x10: [mem 0xa1214000-0xa1215fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.598245] pci 0000:00:11.0: reg 0x18: [mem 0xa121a000-0xa121afff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.604717] pci 0000:00:12.0: [8086:31e3] type 00 class 0x010601 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.604751] pci 0000:00:12.0: reg 0x10: [mem 0xa1216000-0xa1217fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.604761] pci 0000:00:12.0: reg 0x14: [mem 0xa123d000-0xa123d0ff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.604773] pci 0000:00:12.0: reg 0x18: [io 0x2080-0x2087] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.604784] pci 0000:00:12.0: reg 0x1c: [io 0x2088-0x208b] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.604796] pci 0000:00:12.0: reg 0x20: [io 0x2060-0x207f] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.604807] pci 0000:00:12.0: reg 0x24: [mem 0xa123b000-0xa123b7ff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.604897] pci 0000:00:12.0: PME# supported from D3hot Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.607419] pci 0000:00:13.0: [8086:31da] type 01 class 0x060400 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.607569] pci 0000:00:13.0: PME# supported from D0 D3hot D3cold Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.609845] pci 0000:00:15.0: [8086:31a8] type 00 class 0x0c0330 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.609877] pci 0000:00:15.0: reg 0x10: [mem 0xa1200000-0xa120ffff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.609987] pci 0000:00:15.0: PME# supported from D3hot D3cold Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.612222] pci 0000:00:16.0: [8086:31ac] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.612257] pci 0000:00:16.0: reg 0x10: [mem 0xa121b000-0xa121bfff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.612277] pci 0000:00:16.0: reg 0x18: [mem 0xa121c000-0xa121cfff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.614563] pci 0000:00:16.1: [8086:31ae] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.614598] pci 0000:00:16.1: reg 0x10: [mem 0xa121d000-0xa121dfff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.614618] pci 0000:00:16.1: reg 0x18: [mem 0xa121e000-0xa121efff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.616895] pci 0000:00:16.2: [8086:31b0] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.616931] pci 0000:00:16.2: reg 0x10: [mem 0xa121f000-0xa121ffff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.616951] pci 0000:00:16.2: reg 0x18: [mem 0xa1220000-0xa1220fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.619235] pci 0000:00:16.3: [8086:31b2] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.619271] pci 0000:00:16.3: reg 0x10: [mem 0xa1221000-0xa1221fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.619289] pci 0000:00:16.3: reg 0x18: [mem 0xa1222000-0xa1222fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.621556] pci 0000:00:17.0: [8086:31b4] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.621596] pci 0000:00:17.0: reg 0x10: [mem 0xa1223000-0xa1223fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.621631] pci 0000:00:17.0: reg 0x18: [mem 0xa1224000-0xa1224fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.623884] pci 0000:00:17.1: [8086:31b6] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.623919] pci 0000:00:17.1: reg 0x10: [mem 0xa1225000-0xa1225fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.623937] pci 0000:00:17.1: reg 0x18: [mem 0xa1226000-0xa1226fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.626201] pci 0000:00:17.2: [8086:31b8] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.626255] pci 0000:00:17.2: reg 0x10: [mem 0xa1227000-0xa1227fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.626276] pci 0000:00:17.2: reg 0x18: [mem 0xa1228000-0xa1228fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.628527] pci 0000:00:17.3: [8086:31ba] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.628562] pci 0000:00:17.3: reg 0x10: [mem 0xa1229000-0xa1229fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.628582] pci 0000:00:17.3: reg 0x18: [mem 0xa122a000-0xa122afff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.630849] pci 0000:00:18.0: [8086:31bc] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.630884] pci 0000:00:18.0: reg 0x10: [mem 0xa122b000-0xa122bfff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.630900] pci 0000:00:18.0: reg 0x18: [mem 0xa122c000-0xa122cfff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.633153] pci 0000:00:18.1: [8086:31be] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.633191] pci 0000:00:18.1: reg 0x10: [mem 0xa122d000-0xa122dfff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.633211] pci 0000:00:18.1: reg 0x18: [mem 0xa122e000-0xa122efff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.635461] pci 0000:00:18.3: [8086:31ee] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.635497] pci 0000:00:18.3: reg 0x10: [mem 0xa122f000-0xa122ffff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.635515] pci 0000:00:18.3: reg 0x18: [mem 0xa1230000-0xa1230fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.637793] pci 0000:00:19.0: [8086:31c2] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.637832] pci 0000:00:19.0: reg 0x10: [mem 0xa1231000-0xa1231fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.637851] pci 0000:00:19.0: reg 0x18: [mem 0xa1232000-0xa1232fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.640099] pci 0000:00:19.1: [8086:31c4] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.640133] pci 0000:00:19.1: reg 0x10: [mem 0xa1233000-0xa1233fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.640152] pci 0000:00:19.1: reg 0x18: [mem 0xa1234000-0xa1234fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.642401] pci 0000:00:19.2: [8086:31c6] type 00 class 0x118000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.642438] pci 0000:00:19.2: reg 0x10: [mem 0xa1235000-0xa1235fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.642457] pci 0000:00:19.2: reg 0x18: [mem 0xa1236000-0xa1236fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.644742] pci 0000:00:1c.0: [8086:31cc] type 00 class 0x080501 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.644779] pci 0000:00:1c.0: reg 0x10: [mem 0xa1237000-0xa1237fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.644799] pci 0000:00:1c.0: reg 0x18: [mem 0xa1238000-0xa1238fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.647300] pci 0000:00:1e.0: [8086:31d0] type 00 class 0x080501 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.647335] pci 0000:00:1e.0: reg 0x10: [mem 0xa1239000-0xa1239fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.647356] pci 0000:00:1e.0: reg 0x18: [mem 0xa123a000-0xa123afff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.649619] pci 0000:00:1f.0: [8086:3197] type 00 class 0x060100 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.651936] pci 0000:00:1f.1: [8086:31d4] type 00 class 0x0c0500 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.652016] pci 0000:00:1f.1: reg 0x10: [mem 0xa123c000-0xa123c0ff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.652098] pci 0000:00:1f.1: reg 0x20: [io 0x2040-0x205f] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.654685] pci 0000:01:00.0: [10ec:8168] type 00 class 0x020000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.654724] pci 0000:01:00.0: reg 0x10: [io 0x1000-0x10ff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.654759] pci 0000:01:00.0: reg 0x18: [mem 0xa1104000-0xa1104fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.654780] pci 0000:01:00.0: reg 0x20: [mem 0xa1100000-0xa1103fff 64bit] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.654805] pci 0000:01:00.0: can't set Max Payload Size to 256; if necessary, use "pci=pcie_bus_safe" and report a bug Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.654973] pci 0000:01:00.0: supports D1 D2 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.654976] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.664190] pci 0000:00:13.0: PCI bridge to [bus 01] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.664198] pci 0000:00:13.0: bridge window [io 0x1000-0x1fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.664205] pci 0000:00:13.0: bridge window [mem 0xa1100000-0xa11fffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.751741] ACPI: PCI Interrupt Link [LNKA] (IRQs *3 4 5 6 10 11 12 14 15) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.752569] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 *4 5 6 10 11 12 14 15) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.753388] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 10 11 12 14 15) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.754205] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 *6 10 11 12 14 15) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.755022] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 11 12 14 15) *7 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.755849] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 11 12 14 15) *9 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.756668] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 *10 11 12 14 15) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.757488] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 *11 12 14 15) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.769850] ACPI: EC: interrupt unblocked Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.769874] ACPI: EC: event unblocked Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.769905] ACPI: \_SB_.PCI0.LPCB.H_EC: GPE=0x25, EC_CMD/EC_SC=0x66, EC_DATA=0x62 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.769913] ACPI: \_SB_.PCI0.LPCB.H_EC: Used as boot DSDT EC to handle transactions and events Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.770667] pci 0000:00:02.0: vgaarb: setting as boot VGA device Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.770667] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.770667] pci 0000:00:02.0: vgaarb: bridge control possible Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.770667] vgaarb: loaded Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.772638] SCSI subsystem initialized Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.772697] libata version 3.00 loaded. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.772697] ACPI: bus type USB registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.772697] usbcore: registered new interface driver usbfs Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.772697] usbcore: registered new interface driver hub Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.772697] usbcore: registered new device driver usb Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.772767] EDAC MC: Ver: 3.0.0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.772767] Registered efivars operations Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.786961] PCI: Using ACPI for IRQ routing Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.794521] PCI: pci_cache_line_size set to 64 bytes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.794740] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.794754] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.794760] e820: reserve RAM buffer [mem 0x76baf000-0x77ffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.794766] e820: reserve RAM buffer [mem 0x7ac00000-0x7bffffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.795604] NetLabel: Initializing Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.795606] NetLabel: domain hash size = 128 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.795607] NetLabel: protocols = UNLABELED CIPSOv4 CALIPSO Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.795723] NetLabel: unlabeled traffic allowed by default Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.796255] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.796267] hpet0: 8 comparators, 64-bit 19.200000 MHz counter Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.798346] clocksource: Switched to clocksource hpet Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.897805] VFS: Disk quotas dquot_6.6.0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.897961] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.898998] AppArmor: AppArmor Filesystem Enabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.899177] pnp: PnP ACPI init Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.900392] system 00:00: [io 0x06a4] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.900405] system 00:00: [io 0x06a0] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.900427] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.902918] pnp 00:01: disabling [io 0x164e-0x164f] because it overlaps 0000:00:13.0 BAR 13 [io 0x1000-0x1fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.903135] system 00:01: [io 0x0680-0x069f] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.903148] system 00:01: [io 0x0400-0x047f] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.903160] system 00:01: [io 0x0500-0x05fe] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.903172] system 00:01: [io 0x0600-0x061f] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.903191] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.903798] pnp 00:02: Plug and Play ACPI device, IDs PNP0303 (active) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.940510] system 00:03: [mem 0xe0000000-0xefffffff] could not be reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.940524] system 00:03: [mem 0xfea00000-0xfeafffff] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.940536] system 00:03: [mem 0xfed01000-0xfed01fff] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.940549] system 00:03: [mem 0xfed03000-0xfed03fff] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.940561] system 00:03: [mem 0xfed06000-0xfed06fff] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.940574] system 00:03: [mem 0xfed08000-0xfed09fff] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.940586] system 00:03: [mem 0xfed80000-0xfedbffff] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.940598] system 00:03: [mem 0xfed1c000-0xfed1cfff] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.940610] system 00:03: [mem 0xfee00000-0xfeefffff] has been reserved Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.940630] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.943451] pnp 00:04: Plug and Play ACPI device, IDs PNP0b00 (active) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.947413] pnp: PnP ACPI: found 5 devices Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.967989] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968055] pci 0000:00:13.0: PCI bridge to [bus 01] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968062] pci 0000:00:13.0: bridge window [io 0x1000-0x1fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968070] pci 0000:00:13.0: bridge window [mem 0xa1100000-0xa11fffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968084] pci_bus 0000:00: resource 4 [io 0x0070-0x0077] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968088] pci_bus 0000:00: resource 5 [io 0x0000-0x006f window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968091] pci_bus 0000:00: resource 6 [io 0x0078-0x0cf7 window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968094] pci_bus 0000:00: resource 7 [io 0x0d00-0xffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968097] pci_bus 0000:00: resource 8 [mem 0x000a0000-0x000bffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968100] pci_bus 0000:00: resource 9 [mem 0x000c0000-0x000dffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968103] pci_bus 0000:00: resource 10 [mem 0x000e0000-0x000fffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968105] pci_bus 0000:00: resource 11 [mem 0x7c000001-0x7fffffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968108] pci_bus 0000:00: resource 12 [mem 0x80000000-0xbfffffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968111] pci_bus 0000:00: resource 13 [mem 0xe0000000-0xefffffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968114] pci_bus 0000:00: resource 14 [mem 0xfea00000-0xfeafffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968117] pci_bus 0000:00: resource 15 [mem 0xfed00000-0xfed003ff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968120] pci_bus 0000:00: resource 16 [mem 0xfed01000-0xfed01fff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968122] pci_bus 0000:00: resource 17 [mem 0xfed03000-0xfed03fff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968125] pci_bus 0000:00: resource 18 [mem 0xfed06000-0xfed06fff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968128] pci_bus 0000:00: resource 19 [mem 0xfed08000-0xfed09fff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968131] pci_bus 0000:00: resource 20 [mem 0xfed80000-0xfedbffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968134] pci_bus 0000:00: resource 21 [mem 0xfed1c000-0xfed1cfff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968137] pci_bus 0000:00: resource 22 [mem 0xfee00000-0xfeefffff window] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968140] pci_bus 0000:01: resource 0 [io 0x1000-0x1fff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.968143] pci_bus 0000:01: resource 1 [mem 0xa1100000-0xa11fffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.969835] NET: Registered protocol family 2 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.970700] TCP established hash table entries: 65536 (order: 7, 524288 bytes) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.971124] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.971384] TCP: Hash tables configured (established 65536 bind 65536) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.971570] UDP hash table entries: 4096 (order: 5, 131072 bytes) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.971644] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.971998] NET: Registered protocol family 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.972094] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.974365] PCI: CLS 64 bytes, default 64 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 1.974635] Trying to unpack rootfs image as initramfs... Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.634776] Freeing initrd memory: 40032K Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.634919] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.634925] software IO TLB [mem 0x6ec00000-0x72c00000] (64MB) mapped at [000000007db7a4fe-00000000f6508546] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.635135] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0xfc66f4fc7c, max_idle_ns: 440795224246 ns Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.635418] Scanning for low memory corruption every 60 seconds Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.639446] Initialise system trusted keyrings Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.639491] Key type blacklist registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.639675] workingset: timestamp_bits=40 max_order=21 bucket_order=0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.652513] zbud: loaded Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.655682] squashfs: version 4.0 (2009/01/31) Phillip Lougher Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.656913] fuse init (API version 7.26) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.657943] Allocating IMA blacklist keyring. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.664254] Key type asymmetric registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.664257] Asymmetric key parser 'x509' registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.664539] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.664682] io scheduler noop registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.664684] io scheduler deadline registered (default) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.665149] io scheduler cfq registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.665152] io scheduler mq-deadline registered (default) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.665154] io scheduler kyber registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.667452] pcieport 0000:00:13.0: Signaling PME with IRQ 120 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.667767] efifb: probing for efifb Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.667827] efifb: framebuffer at 0x90000000, using 8128k, total 8128k Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.667829] efifb: mode is 1920x1080x32, linelength=7680, pages=1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.667830] efifb: scrolling: redraw Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.667833] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.679581] Console: switching to colour frame buffer device 240x67 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.690360] fb0: EFI VGA frame buffer device Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.690413] intel_idle: MWAIT substates: 0x11242020 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.690415] intel_idle: v0.4.1 model 0x7A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.691400] intel_idle: lapic_timer_reliable_states 0xffffffff Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.691997] ACPI: AC Adapter [ADP1] (off-line) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.692442] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:01/PNP0C09:00/PNP0C0D:00/input/input0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.692548] ACPI: Lid Switch [LID0] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.692905] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.693002] ACPI: Power Button [PWRB] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.711652] (NULL device *): hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info(). Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.736574] thermal LNXTHERM:00: registered as thermal_zone0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.736577] ACPI: Thermal Zone [TZ01] (43 C) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.737568] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.738502] ACPI: Battery Slot [BAT0] (battery present) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.738834] ACPI: Battery Slot [BAT1] (battery absent) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.759776] serial8250: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.772381] Linux agpgart interface v0.103 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.793199] brd: module loaded Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.808207] loop: module loaded Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.810094] libphy: Fixed MDIO Bus: probed Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.810096] tun: Universal TUN/TAP device driver, 1.6 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.810376] PPP generic driver version 2.4.2 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.810723] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.810739] ehci-pci: EHCI PCI platform driver Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.810797] ehci-platform: EHCI generic platform driver Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.810848] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.810861] ohci-pci: OHCI PCI platform driver Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.810916] ohci-platform: OHCI generic platform driver Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.810951] uhci_hcd: USB Universal Host Controller Interface driver Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.812373] xhci_hcd 0000:00:15.0: xHCI Host Controller Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.812410] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.813692] xhci_hcd 0000:00:15.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00009810 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.813699] xhci_hcd 0000:00:15.0: cache line size of 64 is not supported Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.814523] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.814526] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.814529] usb usb1: Product: xHCI Host Controller Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.814532] usb usb1: Manufacturer: Linux 4.15.0-rc6-drm-intel-qa-ww1-commit-cb4a985+ xhci-hcd Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.814534] usb usb1: SerialNumber: 0000:00:15.0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.815419] hub 1-0:1.0: USB hub found Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.815474] hub 1-0:1.0: 9 ports detected Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.834397] xhci_hcd 0000:00:15.0: xHCI Host Controller Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.834420] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 2 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.834722] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.834725] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.834728] usb usb2: Product: xHCI Host Controller Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.834731] usb usb2: Manufacturer: Linux 4.15.0-rc6-drm-intel-qa-ww1-commit-cb4a985+ xhci-hcd Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.834733] usb usb2: SerialNumber: 0000:00:15.0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.835579] hub 2-0:1.0: USB hub found Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.835637] hub 2-0:1.0: 7 ports detected Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.850347] i8042: PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.850349] i8042: PNP: PS/2 appears to have AUX port disabled, if this is incorrect please boot with i8042.nopnp Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.850754] i8042: Warning: Keylock active Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.850888] serio: i8042 KBD port at 0x60,0x64 irq 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.851654] mousedev: PS/2 mouse device common for all mice Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.852542] rtc_cmos 00:04: RTC can wake from S4 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.853310] rtc_cmos 00:04: rtc core: registered rtc_cmos as rtc0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.853429] rtc_cmos 00:04: alarms up to one month, y3k, 242 bytes nvram, hpet irqs Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.853470] i2c /dev entries driver Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.853831] device-mapper: uevent: version 1.0.3 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.854358] device-mapper: ioctl: 4.37.0-ioctl (2017-09-20) initialised: dm-devel@redhat.com Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.854371] intel_pstate: Intel P-state driver initializing Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.854924] ledtrig-cpu: registered to indicate activity on CPUs Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.854929] EFI Variables Facility v0.08 2004-May-17 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.868608] NET: Registered protocol family 10 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.869160] Segment Routing with IPv6 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.869189] NET: Registered protocol family 17 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.869226] Key type dns_resolver registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.869737] microcode: sig=0x706a1, pf=0x1, revision=0x16 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.869939] microcode: Microcode Update Driver: v2.2. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.869964] sched_clock: Marking stable (3869928697, 0)->(3845243035, 24685662) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.870600] registered taskstats version 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.870603] Loading compiled-in X.509 certificates Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.874578] Loaded X.509 cert 'Build time autogenerated kernel key: 9d4c29807f3011197a79957290568aae42eed4b9' Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.874630] zswap: loaded using pool lzo/zbud Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.874873] kmemleak: Kernel memory leak detector initialized Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.874882] kmemleak: Automatic memory scanning thread started Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.879845] Key type big_key registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.882196] Key type trusted registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.884539] Key type encrypted registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.884549] AppArmor: AppArmor sha1 policy hashing enabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.884552] ima: No TPM chip found, activating TPM-bypass! (rc=-19) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.884625] evm: HMAC attrs: 0x1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.887547] Magic number: 8:328:980 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.887648] acpi STK0003:02: hash matches Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.887853] rtc_cmos 00:04: setting system clock to 2016-11-12 09:58:29 UTC (1478944709) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.887999] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 3.887999] EDD information not available. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.076224] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.456241] atkbd serio0: Failed to enable keyboard on isa0060/serio0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.456500] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input2 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.461998] Freeing unused kernel memory: 2300K Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.461999] Write protecting the kernel read-only data: 18432k Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.462770] Freeing unused kernel memory: 2008K Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.463438] Freeing unused kernel memory: 236K Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.472140] x86/mm: Checked W+X mappings: passed, no W+X pages found. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.638318] clocksource: Switched to clocksource tsc Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.652139] hidraw: raw HID events driver (C) Jiri Kosina Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.659658] acpi PNP0C14:01: duplicate WMI GUID 05901221-D566-11D1-B2F0-00A0C9062910 (first instance was on PNP0C14:00) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.666561] ahci 0000:00:12.0: version 3.0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.677374] ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl SATA mode Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.677377] ahci 0000:00:12.0: flags: 64bit ncq sntf pm clo only pmp pio slum part deso sadm sds apst Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.684027] scsi host0: ahci Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.684281] ata1: SATA max UDMA/133 abar m2048@0xa123b000 port 0xa123b100 irq 122 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.701261] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.714161] r8169 0000:01:00.0 eth0: RTL8168h/8111h at 0x00000000366946b8, 90:49:fa:02:ac:bb, XID 14100880 IRQ 123 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.714163] r8169 0000:01:00.0 eth0: jumbo features [frames: 9200 bytes, tx checksumming: ko] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.729476] r8169 0000:01:00.0 enp1s0: renamed from eth0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.792102] Setting dangerous option enable_guc - tainting kernel Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.792105] Setting dangerous option alpha_support - tainting kernel Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.793713] [drm:i915_driver_load [i915]] No PCH found. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.793757] [drm:intel_power_domains_init [i915]] Allowed DC state mask 09 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.794879] [drm:i915_driver_load [i915]] ppgtt mode: 3 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.794931] [drm:intel_uc_sanitize_options [i915]] enable_guc=3 (submission:yes huc:yes) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.795014] [drm:i915_ggtt_probe_hw [i915]] GGTT size = 4078M Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.795053] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.795091] [drm:i915_ggtt_probe_hw [i915]] DSM size = 64M Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.795096] checking generic (90000000 7f0000) vs hw (90000000 10000000) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.795097] fb: switching to inteldrmfb from EFI VGA Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.795163] Console: switching to colour dummy device 80x25 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.795487] [drm] Replacing VGA console driver Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.795575] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 57344K Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.795738] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x799ce018 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.795801] [drm:intel_opregion_setup [i915]] Public ACPI methods supported Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.795844] [drm:intel_opregion_setup [i915]] ASLE supported Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.795901] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796102] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796108] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796108] [drm] Driver supports precise vblank timestamp query. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796151] [drm:intel_bios_init [i915]] Set default to SSC at 100000 kHz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796198] [drm:intel_bios_init [i915]] VBT signature "$VBT GEMINILAKE ", BDB version 212 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796240] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796280] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796322] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 212 not known; assuming 38 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796367] [drm:intel_opregion_get_panel_type [i915]] Failed to get panel details from OpRegion (-19) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796409] [drm:intel_bios_init [i915]] Panel type: 2 (VBT) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796448] [drm:intel_bios_init [i915]] DRRS supported mode is seamless Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796490] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796511] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796549] [drm:intel_bios_init [i915]] VBT initial LVDS value 300 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796590] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 180, controller 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796631] [drm:intel_bios_init [i915]] DRRS State Enabled:1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796671] [drm:intel_bios_init [i915]] Skipping SDVO device mapping Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796714] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796752] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796792] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796829] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796867] [drm:intel_bios_init [i915]] Port C VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.796904] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797119] [drm:intel_dsm_detect [i915]] no _DSM method for intel device Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797169] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797213] [drm:intel_power_well_enable [i915]] enabling power well 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797258] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797310] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797348] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797388] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797441] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797449] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797489] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797632] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797695] [drm:intel_power_well_enable [i915]] DDI PHY 0 already enabled, won't reprogram it Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797731] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797894] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797931] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.797968] [drm:intel_power_well_enable [i915]] enabling AUX C Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.798043] [drm:intel_csr_ucode_init [i915]] Loading i915/glk_dmc_ver1_04.bin Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.798293] [drm] Finished loading DMC firmware i915/glk_dmc_ver1_04.bin (v1.4) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.798398] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.799510] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.799568] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 7 (7.0 usec) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.799605] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 7 (7.0 usec) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.799642] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 8 (8.0 usec) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.799678] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 22 (22.0 usec) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.799714] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 22 (22.0 usec) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.799750] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 22 (22.0 usec) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.799785] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 22 (22.0 usec) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.799821] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 22 (22.0 usec) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.799865] [drm:intel_modeset_init [i915]] 3 display pipes available. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.800464] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.800508] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 316800 kHz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.800550] [drm:intel_modeset_init [i915]] Max dotclock rate: 627264 kHz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.800910] [drm:intel_ddi_init [i915]] Forcing DDI_A_4_LANES for port A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.800962] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.801011] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.801062] [drm:intel_pps_dump_state [i915]] cur t1_t3 0 t8 0 t9 0 t10 500 t11_t12 6000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.801102] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 6000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.801147] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 600 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.801187] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.801231] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.801273] [drm:intel_edp_panel_vdd_sanitize [i915]] VDD left on by BIOS, adjusting state tracking Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.801714] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.802079] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.802390] [drm:intel_dp_init_connector [i915]] Detected EDP PSR Panel. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.802711] [drm:intel_dp_init_connector [i915]] eDP DPCD: 02 fb e7 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.805814] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.805827] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.805855] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.805907] [drm:intel_dp_init_connector [i915]] Downclock mode is not found. DRRS not supported Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.805953] [drm:get_backlight_max_vbt [i915]] VBT defined backlight frequency 200 Hz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.805999] [drm:intel_panel_setup_backlight [i915]] Connector eDP-1 backlight initialized, disabled, brightness 0/96000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806078] [drm:intel_ddi_init [i915]] Forcing DDI_A_4_LANES for port A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806128] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806175] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806275] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806320] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x1 for port B (VBT) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806388] [drm:intel_ddi_init [i915]] Forcing DDI_A_4_LANES for port A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806438] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806481] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port C (VBT) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806523] [drm:intel_dsi_init [i915]] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806603] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806646] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806692] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806734] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806778] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806822] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:43:pipe A] hw state readout: enabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806866] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806907] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806949] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.806990] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807032] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807072] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:59:pipe B] hw state readout: disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807115] [drm:intel_modeset_setup_hw_state [i915]] pipe C active planes 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807156] [drm:intel_modeset_setup_hw_state [i915]] pipe C active planes 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807197] [drm:intel_modeset_setup_hw_state [i915]] pipe C active planes 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807237] [drm:intel_modeset_setup_hw_state [i915]] pipe C active planes 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807278] [drm:intel_modeset_setup_hw_state [i915]] pipe C active planes 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807318] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:75:pipe C] hw state readout: disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807362] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807417] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000001, on 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807458] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807501] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:76:DDI A] hw state readout: disabled, pipe A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807553] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:83:DDI B] hw state readout: enabled, pipe A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807596] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:85:DP-MST A] hw state readout: disabled, pipe A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807635] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:86:DP-MST B] hw state readout: disabled, pipe B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807675] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:87:DP-MST C] hw state readout: disabled, pipe C Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807715] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:91:DDI C] hw state readout: disabled, pipe A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807757] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:77:eDP-1] hw state readout: disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807799] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:84:DP-1] hw state readout: enabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807840] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:89:HDMI-A-1] hw state readout: disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807881] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:92:HDMI-A-2] hw state readout: disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807934] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.807985] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][setup_hw_state] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808028] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808118] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 3460300, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808196] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808234] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808247] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148499 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808285] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808298] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148499 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808337] [drm:intel_dump_pipe_config [i915]] crtc timings: 148499 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808376] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148499 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808416] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808453] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808491] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808537] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808575] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808616] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808653] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808691] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808728] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808765] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808803] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][setup_hw_state] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808840] [drm:intel_dump_pipe_config [i915]] output_types: (0x0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808877] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808914] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808950] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.808963] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809000] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809013] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809051] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809088] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809125] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809162] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809238] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809275] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809312] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809349] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809386] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809422] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809459] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809495] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][setup_hw_state] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809531] [drm:intel_dump_pipe_config [i915]] output_types: (0x0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809568] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809604] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809640] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809653] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809689] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809702] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809739] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809775] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809812] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809884] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809924] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809960] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.809996] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810033] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810069] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810105] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810140] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810301] [drm:intel_power_well_disable [i915]] disabling AUX C Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810341] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810378] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810456] [drm:skylake_get_initial_plane_config [i915]] pipe A/plane 1A with fb: size=1920x1080@32, offset=0, pitch 7680, size 0x7e9000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810503] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] creating preallocated stolen object: stolen_offset=0x0000000000000000, gtt_offset=0x0000000000000000, size=0x00000000007e9000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810551] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] failed to allocate stolen space Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810595] [drm:intel_plane_disable_noatomic [i915]] pipe A active planes 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810643] [drm:intel_uc_fw_fetch [i915]] HuC fw fetch i915/glk_huc_ver02_00_1748.bin Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810682] [drm:intel_uc_fw_fetch [i915]] HuC fw fetch PENDING Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810874] [drm:intel_uc_fw_fetch [i915]] HuC fw size 218688 ptr 0000000050d24bf4 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.810916] [drm:intel_uc_fw_fetch [i915]] HuC fw version 2.0 (wanted 2.0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.811056] [drm:intel_uc_fw_fetch [i915]] HuC fw fetch SUCCESS Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.811102] [drm:intel_uc_fw_fetch [i915]] GuC fw fetch i915/glk_guc_ver10_56.bin Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.811139] [drm:intel_uc_fw_fetch [i915]] GuC fw fetch PENDING Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.811285] [drm:intel_uc_fw_fetch [i915]] GuC fw size 145856 ptr 0000000050d24bf4 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.811323] [drm:intel_uc_fw_fetch [i915]] GuC fw version 10.56 (wanted 10.56) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.811428] [drm:intel_uc_fw_fetch [i915]] GuC fw fetch SUCCESS Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.811854] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, fee00000] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.811988] [drm:i915_gem_contexts_init [i915]] logical context support initialized Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.812108] [drm:intel_engine_create_scratch [i915]] rcs0 pipe control offset: 0xfedff000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.812696] [drm:intel_engine_init_common [i915]] rcs0 hws offset: 0x00001000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.813115] [drm:intel_engine_init_common [i915]] bcs0 hws offset: 0x00002000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.813515] [drm:intel_engine_init_common [i915]] vcs0 hws offset: 0x00003000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.813918] [drm:intel_engine_init_common [i915]] vecs0 hws offset: 0x00004000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.813964] [drm:intel_init_gt_powersave [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.814642] [drm:guc_client_alloc [i915]] reserved cacheline 0x0, next 0x40, linesize 64 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.814684] [drm:guc_client_alloc [i915]] Host engines 0x17 => GuC engines used 0xf Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.814727] [drm:reserve_doorbell [i915]] client 0 (high prio=no) reserved doorbell: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.814766] [drm:guc_client_alloc [i915]] new priority 2 client 00000000bad9d581 for engine(s) 0x17: stage_id 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.814804] [drm:guc_client_alloc [i915]] doorbell id 0, cacheline offset 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.814894] [drm:guc_client_alloc [i915]] reserved cacheline 0x40, next 0x80, linesize 64 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.814931] [drm:guc_client_alloc [i915]] Host engines 0x17 => GuC engines used 0xf Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.814968] [drm:reserve_doorbell [i915]] client 1 (high prio=yes) reserved doorbell: 128 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.815005] [drm:guc_client_alloc [i915]] new priority 0 client 000000000ada1bd7 for engine(s) 0x17: stage_id 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.815042] [drm:guc_client_alloc [i915]] doorbell id 128, cacheline offset 0x40 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.815138] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.815175] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.815933] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.815970] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.815974] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.816033] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.816099] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.817135] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.823013] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.823057] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.823059] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.828355] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.828357] i915 0000:00:02.0: GuC submission enabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.828358] i915 0000:00:02.0: HuC enabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.828541] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.828600] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.828705] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.828810] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.828912] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.830227] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.830270] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.830312] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.830351] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.830450] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.832368] [drm:intel_backlight_device_register [i915]] Connector eDP-1 backlight sysfs interface registered Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.832443] [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-eDP-1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.833097] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.833751] [drm] Initialized i915 1.6.0 20171222 for 0000:00:02.0 on minor 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.834422] [drm:intel_opregion_register [i915]] 4 outputs detected Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.840080] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.841275] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input3 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842523] [drm:drm_setup_crtcs [drm_kms_helper]] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842525] i915 device info: pciid=0x3185 rev=0x03 platform=GEMINILAKE gen=9 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842527] i915 device info: is_mobile: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842528] i915 device info: is_lp: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842529] i915 device info: is_alpha_support: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842530] i915 device info: has_64bit_reloc: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842530] i915 device info: has_aliasing_ppgtt: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842531] i915 device info: has_csr: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842532] i915 device info: has_ddi: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842532] i915 device info: has_dp_mst: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842533] i915 device info: has_reset_engine: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842534] i915 device info: has_fbc: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842534] i915 device info: has_fpga_dbg: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842535] i915 device info: has_full_ppgtt: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842536] i915 device info: has_full_48bit_ppgtt: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842537] i915 device info: has_gmch_display: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842537] i915 device info: has_guc: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842538] i915 device info: has_guc_ct: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842538] i915 device info: has_hotplug: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842539] i915 device info: has_l3_dpf: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842540] i915 device info: has_llc: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842540] i915 device info: has_logical_ring_contexts: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842541] i915 device info: has_logical_ring_preemption: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842542] i915 device info: has_overlay: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842542] i915 device info: has_pooled_eu: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842543] i915 device info: has_psr: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842544] i915 device info: has_rc6: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842544] i915 device info: has_rc6p: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842545] i915 device info: has_resource_streamer: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842546] i915 device info: has_runtime_pm: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842546] i915 device info: has_snoop: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842547] i915 device info: unfenced_needs_alignment: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842554] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:77:eDP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842555] i915 device info: cursor_needs_physical: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842556] i915 device info: hws_needs_physical: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842625] [drm:intel_dp_detect [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842626] i915 device info: overlay_needs_physical: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842627] i915 device info: supports_tv: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842627] i915 device info: has_ipc: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842628] i915 device info: slice mask: 0001 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842629] i915 device info: slice total: 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842674] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842675] i915 device info: subslice total: 2 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842716] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842757] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842758] i915 device info: subslice mask 0003 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842759] i915 device info: subslice per slice: 2 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842761] i915 device info: EU total: 12 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842762] i915 device info: EU per subslice: 6 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842763] i915 device info: has slice power gating: no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842763] i915 device info: has subslice power gating: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842764] i915 device info: has EU power gating: yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.842765] i915 device info: CS timestamp frequency: 19200 kHz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.843133] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.843711] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:77:eDP-1] status updated from unknown to connected Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.843734] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.843761] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.843772] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.843807] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:77:eDP-1] probed modes : Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.843822] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.843828] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:84:DP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.843872] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.843919] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.844927] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.845812] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.845850] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.845888] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.846818] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-e0-4c dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.846872] [drm:intel_dp_detect [i915]] Sink is not MST capable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855716] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855724] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:84:DP-1] status updated from unknown to connected Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855737] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855752] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855763] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855863] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:84:DP-1] probed modes : Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855875] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855888] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855899] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855911] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855922] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855933] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855945] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855956] [drm:drm_mode_debug_printmodeline [drm]] Modeline 106:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855967] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855978] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.855990] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.856001] [drm:drm_mode_debug_printmodeline [drm]] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.856040] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:89:HDMI-A-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.856083] [drm:intel_hdmi_detect [i915]] [CONNECTOR:89:HDMI-A-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.856304] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.856343] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.856548] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.856577] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.856784] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.856839] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.857043] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.857068] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.857074] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:89:HDMI-A-1] status updated from unknown to disconnected Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.857080] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:89:HDMI-A-1] disconnected Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.857087] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.857125] [drm:intel_hdmi_detect [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884115] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884158] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884366] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884397] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884418] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884426] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:92:HDMI-A-2] status updated from unknown to connected Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884440] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884452] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884493] [drm:drm_add_edid_modes [drm]] ELD monitor DELL U2713HM Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884505] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884516] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884526] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884537] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884962] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:92:HDMI-A-2] probed modes : Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884976] [drm:drm_mode_debug_printmodeline [drm]] Modeline 108:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884988] [drm:drm_mode_debug_printmodeline [drm]] Modeline 126:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.884999] [drm:drm_mode_debug_printmodeline [drm]] Modeline 146:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885011] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885022] [drm:drm_mode_debug_printmodeline [drm]] Modeline 142:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885033] [drm:drm_mode_debug_printmodeline [drm]] Modeline 140:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885044] [drm:drm_mode_debug_printmodeline [drm]] Modeline 139:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885055] [drm:drm_mode_debug_printmodeline [drm]] Modeline 141:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885066] [drm:drm_mode_debug_printmodeline [drm]] Modeline 154:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885077] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885088] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885099] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885111] [drm:drm_mode_debug_printmodeline [drm]] Modeline 117:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885122] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885133] [drm:drm_mode_debug_printmodeline [drm]] Modeline 115:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885144] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885155] [drm:drm_mode_debug_printmodeline [drm]] Modeline 143:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885166] [drm:drm_mode_debug_printmodeline [drm]] Modeline 138:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885177] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885188] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885199] [drm:drm_mode_debug_printmodeline [drm]] Modeline 125:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885210] [drm:drm_mode_debug_printmodeline [drm]] Modeline 118:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885221] [drm:drm_mode_debug_printmodeline [drm]] Modeline 135:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885232] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885243] [drm:drm_mode_debug_printmodeline [drm]] Modeline 144:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885254] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885266] [drm:drm_mode_debug_printmodeline [drm]] Modeline 151:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885277] [drm:drm_mode_debug_printmodeline [drm]] Modeline 131:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885288] [drm:drm_mode_debug_printmodeline [drm]] Modeline 119:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885299] [drm:drm_mode_debug_printmodeline [drm]] Modeline 145:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885310] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885321] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885328] [drm:drm_setup_crtcs [drm_kms_helper]] connector 77 enabled? yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885334] [drm:drm_setup_crtcs [drm_kms_helper]] connector 84 enabled? yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885341] [drm:drm_setup_crtcs [drm_kms_helper]] connector 89 enabled? no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885347] [drm:drm_setup_crtcs [drm_kms_helper]] connector 92 enabled? yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885404] [drm:intel_fb_initial_config [i915]] Not using firmware configuration Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885411] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 77 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885417] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 77 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885423] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885428] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 84 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885434] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 84 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885440] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885446] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 92 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885451] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 92 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885456] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885462] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 8192x8192 config Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885515] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 43 (0,0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885524] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 59 (0,0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885531] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 75 (0,0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.885582] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.887845] [drm:intelfb_create [i915]] allocated 1920x1080 fb: 0x00180000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.888181] fbcon: inteldrmfb (fb0) is primary device Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.888542] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.888586] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.888601] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.888646] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.888694] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.888748] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.888790] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.888838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.888883] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.888925] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.888971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889051] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889091] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889103] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889143] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889155] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889196] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889235] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889277] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889316] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889355] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889402] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889441] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889483] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889525] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889566] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889608] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889649] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889692] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889773] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889813] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889852] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889891] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889931] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.889969] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890007] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890046] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890083] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890120] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890133] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890170] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890183] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890221] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890259] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890296] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890334] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890371] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890411] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890448] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890488] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890525] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890562] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890599] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890639] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890680] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890736] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890775] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890816] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890854] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890891] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890928] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.890965] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891002] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891014] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891051] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891063] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891101] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891138] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891175] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891248] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891287] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891324] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891364] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891400] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891440] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891476] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891515] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891597] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891643] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891681] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891723] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891761] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891805] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891842] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.891943] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.911007] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.911480] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.911527] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.911603] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 43 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.911687] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.911731] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.911918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.911961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.912006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.912080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.912136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.912177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.912219] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.912258] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.912297] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.912360] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.912402] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.912543] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 4.912584] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.164205] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.165828] ata1.00: ATA-9: INTEL SSDSC2CW120A3, 400i, max UDMA/133 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.165832] ata1.00: 234441648 sectors, multi 16: LBA48 NCQ (depth 31/32), AA Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.175800] ata1.00: configured for UDMA/133 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.176488] scsi 0:0:0:0: Direct-Access ATA INTEL SSDSC2CW12 400i PQ: 0 ANSI: 5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.177454] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/112 GiB) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.177474] sd 0:0:0:0: [sda] Write Protect is off Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.177476] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.177485] sd 0:0:0:0: Attached scsi generic sg0 type 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.177509] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.179017] sda: sda1 sda2 sda3 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.180107] sd 0:0:0:0: [sda] Attached SCSI disk Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.436335] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 0000006a Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.436382] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.436422] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.436461] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 0000006b Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.637487] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.637537] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.638665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.638704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.638748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.639364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.639400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.639994] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.640029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.640950] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.640991] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.641324] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.641389] [drm:intel_edp_backlight_on [i915]] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.641429] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.641470] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.648146] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.648250] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.648291] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.658259] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.658300] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.658447] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.658498] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.658965] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.659599] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.660076] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.660971] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.661461] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.662358] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.662847] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.662885] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.663358] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.663415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.663456] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.663497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.663535] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.664018] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.664162] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.664622] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.665522] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.666005] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.666043] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.666554] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.666600] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.666643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.666681] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.667164] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.667597] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.668044] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.668945] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.669426] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.669464] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.669958] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.670021] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.670383] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.670422] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.670890] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.671076] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.671131] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.671213] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.671253] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.671382] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.671591] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.672108] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.672150] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.672193] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.672232] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.689171] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.689227] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.689297] [drm:intel_ddi_get_config [i915]] pipe has 24 bpp for eDP panel, overriding BIOS-provided max 18 bpp Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.689347] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.689421] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.689462] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.689529] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.689601] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.689640] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.689705] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.689795] Console: switching to colour frame buffer device 240x67 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.710766] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.728242] [drm:drm_fb_helper_hotplug_event.part.33 [drm_kms_helper]] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.728252] [drm:drm_setup_crtcs [drm_kms_helper]] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.728295] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:77:eDP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.728389] [drm:intel_dp_detect [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.728439] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.728480] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.728520] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.730891] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.731498] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.731525] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.731537] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.731570] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:77:eDP-1] probed modes : Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.731584] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.731591] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:84:DP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.731639] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.731669] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.732669] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.733554] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.733588] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.733618] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.734563] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-e0-4c dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.734598] [drm:intel_dp_detect [i915]] Sink is not MST capable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743520] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743543] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743569] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743581] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743712] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:84:DP-1] probed modes : Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743726] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743739] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743751] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743763] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743775] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743787] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743799] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743811] [drm:drm_mode_debug_printmodeline [drm]] Modeline 106:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743822] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743834] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743846] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743858] [drm:drm_mode_debug_printmodeline [drm]] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743866] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:89:HDMI-A-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.743901] [drm:intel_hdmi_detect [i915]] [CONNECTOR:89:HDMI-A-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.744275] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.744308] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.744498] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.744512] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.744701] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.744732] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.744919] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.744928] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.744935] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:89:HDMI-A-1] disconnected Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.744942] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.744977] [drm:intel_hdmi_detect [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.771441] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.771474] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.771664] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.771676] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.771697] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.771712] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.771724] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.771752] [drm:drm_add_edid_modes [drm]] ELD monitor DELL U2713HM Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.771765] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.771776] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.771787] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.771798] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772256] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772268] [drm:drm_mode_prune_invalid [drm]] Not using 1600x1200 mode: VIRTUAL_Y Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772280] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:92:HDMI-A-2] probed modes : Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772293] [drm:drm_mode_debug_printmodeline [drm]] Modeline 108:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772305] [drm:drm_mode_debug_printmodeline [drm]] Modeline 126:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772316] [drm:drm_mode_debug_printmodeline [drm]] Modeline 146:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772328] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772340] [drm:drm_mode_debug_printmodeline [drm]] Modeline 142:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772352] [drm:drm_mode_debug_printmodeline [drm]] Modeline 140:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772363] [drm:drm_mode_debug_printmodeline [drm]] Modeline 139:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772375] [drm:drm_mode_debug_printmodeline [drm]] Modeline 141:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772386] [drm:drm_mode_debug_printmodeline [drm]] Modeline 154:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772398] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772410] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772421] [drm:drm_mode_debug_printmodeline [drm]] Modeline 117:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772433] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772444] [drm:drm_mode_debug_printmodeline [drm]] Modeline 115:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772456] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772468] [drm:drm_mode_debug_printmodeline [drm]] Modeline 143:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772479] [drm:drm_mode_debug_printmodeline [drm]] Modeline 138:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772491] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772502] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772514] [drm:drm_mode_debug_printmodeline [drm]] Modeline 125:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772526] [drm:drm_mode_debug_printmodeline [drm]] Modeline 118:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772537] [drm:drm_mode_debug_printmodeline [drm]] Modeline 135:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772551] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772562] [drm:drm_mode_debug_printmodeline [drm]] Modeline 144:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772574] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772585] [drm:drm_mode_debug_printmodeline [drm]] Modeline 151:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772597] [drm:drm_mode_debug_printmodeline [drm]] Modeline 131:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772608] [drm:drm_mode_debug_printmodeline [drm]] Modeline 119:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772620] [drm:drm_mode_debug_printmodeline [drm]] Modeline 145:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772632] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772643] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772650] [drm:drm_setup_crtcs [drm_kms_helper]] connector 77 enabled? yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772657] [drm:drm_setup_crtcs [drm_kms_helper]] connector 84 enabled? yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772663] [drm:drm_setup_crtcs [drm_kms_helper]] connector 89 enabled? no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772669] [drm:drm_setup_crtcs [drm_kms_helper]] connector 92 enabled? yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772714] [drm:intel_fb_initial_config [i915]] Not using firmware configuration Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772722] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 77 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772729] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 77 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772735] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772740] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 84 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772746] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 84 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772752] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772757] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 92 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772763] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 92 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772768] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772774] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772825] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 43 (0,0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772834] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 59 (0,0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.772842] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 75 (0,0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.787156] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.788972] [drm:drm_fb_helper_hotplug_event.part.33 [drm_kms_helper]] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.788978] [drm:drm_setup_crtcs [drm_kms_helper]] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.788995] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:77:eDP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.789044] [drm:intel_dp_detect [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.789081] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.789112] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.789142] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.789505] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.790792] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.790815] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.790827] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.790861] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:77:eDP-1] probed modes : Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.790876] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.790883] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:84:DP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.790931] [drm:intel_dp_detect [i915]] [CONNECTOR:84:DP-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.790961] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.791947] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.792811] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.792842] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.792872] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.793802] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-e0-4c dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.793833] [drm:intel_dp_detect [i915]] Sink is not MST capable Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803333] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803357] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803383] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803395] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803513] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:84:DP-1] probed modes : Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803527] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803539] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803551] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803563] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803575] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803587] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803598] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803610] [drm:drm_mode_debug_printmodeline [drm]] Modeline 106:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803622] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803633] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803645] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803657] [drm:drm_mode_debug_printmodeline [drm]] Modeline 102:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803664] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:89:HDMI-A-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803699] [drm:intel_hdmi_detect [i915]] [CONNECTOR:89:HDMI-A-1] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.803922] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.804189] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.804202] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.804389] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.804420] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.804608] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.804617] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.804624] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:89:HDMI-A-1] disconnected Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.804632] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.804665] [drm:intel_hdmi_detect [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.830952] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.830985] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831170] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831182] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831202] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831216] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831228] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831260] [drm:drm_add_edid_modes [drm]] ELD monitor DELL U2713HM Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831273] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831284] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831294] [drm:drm_add_display_info [drm]] non_desktop set to 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831305] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831747] [drm:drm_mode_debug_printmodeline [drm]] Modeline 152:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831759] [drm:drm_mode_prune_invalid [drm]] Not using 1600x1200 mode: VIRTUAL_Y Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831769] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:92:HDMI-A-2] probed modes : Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831782] [drm:drm_mode_debug_printmodeline [drm]] Modeline 108:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831794] [drm:drm_mode_debug_printmodeline [drm]] Modeline 126:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831806] [drm:drm_mode_debug_printmodeline [drm]] Modeline 146:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831818] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831830] [drm:drm_mode_debug_printmodeline [drm]] Modeline 142:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831842] [drm:drm_mode_debug_printmodeline [drm]] Modeline 140:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831853] [drm:drm_mode_debug_printmodeline [drm]] Modeline 139:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831865] [drm:drm_mode_debug_printmodeline [drm]] Modeline 141:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831877] [drm:drm_mode_debug_printmodeline [drm]] Modeline 154:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831889] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831900] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831912] [drm:drm_mode_debug_printmodeline [drm]] Modeline 117:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831924] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831936] [drm:drm_mode_debug_printmodeline [drm]] Modeline 115:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831947] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831959] [drm:drm_mode_debug_printmodeline [drm]] Modeline 143:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831971] [drm:drm_mode_debug_printmodeline [drm]] Modeline 138:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831982] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.831994] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832006] [drm:drm_mode_debug_printmodeline [drm]] Modeline 125:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832027] [drm:drm_mode_debug_printmodeline [drm]] Modeline 118:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832039] [drm:drm_mode_debug_printmodeline [drm]] Modeline 135:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832051] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"720x576i" 50 13500 720 732 795 864 576 580 586 625 0x40 0x101a Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832062] [drm:drm_mode_debug_printmodeline [drm]] Modeline 144:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832074] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832086] [drm:drm_mode_debug_printmodeline [drm]] Modeline 151:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832098] [drm:drm_mode_debug_printmodeline [drm]] Modeline 131:"720x480i" 60 13500 720 739 801 858 480 488 494 525 0x40 0x101a Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832109] [drm:drm_mode_debug_printmodeline [drm]] Modeline 119:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832121] [drm:drm_mode_debug_printmodeline [drm]] Modeline 145:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832133] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832144] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832152] [drm:drm_setup_crtcs [drm_kms_helper]] connector 77 enabled? yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832158] [drm:drm_setup_crtcs [drm_kms_helper]] connector 84 enabled? yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832164] [drm:drm_setup_crtcs [drm_kms_helper]] connector 89 enabled? no Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832170] [drm:drm_setup_crtcs [drm_kms_helper]] connector 92 enabled? yes Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832218] [drm:intel_fb_initial_config [i915]] Not using firmware configuration Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832226] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 77 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832232] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 77 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832238] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832243] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 84 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832249] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 84 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832255] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832261] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 92 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832266] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 92 0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832272] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832277] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832336] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 43 (0,0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832345] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 59 (0,0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.832353] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 75 (0,0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 5.899550] ip_tables: (C) 2000-2006 Netfilter Core Team Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.105208] lp: driver loaded but no devices found Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.117280] ppdev: user-space parallel port driver Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.208934] EXT4-fs (sda2): re-mounted. Opts: (null) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.502558] input: Intel HID events as /devices/platform/INT33D5:00/input/input4 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.504933] intel-hid INT33D5:00: platform supports 5 button array Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.505071] input: Intel HID 5 button array as /devices/platform/INT33D5:00/input/input5 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.569311] input: Intel Virtual Button driver as /devices/pci0000:00/0000:00:1f.0/PNP0C09:00/INT33D6:00/input/input6 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.698570] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.730550] idma64 idma64.0: Found Intel integrated DMA 64-bit Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.777119] [drm:intel_backlight_device_update_status [i915]] updating intel_backlight, brightness=96000/96000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.777154] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.823188] idma64 idma64.1: Found Intel integrated DMA 64-bit Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.875063] idma64 idma64.2: Found Intel integrated DMA 64-bit Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 6.946499] idma64 idma64.3: Found Intel integrated DMA 64-bit Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.016529] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915]) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.017982] idma64 idma64.4: Found Intel integrated DMA 64-bit Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.059763] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.087685] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC298: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.087688] snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.087690] snd_hda_codec_realtek hdaudioC0D0: hp_outs=1 (0x21/0x0/0x0/0x0/0x0) Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.087691] snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.087692] snd_hda_codec_realtek hdaudioC0D0: inputs: Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.087693] snd_hda_codec_realtek hdaudioC0D0: Mic=0x18 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.087694] snd_hda_codec_realtek hdaudioC0D0: Internal Mic=0x12 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.176007] [drm:i915_audio_component_get_eld [i915]] Not valid for port B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.182045] [drm:i915_audio_component_get_eld [i915]] Not valid for port B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.182080] [drm:i915_audio_component_get_eld [i915]] Not valid for port B Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.182123] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.182155] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.182186] [drm:i915_audio_component_get_eld [i915]] Not valid for port D Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.182218] [drm:i915_audio_component_get_eld [i915]] Not valid for port D Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.182249] [drm:i915_audio_component_get_eld [i915]] Not valid for port D Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.186089] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input7 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.186346] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input8 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.186588] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input9 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.186844] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input10 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.187101] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input11 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.187343] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input12 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.187598] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input13 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.270433] audit: type=1400 audit(1478944712.878:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/sbin/dhclient" pid=439 comm="apparmor_parser" Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.270446] audit: type=1400 audit(1478944712.878:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=439 comm="apparmor_parser" Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.270456] audit: type=1400 audit(1478944712.878:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-helper" pid=439 comm="apparmor_parser" Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.270469] audit: type=1400 audit(1478944712.878:5): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=439 comm="apparmor_parser" Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.272866] Adding 16642044k swap on /dev/sda3. Priority:-2 extents:1 across:16642044k SSFS Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.286926] audit: type=1400 audit(1478944712.894:6): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/lightdm/lightdm-guest-session" pid=438 comm="apparmor_parser" Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.286939] audit: type=1400 audit(1478944712.894:7): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/lightdm/lightdm-guest-session//chromium" pid=438 comm="apparmor_parser" Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.292667] audit: type=1400 audit(1478944712.902:8): apparmor="STATUS" operation="profile_load" profile="unconfined" name="unity8-dash" pid=450 comm="apparmor_parser" Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.325839] idma64 idma64.5: Found Intel integrated DMA 64-bit Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.331172] audit: type=1400 audit(1480883604.947:9): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/bin/evince" pid=445 comm="apparmor_parser" Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.331183] audit: type=1400 audit(1480883604.947:10): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/bin/evince//sanitized_helper" pid=445 comm="apparmor_parser" Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.331190] audit: type=1400 audit(1480883604.947:11): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/bin/evince-previewer" pid=445 comm="apparmor_parser" Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.475488] r8169 0000:01:00.0 enp1s0: link down Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.475519] r8169 0000:01:00.0 enp1s0: link down Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.478473] IPv6: ADDRCONF(NETDEV_UP): enp1s0: link is not ready Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.544000] idma64 idma64.6: Found Intel integrated DMA 64-bit Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.731889] new mount options do not match the existing superblock, will be ignored Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 7.835952] ip6_tables: (C) 2000-2006 Netfilter Core Team Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 8.924073] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 8.924110] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067 Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 8.924140] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 11.402001] r8169 0000:01:00.0 enp1s0: link up Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 11.402023] IPv6: ADDRCONF(NETDEV_CHANGE): enp1s0: link becomes ready Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 11.897194] idma64 idma64.7: Found Intel integrated DMA 64-bit Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 11.956432] idma64 idma64.8: Found Intel integrated DMA 64-bit Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 11.957944] idma64 idma64.9: Found Intel integrated DMA 64-bit Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 11.960428] idma64 idma64.11: Found Intel integrated DMA 64-bit Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 11.961888] idma64 idma64.12: Found Intel integrated DMA 64-bit Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 11.963411] idma64 idma64.13: Found Intel integrated DMA 64-bit Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 12.078875] RAPL PMU: API unit is 2^-32 Joules, 4 fixed counters, 655360 ms ovfl timer Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 12.078877] RAPL PMU: hw unit of domain pp0-core 2^-14 Joules Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 12.078878] RAPL PMU: hw unit of domain package 2^-14 Joules Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 12.078879] RAPL PMU: hw unit of domain dram 2^-14 Joules Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 12.078879] RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 12.107051] SSE version of gcm_enc/dec engaged. Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 12.319932] intel_telemetry_core Init Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 12.403828] intel_rapl: Found RAPL domain package Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 12.403832] intel_rapl: Found RAPL domain core Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 12.403833] intel_rapl: Found RAPL domain uncore Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 12.403835] intel_rapl: Found RAPL domain dram Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 12.532711] random: crng init done Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 12.944432] dw-apb-uart.8: ttyS4 at MMIO 0xa122b000 (irq = 4, base_baud = 115200) is a 16550A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 13.072743] dw-apb-uart.9: ttyS5 at MMIO 0xa122d000 (irq = 5, base_baud = 115200) is a 16550A Dec 4 14:33:48 GLK-2-GLKRVP1DDR405 kernel: [ 13.200513] dw-apb-uart.10: ttyS6 at MMIO 0xa122f000 (irq = 7, base_baud = 115200) is a 16550A Dec 4 14:35:24 GLK-2-GLKRVP1DDR405 kernel: [ 126.847933] Console: switching to colour dummy device 80x25 Dec 4 14:35:24 GLK-2-GLKRVP1DDR405 kernel: [ 126.881040] Setting dangerous option reset - tainting kernel Dec 4 14:35:24 GLK-2-GLKRVP1DDR405 kernel: [ 126.916316] gem_evict_every (1722): drop_caches: 4 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828148] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828151] missed_breadcrumb current seqno 2, last 3, hangcheck 0 [-171168 ms], inflight 1 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828152] missed_breadcrumb Reset count: 0 (global 0) Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828153] missed_breadcrumb Requests: Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828155] missed_breadcrumb first 3 [4:1] prio=0 @ 1944ms: gem_evict_every[1722]/0 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828156] missed_breadcrumb last 3 [4:1] prio=0 @ 1944ms: gem_evict_every[1722]/0 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828158] missed_breadcrumb active 3 [4:1] prio=0 @ 1944ms: gem_evict_every[1722]/0 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828159] missed_breadcrumb [head 0000, postfix 0058, tail 0078, batch 0x00000000_00000000] Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828167] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828169] missed_breadcrumb RING_HEAD: 0x00000040 [0x00000000] Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828171] missed_breadcrumb RING_TAIL: 0x00000078 [0x00000078] Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828174] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828178] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828182] missed_breadcrumb ACTHD: 0x0000c5c6_5e39d488 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828187] missed_breadcrumb BBADDR: 0x0000c5c6_5e39ec41 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828191] missed_breadcrumb DMA_FADDR: 0x0000c5c6_5e3a0640 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828193] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828195] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828198] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828201] missed_breadcrumb Execlist CSB read 4 [-1 cached], write 4 [4 from hws], interrupt posted? no Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828202] missed_breadcrumb ELSP[0] count=1, rq: 3 [4:1] prio=0 @ 1944ms: gem_evict_every[1722]/0 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828203] missed_breadcrumb ELSP[1] idle Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828204] missed_breadcrumb HW active? 0x1 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828205] missed_breadcrumb E 3 [4:1] prio=0 @ 1944ms: gem_evict_every[1722]/0 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828206] missed_breadcrumb gem_evict_every [1725] waiting for 3 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828207] missed_breadcrumb gem_evict_every [1722] waiting for 3 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828209] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828210] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828210] missed_breadcrumb HWSP: Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828213] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828213] missed_breadcrumb * Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828215] missed_breadcrumb 00000040 00000001 00000000 00000018 001feda8 00000001 00000000 00000018 001fede8 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828217] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000004 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828218] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828219] missed_breadcrumb * Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828220] missed_breadcrumb 000000c0 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828222] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828222] missed_breadcrumb * Dec 4 14:35:26 GLK-2-GLKRVP1DDR405 kernel: [ 128.828228] missed_breadcrumb Idle? no Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.847351] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.847462] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.847732] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.847908] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 10) banned? no Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.847939] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x3 Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.856134] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.856172] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.858361] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.858393] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.858398] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.858432] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.858466] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.858813] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.861112] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.861145] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.861147] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.861206] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.861207] i915 0000:00:02.0: GuC submission enabled Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.861208] i915 0000:00:02.0: HuC enabled Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.861327] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.861371] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.861461] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.861550] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:35:40 GLK-2-GLKRVP1DDR405 kernel: [ 142.861639] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812150] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812158] missed_breadcrumb current seqno 4, last 5, hangcheck 0 [-153184 ms], inflight 1 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812161] missed_breadcrumb Reset count: 0 (global 1) Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812163] missed_breadcrumb Requests: Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812168] missed_breadcrumb first 5 [4:2] prio=0 @ 3948ms: gem_evict_every[1722]/0 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812172] missed_breadcrumb last 5 [4:2] prio=0 @ 3948ms: gem_evict_every[1722]/0 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812176] missed_breadcrumb active 5 [4:2] prio=0 @ 3948ms: gem_evict_every[1722]/0 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812180] missed_breadcrumb [head 0078, postfix 00d0, tail 00f0, batch 0x00000000_00000000] Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812193] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812196] missed_breadcrumb RING_HEAD: 0x000000b8 [0x00000078] Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812200] missed_breadcrumb RING_TAIL: 0x000000f0 [0x000000f0] Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812205] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812210] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812217] missed_breadcrumb ACTHD: 0x0000c5c6_fb1d469c Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812224] missed_breadcrumb BBADDR: 0x0000c5c6_fb1d6841 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812230] missed_breadcrumb DMA_FADDR: 0x0000c5c6_fb1d9040 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812234] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812237] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812243] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812248] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812253] missed_breadcrumb ELSP[0] count=1, rq: 5 [4:2] prio=0 @ 3948ms: gem_evict_every[1722]/0 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812255] missed_breadcrumb ELSP[1] idle Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812257] missed_breadcrumb HW active? 0x1 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812260] missed_breadcrumb E 5 [4:2] prio=0 @ 3948ms: gem_evict_every[1722]/0 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812263] missed_breadcrumb gem_evict_every [1725] waiting for 5 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812266] missed_breadcrumb gem_evict_every [1722] waiting for 5 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812270] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812273] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812274] missed_breadcrumb HWSP: Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812281] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812283] missed_breadcrumb * Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812289] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812294] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812298] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812300] missed_breadcrumb * Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812305] missed_breadcrumb 000000c0 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812310] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812312] missed_breadcrumb * Dec 4 14:35:44 GLK-2-GLKRVP1DDR405 kernel: [ 146.812330] missed_breadcrumb Idle? no Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.847359] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.847469] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.847624] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.847760] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 19) banned? no Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.847791] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x5 Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.860137] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.860170] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.861280] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.861313] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.861315] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.861349] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.861379] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.862567] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.863418] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.863450] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.863451] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.863510] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.863511] i915 0000:00:02.0: GuC submission enabled Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.863512] i915 0000:00:02.0: HuC enabled Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.863631] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.863675] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.863764] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.863853] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:35:56 GLK-2-GLKRVP1DDR405 kernel: [ 158.863941] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844078] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844081] missed_breadcrumb current seqno 6, last 7, hangcheck 6 [32 ms], inflight 1 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844082] missed_breadcrumb Reset count: 0 (global 2) Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844083] missed_breadcrumb Requests: Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844085] missed_breadcrumb first 7 [4:3] prio=0 @ 3980ms: gem_evict_every[1722]/0 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844087] missed_breadcrumb last 7 [4:3] prio=0 @ 3980ms: gem_evict_every[1722]/0 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844088] missed_breadcrumb active 7 [4:3] prio=0 @ 3980ms: gem_evict_every[1722]/0 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844090] missed_breadcrumb [head 00f0, postfix 0148, tail 0168, batch 0x00000000_00000000] Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844098] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844100] missed_breadcrumb RING_HEAD: 0x00000130 [0x000000f0] Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844102] missed_breadcrumb RING_TAIL: 0x00000168 [0x00000168] Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844105] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844108] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844113] missed_breadcrumb ACTHD: 0x0000c5c7_0a877bc0 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844117] missed_breadcrumb BBADDR: 0x0000c5c7_0a8792c1 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844122] missed_breadcrumb DMA_FADDR: 0x0000c5c7_0a87afc0 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844124] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844126] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844129] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844131] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844133] missed_breadcrumb ELSP[0] count=1, rq: 7 [4:3] prio=0 @ 3980ms: gem_evict_every[1722]/0 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844134] missed_breadcrumb ELSP[1] idle Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844134] missed_breadcrumb HW active? 0x1 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844135] missed_breadcrumb E 7 [4:3] prio=0 @ 3980ms: gem_evict_every[1722]/0 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844136] missed_breadcrumb gem_evict_every [1725] waiting for 7 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844138] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844139] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844140] missed_breadcrumb HWSP: Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844143] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844144] missed_breadcrumb * Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844146] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844147] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844149] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844149] missed_breadcrumb * Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844151] missed_breadcrumb 000000c0 00000006 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844152] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844153] missed_breadcrumb * Dec 4 14:36:00 GLK-2-GLKRVP1DDR405 kernel: [ 162.844159] missed_breadcrumb Idle? no Dec 4 14:36:02 GLK-2-GLKRVP1DDR405 kernel: [ 164.801401] kmemleak: Cannot allocate a kmemleak_object structure Dec 4 14:36:02 GLK-2-GLKRVP1DDR405 kernel: [ 164.801405] kmemleak: Kernel memory leak detector disabled Dec 4 14:36:02 GLK-2-GLKRVP1DDR405 kernel: [ 164.804017] kmemleak: Automatic memory scanning thread ended Dec 4 14:36:14 GLK-2-GLKRVP1DDR405 kernel: [ 176.831550] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:36:14 GLK-2-GLKRVP1DDR405 kernel: [ 176.831644] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.664120] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.665040] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 28) banned? no Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.665074] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x7 Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.665200] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.665235] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.674047] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.674082] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.674083] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.674119] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.674152] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.675111] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.678044] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.678078] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.678079] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.678166] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.678167] i915 0000:00:02.0: GuC submission enabled Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.678168] i915 0000:00:02.0: HuC enabled Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.678289] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.678336] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.678427] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.678517] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:36:17 GLK-2-GLKRVP1DDR405 kernel: [ 179.678607] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980077] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980082] missed_breadcrumb current seqno 8, last 9, hangcheck 6 [2304 ms], inflight 1 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980083] missed_breadcrumb Reset count: 0 (global 3) Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980084] missed_breadcrumb Requests: Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980087] missed_breadcrumb first 9 [4:4] prio=0 @ 2300ms: gem_evict_every[1722]/0 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980088] missed_breadcrumb last 9 [4:4] prio=0 @ 2300ms: gem_evict_every[1722]/0 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980090] missed_breadcrumb active 9 [4:4] prio=0 @ 2300ms: gem_evict_every[1722]/0 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980092] missed_breadcrumb [head 0170, postfix 01c8, tail 01e8, batch 0x00000000_00040000] Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980101] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980103] missed_breadcrumb RING_HEAD: 0x000001b0 [0x00000168] Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980105] missed_breadcrumb RING_TAIL: 0x000001e8 [0x000001e8] Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980108] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980112] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980117] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980121] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980126] missed_breadcrumb DMA_FADDR: 0x00000000_00040200 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980128] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980130] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980134] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980137] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980138] missed_breadcrumb ELSP[0] count=1, rq: 9 [4:4] prio=0 @ 2300ms: gem_evict_every[1722]/0 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980139] missed_breadcrumb ELSP[1] idle Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980140] missed_breadcrumb HW active? 0x1 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980141] missed_breadcrumb E 9 [4:4] prio=0 @ 2300ms: gem_evict_every[1722]/0 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980143] missed_breadcrumb gem_evict_every [1725] waiting for 9 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980145] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980146] missed_breadcrumb IRQ? 0x0 (breadcrumbs? no) (execlists? no) Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980147] missed_breadcrumb HWSP: Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980150] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980151] missed_breadcrumb * Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980153] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980155] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980156] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980157] missed_breadcrumb * Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980159] missed_breadcrumb 000000c0 00000008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980161] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980161] missed_breadcrumb * Dec 4 14:36:19 GLK-2-GLKRVP1DDR405 kernel: [ 181.980168] missed_breadcrumb Idle? no Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878428] hangcheck rcs0 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878434] hangcheck current seqno 8, last 9, hangcheck 8 [6032 ms], inflight 1 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878435] hangcheck Reset count: 0 (global 3) Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878436] hangcheck Requests: Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878439] hangcheck first 9 [4:4] prio=0 @ 9196ms: gem_evict_every[1722]/0 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878441] hangcheck last 9 [4:4] prio=0 @ 9196ms: gem_evict_every[1722]/0 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878442] hangcheck active 9 [4:4] prio=0 @ 9196ms: gem_evict_every[1722]/0 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878444] hangcheck [head 0170, postfix 01c8, tail 01e8, batch 0x00000000_00040000] Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878448] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878450] hangcheck RING_HEAD: 0x000001b0 [0x00000168] Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878452] hangcheck RING_TAIL: 0x000001e8 [0x000001e8] Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878456] hangcheck RING_CTL: 0x00003001 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878460] hangcheck RING_MODE: 0x00000000 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878464] hangcheck ACTHD: 0x00000000_00040008 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878469] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878474] hangcheck DMA_FADDR: 0x00000000_00040200 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878476] hangcheck IPEIR: 0x00000000 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878479] hangcheck IPEHR: 0x18800001 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878482] hangcheck Execlist status: 0x00044032 001feda8 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878485] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878487] hangcheck ELSP[0] count=1, rq: 9 [4:4] prio=0 @ 9196ms: gem_evict_every[1722]/0 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878488] hangcheck ELSP[1] idle Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878489] hangcheck HW active? 0x1 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878490] hangcheck E 9 [4:4] prio=0 @ 9196ms: gem_evict_every[1722]/0 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878492] hangcheck gem_evict_every [1725] waiting for 9 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878494] hangcheck RING_IMR: fffffefe Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878495] hangcheck IRQ? 0x0 (breadcrumbs? no) (execlists? no) Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878496] hangcheck HWSP: Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878499] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878500] hangcheck * Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878503] hangcheck 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878505] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878506] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878507] hangcheck * Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878509] hangcheck 000000c0 00000008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878511] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878512] hangcheck * Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.878519] hangcheck Idle? no Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.883238] [drm] GPU HANG: ecode 9:0:0xe7577ffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.883346] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.888670] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.889646] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 37) banned? no Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.889682] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x9 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.900127] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.900165] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.900647] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.900684] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.900686] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.900725] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.900761] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.901277] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.904213] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.904249] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.904250] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.904689] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.904690] i915 0000:00:02.0: GuC submission enabled Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.904691] i915 0000:00:02.0: HuC enabled Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.904820] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.904871] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.904966] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.905061] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:36:26 GLK-2-GLKRVP1DDR405 kernel: [ 188.905156] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844069] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844073] missed_breadcrumb current seqno a, last b, hangcheck 0 [-109152 ms], inflight 1 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844074] missed_breadcrumb Reset count: 0 (global 4) Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844075] missed_breadcrumb Requests: Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844077] missed_breadcrumb first b [4:5] prio=0 @ 1924ms: gem_evict_every[1722]/0 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844079] missed_breadcrumb last b [4:5] prio=0 @ 1924ms: gem_evict_every[1722]/0 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844080] missed_breadcrumb active b [4:5] prio=0 @ 1924ms: gem_evict_every[1722]/0 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844082] missed_breadcrumb [head 01f0, postfix 0248, tail 0268, batch 0x00000000_00000000] Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844091] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844093] missed_breadcrumb RING_HEAD: 0x00000230 [0x000001e8] Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844095] missed_breadcrumb RING_TAIL: 0x00000268 [0x00000268] Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844098] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844102] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844106] missed_breadcrumb ACTHD: 0x0000c5c6_5098b614 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844111] missed_breadcrumb BBADDR: 0x0000c5c6_5098cd35 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844116] missed_breadcrumb DMA_FADDR: 0x0000c5c6_5098e7c0 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844118] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844120] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844123] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844126] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844127] missed_breadcrumb ELSP[0] count=1, rq: b [4:5] prio=0 @ 1924ms: gem_evict_every[1722]/0 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844128] missed_breadcrumb ELSP[1] idle Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844129] missed_breadcrumb HW active? 0x1 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844130] missed_breadcrumb E b [4:5] prio=0 @ 1924ms: gem_evict_every[1722]/0 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844131] missed_breadcrumb gem_evict_every [1725] waiting for b Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844133] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844134] missed_breadcrumb IRQ? 0x0 (breadcrumbs? no) (execlists? no) Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844135] missed_breadcrumb HWSP: Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844138] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844139] missed_breadcrumb * Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844141] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844143] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844144] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844145] missed_breadcrumb * Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844147] missed_breadcrumb 000000c0 0000000a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844148] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844149] missed_breadcrumb * Dec 4 14:36:28 GLK-2-GLKRVP1DDR405 kernel: [ 190.844155] missed_breadcrumb Idle? no Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.831322] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.831395] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.831704] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.833607] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 46) banned? no Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.833639] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0xb Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.833761] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.833793] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.834418] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.834452] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.834453] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.834487] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.834518] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.834808] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.836154] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.836186] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.836188] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.836247] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.836249] i915 0000:00:02.0: GuC submission enabled Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.836250] i915 0000:00:02.0: HuC enabled Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.836368] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.836415] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.836507] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.836597] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:36:42 GLK-2-GLKRVP1DDR405 kernel: [ 204.836685] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828137] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828144] missed_breadcrumb current seqno c, last d, hangcheck c [2016 ms], inflight 1 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828146] missed_breadcrumb Reset count: 0 (global 5) Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828148] missed_breadcrumb Requests: Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828153] missed_breadcrumb first d [4:6] prio=0 @ 3972ms: gem_evict_every[1722]/0 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828157] missed_breadcrumb last d [4:6] prio=0 @ 3972ms: gem_evict_every[1722]/0 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828160] missed_breadcrumb active d [4:6] prio=0 @ 3972ms: gem_evict_every[1722]/0 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828164] missed_breadcrumb [head 0268, postfix 02c0, tail 02e0, batch 0x00000000_00000000] Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828175] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828179] missed_breadcrumb RING_HEAD: 0x000002a8 [0x00000268] Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828182] missed_breadcrumb RING_TAIL: 0x000002e0 [0x000002e0] Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828187] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828191] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828198] missed_breadcrumb ACTHD: 0x0000c5c6_fc81b440 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828204] missed_breadcrumb BBADDR: 0x0000c5c6_fc81d3b5 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828211] missed_breadcrumb DMA_FADDR: 0x0000c5c6_fc81f940 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828214] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828217] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828222] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828227] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828231] missed_breadcrumb ELSP[0] count=1, rq: d [4:6] prio=0 @ 3972ms: gem_evict_every[1722]/0 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828233] missed_breadcrumb ELSP[1] idle Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828234] missed_breadcrumb HW active? 0x1 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828237] missed_breadcrumb E d [4:6] prio=0 @ 3972ms: gem_evict_every[1722]/0 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828240] missed_breadcrumb gem_evict_every [1725] waiting for d Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828243] missed_breadcrumb kswapd0 [41] waiting for d Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828246] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828249] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828250] missed_breadcrumb HWSP: Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828256] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828258] missed_breadcrumb * Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828263] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828268] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828272] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828274] missed_breadcrumb * Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828278] missed_breadcrumb 000000c0 0000000c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828282] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828284] missed_breadcrumb * Dec 4 14:36:46 GLK-2-GLKRVP1DDR405 kernel: [ 208.828300] missed_breadcrumb Idle? no Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.835199] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.835287] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.836313] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.838026] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 55) banned? no Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.838058] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0xd Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.838180] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.838212] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.838640] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.838675] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.838676] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.838710] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.838741] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.839034] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.841497] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.841529] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.841532] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.841591] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.841592] i915 0000:00:02.0: GuC submission enabled Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.841593] i915 0000:00:02.0: HuC enabled Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.841712] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.841758] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.841847] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.841936] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:36:58 GLK-2-GLKRVP1DDR405 kernel: [ 220.842024] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828106] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828109] missed_breadcrumb current seqno e, last f, hangcheck e [2012 ms], inflight 1 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828111] missed_breadcrumb Reset count: 0 (global 6) Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828111] missed_breadcrumb Requests: Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828113] missed_breadcrumb first f [4:7] prio=0 @ 3980ms: gem_evict_every[1722]/0 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828115] missed_breadcrumb last f [4:7] prio=0 @ 3980ms: gem_evict_every[1722]/0 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828116] missed_breadcrumb active f [4:7] prio=0 @ 3980ms: gem_evict_every[1722]/0 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828117] missed_breadcrumb [head 02e0, postfix 0338, tail 0358, batch 0x00000000_00000000] Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828120] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828122] missed_breadcrumb RING_HEAD: 0x00000320 [0x000002e0] Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828124] missed_breadcrumb RING_TAIL: 0x00000358 [0x00000358] Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828128] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828131] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828135] missed_breadcrumb ACTHD: 0x0000c5c7_0b4b11c0 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828140] missed_breadcrumb BBADDR: 0x0000c5c7_0b4b2a41 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828144] missed_breadcrumb DMA_FADDR: 0x0000c5c7_0b4b4040 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828146] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828148] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828151] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828154] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828155] missed_breadcrumb ELSP[0] count=1, rq: f [4:7] prio=0 @ 3980ms: gem_evict_every[1722]/0 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828156] missed_breadcrumb ELSP[1] idle Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828157] missed_breadcrumb HW active? 0x1 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828158] missed_breadcrumb E f [4:7] prio=0 @ 3980ms: gem_evict_every[1722]/0 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828159] missed_breadcrumb gem_evict_every [1725] waiting for f Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828161] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828162] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828162] missed_breadcrumb HWSP: Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828165] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828166] missed_breadcrumb * Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828167] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828169] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828171] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828171] missed_breadcrumb * Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828173] missed_breadcrumb 000000c0 0000000e 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828174] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828175] missed_breadcrumb * Dec 4 14:37:02 GLK-2-GLKRVP1DDR405 kernel: [ 224.828181] missed_breadcrumb Idle? no Dec 4 14:37:14 GLK-2-GLKRVP1DDR405 kernel: [ 236.831449] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:37:14 GLK-2-GLKRVP1DDR405 kernel: [ 236.831539] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.252957] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.253513] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 64) banned? no Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.253551] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0xf Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.260129] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.260167] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.268051] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.268087] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.268088] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.268126] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.268160] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.268525] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.270670] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.270708] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.270709] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.270825] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.270826] i915 0000:00:02.0: GuC submission enabled Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.270827] i915 0000:00:02.0: HuC enabled Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.270958] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.271009] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.271105] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.271201] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:37:16 GLK-2-GLKRVP1DDR405 kernel: [ 239.271296] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836087] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836092] missed_breadcrumb current seqno 10, last 11, hangcheck 10 [3008 ms], inflight 1 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836093] missed_breadcrumb Reset count: 0 (global 7) Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836094] missed_breadcrumb Requests: Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836096] missed_breadcrumb first 11 [4:8] prio=0 @ 4192ms: gem_evict_every[1722]/0 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836098] missed_breadcrumb last 11 [4:8] prio=0 @ 4192ms: gem_evict_every[1722]/0 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836099] missed_breadcrumb active 11 [4:8] prio=0 @ 4192ms: gem_evict_every[1722]/0 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836101] missed_breadcrumb [head 0358, postfix 03b0, tail 03d0, batch 0x00000000_00000000] Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836110] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836112] missed_breadcrumb RING_HEAD: 0x00000398 [0x00000358] Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836115] missed_breadcrumb RING_TAIL: 0x000003d0 [0x000003d0] Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836118] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836121] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836126] missed_breadcrumb ACTHD: 0x0000c5c6_fc9b9c04 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836131] missed_breadcrumb BBADDR: 0x0000c5c6_fc9bb129 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836136] missed_breadcrumb DMA_FADDR: 0x0000c5c6_fc9bc9c0 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836141] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836143] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836148] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836150] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836152] missed_breadcrumb ELSP[0] count=1, rq: 11 [4:8] prio=0 @ 4192ms: gem_evict_every[1722]/0 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836153] missed_breadcrumb ELSP[1] idle Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836154] missed_breadcrumb HW active? 0x1 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836155] missed_breadcrumb E 11 [4:8] prio=0 @ 4192ms: gem_evict_every[1722]/0 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836156] missed_breadcrumb gem_evict_every [1725] waiting for 11 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836159] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836160] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836160] missed_breadcrumb HWSP: Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836163] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836164] missed_breadcrumb * Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836167] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836169] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836171] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836171] missed_breadcrumb * Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836173] missed_breadcrumb 000000c0 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836175] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836176] missed_breadcrumb * Dec 4 14:37:21 GLK-2-GLKRVP1DDR405 kernel: [ 243.836183] missed_breadcrumb Idle? no Dec 4 14:37:32 GLK-2-GLKRVP1DDR405 kernel: [ 254.848362] [drm] GPU HANG: ecode 9:0:0xe7577ffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:37:32 GLK-2-GLKRVP1DDR405 kernel: [ 254.848455] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.212160] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.212812] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 73) banned? no Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.212847] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x11 Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.212969] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.213005] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.217375] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.217411] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.217413] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.217451] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.217485] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.218786] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.221467] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.221502] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.221503] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.221614] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.221615] i915 0000:00:02.0: GuC submission enabled Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.221616] i915 0000:00:02.0: HuC enabled Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.221740] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.221789] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.221881] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.221974] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:37:34 GLK-2-GLKRVP1DDR405 kernel: [ 257.222067] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828081] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828085] missed_breadcrumb current seqno 12, last 13, hangcheck 10 [3608 ms], inflight 1 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828086] missed_breadcrumb Reset count: 0 (global 8) Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828087] missed_breadcrumb Requests: Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828089] missed_breadcrumb first 13 [4:9] prio=0 @ 3592ms: gem_evict_every[1722]/0 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828091] missed_breadcrumb last 13 [4:9] prio=0 @ 3592ms: gem_evict_every[1722]/0 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828092] missed_breadcrumb active 13 [4:9] prio=0 @ 3592ms: gem_evict_every[1722]/0 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828094] missed_breadcrumb [head 03d0, postfix 0428, tail 0448, batch 0x00000000_00000000] Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828101] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828103] missed_breadcrumb RING_HEAD: 0x00000410 [0x000003d0] Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828105] missed_breadcrumb RING_TAIL: 0x00000448 [0x00000448] Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828108] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828112] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828117] missed_breadcrumb ACTHD: 0x0000c5c6_b94e4a94 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828121] missed_breadcrumb BBADDR: 0x0000c5c6_b94e6001 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828126] missed_breadcrumb DMA_FADDR: 0x0000c5c6_b94e78c0 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828128] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828130] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828133] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828136] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828137] missed_breadcrumb ELSP[0] count=1, rq: 13 [4:9] prio=0 @ 3592ms: gem_evict_every[1722]/0 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828138] missed_breadcrumb ELSP[1] idle Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828139] missed_breadcrumb HW active? 0x1 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828140] missed_breadcrumb E 13 [4:9] prio=0 @ 3592ms: gem_evict_every[1722]/0 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828141] missed_breadcrumb gem_evict_every [1725] waiting for 13 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828143] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828144] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828144] missed_breadcrumb HWSP: Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828147] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828148] missed_breadcrumb * Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828150] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828152] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828153] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828154] missed_breadcrumb * Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828156] missed_breadcrumb 000000c0 00000012 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828157] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828158] missed_breadcrumb * Dec 4 14:37:38 GLK-2-GLKRVP1DDR405 kernel: [ 260.828164] missed_breadcrumb Idle? no Dec 4 14:37:52 GLK-2-GLKRVP1DDR405 kernel: [ 274.847774] [drm] GPU HANG: ecode 9:0:0xe7577ffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:37:52 GLK-2-GLKRVP1DDR405 kernel: [ 274.847869] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.436030] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.436690] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 82) banned? no Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.436726] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x13 Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.436846] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.436882] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.441394] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.441428] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.441430] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.441466] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.441499] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.443107] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.446054] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.446087] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.446088] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.446176] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.446177] i915 0000:00:02.0: GuC submission enabled Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.446178] i915 0000:00:02.0: HuC enabled Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.446301] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.446349] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.446441] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.446533] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:37:53 GLK-2-GLKRVP1DDR405 kernel: [ 275.446625] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980079] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980084] missed_breadcrumb current seqno 14, last 15, hangcheck 14 [1148 ms], inflight 1 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980085] missed_breadcrumb Reset count: 0 (global 9) Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980086] missed_breadcrumb Requests: Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980089] missed_breadcrumb first 15 [4:a] prio=0 @ 2504ms: gem_evict_every[1722]/0 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980090] missed_breadcrumb last 15 [4:a] prio=0 @ 2504ms: gem_evict_every[1722]/0 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980092] missed_breadcrumb active 15 [4:a] prio=0 @ 2504ms: gem_evict_every[1722]/0 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980093] missed_breadcrumb [head 0448, postfix 04a0, tail 04c0, batch 0x00000000_00000000] Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980102] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980104] missed_breadcrumb RING_HEAD: 0x00000488 [0x00000448] Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980106] missed_breadcrumb RING_TAIL: 0x000004c0 [0x000004c0] Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980110] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980113] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980118] missed_breadcrumb ACTHD: 0x0000c5c6_793ac000 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980122] missed_breadcrumb BBADDR: 0x0000c5c6_793ad319 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980127] missed_breadcrumb DMA_FADDR: 0x0000c5c6_793aec40 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980129] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980132] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980135] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980138] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980140] missed_breadcrumb ELSP[0] count=1, rq: 15 [4:a] prio=0 @ 2504ms: gem_evict_every[1722]/0 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980140] missed_breadcrumb ELSP[1] idle Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980141] missed_breadcrumb HW active? 0x1 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980142] missed_breadcrumb E 15 [4:a] prio=0 @ 2504ms: gem_evict_every[1722]/0 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980144] missed_breadcrumb gem_evict_every [1725] waiting for 15 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980146] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980147] missed_breadcrumb IRQ? 0x0 (breadcrumbs? no) (execlists? no) Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980147] missed_breadcrumb HWSP: Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980150] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980151] missed_breadcrumb * Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980154] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980155] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980157] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980158] missed_breadcrumb * Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980160] missed_breadcrumb 000000c0 00000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980161] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980162] missed_breadcrumb * Dec 4 14:37:55 GLK-2-GLKRVP1DDR405 kernel: [ 277.980169] missed_breadcrumb Idle? no Dec 4 14:38:08 GLK-2-GLKRVP1DDR405 kernel: [ 290.815765] [drm] GPU HANG: ecode 9:0:0xe7577ffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:38:08 GLK-2-GLKRVP1DDR405 kernel: [ 290.815869] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.480065] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.480443] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 91) banned? no Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.480477] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x15 Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.480595] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.480629] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.485073] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.485107] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.485108] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.485143] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.485174] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.485637] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.488102] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.488134] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.488135] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.488229] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.488230] i915 0000:00:02.0: GuC submission enabled Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.488231] i915 0000:00:02.0: HuC enabled Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.488354] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.488400] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.488496] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.488587] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:38:11 GLK-2-GLKRVP1DDR405 kernel: [ 293.488677] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820073] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820082] missed_breadcrumb current seqno 16, last 17, hangcheck 16 [992 ms], inflight 1 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820083] missed_breadcrumb Reset count: 0 (global 10) Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820084] missed_breadcrumb Requests: Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820086] missed_breadcrumb first 17 [4:b] prio=0 @ 4324ms: gem_evict_every[1722]/0 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820087] missed_breadcrumb last 17 [4:b] prio=0 @ 4324ms: gem_evict_every[1722]/0 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820089] missed_breadcrumb active 17 [4:b] prio=0 @ 4324ms: gem_evict_every[1722]/0 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820091] missed_breadcrumb [head 04c8, postfix 0520, tail 0540, batch 0x00000000_00040000] Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820099] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820101] missed_breadcrumb RING_HEAD: 0x00000508 [0x000004c0] Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820103] missed_breadcrumb RING_TAIL: 0x00000540 [0x00000540] Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820106] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820109] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820114] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820119] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820124] missed_breadcrumb DMA_FADDR: 0x00000000_00040200 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820126] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820128] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820131] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820134] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820135] missed_breadcrumb ELSP[0] count=1, rq: 17 [4:b] prio=0 @ 4324ms: gem_evict_every[1722]/0 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820136] missed_breadcrumb ELSP[1] idle Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820137] missed_breadcrumb HW active? 0x1 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820138] missed_breadcrumb E 17 [4:b] prio=0 @ 4324ms: gem_evict_every[1722]/0 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820139] missed_breadcrumb gem_evict_every [1725] waiting for 17 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820141] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820142] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820143] missed_breadcrumb HWSP: Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820146] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820147] missed_breadcrumb * Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820149] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820151] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820152] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820153] missed_breadcrumb * Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820155] missed_breadcrumb 000000c0 00000016 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820156] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820157] missed_breadcrumb * Dec 4 14:38:15 GLK-2-GLKRVP1DDR405 kernel: [ 297.820163] missed_breadcrumb Idle? no Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812065] hangcheck rcs0 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812070] hangcheck current seqno 16, last 17, hangcheck 16 [9984 ms], inflight 1 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812071] hangcheck Reset count: 0 (global 10) Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812072] hangcheck Requests: Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812075] hangcheck first 17 [4:b] prio=0 @ 13316ms: gem_evict_every[1722]/0 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812076] hangcheck last 17 [4:b] prio=0 @ 13316ms: gem_evict_every[1722]/0 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812078] hangcheck active 17 [4:b] prio=0 @ 13316ms: gem_evict_every[1722]/0 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812080] hangcheck [head 04c8, postfix 0520, tail 0540, batch 0x00000000_00040000] Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812083] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812085] hangcheck RING_HEAD: 0x00000508 [0x000004c0] Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812087] hangcheck RING_TAIL: 0x00000540 [0x00000540] Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812090] hangcheck RING_CTL: 0x00003001 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812093] hangcheck RING_MODE: 0x00000000 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812098] hangcheck ACTHD: 0x00000000_00040000 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812102] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812107] hangcheck DMA_FADDR: 0x00000000_00040200 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812109] hangcheck IPEIR: 0x00000000 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812111] hangcheck IPEHR: 0x18800001 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812114] hangcheck Execlist status: 0x00044032 001feda8 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812117] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812118] hangcheck ELSP[0] count=1, rq: 17 [4:b] prio=0 @ 13316ms: gem_evict_every[1722]/0 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812119] hangcheck ELSP[1] idle Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812120] hangcheck HW active? 0x1 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812121] hangcheck E 17 [4:b] prio=0 @ 13316ms: gem_evict_every[1722]/0 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812122] hangcheck gem_evict_every [1725] waiting for 17 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812124] hangcheck RING_IMR: fffffefe Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812126] hangcheck IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812126] hangcheck HWSP: Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812129] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812130] hangcheck * Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812132] hangcheck 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812134] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812136] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812136] hangcheck * Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812138] hangcheck 000000c0 00000016 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812140] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812140] hangcheck * Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.812147] hangcheck Idle? no Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.815838] [drm] GPU HANG: ecode 9:0:0xe7577ffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.815930] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.996163] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.996983] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 100) banned? no Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.997017] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x17 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.997136] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 306.997171] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.001766] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.001802] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.001803] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.001840] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.001873] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.002866] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.005559] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.005595] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.005596] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.005904] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.005905] i915 0000:00:02.0: GuC submission enabled Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.005906] i915 0000:00:02.0: HuC enabled Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.006032] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.006081] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.006174] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.006267] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:38:24 GLK-2-GLKRVP1DDR405 kernel: [ 307.006359] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812077] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812081] missed_breadcrumb current seqno 18, last 19, hangcheck 18 [1984 ms], inflight 1 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812082] missed_breadcrumb Reset count: 0 (global 11) Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812082] missed_breadcrumb Requests: Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812085] missed_breadcrumb first 19 [4:c] prio=0 @ 3800ms: gem_evict_every[1722]/0 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812086] missed_breadcrumb last 19 [4:c] prio=0 @ 3800ms: gem_evict_every[1722]/0 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812087] missed_breadcrumb active 19 [4:c] prio=0 @ 3800ms: gem_evict_every[1722]/0 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812089] missed_breadcrumb [head 0548, postfix 05a0, tail 05c0, batch 0x00000000_00000000] Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812097] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812099] missed_breadcrumb RING_HEAD: 0x00000588 [0x00000540] Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812101] missed_breadcrumb RING_TAIL: 0x000005c0 [0x000005c0] Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812104] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812107] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812112] missed_breadcrumb ACTHD: 0x0000c5c6_c407cbc0 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812120] missed_breadcrumb BBADDR: 0x0000c5c6_c407f899 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812125] missed_breadcrumb DMA_FADDR: 0x0000c5c6_c40813c0 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812127] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812130] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812133] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812135] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812137] missed_breadcrumb ELSP[0] count=1, rq: 19 [4:c] prio=0 @ 3800ms: gem_evict_every[1722]/0 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812138] missed_breadcrumb ELSP[1] idle Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812138] missed_breadcrumb HW active? 0x1 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812140] missed_breadcrumb E 19 [4:c] prio=0 @ 3800ms: gem_evict_every[1722]/0 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812141] missed_breadcrumb gem_evict_every [1725] waiting for 19 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812143] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812144] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812144] missed_breadcrumb HWSP: Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812147] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812148] missed_breadcrumb * Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812150] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812151] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812153] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812154] missed_breadcrumb * Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812155] missed_breadcrumb 000000c0 00000018 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812157] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812157] missed_breadcrumb * Dec 4 14:38:28 GLK-2-GLKRVP1DDR405 kernel: [ 310.812163] missed_breadcrumb Idle? no Dec 4 14:38:40 GLK-2-GLKRVP1DDR405 kernel: [ 322.847350] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:38:40 GLK-2-GLKRVP1DDR405 kernel: [ 322.847439] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.564199] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.565334] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 109) banned? no Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.565370] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x19 Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.565491] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.565527] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.781581] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.781619] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.781620] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.781659] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.781693] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.784425] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.786499] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.786532] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.786533] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.786763] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.786764] i915 0000:00:02.0: GuC submission enabled Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.786765] i915 0000:00:02.0: HuC enabled Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.786887] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.786935] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.787026] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.787117] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:38:42 GLK-2-GLKRVP1DDR405 kernel: [ 324.787207] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828073] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828076] missed_breadcrumb current seqno 1a, last 1b, hangcheck 1a [4000 ms], inflight 1 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828078] missed_breadcrumb Reset count: 0 (global 12) Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828078] missed_breadcrumb Requests: Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828081] missed_breadcrumb first 1b [4:d] prio=0 @ 4020ms: gem_evict_every[1722]/0 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828082] missed_breadcrumb last 1b [4:d] prio=0 @ 4020ms: gem_evict_every[1722]/0 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828084] missed_breadcrumb active 1b [4:d] prio=0 @ 4020ms: gem_evict_every[1722]/0 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828086] missed_breadcrumb [head 05c8, postfix 0620, tail 0640, batch 0x00000000_00040000] Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828094] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828096] missed_breadcrumb RING_HEAD: 0x00000608 [0x000005c0] Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828098] missed_breadcrumb RING_TAIL: 0x00000640 [0x00000640] Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828101] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828104] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828109] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828113] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828118] missed_breadcrumb DMA_FADDR: 0x00000000_00040200 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828120] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828122] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828125] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828128] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828130] missed_breadcrumb ELSP[0] count=1, rq: 1b [4:d] prio=0 @ 4020ms: gem_evict_every[1722]/0 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828130] missed_breadcrumb ELSP[1] idle Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828131] missed_breadcrumb HW active? 0x1 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828132] missed_breadcrumb E 1b [4:d] prio=0 @ 4020ms: gem_evict_every[1722]/0 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828133] missed_breadcrumb gem_evict_every [1725] waiting for 1b Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828135] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828136] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828137] missed_breadcrumb HWSP: Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828140] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828141] missed_breadcrumb * Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828143] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828144] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828146] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828147] missed_breadcrumb * Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828148] missed_breadcrumb 000000c0 0000001a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828150] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828151] missed_breadcrumb * Dec 4 14:38:46 GLK-2-GLKRVP1DDR405 kernel: [ 328.828157] missed_breadcrumb Idle? no Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812064] hangcheck rcs0 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812069] hangcheck current seqno 1a, last 1b, hangcheck 1a [5984 ms], inflight 1 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812070] hangcheck Reset count: 0 (global 12) Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812071] hangcheck Requests: Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812074] hangcheck first 1b [4:d] prio=0 @ 6004ms: gem_evict_every[1722]/0 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812075] hangcheck last 1b [4:d] prio=0 @ 6004ms: gem_evict_every[1722]/0 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812077] hangcheck active 1b [4:d] prio=0 @ 6004ms: gem_evict_every[1722]/0 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812079] hangcheck [head 05c8, postfix 0620, tail 0640, batch 0x00000000_00040000] Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812081] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812083] hangcheck RING_HEAD: 0x00000608 [0x000005c0] Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812085] hangcheck RING_TAIL: 0x00000640 [0x00000640] Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812089] hangcheck RING_CTL: 0x00003001 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812092] hangcheck RING_MODE: 0x00000000 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812097] hangcheck ACTHD: 0x00000000_00040000 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812101] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812120] hangcheck DMA_FADDR: 0x00000000_00040200 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812122] hangcheck IPEIR: 0x00000000 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812124] hangcheck IPEHR: 0x18800001 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812128] hangcheck Execlist status: 0x00044032 001feda8 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812130] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812132] hangcheck ELSP[0] count=1, rq: 1b [4:d] prio=0 @ 6004ms: gem_evict_every[1722]/0 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812133] hangcheck ELSP[1] idle Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812133] hangcheck HW active? 0x1 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812135] hangcheck E 1b [4:d] prio=0 @ 6004ms: gem_evict_every[1722]/0 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812136] hangcheck gem_evict_every [1725] waiting for 1b Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812138] hangcheck RING_IMR: fffffefe Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812139] hangcheck IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812140] hangcheck HWSP: Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812143] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812143] hangcheck * Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812146] hangcheck 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812147] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812149] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812150] hangcheck * Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812151] hangcheck 000000c0 0000001a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812153] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812154] hangcheck * Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.812160] hangcheck Idle? no Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.815588] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:38:48 GLK-2-GLKRVP1DDR405 kernel: [ 330.815684] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.596049] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.597059] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 118) banned? no Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.597092] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x1b Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.597211] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.597245] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.604052] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.604086] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.604087] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.604124] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.604157] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.604459] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.606537] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.606570] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.606571] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.606797] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.606799] i915 0000:00:02.0: GuC submission enabled Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.606800] i915 0000:00:02.0: HuC enabled Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.606921] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.606968] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.607059] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.607150] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:38:51 GLK-2-GLKRVP1DDR405 kernel: [ 333.607240] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836083] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836088] missed_breadcrumb current seqno 1c, last 1d, hangcheck 1a [2232 ms], inflight 1 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836089] missed_breadcrumb Reset count: 0 (global 13) Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836090] missed_breadcrumb Requests: Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836092] missed_breadcrumb first 1d [4:e] prio=0 @ 2216ms: gem_evict_every[1722]/0 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836093] missed_breadcrumb last 1d [4:e] prio=0 @ 2216ms: gem_evict_every[1722]/0 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836095] missed_breadcrumb active 1d [4:e] prio=0 @ 2216ms: gem_evict_every[1722]/0 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836096] missed_breadcrumb [head 0648, postfix 06a0, tail 06c0, batch 0x00000000_00000000] Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836106] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836108] missed_breadcrumb RING_HEAD: 0x00000688 [0x00000640] Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836110] missed_breadcrumb RING_TAIL: 0x000006c0 [0x000006c0] Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836113] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836117] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836122] missed_breadcrumb ACTHD: 0x0000c5c6_6649f61c Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836126] missed_breadcrumb BBADDR: 0x0000c5c6_664a0ef5 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836131] missed_breadcrumb DMA_FADDR: 0x0000c5c6_664a27c0 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836133] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836135] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836138] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836141] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836143] missed_breadcrumb ELSP[0] count=1, rq: 1d [4:e] prio=0 @ 2216ms: gem_evict_every[1722]/0 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836144] missed_breadcrumb ELSP[1] idle Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836144] missed_breadcrumb HW active? 0x1 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836145] missed_breadcrumb E 1d [4:e] prio=0 @ 2216ms: gem_evict_every[1722]/0 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836147] missed_breadcrumb gem_evict_every [1725] waiting for 1d Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836149] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836150] missed_breadcrumb IRQ? 0x0 (breadcrumbs? no) (execlists? no) Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836150] missed_breadcrumb HWSP: Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836153] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836154] missed_breadcrumb * Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836156] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836158] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836160] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836160] missed_breadcrumb * Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836162] missed_breadcrumb 000000c0 0000001c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836164] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836164] missed_breadcrumb * Dec 4 14:38:53 GLK-2-GLKRVP1DDR405 kernel: [ 335.836171] missed_breadcrumb Idle? no Dec 4 14:39:08 GLK-2-GLKRVP1DDR405 kernel: [ 350.815576] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:39:08 GLK-2-GLKRVP1DDR405 kernel: [ 350.815675] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.880062] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.881190] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 127) banned? no Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.881226] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x1d Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.881348] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.881384] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.884208] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.884246] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.884247] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.884286] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.884321] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.888189] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.888227] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.888262] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.888263] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.888539] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.888540] i915 0000:00:02.0: GuC submission enabled Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.888541] i915 0000:00:02.0: HuC enabled Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.888667] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.888727] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.888831] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.888925] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:39:09 GLK-2-GLKRVP1DDR405 kernel: [ 351.889017] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804072] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804076] missed_breadcrumb current seqno 1e, last 1f, hangcheck 1e [2976 ms], inflight 1 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804077] missed_breadcrumb Reset count: 0 (global 14) Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804078] missed_breadcrumb Requests: Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804080] missed_breadcrumb first 1f [4:f] prio=0 @ 3896ms: gem_evict_every[1722]/0 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804082] missed_breadcrumb last 1f [4:f] prio=0 @ 3896ms: gem_evict_every[1722]/0 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804083] missed_breadcrumb active 1f [4:f] prio=0 @ 3896ms: gem_evict_every[1722]/0 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804085] missed_breadcrumb [head 06c8, postfix 0720, tail 0740, batch 0x00000000_00040000] Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804097] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804099] missed_breadcrumb RING_HEAD: 0x00000708 [0x000006c0] Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804101] missed_breadcrumb RING_TAIL: 0x00000740 [0x00000740] Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804105] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804108] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804112] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804117] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804121] missed_breadcrumb DMA_FADDR: 0x00000000_00040040 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804123] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804125] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804128] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804131] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804133] missed_breadcrumb ELSP[0] count=1, rq: 1f [4:f] prio=0 @ 3896ms: gem_evict_every[1722]/0 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804133] missed_breadcrumb ELSP[1] idle Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804134] missed_breadcrumb HW active? 0x1 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804135] missed_breadcrumb E 1f [4:f] prio=0 @ 3896ms: gem_evict_every[1722]/0 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804136] missed_breadcrumb gem_evict_every [1725] waiting for 1f Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804138] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804139] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804140] missed_breadcrumb HWSP: Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804143] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804144] missed_breadcrumb * Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804146] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804147] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804149] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804150] missed_breadcrumb * Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804151] missed_breadcrumb 000000c0 0000001e 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804153] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804153] missed_breadcrumb * Dec 4 14:39:13 GLK-2-GLKRVP1DDR405 kernel: [ 355.804160] missed_breadcrumb Idle? no Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844156] hangcheck rcs0 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844161] hangcheck current seqno 1e, last 1f, hangcheck 1e [6016 ms], inflight 1 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844162] hangcheck Reset count: 0 (global 14) Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844163] hangcheck Requests: Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844166] hangcheck first 1f [4:f] prio=0 @ 6936ms: gem_evict_every[1722]/0 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844167] hangcheck last 1f [4:f] prio=0 @ 6936ms: gem_evict_every[1722]/0 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844169] hangcheck active 1f [4:f] prio=0 @ 6936ms: gem_evict_every[1722]/0 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844171] hangcheck [head 06c8, postfix 0720, tail 0740, batch 0x00000000_00040000] Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844174] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844176] hangcheck RING_HEAD: 0x00000708 [0x000006c0] Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844178] hangcheck RING_TAIL: 0x00000740 [0x00000740] Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844182] hangcheck RING_CTL: 0x00003001 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844185] hangcheck RING_MODE: 0x00000000 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844190] hangcheck ACTHD: 0x00000000_00040000 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844195] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844200] hangcheck DMA_FADDR: 0x00000000_00040200 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844202] hangcheck IPEIR: 0x00000000 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844204] hangcheck IPEHR: 0x18800001 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844207] hangcheck Execlist status: 0x00044032 001feda8 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844210] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844212] hangcheck ELSP[0] count=1, rq: 1f [4:f] prio=0 @ 6936ms: gem_evict_every[1722]/0 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844213] hangcheck ELSP[1] idle Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844213] hangcheck HW active? 0x1 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844215] hangcheck E 1f [4:f] prio=0 @ 6936ms: gem_evict_every[1722]/0 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844216] hangcheck gem_evict_every [1725] waiting for 1f Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844218] hangcheck RING_IMR: fffffefe Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844219] hangcheck IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844220] hangcheck HWSP: Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844223] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844224] hangcheck * Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844226] hangcheck 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844228] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844230] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844231] hangcheck * Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844233] hangcheck 000000c0 0000001e 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844234] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844235] hangcheck * Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.844242] hangcheck Idle? no Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.847949] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:39:16 GLK-2-GLKRVP1DDR405 kernel: [ 358.848044] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.476078] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.476624] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 136) banned? no Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.476660] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x1f Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.476780] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.476817] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.480121] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.480158] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.480162] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.480200] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.480235] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.480690] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.483288] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.483323] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.483324] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.483443] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.483444] i915 0000:00:02.0: GuC submission enabled Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.483445] i915 0000:00:02.0: HuC enabled Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.483570] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.483620] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.483713] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.483806] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:39:18 GLK-2-GLKRVP1DDR405 kernel: [ 360.483898] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828089] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828094] missed_breadcrumb current seqno 20, last 21, hangcheck 20 [3996 ms], inflight 1 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828095] missed_breadcrumb Reset count: 0 (global 15) Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828096] missed_breadcrumb Requests: Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828099] missed_breadcrumb first 21 [4:10] prio=0 @ 4336ms: gem_evict_every[1722]/0 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828100] missed_breadcrumb last 21 [4:10] prio=0 @ 4336ms: gem_evict_every[1722]/0 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828102] missed_breadcrumb active 21 [4:10] prio=0 @ 4336ms: gem_evict_every[1722]/0 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828104] missed_breadcrumb [head 0748, postfix 07a0, tail 07c0, batch 0x00000000_00000000] Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828112] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828115] missed_breadcrumb RING_HEAD: 0x00000788 [0x00000740] Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828117] missed_breadcrumb RING_TAIL: 0x000007c0 [0x000007c0] Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828120] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828124] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828129] missed_breadcrumb ACTHD: 0x0000c5c7_04118610 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828134] missed_breadcrumb BBADDR: 0x0000c5c7_04119cb1 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828139] missed_breadcrumb DMA_FADDR: 0x0000c5c7_0411b3c0 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828141] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828143] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828146] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828149] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828151] missed_breadcrumb ELSP[0] count=1, rq: 21 [4:10] prio=0 @ 4336ms: gem_evict_every[1722]/0 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828152] missed_breadcrumb ELSP[1] idle Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828153] missed_breadcrumb HW active? 0x1 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828154] missed_breadcrumb E 21 [4:10] prio=0 @ 4336ms: gem_evict_every[1722]/0 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828155] missed_breadcrumb gem_evict_every [1725] waiting for 21 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828157] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828159] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828159] missed_breadcrumb HWSP: Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828163] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828164] missed_breadcrumb * Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828166] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828168] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828170] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828170] missed_breadcrumb * Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828172] missed_breadcrumb 000000c0 00000020 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828174] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828175] missed_breadcrumb * Dec 4 14:39:22 GLK-2-GLKRVP1DDR405 kernel: [ 364.828182] missed_breadcrumb Idle? no Dec 4 14:39:32 GLK-2-GLKRVP1DDR405 kernel: [ 374.847449] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:39:32 GLK-2-GLKRVP1DDR405 kernel: [ 374.847541] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.760117] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.760673] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 145) banned? no Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.760713] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x21 Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.760842] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.760882] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.909361] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.909398] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.909400] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.909438] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.909472] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.910398] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.913458] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.913492] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.913493] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.913608] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.913609] i915 0000:00:02.0: GuC submission enabled Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.913610] i915 0000:00:02.0: HuC enabled Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.913734] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.913783] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.913876] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.913969] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:39:36 GLK-2-GLKRVP1DDR405 kernel: [ 378.914061] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828093] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828097] missed_breadcrumb current seqno 22, last 23, hangcheck 20 [1916 ms], inflight 1 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828098] missed_breadcrumb Reset count: 0 (global 16) Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828099] missed_breadcrumb Requests: Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828102] missed_breadcrumb first 23 [4:11] prio=0 @ 1912ms: gem_evict_every[1722]/0 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828103] missed_breadcrumb last 23 [4:11] prio=0 @ 1912ms: gem_evict_every[1722]/0 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828105] missed_breadcrumb active 23 [4:11] prio=0 @ 1912ms: gem_evict_every[1722]/0 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828107] missed_breadcrumb [head 07c8, postfix 0820, tail 0840, batch 0x00000000_00040000] Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828115] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828117] missed_breadcrumb RING_HEAD: 0x00000808 [0x000007c0] Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828119] missed_breadcrumb RING_TAIL: 0x00000840 [0x00000840] Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828122] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828126] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828131] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828135] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828140] missed_breadcrumb DMA_FADDR: 0x00000000_00040200 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828142] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828144] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828147] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828150] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828151] missed_breadcrumb ELSP[0] count=1, rq: 23 [4:11] prio=0 @ 1912ms: gem_evict_every[1722]/0 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828152] missed_breadcrumb ELSP[1] idle Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828153] missed_breadcrumb HW active? 0x1 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828154] missed_breadcrumb E 23 [4:11] prio=0 @ 1912ms: gem_evict_every[1722]/0 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828155] missed_breadcrumb gem_evict_every [1725] waiting for 23 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828157] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828159] missed_breadcrumb IRQ? 0x0 (breadcrumbs? no) (execlists? no) Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828159] missed_breadcrumb HWSP: Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828162] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828163] missed_breadcrumb * Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828165] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828167] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828169] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828169] missed_breadcrumb * Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828171] missed_breadcrumb 000000c0 00000022 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828173] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828173] missed_breadcrumb * Dec 4 14:39:38 GLK-2-GLKRVP1DDR405 kernel: [ 380.828180] missed_breadcrumb Idle? no Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828066] hangcheck rcs0 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828071] hangcheck current seqno 22, last 23, hangcheck 22 [6016 ms], inflight 1 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828072] hangcheck Reset count: 0 (global 16) Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828073] hangcheck Requests: Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828076] hangcheck first 23 [4:11] prio=0 @ 9912ms: gem_evict_every[1722]/0 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828077] hangcheck last 23 [4:11] prio=0 @ 9912ms: gem_evict_every[1722]/0 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828079] hangcheck active 23 [4:11] prio=0 @ 9912ms: gem_evict_every[1722]/0 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828081] hangcheck [head 07c8, postfix 0820, tail 0840, batch 0x00000000_00040000] Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828084] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828086] hangcheck RING_HEAD: 0x00000808 [0x000007c0] Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828088] hangcheck RING_TAIL: 0x00000840 [0x00000840] Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828091] hangcheck RING_CTL: 0x00003001 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828095] hangcheck RING_MODE: 0x00000000 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828099] hangcheck ACTHD: 0x00000000_00040000 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828104] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828108] hangcheck DMA_FADDR: 0x00000000_00040200 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828110] hangcheck IPEIR: 0x00000000 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828112] hangcheck IPEHR: 0x18800001 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828116] hangcheck Execlist status: 0x00044032 001feda8 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828118] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828120] hangcheck ELSP[0] count=1, rq: 23 [4:11] prio=0 @ 9912ms: gem_evict_every[1722]/0 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828121] hangcheck ELSP[1] idle Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828122] hangcheck HW active? 0x1 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828123] hangcheck E 23 [4:11] prio=0 @ 9912ms: gem_evict_every[1722]/0 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828124] hangcheck gem_evict_every [1725] waiting for 23 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828126] hangcheck RING_IMR: fffffefe Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828127] hangcheck IRQ? 0x0 (breadcrumbs? no) (execlists? no) Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828127] hangcheck HWSP: Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828130] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828131] hangcheck * Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828133] hangcheck 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828135] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828137] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828137] hangcheck * Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828139] hangcheck 000000c0 00000022 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828141] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828141] hangcheck * Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.828147] hangcheck Idle? no Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.831828] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:39:46 GLK-2-GLKRVP1DDR405 kernel: [ 388.831922] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.396036] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.396438] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 154) banned? no Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.396471] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x23 Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.396586] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.396619] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.400186] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.400219] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.400220] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.400255] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.400286] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.400606] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.403201] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.403232] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.403233] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.403319] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.403320] i915 0000:00:02.0: GuC submission enabled Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.403321] i915 0000:00:02.0: HuC enabled Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.403442] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.403489] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.403579] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.403669] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:39:49 GLK-2-GLKRVP1DDR405 kernel: [ 391.403759] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804078] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804083] missed_breadcrumb current seqno 24, last 25, hangcheck 24 [960 ms], inflight 1 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804084] missed_breadcrumb Reset count: 0 (global 17) Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804084] missed_breadcrumb Requests: Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804087] missed_breadcrumb first 25 [4:12] prio=0 @ 4392ms: gem_evict_every[1722]/0 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804088] missed_breadcrumb last 25 [4:12] prio=0 @ 4392ms: gem_evict_every[1722]/0 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804090] missed_breadcrumb active 25 [4:12] prio=0 @ 4392ms: gem_evict_every[1722]/0 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804092] missed_breadcrumb [head 0848, postfix 08a0, tail 08c0, batch 0x00000000_00000000] Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804099] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804102] missed_breadcrumb RING_HEAD: 0x00000888 [0x00000840] Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804104] missed_breadcrumb RING_TAIL: 0x000008c0 [0x000008c0] Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804107] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804111] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804115] missed_breadcrumb ACTHD: 0x0000c5c7_0aedd5c0 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804120] missed_breadcrumb BBADDR: 0x0000c5c7_0aedebc1 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804125] missed_breadcrumb DMA_FADDR: 0x0000c5c7_0aee02c0 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804127] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804129] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804132] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804135] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804136] missed_breadcrumb ELSP[0] count=1, rq: 25 [4:12] prio=0 @ 4392ms: gem_evict_every[1722]/0 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804137] missed_breadcrumb ELSP[1] idle Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804138] missed_breadcrumb HW active? 0x1 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804139] missed_breadcrumb E 25 [4:12] prio=0 @ 4392ms: gem_evict_every[1722]/0 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804140] missed_breadcrumb gem_evict_every [1725] waiting for 25 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804142] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804143] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804144] missed_breadcrumb HWSP: Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804147] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804148] missed_breadcrumb * Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804150] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804152] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804153] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804154] missed_breadcrumb * Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804156] missed_breadcrumb 000000c0 00000024 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804157] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804158] missed_breadcrumb * Dec 4 14:39:53 GLK-2-GLKRVP1DDR405 kernel: [ 395.804165] missed_breadcrumb Idle? no Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.831324] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.831414] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.831444] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.833389] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 163) banned? no Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.833421] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x25 Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.833543] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.833575] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.834332] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.834366] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.834367] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.834401] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.834432] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.834726] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.837329] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.837360] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.837361] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.837444] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.837445] i915 0000:00:02.0: GuC submission enabled Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.837446] i915 0000:00:02.0: HuC enabled Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.837565] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.837611] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.837699] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.837788] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:40:06 GLK-2-GLKRVP1DDR405 kernel: [ 408.837876] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828087] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828091] missed_breadcrumb current seqno 26, last 27, hangcheck 26 [2016 ms], inflight 1 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828093] missed_breadcrumb Reset count: 0 (global 18) Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828093] missed_breadcrumb Requests: Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828096] missed_breadcrumb first 27 [4:13] prio=0 @ 3984ms: gem_evict_every[1722]/0 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828097] missed_breadcrumb last 27 [4:13] prio=0 @ 3984ms: gem_evict_every[1722]/0 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828099] missed_breadcrumb active 27 [4:13] prio=0 @ 3984ms: gem_evict_every[1722]/0 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828101] missed_breadcrumb [head 08c0, postfix 0918, tail 0938, batch 0x00000000_00000000] Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828105] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828108] missed_breadcrumb RING_HEAD: 0x00000900 [0x000008c0] Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828111] missed_breadcrumb RING_TAIL: 0x00000938 [0x00000938] Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828117] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828122] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828129] missed_breadcrumb ACTHD: 0x0000c5c6_ee8fe000 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828134] missed_breadcrumb BBADDR: 0x0000c5c6_ee8ff691 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828139] missed_breadcrumb DMA_FADDR: 0x0000c5c6_ee9010c0 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828141] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828143] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828147] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828149] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828151] missed_breadcrumb ELSP[0] count=1, rq: 27 [4:13] prio=0 @ 3984ms: gem_evict_every[1722]/0 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828152] missed_breadcrumb ELSP[1] idle Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828153] missed_breadcrumb HW active? 0x1 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828154] missed_breadcrumb E 27 [4:13] prio=0 @ 3984ms: gem_evict_every[1722]/0 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828156] missed_breadcrumb gem_evict_every [1725] waiting for 27 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828158] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828159] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828160] missed_breadcrumb HWSP: Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828163] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828164] missed_breadcrumb * Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828166] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828168] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828170] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828171] missed_breadcrumb * Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828172] missed_breadcrumb 000000c0 00000026 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828174] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828175] missed_breadcrumb * Dec 4 14:40:10 GLK-2-GLKRVP1DDR405 kernel: [ 412.828182] missed_breadcrumb Idle? no Dec 4 14:40:20 GLK-2-GLKRVP1DDR405 kernel: [ 422.847952] [drm] GPU HANG: ecode 9:0:0xe7577ffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:40:20 GLK-2-GLKRVP1DDR405 kernel: [ 422.848046] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.124053] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.124874] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 172) banned? no Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.124909] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x27 Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.125030] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.125066] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.132056] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.132092] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.132093] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.132131] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.132165] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.132639] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.134758] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.134790] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.134791] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.135021] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.135022] i915 0000:00:02.0: GuC submission enabled Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.135023] i915 0000:00:02.0: HuC enabled Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.135146] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.135193] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.135284] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.135374] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:40:23 GLK-2-GLKRVP1DDR405 kernel: [ 426.135464] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812080] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812084] missed_breadcrumb current seqno 28, last 29, hangcheck 28 [1984 ms], inflight 1 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812085] missed_breadcrumb Reset count: 0 (global 19) Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812086] missed_breadcrumb Requests: Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812089] missed_breadcrumb first 29 [4:14] prio=0 @ 4660ms: gem_evict_every[1722]/0 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812090] missed_breadcrumb last 29 [4:14] prio=0 @ 4660ms: gem_evict_every[1722]/0 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812092] missed_breadcrumb active 29 [4:14] prio=0 @ 4660ms: gem_evict_every[1722]/0 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812094] missed_breadcrumb [head 0940, postfix 0998, tail 09b8, batch 0x00000000_00040000] Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812102] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812105] missed_breadcrumb RING_HEAD: 0x00000980 [0x00000938] Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812107] missed_breadcrumb RING_TAIL: 0x000009b8 [0x000009b8] Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812110] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812113] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812118] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812123] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812128] missed_breadcrumb DMA_FADDR: 0x00000000_00040200 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812130] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812132] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812135] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812138] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812140] missed_breadcrumb ELSP[0] count=1, rq: 29 [4:14] prio=0 @ 4660ms: gem_evict_every[1722]/0 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812141] missed_breadcrumb ELSP[1] idle Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812141] missed_breadcrumb HW active? 0x1 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812143] missed_breadcrumb E 29 [4:14] prio=0 @ 4660ms: gem_evict_every[1722]/0 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812144] missed_breadcrumb gem_evict_every [1725] waiting for 29 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812146] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812147] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812148] missed_breadcrumb HWSP: Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812151] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812152] missed_breadcrumb * Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812154] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812156] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812158] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812158] missed_breadcrumb * Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812160] missed_breadcrumb 000000c0 00000028 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812162] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812163] missed_breadcrumb * Dec 4 14:40:28 GLK-2-GLKRVP1DDR405 kernel: [ 430.812169] missed_breadcrumb Idle? no Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844066] hangcheck rcs0 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844071] hangcheck current seqno 28, last 29, hangcheck 28 [6016 ms], inflight 1 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844072] hangcheck Reset count: 0 (global 19) Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844073] hangcheck Requests: Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844076] hangcheck first 29 [4:14] prio=0 @ 8692ms: gem_evict_every[1722]/0 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844077] hangcheck last 29 [4:14] prio=0 @ 8692ms: gem_evict_every[1722]/0 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844079] hangcheck active 29 [4:14] prio=0 @ 8692ms: gem_evict_every[1722]/0 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844081] hangcheck [head 0940, postfix 0998, tail 09b8, batch 0x00000000_00040000] Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844083] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844086] hangcheck RING_HEAD: 0x00000980 [0x00000938] Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844088] hangcheck RING_TAIL: 0x000009b8 [0x000009b8] Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844091] hangcheck RING_CTL: 0x00003001 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844094] hangcheck RING_MODE: 0x00000000 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844099] hangcheck ACTHD: 0x00000000_00040000 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844103] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844108] hangcheck DMA_FADDR: 0x00000000_00040200 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844110] hangcheck IPEIR: 0x00000000 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844112] hangcheck IPEHR: 0x18800001 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844116] hangcheck Execlist status: 0x00044032 001feda5 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844118] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844120] hangcheck ELSP[0] count=1, rq: 29 [4:14] prio=0 @ 8692ms: gem_evict_every[1722]/0 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844121] hangcheck ELSP[1] idle Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844121] hangcheck HW active? 0x1 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844123] hangcheck E 29 [4:14] prio=0 @ 8692ms: gem_evict_every[1722]/0 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844124] hangcheck gem_evict_every [1725] waiting for 29 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844126] hangcheck RING_IMR: fffffefe Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844127] hangcheck IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844128] hangcheck HWSP: Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844130] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844131] hangcheck * Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844133] hangcheck 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844135] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844137] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844138] hangcheck * Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844139] hangcheck 000000c0 00000028 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844141] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844141] hangcheck * Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.844148] hangcheck Idle? no Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.847712] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 434.847803] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.204049] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.205014] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 181) banned? no Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.205048] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x29 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.205166] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.205201] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.208152] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.208187] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.208188] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.208224] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.208257] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.212162] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.212197] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.212230] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.212231] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.212456] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.212458] i915 0000:00:02.0: GuC submission enabled Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.212459] i915 0000:00:02.0: HuC enabled Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.212583] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.212631] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.212722] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.212812] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:40:32 GLK-2-GLKRVP1DDR405 kernel: [ 435.212903] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844076] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844080] missed_breadcrumb current seqno 2a, last 2b, hangcheck 2a [2016 ms], inflight 1 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844081] missed_breadcrumb Reset count: 0 (global 20) Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844081] missed_breadcrumb Requests: Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844084] missed_breadcrumb first 2b [4:15] prio=0 @ 3624ms: gem_evict_every[1722]/0 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844085] missed_breadcrumb last 2b [4:15] prio=0 @ 3624ms: gem_evict_every[1722]/0 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844086] missed_breadcrumb active 2b [4:15] prio=0 @ 3624ms: gem_evict_every[1722]/0 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844088] missed_breadcrumb [head 09c0, postfix 0a18, tail 0a38, batch 0x00000000_00000000] Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844096] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844098] missed_breadcrumb RING_HEAD: 0x00000a00 [0x000009b8] Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844100] missed_breadcrumb RING_TAIL: 0x00000a38 [0x00000a38] Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844103] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844107] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844112] missed_breadcrumb ACTHD: 0x0000c5c6_cbf1c3dc Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844116] missed_breadcrumb BBADDR: 0x0000c5c6_cbf1dc9d Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844121] missed_breadcrumb DMA_FADDR: 0x0000c5c6_cbf1f840 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844123] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844125] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844128] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844131] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844133] missed_breadcrumb ELSP[0] count=1, rq: 2b [4:15] prio=0 @ 3624ms: gem_evict_every[1722]/0 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844133] missed_breadcrumb ELSP[1] idle Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844134] missed_breadcrumb HW active? 0x1 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844135] missed_breadcrumb E 2b [4:15] prio=0 @ 3624ms: gem_evict_every[1722]/0 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844136] missed_breadcrumb gem_evict_every [1725] waiting for 2b Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844138] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844139] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844140] missed_breadcrumb HWSP: Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844143] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844143] missed_breadcrumb * Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844145] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844147] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844149] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844149] missed_breadcrumb * Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844151] missed_breadcrumb 000000c0 0000002a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844153] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844153] missed_breadcrumb * Dec 4 14:40:36 GLK-2-GLKRVP1DDR405 kernel: [ 438.844159] missed_breadcrumb Idle? no Dec 4 14:40:46 GLK-2-GLKRVP1DDR405 kernel: [ 448.835507] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:40:46 GLK-2-GLKRVP1DDR405 kernel: [ 448.835628] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.788129] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.788921] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 190) banned? no Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.788955] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x2b Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.789076] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.789110] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.793959] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.793994] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.793995] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.794031] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.794064] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.795414] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.798116] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.798150] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.798151] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.798377] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.798378] i915 0000:00:02.0: GuC submission enabled Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.798379] i915 0000:00:02.0: HuC enabled Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.798501] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.798549] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.798639] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.798730] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:40:49 GLK-2-GLKRVP1DDR405 kernel: [ 451.798820] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836079] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836083] missed_breadcrumb current seqno 2c, last 2d, hangcheck 2c [992 ms], inflight 1 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836084] missed_breadcrumb Reset count: 0 (global 21) Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836085] missed_breadcrumb Requests: Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836087] missed_breadcrumb first 2d [4:16] prio=0 @ 4024ms: gem_evict_every[1722]/0 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836088] missed_breadcrumb last 2d [4:16] prio=0 @ 4024ms: gem_evict_every[1722]/0 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836090] missed_breadcrumb active 2d [4:16] prio=0 @ 4024ms: gem_evict_every[1722]/0 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836092] missed_breadcrumb [head 0a40, postfix 0a98, tail 0ab8, batch 0x00000000_00040000] Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836100] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836102] missed_breadcrumb RING_HEAD: 0x00000a80 [0x00000a38] Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836104] missed_breadcrumb RING_TAIL: 0x00000ab8 [0x00000ab8] Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836107] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836111] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836115] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836120] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836124] missed_breadcrumb DMA_FADDR: 0x00000000_00040200 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836127] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836128] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836132] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836134] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836136] missed_breadcrumb ELSP[0] count=1, rq: 2d [4:16] prio=0 @ 4024ms: gem_evict_every[1722]/0 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836137] missed_breadcrumb ELSP[1] idle Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836137] missed_breadcrumb HW active? 0x1 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836139] missed_breadcrumb E 2d [4:16] prio=0 @ 4024ms: gem_evict_every[1722]/0 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836140] missed_breadcrumb gem_evict_every [1725] waiting for 2d Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836142] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836143] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836144] missed_breadcrumb HWSP: Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836146] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836147] missed_breadcrumb * Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836149] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836151] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836153] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836153] missed_breadcrumb * Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836155] missed_breadcrumb 000000c0 0000002c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836157] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836157] missed_breadcrumb * Dec 4 14:40:53 GLK-2-GLKRVP1DDR405 kernel: [ 455.836164] missed_breadcrumb Idle? no Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828065] hangcheck rcs0 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828069] hangcheck current seqno 2c, last 2d, hangcheck 2c [5984 ms], inflight 1 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828071] hangcheck Reset count: 0 (global 21) Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828071] hangcheck Requests: Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828074] hangcheck first 2d [4:16] prio=0 @ 9016ms: gem_evict_every[1722]/0 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828075] hangcheck last 2d [4:16] prio=0 @ 9016ms: gem_evict_every[1722]/0 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828077] hangcheck active 2d [4:16] prio=0 @ 9016ms: gem_evict_every[1722]/0 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828079] hangcheck [head 0a40, postfix 0a98, tail 0ab8, batch 0x00000000_00040000] Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828081] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828083] hangcheck RING_HEAD: 0x00000a80 [0x00000a38] Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828085] hangcheck RING_TAIL: 0x00000ab8 [0x00000ab8] Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828088] hangcheck RING_CTL: 0x00003001 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828092] hangcheck RING_MODE: 0x00000000 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828096] hangcheck ACTHD: 0x00000000_00040000 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828100] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828105] hangcheck DMA_FADDR: 0x00000000_00040200 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828107] hangcheck IPEIR: 0x00000000 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828109] hangcheck IPEHR: 0x18800001 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828112] hangcheck Execlist status: 0x00044032 001feda5 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828115] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828116] hangcheck ELSP[0] count=1, rq: 2d [4:16] prio=0 @ 9016ms: gem_evict_every[1722]/0 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828117] hangcheck ELSP[1] idle Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828118] hangcheck HW active? 0x1 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828119] hangcheck E 2d [4:16] prio=0 @ 9016ms: gem_evict_every[1722]/0 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828120] hangcheck gem_evict_every [1725] waiting for 2d Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828122] hangcheck RING_IMR: fffffefe Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828123] hangcheck IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828123] hangcheck HWSP: Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828126] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828127] hangcheck * Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828129] hangcheck 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828131] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828132] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828133] hangcheck * Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828135] hangcheck 000000c0 0000002c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828136] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828137] hangcheck * Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.828143] hangcheck Idle? no Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.831627] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:40:58 GLK-2-GLKRVP1DDR405 kernel: [ 460.831718] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.608218] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.609369] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 199) banned? no Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.609403] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x2d Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.609520] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.609554] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.612152] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.612186] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.612187] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.612223] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.612256] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.612657] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.614671] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.614704] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.614705] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.614931] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.614932] i915 0000:00:02.0: GuC submission enabled Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.614933] i915 0000:00:02.0: HuC enabled Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.615056] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.615103] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.615193] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.615284] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:40:59 GLK-2-GLKRVP1DDR405 kernel: [ 461.615374] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804081] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804085] missed_breadcrumb current seqno 2e, last 2f, hangcheck 2e [988 ms], inflight 1 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804086] missed_breadcrumb Reset count: 0 (global 22) Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804087] missed_breadcrumb Requests: Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804090] missed_breadcrumb first 2f [4:17] prio=0 @ 2168ms: gem_evict_every[1722]/0 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804091] missed_breadcrumb last 2f [4:17] prio=0 @ 2168ms: gem_evict_every[1722]/0 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804092] missed_breadcrumb active 2f [4:17] prio=0 @ 2168ms: gem_evict_every[1722]/0 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804094] missed_breadcrumb [head 0ac0, postfix 0b18, tail 0b38, batch 0x00000000_00000000] Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804102] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804105] missed_breadcrumb RING_HEAD: 0x00000b00 [0x00000ab8] Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804107] missed_breadcrumb RING_TAIL: 0x00000b38 [0x00000b38] Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804110] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804114] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804118] missed_breadcrumb ACTHD: 0x0000c5c6_51e1051c Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804123] missed_breadcrumb BBADDR: 0x0000c5c6_51e11a41 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804128] missed_breadcrumb DMA_FADDR: 0x0000c5c6_51e131c0 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804130] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804132] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804136] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804138] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804140] missed_breadcrumb ELSP[0] count=1, rq: 2f [4:17] prio=0 @ 2168ms: gem_evict_every[1722]/0 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804141] missed_breadcrumb ELSP[1] idle Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804141] missed_breadcrumb HW active? 0x1 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804143] missed_breadcrumb E 2f [4:17] prio=0 @ 2168ms: gem_evict_every[1722]/0 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804144] missed_breadcrumb gem_evict_every [1725] waiting for 2f Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804146] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804147] missed_breadcrumb IRQ? 0x0 (breadcrumbs? no) (execlists? no) Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804148] missed_breadcrumb HWSP: Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804151] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804152] missed_breadcrumb * Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804154] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804156] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804157] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804158] missed_breadcrumb * Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804160] missed_breadcrumb 000000c0 0000002e 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804162] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804162] missed_breadcrumb * Dec 4 14:41:01 GLK-2-GLKRVP1DDR405 kernel: [ 463.804169] missed_breadcrumb Idle? no Dec 4 14:41:14 GLK-2-GLKRVP1DDR405 kernel: [ 476.831586] [drm] GPU HANG: ecode 9:0:0xe7577ffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:41:14 GLK-2-GLKRVP1DDR405 kernel: [ 476.831678] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.500063] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.500490] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 208) banned? no Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.500526] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x2f Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.500647] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.500683] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.508058] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.508093] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.508095] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.508131] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.508164] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.508633] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.511028] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.511062] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.511063] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.511174] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.511175] i915 0000:00:02.0: GuC submission enabled Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.511176] i915 0000:00:02.0: HuC enabled Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.511301] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.511350] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.511442] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.511535] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:41:18 GLK-2-GLKRVP1DDR405 kernel: [ 480.511627] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828084] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828090] missed_breadcrumb current seqno 30, last 31, hangcheck 30 [2016 ms], inflight 1 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828091] missed_breadcrumb Reset count: 0 (global 23) Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828091] missed_breadcrumb Requests: Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828094] missed_breadcrumb first 31 [4:18] prio=0 @ 4304ms: gem_evict_every[1722]/0 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828095] missed_breadcrumb last 31 [4:18] prio=0 @ 4304ms: gem_evict_every[1722]/0 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828097] missed_breadcrumb active 31 [4:18] prio=0 @ 4304ms: gem_evict_every[1722]/0 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828099] missed_breadcrumb [head 0b40, postfix 0b98, tail 0bb8, batch 0x00000000_00040000] Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828108] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828110] missed_breadcrumb RING_HEAD: 0x00000b80 [0x00000b38] Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828112] missed_breadcrumb RING_TAIL: 0x00000bb8 [0x00000bb8] Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828115] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828119] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828124] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828128] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828133] missed_breadcrumb DMA_FADDR: 0x00000000_00040200 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828135] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828137] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828140] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828143] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828145] missed_breadcrumb ELSP[0] count=1, rq: 31 [4:18] prio=0 @ 4304ms: gem_evict_every[1722]/0 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828146] missed_breadcrumb ELSP[1] idle Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828146] missed_breadcrumb HW active? 0x1 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828148] missed_breadcrumb E 31 [4:18] prio=0 @ 4304ms: gem_evict_every[1722]/0 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828149] missed_breadcrumb gem_evict_every [1725] waiting for 31 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828151] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828152] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828153] missed_breadcrumb HWSP: Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828156] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828157] missed_breadcrumb * Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828159] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828161] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828162] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828163] missed_breadcrumb * Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828165] missed_breadcrumb 000000c0 00000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828167] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828167] missed_breadcrumb * Dec 4 14:41:22 GLK-2-GLKRVP1DDR405 kernel: [ 484.828174] missed_breadcrumb Idle? no Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828059] hangcheck rcs0 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828063] hangcheck current seqno 30, last 31, hangcheck 30 [6016 ms], inflight 1 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828065] hangcheck Reset count: 0 (global 23) Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828065] hangcheck Requests: Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828068] hangcheck first 31 [4:18] prio=0 @ 8304ms: gem_evict_every[1722]/0 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828069] hangcheck last 31 [4:18] prio=0 @ 8304ms: gem_evict_every[1722]/0 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828070] hangcheck active 31 [4:18] prio=0 @ 8304ms: gem_evict_every[1722]/0 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828072] hangcheck [head 0b40, postfix 0b98, tail 0bb8, batch 0x00000000_00040000] Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828075] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828077] hangcheck RING_HEAD: 0x00000b80 [0x00000b38] Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828079] hangcheck RING_TAIL: 0x00000bb8 [0x00000bb8] Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828082] hangcheck RING_CTL: 0x00003001 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828086] hangcheck RING_MODE: 0x00000000 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828090] hangcheck ACTHD: 0x00000000_00040000 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828095] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828099] hangcheck DMA_FADDR: 0x00000000_00040200 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828102] hangcheck IPEIR: 0x00000000 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828104] hangcheck IPEHR: 0x18800001 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828107] hangcheck Execlist status: 0x00044032 001feda5 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828109] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828111] hangcheck ELSP[0] count=1, rq: 31 [4:18] prio=0 @ 8304ms: gem_evict_every[1722]/0 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828112] hangcheck ELSP[1] idle Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828113] hangcheck HW active? 0x1 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828114] hangcheck E 31 [4:18] prio=0 @ 8304ms: gem_evict_every[1722]/0 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828115] hangcheck gem_evict_every [1725] waiting for 31 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828117] hangcheck RING_IMR: fffffefe Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828118] hangcheck IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828119] hangcheck HWSP: Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828122] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828122] hangcheck * Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828124] hangcheck 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828126] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828128] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828128] hangcheck * Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828130] hangcheck 000000c0 00000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828132] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828132] hangcheck * Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.828139] hangcheck Idle? no Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.831898] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:41:26 GLK-2-GLKRVP1DDR405 kernel: [ 488.831991] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.592071] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.592572] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 217) banned? no Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.592607] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x31 Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.592727] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.592764] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.596065] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.596103] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.596108] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.596148] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.596183] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.596651] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.598747] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.598781] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.598782] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.598893] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.598894] i915 0000:00:02.0: GuC submission enabled Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.598895] i915 0000:00:02.0: HuC enabled Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.599020] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.599069] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.599162] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.599254] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:41:27 GLK-2-GLKRVP1DDR405 kernel: [ 489.599346] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824081] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824091] missed_breadcrumb current seqno 32, last 33, hangcheck 32 [2980 ms], inflight 1 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824092] missed_breadcrumb Reset count: 0 (global 24) Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824093] missed_breadcrumb Requests: Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824095] missed_breadcrumb first 33 [4:19] prio=0 @ 4204ms: gem_evict_every[1722]/0 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824097] missed_breadcrumb last 33 [4:19] prio=0 @ 4204ms: gem_evict_every[1722]/0 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824099] missed_breadcrumb active 33 [4:19] prio=0 @ 4204ms: gem_evict_every[1722]/0 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824100] missed_breadcrumb [head 0bc0, postfix 0c18, tail 0c38, batch 0x00000000_00000000] Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824109] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824111] missed_breadcrumb RING_HEAD: 0x00000c00 [0x00000bb8] Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824113] missed_breadcrumb RING_TAIL: 0x00000c38 [0x00000c38] Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824117] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824120] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824125] missed_breadcrumb ACTHD: 0x0000c5c6_e0e7d614 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824129] missed_breadcrumb BBADDR: 0x0000c5c6_e0e7ecd9 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824134] missed_breadcrumb DMA_FADDR: 0x0000c5c6_e0e803c0 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824137] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824139] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824143] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824145] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824147] missed_breadcrumb ELSP[0] count=1, rq: 33 [4:19] prio=0 @ 4204ms: gem_evict_every[1722]/0 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824148] missed_breadcrumb ELSP[1] idle Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824148] missed_breadcrumb HW active? 0x1 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824150] missed_breadcrumb E 33 [4:19] prio=0 @ 4204ms: gem_evict_every[1722]/0 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824151] missed_breadcrumb gem_evict_every [1725] waiting for 33 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824153] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824154] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824155] missed_breadcrumb HWSP: Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824158] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824159] missed_breadcrumb * Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824161] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824162] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824164] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824165] missed_breadcrumb * Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824166] missed_breadcrumb 000000c0 00000032 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824168] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824169] missed_breadcrumb * Dec 4 14:41:31 GLK-2-GLKRVP1DDR405 kernel: [ 493.824175] missed_breadcrumb Idle? no Dec 4 14:41:42 GLK-2-GLKRVP1DDR405 kernel: [ 504.831562] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:41:42 GLK-2-GLKRVP1DDR405 kernel: [ 504.831659] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.308037] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.308639] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 226) banned? no Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.308675] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x33 Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.308795] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.308831] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.313963] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.314000] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.314001] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.314038] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.314072] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.315247] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.317850] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.317885] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.317886] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.317997] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.317998] i915 0000:00:02.0: GuC submission enabled Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.317999] i915 0000:00:02.0: HuC enabled Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.318124] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.318173] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.318266] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.318358] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:41:43 GLK-2-GLKRVP1DDR405 kernel: [ 506.318450] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844080] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844085] missed_breadcrumb current seqno 34, last 35, hangcheck 34 [4032 ms], inflight 1 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844086] missed_breadcrumb Reset count: 0 (global 25) Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844086] missed_breadcrumb Requests: Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844089] missed_breadcrumb first 35 [4:1a] prio=0 @ 4512ms: gem_evict_every[1722]/0 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844090] missed_breadcrumb last 35 [4:1a] prio=0 @ 4512ms: gem_evict_every[1722]/0 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844091] missed_breadcrumb active 35 [4:1a] prio=0 @ 4512ms: gem_evict_every[1722]/0 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844093] missed_breadcrumb [head 0c40, postfix 0c98, tail 0cb8, batch 0x00000000_00040000] Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844100] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844102] missed_breadcrumb RING_HEAD: 0x00000c80 [0x00000c38] Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844104] missed_breadcrumb RING_TAIL: 0x00000cb8 [0x00000cb8] Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844107] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844110] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844115] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844119] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844124] missed_breadcrumb DMA_FADDR: 0x00000000_00040200 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844125] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844127] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844131] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844133] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844134] missed_breadcrumb ELSP[0] count=1, rq: 35 [4:1a] prio=0 @ 4512ms: gem_evict_every[1722]/0 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844135] missed_breadcrumb ELSP[1] idle Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844136] missed_breadcrumb HW active? 0x1 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844137] missed_breadcrumb E 35 [4:1a] prio=0 @ 4512ms: gem_evict_every[1722]/0 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844138] missed_breadcrumb gem_evict_every [1725] waiting for 35 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844140] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844141] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844141] missed_breadcrumb HWSP: Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844144] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844145] missed_breadcrumb * Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844147] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844148] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844150] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844150] missed_breadcrumb * Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844152] missed_breadcrumb 000000c0 00000034 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844154] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844154] missed_breadcrumb * Dec 4 14:41:48 GLK-2-GLKRVP1DDR405 kernel: [ 510.844160] missed_breadcrumb Idle? no Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828066] hangcheck rcs0 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828071] hangcheck current seqno 34, last 35, hangcheck 34 [6016 ms], inflight 1 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828073] hangcheck Reset count: 0 (global 25) Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828073] hangcheck Requests: Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828076] hangcheck first 35 [4:1a] prio=0 @ 6496ms: gem_evict_every[1722]/0 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828077] hangcheck last 35 [4:1a] prio=0 @ 6496ms: gem_evict_every[1722]/0 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828079] hangcheck active 35 [4:1a] prio=0 @ 6496ms: gem_evict_every[1722]/0 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828081] hangcheck [head 0c40, postfix 0c98, tail 0cb8, batch 0x00000000_00040000] Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828084] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828086] hangcheck RING_HEAD: 0x00000c80 [0x00000c38] Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828088] hangcheck RING_TAIL: 0x00000cb8 [0x00000cb8] Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828091] hangcheck RING_CTL: 0x00003001 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828094] hangcheck RING_MODE: 0x00000000 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828099] hangcheck ACTHD: 0x00000000_00040000 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828103] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828108] hangcheck DMA_FADDR: 0x00000000_00040200 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828110] hangcheck IPEIR: 0x00000000 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828112] hangcheck IPEHR: 0x18800001 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828115] hangcheck Execlist status: 0x00044032 001feda5 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828118] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828119] hangcheck ELSP[0] count=1, rq: 35 [4:1a] prio=0 @ 6496ms: gem_evict_every[1722]/0 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828120] hangcheck ELSP[1] idle Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828121] hangcheck HW active? 0x1 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828122] hangcheck E 35 [4:1a] prio=0 @ 6496ms: gem_evict_every[1722]/0 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828123] hangcheck gem_evict_every [1725] waiting for 35 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828125] hangcheck RING_IMR: fffffefe Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828126] hangcheck IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828127] hangcheck HWSP: Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828130] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828131] hangcheck * Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828133] hangcheck 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828135] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828136] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828137] hangcheck * Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828139] hangcheck 000000c0 00000034 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828140] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828141] hangcheck * Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.828147] hangcheck Idle? no Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.831793] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:41:50 GLK-2-GLKRVP1DDR405 kernel: [ 512.831887] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.300097] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.301224] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 235) banned? no Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.301260] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x35 Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.301384] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.301421] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.304344] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.304380] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.304382] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.304420] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.304454] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.304876] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.306756] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.306791] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.306792] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.307139] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.307141] i915 0000:00:02.0: GuC submission enabled Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.307142] i915 0000:00:02.0: HuC enabled Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.307268] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.307317] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.307410] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.307504] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:41:53 GLK-2-GLKRVP1DDR405 kernel: [ 516.307597] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828082] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828091] missed_breadcrumb current seqno 36, last 37, hangcheck 36 [2016 ms], inflight 1 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828092] missed_breadcrumb Reset count: 0 (global 26) Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828092] missed_breadcrumb Requests: Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828095] missed_breadcrumb first 37 [4:1b] prio=0 @ 4500ms: gem_evict_every[1722]/0 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828097] missed_breadcrumb last 37 [4:1b] prio=0 @ 4500ms: gem_evict_every[1722]/0 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828098] missed_breadcrumb active 37 [4:1b] prio=0 @ 4500ms: gem_evict_every[1722]/0 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828100] missed_breadcrumb [head 0cc0, postfix 0d18, tail 0d38, batch 0x00000000_00000000] Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828109] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828111] missed_breadcrumb RING_HEAD: 0x00000d00 [0x00000cb8] Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828113] missed_breadcrumb RING_TAIL: 0x00000d38 [0x00000d38] Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828116] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828120] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828124] missed_breadcrumb ACTHD: 0x0000c5c7_062651c0 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828129] missed_breadcrumb BBADDR: 0x0000c5c7_06266605 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828134] missed_breadcrumb DMA_FADDR: 0x0000c5c7_06268040 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828136] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828138] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828141] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828144] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828146] missed_breadcrumb ELSP[0] count=1, rq: 37 [4:1b] prio=0 @ 4500ms: gem_evict_every[1722]/0 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828146] missed_breadcrumb ELSP[1] idle Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828147] missed_breadcrumb HW active? 0x1 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828148] missed_breadcrumb E 37 [4:1b] prio=0 @ 4500ms: gem_evict_every[1722]/0 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828150] missed_breadcrumb gem_evict_every [1725] waiting for 37 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828152] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828153] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828153] missed_breadcrumb HWSP: Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828156] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828157] missed_breadcrumb * Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828159] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828161] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828163] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828163] missed_breadcrumb * Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828165] missed_breadcrumb 000000c0 00000036 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828167] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828167] missed_breadcrumb * Dec 4 14:41:58 GLK-2-GLKRVP1DDR405 kernel: [ 520.828174] missed_breadcrumb Idle? no Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.847276] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.847387] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.847954] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.850130] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 244) banned? no Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.850162] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x37 Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.850282] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.850314] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.850743] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.850776] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.850777] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.850811] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.850842] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.851128] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.852445] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.852476] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.852477] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.852534] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.852535] i915 0000:00:02.0: GuC submission enabled Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.852536] i915 0000:00:02.0: HuC enabled Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.852655] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.852701] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.852789] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.852878] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:42:08 GLK-2-GLKRVP1DDR405 kernel: [ 530.852966] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844167] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844174] missed_breadcrumb current seqno 38, last 39, hangcheck 38 [2016 ms], inflight 1 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844177] missed_breadcrumb Reset count: 0 (global 27) Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844179] missed_breadcrumb Requests: Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844199] missed_breadcrumb first 39 [4:1c] prio=0 @ 3984ms: gem_evict_every[1722]/0 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844200] missed_breadcrumb last 39 [4:1c] prio=0 @ 3984ms: gem_evict_every[1722]/0 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844201] missed_breadcrumb active 39 [4:1c] prio=0 @ 3984ms: gem_evict_every[1722]/0 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844203] missed_breadcrumb [head 0d38, postfix 0d90, tail 0db0, batch 0x00000000_00000000] Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844210] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844212] missed_breadcrumb RING_HEAD: 0x00000d78 [0x00000d38] Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844214] missed_breadcrumb RING_TAIL: 0x00000db0 [0x00000db0] Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844217] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844220] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844225] missed_breadcrumb ACTHD: 0x0000c5c6_fd3d3a40 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844229] missed_breadcrumb BBADDR: 0x0000c5c6_fd3d51c1 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844234] missed_breadcrumb DMA_FADDR: 0x0000c5c6_fd3d6ac0 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844236] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844237] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844241] missed_breadcrumb Execlist status: 0x00044032 001feda8 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844243] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844245] missed_breadcrumb ELSP[0] count=1, rq: 39 [4:1c] prio=0 @ 3984ms: gem_evict_every[1722]/0 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844246] missed_breadcrumb ELSP[1] idle Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844246] missed_breadcrumb HW active? 0x1 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844247] missed_breadcrumb E 39 [4:1c] prio=0 @ 3984ms: gem_evict_every[1722]/0 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844249] missed_breadcrumb gem_evict_every [1725] waiting for 39 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844250] missed_breadcrumb kswapd0 [41] waiting for 39 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844252] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844252] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844253] missed_breadcrumb HWSP: Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844256] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844256] missed_breadcrumb * Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844258] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844260] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844261] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844262] missed_breadcrumb * Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844263] missed_breadcrumb 000000c0 00000038 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844265] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844265] missed_breadcrumb * Dec 4 14:42:12 GLK-2-GLKRVP1DDR405 kernel: [ 534.844271] missed_breadcrumb Idle? no Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.815317] [drm] GPU HANG: ecode 9:0:0xe7577ffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.815390] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.816371] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.818142] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 253) banned? no Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.818175] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x39 Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.818298] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.818329] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.818760] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.818794] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.818795] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.818830] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.818861] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.819150] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.820470] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.820501] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.820502] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.820560] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.820561] i915 0000:00:02.0: GuC submission enabled Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.820562] i915 0000:00:02.0: HuC enabled Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.820681] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.820726] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.820815] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.820904] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:42:24 GLK-2-GLKRVP1DDR405 kernel: [ 546.820992] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844163] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844166] missed_breadcrumb current seqno 3a, last 3b, hangcheck 3a [2016 ms], inflight 1 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844167] missed_breadcrumb Reset count: 0 (global 28) Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844167] missed_breadcrumb Requests: Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844170] missed_breadcrumb first 3b [4:1d] prio=0 @ 3996ms: gem_evict_every[1722]/0 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844171] missed_breadcrumb last 3b [4:1d] prio=0 @ 3996ms: gem_evict_every[1722]/0 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844172] missed_breadcrumb active 3b [4:1d] prio=0 @ 3996ms: gem_evict_every[1722]/0 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844174] missed_breadcrumb [head 0db0, postfix 0e08, tail 0e28, batch 0x00000000_00000000] Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844181] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844183] missed_breadcrumb RING_HEAD: 0x00000df0 [0x00000db0] Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844185] missed_breadcrumb RING_TAIL: 0x00000e28 [0x00000e28] Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844188] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844191] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844196] missed_breadcrumb ACTHD: 0x0000c5c6_fe533240 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844200] missed_breadcrumb BBADDR: 0x0000c5c6_fe534bc1 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844205] missed_breadcrumb DMA_FADDR: 0x0000c5c6_fe5363c0 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844207] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844209] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844212] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844215] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844216] missed_breadcrumb ELSP[0] count=1, rq: 3b [4:1d] prio=0 @ 3996ms: gem_evict_every[1722]/0 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844217] missed_breadcrumb ELSP[1] idle Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844217] missed_breadcrumb HW active? 0x1 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844219] missed_breadcrumb E 3b [4:1d] prio=0 @ 3996ms: gem_evict_every[1722]/0 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844220] missed_breadcrumb gem_evict_every [1725] waiting for 3b Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844220] missed_breadcrumb kswapd0 [41] waiting for 3b Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844222] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844223] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844224] missed_breadcrumb HWSP: Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844227] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844227] missed_breadcrumb * Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844229] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda8 00000018 001fede8 00000001 00000000 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844231] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844232] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844233] missed_breadcrumb * Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844234] missed_breadcrumb 000000c0 0000003a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844236] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844236] missed_breadcrumb * Dec 4 14:42:28 GLK-2-GLKRVP1DDR405 kernel: [ 550.844242] missed_breadcrumb Idle? no Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.847300] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.847371] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.847392] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.849014] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 262) banned? no Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.849046] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x3b Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.849167] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.849199] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.850073] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.850107] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.850108] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.850143] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.850173] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.850466] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.852991] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.853022] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.853023] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.853079] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.853080] i915 0000:00:02.0: GuC submission enabled Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.853081] i915 0000:00:02.0: HuC enabled Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.853199] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.853246] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.853334] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.853423] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:42:40 GLK-2-GLKRVP1DDR405 kernel: [ 562.853511] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812084] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812093] missed_breadcrumb current seqno 3c, last 3d, hangcheck 3c [1984 ms], inflight 1 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812094] missed_breadcrumb Reset count: 0 (global 29) Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812094] missed_breadcrumb Requests: Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812097] missed_breadcrumb first 3d [4:1e] prio=0 @ 3940ms: gem_evict_every[1722]/0 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812098] missed_breadcrumb last 3d [4:1e] prio=0 @ 3940ms: gem_evict_every[1722]/0 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812100] missed_breadcrumb active 3d [4:1e] prio=0 @ 3940ms: gem_evict_every[1722]/0 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812101] missed_breadcrumb [head 0e28, postfix 0e80, tail 0ea0, batch 0x00000000_00000000] Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812110] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812112] missed_breadcrumb RING_HEAD: 0x00000e68 [0x00000e28] Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812114] missed_breadcrumb RING_TAIL: 0x00000ea0 [0x00000ea0] Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812117] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812120] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812125] missed_breadcrumb ACTHD: 0x0000c5c7_07b05c40 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812129] missed_breadcrumb BBADDR: 0x0000c5c7_07b06f79 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812134] missed_breadcrumb DMA_FADDR: 0x0000c5c7_07b089c0 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812136] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812138] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812141] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812144] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812146] missed_breadcrumb ELSP[0] count=1, rq: 3d [4:1e] prio=0 @ 3940ms: gem_evict_every[1722]/0 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812146] missed_breadcrumb ELSP[1] idle Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812147] missed_breadcrumb HW active? 0x1 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812148] missed_breadcrumb E 3d [4:1e] prio=0 @ 3940ms: gem_evict_every[1722]/0 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812149] missed_breadcrumb gem_evict_every [1725] waiting for 3d Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812151] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812152] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812153] missed_breadcrumb HWSP: Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812155] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812156] missed_breadcrumb * Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812158] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812160] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812161] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812162] missed_breadcrumb * Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812164] missed_breadcrumb 000000c0 0000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812165] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812166] missed_breadcrumb * Dec 4 14:42:44 GLK-2-GLKRVP1DDR405 kernel: [ 566.812172] missed_breadcrumb Idle? no Dec 4 14:42:54 GLK-2-GLKRVP1DDR405 kernel: [ 576.835441] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:42:54 GLK-2-GLKRVP1DDR405 kernel: [ 576.835534] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.044127] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.044328] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 271) banned? no Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.044363] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x3d Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.044488] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.044523] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.237443] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.237481] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.237482] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.237521] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.237556] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.238006] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.240175] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.240210] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.240211] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.240302] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.240303] i915 0000:00:02.0: GuC submission enabled Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.240304] i915 0000:00:02.0: HuC enabled Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.240428] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.240477] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.240570] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.240663] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:42:57 GLK-2-GLKRVP1DDR405 kernel: [ 580.240755] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824080] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824084] missed_breadcrumb current seqno 3e, last 3f, hangcheck 3c [1584 ms], inflight 1 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824085] missed_breadcrumb Reset count: 0 (global 30) Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824086] missed_breadcrumb Requests: Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824089] missed_breadcrumb first 3f [4:1f] prio=0 @ 1580ms: gem_evict_every[1722]/0 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824090] missed_breadcrumb last 3f [4:1f] prio=0 @ 1580ms: gem_evict_every[1722]/0 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824091] missed_breadcrumb active 3f [4:1f] prio=0 @ 1580ms: gem_evict_every[1722]/0 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824093] missed_breadcrumb [head 0ea8, postfix 0f00, tail 0f20, batch 0x00000000_00040000] Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824101] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824104] missed_breadcrumb RING_HEAD: 0x00000ee8 [0x00000ea0] Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824106] missed_breadcrumb RING_TAIL: 0x00000f20 [0x00000f20] Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824109] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824112] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824117] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824122] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824126] missed_breadcrumb DMA_FADDR: 0x00000000_00040200 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824128] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824130] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824134] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824136] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824138] missed_breadcrumb ELSP[0] count=1, rq: 3f [4:1f] prio=0 @ 1580ms: gem_evict_every[1722]/0 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824139] missed_breadcrumb ELSP[1] idle Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824139] missed_breadcrumb HW active? 0x1 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824140] missed_breadcrumb E 3f [4:1f] prio=0 @ 1580ms: gem_evict_every[1722]/0 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824142] missed_breadcrumb gem_evict_every [1725] waiting for 3f Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824144] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824145] missed_breadcrumb IRQ? 0x0 (breadcrumbs? no) (execlists? no) Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824146] missed_breadcrumb HWSP: Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824148] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824149] missed_breadcrumb * Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824151] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824153] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824155] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824155] missed_breadcrumb * Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824157] missed_breadcrumb 000000c0 0000003e 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824159] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824159] missed_breadcrumb * Dec 4 14:42:59 GLK-2-GLKRVP1DDR405 kernel: [ 581.824166] missed_breadcrumb Idle? no Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828858] hangcheck rcs0 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828863] hangcheck current seqno 3e, last 3f, hangcheck 3e [5984 ms], inflight 1 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828865] hangcheck Reset count: 0 (global 30) Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828866] hangcheck Requests: Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828869] hangcheck first 3f [4:1f] prio=0 @ 8584ms: gem_evict_every[1722]/0 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828871] hangcheck last 3f [4:1f] prio=0 @ 8584ms: gem_evict_every[1722]/0 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828872] hangcheck active 3f [4:1f] prio=0 @ 8584ms: gem_evict_every[1722]/0 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828874] hangcheck [head 0ea8, postfix 0f00, tail 0f20, batch 0x00000000_00040000] Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828877] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828879] hangcheck RING_HEAD: 0x00000ee8 [0x00000ea0] Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828882] hangcheck RING_TAIL: 0x00000f20 [0x00000f20] Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828885] hangcheck RING_CTL: 0x00003001 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828889] hangcheck RING_MODE: 0x00000000 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828894] hangcheck ACTHD: 0x00000000_00040000 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828898] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828904] hangcheck DMA_FADDR: 0x00000000_00040200 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828906] hangcheck IPEIR: 0x00000000 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828908] hangcheck IPEHR: 0x18800001 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828911] hangcheck Execlist status: 0x00044032 001feda5 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828914] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828916] hangcheck ELSP[0] count=1, rq: 3f [4:1f] prio=0 @ 8584ms: gem_evict_every[1722]/0 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828917] hangcheck ELSP[1] idle Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828918] hangcheck HW active? 0x1 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828919] hangcheck E 3f [4:1f] prio=0 @ 8584ms: gem_evict_every[1722]/0 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828921] hangcheck gem_evict_every [1725] waiting for 3f Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828923] hangcheck RING_IMR: fffffefe Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828925] hangcheck IRQ? 0x0 (breadcrumbs? no) (execlists? no) Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828925] hangcheck HWSP: Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828929] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828930] hangcheck * Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828932] hangcheck 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828934] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828936] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828937] hangcheck * Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828939] hangcheck 000000c0 0000003e 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828941] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828941] hangcheck * Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.828948] hangcheck Idle? no Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.833006] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.833102] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.840037] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.840671] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 280) banned? no Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.840708] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x3f Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.840835] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.840873] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.844401] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.844440] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.844441] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.844482] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.844518] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.844888] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.847491] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.847528] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.847529] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.847665] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.847666] i915 0000:00:02.0: GuC submission enabled Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.847667] i915 0000:00:02.0: HuC enabled Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.847797] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.847848] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.847944] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.848039] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:43:06 GLK-2-GLKRVP1DDR405 kernel: [ 588.848142] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828095] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828099] missed_breadcrumb current seqno 40, last 41, hangcheck 40 [1984 ms], inflight 1 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828100] missed_breadcrumb Reset count: 0 (global 31) Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828101] missed_breadcrumb Requests: Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828104] missed_breadcrumb first 41 [4:20] prio=0 @ 3972ms: gem_evict_every[1722]/0 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828105] missed_breadcrumb last 41 [4:20] prio=0 @ 3972ms: gem_evict_every[1722]/0 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828107] missed_breadcrumb active 41 [4:20] prio=0 @ 3972ms: gem_evict_every[1722]/0 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828109] missed_breadcrumb [head 0f28, postfix 0f80, tail 0fa0, batch 0x00000000_00000000] Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828117] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828119] missed_breadcrumb RING_HEAD: 0x00000f68 [0x00000f20] Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828122] missed_breadcrumb RING_TAIL: 0x00000fa0 [0x00000fa0] Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828125] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828128] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828133] missed_breadcrumb ACTHD: 0x0000c5c6_e7b17bc0 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828138] missed_breadcrumb BBADDR: 0x0000c5c6_e7b18dd9 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828143] missed_breadcrumb DMA_FADDR: 0x0000c5c6_e7b1a440 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828145] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828147] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828151] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828153] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828155] missed_breadcrumb ELSP[0] count=1, rq: 41 [4:20] prio=0 @ 3972ms: gem_evict_every[1722]/0 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828156] missed_breadcrumb ELSP[1] idle Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828157] missed_breadcrumb HW active? 0x1 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828158] missed_breadcrumb E 41 [4:20] prio=0 @ 3972ms: gem_evict_every[1722]/0 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828160] missed_breadcrumb gem_evict_every [1725] waiting for 41 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828162] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828163] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828164] missed_breadcrumb HWSP: Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828167] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828168] missed_breadcrumb * Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828170] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828172] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828174] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828174] missed_breadcrumb * Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828176] missed_breadcrumb 000000c0 00000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828178] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828179] missed_breadcrumb * Dec 4 14:43:10 GLK-2-GLKRVP1DDR405 kernel: [ 592.828186] missed_breadcrumb Idle? no Dec 4 14:43:20 GLK-2-GLKRVP1DDR405 kernel: [ 602.851586] [drm] GPU HANG: ecode 9:0:0xe7577ffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:43:20 GLK-2-GLKRVP1DDR405 kernel: [ 602.851682] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.812038] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.812432] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 289) banned? no Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.812466] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x41 Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.812583] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.812617] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.818592] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.818627] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.818628] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.818665] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.818697] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.819625] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.822227] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.822262] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.822263] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.822383] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.822384] i915 0000:00:02.0: GuC submission enabled Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.822385] i915 0000:00:02.0: HuC enabled Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.822510] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.822559] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.822651] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.822744] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:43:23 GLK-2-GLKRVP1DDR405 kernel: [ 605.822836] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820083] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820087] missed_breadcrumb current seqno 42, last 43, hangcheck 42 [992 ms], inflight 1 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820088] missed_breadcrumb Reset count: 0 (global 32) Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820089] missed_breadcrumb Requests: Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820091] missed_breadcrumb first 43 [4:21] prio=0 @ 3988ms: gem_evict_every[1722]/0 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820093] missed_breadcrumb last 43 [4:21] prio=0 @ 3988ms: gem_evict_every[1722]/0 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820094] missed_breadcrumb active 43 [4:21] prio=0 @ 3988ms: gem_evict_every[1722]/0 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820096] missed_breadcrumb [head 0fa8, postfix 1000, tail 1020, batch 0x00000000_00040000] Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820104] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820106] missed_breadcrumb RING_HEAD: 0x00000fe8 [0x00000fa0] Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820108] missed_breadcrumb RING_TAIL: 0x00001020 [0x00001020] Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820111] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820114] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820119] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820123] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820128] missed_breadcrumb DMA_FADDR: 0x00000000_00040200 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820130] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820132] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820135] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820138] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820139] missed_breadcrumb ELSP[0] count=1, rq: 43 [4:21] prio=0 @ 3988ms: gem_evict_every[1722]/0 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820140] missed_breadcrumb ELSP[1] idle Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820141] missed_breadcrumb HW active? 0x1 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820142] missed_breadcrumb E 43 [4:21] prio=0 @ 3988ms: gem_evict_every[1722]/0 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820143] missed_breadcrumb gem_evict_every [1725] waiting for 43 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820145] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820146] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820147] missed_breadcrumb HWSP: Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820150] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820150] missed_breadcrumb * Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820152] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820154] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820156] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820156] missed_breadcrumb * Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820158] missed_breadcrumb 000000c0 00000042 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820159] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820160] missed_breadcrumb * Dec 4 14:43:27 GLK-2-GLKRVP1DDR405 kernel: [ 609.820166] missed_breadcrumb Idle? no Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858840] hangcheck rcs0 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858845] hangcheck current seqno 42, last 43, hangcheck 42 [6028 ms], inflight 1 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858847] hangcheck Reset count: 0 (global 32) Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858848] hangcheck Requests: Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858851] hangcheck first 43 [4:21] prio=0 @ 9024ms: gem_evict_every[1722]/0 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858852] hangcheck last 43 [4:21] prio=0 @ 9024ms: gem_evict_every[1722]/0 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858854] hangcheck active 43 [4:21] prio=0 @ 9024ms: gem_evict_every[1722]/0 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858856] hangcheck [head 0fa8, postfix 1000, tail 1020, batch 0x00000000_00040000] Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858859] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858861] hangcheck RING_HEAD: 0x00000fe8 [0x00000fa0] Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858863] hangcheck RING_TAIL: 0x00001020 [0x00001020] Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858866] hangcheck RING_CTL: 0x00003001 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858870] hangcheck RING_MODE: 0x00000000 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858874] hangcheck ACTHD: 0x00000000_00040000 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858879] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858884] hangcheck DMA_FADDR: 0x00000000_00040200 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858886] hangcheck IPEIR: 0x00000000 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858888] hangcheck IPEHR: 0x18800001 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858892] hangcheck Execlist status: 0x00044032 001feda5 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858894] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858896] hangcheck ELSP[0] count=1, rq: 43 [4:21] prio=0 @ 9024ms: gem_evict_every[1722]/0 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858897] hangcheck ELSP[1] idle Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858898] hangcheck HW active? 0x1 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858899] hangcheck E 43 [4:21] prio=0 @ 9024ms: gem_evict_every[1722]/0 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858900] hangcheck gem_evict_every [1725] waiting for 43 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858903] hangcheck RING_IMR: fffffefe Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858904] hangcheck IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858904] hangcheck HWSP: Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858907] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858908] hangcheck * Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858911] hangcheck 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858913] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858915] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858915] hangcheck * Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858917] hangcheck 000000c0 00000042 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858919] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858920] hangcheck * Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.858927] hangcheck Idle? no Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.863479] [drm] GPU HANG: ecode 9:0:0xe75ffffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.863577] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.868515] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.869613] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 298) banned? no Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.869651] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x43 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.876136] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.876174] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.876661] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.876698] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.876700] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.876739] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.876775] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.877285] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.880095] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.880132] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.880133] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.880553] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.880555] i915 0000:00:02.0: GuC submission enabled Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.880556] i915 0000:00:02.0: HuC enabled Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.880685] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.880736] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.880831] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.880926] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:43:32 GLK-2-GLKRVP1DDR405 kernel: [ 614.881021] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844091] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844096] missed_breadcrumb current seqno 44, last 45, hangcheck 44 [2016 ms], inflight 1 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844097] missed_breadcrumb Reset count: 0 (global 33) Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844098] missed_breadcrumb Requests: Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844101] missed_breadcrumb first 45 [4:22] prio=0 @ 3960ms: gem_evict_every[1722]/0 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844102] missed_breadcrumb last 45 [4:22] prio=0 @ 3960ms: gem_evict_every[1722]/0 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844104] missed_breadcrumb active 45 [4:22] prio=0 @ 3960ms: gem_evict_every[1722]/0 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844105] missed_breadcrumb [head 1028, postfix 1080, tail 10a0, batch 0x00000000_00000000] Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844114] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844116] missed_breadcrumb RING_HEAD: 0x00001068 [0x00001020] Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844118] missed_breadcrumb RING_TAIL: 0x000010a0 [0x000010a0] Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844122] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844125] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844130] missed_breadcrumb ACTHD: 0x0000c5c6_e726e6ac Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844135] missed_breadcrumb BBADDR: 0x0000c5c6_e726fb85 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844140] missed_breadcrumb DMA_FADDR: 0x0000c5c6_e72713c0 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844142] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844144] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844148] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844151] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844153] missed_breadcrumb ELSP[0] count=1, rq: 45 [4:22] prio=0 @ 3960ms: gem_evict_every[1722]/0 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844153] missed_breadcrumb ELSP[1] idle Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844154] missed_breadcrumb HW active? 0x1 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844156] missed_breadcrumb E 45 [4:22] prio=0 @ 3960ms: gem_evict_every[1722]/0 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844157] missed_breadcrumb gem_evict_every [1725] waiting for 45 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844159] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844160] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844161] missed_breadcrumb HWSP: Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844164] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844165] missed_breadcrumb * Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844167] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844169] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844171] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844172] missed_breadcrumb * Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844174] missed_breadcrumb 000000c0 00000044 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844175] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844176] missed_breadcrumb * Dec 4 14:43:36 GLK-2-GLKRVP1DDR405 kernel: [ 618.844183] missed_breadcrumb Idle? no Dec 4 14:43:48 GLK-2-GLKRVP1DDR405 kernel: [ 630.847870] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:43:48 GLK-2-GLKRVP1DDR405 kernel: [ 630.847966] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.876063] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.876566] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 307) banned? no Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.876602] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x45 Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.876722] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.876757] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.882257] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.882293] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.882294] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.882332] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.882365] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.883455] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.886047] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.886082] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.886083] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.886197] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.886199] i915 0000:00:02.0: GuC submission enabled Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.886200] i915 0000:00:02.0: HuC enabled Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.886326] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.886375] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.886467] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.886560] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:43:50 GLK-2-GLKRVP1DDR405 kernel: [ 632.886652] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828129] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828135] missed_breadcrumb current seqno 46, last 47, hangcheck 44 [3944 ms], inflight 1 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828137] missed_breadcrumb Reset count: 0 (global 34) Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828138] missed_breadcrumb Requests: Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828142] missed_breadcrumb first 47 [4:23] prio=0 @ 3928ms: gem_evict_every[1722]/0 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828144] missed_breadcrumb last 47 [4:23] prio=0 @ 3928ms: gem_evict_every[1722]/0 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828147] missed_breadcrumb active 47 [4:23] prio=0 @ 3928ms: gem_evict_every[1722]/0 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828150] missed_breadcrumb [head 10a8, postfix 1100, tail 1120, batch 0x00000000_00040000] Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828159] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828162] missed_breadcrumb RING_HEAD: 0x000010e8 [0x000010a0] Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828164] missed_breadcrumb RING_TAIL: 0x00001120 [0x00001120] Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828168] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828172] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828178] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828183] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828188] missed_breadcrumb DMA_FADDR: 0x00000000_00040200 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828191] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828193] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828198] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828201] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828204] missed_breadcrumb ELSP[0] count=1, rq: 47 [4:23] prio=0 @ 3928ms: gem_evict_every[1722]/0 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828206] missed_breadcrumb ELSP[1] idle Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828207] missed_breadcrumb HW active? 0x1 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828209] missed_breadcrumb E 47 [4:23] prio=0 @ 3928ms: gem_evict_every[1722]/0 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828211] missed_breadcrumb gem_evict_every [1725] waiting for 47 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828214] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828215] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828217] missed_breadcrumb HWSP: Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828221] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828223] missed_breadcrumb * Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828226] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828229] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828232] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828233] missed_breadcrumb * Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828236] missed_breadcrumb 000000c0 00000046 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828239] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828240] missed_breadcrumb * Dec 4 14:43:54 GLK-2-GLKRVP1DDR405 kernel: [ 636.828252] missed_breadcrumb Idle? no Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832077] hangcheck rcs0 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832083] hangcheck current seqno 46, last 47, hangcheck 46 [8004 ms], inflight 1 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832085] hangcheck Reset count: 0 (global 34) Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832085] hangcheck Requests: Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832088] hangcheck first 47 [4:23] prio=0 @ 11932ms: gem_evict_every[1722]/0 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832090] hangcheck last 47 [4:23] prio=0 @ 11932ms: gem_evict_every[1722]/0 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832091] hangcheck active 47 [4:23] prio=0 @ 11932ms: gem_evict_every[1722]/0 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832093] hangcheck [head 10a8, postfix 1100, tail 1120, batch 0x00000000_00040000] Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832096] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832099] hangcheck RING_HEAD: 0x000010e8 [0x000010a0] Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832101] hangcheck RING_TAIL: 0x00001120 [0x00001120] Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832104] hangcheck RING_CTL: 0x00003001 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832108] hangcheck RING_MODE: 0x00000000 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832112] hangcheck ACTHD: 0x00000000_00040000 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832117] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832122] hangcheck DMA_FADDR: 0x00000000_00040200 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832124] hangcheck IPEIR: 0x00000000 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832126] hangcheck IPEHR: 0x18800001 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832129] hangcheck Execlist status: 0x00044032 001feda5 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832132] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832134] hangcheck ELSP[0] count=1, rq: 47 [4:23] prio=0 @ 11932ms: gem_evict_every[1722]/0 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832135] hangcheck ELSP[1] idle Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832136] hangcheck HW active? 0x1 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832137] hangcheck E 47 [4:23] prio=0 @ 11932ms: gem_evict_every[1722]/0 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832138] hangcheck gem_evict_every [1725] waiting for 47 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832140] hangcheck RING_IMR: fffffefe Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832142] hangcheck IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832142] hangcheck HWSP: Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832145] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832146] hangcheck * Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832149] hangcheck 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832151] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832152] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832153] hangcheck * Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832155] hangcheck 000000c0 00000046 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832157] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832157] hangcheck * Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.832164] hangcheck Idle? no Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.835832] [drm] GPU HANG: ecode 9:0:0xe7577ffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:44:02 GLK-2-GLKRVP1DDR405 kernel: [ 644.835928] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.364126] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.365090] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 316) banned? no Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.365125] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x47 Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.365246] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.365282] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.368166] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.368202] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.368203] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.368241] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.368275] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.372188] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.372224] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.372257] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.372259] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.372574] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.372575] i915 0000:00:02.0: GuC submission enabled Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.372576] i915 0000:00:02.0: HuC enabled Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.372701] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.372750] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.372843] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.372936] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:44:03 GLK-2-GLKRVP1DDR405 kernel: [ 646.373028] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844110] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844114] missed_breadcrumb current seqno 48, last 49, hangcheck 48 [4032 ms], inflight 1 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844116] missed_breadcrumb Reset count: 0 (global 35) Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844116] missed_breadcrumb Requests: Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844119] missed_breadcrumb first 49 [4:24] prio=0 @ 4464ms: gem_evict_every[1722]/0 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844121] missed_breadcrumb last 49 [4:24] prio=0 @ 4464ms: gem_evict_every[1722]/0 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844122] missed_breadcrumb active 49 [4:24] prio=0 @ 4464ms: gem_evict_every[1722]/0 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844124] missed_breadcrumb [head 1128, postfix 1180, tail 11a0, batch 0x00000000_00000000] Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844133] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844135] missed_breadcrumb RING_HEAD: 0x00001168 [0x00001120] Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844137] missed_breadcrumb RING_TAIL: 0x000011a0 [0x000011a0] Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844141] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844144] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844149] missed_breadcrumb ACTHD: 0x0000c5c7_0d989e40 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844154] missed_breadcrumb BBADDR: 0x0000c5c7_0d98b3b1 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844159] missed_breadcrumb DMA_FADDR: 0x0000c5c7_0d98cdc0 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844161] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844163] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844167] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844170] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844172] missed_breadcrumb ELSP[0] count=1, rq: 49 [4:24] prio=0 @ 4464ms: gem_evict_every[1722]/0 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844172] missed_breadcrumb ELSP[1] idle Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844173] missed_breadcrumb HW active? 0x1 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844175] missed_breadcrumb E 49 [4:24] prio=0 @ 4464ms: gem_evict_every[1722]/0 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844176] missed_breadcrumb gem_evict_every [1725] waiting for 49 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844178] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844179] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844180] missed_breadcrumb HWSP: Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844183] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844184] missed_breadcrumb * Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844186] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844188] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844190] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844191] missed_breadcrumb * Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844193] missed_breadcrumb 000000c0 00000048 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844195] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844195] missed_breadcrumb * Dec 4 14:44:08 GLK-2-GLKRVP1DDR405 kernel: [ 650.844203] missed_breadcrumb Idle? no Dec 4 14:44:18 GLK-2-GLKRVP1DDR405 kernel: [ 660.831808] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:44:18 GLK-2-GLKRVP1DDR405 kernel: [ 660.831909] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.732045] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.732285] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 325) banned? no Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.732321] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x49 Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.732446] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.732484] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.738077] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.738113] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.738114] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.738151] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.738183] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.739131] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.741730] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.741764] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.741765] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.741876] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.741877] i915 0000:00:02.0: GuC submission enabled Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.741878] i915 0000:00:02.0: HuC enabled Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.742002] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.742050] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.742142] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.742234] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:44:22 GLK-2-GLKRVP1DDR405 kernel: [ 664.742326] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828094] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828098] missed_breadcrumb current seqno 4a, last 4b, hangcheck 4a [1984 ms], inflight 1 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828099] missed_breadcrumb Reset count: 0 (global 36) Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828100] missed_breadcrumb Requests: Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828102] missed_breadcrumb first 4b [4:25] prio=0 @ 3976ms: gem_evict_every[1722]/0 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828103] missed_breadcrumb last 4b [4:25] prio=0 @ 3976ms: gem_evict_every[1722]/0 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828105] missed_breadcrumb active 4b [4:25] prio=0 @ 3976ms: gem_evict_every[1722]/0 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828106] missed_breadcrumb [head 11a8, postfix 1200, tail 1220, batch 0x00000000_00040000] Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828115] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828117] missed_breadcrumb RING_HEAD: 0x000011e8 [0x000011a0] Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828119] missed_breadcrumb RING_TAIL: 0x00001220 [0x00001220] Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828122] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828125] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828130] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828135] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828139] missed_breadcrumb DMA_FADDR: 0x00000000_00040200 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828141] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828143] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828146] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828149] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828151] missed_breadcrumb ELSP[0] count=1, rq: 4b [4:25] prio=0 @ 3976ms: gem_evict_every[1722]/0 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828152] missed_breadcrumb ELSP[1] idle Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828152] missed_breadcrumb HW active? 0x1 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828153] missed_breadcrumb E 4b [4:25] prio=0 @ 3976ms: gem_evict_every[1722]/0 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828154] missed_breadcrumb gem_evict_every [1725] waiting for 4b Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828156] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828158] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828158] missed_breadcrumb HWSP: Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828161] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828162] missed_breadcrumb * Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828164] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828166] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828167] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828168] missed_breadcrumb * Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828169] missed_breadcrumb 000000c0 0000004a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828171] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828172] missed_breadcrumb * Dec 4 14:44:26 GLK-2-GLKRVP1DDR405 kernel: [ 668.828178] missed_breadcrumb Idle? no Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844071] hangcheck rcs0 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844076] hangcheck current seqno 4a, last 4b, hangcheck 4a [8000 ms], inflight 1 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844078] hangcheck Reset count: 0 (global 36) Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844079] hangcheck Requests: Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844081] hangcheck first 4b [4:25] prio=0 @ 9992ms: gem_evict_every[1722]/0 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844083] hangcheck last 4b [4:25] prio=0 @ 9992ms: gem_evict_every[1722]/0 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844084] hangcheck active 4b [4:25] prio=0 @ 9992ms: gem_evict_every[1722]/0 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844086] hangcheck [head 11a8, postfix 1200, tail 1220, batch 0x00000000_00040000] Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844089] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844091] hangcheck RING_HEAD: 0x000011e8 [0x000011a0] Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844093] hangcheck RING_TAIL: 0x00001220 [0x00001220] Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844097] hangcheck RING_CTL: 0x00003001 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844100] hangcheck RING_MODE: 0x00000000 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844104] hangcheck ACTHD: 0x00000000_00040000 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844109] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844114] hangcheck DMA_FADDR: 0x00000000_00040080 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844115] hangcheck IPEIR: 0x00000000 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844117] hangcheck IPEHR: 0x18800001 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844121] hangcheck Execlist status: 0x00044032 001feda5 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844124] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844125] hangcheck ELSP[0] count=1, rq: 4b [4:25] prio=0 @ 9992ms: gem_evict_every[1722]/0 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844126] hangcheck ELSP[1] idle Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844127] hangcheck HW active? 0x1 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844128] hangcheck E 4b [4:25] prio=0 @ 9992ms: gem_evict_every[1722]/0 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844129] hangcheck gem_evict_every [1725] waiting for 4b Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844131] hangcheck RING_IMR: fffffefe Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844132] hangcheck IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844133] hangcheck HWSP: Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844136] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844137] hangcheck * Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844139] hangcheck 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844140] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844142] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844146] hangcheck * Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844148] hangcheck 000000c0 0000004a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844150] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844150] hangcheck * Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.844157] hangcheck Idle? no Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.847638] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:44:32 GLK-2-GLKRVP1DDR405 kernel: [ 674.847730] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.088090] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.089119] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 334) banned? no Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.089154] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x4b Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.089275] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.089311] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.096063] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.096099] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.096100] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.096139] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.096173] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.096641] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.098596] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.098630] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.098632] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.098861] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.098862] i915 0000:00:02.0: GuC submission enabled Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.098863] i915 0000:00:02.0: HuC enabled Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.098989] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.099037] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.099130] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.099223] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:44:34 GLK-2-GLKRVP1DDR405 kernel: [ 677.099315] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828086] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828095] missed_breadcrumb current seqno 4c, last 4d, hangcheck 4a [3732 ms], inflight 1 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828096] missed_breadcrumb Reset count: 0 (global 37) Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828096] missed_breadcrumb Requests: Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828099] missed_breadcrumb first 4d [4:26] prio=0 @ 3724ms: gem_evict_every[1722]/0 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828100] missed_breadcrumb last 4d [4:26] prio=0 @ 3724ms: gem_evict_every[1722]/0 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828102] missed_breadcrumb active 4d [4:26] prio=0 @ 3724ms: gem_evict_every[1722]/0 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828103] missed_breadcrumb [head 1228, postfix 1280, tail 12a0, batch 0x00000000_00000000] Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828112] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828114] missed_breadcrumb RING_HEAD: 0x00001268 [0x00001220] Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828116] missed_breadcrumb RING_TAIL: 0x000012a0 [0x000012a0] Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828120] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828123] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828128] missed_breadcrumb ACTHD: 0x0000c5c6_d1781c40 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828133] missed_breadcrumb BBADDR: 0x0000c5c6_d1783155 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828137] missed_breadcrumb DMA_FADDR: 0x0000c5c6_d1784a40 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828139] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828141] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828145] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828148] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828149] missed_breadcrumb ELSP[0] count=1, rq: 4d [4:26] prio=0 @ 3724ms: gem_evict_every[1722]/0 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828150] missed_breadcrumb ELSP[1] idle Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828151] missed_breadcrumb HW active? 0x1 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828152] missed_breadcrumb E 4d [4:26] prio=0 @ 3724ms: gem_evict_every[1722]/0 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828153] missed_breadcrumb gem_evict_every [1725] waiting for 4d Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828155] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828156] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828157] missed_breadcrumb HWSP: Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828160] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828160] missed_breadcrumb * Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828163] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828164] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828166] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828167] missed_breadcrumb * Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828168] missed_breadcrumb 000000c0 0000004c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828170] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828171] missed_breadcrumb * Dec 4 14:44:38 GLK-2-GLKRVP1DDR405 kernel: [ 680.828177] missed_breadcrumb Idle? no Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.815502] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.815596] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.924111] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.924727] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 343) banned? no Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.924764] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x4d Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.924888] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.924926] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.988497] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.988535] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.988536] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.988575] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.988609] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.989851] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.992076] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.992112] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.992116] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.992209] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.992210] i915 0000:00:02.0: GuC submission enabled Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.992211] i915 0000:00:02.0: HuC enabled Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.992336] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.992387] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.992481] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.992575] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:44:52 GLK-2-GLKRVP1DDR405 kernel: [ 694.992668] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828088] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828092] missed_breadcrumb current seqno 4e, last 4f, hangcheck 0 [396832 ms], inflight 1 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828094] missed_breadcrumb Reset count: 0 (global 38) Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828094] missed_breadcrumb Requests: Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828097] missed_breadcrumb first 4f [4:27] prio=0 @ 1836ms: gem_evict_every[1722]/0 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828099] missed_breadcrumb last 4f [4:27] prio=0 @ 1836ms: gem_evict_every[1722]/0 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828100] missed_breadcrumb active 4f [4:27] prio=0 @ 1836ms: gem_evict_every[1722]/0 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828102] missed_breadcrumb [head 12a8, postfix 1300, tail 1320, batch 0x00000000_00040000] Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828112] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828114] missed_breadcrumb RING_HEAD: 0x000012e8 [0x000012a0] Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828116] missed_breadcrumb RING_TAIL: 0x00001320 [0x00001320] Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828119] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828123] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828127] missed_breadcrumb ACTHD: 0x00000000_00040000 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828132] missed_breadcrumb BBADDR: 0x00000000_00040001 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828137] missed_breadcrumb DMA_FADDR: 0x00000000_00040200 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828139] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828141] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828144] missed_breadcrumb Execlist status: 0x00024029 001feda5 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828147] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828148] missed_breadcrumb ELSP[0] count=1, rq: 4f [4:27] prio=0 @ 1836ms: gem_evict_every[1722]/0 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828149] missed_breadcrumb ELSP[1] idle Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828150] missed_breadcrumb HW active? 0x1 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828151] missed_breadcrumb E 4f [4:27] prio=0 @ 1836ms: gem_evict_every[1722]/0 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828152] missed_breadcrumb gem_evict_every [1725] waiting for 4f Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828154] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828155] missed_breadcrumb IRQ? 0x0 (breadcrumbs? no) (execlists? no) Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828156] missed_breadcrumb HWSP: Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828159] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828160] missed_breadcrumb * Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828162] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828163] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828165] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828166] missed_breadcrumb * Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828167] missed_breadcrumb 000000c0 0000004e 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828169] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828170] missed_breadcrumb * Dec 4 14:44:54 GLK-2-GLKRVP1DDR405 kernel: [ 696.828176] missed_breadcrumb Idle? no Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828096] hangcheck rcs0 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828101] hangcheck current seqno 4e, last 4f, hangcheck 4e [8000 ms], inflight 1 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828103] hangcheck Reset count: 0 (global 38) Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828103] hangcheck Requests: Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828106] hangcheck first 4f [4:27] prio=0 @ 9836ms: gem_evict_every[1722]/0 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828108] hangcheck last 4f [4:27] prio=0 @ 9836ms: gem_evict_every[1722]/0 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828109] hangcheck active 4f [4:27] prio=0 @ 9836ms: gem_evict_every[1722]/0 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828111] hangcheck [head 12a8, postfix 1300, tail 1320, batch 0x00000000_00040000] Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828114] hangcheck RING_START: 0x000f2000 [0x000f2000] Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828116] hangcheck RING_HEAD: 0x000012e8 [0x000012a0] Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828118] hangcheck RING_TAIL: 0x00001320 [0x00001320] Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828122] hangcheck RING_CTL: 0x00003001 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828125] hangcheck RING_MODE: 0x00000000 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828130] hangcheck ACTHD: 0x00000000_00040000 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828134] hangcheck BBADDR: 0x00000000_00040001 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828139] hangcheck DMA_FADDR: 0x00000000_00040200 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828141] hangcheck IPEIR: 0x00000000 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828143] hangcheck IPEHR: 0x18800001 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828146] hangcheck Execlist status: 0x00024029 001feda5 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828149] hangcheck Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828151] hangcheck ELSP[0] count=1, rq: 4f [4:27] prio=0 @ 9836ms: gem_evict_every[1722]/0 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828151] hangcheck ELSP[1] idle Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828152] hangcheck HW active? 0x1 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828153] hangcheck E 4f [4:27] prio=0 @ 9836ms: gem_evict_every[1722]/0 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828155] hangcheck gem_evict_every [1725] waiting for 4f Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828157] hangcheck RING_IMR: fffffefe Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828158] hangcheck IRQ? 0x0 (breadcrumbs? no) (execlists? no) Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828158] hangcheck HWSP: Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828162] hangcheck 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828162] hangcheck * Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828165] hangcheck 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828166] hangcheck 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828168] hangcheck 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828169] hangcheck * Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828171] hangcheck 000000c0 0000004e 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828172] hangcheck 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828173] hangcheck * Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.828180] hangcheck Idle? no Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.832581] [drm] GPU HANG: ecode 9:0:0xe7577ffe, in gem_evict_every [1722], reason: Hang on rcs0, action: reset Dec 4 14:45:02 GLK-2-GLKRVP1DDR405 kernel: [ 704.832677] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.776087] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.776893] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 352) banned? no Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.776928] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x4f Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.777049] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.777085] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.780178] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.780213] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.780214] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.780250] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.780283] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.780739] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.783437] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.783472] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.783473] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.783562] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.783563] i915 0000:00:02.0: GuC submission enabled Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.783564] i915 0000:00:02.0: HuC enabled Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.783711] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.783758] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.783849] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.783939] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:45:03 GLK-2-GLKRVP1DDR405 kernel: [ 705.784030] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820088] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820093] missed_breadcrumb current seqno 50, last 51, hangcheck 50 [2976 ms], inflight 1 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820094] missed_breadcrumb Reset count: 0 (global 39) Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820095] missed_breadcrumb Requests: Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820097] missed_breadcrumb first 51 [4:28] prio=0 @ 4012ms: gem_evict_every[1722]/0 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820099] missed_breadcrumb last 51 [4:28] prio=0 @ 4012ms: gem_evict_every[1722]/0 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820100] missed_breadcrumb active 51 [4:28] prio=0 @ 4012ms: gem_evict_every[1722]/0 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820102] missed_breadcrumb [head 1328, postfix 1380, tail 13a0, batch 0x00000000_00000000] Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820110] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820113] missed_breadcrumb RING_HEAD: 0x00001368 [0x00001320] Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820115] missed_breadcrumb RING_TAIL: 0x000013a0 [0x000013a0] Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820118] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820121] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820126] missed_breadcrumb ACTHD: 0x0000c5c6_d6fcb358 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820131] missed_breadcrumb BBADDR: 0x0000c5c6_d6fccb19 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820136] missed_breadcrumb DMA_FADDR: 0x0000c5c6_d6fce3c0 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820138] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820140] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820143] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820146] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820148] missed_breadcrumb ELSP[0] count=1, rq: 51 [4:28] prio=0 @ 4012ms: gem_evict_every[1722]/0 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820149] missed_breadcrumb ELSP[1] idle Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820149] missed_breadcrumb HW active? 0x1 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820151] missed_breadcrumb E 51 [4:28] prio=0 @ 4012ms: gem_evict_every[1722]/0 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820152] missed_breadcrumb gem_evict_every [1725] waiting for 51 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820154] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820155] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820155] missed_breadcrumb HWSP: Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820158] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820159] missed_breadcrumb * Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820161] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820163] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820165] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820165] missed_breadcrumb * Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820167] missed_breadcrumb 000000c0 00000050 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820169] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820169] missed_breadcrumb * Dec 4 14:45:07 GLK-2-GLKRVP1DDR405 kernel: [ 709.820176] missed_breadcrumb Idle? no Dec 4 14:45:18 GLK-2-GLKRVP1DDR405 kernel: [ 720.835431] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_evict_every [1722], reason: No progress on rcs0, action: reset Dec 4 14:45:18 GLK-2-GLKRVP1DDR405 kernel: [ 720.835523] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.587374] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.587691] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 361) banned? no Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.587729] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x51 Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.600149] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.600187] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.602992] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.603030] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.603031] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.603070] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.603106] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.604231] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.606947] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.606983] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.606984] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.607120] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.607122] i915 0000:00:02.0: GuC submission enabled Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.607123] i915 0000:00:02.0: HuC enabled Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.607252] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.607304] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.607399] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.607494] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:45:21 GLK-2-GLKRVP1DDR405 kernel: [ 723.607589] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804128] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915] Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804132] missed_breadcrumb current seqno 52, last 53, hangcheck 52 [1824 ms], inflight 1 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804133] missed_breadcrumb Reset count: 0 (global 40) Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804134] missed_breadcrumb Requests: Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804136] missed_breadcrumb first 53 [4:29] prio=0 @ 4000ms: gem_evict_every[1722]/0 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804138] missed_breadcrumb last 53 [4:29] prio=0 @ 4000ms: gem_evict_every[1722]/0 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804139] missed_breadcrumb active 53 [4:29] prio=0 @ 4000ms: gem_evict_every[1722]/0 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804141] missed_breadcrumb [head 13a0, postfix 13f8, tail 1418, batch 0x00000000_00000000] Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804149] missed_breadcrumb RING_START: 0x000f2000 [0x000f2000] Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804152] missed_breadcrumb RING_HEAD: 0x000013e0 [0x000013a0] Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804154] missed_breadcrumb RING_TAIL: 0x00001418 [0x00001418] Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804157] missed_breadcrumb RING_CTL: 0x00003001 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804160] missed_breadcrumb RING_MODE: 0x00000000 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804165] missed_breadcrumb ACTHD: 0x0000c5c6_f0e19240 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804169] missed_breadcrumb BBADDR: 0x0000c5c6_f0e1a9c1 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804174] missed_breadcrumb DMA_FADDR: 0x0000c5c6_f0e1c140 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804176] missed_breadcrumb IPEIR: 0x00000000 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804178] missed_breadcrumb IPEHR: 0x18800001 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804182] missed_breadcrumb Execlist status: 0x00044032 001feda5 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804184] missed_breadcrumb Execlist CSB read 3 [-1 cached], write 3 [3 from hws], interrupt posted? no Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804186] missed_breadcrumb ELSP[0] count=1, rq: 53 [4:29] prio=0 @ 4000ms: gem_evict_every[1722]/0 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804187] missed_breadcrumb ELSP[1] idle Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804188] missed_breadcrumb HW active? 0x1 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804189] missed_breadcrumb E 53 [4:29] prio=0 @ 4000ms: gem_evict_every[1722]/0 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804190] missed_breadcrumb gem_evict_every [1722] waiting for 53 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804192] missed_breadcrumb RING_IMR: fffffefe Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804193] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no) Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804194] missed_breadcrumb HWSP: Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804197] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804198] missed_breadcrumb * Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804200] missed_breadcrumb 00000040 00000001 00000000 00000014 001feda5 00000018 001fede8 00000001 00000000 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804201] missed_breadcrumb 00000060 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000003 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804203] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804204] missed_breadcrumb * Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804205] missed_breadcrumb 000000c0 00000052 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804207] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804208] missed_breadcrumb * Dec 4 14:45:25 GLK-2-GLKRVP1DDR405 kernel: [ 727.804214] missed_breadcrumb Idle? no Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.811778] [drm] GPU HANG: ecode 9:0:0xe757fffe, reason: No progress on rcs0, action: reset Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.811965] [drm:i915_reset_device [i915]] resetting chip Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.812519] i915 0000:00:02.0: Resetting chip after gpu hang Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.813778] [drm:i915_gem_reset_engine [i915]] context gem_evict_every[1722]/0 marked guilty (score 370) banned? no Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.813809] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x53 Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.813931] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/glk_huc_ver02_00_1748.bin Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.813962] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.814288] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0 Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.814321] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.814322] [drm] HuC: Loaded firmware i915/glk_huc_ver02_00_1748.bin (version 2.0) Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.814355] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/glk_guc_ver10_56.bin Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.814384] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.814689] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10 Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.816048] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.816089] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.816090] [drm] GuC: Loaded firmware i915/glk_guc_ver10_56.bin (version 10.56) Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.816148] i915 0000:00:02.0: GuC firmware version 10.56 Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.816149] i915 0000:00:02.0: GuC submission enabled Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.816149] i915 0000:00:02.0: HuC enabled Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.816269] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.816313] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 11 Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.816401] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.816489] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.816579] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.865058] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.865145] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.865211] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.867338] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.885177] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.889134] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.889213] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.889274] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.891148] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.891169] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.905260] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.905331] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 739.905395] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.105288] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.105806] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.105862] Setting dangerous option enable_psr - tainting kernel Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.129290] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.129636] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.129806] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.134044] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.154855] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.159011] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.159096] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.159164] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.159181] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.159258] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.159292] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.159369] [drm:intel_edp_backlight_off [i915]] Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.364358] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.364480] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.373184] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.373289] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:45:37 GLK-2-GLKRVP1DDR405 kernel: [ 740.373389] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.424342] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.424439] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.424529] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.424669] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.424775] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.424897] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.425020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.425117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.425210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.425302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.425394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.425484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.425579] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.425675] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.425768] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.425875] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.426296] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.426404] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.426504] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.426652] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.455820] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.455945] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.456444] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.456581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.456678] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.456852] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.473518] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.474055] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.474149] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.474293] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.474421] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.474547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.474643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.474741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.474833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.474924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.475015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.475109] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.475204] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.475298] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.475390] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.489149] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.489276] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.489448] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.489584] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.489683] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.489835] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.489939] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.490075] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.506550] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.506653] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.506740] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.506818] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.506908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.506965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.507023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.507077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.507131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.507185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.507243] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.507296] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.507349] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.507401] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.507463] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.507520] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.507588] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.512508] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516135] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516155] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516223] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516254] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516271] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516304] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516346] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516378] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516410] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516444] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516477] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516507] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516540] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516572] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516602] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516631] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516648] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516677] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516691] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516721] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516753] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516783] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516812] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516841] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516880] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516909] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516939] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.516971] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517001] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517036] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517066] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517131] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517171] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517202] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517556] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517891] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517920] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.517948] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.518000] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.518031] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.518165] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.518202] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 740.518235] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.052338] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.052448] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.052544] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.052638] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.154617] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.154729] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.154835] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.155004] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.255215] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.255315] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.255413] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.255566] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.255674] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.255779] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.257000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.257091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.257186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.257901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.257990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.258646] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.258736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.259700] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.259794] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.260408] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.260525] [drm:intel_edp_backlight_on [i915]] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.260622] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.260719] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.260821] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.277337] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.277417] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:38 GLK-2-GLKRVP1DDR405 kernel: [ 741.277557] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.527496] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.527642] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.527799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.527900] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.528078] [drm:intel_edp_backlight_off [i915]] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.736342] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.736468] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.745202] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.745307] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.745410] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.796613] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.796710] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.796802] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.796953] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.797083] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.797211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.797312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.797410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.797504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.797597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.797690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.797787] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.797883] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.797975] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.798067] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.798166] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.798269] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.798368] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.798465] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.798588] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.798700] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.798802] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.798894] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.798984] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.799076] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.799228] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.799339] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.809995] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.817270] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.823743] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.828668] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.981718] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.981739] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.981808] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.981838] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.981853] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.981888] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.981928] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.981957] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.981989] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982057] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982087] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982120] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982152] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982180] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982208] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982221] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982250] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982263] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982292] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982323] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982351] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982379] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982407] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982444] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982472] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982503] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982536] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982566] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982597] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982628] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982659] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982691] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982727] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.982760] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.983601] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.983628] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.984617] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.984655] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985396] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985428] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985457] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985510] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985539] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985661] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985744] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:45:39 GLK-2-GLKRVP1DDR405 kernel: [ 741.985777] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.428338] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.428448] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.428547] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.428644] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.530625] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.530739] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.530846] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.531032] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.629977] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.630075] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.630173] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.630281] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.630388] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.630492] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.631669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.631761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.631857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.632722] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.632818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.633785] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.633881] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.634478] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.634615] [drm:intel_edp_backlight_on [i915]] Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.634712] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.634807] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.640178] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.651513] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.651609] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.651741] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.901492] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.901578] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 742.901640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 743.168052] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 743.168173] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:40 GLK-2-GLKRVP1DDR405 kernel: [ 743.168234] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.434496] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.434582] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.434643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.700907] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.701098] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.701250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.701350] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.701518] [drm:intel_edp_backlight_off [i915]] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.908331] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.908458] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.917212] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.917316] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.917419] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.969034] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.969136] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.969230] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.969383] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.969511] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.969638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.969739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.969837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.969931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.970024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.970116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.970213] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.970309] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.970405] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.970500] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.970615] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.970726] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.970820] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.970911] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.971012] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.971119] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.971220] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.971312] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.971401] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.971493] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.971639] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.971749] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.972274] Setting dangerous option enable_psr - tainting kernel Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.974114] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.974200] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.975179] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.976516] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.976537] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.976593] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.976635] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.976655] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.976700] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.976753] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.976794] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.976838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.976882] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.976924] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.976965] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977007] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977048] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977088] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977106] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977147] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977165] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977207] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977249] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977289] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977330] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977370] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977414] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977455] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977495] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977536] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977576] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977616] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977656] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977699] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977740] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977789] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.977831] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.980204] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.980533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.980581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.980653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.980698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.980741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.980784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.980831] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.980877] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.980921] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.980991] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.981034] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.981179] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.981234] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:45:41 GLK-2-GLKRVP1DDR405 kernel: [ 743.981278] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.604352] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.604460] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.604556] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.604651] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.706653] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.706766] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.706872] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.707040] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.806284] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.806385] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.806483] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.806590] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.806698] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.806803] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.807983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.808076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.808217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.809444] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.809582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.810558] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.810653] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.811252] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.811390] [drm:intel_edp_backlight_on [i915]] Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.811487] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.811582] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.816434] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.828305] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.828386] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 744.828502] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 745.078357] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:42 GLK-2-GLKRVP1DDR405 kernel: [ 745.328243] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.577958] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.594508] Setting dangerous option enable_psr - tainting kernel Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.594523] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.624397] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.624481] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.624567] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.624651] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.624725] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.624806] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.624885] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.624961] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625035] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625110] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625182] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625254] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625295] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625368] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625401] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625477] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625550] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625623] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625696] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625767] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625849] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625922] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.625996] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.626068] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.626140] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.626212] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.626284] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.626361] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.626471] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.626547] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.626624] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.626699] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.626772] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.626844] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.626916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.626988] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627021] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627093] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627126] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627200] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627273] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627345] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627417] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627488] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627567] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627639] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627711] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627783] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627855] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627927] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.627998] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.628079] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.628190] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.628253] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.628285] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.628321] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.628353] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.628390] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.628426] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.629040] [drm:intel_edp_backlight_off [i915]] Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.836344] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.836470] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.845149] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.845254] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.845359] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.896911] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.897012] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.897106] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.897259] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.897388] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.897487] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.897626] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.897847] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.898087] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.898221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.898315] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.898412] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.898508] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.898621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.898730] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.898826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.898921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.899015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.899109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.899204] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.899299] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.899392] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.899537] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.899632] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.899978] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.900081] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:45:43 GLK-2-GLKRVP1DDR405 kernel: [ 745.900233] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.524345] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.524455] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.524552] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.524647] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.626621] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.626731] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.626838] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.626975] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.725788] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.725888] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.725986] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.726139] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.726246] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.726349] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.727521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.727614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.727706] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.728714] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.728811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.729776] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.729871] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.730324] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.730439] [drm:intel_edp_backlight_on [i915]] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.730536] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.730631] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.736332] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.736443] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.736538] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.747342] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.747437] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.747635] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.747734] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.748377] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.749062] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.749569] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.749647] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.750178] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.750275] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.750352] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.750434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.750505] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.751025] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.751196] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.751684] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.751755] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.752310] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.752401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.752477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.752552] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.753067] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.753237] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.753723] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.753793] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.754322] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.754401] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.754477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.754548] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.755068] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.755535] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.756022] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.756123] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.756666] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.756752] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.757166] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.757238] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.757728] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.758006] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.758100] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.758228] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.758303] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.758474] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.758806] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.759393] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.759472] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.759554] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.759627] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.776428] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.776519] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.776652] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.776778] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.776852] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.776966] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.777087] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.777161] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.777262] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.864307] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.864598] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.864750] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.868878] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.887343] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.891297] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.891376] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.891436] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.891949] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 746.891970] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.097354] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.097855] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.097904] Setting dangerous option enable_psr - tainting kernel Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.122011] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.122123] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.122213] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.124907] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.143584] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.148214] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.148350] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.148412] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.148428] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.148503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.148537] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.148775] [drm:intel_edp_backlight_off [i915]] Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.356359] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.356483] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.365221] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.365326] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:45:44 GLK-2-GLKRVP1DDR405 kernel: [ 747.365426] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.416369] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.416467] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.416558] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.416701] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.416809] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.416932] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.417056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.417154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.417249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.417341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.417433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.417524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.417619] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.417715] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.417808] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.417915] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.418298] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.418405] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.418504] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.418656] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.426408] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.426532] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.426721] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.426856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.426956] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.427132] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.443031] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.443562] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.443674] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.443818] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.443945] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.444073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.444217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.444809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.444904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.444998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.445092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.445190] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.445286] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.445382] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.445474] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.459743] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.459869] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.460045] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.460521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.460622] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.460776] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.460881] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.461017] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.477745] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.477902] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.478032] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.478160] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.478292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.478390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.478488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.478582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.478674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.478766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.478865] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.478959] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.479051] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.479142] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.479246] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.479341] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.479452] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.488664] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492310] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492331] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492399] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492428] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492444] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492478] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492518] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492547] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492578] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492646] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492676] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492710] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492740] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492768] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492796] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492809] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492837] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492849] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492878] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492906] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492937] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492965] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.492993] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493032] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493060] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493091] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493123] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493153] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493186] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493216] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493278] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493314] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493346] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493690] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.493981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.494009] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.494041] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.494069] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.494122] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.494150] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.494285] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.494323] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 747.494353] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.028381] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.028489] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.028586] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.028682] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.130618] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.130729] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.130834] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.131009] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.229358] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.229456] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.229554] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.229708] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.229816] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.229918] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.231166] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.231267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.231366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.232035] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.232172] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.233404] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.233500] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.234099] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.234219] [drm:intel_edp_backlight_on [i915]] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.234315] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.234409] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.240146] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.251141] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.251230] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:45 GLK-2-GLKRVP1DDR405 kernel: [ 748.251374] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.501222] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.501367] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.501520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.501621] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.501795] [drm:intel_edp_backlight_off [i915]] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.708340] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.708465] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.719941] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.720046] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.720208] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.770240] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.770341] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.770433] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.770587] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.770714] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.770842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.770944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.771041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.771135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.771228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.771321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.771418] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.771513] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.771606] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.771697] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.771796] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.771903] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.772066] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.772945] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.773042] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.773139] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.773296] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.773464] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.778693] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.782827] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.786923] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.790962] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.932394] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.932427] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.932460] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.932494] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.946815] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.946836] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.946892] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.946924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.946940] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.946978] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947018] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947048] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947080] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947117] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947151] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947181] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947245] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947274] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947303] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947316] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947345] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947357] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947387] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947416] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947447] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947476] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947504] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947541] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947570] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947601] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947633] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947664] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947695] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947726] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947758] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947790] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947826] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.947858] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.948725] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.948753] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.949733] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.949766] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.949910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.949942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.949974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.950002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.950033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.950064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.950092] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.950125] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.950154] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.950208] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.950237] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.950360] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.950398] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:45:46 GLK-2-GLKRVP1DDR405 kernel: [ 748.950428] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.404343] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.404452] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.404549] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.404644] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.506562] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.506673] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.506778] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.506937] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.607024] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.607124] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.607222] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.607331] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.607439] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.607544] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.608765] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.608859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.608957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.609634] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.609723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.610378] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.610469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.611433] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.611528] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.612151] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.612292] [drm:intel_edp_backlight_on [i915]] Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.612387] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.612488] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.612591] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.629267] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.629384] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.629537] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.879280] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.879368] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 749.879430] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 750.145709] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 750.145796] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:47 GLK-2-GLKRVP1DDR405 kernel: [ 750.145857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.412062] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.412174] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.412235] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.678652] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.678846] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.679005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.679106] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.679284] [drm:intel_edp_backlight_off [i915]] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.884348] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.884477] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.895954] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.896057] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.896200] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.948322] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.948424] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.948518] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.948671] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.948798] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.948925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.949027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.949117] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.949223] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.949321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.949415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.949508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.949612] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.949705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.949811] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.949909] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.950385] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.950483] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.950577] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.950679] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.950788] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.950889] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.950983] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.951075] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.951168] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.951327] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.951426] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.951851] Setting dangerous option enable_psr - tainting kernel Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.953787] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.953866] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.954685] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.955056] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.955096] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.955206] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.955290] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.955331] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.955420] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.955525] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.955608] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.955694] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.955779] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.955863] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.955956] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.956040] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.956142] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.956227] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.956269] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.956357] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.956399] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.956489] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.956576] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.956662] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.956749] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.956835] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.956927] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.957015] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.957081] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.957152] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.957218] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.957284] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.957350] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.957424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.957491] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.957572] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.957641] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.958878] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959198] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959227] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959255] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959309] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959340] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959463] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959500] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:45:48 GLK-2-GLKRVP1DDR405 kernel: [ 750.959530] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.580343] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.580452] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.580550] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.580646] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.682598] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.682711] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.682818] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.682992] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.783457] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.783557] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.783655] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.783763] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.783868] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.783973] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.785407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.785500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.785595] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.786261] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.786342] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.787300] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.787385] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.787974] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.788087] [drm:intel_edp_backlight_on [i915]] Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.788202] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.788288] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.788537] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.805071] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.805189] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 751.805343] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 752.055091] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:49 GLK-2-GLKRVP1DDR405 kernel: [ 752.304874] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.554668] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.571296] Setting dangerous option enable_psr - tainting kernel Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.571315] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.592470] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.592546] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.592625] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.592701] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.592768] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.592840] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.592913] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.592982] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593183] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593248] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593286] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593352] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593382] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593451] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593517] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593582] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593713] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593787] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593853] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593919] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.593984] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594050] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594115] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594180] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594249] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594348] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594417] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594485] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594553] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594619] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594685] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594750] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594849] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594879] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594945] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.594974] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595042] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595107] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595173] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595238] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595302] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595374] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595440] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595505] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595570] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595635] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595700] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595765] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595906] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.595988] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.596056] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.596164] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.596221] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.596257] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.596289] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.597321] [drm:intel_edp_backlight_off [i915]] Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.804365] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.804492] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.821403] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.821508] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.821611] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.873372] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.873473] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.873568] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.873722] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.873850] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.873950] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.874089] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.874314] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.874486] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.874587] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.874695] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.874798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.874894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.874997] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.875097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.875199] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.875294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.875394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.875494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.875594] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.875693] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.875790] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.875929] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.876025] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.876425] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.876531] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:45:50 GLK-2-GLKRVP1DDR405 kernel: [ 752.876635] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.500387] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.500495] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.500592] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.500686] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.602614] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.602725] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.602832] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.602990] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.702982] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.703080] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.703178] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.703330] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.703437] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.703541] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.704750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.704852] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.704954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.705621] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.705714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.706674] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.706770] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.707221] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.707336] [drm:intel_edp_backlight_on [i915]] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.707435] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.707529] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.716291] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.716391] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.716474] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.724155] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.724215] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.724341] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.724386] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.724829] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.725455] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.725902] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.725943] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.726390] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.726447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.726476] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.726506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.726534] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.727005] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.727132] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.727563] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.728198] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.728640] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.728682] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.729164] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.729209] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.729238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.729266] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.729737] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.730161] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.730592] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.731223] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.731662] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.731704] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.732189] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.732222] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.732587] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.732620] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.733064] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.733245] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.733323] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.733395] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.733429] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.733551] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.733759] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.734218] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.734252] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.734290] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.734324] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.751256] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.751327] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.751424] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.751518] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.751577] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.751662] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.751753] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.751809] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.751891] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.840268] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.840426] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.840500] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.842769] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.860504] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.864453] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.864592] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.864653] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.865151] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 753.865170] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.074210] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.074718] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.074766] Setting dangerous option enable_psr - tainting kernel Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.098380] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.098497] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.098600] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.101350] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.120860] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.128209] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.128372] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.128443] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.128460] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.128534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.128567] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.128776] [drm:intel_edp_backlight_off [i915]] Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.336338] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.336461] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.342479] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.342584] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:45:51 GLK-2-GLKRVP1DDR405 kernel: [ 754.342684] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.393010] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.393109] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.393200] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.393340] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.393447] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.393569] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.393693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.393790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.393883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.393974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.394065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.394155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.394250] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.394345] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.394438] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.394544] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.395676] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.395786] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.395888] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.396067] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.401233] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.401298] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.401400] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.401447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.401478] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.401544] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.417794] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418266] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418317] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418401] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418477] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418826] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418873] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418920] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.418966] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.434626] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.434739] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.434898] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.435021] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.435111] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.435244] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.435336] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.435453] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.452353] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.452508] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.452639] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.452767] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.452900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.452998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.453096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.453190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.453283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.453375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.453475] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.453568] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.453661] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.453752] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.453856] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.453951] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.454062] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.462247] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467099] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467213] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467252] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467274] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467322] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467375] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467415] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467457] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467503] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467547] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467587] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467629] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467669] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467707] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467745] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467763] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467801] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467818] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467858] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467897] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467937] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.467975] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.468013] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.468059] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.468110] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.468156] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.468200] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.468243] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.468287] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.468329] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.468376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.468421] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.468474] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.468518] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469004] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469400] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469440] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469481] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469546] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469586] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469735] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469785] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 754.469827] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.004343] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.004452] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.004549] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.004646] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.106615] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.106725] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.106830] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.107004] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.206895] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.206995] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.207093] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.207245] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.207352] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.207457] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.209163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.209257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.209351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.210016] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.210108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.211071] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.211166] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.211764] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.211882] [drm:intel_edp_backlight_on [i915]] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.211978] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.212073] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.212810] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.228739] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.228836] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:52 GLK-2-GLKRVP1DDR405 kernel: [ 755.228993] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.478889] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.479033] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.479185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.479287] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.479461] [drm:intel_edp_backlight_off [i915]] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.684344] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.684472] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.695949] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.696054] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.696226] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.747093] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.747195] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.747289] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.747441] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.747568] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.747695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.747796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.747893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.747987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.748080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.748235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.748334] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.748435] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.748528] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.748626] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.748727] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.748838] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.749054] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.749154] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.749253] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.749312] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.749426] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.750294] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.757741] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.762026] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.766216] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.771707] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.803772] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.803793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.803861] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.803892] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.803909] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.803944] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.803983] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804012] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804043] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804112] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804144] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804176] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804209] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804242] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804272] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804302] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804318] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804348] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804364] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804396] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804426] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804458] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804519] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804556] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804586] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804619] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804650] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804682] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804714] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804744] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804812] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804854] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.804885] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805235] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805565] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805598] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805628] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805682] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805715] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805851] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805888] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:45:53 GLK-2-GLKRVP1DDR405 kernel: [ 755.805919] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.380348] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.380458] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.380555] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.380651] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.482618] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.482729] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.482835] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.483009] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.581072] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.581172] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.581270] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.581423] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.581530] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.581634] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.582873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.582973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.583072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.583738] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.583830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.584812] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.584908] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.585509] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.585629] [drm:intel_edp_backlight_on [i915]] Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.585725] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.585819] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.592162] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.602592] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.602697] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.602859] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.852649] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.852727] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 756.852784] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 757.119102] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 757.119189] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:54 GLK-2-GLKRVP1DDR405 kernel: [ 757.119250] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.385547] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.385633] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.385694] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.651955] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.652439] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.652598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.652698] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.652867] [drm:intel_edp_backlight_off [i915]] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.860336] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.860463] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.869215] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.869320] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.869424] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.920188] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.920251] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.920308] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.920413] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.920503] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.920585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.920649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.920709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.920768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.920826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.920885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.920945] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.921005] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.921062] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.921119] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.921180] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.921248] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.921312] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.921371] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.921428] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.921487] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.921585] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.921654] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.921942] Setting dangerous option enable_psr - tainting kernel Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.922651] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.922711] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.922764] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.922833] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.922899] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.923687] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.923769] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.925061] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.925098] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.925198] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.925274] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.925312] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.925393] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.925490] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.925564] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.925645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.925722] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.925799] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.925873] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.925949] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926022] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926095] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926129] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926203] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926236] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926313] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926386] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926461] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926533] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926607] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926687] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926761] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926838] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926912] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.926984] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.927058] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.927130] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.927210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.927284] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.927371] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.927447] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.928421] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.928599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.928681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.928759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.928835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.928955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.929031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.929112] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.929193] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.929274] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.929389] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.929468] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.929650] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.929738] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:45:55 GLK-2-GLKRVP1DDR405 kernel: [ 757.929818] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.556348] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.556457] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.556554] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.556650] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.658608] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.658720] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.658827] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.659000] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.757475] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.757575] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.757674] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.757781] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.757889] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.757994] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.759173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.759265] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.759360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.760035] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.760173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.761032] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.761124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.762091] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.762185] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.762731] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.762814] [drm:intel_edp_backlight_on [i915]] Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.762866] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.762918] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.768256] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.779804] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.779901] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 758.780032] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 759.029861] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:56 GLK-2-GLKRVP1DDR405 kernel: [ 759.279668] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 759.529462] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 759.779230] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.029029] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.045581] Setting dangerous option enable_psr - tainting kernel Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.045596] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.076359] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.076434] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.076513] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.076589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.076656] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.076729] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.076801] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.076870] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.076937] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077005] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077071] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077136] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077174] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077240] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077270] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077339] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077405] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077471] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077536] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077601] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077673] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077739] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077805] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077870] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.077936] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078001] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078066] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078135] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078235] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078303] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078372] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078439] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078505] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078570] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078634] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078698] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078730] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078794] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078824] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078891] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.078957] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079021] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079085] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079146] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079176] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079203] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079231] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079258] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079286] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079313] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079341] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079372] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079403] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079443] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079472] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079504] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079532] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079565] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079592] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.079813] [drm:intel_edp_backlight_off [i915]] Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.284341] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.284470] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.295815] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.295920] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.296023] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.347079] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.347180] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.347274] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.347426] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.347554] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.347654] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.347793] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.348015] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.348873] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.348976] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.349081] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.349182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.349279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.349382] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.349477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.349582] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.349677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.349770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.349863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.349959] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.350053] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.350146] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.350283] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.350378] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.350726] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.350830] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:45:57 GLK-2-GLKRVP1DDR405 kernel: [ 760.350927] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 760.956361] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 760.956470] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 760.956566] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 760.956660] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.058619] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.058732] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.058838] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.059015] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.159282] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.159382] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.159481] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.159634] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.159742] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.159847] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.161070] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.161163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.161258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.161933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.162023] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.162673] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.162764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.163723] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.163818] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.164293] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.164410] [drm:intel_edp_backlight_on [i915]] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.164508] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.164606] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.164858] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.164971] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.165065] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.181302] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.181388] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.181574] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.181665] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.182160] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.182835] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.183330] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.183400] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.183893] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.183989] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.184080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.184221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.184468] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.185016] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.185209] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.185726] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.185817] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.186369] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.186479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.186571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.186659] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.187142] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.187285] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.187744] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.187788] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.188294] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.188350] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.188400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.188444] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.188937] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.189378] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.189836] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.189880] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.190380] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.190432] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.190812] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.190857] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.191319] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.191533] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.191598] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.191692] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.191738] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.191876] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.192173] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.192709] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.192760] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.192813] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.192862] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.209769] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.209840] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.209962] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.210056] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.210114] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.210196] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.210313] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.210368] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.210448] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.290634] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.290750] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.290853] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.294133] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.313605] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.317585] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.317666] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.317728] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.318167] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:58 GLK-2-GLKRVP1DDR405 kernel: [ 761.318187] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.531333] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.531863] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.531910] Setting dangerous option enable_psr - tainting kernel Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.555505] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.555637] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.555761] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.559003] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.578718] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.582859] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.582938] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.583001] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.583017] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.583092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.583127] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.583376] [drm:intel_edp_backlight_off [i915]] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.788360] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.788482] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.798804] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.798909] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.799008] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.849896] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.849995] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.850086] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.850225] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.850332] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.850454] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.850577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.850675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.850768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.850859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.850950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.851040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.851134] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.851228] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.851320] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.851427] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.851970] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.852078] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.852185] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.852346] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.859733] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.859859] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.860047] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.860231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.860335] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.860509] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.876835] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.877312] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.877361] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.877444] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.877519] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.877588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.877637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.877685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.877731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.877776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.877822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.877870] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.877918] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.877965] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.878010] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.893092] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.893185] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.893328] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.893432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.893507] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.893617] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.893695] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.893793] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.909915] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.910056] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.910174] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.910289] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.910411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.910498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.910586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.910669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.910752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.910834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.910922] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.911006] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.911089] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.911170] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.911261] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.911346] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.911446] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.920298] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924213] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924235] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924304] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924336] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924353] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924389] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924423] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924456] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924493] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924525] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924560] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924593] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924629] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924660] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924698] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924731] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924803] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924835] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924867] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924882] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924914] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924930] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924963] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.924995] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925027] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925062] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925095] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925129] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925163] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925193] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925224] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925254] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925285] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925317] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925384] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925426] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925457] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925763] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.925792] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926321] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926357] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926694] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926728] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926758] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926813] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926847] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.926971] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.927010] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:45:59 GLK-2-GLKRVP1DDR405 kernel: [ 761.927046] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.460349] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.460459] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.460557] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.460654] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.562503] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.562613] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.562717] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.562892] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.663116] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.663214] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.663312] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.663421] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.663528] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.663632] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.664841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.664946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.665047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.665717] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.665809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.666772] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.666866] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.667465] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.667599] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.667695] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.667788] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.672147] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.684577] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.684684] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.684823] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.934585] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.934730] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.934888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.934990] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 762.935167] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.140368] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.140497] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.151226] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.151330] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.151434] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.203468] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.203567] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.203661] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.203813] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.203941] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.204066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.204217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.204319] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.204424] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.204526] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.204638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.204733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.204831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.204924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.205021] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.205132] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.205227] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.205323] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.205426] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.205524] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.205634] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.205737] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.205830] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.205920] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.206011] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.206151] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.206260] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.213081] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.218793] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.223725] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.228678] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.261997] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262017] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262084] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262114] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262129] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262164] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262203] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262232] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262263] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262299] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262332] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262362] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262424] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262453] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262481] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262494] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262522] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262534] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262564] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262592] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262623] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262715] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262743] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262774] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262807] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262837] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262867] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262898] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262929] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262961] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.262997] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.263028] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.263867] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.263894] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.264895] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.264936] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.265491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.265523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.265555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.265583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.265614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.265645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.265674] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.265706] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.265735] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.265788] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.265816] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.265990] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.266026] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:00 GLK-2-GLKRVP1DDR405 kernel: [ 763.266058] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 763.836345] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 763.836474] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 763.836573] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 763.836670] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 763.938607] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 763.938718] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 763.938825] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 763.938992] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.037863] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.037900] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.037936] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.037982] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.038021] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.038059] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.039149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.039177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.039209] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.039818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.039845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.040430] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.040479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.041379] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.041431] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.041969] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.042039] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.042089] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.042138] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.048307] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.058975] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.059041] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.059144] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.309047] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.309132] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:01 GLK-2-GLKRVP1DDR405 kernel: [ 764.309190] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 764.575448] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 764.575533] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 764.575593] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 764.841969] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 764.842055] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 764.842116] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 765.108447] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 765.108635] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 765.108791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 765.108892] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 765.109051] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 765.316340] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 765.316467] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 765.325168] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 765.325202] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:02 GLK-2-GLKRVP1DDR405 kernel: [ 765.325239] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.376643] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.376742] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.376836] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.376988] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.377116] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.377244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.377346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.377444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.377538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.377632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.377725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.377821] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.377916] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.378009] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.378101] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.378201] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.378292] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.378400] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.378495] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.378601] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.378690] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.378782] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.378890] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.378980] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.379079] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.379224] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.379333] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.379795] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.381688] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.381776] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.382645] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.383032] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.383077] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.383200] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.383293] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.383338] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.383438] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.383556] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.383649] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.383746] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.383842] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.383936] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384028] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384153] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384228] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384262] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384279] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384313] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384330] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384364] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384398] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384432] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384466] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384536] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384569] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384601] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384633] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384664] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384696] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384727] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384763] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384795] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384836] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.384869] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.386543] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.386686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.386720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.386755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.386786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.386817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.386847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.386879] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.386910] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.386938] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.386992] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.387024] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.387166] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.387223] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 765.387254] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.012336] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.012445] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.012542] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.012638] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.114498] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.114609] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.114716] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.114928] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.214924] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.215024] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.215122] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.215230] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.215338] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.215441] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.216688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.216790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.216887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.217597] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.217700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.218678] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.218776] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.219343] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.219451] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.219523] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.219592] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.224508] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.236412] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.236517] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:03 GLK-2-GLKRVP1DDR405 kernel: [ 766.236661] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:04 GLK-2-GLKRVP1DDR405 kernel: [ 766.486463] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:04 GLK-2-GLKRVP1DDR405 kernel: [ 766.736267] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:04 GLK-2-GLKRVP1DDR405 kernel: [ 767.002593] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:04 GLK-2-GLKRVP1DDR405 kernel: [ 767.252509] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.502184] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.535560] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.535579] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.560425] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.560490] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.560556] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.560620] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.560677] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.560739] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.560801] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.560860] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.560918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.560976] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561032] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561086] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561120] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561176] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561202] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561259] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561315] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561371] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561427] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561482] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561545] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561600] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561656] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561712] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561767] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561822] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561878] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.561936] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562021] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562079] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562137] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562194] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562250] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562306] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562361] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562415] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562441] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562497] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562522] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562580] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562636] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562691] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562747] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562801] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562863] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562918] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.562974] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.563029] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.563084] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.563140] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.563194] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.563257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.563313] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.563383] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.563441] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.563501] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.563558] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.563621] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.563677] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.563945] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.768320] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.768447] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.785349] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.785453] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.785558] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.836708] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.836809] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.836903] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.837054] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.837183] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.837283] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.837422] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.837643] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.837884] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.838017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.838114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.838209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.838302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.838393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.838486] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.838592] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.838684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.838781] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.838884] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.838978] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.839081] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.839176] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.839329] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.839425] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.839778] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.839887] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:05 GLK-2-GLKRVP1DDR405 kernel: [ 767.839990] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.444355] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.444464] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.444561] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.444656] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.546596] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.546708] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.546814] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.546993] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.647055] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.647155] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.647253] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.647406] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.647513] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.647616] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.649240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.649334] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.649426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.650108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.650199] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.650860] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.650951] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.651913] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.652008] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.652835] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.652950] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.653048] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.653143] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.653399] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.653511] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.653604] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.669873] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.669981] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.670195] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.670304] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.670825] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.671517] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.672038] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.672465] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.672987] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.673080] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.673111] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.673145] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.673175] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.673654] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.673781] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.674227] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.674270] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.674757] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.674812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.674840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.674867] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.675337] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.675464] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.675910] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.675939] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.676428] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.676473] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.676504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.676531] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.677009] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.677434] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.677881] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.677924] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.678411] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.678455] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.678816] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.678844] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.679290] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.679493] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.679550] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.679618] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.679647] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.679764] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.679976] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.680533] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.680568] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.680978] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.681009] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.697609] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.697675] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.697769] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.697856] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.697910] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.697989] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.698074] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.698127] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.698204] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.788249] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.788410] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.788484] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.790747] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.807673] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.811604] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.811685] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.811746] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.812431] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 768.812451] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.019861] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.020486] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.020532] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.044672] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.044845] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.044921] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.047094] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.064901] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.068955] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.069038] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.069099] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.069383] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.069454] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.069486] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.069709] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.276332] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.276455] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.287853] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.287958] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.288060] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.339473] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.339572] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.339662] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.339804] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.339911] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.340033] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.340748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.340847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.340941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.341036] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.341131] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.341224] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.341329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.341437] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.341530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.341622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.341717] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.341813] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.341906] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.342014] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.347548] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.347674] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.347857] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.347991] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.348088] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.348698] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.365360] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.365894] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.365988] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.366130] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.366257] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.366382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.366479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.366575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.366666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.366756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.366846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.366940] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.367035] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.367128] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:06 GLK-2-GLKRVP1DDR405 kernel: [ 769.367219] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.380890] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.381014] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.381186] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.381322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.381422] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.381570] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.381674] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.381811] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.397651] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.399436] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.399568] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.399695] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.399827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.399923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.400017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.400113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.400247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.400339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.400812] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.400919] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.401020] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.401117] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.401221] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.401320] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.401436] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.406477] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410132] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410153] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410221] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410251] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410268] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410303] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410342] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410371] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410402] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410438] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410471] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410500] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410565] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410592] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410620] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410633] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410661] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410674] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410703] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410733] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410761] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410789] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410816] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410853] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410881] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410912] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410944] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.410974] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411004] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411035] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411099] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411136] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411168] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411500] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411819] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411851] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411879] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411932] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.411961] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.412570] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.412603] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.412652] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.948380] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.948489] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.948587] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 769.948682] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.050597] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.050709] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.050815] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.050988] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.149721] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.149821] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.149919] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.150072] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.150179] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.150282] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.151484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.151576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.151670] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.152496] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.152589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.153557] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.153651] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.154250] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.154366] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.154462] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.154557] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.160151] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.171332] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.171451] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:07 GLK-2-GLKRVP1DDR405 kernel: [ 770.171627] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.421374] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.421522] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.421678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.421780] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.421956] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.628241] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.628369] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.639803] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.639906] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.640011] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.691366] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.691467] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.691559] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.691715] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.691843] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.691971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.692072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.692242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.692342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.692442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.692539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.692639] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.692781] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.692877] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.692975] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.693072] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.693187] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.693295] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.693389] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.693488] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.693601] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.693758] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.693868] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.703123] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.707908] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.713417] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.718416] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871197] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871218] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871286] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871316] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871334] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871369] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871408] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871437] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871468] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871504] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871537] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871568] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871602] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871634] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871662] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871690] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871706] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871734] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871747] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871777] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871805] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871836] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871929] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871957] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.871989] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872021] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872052] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872110] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872145] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872216] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872258] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872293] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872653] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.872984] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.873017] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.873047] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.873102] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.873132] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.873267] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.873302] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 770.873334] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 771.324340] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 771.324448] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 771.324546] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:08 GLK-2-GLKRVP1DDR405 kernel: [ 771.324641] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.426598] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.426711] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.426816] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.426995] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.527060] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.527160] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.527258] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.527411] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.527519] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.527624] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.528874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.528975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.529077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.529750] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.529843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.530807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.530910] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.531513] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.531632] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.531728] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.531823] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.536152] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.548541] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.548657] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.548830] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.798666] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.798752] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 771.798814] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 772.065117] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 772.065204] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 772.065264] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 772.331454] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 772.331541] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:09 GLK-2-GLKRVP1DDR405 kernel: [ 772.331602] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.597895] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.598088] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.598243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.598344] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.598509] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.804335] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.804461] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.815898] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.816004] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.816107] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.867905] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.868007] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.868099] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.868517] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.868648] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.868776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.868877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.868978] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.869078] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.869176] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.869291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.869387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.869483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.869577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.869677] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.869774] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.869870] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.869963] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.870065] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.870175] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.870279] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.870372] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.870464] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.870558] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.870705] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.870817] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.871251] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.871289] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.871506] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.871583] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.872188] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.873507] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.873546] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.873657] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.873741] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.873781] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.873871] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.873976] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.874059] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.874147] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.874233] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.874316] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.874399] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.874482] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.874563] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.874642] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.874679] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.874760] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.874796] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.874880] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.874961] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.875042] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.875123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.875202] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.875296] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.875377] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.875458] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.875539] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.875619] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.875699] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.875778] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.875865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.875947] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.876043] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.876152] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.877316] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.877469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.877508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.877547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.877585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.877623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.877661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.877699] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.877738] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.877810] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.877877] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.877920] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.878056] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.878106] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:10 GLK-2-GLKRVP1DDR405 kernel: [ 772.878147] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.500342] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.500448] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.500545] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.500640] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.602600] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.602712] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.602818] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.603002] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.702725] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.702825] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.702923] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.703030] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.703139] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.703241] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.704620] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.704713] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.704812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.705499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.705588] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.706240] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.706321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.707274] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.707359] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.707950] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.708061] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.708187] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.708316] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.708562] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.725018] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.725124] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.725265] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 773.975088] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.224771] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.241499] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.241523] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276435] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276516] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276552] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276584] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276624] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276662] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276696] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276734] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276800] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276831] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276855] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276887] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276902] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276934] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276966] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.276997] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277029] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277103] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277134] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277168] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277202] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277236] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277270] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277304] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277339] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277391] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277424] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277457] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277491] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277522] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277584] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277615] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277629] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277661] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277675] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277707] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277738] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277769] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277800] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277831] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277865] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277896] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277930] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277961] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.277995] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.278029] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.278062] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.278098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.278132] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.278176] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.278209] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.278245] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.278277] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.278314] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.278345] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:46:11 GLK-2-GLKRVP1DDR405 kernel: [ 774.278573] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.484338] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.484466] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.493198] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.493303] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.493405] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.544410] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.544511] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.544605] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.544757] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.544885] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.544985] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.545124] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.545349] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.545588] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.545721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.545818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.545912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.546006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.546099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.546189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.546283] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.546387] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.546482] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.546586] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.546680] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.546775] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.546928] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.547023] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.547293] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.547380] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.547463] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 774.547543] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.164368] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.164474] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.164571] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.164666] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.266595] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.266706] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.266812] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.266987] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.366270] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.366370] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.366468] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.366621] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.366729] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.366832] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.368040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.368180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.368285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.368989] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.369093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.370098] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.370204] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.370660] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.370781] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.370882] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:12 GLK-2-GLKRVP1DDR405 kernel: [ 775.370977] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.376545] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.376666] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.376763] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.387618] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.387697] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.387878] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.387962] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.388457] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.389127] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.389620] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.389684] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.390171] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.390258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.390328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.390404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.390469] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.390985] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.391150] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.391637] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.391701] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.392279] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.392368] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.392435] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.392501] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.393010] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.393173] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.393652] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.393717] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.394238] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.394320] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.394389] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.394454] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.394967] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.395428] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.395907] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.395971] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.396501] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.396579] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.396998] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.397064] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.397545] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.397820] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.397920] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.398047] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.398116] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.398278] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.398581] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.399175] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.399248] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.399323] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.399393] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.416204] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.416270] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.416364] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.416454] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.416506] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.416585] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.416675] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.416727] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.416804] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.503815] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.503956] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.504217] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.506528] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.524295] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.528238] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.528401] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.528462] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.528961] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.528980] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.737505] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.738056] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.738103] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.762791] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.763128] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.763306] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.767847] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.788389] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.792655] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.792739] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.792814] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.792831] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.792907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.792940] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 775.793167] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.000346] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.000468] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.006468] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.006572] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.006672] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.057632] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.057730] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.057821] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.057962] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.058070] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.058191] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.058314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.058411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.058504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.058596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.058687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.058778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.058873] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.058969] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.059062] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.059168] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.059607] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.059715] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.059816] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.059977] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.066159] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.066231] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.066323] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.066371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.066401] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.066463] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.083114] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.083613] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.083677] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.083781] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.083874] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.083962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.084026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.084507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.084570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.084631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.084692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.084756] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.084820] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.084884] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.084945] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.099525] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.099638] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.099796] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.099919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.100008] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.100198] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.100294] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.100411] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.116321] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.116475] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.116605] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.116732] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.116865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.116962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.117058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.117151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.117244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.117337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.117436] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.117529] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.117621] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.117712] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.117813] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.117909] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.118019] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.126189] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131045] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131072] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131152] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131192] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131213] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131312] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131351] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131392] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131438] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131482] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131522] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131566] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131607] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131645] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131683] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131700] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131738] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131755] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131795] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131836] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131874] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131912] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131950] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.131997] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.132036] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.132088] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.132134] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.132178] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.132220] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.132263] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.132311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.132358] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.132412] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.132455] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.132833] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.132964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.133007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.133049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.133088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.133127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.133168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.133208] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.133253] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.133295] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.133359] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.133399] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.133547] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.133597] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:13 GLK-2-GLKRVP1DDR405 kernel: [ 776.133640] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.668349] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.668456] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.668552] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.668647] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.770596] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.770709] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.770815] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.770990] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.871015] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.871116] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.871214] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.871367] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.871474] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.871578] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.873234] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.873327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.873422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.874086] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.874177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.875140] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.875235] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.875835] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.875953] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.876051] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.876777] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.876826] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.892884] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.892991] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 776.893154] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 777.142939] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 777.143086] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 777.143245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 777.143343] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 777.143519] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 777.348341] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 777.348468] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 777.359911] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 777.360016] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:14 GLK-2-GLKRVP1DDR405 kernel: [ 777.360118] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.412207] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.412308] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.412399] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.412554] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.412681] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.412808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.412908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.413006] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.413102] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.413199] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.413316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.413425] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.413521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.413614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.413707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.413804] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.413899] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.413992] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.414083] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.414182] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.414289] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.414390] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.414482] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.414572] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.414664] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.414813] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.414923] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.425549] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.433094] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.438507] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.443066] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596163] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596251] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596281] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596298] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596375] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596404] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596435] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596470] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596504] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596534] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596567] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596598] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596626] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596654] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596666] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596695] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596707] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596736] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596766] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596795] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596823] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596850] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596887] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596914] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596945] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.596976] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.597007] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.597038] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.597068] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.597100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.597131] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.597167] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.597199] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.598044] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.598072] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599029] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599063] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599385] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599417] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599446] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599498] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599527] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599652] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599689] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 777.599720] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.044342] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.044452] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.044549] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.044644] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.146598] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.146710] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.146815] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.146989] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.245769] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.245869] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.245968] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.246075] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.246182] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.246286] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.247492] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.247593] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.247689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.248528] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.248621] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.249591] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.249687] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.250286] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.250419] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.250516] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.250611] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.256178] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.267326] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.267421] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:15 GLK-2-GLKRVP1DDR405 kernel: [ 778.267553] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 778.517444] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 778.517531] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 778.517592] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 778.783863] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 778.783951] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 778.784011] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 779.050297] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 779.050384] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 779.050445] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 779.316641] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 779.316833] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 779.316987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 779.317089] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:16 GLK-2-GLKRVP1DDR405 kernel: [ 779.317261] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.524335] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.524462] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.533196] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.533301] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.533406] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.584507] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.584607] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.584701] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.584852] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.584980] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.585108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.585210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.585310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.585404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.585498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.585591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.585689] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.585785] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.585878] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.585970] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.586069] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.586173] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.586271] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.586367] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.586463] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.586577] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.586691] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.586782] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.586871] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.586963] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.587109] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.587220] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.587688] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.589613] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.589706] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.590552] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.590946] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.590993] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.591117] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.591212] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.591259] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.591360] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.591480] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.591573] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.591673] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.591769] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.591866] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.591958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.592054] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.592174] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.592267] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.592309] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.592404] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.592445] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.592544] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.592642] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.592740] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.592835] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.592932] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.593037] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.593134] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.593231] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.593326] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.593423] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.593520] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.593655] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.593753] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.593846] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.593952] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.594047] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.594683] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.594883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.594978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.595072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.595165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.595258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.595348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.595442] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.595540] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.595634] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.595771] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.595866] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.596067] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.596200] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 779.596245] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 780.220340] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 780.220448] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 780.220545] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 780.220640] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 780.322592] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 780.322703] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 780.322809] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:17 GLK-2-GLKRVP1DDR405 kernel: [ 780.322993] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.423199] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.423300] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.423398] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.423505] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.423613] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.423718] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.424906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.425000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.425095] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.425772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.425862] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.426502] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.426583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.427531] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.427616] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.428210] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.428320] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.428410] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.428498] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.428741] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.445179] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.445287] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.445437] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.695328] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.945111] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.945754] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.945806] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:84:DP-1] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.945948] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.946048] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.946151] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.946252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.946344] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.946442] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.946539] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.946635] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.946727] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.946821] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.946912] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.947002] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.947043] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.947134] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.947175] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.947269] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.947361] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.947453] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.947550] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.947640] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.947741] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.947831] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.947922] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.948013] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.948104] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.948254] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.948344] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.948451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.948551] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.948664] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.948762] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.949525] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.949668] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.949903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.950000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.950097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.950188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.950280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.950376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.950470] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.950583] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.950678] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.961413] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.961465] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.961616] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.961676] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.962136] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.962779] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.963245] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.963343] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.963805] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.963911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.963956] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.964005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.964048] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.964813] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.964956] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.965401] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.966084] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.966538] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.966625] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.967210] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.967274] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.967323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.967370] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.967853] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.968000] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.968456] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.969305] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.969784] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.969834] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.970335] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.970392] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.970447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.970495] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.970986] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.971431] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.971882] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.972583] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.973048] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.973096] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.973597] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.973655] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.974034] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.974083] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.974544] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.974908] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.974978] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.991911] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.991997] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 780.992189] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:18 GLK-2-GLKRVP1DDR405 kernel: [ 781.228054] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.477981] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.727712] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.744391] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.744406] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.766488] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.766559] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.766601] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.766649] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.766691] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.766731] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.766770] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.766814] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.766852] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.766879] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.766918] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.766935] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.766975] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767013] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767052] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767131] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767178] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767216] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767256] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767295] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767335] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767375] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767415] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767501] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767553] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767592] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767637] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767675] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767719] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767756] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.767994] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.972364] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.972491] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.978528] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.978634] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 781.978739] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.029751] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.029852] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.029947] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.030101] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.030230] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.030363] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.031668] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.031777] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.031879] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.032053] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.043075] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.043613] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.043708] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.043855] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.043985] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.044081] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.044847] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.044981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.045078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.045176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.045270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.045363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.045455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.045549] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.045643] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.045735] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.045882] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.045976] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.046324] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.046426] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:19 GLK-2-GLKRVP1DDR405 kernel: [ 782.046523] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.652356] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.652464] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.652560] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.652655] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.754592] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.754704] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.754811] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.754992] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.853729] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.853829] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.853926] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.854079] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.854186] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.854289] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.855473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.855564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.855658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.857031] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.857123] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.858097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.858192] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.858649] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.858765] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.858861] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.858956] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.864303] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.864357] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.864399] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.875651] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.875700] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.875864] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.875922] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.876385] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.877028] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.877495] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.877534] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.878012] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.878072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.878114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.878163] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.878203] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.878705] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.878846] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.879291] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.879978] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.880471] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.880534] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.881054] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.881127] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.881196] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.881255] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.881781] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.882233] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.882703] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.883547] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.884038] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.884132] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.884654] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.884721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.885109] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.885167] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.885619] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.885792] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.885840] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.902803] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.902858] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.902988] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.903212] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.903749] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.903781] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.903816] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.903843] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.920833] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.920913] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.921021] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.921124] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.921190] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.921291] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.921392] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.921456] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 782.921570] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.012748] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.012911] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.012984] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.015263] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.033016] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.036988] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.037068] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.037130] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.037639] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.037659] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.242165] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.242748] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.242797] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.266514] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.266629] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.266731] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.269550] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.289076] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.293143] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.293222] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.293285] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.293301] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.293377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.293410] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:20 GLK-2-GLKRVP1DDR405 kernel: [ 783.293682] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.500349] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.500459] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.509166] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.509259] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.509347] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.561242] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.561341] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.561432] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.561573] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.561680] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.561802] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.561925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.562023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.562116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.562207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.562302] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.562396] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.562488] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.562592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.562701] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.562793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.562888] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.562982] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.563074] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.563180] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.570765] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.570880] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.571050] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.571170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.571259] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.571416] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.587039] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.587510] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.587561] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.587648] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.587726] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.587797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.587845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.587893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.587939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.587985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.588030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.588118] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.588603] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.588651] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.588697] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.604094] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.604224] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.604362] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.604464] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.604539] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.604651] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.604728] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.604830] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.623005] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.623146] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.623265] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.623380] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.623500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.623587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.623673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.623756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.623838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.623919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.624007] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.624092] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.625031] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.625125] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.625227] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.625322] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.625433] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.634909] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639451] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639472] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639542] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639571] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639588] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639625] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639664] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639693] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639724] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639759] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639792] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639822] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639855] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639886] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639914] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639942] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639955] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639983] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.639995] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640024] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640081] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640111] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640173] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640208] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640238] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640270] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640302] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640333] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640365] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640395] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640461] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640503] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640534] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.640915] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641245] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641276] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641309] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641361] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641394] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641527] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641575] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 783.641607] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 784.188348] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 784.188457] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 784.188554] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 784.188650] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 784.290592] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 784.290703] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 784.290810] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:21 GLK-2-GLKRVP1DDR405 kernel: [ 784.290980] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.389346] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.389436] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.389525] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.389658] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.389754] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.389846] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.391024] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.391105] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.391189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.391841] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.391922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.393244] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.393340] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.393938] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.394055] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.394152] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.394246] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.400178] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.411017] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.411137] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.411314] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.661042] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.661186] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.661337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.661435] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.661604] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.868327] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.868454] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.879879] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.879984] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.880087] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.932063] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.932253] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.932410] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.932546] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.932684] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.932812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.932913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.933007] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.933104] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.933199] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.933309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.933418] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.933514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.933608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.933702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.933800] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.933897] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.933991] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.934083] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.934184] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.934286] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.934389] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.934481] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.934571] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.934663] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.934806] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.934917] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.944804] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.949440] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.954017] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 784.958568] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114000] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114021] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114089] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114119] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114136] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114171] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114211] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114240] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114272] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114341] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114372] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114406] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114437] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114466] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114494] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114507] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114535] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114548] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114577] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114608] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114639] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114667] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114732] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114760] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114792] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114824] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114855] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114886] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114925] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.114991] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.115027] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.115059] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.115898] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.115925] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.116915] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.116952] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117371] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117402] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117436] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117490] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117521] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117646] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117684] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:22 GLK-2-GLKRVP1DDR405 kernel: [ 785.117716] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.564357] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.564466] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.564564] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.564660] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.666596] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.666707] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.666812] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.666998] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.767048] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.767148] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.767247] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.767354] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.767462] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.767566] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.768777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.768879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.768979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.769652] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.769746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.770711] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.770805] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.771404] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.771541] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.771637] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.771732] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.776152] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.788474] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.788561] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 785.788684] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 786.038417] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 786.038504] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 786.038565] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 786.304979] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 786.305066] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:23 GLK-2-GLKRVP1DDR405 kernel: [ 786.305127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 786.571403] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 786.571491] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 786.571552] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 786.837872] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 786.838066] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 786.838221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 786.838322] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 786.838497] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.044336] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.044464] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.055896] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.056000] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.056104] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.107046] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.107148] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.107240] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.107391] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.107519] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.107648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.107749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.107848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.107942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.108036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.108179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.108283] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.108383] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.108481] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.108578] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.108683] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.108788] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.108895] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.108991] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.109098] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.109185] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.109275] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.109377] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.109470] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.109620] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.109735] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.110216] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.111653] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.111760] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.111847] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.112590] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.114035] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.114081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.114206] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.114300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.114345] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.114446] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.114565] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.114659] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.114756] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.114852] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.114946] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.115037] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.115130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.115221] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.115310] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.115352] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.115442] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.115484] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.115578] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.115668] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.115764] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.115854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.115944] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.116043] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.116157] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.116248] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.116342] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.116432] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.116525] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.116615] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.116715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.116808] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.116918] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.117012] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.118637] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.118773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.118805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.118835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.118864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.118894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.118923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.118955] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.118985] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.119016] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.119066] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.119096] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.119222] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.119256] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:24 GLK-2-GLKRVP1DDR405 kernel: [ 787.119288] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.740342] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.740450] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.740547] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.740642] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.842591] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.842704] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.842811] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.842990] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.941851] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.941949] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.942047] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.942154] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.942262] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.942366] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.943542] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.943634] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.943728] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.945036] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.945129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.946093] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.946188] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.946787] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.946920] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.947017] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.947112] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.952470] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.963847] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.963942] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 787.964075] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:25 GLK-2-GLKRVP1DDR405 kernel: [ 788.213918] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.463623] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.464053] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.464402] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:84:DP-1] Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.464546] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.464645] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.464749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.464852] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.464945] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.465043] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.465141] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.465236] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.465329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.465423] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.465515] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.465605] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.465648] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.465739] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.465780] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.465874] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.465966] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.466058] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.466149] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.466239] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.466338] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.466429] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.466520] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.466611] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.466702] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.466793] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.466883] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.466982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.467074] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.467183] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.467277] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.470541] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.470685] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.470963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.471067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.471169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.471262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.471357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.471453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.471551] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.471666] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.471831] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.480009] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.480059] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.480382] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.480442] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.480902] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.481546] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.482008] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.482050] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.482511] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.482574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.482619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.482667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.482709] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.483196] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.483339] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.483799] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.483841] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.484364] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.484432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.484481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.484525] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.485009] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.485152] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.485610] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.485653] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.486152] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.486200] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.486246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.486289] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.486785] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.487230] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.487695] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.487742] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.488249] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.488307] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.488697] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.488743] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.489190] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.489590] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.489659] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.506630] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.506701] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.506799] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 788.746702] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:26 GLK-2-GLKRVP1DDR405 kernel: [ 789.179733] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.429562] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.446115] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.446128] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476465] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476528] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476563] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476605] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476644] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476679] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476718] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476750] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476785] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476810] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476842] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476857] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476891] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476924] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476957] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.476989] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477021] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477062] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477095] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477130] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477165] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477200] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477235] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477270] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477343] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477389] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477423] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477464] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477496] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477536] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477568] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.477797] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.684336] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.684463] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.697734] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.697839] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.697942] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.749612] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.749713] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.749807] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.749958] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.750086] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.750220] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.750785] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.750890] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.750992] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.751132] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.758691] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.759229] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.759328] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.759476] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.759603] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.759699] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.759947] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.760081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.760233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.760337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.760436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.760534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.760634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.760733] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.760836] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.760928] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.761084] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.761178] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.761546] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.761656] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 789.761756] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 790.364346] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 790.364454] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 790.364551] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:27 GLK-2-GLKRVP1DDR405 kernel: [ 790.364645] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.466602] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.466714] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.466819] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.466988] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.565337] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.565437] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.565535] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.565687] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.565795] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.565900] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.567072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.567164] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.567259] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.567920] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.568012] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.569113] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.569250] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.569706] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.569822] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.569920] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.570016] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.576477] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.576560] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.576624] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.586759] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.586854] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.587071] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.587170] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.587685] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.588379] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.588891] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.588969] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.589472] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.589576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.589661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.589746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.589825] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.590361] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.590539] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.591039] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.591726] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.592696] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.592780] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.593310] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.593382] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.593452] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.593517] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.594039] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.594500] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.594972] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.595814] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.596559] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.596627] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.597158] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.597235] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.597590] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.597619] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.598060] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.598251] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.598295] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.615285] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.615357] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.615527] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.615837] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.616470] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.616540] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.616990] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.617054] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.633514] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.633621] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.633763] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.633896] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.633989] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.634121] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.634264] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.634352] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.634469] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.745424] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.745720] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.745891] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.750420] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.768170] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.772120] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.772275] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.772339] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.772807] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.772826] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.986520] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.987116] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 790.987164] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.011856] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.012399] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.012585] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.017297] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.037591] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.041846] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.041929] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.041991] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.042008] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.042082] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.042114] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.042357] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.248359] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.248481] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.254511] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.254615] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.254715] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.306054] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.306153] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.306244] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.306385] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.306491] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.306613] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.306735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.306831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.306924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.307016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.307107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.307198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.307293] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.307389] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.307482] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.307577] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.307672] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.307764] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.307885] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.307992] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.316798] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.316911] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.317083] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.317204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.317292] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.317447] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.333868] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.334402] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.334496] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.334638] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.334767] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.334893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.334990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.335086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.335178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.335269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.335361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.335456] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.335551] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.335645] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.335736] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.350143] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.350270] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.350445] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.350583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.350683] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.350832] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.350935] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.351069] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.367591] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.367748] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.367880] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.368007] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.368191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.368295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.368397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.368494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.368591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.368687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.368787] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.368888] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.368982] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.369073] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.369174] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.369275] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.369385] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.369482] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.369579] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.369672] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:28 GLK-2-GLKRVP1DDR405 kernel: [ 791.369762] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.376992] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383078] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383110] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383207] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383283] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383406] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383455] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383507] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383618] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383668] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383722] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383774] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383822] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383870] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383893] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383941] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.383964] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384014] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384063] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384137] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384189] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384280] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384310] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384344] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384378] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384409] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384441] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384472] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384535] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384575] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.384607] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.385493] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.385522] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.386462] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.386496] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.386643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.386674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.386705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.386734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.386764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.386795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.386824] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.386856] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.386884] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.386937] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.386969] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.387091] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.387128] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.387158] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.932359] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.932468] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.932566] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 791.932661] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.034598] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.034711] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.034818] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.034998] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.133694] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.133794] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.133893] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.134000] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.134108] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.134212] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.135390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.135482] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.135574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.136499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.136594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.137261] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.137352] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.138314] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.138409] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.138952] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.139037] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.139089] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.139141] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.148301] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.155981] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.156076] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:29 GLK-2-GLKRVP1DDR405 kernel: [ 792.156260] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.406103] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.406248] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.406404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.406506] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.406682] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.612352] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.612477] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.623235] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.623338] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.623439] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.673752] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.673853] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.673947] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.674100] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.674229] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.674356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.674458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.674556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.674650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.674744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.674837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.674934] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.675030] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.675124] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.675216] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.675314] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.675422] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.675524] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.675616] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.675706] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.675799] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.675949] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.676061] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.676776] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.676887] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.676994] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.678033] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.684681] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.689305] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.693888] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.698460] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.731856] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.731877] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.731947] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.731977] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.731994] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732105] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732139] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732174] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732242] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732273] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732309] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732341] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732371] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732403] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732418] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732448] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732462] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732493] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732523] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732556] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732586] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732616] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732652] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732683] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732716] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732748] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732779] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732812] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732842] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732909] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732950] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.732982] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.733842] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.733870] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.734817] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.734851] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.734994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.735025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.735057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.735085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.735116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.735146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.735176] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.735208] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.735236] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.735289] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.735320] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.735443] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.735480] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 792.735514] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 793.308214] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 793.308323] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 793.308420] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:30 GLK-2-GLKRVP1DDR405 kernel: [ 793.308515] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.410396] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.410507] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.410608] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.410752] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.511065] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.511165] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.511263] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.511371] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.511478] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.511583] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.513217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.513311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.513405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.514082] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.514174] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.515148] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.515244] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.515850] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.515976] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.516073] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.516817] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.516866] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.532925] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.533029] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.533171] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.782998] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.783085] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 793.783146] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 794.049416] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 794.049502] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 794.049563] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 794.315867] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 794.315955] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:31 GLK-2-GLKRVP1DDR405 kernel: [ 794.316016] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.582197] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.582388] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.582540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.582641] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.582812] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.788349] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.788474] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.799905] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.800009] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.800111] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.852307] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.852406] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.852500] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.852652] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.852779] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.852906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.853003] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.853099] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.853195] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.853309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.853419] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.853518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.853613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.853706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.853800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.853897] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.853993] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.854085] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.854177] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.854277] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.854383] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.854486] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.854579] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.854669] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.854761] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.854907] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.855017] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.855492] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.858567] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.858654] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.859242] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.859674] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.859720] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.859848] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.859943] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.859991] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.860092] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.860238] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.860332] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.860435] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.860532] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.860630] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.860724] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.860821] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.860913] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.861006] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.861049] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.861143] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.861184] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.861282] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.861378] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.861472] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.861563] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.861655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.861755] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.861847] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.861939] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.862032] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.862122] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.862215] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.862305] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.862404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.862496] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.862605] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.862699] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.863334] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.863683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.863740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.863801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.863862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.863917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.863973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.864030] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.864109] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.864169] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.864253] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.864313] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.864476] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.864545] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:32 GLK-2-GLKRVP1DDR405 kernel: [ 794.864607] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.484383] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.484491] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.484587] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.484682] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.586600] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.586712] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.586819] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.587004] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.687227] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.687325] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.687424] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.687532] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.687640] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.687744] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.688937] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.689031] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.689129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.689830] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.689936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.690908] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.691009] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.691609] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.691740] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.691838] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.691933] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.696515] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.708617] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.708712] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.708845] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 795.958732] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:33 GLK-2-GLKRVP1DDR405 kernel: [ 796.208524] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.458321] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.708116] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.708599] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.708653] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:84:DP-1] Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.708798] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.708898] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.709001] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.709102] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.709194] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.709292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.709390] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.709486] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.709579] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.709672] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.709763] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.709853] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.709896] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.709987] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.710029] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.710123] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.710214] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.710304] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.710394] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.710484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.710583] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.710673] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.710764] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.710854] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.710943] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.711033] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.711122] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.711219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.711312] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.711419] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.711514] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.715395] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.715538] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.715838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.715942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.716043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.716161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.716260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.716354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.716451] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.716791] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.716888] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.724361] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.724411] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.724554] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.724612] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.725067] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.725706] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.726165] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.726205] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.726663] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.726719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.726762] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.726805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.726845] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.727328] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.727468] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.727917] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.727957] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.728452] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.728535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.728577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.728618] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.729095] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.729234] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.729685] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.729725] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.730237] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.730278] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.730317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.730356] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.730835] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.731270] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.731718] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.731756] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.732249] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.732291] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.732652] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.732691] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.733144] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.733520] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.733601] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.750541] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.750580] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.750653] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 796.991082] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:34 GLK-2-GLKRVP1DDR405 kernel: [ 797.241007] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.490675] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.507392] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.507410] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544229] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544281] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544313] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544346] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544380] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544411] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544441] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544470] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544499] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544519] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544548] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544561] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544591] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544620] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544649] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544720] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544756] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544784] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544814] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544845] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544875] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544905] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544935] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.544999] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.545039] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.545068] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.545103] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.545131] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.545164] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.545192] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.545433] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.752348] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.752475] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.758528] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.758633] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.758738] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.810331] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.810432] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.810526] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.810677] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.810805] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.810939] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.811571] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.811676] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.811779] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.811940] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.819440] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.819980] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.820079] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.820316] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.820446] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.820543] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.820811] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.820946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.821044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.821144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.821239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.821335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.821428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.821528] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.821622] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.821718] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.821866] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.821963] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.822308] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.822417] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:35 GLK-2-GLKRVP1DDR405 kernel: [ 797.822517] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.428335] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.428444] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.428541] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.428636] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.530497] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.530610] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.530715] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.530896] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.631088] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.631189] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.631287] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.631439] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.631546] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.631650] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.632838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.632931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.633029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.633701] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.633792] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.634762] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.634856] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.635313] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.635426] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.635524] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.635618] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.640323] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.640430] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.640524] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.652351] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.652388] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.652534] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.652581] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.653032] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.653663] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.654118] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.654148] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.654601] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.654648] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.654679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.654718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.654748] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.655227] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.655356] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.655793] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.656432] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.656901] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.656952] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.657462] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.657516] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.657568] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.657626] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.658124] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.658568] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.659029] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.659873] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.660358] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.660409] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.660917] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.660976] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.661355] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.661405] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.661871] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.662084] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.662154] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.679136] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.679209] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.679378] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.679690] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.680304] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.680375] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.680446] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.680507] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.697368] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.697475] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.697616] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.697750] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.697843] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.697975] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.698113] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.698201] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.698322] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.808250] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.808478] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.808625] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.812671] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.831212] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.835192] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.835274] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.835336] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.835850] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 798.835870] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.052323] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.052927] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.052975] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.077089] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.077402] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.077577] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.081942] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.102724] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.106819] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.106898] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.106959] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.106974] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.107047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.107079] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.107311] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.312332] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.312455] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.318479] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.318583] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.318682] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.369783] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.369882] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.369973] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.370112] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.370218] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.370340] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.370462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.370559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.370652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.370744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.370835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.370925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.371020] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.371116] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.371209] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.371316] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.371576] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.371681] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.371781] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:36 GLK-2-GLKRVP1DDR405 kernel: [ 799.371899] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.380652] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.380777] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.380962] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.381097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.381198] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.381368] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.398018] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.398552] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.398646] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.398789] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.398915] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.399040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.399135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.399231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.399323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.399413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.399504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.399599] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.399694] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.399788] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.399880] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.413983] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.414107] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.414280] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.414417] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.414517] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.414666] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.414770] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.414904] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.431517] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.431675] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.431807] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.431935] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.432065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.432218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.432321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.432420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.432517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.432614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.432736] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.432832] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.432927] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.433018] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.433124] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.433222] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.433332] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.433430] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.433528] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.433620] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.433711] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.440966] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447051] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447084] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447181] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447258] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447315] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447380] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447430] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447481] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447538] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447593] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447644] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447699] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447750] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447799] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447847] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447869] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447917] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447939] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.447989] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448040] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448107] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448160] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448216] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448254] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448284] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448319] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448353] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448388] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448422] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448456] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448490] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448522] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448563] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.448593] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.449457] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.449484] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.450430] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.450464] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.450607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.450639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.450670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.450698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.450728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.450759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.450788] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.450820] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.450849] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.450901] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.450933] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.451054] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.451091] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.451122] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.996340] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.996449] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.996546] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 799.996642] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.098596] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.098709] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.098816] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.098996] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.197844] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.197944] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.198042] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.198150] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.198257] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.198362] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.199549] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.199641] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.199737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.200637] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.200732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.201710] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.201806] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.202413] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.202540] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.202637] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.202733] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.208353] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.219438] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.219502] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:37 GLK-2-GLKRVP1DDR405 kernel: [ 800.219602] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.469561] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.469706] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.469860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.469961] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.470135] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.676328] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.676454] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.687878] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.687982] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.688085] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.739079] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.739181] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.739275] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.739426] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.739556] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.739682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.739782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.739881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.739975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.740067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.740222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.740325] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.740426] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.740526] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.740620] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.740725] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.740831] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.740936] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.741024] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.741129] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.741217] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.741320] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.741408] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.741503] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.741646] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.741757] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.742552] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.749343] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.754091] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.758757] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.764759] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.796717] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.796738] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.796807] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.796837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.796853] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.796887] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.796927] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.796956] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.796987] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797055] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797085] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797150] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797179] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797206] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797220] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797248] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797261] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797290] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797318] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797348] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797404] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797440] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797467] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797498] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797531] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797562] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797592] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797622] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797685] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797721] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.797753] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.798591] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.798618] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.799582] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.799616] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.799760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.799792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.799823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.799851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.799882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.799913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.799941] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.799973] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.800002] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.800055] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.800112] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.800997] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.801034] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 800.801065] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 801.372356] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 801.372465] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 801.372563] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:38 GLK-2-GLKRVP1DDR405 kernel: [ 801.372658] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.474529] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.474641] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.474744] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.474896] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.573534] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.573634] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.573733] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.573840] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.573947] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.574051] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.575230] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.575322] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.575416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.576096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.576235] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.576940] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.577043] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.578028] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.578126] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.578736] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.578859] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.578957] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.579053] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.584175] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.595826] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.595943] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.596097] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.845851] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.845939] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 801.846000] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 802.112274] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 802.112361] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:39 GLK-2-GLKRVP1DDR405 kernel: [ 802.112422] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.378741] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.378828] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.378886] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.645190] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.645382] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.645538] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.645641] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.645817] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.852341] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.852468] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.863915] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.864021] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.864182] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.916207] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.916308] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.916402] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.916554] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.916682] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.916810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.916910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.917008] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.917104] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.917198] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.917316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.917424] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.917519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.917613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.917706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.917803] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.917898] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.917991] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.918083] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.918182] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.918289] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.918392] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.918484] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.918575] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.918667] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.918816] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.918927] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.919396] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.921312] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.921402] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.922260] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.922661] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.922706] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.922832] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.922928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.922975] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.923076] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.923197] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.923290] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.923392] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.923488] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.923585] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.923679] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.923775] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.923866] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.923959] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.924002] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.924096] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.924169] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.924271] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.924369] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.924467] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.924562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.924659] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.924765] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.924861] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.924960] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.925056] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.925147] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.925238] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.925328] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.925426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.925522] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.925628] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.925722] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.926356] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.926554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.926650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.926744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.926834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.926927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.927018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.927112] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.927208] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.927301] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.927447] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.927543] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.927747] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.927854] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:40 GLK-2-GLKRVP1DDR405 kernel: [ 802.927952] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.548343] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.548451] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.548548] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.548643] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.650600] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.650712] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.650817] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.650993] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.749787] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.749887] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.749985] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.750092] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.750199] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.750304] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.751481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.751573] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.751668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.752933] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.753026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.753991] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.754086] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.754684] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.754822] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.754918] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.755013] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.760334] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.771733] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.771827] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 803.771958] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 804.021697] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:41 GLK-2-GLKRVP1DDR405 kernel: [ 804.271607] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.538048] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.787846] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.788365] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.788418] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:84:DP-1] Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.788569] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.788670] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.788777] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.788879] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.788975] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.789073] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.789174] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.789270] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.789366] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.789461] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.789555] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.789645] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.789691] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.789782] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.789826] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.789921] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.790015] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.790107] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.790200] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.790291] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.790393] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.790485] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.790579] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.790669] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.790762] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.790852] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.790945] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.791043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.791137] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.791246] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.791340] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.795244] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.795394] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.795649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.795752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.795852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.795947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.796041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.796185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.796287] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.796434] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.796529] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.804198] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.804253] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.804402] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.804464] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.804979] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.805627] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.806093] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.806137] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.806602] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.806668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.806716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.806771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.806817] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.807306] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.807451] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.807907] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.807951] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.808454] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.808517] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.808564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.808610] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.809098] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.809242] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.809699] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.809743] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.810267] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.810355] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.810404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.810449] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.810929] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.811362] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.811830] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.811866] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.812412] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.812499] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.812867] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.812904] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.813351] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.813749] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.813807] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.830804] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.830881] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 804.830995] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 805.070927] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:42 GLK-2-GLKRVP1DDR405 kernel: [ 805.320580] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.570509] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.603833] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.603857] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.636419] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.636497] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.636542] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.636595] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.636645] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.636690] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.636738] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.636781] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.636822] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.636852] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.636895] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.636914] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.636958] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637001] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637045] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637087] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637129] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637181] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637224] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637269] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637314] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637358] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637403] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637447] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637496] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637542] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637599] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637643] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637694] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637736] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637786] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.637828] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.638075] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.844356] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.844484] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.855383] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.855489] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.855592] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.907335] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.907437] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.907531] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.907683] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.907810] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.907943] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.908443] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.908548] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.908652] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.908815] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.913947] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.914486] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.914584] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.914731] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.914860] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.914956] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.915213] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.915347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.915445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.915543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.915636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.915730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.915823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.915917] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.916011] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.916103] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.916416] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.916513] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.916868] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.916974] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:43 GLK-2-GLKRVP1DDR405 kernel: [ 805.917074] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.524405] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.524514] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.524611] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.524707] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.626596] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.626707] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.626812] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.626997] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.727095] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.727195] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.727293] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.727446] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.727552] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.727655] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.728839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.728934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.729031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.729705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.729794] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.730445] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.730537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.731496] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.731591] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.732043] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.732184] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.732287] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.732389] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.732808] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.732923] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.733019] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.749116] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.749224] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.749457] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.749566] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.750083] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.750775] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.751289] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.751377] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.751889] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.752004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.752099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.752256] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.752356] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.752921] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.753118] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.753627] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.754373] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.754889] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.754978] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.755554] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.755659] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.755761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.755850] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.756393] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.756873] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.757372] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.758220] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.758746] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.758826] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.759370] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.759464] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.759891] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.759972] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.760478] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.760770] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.760879] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.777872] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.777978] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.778186] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.778575] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.779192] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.779290] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.779391] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.779481] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.796313] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.796435] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.796600] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.796757] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.796858] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.796993] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.797135] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.797246] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.797375] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.898845] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.898975] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.899093] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.902404] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.921497] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.925434] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.925512] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.925573] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.926072] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 806.926092] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.132371] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.133003] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.133052] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.157499] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.157840] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.158019] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.162541] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.184385] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.188665] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.188749] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.188822] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.188838] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.188912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.188947] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:44 GLK-2-GLKRVP1DDR405 kernel: [ 807.189188] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.396326] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.396449] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.399740] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.399843] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.399944] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.451070] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.451169] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.451260] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.451400] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.451506] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.451628] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.451751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.451848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.451942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.452034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.452184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.452281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.452381] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.452480] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.452579] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.452689] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.452784] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.452880] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.452973] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.453168] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.462808] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.462920] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.463092] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.463213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.463302] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.463460] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.480261] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.480793] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.480886] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.481028] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.481154] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.481279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.481375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.481470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.481563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.481654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.481745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.481841] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.481937] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.482031] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.482123] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.496248] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.496374] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.496542] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.496680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.496781] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.496931] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.497035] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.497171] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.514112] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.514270] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.514398] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.514525] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.514659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.514757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.514854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.514948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.515040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.515132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.515231] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.515325] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.515417] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.515508] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.515611] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.515706] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.515818] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.523227] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.528662] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.528692] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.528780] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.528824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.528848] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.528898] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.528956] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529000] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529046] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529096] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529145] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529190] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529238] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529284] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529326] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529368] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529388] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529431] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529450] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529494] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529537] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529582] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529625] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529667] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529718] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529761] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529806] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529851] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529896] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529942] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.529986] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530081] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530133] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530183] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530583] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530897] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530929] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.530957] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.531010] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.531038] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.531175] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.531212] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 807.531242] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.060401] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.060508] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.060605] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.060701] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.162599] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.162710] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.162816] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.162996] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.261124] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.261224] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.261323] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.261475] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.261583] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.261686] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.262885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.262976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.263069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.263745] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.263835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.264858] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.264955] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.265556] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.265672] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.265771] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.265865] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.272167] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.282604] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.282681] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:45 GLK-2-GLKRVP1DDR405 kernel: [ 808.282812] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.532571] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.532717] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.532870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.532971] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.533145] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.740349] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.740477] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.749241] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.749345] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.749450] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.800382] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.800480] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.800572] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.800728] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.800855] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.800983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.801083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.801181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.801275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.801368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.801461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.801559] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.801655] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.801749] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.801842] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.801942] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.802050] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.802213] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.802305] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.802411] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.802454] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.802557] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.802717] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.811593] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.819358] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.823395] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.827435] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.932397] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.932430] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.932464] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.932497] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982051] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982072] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982133] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982163] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982179] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982217] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982256] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982285] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982317] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982353] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982387] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982417] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982483] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982512] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982540] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982553] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982581] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982594] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982623] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982652] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982682] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982711] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982739] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982776] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982804] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982836] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982867] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982897] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982925] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982958] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.982990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.983022] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.983059] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.983092] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.983938] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.983965] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.984956] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.984991] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.985722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.985754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.985786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.985814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.985845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.985876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.985905] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.985938] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.985967] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.986021] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.986052] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.986176] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.986214] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:46 GLK-2-GLKRVP1DDR405 kernel: [ 808.986245] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.436353] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.436461] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.436559] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.436654] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.538606] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.538718] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.538824] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.538993] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.637769] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.637867] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.637966] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.638073] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.638181] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.638285] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.639463] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.639556] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.639651] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.640405] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.640488] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.641453] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.641541] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.642124] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.642241] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.642327] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.642411] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.648181] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.659184] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.659302] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.659457] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.909237] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.909324] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 809.909385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 810.175689] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 810.175776] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:47 GLK-2-GLKRVP1DDR405 kernel: [ 810.175838] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.442024] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.442110] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.442168] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.708587] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.708780] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.708938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.709040] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.709214] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.916350] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.916477] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.925243] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.925348] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.925452] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.976203] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.976301] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.976392] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.976544] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.976673] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.976801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.976903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.977002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.977097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.977190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.977284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.977381] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.977477] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.977570] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.977662] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.977761] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.977869] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.977970] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.978062] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.978150] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.978246] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.978342] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.978438] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.978544] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.978655] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.978800] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.978911] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.979377] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.981311] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.981355] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.982199] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.982502] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.982525] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.982588] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.982635] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.982658] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.982709] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.982769] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.982816] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.982865] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.982913] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.982960] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983098] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983143] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983164] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983209] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983230] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983277] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983323] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983368] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983413] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983458] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983507] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983552] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983597] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983642] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983687] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983732] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983777] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983871] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983927] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.983974] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986066] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986515] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986563] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986611] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986683] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986732] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986879] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986938] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:48 GLK-2-GLKRVP1DDR405 kernel: [ 810.986987] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.612344] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.612453] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.612549] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.612644] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.714592] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.714704] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.714810] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.714980] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.813781] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.813881] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.813979] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.814086] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.814195] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.814299] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.815485] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.815577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.815671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.816501] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.816598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.817578] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.817673] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.818272] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.818406] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.818504] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.818599] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.824251] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.835338] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.835426] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 811.835549] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.085390] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.085922] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.085974] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:84:DP-1] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.086116] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.086215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.086319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.086422] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.086514] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.086612] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.086711] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.086805] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.086897] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.086990] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.087080] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.087169] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.087212] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.087303] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.087345] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.087439] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.087530] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.087621] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.087711] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.087800] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.087900] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.087991] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.088082] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.088233] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.088329] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.088423] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.088519] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.088623] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.088721] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.088833] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.088932] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.089757] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.089902] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.090119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.090225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.090325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.090420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.090519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.090620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.090720] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.090887] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.090990] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.101737] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.101780] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.101920] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.101972] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.102427] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.103096] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.103557] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.103592] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.104048] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.104279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.104317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.104360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.104397] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.104879] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.105013] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.105478] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.105513] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.106030] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.106099] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.106134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.106168] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.106643] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.106777] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.107226] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.107260] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.107751] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.107789] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.107826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.107861] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.108343] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.108779] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.109229] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.109264] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.109757] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.109800] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.110206] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.110241] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.110719] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.111069] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.111157] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.128154] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.128210] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.128301] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:49 GLK-2-GLKRVP1DDR405 kernel: [ 812.368495] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.184500] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.201038] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.201052] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232265] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232326] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232363] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232402] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232441] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232478] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232513] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232548] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232582] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232605] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232639] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232655] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232691] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232725] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232760] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232795] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232829] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232868] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232902] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232937] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.232971] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.233005] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.233040] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.233073] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.233113] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.233148] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.233196] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.233232] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.233273] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.233308] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.233350] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.233384] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:46:50 GLK-2-GLKRVP1DDR405 kernel: [ 813.233611] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.440343] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.440471] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.451906] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.452011] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.452115] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.503035] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.503137] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.503231] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.503385] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.503512] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.503644] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.504985] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.505092] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.505195] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.505354] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.513784] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.514320] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.514416] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.514561] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.514692] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.514788] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.515040] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.515174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.515271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.515369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.515463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.515556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.515648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.515743] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.515837] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.515930] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.516075] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.516233] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.516907] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.517006] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 813.517098] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.140339] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.140447] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.140544] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.140640] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.242601] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.242713] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.242819] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.242995] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.340993] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.341093] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.341192] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.341345] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.341452] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.341555] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.342738] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.342830] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.342922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.343605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.343693] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.344668] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.344761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.345731] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.345826] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.346284] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.346398] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.346497] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.346593] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.352266] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.352326] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.352370] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.363313] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.363366] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.363531] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.363591] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.364057] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.364876] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.365347] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.365389] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.365856] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.365918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.365964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.366015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.366057] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.366551] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.366692] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.367145] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.367812] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.368298] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.368362] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.368884] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.368951] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.369016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.369078] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.369597] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.370053] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.370525] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.371372] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.371871] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.371932] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.372455] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.372528] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.372927] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.372988] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.373467] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.373705] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:46:51 GLK-2-GLKRVP1DDR405 kernel: [ 814.373790] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.390745] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.390817] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.390987] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.391298] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.391883] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.391949] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.392018] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.392078] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.408941] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.409052] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.409204] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.409337] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.409428] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.409548] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.409690] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.409780] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.409896] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.516986] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.517267] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.517428] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.521146] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.537855] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.541829] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.541906] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.541971] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.542476] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.542498] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.763062] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.763734] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.763781] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.787596] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.787733] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.787856] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.791119] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.810791] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.814863] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.814945] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.815006] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.815023] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.815099] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.815133] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 814.815360] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.020340] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.020463] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.031909] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.032013] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.032114] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.083083] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.083182] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.083273] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.083413] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.083520] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.083641] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.083765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.083861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.083955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.084045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.084192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.084284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.084384] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.084479] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.084572] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.084680] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.084955] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.085063] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.085165] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.085316] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.092228] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.092355] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.092541] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.092677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.092778] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.092951] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.109621] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.110153] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.110247] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.110389] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.110516] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.110682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.110778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.110874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.110966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.111056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.111146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.111241] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.111337] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.111431] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.111522] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.125492] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.125619] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.125792] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.125927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.126025] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.126169] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.126269] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.126401] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.144336] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.144491] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.144622] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.144748] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.144881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.144977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.145074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.145167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.145259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.145351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.145450] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.145544] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.145688] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.145780] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.145880] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.145976] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.146086] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.146180] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.146276] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.146366] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.146455] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.156863] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160520] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160542] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160610] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160639] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160656] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160692] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160731] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160760] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160790] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160826] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160859] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160888] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160922] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160953] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.160981] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161009] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161022] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161050] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161063] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161092] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161120] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161150] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161206] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161242] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161270] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161301] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161333] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161364] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161394] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161425] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161487] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161523] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.161554] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.162398] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.162425] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.163386] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.163419] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.163564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.163596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.163626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.163654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.163684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.163714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.163743] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.163775] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.163803] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.163856] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.163885] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.164009] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.164061] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:52 GLK-2-GLKRVP1DDR405 kernel: [ 815.164112] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.708346] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.708454] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.708551] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.708646] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.810540] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.810652] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.810758] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.810918] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.909792] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.909889] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.909988] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.910095] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.910203] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.910308] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.911484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.911576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.911670] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.912530] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.912624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.913595] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.913690] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.914290] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.914423] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.914519] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.914613] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.920167] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.931376] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.931484] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 815.931626] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 816.181412] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 816.181560] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 816.181713] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 816.181814] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:53 GLK-2-GLKRVP1DDR405 kernel: [ 816.181987] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.388344] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.388471] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.399391] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.399496] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.399599] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.450157] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.450259] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.450353] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.450505] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.450635] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.450763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.450864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.450963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.451056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.451149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.451242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.451339] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.451435] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.451529] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.451621] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.451721] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.451828] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.451929] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.452021] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.452111] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.452269] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.453238] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.453339] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.453438] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.453570] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.454289] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.454401] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.462681] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.467323] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.471903] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.476666] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632144] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632164] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632233] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632264] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632281] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632318] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632358] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632389] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632421] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632456] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632489] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632519] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632554] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632585] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632613] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632642] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632654] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632683] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632696] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632725] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632754] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632785] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632813] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632841] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632877] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632906] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632937] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.632969] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.633000] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.633031] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.633062] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.633094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.633126] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.633162] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.633194] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.634033] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.634060] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635022] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635056] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635384] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635416] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635445] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635498] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635527] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635651] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635688] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 816.635719] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.084350] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.084459] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.084556] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.084652] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.186604] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.186717] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.186824] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.187000] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.286941] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.287039] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.287138] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.287245] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.287353] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.287457] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.288682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.288785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.288885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.289592] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.289695] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.290693] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.290782] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.291368] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.291482] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.291570] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.291656] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.296156] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.308459] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.308577] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:54 GLK-2-GLKRVP1DDR405 kernel: [ 817.308730] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 817.558486] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 817.558574] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 817.558636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 817.824889] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 817.824975] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 817.825032] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 818.091371] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 818.091459] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 818.091521] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 818.357712] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 818.357906] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 818.358059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 818.358161] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:55 GLK-2-GLKRVP1DDR405 kernel: [ 818.358334] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.564351] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.564477] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.575959] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.576065] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.576209] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.628127] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.628279] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.628371] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.628524] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.628652] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.628781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.628882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.628981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.629078] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.629174] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.629270] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.629379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.629488] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.629583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.629677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.629774] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.629870] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.629964] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.630056] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.630155] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.630262] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.630364] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.630459] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.630549] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.630638] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.630799] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.630898] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.631321] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.631350] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.633212] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.633295] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.634185] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.634538] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.634578] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.634689] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.634774] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.634816] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.634906] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.635014] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.635097] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.635188] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.635275] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.635360] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.635443] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.635528] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.635609] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.635692] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.635730] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.635813] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.635850] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.635936] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.636018] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.636102] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.636212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.636297] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.636391] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.636477] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.636564] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.636648] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.636732] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.636819] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.636905] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.636997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.637085] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.637183] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.637266] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.637934] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.638128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.638221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.638309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.638391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.638475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.638561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.638646] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.638732] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.638817] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.638942] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.639025] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.639218] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.639314] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 818.639403] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 819.260355] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 819.260463] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 819.260560] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 819.260656] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 819.362603] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 819.362716] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 819.362817] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:56 GLK-2-GLKRVP1DDR405 kernel: [ 819.362982] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.462300] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.462400] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.462498] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.462605] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.462713] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.462816] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.464001] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.464092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.464237] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.465550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.465640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.466304] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.466394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.467362] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.467456] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.468061] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.468617] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.468713] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.468811] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.469068] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.469179] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.469273] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.485487] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.485582] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.485718] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.735589] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 819.985363] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.235161] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.251753] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.251768] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.284470] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.284534] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.284606] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.284670] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.284727] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.284792] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.284856] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.284915] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.284976] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285035] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285090] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285145] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285181] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285237] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285262] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285320] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285376] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285434] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285490] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285544] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285611] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285667] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285725] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285783] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285841] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285899] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.285957] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286018] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286106] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286164] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286222] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286281] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286337] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286392] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286447] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286502] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286528] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286583] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286608] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286666] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286722] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286777] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286832] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.286950] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287005] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287064] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287119] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287177] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287234] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287292] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287354] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287413] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287486] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287544] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287606] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287663] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287727] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.287783] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:46:57 GLK-2-GLKRVP1DDR405 kernel: [ 820.288056] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.496363] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.496491] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.502549] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.502655] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.502758] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.554772] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.554873] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.554968] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.555111] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.555222] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.555348] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.555448] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.555588] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.555713] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.555808] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.555902] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.556063] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.556563] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.556812] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.556945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.557043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.557144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.557240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.557337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.557431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.557529] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.557629] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.557726] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.557867] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.557962] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.558309] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.558414] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 820.558512] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 821.180344] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 821.180451] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 821.180546] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 821.180640] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 821.282595] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 821.282707] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 821.282813] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:46:58 GLK-2-GLKRVP1DDR405 kernel: [ 821.282982] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.383422] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.383523] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.383621] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.383773] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.383880] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.383983] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.385183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.385284] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.385382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.386059] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.386151] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.387125] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.387221] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.387680] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.387795] [drm:intel_edp_backlight_on [i915]] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.387893] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.387987] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.392564] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.392685] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.392784] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.404683] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.404746] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.404905] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.404975] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.405450] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.406104] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.406582] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.406632] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.407110] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.407182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.407236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.407301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.407352] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.407876] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.408047] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.409346] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.409417] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.409952] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.410031] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.410108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.410179] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.410704] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.411171] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.411656] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.412376] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.412879] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.412952] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.413488] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.413575] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.413993] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.414065] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.414553] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.414844] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.414975] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.415101] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.415176] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.415347] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.415665] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.416258] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.416344] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.416430] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.416510] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.433256] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.433330] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.433433] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.433531] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.433589] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.433675] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.433772] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.433831] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.433915] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.548249] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.548403] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.548478] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.550757] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.568452] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.572430] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.572568] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.572628] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.573127] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.573147] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.787845] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.788562] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.788613] Setting dangerous option enable_psr - tainting kernel Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.812090] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.812244] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.812326] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.814668] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.833278] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.837264] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.837343] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.837404] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.837419] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.837492] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.837524] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 821.837748] [drm:intel_edp_backlight_off [i915]] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.044337] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.044459] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.055893] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.055997] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.056098] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.108252] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.108350] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.108440] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.108580] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.108688] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.108810] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.108931] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.109025] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.109118] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.109225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.109333] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.109431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.109523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.109616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.109706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.109797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.109892] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.109987] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.110080] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.110187] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.116485] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.116606] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.116785] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.116917] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.117015] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.117182] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.134136] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.134671] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.134764] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.134907] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.135033] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.135159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.135255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.135351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.135442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.135533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.135623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.135718] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.135813] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.135907] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.135998] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.149924] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.150050] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.150212] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.150347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.150446] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.150584] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.150687] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.150824] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.167079] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.167238] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.167369] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.167497] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.167629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.167725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.167823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.167916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.168008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.168098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.168268] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.168367] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.168465] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.168562] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.168666] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.168759] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.168876] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.168972] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.169065] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.169156] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.169253] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.178262] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182181] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182204] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182276] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182307] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182325] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182404] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182436] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182469] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182507] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182542] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182574] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182610] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182673] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182703] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182717] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182748] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182761] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182793] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182824] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182856] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182916] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182955] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.182985] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.183018] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.183051] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.183084] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.183116] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.183149] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.183183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.183216] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.183255] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.183288] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.184163] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.184195] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185131] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185167] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185509] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185543] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185574] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185629] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185660] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185787] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185826] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:46:59 GLK-2-GLKRVP1DDR405 kernel: [ 822.185859] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.716396] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.716506] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.716603] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.716698] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.818588] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.818699] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.818805] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.818980] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.919002] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.919102] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.919200] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.919308] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.919415] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.919518] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.921165] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.921258] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.921351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.922030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.922119] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.922774] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.922865] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.923828] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.923922] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.924601] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.924720] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.924817] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.924913] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.925015] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.941531] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.941628] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 822.941768] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 823.191701] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 823.191846] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 823.192004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 823.192105] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:00 GLK-2-GLKRVP1DDR405 kernel: [ 823.192335] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.400345] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.400469] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.409206] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.409310] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.409413] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.461099] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.461200] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.461294] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.461446] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.461574] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.461701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.461802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.461901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.461995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.462088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.462181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.462277] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.462373] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.462469] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.462586] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.462697] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.462794] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.462888] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.462979] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.463080] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.463188] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.463289] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.463382] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.463471] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.463564] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.463711] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.463822] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.474480] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.480651] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.485231] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.489781] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645104] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645195] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645225] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645242] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645279] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645319] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645348] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645379] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645415] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645449] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645478] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645513] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645544] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645572] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645600] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645613] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645641] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645653] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645683] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645711] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645742] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645798] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645835] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645863] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645894] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645926] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645957] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.645988] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.646018] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.646050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.646083] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.646120] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.646154] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.647002] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.647029] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.647987] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.648020] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.648872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.648905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.648936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.648965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.648996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.649026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.649055] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.649088] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.649117] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.649170] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.649201] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.649325] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.649362] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 823.649393] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.092346] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.092454] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.092552] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.092647] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.194610] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.194723] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.194828] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.195004] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.293781] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.293881] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.293979] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.294088] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.294195] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.294300] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.295507] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.295607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.295703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.296732] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.296827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.297796] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.297892] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.298490] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.298623] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.298722] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.298816] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.304158] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.315533] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.315620] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:01 GLK-2-GLKRVP1DDR405 kernel: [ 824.315744] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 824.565611] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 824.565697] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 824.565758] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 824.832063] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 824.832241] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 824.832302] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 825.098507] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 825.098592] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 825.098652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 825.364962] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 825.365164] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 825.365315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 825.365418] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:02 GLK-2-GLKRVP1DDR405 kernel: [ 825.365592] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.572345] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.572469] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.581237] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.581342] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.581446] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.632340] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.632438] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.632530] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.632680] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.632809] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.632934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.633035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.633132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.633226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.633319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.633412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.633508] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.633604] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.633698] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.633790] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.633887] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.633994] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.634095] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.634190] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.634286] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.634382] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.634478] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.634581] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.634689] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.634779] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.634933] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.635032] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.635455] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.635484] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.637399] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.637476] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.638316] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.638702] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.638742] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.638854] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.638939] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.638981] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.639072] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.639179] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.639262] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.639351] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.639437] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.639523] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.639605] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.639689] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.639770] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.639851] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.639889] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.639972] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.640009] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.640095] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.640211] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.640298] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.640384] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.640467] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.640558] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.640644] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.640728] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.640814] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.640898] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.640983] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.641066] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.641152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.641235] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.641331] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.641415] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.642952] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.643137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.643222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.643305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.643388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.643470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.643552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.643636] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.643723] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.643807] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.643933] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.644019] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.644223] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.644269] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 825.644312] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 826.268398] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 826.268507] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 826.268605] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 826.268701] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 826.370606] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 826.370719] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 826.370826] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:03 GLK-2-GLKRVP1DDR405 kernel: [ 826.370998] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.471263] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.471361] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.471459] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.471567] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.471676] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.471783] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.472978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.473073] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.473167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.473855] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.473945] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.474610] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.474702] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.475676] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.475772] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.476392] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.476536] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.476637] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.476732] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.476938] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.476998] [drm:intel_fbc_enable [i915]] reserved 21012480 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.477046] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.493323] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.493383] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.493479] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.743522] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 826.993114] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.243096] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.259698] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.259715] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.281688] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.281772] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.281863] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.281946] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282019] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282102] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282183] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282259] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282338] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282413] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282486] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282557] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282601] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282674] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282707] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282782] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282854] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.282929] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.283001] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.283073] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.283158] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.283229] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.283305] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.283380] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.283455] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.283529] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.283603] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.283682] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.283794] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.283869] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.283946] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284022] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284095] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284281] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284356] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284393] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284471] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284507] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284587] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284663] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284738] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284894] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.284976] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.285050] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.285128] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.285205] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.285282] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.285360] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.285439] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.286053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.286139] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.286242] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.286319] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.286400] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.286478] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.286562] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.286639] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:47:04 GLK-2-GLKRVP1DDR405 kernel: [ 827.286904] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.492352] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.492481] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.509383] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.509488] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.509591] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.561236] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.561337] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.561432] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.561579] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.561691] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.561815] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.561915] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.562054] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.562276] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.562481] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.562584] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.562691] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.562794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.562891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.562994] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.563093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.563200] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.563295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.563395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.563493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.563595] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.563695] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.563794] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.563940] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.564037] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.564476] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.564584] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 827.564683] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 828.188353] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 828.188461] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 828.188559] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 828.188655] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 828.290607] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 828.290720] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 828.290827] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:05 GLK-2-GLKRVP1DDR405 kernel: [ 828.290997] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.391303] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.391401] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.391498] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.391653] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.391762] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.391866] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.393102] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.393195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.393290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.393974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.394063] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.394724] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.394816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.395782] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.395877] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.396357] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.396481] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.396579] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.396677] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.396936] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.397051] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.397147] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.413375] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.413428] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.413576] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.413636] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.414101] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.414746] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.415213] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.415255] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.415732] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.415795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.415841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.415893] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.415936] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.416459] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.416624] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.417105] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.417164] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.417680] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.417762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.417827] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.417886] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.418388] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.418546] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.419027] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.419085] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.419601] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.419667] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.419732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.419791] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.420303] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.420763] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.421238] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.421297] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.421825] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.421893] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.422291] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.422351] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.422825] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.423082] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.423176] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.423287] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.423350] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.423506] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.423802] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.424368] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.424439] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.424539] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.424602] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.441385] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.441457] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.441560] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.441670] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.441731] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.441828] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.441926] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.441996] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.442081] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.556245] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.556404] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.556476] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.558761] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.576437] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.580395] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.580533] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.580595] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.581092] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.581112] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.796636] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.797320] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.797367] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.821416] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.821747] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.821920] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.826309] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.844443] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.852239] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.852378] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.852441] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.852457] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.852529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.852561] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 828.852792] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.060363] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.060485] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.063810] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.063914] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.064016] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.115034] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.115132] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.115223] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.115366] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.115472] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.115594] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.115718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.115815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.115909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.116001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.116093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.116236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.116338] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.116828] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.116934] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.117020] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.117115] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.117210] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.117303] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.117458] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.124628] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.124750] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.124912] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.125043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.125141] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.125299] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.141743] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.142278] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.142372] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.142514] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.142641] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.142766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.142861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.142957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.143049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.143140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.143230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.143324] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.143419] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.143512] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.143604] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.158062] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.158188] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.158360] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.158497] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.158598] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.158748] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.158852] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.158986] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.175049] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.175205] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.175336] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.175463] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.175596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.175694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.175791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.175884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.175976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.176065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.176230] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.176329] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.176427] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.176525] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.176630] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.176723] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.176841] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.176936] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.177029] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.177121] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.177217] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.188005] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.191797] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.191819] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.191887] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.191916] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.191933] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.191967] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192006] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192034] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192094] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192166] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192199] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192296] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192324] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192341] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192372] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192386] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192417] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192447] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192477] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192506] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192537] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192574] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192604] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192637] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192668] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192700] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192732] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192764] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192832] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192873] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.192904] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.193775] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.193802] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.194744] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.194778] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.194921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.194952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.194983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.195011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.195042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.195072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.195100] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.195132] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.195163] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.195217] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.195249] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.195370] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.195407] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:06 GLK-2-GLKRVP1DDR405 kernel: [ 829.195437] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.724394] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.724503] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.724600] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.724695] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.826527] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.826639] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.826745] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.826910] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.926396] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.926496] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.926594] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.926702] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.926810] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.926915] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.928091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.928254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.928357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.929650] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.929742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.930706] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.930802] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.931400] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.931535] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.931635] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.931730] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.936145] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.948462] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.948558] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 829.948691] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 830.198518] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 830.198663] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 830.198817] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 830.198918] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:07 GLK-2-GLKRVP1DDR405 kernel: [ 830.199093] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.404368] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.404492] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.415934] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.416040] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.416200] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.467149] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.467251] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.467345] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.467497] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.467626] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.467752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.467852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.467947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.468040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.468188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.468286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.468390] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.468493] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.468591] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.468688] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.468792] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.468899] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.468989] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.469096] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.469184] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.469288] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.469376] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.469464] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.469556] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.469670] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.469816] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.469925] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.476897] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.482609] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.487584] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.492156] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.525571] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.525592] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.525661] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.525692] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.525709] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.525746] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.525785] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.525815] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.525845] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.525879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.525912] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.525942] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.525975] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526007] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526035] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526063] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526076] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526104] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526117] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526146] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526174] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526205] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526233] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526261] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526297] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526326] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526357] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526390] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526421] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526452] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526482] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526545] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526581] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.526613] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.527450] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.527477] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.528468] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.528505] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529444] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529476] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529505] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529559] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529588] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529714] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529752] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 830.529783] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.100394] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.100502] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.100600] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.100695] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.202601] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.202712] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.202818] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.202997] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.302671] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.302769] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.302867] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.302975] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.303083] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.303188] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.304653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.304747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.304840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.305508] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.305600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.306563] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.306658] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.307258] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.307391] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.307490] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.307586] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.312150] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.324354] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.324459] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:08 GLK-2-GLKRVP1DDR405 kernel: [ 831.324600] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 831.574376] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 831.574463] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 831.574525] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 831.840827] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 831.840914] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 831.840975] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 832.107167] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 832.107254] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 832.107315] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 832.373723] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 832.373917] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 832.374070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 832.374171] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:09 GLK-2-GLKRVP1DDR405 kernel: [ 832.374344] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.580367] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.580493] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.591966] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.592071] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.592235] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.644340] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.644438] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.644529] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.644681] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.644808] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.644934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.645035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.645129] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.645235] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.645332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.645425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.645526] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.645618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.645720] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.645813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.645916] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.646396] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.646498] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.646593] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.646695] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.646809] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.646914] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.647007] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.647100] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.647193] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.647336] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.647449] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.647911] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.647952] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.648821] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.648890] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.649754] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650005] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650040] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650142] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650224] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650259] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650434] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650508] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650664] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650740] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650888] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.650962] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651033] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651067] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651140] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651172] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651247] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651321] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651394] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651466] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651538] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651617] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651689] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651762] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651834] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651909] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.651981] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.652053] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.652156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.652237] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.652327] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.652407] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.653386] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.653568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.653654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.653730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.653806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.653884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.653957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.654033] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.654112] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.654192] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.654305] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.654384] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.654563] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.654633] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 832.654666] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 833.276342] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 833.276450] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 833.276546] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:10 GLK-2-GLKRVP1DDR405 kernel: [ 833.276642] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.378612] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.378724] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.378831] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.379010] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.479298] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.479397] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.479496] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.479603] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.479711] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.479815] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.481003] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.481095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.481190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.481872] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.481961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.482614] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.482705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.483666] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.483761] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.484372] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.484494] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.484594] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.484691] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.484948] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.485062] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.485157] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.501457] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.501575] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.501730] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 833.751450] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 834.001258] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:11 GLK-2-GLKRVP1DDR405 kernel: [ 834.251029] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.500845] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.750459] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.767201] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.767213] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.784712] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.784789] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.784872] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.784949] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785017] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785167] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785237] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785310] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785379] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785445] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785510] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785550] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785617] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785647] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785716] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785783] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785851] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785917] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.785982] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786060] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786125] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786194] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786262] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786328] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786395] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786461] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786532] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786634] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786701] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786769] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786839] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786905] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.786970] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787035] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787099] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787130] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787195] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787225] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787293] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787358] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787424] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787554] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787625] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787689] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787757] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787822] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787889] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.787957] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.788024] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.788136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.788212] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.788303] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.788376] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.788452] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.788524] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.788604] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.788673] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 834.792175] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.000352] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.000478] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.017390] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.017494] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.017597] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.070107] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.070208] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.070303] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.070434] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.070539] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.070639] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.070761] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.070871] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.070974] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.071096] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.071196] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.071336] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.071603] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.071843] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.071975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.072072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.072216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.072316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.072415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.072515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.072612] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.072713] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.072814] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.072961] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.073055] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.073407] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.073511] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:12 GLK-2-GLKRVP1DDR405 kernel: [ 835.073612] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.708337] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.708446] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.708542] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.708636] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.810500] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.810613] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.810720] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.810896] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.911000] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.911100] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.911198] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.911351] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.911458] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.911561] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.913217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.913310] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.913405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.914067] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.914159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.915119] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.915213] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.915664] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.915778] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.915876] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.915970] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.920485] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.920557] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.920613] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.932533] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.932594] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.932752] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.932821] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.933343] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.934012] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.934506] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.934577] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.935069] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.935161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.935236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.935311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.935382] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.935900] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.936070] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.936604] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.936679] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.937215] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.937310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.937388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.937459] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.937969] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.938140] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.938626] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.938695] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.939228] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.939307] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.939382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.939453] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.939976] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.940445] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.940938] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.941009] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.941542] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.941620] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.942028] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.942100] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.942591] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.942864] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.942966] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.943091] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.943166] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.943336] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.943652] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.944184] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.944267] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.944352] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.944428] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.961208] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.961257] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.961332] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.961404] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.961444] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.961509] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.961580] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.961618] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 835.961681] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.075434] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.075717] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.075858] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.079627] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.098582] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.102537] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.102615] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.102676] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.103177] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.103198] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.316031] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.316789] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.316836] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.340360] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.340582] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.340727] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.344554] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.363900] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.367955] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.372032] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.372215] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.372233] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.372308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.372340] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:13 GLK-2-GLKRVP1DDR405 kernel: [ 836.372569] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.580343] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.580466] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.582241] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.582346] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.582446] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.633742] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.633841] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.633932] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.634076] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.634183] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.634305] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.634427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.634522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.634614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.634704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.634795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.634885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.634979] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.635073] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.635166] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.635260] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.635355] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.635448] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.635568] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.635675] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.644521] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.644644] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.644828] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.644965] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.645065] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.645239] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.661786] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.662394] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.662488] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.662632] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.662760] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.662885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.662981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.663076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.663168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.663259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.663350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.663445] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.663541] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.663635] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.663727] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.677841] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.677968] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.678142] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.678279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.678379] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.678528] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.678632] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.678769] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.695058] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.695218] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.695349] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.695475] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.695608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.695706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.695803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.695895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.695987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.696076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.696278] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.696372] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.696470] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.696564] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.696671] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.696766] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.696881] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.706269] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711244] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711265] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711333] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711362] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711377] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711412] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711452] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711480] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711512] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711547] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711580] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711609] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711642] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711673] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711701] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711731] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711743] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711771] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711784] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711813] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711843] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711871] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711899] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711926] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711962] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.711989] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712020] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712052] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712108] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712142] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712175] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712249] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712291] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712325] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712711] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.712977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.713008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.713038] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.713069] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.713102] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.713154] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.713184] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.713319] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.713353] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 836.713385] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 837.244357] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 837.244467] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 837.244565] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 837.244661] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 837.346606] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 837.346718] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 837.346824] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:14 GLK-2-GLKRVP1DDR405 kernel: [ 837.347002] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.445047] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.445148] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.445246] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.445400] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.445507] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.445611] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.446858] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.446959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.447060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.447782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.447872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.449275] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.449367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.450334] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.450431] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.451031] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.451148] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.451247] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.451341] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.456160] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.468104] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.468247] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.468410] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.718158] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.718302] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.718455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.718557] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.718729] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.924380] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.924535] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.935971] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.936075] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.936251] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.987276] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.987378] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.987472] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.987626] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.987755] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.987883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.987984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.988082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.988236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.988331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.988427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.988525] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.988623] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.988721] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.988816] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.988918] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.989029] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.989130] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.989229] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.989328] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.989462] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.989551] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.989641] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.989734] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.989829] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.989971] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 837.990082] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.000488] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.006462] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.011020] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.016655] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.047831] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.047851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.047921] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.047951] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.047969] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048004] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048060] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048103] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048136] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048173] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048209] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048241] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048306] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048336] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048368] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048382] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048413] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048427] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048458] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048489] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048521] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048583] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048619] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048649] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048682] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048712] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048745] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048776] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048809] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048843] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048876] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048917] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.048948] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.049816] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.049844] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.050787] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.050820] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.050963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.050994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.051023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.051051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.051082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.051113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.051142] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.051174] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.051202] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.051256] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.051287] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.051409] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.051447] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:15 GLK-2-GLKRVP1DDR405 kernel: [ 838.051478] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.620359] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.620468] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.620567] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.620663] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.722596] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.722708] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.722814] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.722979] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.822836] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.822936] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.823033] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.823140] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.823244] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.823348] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.824546] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.824647] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.824749] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.825428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.825518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.826173] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.826263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.827168] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.827220] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.827761] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.827829] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.827884] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.827936] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.832302] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.844759] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.844846] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 838.844971] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 839.094896] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 839.094982] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 839.095041] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 839.361307] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 839.361392] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:16 GLK-2-GLKRVP1DDR405 kernel: [ 839.361453] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 839.627648] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 839.627735] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 839.627797] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 839.894210] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 839.894403] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 839.894559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 839.894659] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 839.894833] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.100347] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.100475] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.111953] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.112058] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.112229] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.163042] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.163143] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.163237] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.163393] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.163520] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.163646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.163746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.163844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.163937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.164030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.164183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.164282] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.164383] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.164476] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.164574] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.164675] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.164785] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.164887] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.164983] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.165085] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.165184] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.165283] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.165390] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.165498] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.165591] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.165751] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.165850] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.166263] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.166293] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.167121] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.167198] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.168051] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.169416] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.169455] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.169565] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.169649] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.169688] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.169778] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.169883] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.169965] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.170085] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.170171] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.170255] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.170336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.170419] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.170499] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.170578] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.170616] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.170696] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.170733] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.170816] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.170897] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.170978] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.171058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.171142] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.171230] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.171311] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.171391] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.171471] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.171550] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.171630] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.171709] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.171795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.171877] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.171971] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.172054] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.172994] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.173182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.173270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.173354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.173439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.173522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.173604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.173689] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.173774] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.173861] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.173989] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.174074] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.174269] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.174364] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:17 GLK-2-GLKRVP1DDR405 kernel: [ 840.174451] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.796356] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.796464] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.796562] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.796658] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.898599] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.898711] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.898818] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.898992] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.996963] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.997063] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.997161] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.997269] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.997375] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.997479] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.998665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.998757] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.998852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.999540] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 840.999629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.001111] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.001203] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.002176] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.002271] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.002876] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.003004] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.003101] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.003195] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.008285] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.008340] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.008382] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.019997] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.020093] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.020273] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:18 GLK-2-GLKRVP1DDR405 kernel: [ 841.269821] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 841.519763] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 841.786204] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.035824] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.285798] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.319130] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.319151] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.337166] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.337260] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.337358] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.337449] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.337531] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.337622] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.337712] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.337796] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.337884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.337967] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.338047] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.338126] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.338173] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.338254] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.338291] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.338374] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.338456] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.338536] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.338616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.338695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.338787] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.338866] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.338950] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.339032] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.339113] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.339195] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.339276] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.339363] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.339486] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.339568] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.339652] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.339735] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.339815] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.339894] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.339973] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.340051] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.340155] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.340251] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.340300] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.340397] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.340491] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.340584] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.340677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.340770] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.340872] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.340968] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.341069] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.341163] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.341258] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.341354] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.341449] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.344167] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.344260] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.344375] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.344469] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.344569] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.344661] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.344763] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.344853] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:47:19 GLK-2-GLKRVP1DDR405 kernel: [ 842.345628] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.552331] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.552447] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.569315] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.569409] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.569500] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.620537] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.620636] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.620730] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.620871] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.620981] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.621105] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.621204] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.621344] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.621567] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.621805] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.621936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.622033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.622131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.622225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.622319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.622411] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.622518] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.622611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.622708] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.622812] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.622907] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.623016] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.623113] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.623264] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.623359] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.623712] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.623821] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 842.623924] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 843.228394] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 843.228501] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 843.228597] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 843.228692] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 843.330597] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 843.330709] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 843.330816] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:20 GLK-2-GLKRVP1DDR405 kernel: [ 843.330995] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.431095] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.431196] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.431293] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.431446] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.431553] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.431656] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.432834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.432928] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.433025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.433696] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.433785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.434435] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.434526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.435485] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.435580] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.436031] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.436218] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.436315] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.436411] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.436666] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.436781] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.436878] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.453118] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.453226] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.453438] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.453547] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.454063] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.454752] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.455266] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.455354] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.455869] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.455985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.456079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.456238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.456328] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.456890] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.457083] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.457599] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.457687] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.458236] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.458344] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.458435] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.458522] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.459053] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.459240] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.459736] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.460443] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.460961] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.461050] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.461598] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.461694] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.461787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.461876] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.462421] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.462847] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.463279] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.463912] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.464356] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.464398] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.464880] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.464929] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.465281] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.465310] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.465749] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.465943] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.466025] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.466114] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.466143] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.466259] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.466472] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.466990] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.467023] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.467058] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.467087] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.484025] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.484125] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.484219] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.484308] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.484373] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.484452] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.484541] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.484594] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.484670] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.590625] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.590739] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.590843] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.593564] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.611386] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.615319] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.615400] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.615462] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.615985] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.616004] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.836433] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.837167] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.837216] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.863147] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.863275] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.863337] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.865307] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.884366] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.888567] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.888648] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.888709] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.888822] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.888893] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.888925] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 843.889156] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.096341] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.096463] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.105200] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.105305] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.105405] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.156331] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.156428] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.156519] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.156659] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.156766] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.156888] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.157011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.157108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.157202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.157293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.157384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.157475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.157570] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.157665] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.157758] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.157865] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.158304] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.158411] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.158514] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.158683] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.167345] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.167458] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.167628] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.167750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.167840] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.167998] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.184240] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.184766] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.184860] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.185020] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.185150] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.185278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.185377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.185477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.185571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.185664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.185757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.185855] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.185950] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.186044] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.186136] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.200673] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.200799] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.200972] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.201107] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.201204] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.201351] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.201452] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.201582] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.217727] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.217882] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.218012] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.218138] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.218271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.218368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.218465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.218558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.218650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.218742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.218840] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.218935] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.219027] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.219118] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.219219] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.219314] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.219426] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.228571] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232231] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232252] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232320] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232350] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232368] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232448] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232481] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232513] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232548] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232580] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232612] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232644] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232707] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232736] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232750] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232780] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232795] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232826] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232856] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232888] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232918] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232947] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.232983] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233013] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233046] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233077] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233109] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233140] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233172] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233238] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233280] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233311] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233655] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.233981] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.234010] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.234039] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.234091] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.234122] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.234255] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.234293] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:21 GLK-2-GLKRVP1DDR405 kernel: [ 844.234323] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.764361] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.764468] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.764565] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.764661] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.866603] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.866715] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.866821] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.866997] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.967149] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.967249] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.967347] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.967500] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.967606] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.967710] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.968941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.969033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.969130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.969805] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.969896] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.970853] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.970937] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.971528] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.971633] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.971722] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.971806] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.976155] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.988567] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.988687] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 844.988860] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 845.238662] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 845.238806] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 845.238958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 845.239059] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:22 GLK-2-GLKRVP1DDR405 kernel: [ 845.239232] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.444342] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.444470] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.455937] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.456042] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.456202] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.507632] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.507734] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.507828] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.507979] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.508106] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.508723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.508826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.508926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.509016] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.509121] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.509216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.509310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.509413] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.509508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.509614] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.509713] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.510459] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.510543] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.510626] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.510716] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.510815] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.510958] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.511057] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.519412] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.527462] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.531488] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.536449] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.689816] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.689836] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.689905] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.689935] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.689950] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.689986] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690026] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690055] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690087] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690155] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690185] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690250] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690279] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690307] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690319] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690348] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690360] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690390] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690418] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690450] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690478] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690542] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690570] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690601] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690632] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690663] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690694] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690725] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690757] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690788] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690824] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.690859] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691208] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691529] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691561] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691589] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691643] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691671] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691807] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691842] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 845.691873] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.140393] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.140501] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.140597] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.140691] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.242600] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.242713] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.242820] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.242999] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.342690] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.342790] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.342888] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.343041] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.343149] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.343252] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.344834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.344927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.345023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.345701] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.345793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.346768] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.346862] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.347467] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.347585] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.347684] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.347778] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.352147] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.364461] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.364524] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:23 GLK-2-GLKRVP1DDR405 kernel: [ 846.364642] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:24 GLK-2-GLKRVP1DDR405 kernel: [ 846.614612] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:24 GLK-2-GLKRVP1DDR405 kernel: [ 846.614700] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:24 GLK-2-GLKRVP1DDR405 kernel: [ 846.614761] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:24 GLK-2-GLKRVP1DDR405 kernel: [ 846.881016] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:24 GLK-2-GLKRVP1DDR405 kernel: [ 846.881100] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:24 GLK-2-GLKRVP1DDR405 kernel: [ 846.881157] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:24 GLK-2-GLKRVP1DDR405 kernel: [ 847.147502] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:24 GLK-2-GLKRVP1DDR405 kernel: [ 847.147589] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:24 GLK-2-GLKRVP1DDR405 kernel: [ 847.147650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.413909] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.414085] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.414232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.414331] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.414496] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.620357] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.620484] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.631946] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.632052] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.632197] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.683087] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.683188] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.683282] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.683433] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.683561] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.683689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.683791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.683889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.683984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.684075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.684216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.684315] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.684416] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.684509] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.684607] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.684709] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.684817] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.684918] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.685011] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.685104] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.685196] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.685301] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.685389] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.685493] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.685540] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.685650] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.686118] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.686151] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.686386] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.686475] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.687323] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.687722] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.687767] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.687891] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.687986] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.688034] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.688151] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.688252] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.688371] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.688471] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.688575] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.688676] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.688773] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.688872] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.688969] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.689066] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.689162] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.689210] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.689306] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.689355] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.689461] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.689559] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.689658] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.689756] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.689850] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.689953] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.690051] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.690145] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.690236] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.690333] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.690423] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.690513] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.690612] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.690705] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.690812] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.690909] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.692374] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.692520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.692558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.692594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.692628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.692663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.692698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.692733] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.692772] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.692808] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.692867] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.692903] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.693037] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.693083] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 847.693120] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 848.316346] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 848.316455] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 848.316552] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:25 GLK-2-GLKRVP1DDR405 kernel: [ 848.316648] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.418597] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.418709] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.418815] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.418996] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.517333] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.517433] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.517532] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.517639] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.517746] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.517849] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.519035] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.519127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.519222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.519898] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.519990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.521302] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.521399] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.522004] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.522132] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.522229] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.522325] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.528538] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.528618] [drm:intel_fbc_enable [i915]] reserved 21012480 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.528679] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.539065] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.539139] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.539249] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 848.788951] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.038919] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.055526] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.055545] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.078608] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.078662] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.078699] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.078732] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.078760] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.078796] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.078830] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.078860] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.078894] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.078925] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.078952] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.078980] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079002] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079030] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079043] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079072] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079100] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079128] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079183] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079222] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079250] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079281] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079311] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079341] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079371] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079402] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079434] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079480] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079509] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079538] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079569] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079597] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079652] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079679] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079692] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079719] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079732] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079760] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079788] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079816] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079843] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079870] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079901] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079929] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079959] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.079987] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.080017] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.080062] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.080110] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.081423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.081453] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.081492] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.081523] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.081554] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.081584] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.081617] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.081647] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.081857] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.288365] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.288493] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.305388] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.305493] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.305598] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.357806] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.357907] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.358001] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.358144] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.358256] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.358379] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.358477] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.358568] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.358673] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.358778] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.358872] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.358976] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.359529] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.359781] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.359917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.360015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.360111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.360227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.360321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.360417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.360514] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.360611] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.360706] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.360858] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.360955] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.361484] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.361560] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:26 GLK-2-GLKRVP1DDR405 kernel: [ 849.361631] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 849.980346] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 849.980454] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 849.980551] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 849.980645] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.082605] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.082718] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.082823] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.082999] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.183093] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.183193] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.183291] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.183443] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.183550] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.183654] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.184882] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.184983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.185083] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.185763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.185853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.186504] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.186595] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.187540] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.187625] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.188051] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.188671] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.188752] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.188829] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.189064] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.189153] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.189228] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.205599] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.205707] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.205919] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.206028] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.206555] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.207244] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.207759] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.207847] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.208473] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.208604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.208705] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.208809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.208910] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.209460] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.209649] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.210157] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.210249] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.210799] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.210906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.210997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.211085] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.211621] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.211808] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.212333] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.212427] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.212990] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.213038] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.213086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.213131] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.213626] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.214067] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.214530] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.214574] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.215080] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.215132] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.215506] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.215551] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.216015] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.216257] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.216348] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.216480] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.216530] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.216679] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.216938] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.217465] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.217515] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.217569] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.217618] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.234524] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.234571] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.234643] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.234714] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.234752] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.234813] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.234886] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.234922] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.234994] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.344994] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.345080] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.345142] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.347264] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.364501] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.368478] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.368555] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.368616] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.369121] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:27 GLK-2-GLKRVP1DDR405 kernel: [ 850.369140] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.588715] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.589470] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.589518] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.614055] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.614429] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.614605] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.617670] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.635268] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.639342] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.639424] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.639497] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.639513] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.639589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.639623] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.639863] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.844365] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.844487] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.855934] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.856038] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.856193] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.907050] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.907148] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.907239] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.907381] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.907487] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.907609] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.907732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.907829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.907923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.908015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.908106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.908253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.908355] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.908782] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.908887] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.908990] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.909085] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.909182] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.909276] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.909435] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.917825] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.917920] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.918068] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.918169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.918243] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.918374] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.935177] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.935698] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.935782] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.935910] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.936026] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.936598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.936694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.936790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.936882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.936974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.937064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.937159] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.937254] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.937348] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.937440] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.951157] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.951282] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.951458] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.951595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.951692] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.951835] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.951936] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.952071] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.969289] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.969446] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.969578] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.969706] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.969838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.969936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.970033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.970126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.970219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.970311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.970411] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.970505] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.970598] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.970690] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.970791] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.970886] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.970999] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.980636] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.986725] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.986746] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.986815] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.986845] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.986861] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.986898] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.986937] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.986966] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.986997] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987031] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987064] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987094] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987127] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987158] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987186] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987214] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987227] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987255] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987267] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987296] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987324] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987352] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987380] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987407] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987443] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987471] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987502] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987532] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987563] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987593] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987624] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987686] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987723] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.987755] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988119] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988452] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988483] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988515] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988566] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988597] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988799] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988834] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:28 GLK-2-GLKRVP1DDR405 kernel: [ 850.988866] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.516356] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.516464] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.516562] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.516658] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.618596] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.618710] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.618816] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.618985] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.719177] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.719275] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.719374] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.719526] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.719634] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.719739] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.720959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.721053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.721152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.721905] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.721997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.722962] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.723057] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.723652] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.723770] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.723867] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.723962] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.728293] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.740737] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.740836] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.740989] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.990767] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.990911] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.991066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.991169] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 851.991343] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.196351] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.196479] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.207966] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.208070] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.208242] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.259094] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.259195] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.259289] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.259442] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.259569] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.259697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.259799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.259898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.259993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.260087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.260241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.260344] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.260445] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.260544] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.260644] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.260748] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.260853] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.260960] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.261057] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.261157] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.261258] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.261370] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.261479] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.261568] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.261661] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.261816] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.261913] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.271746] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.276734] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.282700] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:29 GLK-2-GLKRVP1DDR405 kernel: [ 852.287224] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441026] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441046] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441115] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441145] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441163] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441237] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441266] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441298] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441367] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441397] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441461] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441490] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441518] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441531] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441560] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441572] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441602] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441631] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441662] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441718] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441755] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441783] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441815] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441846] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441877] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441908] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441938] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.441970] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.442004] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.442041] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.442073] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.442912] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.442940] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.443903] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.443936] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.444094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.444133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.444167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.444199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.444233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.444267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.444299] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.444335] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.444370] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.444422] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.444452] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.445421] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.445458] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.445489] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.892378] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.892486] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.892583] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.892679] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.994594] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.994707] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.994814] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 852.994987] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.095461] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.095559] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.095657] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.095764] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.095872] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.095975] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.097378] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.097471] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.097566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.098232] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.098324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.099289] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.099384] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.099984] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.100119] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.100249] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.100352] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.100459] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.116941] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.117047] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.117200] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.367109] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.367196] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:30 GLK-2-GLKRVP1DDR405 kernel: [ 853.367257] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:31 GLK-2-GLKRVP1DDR405 kernel: [ 853.633558] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:31 GLK-2-GLKRVP1DDR405 kernel: [ 853.633646] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:31 GLK-2-GLKRVP1DDR405 kernel: [ 853.633707] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:31 GLK-2-GLKRVP1DDR405 kernel: [ 853.899926] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:31 GLK-2-GLKRVP1DDR405 kernel: [ 853.900011] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:31 GLK-2-GLKRVP1DDR405 kernel: [ 853.900119] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:31 GLK-2-GLKRVP1DDR405 kernel: [ 854.166469] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:31 GLK-2-GLKRVP1DDR405 kernel: [ 854.166664] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:31 GLK-2-GLKRVP1DDR405 kernel: [ 854.166820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:31 GLK-2-GLKRVP1DDR405 kernel: [ 854.166920] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:31 GLK-2-GLKRVP1DDR405 kernel: [ 854.167099] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:31 GLK-2-GLKRVP1DDR405 kernel: [ 854.372366] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:31 GLK-2-GLKRVP1DDR405 kernel: [ 854.372493] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.383965] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.384071] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.384236] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.436217] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.436317] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.436410] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.436562] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.436690] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.436817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.436919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.437017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.437114] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.437209] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.437305] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.437412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.437522] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.437617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.437710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.437807] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.437902] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.437994] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.438085] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.438185] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.438292] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.438394] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.438487] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.438577] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.438669] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.438833] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.438931] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.439356] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.439386] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.442695] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.442773] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.443348] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.443726] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.443765] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.443876] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.443960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.444000] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.444090] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.444220] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.444310] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.444403] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.444493] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.444580] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.444668] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.444755] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.444836] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.444916] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.444954] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.445039] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.445076] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.445163] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.445245] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.445328] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.445409] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.445494] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.445583] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.445667] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.445748] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.445831] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.445911] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.445994] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.446074] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.446164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.446247] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.446345] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.446429] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.447122] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.447404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.447497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.447584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.447666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.447749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.447831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.447917] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.448005] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.448093] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.448304] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.448388] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.448584] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.448680] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 854.448768] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.068368] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.068475] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.068574] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.068670] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.170614] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.170724] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.170830] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.171004] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.271213] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.271314] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.271412] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.271520] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.271628] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.271733] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.272926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.273019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.273117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.273790] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.273881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.274854] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.274948] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.275552] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.275683] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.275782] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.275876] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.280272] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.280339] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.280393] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.292569] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.292661] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:32 GLK-2-GLKRVP1DDR405 kernel: [ 855.292792] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.542650] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.792263] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.792742] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.792794] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:84:DP-1] Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.792936] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.793035] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.793138] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.793241] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.793334] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.793433] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.793531] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.793626] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.793719] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.793813] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.793904] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.793993] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.794036] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.794126] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.794167] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.794260] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.794351] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.794442] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.794533] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.794622] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.794721] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.794811] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.794903] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.794993] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.795083] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.795173] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.795263] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.795361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.795453] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.795561] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.795656] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.796245] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.796911] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.797133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.797239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.797341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.797436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.797531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.797626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.797725] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.797844] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.797942] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.808788] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.808834] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.808976] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.809030] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.809487] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.810124] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.810587] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.810623] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.811114] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.811167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.811205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.811249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.811286] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.811791] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.811927] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.812380] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.812422] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.812916] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.812967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.813003] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.813039] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.813515] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.813650] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.814102] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.814138] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.814631] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.814671] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.814710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.814746] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.815229] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.815662] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.816289] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.816338] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.816841] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.816893] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.817270] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.817316] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.817816] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.818179] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.818262] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.835278] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.835366] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 855.835491] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 856.075538] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:33 GLK-2-GLKRVP1DDR405 kernel: [ 856.325195] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.575132] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.591729] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.591743] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.610427] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.610550] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.610628] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.610712] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.610794] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.610870] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.610948] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611020] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611091] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611135] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611207] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611240] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611315] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611387] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611459] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611531] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611602] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611686] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611758] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611833] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611907] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.611981] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.612052] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.612186] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.613499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.613582] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.613683] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.613767] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.613853] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.613934] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.614024] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.614104] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.614421] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.820343] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.820469] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.826527] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.826632] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.826736] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.877810] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.877911] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.878005] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.878150] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.878259] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.878384] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.878514] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.879607] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.879718] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.879824] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.879986] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.887383] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.887922] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.888022] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.888245] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.888377] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.888474] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.888734] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.888869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.888967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.889067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.889162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.889258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.889351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.889450] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.889545] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.889641] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.889789] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.889885] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.890232] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.890341] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:34 GLK-2-GLKRVP1DDR405 kernel: [ 856.890441] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.500358] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.500467] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.500565] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.500659] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.602598] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.602710] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.602816] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.602994] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.701820] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.701920] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.702018] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.702172] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.702278] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.702383] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.703568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.703661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.703755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.704639] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.704733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.705707] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.705803] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.706263] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.706378] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.706476] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.706571] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.712293] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.712365] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.712424] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.723271] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.723338] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.723521] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.723595] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.724076] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.724778] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.725279] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.725349] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.725850] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.725946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.726021] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.726103] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.726174] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.726698] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.726870] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.727354] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.728035] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.728562] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.728637] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.729174] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.729268] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.729349] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.729421] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.729941] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.730409] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.730862] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.731704] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.732301] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.732352] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.732859] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.732918] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.733298] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.733348] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.733809] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.734023] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.734092] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.751046] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.751096] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.751242] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.751502] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.752059] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.752142] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.752197] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.752245] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.769098] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.769182] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.769296] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.769402] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.769475] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.769583] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.769691] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.769757] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.769862] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.888265] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.888496] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.888636] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.892350] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.909145] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.913102] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.913182] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.913247] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.913750] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 857.913769] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.123048] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.123828] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.123876] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.147476] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.147610] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.147733] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.150963] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.170644] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.174782] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.174863] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.174946] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.174963] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.175053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.175085] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:35 GLK-2-GLKRVP1DDR405 kernel: [ 858.175322] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.380350] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.380473] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.391913] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.392017] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.392118] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.444323] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.444422] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.444512] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.444653] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.444760] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.444918] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.445009] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.445115] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.445217] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.445339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.445442] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.445540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.445633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.445725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.445815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.445906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.446001] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.446096] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.446189] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.446296] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.452446] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.452572] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.452756] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.452891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.452991] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.453168] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.469775] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.470296] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.470380] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.470509] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.470625] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.470737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.470822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.470906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.470987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.471067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.471147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.471232] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.471316] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.471399] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.471481] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.485764] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.485889] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.486064] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.486203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.486303] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.486452] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.486555] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.486691] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.503591] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.503749] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.503881] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.504009] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.504201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.504304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.504408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.504505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.504601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.504693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.504837] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.504934] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.505027] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.505130] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.505230] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.505328] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.505443] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.514880] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519459] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519481] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519548] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519594] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519628] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519667] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519696] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519726] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519760] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519792] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519822] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519853] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519911] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519939] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519952] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519979] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.519992] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520021] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520049] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520107] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520169] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520207] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520237] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520274] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520308] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520342] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520375] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520409] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520481] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520519] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520549] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.520909] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521237] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521268] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521299] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521350] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521380] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521515] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521549] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 858.521582] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.068339] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.068446] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.068543] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.068639] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.170507] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.170618] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.170723] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.170881] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.271270] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.271370] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.271468] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.271622] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.271729] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.271833] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.273046] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.273139] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.273234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.273955] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.274044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.274698] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.274788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.275751] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.275846] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.276463] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.276583] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.276683] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.276780] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.276883] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.293420] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.293518] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:36 GLK-2-GLKRVP1DDR405 kernel: [ 859.293676] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.543596] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.543741] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.543899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.544001] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.544228] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.752340] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.752467] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.761239] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.761344] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.761449] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.812328] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.812427] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.812521] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.812673] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.812801] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.812928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.813028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.813125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.813218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.813311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.813403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.813499] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.813594] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.813686] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.813777] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.813877] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.813983] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.814138] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.814266] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.814306] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.814412] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.814513] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.814634] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.822200] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.826896] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.832919] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.837972] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.908412] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.908445] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.908479] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.908512] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991384] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991404] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991459] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991489] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991507] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991541] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991580] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991609] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991641] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991676] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991709] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991739] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991771] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991802] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991831] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991858] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991871] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991900] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991912] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991941] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.991970] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992000] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992028] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992083] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992119] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992149] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992182] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992213] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992245] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992277] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992309] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992343] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992375] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992414] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.992450] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.993311] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.993338] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994284] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994318] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994640] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994672] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994700] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994753] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994781] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994906] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994942] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:37 GLK-2-GLKRVP1DDR405 kernel: [ 859.994973] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.444398] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.444507] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.444604] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.444700] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.546591] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.546704] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.546811] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.546983] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.647040] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.647141] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.647239] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.647346] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.647454] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.647558] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.649214] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.649315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.649412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.650080] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.650173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.651137] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.651233] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.651834] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.651968] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.652065] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.652811] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.652917] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.668872] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.668967] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.669099] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.918980] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.919064] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 860.919125] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 861.185423] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 861.185509] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:38 GLK-2-GLKRVP1DDR405 kernel: [ 861.185570] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.451739] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.451825] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.451885] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.718292] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.718486] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.718646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.718747] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.718923] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.924367] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.924495] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.935965] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.936069] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.936226] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.987437] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.987538] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.987630] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.987786] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.987913] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.988039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.988247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.988347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.988441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.988536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.988632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.988730] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.988829] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.988925] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.989020] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.989124] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.989224] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.989323] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.989437] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.989550] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.989654] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.989747] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.989839] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.989933] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.990093] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.990191] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.990624] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.990654] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.990885] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.992581] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.992660] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.993481] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.993852] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.993891] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.994003] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.994086] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.994126] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.994215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.994319] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.994403] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.994490] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.994576] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.994660] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.994742] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.994825] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.994906] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.994985] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.995023] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.995103] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.995140] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.995223] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.995304] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.995384] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.995464] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.995543] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.995635] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.995715] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.995795] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.995875] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.995954] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.996033] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.996139] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.996226] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.996311] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.996407] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.996490] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.998075] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.998352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.998435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.998523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.998609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.998689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.998769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.998850] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.998933] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.999013] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.999139] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.999221] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.999414] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.999507] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:39 GLK-2-GLKRVP1DDR405 kernel: [ 861.999592] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.620346] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.620456] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.620554] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.620650] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.722593] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.722705] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.722811] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.722985] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.821749] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.821849] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.821948] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.822055] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.822162] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.822265] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.823441] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.823532] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.823627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.824350] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.824444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.825452] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.825559] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.826171] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.826320] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.826418] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.826516] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.832477] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.832560] [drm:intel_fbc_enable [i915]] reserved 21012480 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.832624] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.843241] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.843321] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 862.843437] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.093302] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.343093] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.343524] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.343576] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:84:DP-1] Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.343719] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.343818] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.343922] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.344023] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.344114] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.344283] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.344384] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.344484] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.344581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.344678] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.344772] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.344861] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.344910] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.345002] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.345044] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.345138] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.345230] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.345326] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.345416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.345505] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.345608] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.345699] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.345792] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.345882] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.345975] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.346065] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.346157] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.346255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.346350] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.346459] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.346553] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.350366] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.350516] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.350765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.350867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.350967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.351062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.351155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.351248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.351345] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.351456] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.351549] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.359405] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.359464] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.359621] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.359687] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.360269] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.360920] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.361395] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.361443] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.361915] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.361985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.362036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.362093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.362142] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.362633] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.362821] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.363294] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.363341] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.363841] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.363905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.363954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.364001] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.364489] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.364640] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.365101] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.365151] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.365651] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.365704] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.365755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.365853] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.366379] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.366809] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.367276] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.367309] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.367828] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.367895] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.368324] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.368404] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.368849] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.369229] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:47:40 GLK-2-GLKRVP1DDR405 kernel: [ 863.369300] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:41 GLK-2-GLKRVP1DDR405 kernel: [ 863.386293] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:41 GLK-2-GLKRVP1DDR405 kernel: [ 863.386365] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:41 GLK-2-GLKRVP1DDR405 kernel: [ 863.386474] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:41 GLK-2-GLKRVP1DDR405 kernel: [ 863.625989] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:41 GLK-2-GLKRVP1DDR405 kernel: [ 864.159075] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.408781] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.425454] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.425469] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.460467] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.460545] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.460592] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.460645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.460694] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.460739] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.460788] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.460831] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.460872] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.460902] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.460944] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.460964] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461008] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461050] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461094] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461178] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461230] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461273] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461318] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461363] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461407] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461452] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461496] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461545] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461591] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461648] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461692] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461743] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461785] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461835] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.461877] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.462124] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.668360] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.668488] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.677249] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.677352] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.677456] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.728670] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.728772] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.728866] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.729009] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.729122] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.729248] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.729381] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.730405] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.730517] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.730621] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.730777] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.737783] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.738322] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.738419] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.738566] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.738694] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.738791] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.739042] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.739176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.739273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.739371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.739465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.739558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.739650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.739744] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.739838] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.739930] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.740074] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.740206] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.740907] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.741017] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 864.741115] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 865.340394] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 865.340502] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 865.340600] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:42 GLK-2-GLKRVP1DDR405 kernel: [ 865.340697] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.442604] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.442716] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.442822] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.442988] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.543082] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.543182] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.543280] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.543432] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.543541] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.543646] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.544835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.544929] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.545028] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.545710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.545800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.546465] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.546558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.547522] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.547618] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.548076] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.548261] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.548356] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.548455] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.548715] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.548834] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.548929] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.565133] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.565192] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.565365] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.565431] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.565903] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.566553] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.567046] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.567110] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.567603] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.567692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.567763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.567838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.567903] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.568425] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.568594] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.569070] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.569745] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.570234] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.570298] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.570824] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.570897] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.570968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.571032] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.571549] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.572010] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.572493] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.573353] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.573859] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.573925] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.574452] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.574530] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.574933] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.575001] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.575485] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.575738] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.575828] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.592806] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.592856] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.593000] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.593253] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.593786] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.593828] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.593879] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.593922] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.610891] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.611002] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.611141] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.611273] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.611366] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.611497] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.611641] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.611729] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.611856] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.731432] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.731712] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.731853] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.735614] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.754602] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.758550] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.758627] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.758691] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.759206] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.759226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.964930] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.965709] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.965756] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.990250] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.990592] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.990784] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 865.995341] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.013511] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.019311] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.019474] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.019544] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.019561] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.019635] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.019668] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.019880] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.224350] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.224473] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.233201] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.233306] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.233406] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.285333] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.285432] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.285523] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.285664] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.285770] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.285891] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.286013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.286111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.286205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.286300] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.286394] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.286485] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.286595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.286702] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.286795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.286886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.286981] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.287077] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.287169] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.287276] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.294148] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.294270] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.294454] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.294589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.294689] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.294863] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.311575] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.312109] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.312246] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.312667] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.312795] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.312920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.313016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.313112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.313204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.313294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.313385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.313480] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.313576] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.313671] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.313763] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.327491] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.327614] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.327787] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.327924] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.328023] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.328223] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.328326] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.328459] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.344324] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.344477] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.344610] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.344736] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.344871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.344968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.345065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.345159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.345252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.345344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.345443] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.345537] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.345630] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.345721] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.345822] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.345917] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.346028] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.354254] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359237] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359263] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359345] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359385] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359407] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359453] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359505] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359544] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359585] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359630] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359673] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359713] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359757] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359799] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359837] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359874] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359892] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359931] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359948] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.359988] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360029] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360081] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360159] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360210] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360250] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360294] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360337] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360382] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360423] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360466] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360512] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360557] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360608] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.360647] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361031] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361437] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361480] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361522] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361588] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361630] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361777] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361827] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:43 GLK-2-GLKRVP1DDR405 kernel: [ 866.361868] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 866.908331] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 866.908441] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 866.908538] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 866.908634] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.010494] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.010605] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.010711] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.010888] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.109793] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.109894] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.109992] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.110145] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.110252] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.110357] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.111561] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.111654] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.111749] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.112681] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.112777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.113748] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.113844] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.114444] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.114564] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.114662] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.114758] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.120387] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.131503] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.131610] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:44 GLK-2-GLKRVP1DDR405 kernel: [ 867.131773] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.381562] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.381707] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.381861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.381963] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.382133] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.588351] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.588477] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.599953] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.600059] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.600204] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.651033] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.651134] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.651229] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.651384] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.651512] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.651639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.651740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.651838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.651931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.652025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.652117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.652284] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.652390] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.652487] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.652581] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.652686] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.652793] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.652895] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.652992] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.653089] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.653189] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.653289] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.653398] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.653491] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.653607] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.653751] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.653859] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.661720] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.667952] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.672684] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.677248] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.710611] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.710631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.710700] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.710730] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.710747] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.710782] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.710821] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.710850] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.710881] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.710918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.710951] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.710981] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711075] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711104] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711117] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711145] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711158] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711188] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711216] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711245] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711301] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711340] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711368] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711399] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711430] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711461] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711492] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711523] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711586] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711623] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.711655] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.712582] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.712612] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.713497] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.713531] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.713675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.713707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.713738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.713766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.713797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.713828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.713857] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.713889] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.713917] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.713971] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.713999] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.714124] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.714161] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 867.714192] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 868.284352] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 868.284460] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 868.284556] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:45 GLK-2-GLKRVP1DDR405 kernel: [ 868.284651] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.386604] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.386717] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.386823] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.386999] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.486381] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.486481] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.486580] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.486687] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.486794] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.486898] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.488071] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.488208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.488310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.489320] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.489410] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.490029] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.490096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.491024] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.491094] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.491659] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.491768] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.491839] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.491909] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.496144] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.508721] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.508826] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.508968] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.758778] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.758865] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 868.758927] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 869.025227] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 869.025314] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 869.025375] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 869.291671] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 869.291759] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:46 GLK-2-GLKRVP1DDR405 kernel: [ 869.291820] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.558124] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.558319] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.558476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.558577] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.558748] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.764342] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.764470] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.775944] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.776049] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.776221] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.827119] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.827220] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.827311] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.827464] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.827592] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.827719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.827821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.827919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.828014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.828107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.828255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.828359] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.828458] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.828557] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.828654] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.828757] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.828862] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.828970] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.829060] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.829166] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.829254] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.829343] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.829446] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.829539] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.829685] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.829797] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.830272] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.830304] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.830729] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.831625] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.831715] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.832674] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.834050] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.834095] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.834219] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.834312] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.834357] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.834458] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.834574] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.834667] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.834764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.834860] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.834953] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.835045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.835138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.835228] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.835317] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.835360] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.835451] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.835493] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.835587] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.835678] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.835773] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.835863] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.835953] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.836051] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.836167] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.836259] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.836353] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.836443] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.836535] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.836625] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.836725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.836817] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.836925] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.837019] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.837572] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.837729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.837761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.837791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.837822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.837852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.837881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.837911] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.837942] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.837972] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.838024] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.838054] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.838187] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.838221] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:47 GLK-2-GLKRVP1DDR405 kernel: [ 869.838254] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.460349] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.460457] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.460555] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.460651] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.562603] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.562714] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.562821] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.562993] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.661721] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.661821] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.661920] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.662027] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.662135] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.662239] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.663418] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.663510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.663603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.664482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.664575] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.665238] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.665330] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.666292] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.666386] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.666985] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.667121] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.667220] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.667314] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.672377] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.672499] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.672596] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.684048] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.684178] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.684299] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 870.934063] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:48 GLK-2-GLKRVP1DDR405 kernel: [ 871.183899] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.433695] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.683449] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.683892] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.683945] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:84:DP-1] Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.684093] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.684252] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.684361] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.684465] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.684561] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.684660] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.684759] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.684854] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.684952] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.685044] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.685135] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.685258] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.685302] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.685395] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.685437] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.685534] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.685626] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.685719] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.685810] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.685902] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.686003] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.686096] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.686187] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.686280] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.686371] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.686463] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.686553] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.686654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.686746] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.686856] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.686950] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.690772] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.690871] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.691066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.691126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.691186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.691241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.691295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.691349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.691406] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.691476] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.691531] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.699809] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.699872] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.700034] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.700146] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.700657] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.701312] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.701799] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.701863] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.702350] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.702439] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.702509] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.702581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.702647] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.703158] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.703323] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.703806] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.703871] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.704409] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.704509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.704585] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.704653] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.705161] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.705327] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.705809] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.705873] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.706394] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.706467] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.706537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.706603] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.707110] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.707604] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.708077] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.708194] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.708758] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.708852] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.709242] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.709298] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.709810] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.710233] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.710333] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.727358] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.727447] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.727572] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 871.966590] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:49 GLK-2-GLKRVP1DDR405 kernel: [ 872.216393] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.466013] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.482827] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.482849] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520249] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520302] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520333] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520366] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520399] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520430] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520489] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520518] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520538] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520567] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520581] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520611] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520653] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520681] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520712] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520739] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520775] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520803] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520833] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520863] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520893] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520923] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520953] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.520985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.521016] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.521056] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.521085] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.521120] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.521147] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.521181] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.521208] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.521448] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.728348] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.728476] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.734533] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.734639] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.734740] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.785809] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.785911] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.786005] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.786149] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.786260] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.786385] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.786516] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.787597] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.787706] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.787808] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.787935] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.794946] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.795483] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.795579] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.795725] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.795856] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.795952] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.796568] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.796880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.796979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.797077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.797171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.797265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.797358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.797455] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.797550] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.797642] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.797788] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.797885] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.798120] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.798191] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:50 GLK-2-GLKRVP1DDR405 kernel: [ 872.798256] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.404339] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.404447] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.404543] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.404637] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.506602] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.506715] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.506821] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.507001] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.607041] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.607141] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.607240] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.607393] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.607500] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.607604] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.608792] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.608885] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.608983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.609662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.609751] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.610412] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.610503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.611467] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.611561] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.612020] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.612166] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.612263] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.612357] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.612613] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.612728] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.612823] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.629096] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.629191] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.629408] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.629508] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.630030] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.630709] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.631218] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.631297] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.631806] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.631910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.631995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.632085] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.632216] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.632805] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.633000] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.633509] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.634250] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.634767] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.634857] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.635413] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.635520] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.635622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.635711] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.636375] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.636867] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.637369] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.638236] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.638771] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.638862] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.639411] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.639518] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.639955] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.640046] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.640616] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.640930] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.641052] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.657986] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.658073] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.658258] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.658603] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.659222] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.659300] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.659381] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.659457] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.676314] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.676437] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.676589] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.676747] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.676851] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.676982] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.677136] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.677233] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.677366] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.798691] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.798810] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.798914] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.801606] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.819512] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.823649] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.823737] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.823802] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.824557] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 873.824578] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.028933] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.029715] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.029764] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.054246] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.054431] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.054613] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.057688] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.074847] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.078881] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.078972] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.079036] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.079052] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.079127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.079159] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.079382] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.284341] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.284464] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.295916] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.296020] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.296122] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.347267] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.347366] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.347457] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.347597] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.347703] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.347824] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.347946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.348043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.348195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.348292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.348390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.348487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.348588] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.348689] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.348782] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.348896] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.348986] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.349092] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.349194] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.349359] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.359564] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.359691] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.359876] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.360010] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.360109] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.360429] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.374690] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.375214] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.375298] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.375428] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.375545] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.375661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.375747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.375834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.375916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.376000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.376082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:51 GLK-2-GLKRVP1DDR405 kernel: [ 874.376209] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.376423] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.376510] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.376595] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.392898] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.393011] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.393200] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.393338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.393438] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.393587] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.393691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.393828] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.409899] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.410054] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.410186] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.410313] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.410446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.410543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.410640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.410732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.410824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.410916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.411015] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.411109] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.411201] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.411292] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.411394] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.411488] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.411600] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.419234] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.424641] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.424670] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.424757] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.424802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.424826] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.424877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.424935] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.424979] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425025] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425075] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425124] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425169] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425263] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425305] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425347] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425367] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425410] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425430] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425474] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425517] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425561] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425645] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425696] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425739] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425784] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425830] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425875] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425921] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.425965] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426012] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426058] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426111] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426157] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426555] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426869] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426901] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426930] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.426983] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.427012] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.427148] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.427185] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.427216] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.972225] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.972333] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.972430] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 874.972526] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.074320] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.074431] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.074537] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.074697] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.175052] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.175151] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.175249] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.175402] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.175506] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.175612] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.176853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.176957] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.177058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.177730] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.177823] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.178787] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.178882] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.179480] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.179597] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.179695] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.179789] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.184171] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.196584] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.196690] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:52 GLK-2-GLKRVP1DDR405 kernel: [ 875.196850] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.446600] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.446744] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.446900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.447001] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.447179] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.652350] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.652475] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.663238] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.663342] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.663446] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.715029] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.715131] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.715225] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.715381] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.715509] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.715634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.715736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.715833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.715926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.716019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.716110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.716241] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.716338] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.716442] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.716575] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.716673] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.717146] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.717247] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.717341] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.717441] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.717554] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.717712] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.717823] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.726958] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.731845] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.735941] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.739992] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773456] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773477] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773546] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773593] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773628] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773667] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773697] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773728] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773797] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773827] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773861] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773921] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773951] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773964] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.773992] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774005] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774034] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774062] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774093] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774121] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774149] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774185] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774213] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774244] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774275] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774306] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774338] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774369] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774401] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774432] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774469] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774501] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774842] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.774984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.775015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.775046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.775074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.775105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.775136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.775165] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.775197] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.775226] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.775279] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.775308] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.775443] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.775478] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 875.775509] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 876.348366] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 876.348474] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 876.348571] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:53 GLK-2-GLKRVP1DDR405 kernel: [ 876.348666] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.450597] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.450709] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.450815] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.450996] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.551091] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.551191] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.551289] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.551442] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.551550] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.551654] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.552875] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.552967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.553065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.553738] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.553829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.554803] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.554896] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.555497] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.555613] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.555711] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.555805] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.560153] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.572519] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.572624] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.572785] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.822646] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.822732] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 876.822794] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 877.089099] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 877.089185] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 877.089245] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 877.355549] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 877.355635] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:54 GLK-2-GLKRVP1DDR405 kernel: [ 877.355696] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.621988] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.622180] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.622332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.622432] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.622608] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.828362] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.828488] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.839949] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.840054] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.840217] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.892388] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.892488] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.892582] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.892732] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.892860] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.892985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.893076] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.893184] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.893281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.893379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.893483] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.893578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.893683] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.893777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.893875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.893980] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.894459] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.894563] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.894660] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.894762] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.894877] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.894981] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.895075] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.895167] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.895261] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.895407] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.895521] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.895985] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.896019] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.897014] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.897077] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.897964] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.898209] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.898242] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.898335] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.898409] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.898442] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.898517] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.898604] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.898671] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.898744] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.898815] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.898884] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.898951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899019] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899085] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899151] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899181] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899248] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899277] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899346] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899413] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899480] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899683] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899749] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899815] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899881] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.899946] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.900011] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.900079] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.900172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.900240] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.900321] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.900390] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.901589] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.901763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.901840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.901911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.901981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.902048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.902117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.902188] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.902257] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.902326] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.902426] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.902496] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.902670] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.902751] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:55 GLK-2-GLKRVP1DDR405 kernel: [ 877.902824] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.524368] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.524478] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.524575] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.524671] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.626594] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.626705] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.626811] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.626994] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.727078] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.727176] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.727274] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.727382] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.727490] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.727596] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.728790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.728884] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.728982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.729671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.729760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.730426] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.730516] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.731490] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.731585] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.732203] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.732322] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.732426] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.732520] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.732782] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.732896] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.732991] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.749311] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.749426] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.749579] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 878.999291] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:56 GLK-2-GLKRVP1DDR405 kernel: [ 879.249107] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.515344] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.765312] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.765748] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.765802] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:84:DP-1] Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.765948] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.766048] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.766152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.766253] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.766346] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.766444] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.766542] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.766636] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.766728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.766821] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.766911] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.767000] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.767043] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.767134] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.767175] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.767269] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.767360] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.767450] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.767540] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.767630] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.767729] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.767819] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.767910] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.768000] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.768089] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.768247] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.768341] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.768445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.768541] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.768653] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.768752] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.772594] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.772738] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.772992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.773095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.773197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.773293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.773388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.773482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.773580] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.773693] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.773787] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.781652] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.781695] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.781836] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.781887] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.782337] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.782972] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.783427] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.783461] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.783964] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.784015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.784052] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.784130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.784174] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.784659] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.784794] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.785239] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.785273] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.785760] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.785809] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.785844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.785878] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.786347] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.786480] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.786962] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.787002] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.787494] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.787538] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.787582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.787622] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.788233] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.788673] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.789126] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.789166] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.789658] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.789706] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.790077] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.790118] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.790572] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.790932] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.791018] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.807983] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.808061] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 879.808404] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 880.048411] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:57 GLK-2-GLKRVP1DDR405 kernel: [ 880.298044] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.548006] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.581302] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.581324] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.602982] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603050] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603088] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603134] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603176] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603215] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603256] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603292] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603328] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603355] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603391] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603408] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603445] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603481] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603517] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603589] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603633] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603669] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603708] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603746] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603785] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603823] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603861] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603942] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.603992] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.604030] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.604094] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.604134] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.604183] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.604225] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.605222] [drm:intel_edp_backlight_off [i915]] Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.812369] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.812497] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.814423] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.814526] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.814629] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.865994] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.866095] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.866190] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.866335] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.866445] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.866571] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.866702] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.867595] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.867704] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.867807] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.867974] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.875468] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.876005] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.876102] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.876261] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.876389] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.876486] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.876747] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.876870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.876958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.877048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.877132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.877217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.877300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.877388] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.877472] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.877556] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.877687] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.877773] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.878062] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.878160] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:47:58 GLK-2-GLKRVP1DDR405 kernel: [ 880.878250] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.500393] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.500501] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.500597] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.500692] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.602606] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.602716] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.602824] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.603004] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.702863] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.702963] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.703061] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.703214] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.703321] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.703424] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.704918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.705010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.705105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.705780] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.705871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.706841] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.706936] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.707392] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.707507] [drm:intel_edp_backlight_on [i915]] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.707606] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.707700] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.716272] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.716351] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.716413] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.724377] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.724450] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.724636] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.724711] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.725195] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.725853] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.726339] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.726398] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.726883] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.726962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.727026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.727090] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.727150] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.727659] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.727817] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.728393] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.729069] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.729553] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.729617] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.730146] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.730218] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.730287] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.730351] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.730868] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.731329] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.731802] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.732560] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.733063] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.733129] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.733653] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.733731] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.734137] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.734203] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.734688] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.734941] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.735031] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.751987] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.752054] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.752385] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.752667] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.753248] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.753310] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.753373] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.753432] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.770295] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.770396] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.770526] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.770649] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.770744] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.770855] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.770971] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.771052] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.771159] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.912671] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.912826] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.912899] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.915169] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.932915] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.936886] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.936964] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.937028] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.937542] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 881.937561] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.157638] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.158457] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.158504] Setting dangerous option enable_psr - tainting kernel Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.182815] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.183039] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.183201] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.185929] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.203550] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.207559] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.207642] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.207705] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.207722] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.207797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.207831] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:47:59 GLK-2-GLKRVP1DDR405 kernel: [ 882.212115] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.420327] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.420449] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.426477] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.426582] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.426682] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.477971] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.478070] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.478160] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.478300] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.478406] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.478528] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.478652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.478750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.478844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.478935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.479026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.479117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.479211] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.479306] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.479400] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.479506] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.479601] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.479696] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.479789] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.479950] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.486926] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.487051] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.487238] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.487373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.487474] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.487645] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.504234] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.504766] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.504860] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.505002] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.505128] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.505253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.505348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.505444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.505535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.505625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.505714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.505809] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.505903] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.505996] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.506087] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.520254] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.520378] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.520549] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.520688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.520788] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.520939] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.521044] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.521179] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.538163] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.538320] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.538450] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.538576] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.538709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.538804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.538901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.538994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.539086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.539178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.539277] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.539371] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.539462] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.539552] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.539655] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.539750] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.539860] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.547311] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.552718] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.552747] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.552836] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.552880] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.552904] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.552955] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553013] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553057] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553103] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553154] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553202] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553247] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553295] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553340] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553382] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553427] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553447] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553489] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553508] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553552] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553595] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553637] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553680] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553722] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553773] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553815] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553861] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553906] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553951] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.553996] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554040] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554135] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554188] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554235] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554626] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554927] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554959] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.554987] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.555040] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.555068] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.555204] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.555241] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 882.555271] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.100352] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.100462] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.100559] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.100654] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.202604] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.202714] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.202820] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.202992] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.302183] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.302284] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.302382] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.302535] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.302643] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.302746] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.303950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.304042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.304179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.305550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.305639] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.306295] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.306386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.307348] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.307442] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.308040] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.308577] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.308674] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.308769] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.308871] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.325447] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.325545] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:00 GLK-2-GLKRVP1DDR405 kernel: [ 883.325699] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.575571] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.575715] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.575869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.575971] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.576289] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.784369] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.784497] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.793270] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.793374] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.793477] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.844565] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.844666] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.844760] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.844910] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.845037] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.845165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.845265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.845363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.845457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.845550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.845643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.845740] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.845835] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.845929] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.846020] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.846120] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.846227] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.846349] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.846448] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.846544] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.846699] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.846747] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.846856] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.854598] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.859275] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.863901] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.868010] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.908382] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.908416] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.908448] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 883.908482] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023481] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023501] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023560] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023591] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023608] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023645] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023684] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023714] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023744] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023780] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023813] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023844] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023910] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023938] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023966] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.023979] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024008] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024020] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024049] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024106] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024136] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024233] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024263] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024296] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024329] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024360] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024392] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024423] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024490] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024532] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.024563] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.025443] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.025470] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.026417] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.026451] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.026595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.026626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.026657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.026686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.026716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.026747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.026776] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.026808] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.026837] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.026890] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.026921] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.027042] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.027080] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:01 GLK-2-GLKRVP1DDR405 kernel: [ 884.027110] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.476356] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.476465] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.476562] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.476657] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.578597] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.578709] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.578815] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.578989] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.677798] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.677898] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.677997] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.678104] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.678212] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.678317] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.679495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.679587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.679681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.680491] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.680586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.681557] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.681653] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.682254] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.682387] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.682485] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.682580] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.688152] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.699318] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.699437] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.699591] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.949379] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.949464] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 884.949525] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 885.215802] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 885.215888] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:02 GLK-2-GLKRVP1DDR405 kernel: [ 885.215949] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 885.482294] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 885.482379] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 885.482440] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 885.748745] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 885.748934] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 885.749084] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 885.749183] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 885.749354] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 885.956356] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 885.956483] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 885.965254] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 885.965360] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 885.965463] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.016383] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.016483] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.016577] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.016733] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.016861] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.016989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.017090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.017189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.017282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.017375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.017468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.017565] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.017660] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.017752] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.017844] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.017945] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.018052] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.018154] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.018246] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.018342] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.018439] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.018536] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.018639] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.018748] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.018841] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.018989] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.019099] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.019569] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.019602] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.021590] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.021680] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.022457] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.022861] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.022908] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.023034] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.023129] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.023176] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.023277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.023399] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.023493] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.023593] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.023690] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.023789] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.023882] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.023978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024069] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024189] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024232] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024285] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024299] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024331] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024362] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024394] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024456] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024490] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024521] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024552] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024584] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024614] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024646] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024676] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024742] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024781] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.024813] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.026429] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.026582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.026618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.026655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.026689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.026722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.026754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.026789] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.026822] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.026853] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.026909] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.026944] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.027071] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.027115] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:03 GLK-2-GLKRVP1DDR405 kernel: [ 886.027148] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.652360] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.652468] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.652566] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.652662] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.754598] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.754710] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.754816] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.754994] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.853368] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.853468] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.853566] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.853673] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.853781] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.853885] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.855064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.855155] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.855249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.855923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.856011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.856725] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.856830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.857816] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.857914] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.858521] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.858644] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.858742] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.858837] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.864469] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.864543] [drm:intel_fbc_enable [i915]] reserved 21012480 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.864599] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.875571] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.875640] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 886.875745] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.125634] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.126221] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.126275] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:84:DP-1] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.126418] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.126517] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.126620] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.126721] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.126813] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.126911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.127008] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.127102] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.127195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.127288] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.127378] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.127468] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.127511] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.127601] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.127643] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.127737] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.127828] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.127918] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.128008] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.128097] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.128264] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.128358] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.128455] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.128550] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.128643] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.128736] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.128830] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.128933] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.129029] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.129140] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.129237] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.133051] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.133141] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.133312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.133346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.133380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.133412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.133442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.133473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.133505] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.133551] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.133582] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.141965] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.142001] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.142133] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.142179] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.142624] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.143251] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.143700] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.143753] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.144266] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.144313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.144344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.144384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.144415] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.144891] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.145019] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.145459] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.145501] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.145981] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.146038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.146067] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.146094] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.146557] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.146685] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.147123] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.147166] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.147645] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.147691] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.147721] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.147750] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.148223] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.148652] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.149092] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.149121] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.149603] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.149651] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.150005] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.150034] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.150473] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.150829] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.150945] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.167870] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.167938] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:04 GLK-2-GLKRVP1DDR405 kernel: [ 887.168039] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 887.408641] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.158070] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.174782] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.174803] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208435] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208509] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208553] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208603] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208651] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208693] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208779] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208819] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208847] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208888] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208907] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208949] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.208989] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209031] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209071] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209111] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209162] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209202] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209245] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209287] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209330] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209372] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209414] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209504] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209559] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209601] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209650] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209691] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209738] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.209779] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:48:05 GLK-2-GLKRVP1DDR405 kernel: [ 888.210027] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.416344] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.416470] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.425237] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.425340] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.425444] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.476388] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.476488] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.476581] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.476730] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.476844] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.476969] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.477101] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.478356] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.478465] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.478569] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.478740] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.484387] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.484922] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.485018] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.485164] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.485294] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.485390] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.485640] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.485774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.485872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.485971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.486065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.486158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.486251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.486345] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.486439] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.486531] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.486677] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.486772] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.487025] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.487083] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 888.487135] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.084343] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.084452] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.084549] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.084644] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.186601] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.186713] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.186819] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.186991] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.286303] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.286404] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.286501] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.286655] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.286762] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.286867] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.288041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.288191] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.288292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.289325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.289415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.290064] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.290149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.291104] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.291190] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.291622] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.291726] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.291815] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.291899] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.296377] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.296456] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.296521] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.308629] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.308702] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.308890] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.308968] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.309449] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.310111] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.310593] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.310652] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.311134] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.311214] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.311277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.311347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.311406] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.311912] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.312094] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.312929] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.313012] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.313556] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.313653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.313734] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.313812] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.314335] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.314512] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.315006] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.315084] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.315622] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.315708] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.315792] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.315870] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.316408] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.316888] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.317396] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.317474] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.318011] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.318099] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.318522] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.318602] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.319097] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.319396] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.319499] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.336333] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.336409] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.336580] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.336889] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.337412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.337482] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.337553] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.337619] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.354436] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.354542] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.354677] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.354805] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.354895] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.355012] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.355135] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.355221] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:06 GLK-2-GLKRVP1DDR405 kernel: [ 889.355335] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.476269] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.476502] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.476642] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.480350] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.497132] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.501089] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.501166] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.501229] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.501735] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.501755] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.708620] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.709607] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.709655] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.733623] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.733964] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.734143] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.737538] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.754821] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.759272] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.759360] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.759437] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.759453] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.759530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.759563] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.759786] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.964358] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.964480] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.975918] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.976023] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 889.976124] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.028302] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.028400] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.028491] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.028632] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.028739] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.028861] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.028983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.029073] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.029179] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.029273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.029366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.029467] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.029560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.029661] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.029752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.029849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.029951] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.030443] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.030543] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.030655] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.037741] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.037864] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.038048] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.038182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.038283] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.038454] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.055283] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.055821] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.055914] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.056056] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.056237] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.056364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.056461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.056562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.056654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.056745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.056839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.056935] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.057033] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.057127] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.057221] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.071100] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.071228] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.071390] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.071530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.071628] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.071767] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.071870] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.072007] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.088908] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.089065] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.089194] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.089321] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.089454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.089551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.089647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.089740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.089832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.089924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.090022] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.090115] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.090206] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.090296] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.090399] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.090493] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.090605] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.098431] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.103540] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.103568] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.103655] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.103697] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.103719] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.103769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.103825] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.103866] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.103909] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.103958] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104003] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104045] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104148] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104190] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104233] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104255] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104299] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104320] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104365] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104407] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104448] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104529] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104582] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104624] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104668] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104713] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104757] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104801] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104845] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104936] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.104991] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.105034] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.105404] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.105563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.105607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.105652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.105693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.105737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.105780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.105822] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.105869] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.105913] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.105981] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.106026] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.106185] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.106220] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:07 GLK-2-GLKRVP1DDR405 kernel: [ 890.106252] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.652380] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.652489] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.652587] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.652683] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.754596] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.754708] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.754809] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.754964] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.855176] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.855276] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.855374] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.855527] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.855635] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.855739] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.857003] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.857096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.857192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.857904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.857993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.858646] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.858736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.859698] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.859793] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.860409] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.860527] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.860624] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.860721] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.860823] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.877442] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.877531] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 890.877676] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 891.127512] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 891.127657] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 891.127816] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 891.127918] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 891.128092] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 891.336345] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 891.336472] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 891.345233] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 891.345338] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:08 GLK-2-GLKRVP1DDR405 kernel: [ 891.345442] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.396413] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.396513] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.396608] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.396760] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.396887] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.397013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.397114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.397212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.397306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.397399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.397492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.397589] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.397683] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.397775] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.397866] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.397965] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.398073] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.398175] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.398274] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.398370] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.398465] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.398569] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.398681] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.398771] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.398863] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.399010] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.399120] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.409192] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.415161] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.419682] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.425175] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578322] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578343] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578411] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578442] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578460] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578495] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578534] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578563] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578595] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578631] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578665] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578694] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578759] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578787] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578815] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578828] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578858] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578870] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578899] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578930] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578958] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.578986] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.579014] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.579053] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.579081] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.579112] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.579144] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.579175] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.579205] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.579236] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.579267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.579301] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.579337] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.579369] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.580237] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.580267] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581218] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581251] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581579] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581611] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581639] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581692] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581721] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581844] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581881] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 891.581912] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.028343] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.028451] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.028547] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.028642] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.130594] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.130706] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.130812] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.130987] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.229781] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.229881] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.229979] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.230086] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.230193] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.230297] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.231507] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.231608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.231705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.232688] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.232784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.233753] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.233849] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.234450] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.234581] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.234678] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.234773] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.240149] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.251523] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.251618] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:09 GLK-2-GLKRVP1DDR405 kernel: [ 892.251750] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 892.501464] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 892.501547] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 892.501605] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 892.768021] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 892.768472] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 892.768529] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 893.034352] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 893.034438] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 893.034499] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 893.300919] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 893.301113] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 893.301268] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 893.301370] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:10 GLK-2-GLKRVP1DDR405 kernel: [ 893.301543] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.508349] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.508474] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.517245] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.517351] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.517453] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.568596] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.568694] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.568786] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.568935] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.569063] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.569190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.569292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.569390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.569484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.569577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.569670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.569767] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.569863] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.569956] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.570047] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.570147] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.570253] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.570358] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.570456] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.570551] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.570663] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.570774] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.570865] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.570953] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.571054] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.571196] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.571307] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.571782] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.571814] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.573686] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.573732] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.574626] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.574916] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.574940] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575004] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575052] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575076] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575127] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575187] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575234] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575334] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575382] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575429] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575477] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575523] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575569] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575591] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575638] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575659] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575707] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575753] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575800] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575846] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575892] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575942] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.575988] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.576034] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.576096] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.576146] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.576195] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.576243] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.576295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.576343] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.576400] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.576450] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.578479] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.578653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.578705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.578759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.578808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.578855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.578903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.578953] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.579002] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.579050] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.579122] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.579172] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.579318] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.579377] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 893.579426] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 894.204359] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 894.204464] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 894.204562] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 894.204657] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 894.306572] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 894.306685] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 894.306792] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:11 GLK-2-GLKRVP1DDR405 kernel: [ 894.306972] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.405794] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.405894] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.405992] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.406099] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.406208] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.406313] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.407489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.407581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.407677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.408735] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.408831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.409801] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.409898] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.410496] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.410630] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.410727] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.410822] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.416338] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.416450] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.416544] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.427583] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.427688] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.427828] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.677572] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.927394] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 894.936275] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:12 GLK-2-GLKRVP1DDR405 kernel: [ 895.193849] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.443453] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.693404] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.709950] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.709965] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740507] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740540] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740578] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740611] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740639] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740675] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740709] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740739] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740772] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740803] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740831] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740858] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740881] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740909] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740922] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740951] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.740979] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741009] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741036] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741064] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741099] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741126] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741157] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741187] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741217] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741247] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741278] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741309] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741356] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741384] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741415] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741447] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741474] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741502] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741529] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741556] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741569] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741597] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741610] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741638] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741666] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741694] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741721] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741748] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741779] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741806] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741836] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741864] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741894] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741924] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741954] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.741986] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.742016] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.742056] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.742085] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.742118] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.742146] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.742180] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.742208] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.742432] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.948351] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.948480] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.959957] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.960063] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 895.960243] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.011279] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.011381] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.011475] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.011619] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.011729] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.011855] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.011954] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.012094] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.012456] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.012825] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.012957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.013056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.013149] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.013253] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.013352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.013446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.013550] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.013643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.013736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.013835] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.013933] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.014026] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.014174] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.014272] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.014418] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.014684] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.014781] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:13 GLK-2-GLKRVP1DDR405 kernel: [ 896.014868] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.636349] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.636459] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.636556] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.636650] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.738562] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.738673] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.738776] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.738933] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.837894] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.837994] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.838093] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.838247] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.838353] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.838456] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.839629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.839720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.839812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.841030] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.841122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.842085] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.842180] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.842632] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.842745] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.842843] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.842938] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.848260] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.848319] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.848366] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.859644] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.859730] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.859917] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.860008] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.860511] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.861196] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.861692] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.861763] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.862256] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.862352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.862428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.862508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.862579] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.863099] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.863270] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.863756] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.863829] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.864366] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.864458] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.864534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.864607] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.865125] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.865295] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.865782] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.865852] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.866381] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.866457] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.866532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.866603] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.867121] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.867589] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.868074] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.868172] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.868706] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.868788] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.869195] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.869268] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.869758] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.870047] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.870187] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.870314] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.870389] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.870560] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.870801] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.871329] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.871362] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.871397] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.871428] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.888365] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.888431] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.888535] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.888638] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.888695] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.888777] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.888870] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.888936] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 896.889016] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.010960] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.011082] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.011191] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.013860] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.031669] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.035609] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.035692] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.035754] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.036439] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.036458] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.242961] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.243941] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.243989] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.268001] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.268343] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.268415] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.270500] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.287833] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.292410] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.292543] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.292604] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.292619] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.292694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.292726] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:14 GLK-2-GLKRVP1DDR405 kernel: [ 897.292965] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.500345] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.500469] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.509213] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.509316] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.509416] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.560343] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.560441] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.560532] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.560671] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.560779] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.560901] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.561024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.561121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.561215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.561306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.561398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.561488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.561583] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.561678] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.561772] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.561878] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.562309] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.562417] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.562518] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.562644] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.571703] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.571829] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.572017] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.572212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.572319] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.572494] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.588872] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.589406] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.589500] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.589642] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.589769] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.589894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.589990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.590085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.590176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.590266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.590356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.590451] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.590546] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.590640] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.590731] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.605054] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.605181] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.605354] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.605492] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.605594] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.605743] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.605847] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.605978] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.622551] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.622707] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.622838] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.622965] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.623099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.623197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.623294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.623388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.623481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.623573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.623672] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.623766] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.623858] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.623949] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.624051] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.624215] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.624340] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.631669] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.637403] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.637434] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.637528] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.637574] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.637599] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.637653] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.637715] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.637762] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.637811] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.637865] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.637916] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.637964] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638109] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638153] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638174] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638220] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638240] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638288] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638335] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638381] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638426] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638470] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638525] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638571] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638619] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638667] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638714] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638762] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638809] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638908] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.638965] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639014] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639416] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639715] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639747] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639776] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639828] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639857] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.639992] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.640030] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 897.640090] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.172363] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.172471] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.172567] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.172662] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.274525] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.274636] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.274737] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.274894] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.374022] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.374122] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.374220] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.374373] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.374483] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.374589] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.375794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.375886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:15 GLK-2-GLKRVP1DDR405 kernel: [ 898.375982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.376926] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.377018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.377984] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.378080] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.378679] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.378797] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.378895] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.378991] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.384337] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.395735] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.395843] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.396006] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.645735] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.645879] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.646036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.646139] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.646312] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.852360] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.852485] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.863230] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.863334] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.863439] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.915076] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.915177] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.915272] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.915426] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.915555] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.915683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.915785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.915884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.915978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.916072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.916226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.916328] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.916433] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.916534] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.916645] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.917020] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.917126] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.917226] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.917333] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.917447] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.917609] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.917722] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.918927] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.919024] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.919118] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.919214] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.919318] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.927296] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.934013] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.938609] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 898.944115] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097379] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097398] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097467] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097498] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097515] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097550] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097590] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097619] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097651] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097690] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097724] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097754] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097788] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097819] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097848] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097876] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097889] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097917] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097930] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097959] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.097988] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098019] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098047] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098075] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098111] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098139] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098170] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098201] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098232] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098263] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098293] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098359] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098395] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.098427] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.099267] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.099294] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.100284] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.100322] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101298] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101330] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101359] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101412] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101441] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101568] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101606] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:16 GLK-2-GLKRVP1DDR405 kernel: [ 899.101637] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.548398] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.548506] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.548602] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.548698] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.650609] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.650720] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.650827] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.651004] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.751084] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.751184] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.751282] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.751390] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.751498] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.751603] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.752796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.752890] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.752989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.753673] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.753762] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.754428] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.754519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.755486] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.755581] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.756244] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.756377] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.756475] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.756573] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.756677] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.773286] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.773357] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 899.773465] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 900.023391] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 900.023477] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 900.023538] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 900.289840] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 900.289927] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:17 GLK-2-GLKRVP1DDR405 kernel: [ 900.289988] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 900.556291] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 900.556378] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 900.556439] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 900.822733] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 900.822928] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 900.823083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 900.823182] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 900.823356] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.028369] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.028496] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.039977] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.040082] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.040240] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.092311] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.092411] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.092505] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.092657] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.092785] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.092913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.093014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.093111] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.093207] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.093302] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.093417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.093527] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.093623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.093717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.093810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.093907] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.094002] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.094094] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.094186] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.094286] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.094393] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.094494] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.094586] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.094676] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.094768] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.094922] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.095035] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.095509] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.095542] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.097528] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.097615] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.098396] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.098960] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.099005] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.099130] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.099223] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.099271] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.099372] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.099491] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.099585] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.099685] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.099783] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.099879] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.099972] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.100067] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.100189] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.100284] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.100333] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.100430] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.100479] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.100579] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.100678] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.100775] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.100873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.100968] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.101073] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.101163] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.101255] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.101347] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.101437] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.101531] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.101621] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.101721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.101812] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.101922] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.102016] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.103651] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.103849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.103944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.104036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.104163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.104257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.104352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.104448] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.104558] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.104656] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.104799] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.104892] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.105099] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.105206] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:18 GLK-2-GLKRVP1DDR405 kernel: [ 901.105304] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.724341] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.724448] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.724544] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.724638] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063 Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.826590] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.826703] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.826809] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.826987] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.925877] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.925978] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.926077] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.926184] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.926292] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.926396] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.927574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.927666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.927759] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.928726] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.928821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.929792] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.929888] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.930489] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.930623] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.930720] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.930815] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.936521] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.936645] [drm:intel_fbc_enable [i915]] reserved 21012480 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.936743] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.947575] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.947680] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 901.947822] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:19 GLK-2-GLKRVP1DDR405 kernel: [ 902.197565] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 902.447374] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 902.470138] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 902.747140] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 902.996825] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.246748] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.263319] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.263341] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300498] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300531] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300571] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300604] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300632] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300702] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300732] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300796] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300824] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300851] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300874] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300902] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300915] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300944] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.300972] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301002] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301030] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301057] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301093] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301120] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301151] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301181] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301211] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301241] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301271] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301303] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301349] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301378] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301409] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301439] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301467] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301495] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301524] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301551] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301565] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301592] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301605] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301634] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301661] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301689] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301716] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301743] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301773] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301800] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301830] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301857] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301887] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301917] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301947] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.301978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.302009] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.302051] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.302079] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.302111] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.302139] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.302173] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.302200] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:48:20 GLK-2-GLKRVP1DDR405 kernel: [ 903.302413] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.508321] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.508437] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.514410] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.514503] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.514597] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.566810] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.566911] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.567005] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.567149] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.567261] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.567387] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.567484] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.567578] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.567671] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.567783] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.567893] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.568030] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.569109] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.569352] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.569484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.569581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.569680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.569774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.569868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.569961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.570055] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.570150] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.570243] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.570387] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.570482] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.570827] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.570928] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 903.571024] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 904.188346] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 904.188455] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 904.188552] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 904.188646] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 904.290590] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 904.290689] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 904.290784] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:21 GLK-2-GLKRVP1DDR405 kernel: [ 904.290939] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.391079] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.391179] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.391277] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.391430] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.391538] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.391642] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.392819] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.392913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.393012] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.393674] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.393767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.394725] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.394819] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.395270] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.395387] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.395482] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.395577] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.400306] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.400417] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.400511] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.412325] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.412390] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.412551] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.412625] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.413099] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.413756] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.414237] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.414291] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.414819] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.414915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.414991] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.415072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.415144] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.415662] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.415834] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.416435] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.416509] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.417056] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.417146] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.417219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.417290] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.417800] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.417970] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.418455] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.418526] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.419055] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.419132] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.419208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.419285] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.419804] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.420305] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.420799] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.420873] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.421416] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.421496] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.421906] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.421977] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.422464] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.422754] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.422893] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.423025] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.423100] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.423270] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.423591] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.424185] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.424267] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.424356] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.424435] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.441214] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.441324] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.441462] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.441617] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.441709] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.441830] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.441985] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.442075] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.442192] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.576048] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.576296] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.576436] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.580192] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.598865] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.602805] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.602882] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.602943] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.603453] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.603474] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.812279] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.813266] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.813314] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.836306] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.836407] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.836490] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.838877] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.857161] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.861175] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.861258] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.861323] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.861340] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.861415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.861450] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 904.861672] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.068340] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.068462] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.079918] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.080021] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.080121] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.131082] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.131181] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.131272] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.131413] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.131521] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.131643] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.131765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.131862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.131955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.132047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.132194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.132292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.132394] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.132495] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.132593] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.132707] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.132942] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.133048] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.133150] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.133374] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.141179] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.141280] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.141441] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.141550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.141631] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.141776] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.157801] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.158331] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.158425] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.158568] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.158695] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.158819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.158916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.159012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.159103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.159194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.159285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.159380] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.159475] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.159568] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.159660] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.174533] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.174660] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.174834] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.174972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.175072] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.175223] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.175327] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.175464] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.192342] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.192497] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.192627] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.192753] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.192890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.192986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.193082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.193176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.193268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.193360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.193458] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.193553] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.193645] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.193736] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.193838] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.193933] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.194044] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.194139] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.194236] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.194326] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.194416] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.205306] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.210953] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.210974] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211043] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211072] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211089] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211124] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211163] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211192] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211223] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211259] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211291] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211321] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211355] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211413] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211444] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211457] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211485] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211498] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211527] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211555] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211586] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211614] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211641] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211677] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211705] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211736] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211768] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211799] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211829] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211860] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211922] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211959] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.211990] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.212883] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.212912] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.213899] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.213933] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214271] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214302] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214331] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214384] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214412] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214547] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214595] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:22 GLK-2-GLKRVP1DDR405 kernel: [ 905.214626] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.756353] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.756462] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.756559] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.756654] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.858598] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.858710] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.858816] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.858992] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.956865] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.956963] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.957062] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.957169] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.957278] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.957380] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.958568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.958660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.958755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.959440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.959529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.960216] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.960317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.961295] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.961383] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.961960] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.962080] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.962160] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.962238] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.968156] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.979037] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.979157] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 905.979312] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 906.229065] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 906.229210] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 906.229363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 906.229464] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:23 GLK-2-GLKRVP1DDR405 kernel: [ 906.229637] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.436365] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.436493] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.445263] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.445368] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.445472] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.497253] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.497354] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.497448] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.497601] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.497729] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.497856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.497956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.498054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.498148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.498241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.498334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.498430] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.498525] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.498621] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.498737] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.498846] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.498943] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.499036] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.499128] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.499229] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.499337] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.499438] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.499530] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.499620] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.499712] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.499858] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.499968] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.507667] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.513029] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.518221] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.522819] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.678591] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.678612] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.678679] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.678709] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.678726] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.678763] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.678803] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.678832] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.678864] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.678899] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.678933] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.678963] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.678997] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679057] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679088] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679101] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679129] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679142] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679171] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679200] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679231] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679260] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679324] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679353] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679384] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679415] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679446] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679474] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679505] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679568] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679605] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.679637] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.680533] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.680562] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.681482] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.681516] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.681657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.681688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.681716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.681744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.681775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.681806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.681834] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.681866] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.681895] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.681948] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.681976] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.682101] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.682138] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 906.682169] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.132348] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.132458] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.132556] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.132651] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.234585] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.234695] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.234802] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.234939] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.335466] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.335564] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.335663] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.335770] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.335878] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.335981] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.337260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.337352] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.337446] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.338121] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.338211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.339183] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.339277] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.339876] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.340011] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.340110] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.340238] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.340346] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.356834] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.356897] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:24 GLK-2-GLKRVP1DDR405 kernel: [ 907.357001] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:25 GLK-2-GLKRVP1DDR405 kernel: [ 907.607026] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:25 GLK-2-GLKRVP1DDR405 kernel: [ 907.607110] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:25 GLK-2-GLKRVP1DDR405 kernel: [ 907.607172] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:25 GLK-2-GLKRVP1DDR405 kernel: [ 907.873364] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:25 GLK-2-GLKRVP1DDR405 kernel: [ 907.873446] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:25 GLK-2-GLKRVP1DDR405 kernel: [ 907.873507] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:25 GLK-2-GLKRVP1DDR405 kernel: [ 908.139878] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:25 GLK-2-GLKRVP1DDR405 kernel: [ 908.139948] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:25 GLK-2-GLKRVP1DDR405 kernel: [ 908.139996] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.406357] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.406535] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.406677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.406768] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.406926] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.612353] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.612480] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.623961] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.624066] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.624241] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676143] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676178] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676211] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676282] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676341] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676616] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676650] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676682] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676713] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676748] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676785] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676825] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676857] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676887] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.676919] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.677893] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.677928] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.677962] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.678013] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.678980] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.679020] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.679215] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.679229] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.680854] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.680884] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.681433] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.681755] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.681772] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.681818] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.681864] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.681880] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.681916] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.681970] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682002] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682038] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682083] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682117] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682150] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682183] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682215] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682246] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682261] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682298] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682323] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682357] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682389] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682421] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682453] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682519] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682551] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682583] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682614] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682646] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682678] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682709] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682776] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682816] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.682849] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685069] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685418] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685468] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685498] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685593] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685635] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685755] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685791] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 908.685844] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 909.308359] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 909.308467] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 909.308564] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:26 GLK-2-GLKRVP1DDR405 kernel: [ 909.308659] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.410586] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.410698] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.410805] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.410977] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.510861] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.510961] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.511060] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.511168] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.511275] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.511379] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.512700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.512794] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.512892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.513572] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.513662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.514316] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.514407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.515369] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.515463] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.516060] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.516229] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.516324] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.516418] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.516679] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.516796] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.516890] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.533212] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.533317] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.533457] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 909.783184] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.032983] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.033623] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.033674] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:84:DP-1] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.033816] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.033916] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.034020] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.034122] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.034215] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.034314] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.034411] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.034505] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.034597] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.034690] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.034781] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.034870] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.034913] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.035003] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.035044] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.035137] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.035229] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.035327] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.035416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.035506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.035606] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.035696] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.035786] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.035876] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.035966] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.036055] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.036219] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.036323] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.036419] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.036531] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.036632] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.037311] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.037542] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.037753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.037848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.037945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.038035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.038128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.038225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.038320] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.038434] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.038528] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.049316] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.049372] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.049526] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.049590] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.050053] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.050758] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.051260] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.051305] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.051804] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.051871] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.051918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.051970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.052015] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.052508] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.052655] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.053113] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.053158] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.053655] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.053715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.053761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.053805] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.054288] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.054432] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.054945] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.054990] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.055534] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.055633] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.055681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.055726] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.056219] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.056667] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.057135] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.057180] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.057722] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.057824] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.058201] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.058247] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.058704] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.059114] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.059192] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.076235] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.076311] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.076424] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:27 GLK-2-GLKRVP1DDR405 kernel: [ 910.316112] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:28 GLK-2-GLKRVP1DDR405 kernel: [ 910.565907] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:28 GLK-2-GLKRVP1DDR405 kernel: [ 910.575020] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:28 GLK-2-GLKRVP1DDR405 kernel: [ 910.849010] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:28 GLK-2-GLKRVP1DDR405 kernel: [ 911.098628] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:28 GLK-2-GLKRVP1DDR405 kernel: [ 911.348619] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:28 GLK-2-GLKRVP1DDR405 kernel: [ 911.365089] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:28 GLK-2-GLKRVP1DDR405 kernel: [ 911.365103] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400501] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400556] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400586] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400657] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400687] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400721] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400749] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400776] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400799] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400827] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400839] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400868] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400896] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400926] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400954] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.400981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401018] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401045] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401076] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401106] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401136] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401166] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401196] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401260] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401299] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401328] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401364] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401392] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401426] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401454] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.401691] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.608350] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.608479] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.617253] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.617357] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.617460] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.668449] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.668549] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.668643] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.668785] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.668895] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.669020] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.669151] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.670481] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.670590] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.670692] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.670866] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.676342] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.676875] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.676971] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.677118] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.677248] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.677344] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.677595] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.677730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.677828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.677926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.678020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.678113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.678206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.678300] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.678395] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.678488] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.678625] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.678721] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.679066] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.679171] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 911.679268] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 912.284348] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 912.284455] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 912.284551] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:29 GLK-2-GLKRVP1DDR405 kernel: [ 912.284646] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.386598] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.386711] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.386816] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.386994] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.486202] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.486302] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.486400] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.486553] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.486660] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.486764] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.487938] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.488029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.488193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.489536] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.489626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.490277] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.490368] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.491274] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.491326] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.491675] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.491742] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.491797] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.491849] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.496257] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.496319] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.496369] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.508514] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.508591] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.508784] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.508866] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.509353] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.510022] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.510515] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.510586] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.511079] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.511166] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.511239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.511312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.511383] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.511902] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.512072] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.512575] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.513256] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.513744] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.513814] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.514343] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.514419] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.514492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.514562] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.515081] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.515548] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.516026] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.516771] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.517268] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.517340] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.517868] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.517953] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.518366] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.518439] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.518925] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.519187] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.519277] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.536216] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.536294] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.536471] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.536798] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.537425] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.537497] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.537570] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.537639] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.554503] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.554612] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.554753] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.554883] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.554987] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.555107] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.555246] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.555335] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.555451] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.683155] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.683428] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.683555] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.687092] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.706204] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.710187] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.710262] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.710322] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.710830] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.710851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.925301] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.926289] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.926337] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.950346] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.950633] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.950808] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.953762] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.970708] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.974795] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.974872] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.974934] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.974950] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.975027] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.975061] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 912.975305] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.180334] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.180456] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.191894] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.191999] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.192101] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.242995] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.243094] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.243185] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.243326] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.243433] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.243555] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.243677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.243774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.243867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.243958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.244049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.244185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.244286] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.244385] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.244483] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.244596] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.244957] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.245063] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.245166] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.245299] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.254433] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.254528] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.254680] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.254781] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.254854] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.254987] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.271151] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.271683] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.271778] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.271925] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.272081] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.272265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.272364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.272462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.272555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.272649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.272745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.272842] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.272938] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.273034] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.273131] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.287767] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.287893] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.288055] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.288250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.288349] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.288488] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.288595] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.288726] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.304347] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.304503] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.304634] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.304761] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.304896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.304992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.305088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.305182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.305274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.305366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.305465] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.305559] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.305652] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.305744] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.305846] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.305941] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.306051] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.315347] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322306] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322328] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322396] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322425] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322440] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322477] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322517] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322546] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322577] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322643] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322673] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322705] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322735] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322763] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322790] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322803] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322831] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322844] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322873] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322901] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322931] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322959] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.322986] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323023] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323051] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323082] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323114] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323145] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323177] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323208] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323270] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323306] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323338] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323681] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.323973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.324001] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.324033] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.324091] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.324146] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.324178] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.325150] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.325187] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:30 GLK-2-GLKRVP1DDR405 kernel: [ 913.325218] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 913.852416] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 913.852526] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 913.852623] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 913.852718] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 913.954587] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 913.954700] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 913.954806] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 913.954979] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.053805] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.053905] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.054003] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.054155] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.054262] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.054367] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.055580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.055671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.055766] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.056730] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.056815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.057779] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.057864] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.058451] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.058557] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.058646] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.058730] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.064153] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.075540] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.075660] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.075837] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.325594] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.325737] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.325895] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.325996] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:31 GLK-2-GLKRVP1DDR405 kernel: [ 914.326175] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.532349] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.532475] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.543951] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.544055] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.544228] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.595277] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.595376] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.595470] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.595624] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.595752] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.595879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.595979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.596077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.596231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.596330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.596429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.596530] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.596632] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.596729] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.596826] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.596924] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.597037] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.597127] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.597234] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.597322] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.597426] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.597511] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.597602] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.597696] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.598693] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.599013] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.599121] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.607033] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.612003] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.618254] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.622802] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777000] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777020] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777089] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777121] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777137] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777172] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777212] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777241] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777272] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777311] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777345] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777375] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777410] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777441] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777470] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777498] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777511] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777539] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777552] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777581] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777612] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777641] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777669] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777697] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777733] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777761] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777793] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777824] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777855] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777886] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777916] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.777979] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.778015] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.778047] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.778886] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.778914] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.779876] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.779910] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780265] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780299] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780329] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780382] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780413] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780585] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780621] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 914.780653] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 915.228399] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 915.228508] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 915.228606] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 915.228702] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 915.330590] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 915.330700] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 915.330806] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:32 GLK-2-GLKRVP1DDR405 kernel: [ 915.330949] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.431083] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.431184] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.431282] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.431389] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.431497] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.431602] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.432780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.432873] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.432968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.433633] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.433724] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.434686] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.434781] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.435379] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.435517] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.435613] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.435708] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.440154] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.452511] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.452614] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.452755] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.702498] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.702585] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.702647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.968955] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.969042] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 915.969102] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 916.235380] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 916.235465] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:33 GLK-2-GLKRVP1DDR405 kernel: [ 916.235521] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.501846] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.502038] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.502190] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.502289] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.502456] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.708348] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.708472] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.719239] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.719344] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.719447] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.771066] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.771165] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.771257] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.771411] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.771538] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.771666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.771767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.771865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.771959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.772053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.772209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.772311] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.772413] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.772515] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.772631] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.772742] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.772850] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.772946] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.773039] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.773143] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.773252] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.773352] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.773445] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.773535] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.773628] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.773769] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.773877] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.774340] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.774372] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.776303] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.776385] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.777202] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.777571] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.777611] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.777721] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.777816] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.777856] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.777946] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.778051] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.778134] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.778221] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.778306] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.778390] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.778473] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.778556] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.778636] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.778716] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.778753] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.778834] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.778871] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.778954] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.779036] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.779116] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.779197] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.779277] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.779369] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.779450] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.779530] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.779611] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.779691] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.779771] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.779851] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.779937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.780019] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.780141] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.780225] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781263] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781585] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781616] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781647] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781701] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781732] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781858] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781897] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:34 GLK-2-GLKRVP1DDR405 kernel: [ 916.781930] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.404345] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.404455] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.404552] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.404649] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.506600] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.506712] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.506818] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.507003] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.607079] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.607177] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.607275] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.607383] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.607489] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.607594] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.608804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.608906] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.609007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.609686] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.609780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.610756] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.610852] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.611460] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.611586] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.611686] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.611780] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.616318] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.616429] [drm:intel_fbc_enable [i915]] reserved 21012480 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.616523] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.628505] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.628600] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.628732] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 917.878557] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.128183] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.128783] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.128834] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:84:DP-1] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.128978] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.129078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.129182] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.129284] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.129377] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.129476] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.129574] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.129670] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.129763] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.129857] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.129947] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.130037] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.130079] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.130170] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.130210] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.130304] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.130396] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.130492] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.130582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.130672] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.130772] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.130862] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.130954] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.131044] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.131134] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.131224] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.131314] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.131412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.131504] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.131613] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.131708] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.132739] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.132881] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.133124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.133222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.133320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.133412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.133506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.133603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.133698] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.133812] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.133908] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.144616] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.144672] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.144824] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.144887] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.145351] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.145998] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.146518] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.146563] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.147031] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.147096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.147144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.147196] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.147241] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.147730] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.147874] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.148335] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.148383] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.148883] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.148944] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.148990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.149081] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.149602] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.149746] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.150203] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.150247] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.150749] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.150798] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.150846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.150891] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.151384] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.151818] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.152269] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.152309] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.152799] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.152842] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.153208] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.153245] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.153701] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.154053] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.154150] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.171119] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.171195] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:35 GLK-2-GLKRVP1DDR405 kernel: [ 918.171305] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:36 GLK-2-GLKRVP1DDR405 kernel: [ 918.411446] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:37 GLK-2-GLKRVP1DDR405 kernel: [ 920.143382] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:37 GLK-2-GLKRVP1DDR405 kernel: [ 920.167664] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 920.443121] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 920.692795] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 920.942470] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 920.959246] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 920.959262] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000411] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000471] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000505] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000544] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000583] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000616] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000653] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000685] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000716] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000741] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000772] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000787] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000819] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000851] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000885] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000947] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.000987] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001018] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001053] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001087] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001120] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001154] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001187] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001223] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001258] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001305] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001337] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001377] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001409] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001446] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001478] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.001704] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.208369] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.208494] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.208836] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.208933] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.209034] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.260347] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.260445] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.260536] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.260682] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.260796] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.260922] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.261054] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.261977] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.262086] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.262187] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.262353] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.272257] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.272792] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.272889] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.273037] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.273167] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.273263] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.273514] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.273648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.273744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.273842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.273937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.274030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.274122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.274216] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.274310] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.274402] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.274549] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.274644] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.274915] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.275000] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:38 GLK-2-GLKRVP1DDR405 kernel: [ 921.275078] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 921.884389] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 921.884497] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 921.884594] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 921.884689] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 921.986608] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 921.986721] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 921.986828] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 921.986998] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.085843] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.085943] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.086040] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.086194] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.086301] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.086404] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.087584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.087674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.087768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.088557] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.088650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.089623] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.089717] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.090172] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.090287] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.090386] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.090481] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.096293] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.096356] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.096406] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.107173] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.107231] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.107456] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.107547] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.108048] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.108765] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.109267] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.109338] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.109836] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.109933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.110009] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.110086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.110158] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.110683] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.110854] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.111338] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.112018] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.112521] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.112596] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.113129] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.113209] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.113287] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.113358] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.113883] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.114351] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.114836] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.115672] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.116380] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.116455] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.116993] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.117078] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.117491] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.117565] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.118057] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.118325] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.118423] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.135341] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.135380] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.135512] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.135742] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.136341] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.136403] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.136500] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.136558] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.153372] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.153473] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.153603] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.153726] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.153816] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.153927] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.154044] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.154125] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.154233] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.285294] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.285435] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.285665] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.289227] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.307392] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.311390] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.311469] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.311531] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.312088] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:39 GLK-2-GLKRVP1DDR405 kernel: [ 922.312108] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.523800] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.524973] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.525021] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.548198] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.548513] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.548659] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.552645] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.571929] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.576005] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.576840] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.576913] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.576930] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.577004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.577036] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.577240] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.784332] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.784455] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.790485] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.790589] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.790689] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.842639] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.842738] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.842829] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.842971] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.843078] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.843200] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.843323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.843421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.843516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.843606] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.843710] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.843803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.843894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.843994] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.844087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.844188] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.844286] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.844412] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.844511] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.844624] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.853366] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.853489] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.853674] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.853809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.853909] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.854085] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.869822] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.870353] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.870449] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.870590] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.870718] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.870843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.870938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.871033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.871125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.871216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.871307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.871402] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.871497] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.871591] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.871682] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.886705] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.886831] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.887006] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.887145] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.887245] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.887394] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.887497] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.887630] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.905781] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.905937] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.906067] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.906194] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.906328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.906425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.906522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.906615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.906707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.906799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.906897] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.906992] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.907084] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.907175] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.907276] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.907371] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.907483] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.915122] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.920564] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.920594] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.920682] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.920726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.920750] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.920801] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.920859] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.920903] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.920949] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.920999] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921047] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921092] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921137] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921182] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921224] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921266] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921286] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921328] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921347] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921391] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921434] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921479] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921521] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921563] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921615] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921657] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921702] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921748] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921793] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921837] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921882] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921929] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.921974] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922027] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922074] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922473] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922786] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922817] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922845] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922898] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.922927] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.923063] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.923100] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:40 GLK-2-GLKRVP1DDR405 kernel: [ 922.923130] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.452349] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.452455] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.452552] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.452647] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.554597] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.554709] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.554815] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.554988] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.655362] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.655462] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.655560] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.655714] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.655822] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.655926] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.657479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.657580] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.657676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.658391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.658480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.659134] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.659225] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.660247] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.660344] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.660951] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.661056] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.661142] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.661226] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.661318] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.678002] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.678109] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.678272] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.928069] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.928289] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.928447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.928549] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 923.928719] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.136368] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.136492] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.145260] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.145364] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.145466] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.197775] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.197874] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.197967] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.198119] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.198249] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.198377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.198468] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.198575] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.198672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.198771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.198874] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.198969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.199075] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.199168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.199262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.199359] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.199454] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.199546] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.199637] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.199738] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.199845] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.199947] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.200039] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.200188] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.200287] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.200910] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.201022] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.209015] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.216022] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.220741] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:41 GLK-2-GLKRVP1DDR405 kernel: [ 924.226799] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.380924] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.380945] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381014] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381063] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381099] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381139] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381169] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381201] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381241] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381275] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381305] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381372] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381400] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381429] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381442] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381472] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381485] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381516] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381545] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381576] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381605] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381633] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381670] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381698] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381730] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381763] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381795] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381828] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381859] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381923] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381960] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.381993] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.382830] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.382858] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.383841] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.383876] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.384019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.384050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.384089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.384122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.384156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.384191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.384223] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.384261] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.384293] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.384348] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.384379] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.385388] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.385426] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.385457] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.828365] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.828473] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.828570] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.828666] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.930589] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.930700] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.930806] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 924.930984] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.031088] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.031188] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.031286] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.031393] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.031501] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.031605] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.033290] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.033392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.033492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.034164] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.034258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.035224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.035320] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.035920] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.036052] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.036178] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.036888] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.036992] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.052884] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.052991] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.053143] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.303042] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.303128] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:42 GLK-2-GLKRVP1DDR405 kernel: [ 925.303189] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 925.569514] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 925.569602] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 925.569664] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 925.835960] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 925.836047] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 925.836208] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.102420] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.102612] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.102769] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.102871] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.103047] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.308357] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.308484] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.319964] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.320069] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.320210] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.372351] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.372452] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.372546] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.372699] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.372826] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.372951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.373052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.373143] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.373248] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.373344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.373439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.373541] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.373636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.373739] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.373832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:43 GLK-2-GLKRVP1DDR405 kernel: [ 926.373931] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.374375] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.374473] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.374568] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.374668] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.374777] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.374880] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.374974] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.375066] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.375159] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.375319] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.375419] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.375853] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.377714] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.377792] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.378690] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.379061] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.379101] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.379211] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.379295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.379335] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.379424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.379529] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.379612] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.379700] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.379786] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.379869] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.379952] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.380034] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.380142] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.380229] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.380270] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.380357] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.380400] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.380489] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.380577] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.380664] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.380749] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.380835] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.380931] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.380997] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.381064] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.381130] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.381196] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.381264] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.381330] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.381404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.381471] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.381552] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.381621] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.382413] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.382589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.382666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.382738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.382808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.382877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.382944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.383017] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.383088] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.383159] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.383264] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.383335] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.383509] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.383591] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 926.383662] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.004367] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.004475] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.004572] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.004668] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.106602] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.106714] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.106819] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.107004] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.207032] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.207132] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.207230] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.207337] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.207444] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.207547] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.208758] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.208861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.208963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.209657] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.209746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.210415] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.210506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.211483] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.211578] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.212201] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.212343] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.212441] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.212538] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.212797] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.229139] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.229207] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:44 GLK-2-GLKRVP1DDR405 kernel: [ 927.229316] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:45 GLK-2-GLKRVP1DDR405 kernel: [ 927.479360] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:45 GLK-2-GLKRVP1DDR405 kernel: [ 927.729146] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:45 GLK-2-GLKRVP1DDR405 kernel: [ 927.767760] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:45 GLK-2-GLKRVP1DDR405 kernel: [ 927.798235] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:45 GLK-2-GLKRVP1DDR405 kernel: [ 927.798256] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:45 GLK-2-GLKRVP1DDR405 kernel: [ 928.062208] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:45 GLK-2-GLKRVP1DDR405 kernel: [ 928.312011] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.561802] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.578301] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.578317] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616447] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616486] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616532] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616571] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616605] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616647] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616686] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616721] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616795] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616828] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616860] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616886] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616918] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616933] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.616967] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617000] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617035] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617099] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617144] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617176] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617212] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617247] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617282] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617317] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617352] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617389] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617443] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617478] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617514] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617550] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617583] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617648] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617680] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617695] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617727] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617742] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617776] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617808] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617840] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617905] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617940] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.617972] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618008] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618040] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618075] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618110] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618145] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618218] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618266] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618300] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618338] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618371] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618411] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618444] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.618670] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.824352] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.824477] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.830542] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.830648] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.830751] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.881812] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.881914] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.882008] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.882161] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.882288] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.882388] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.882527] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.882748] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.882988] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.883121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.883218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.883312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.883406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.883497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.883591] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.883696] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.883787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.883884] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.883987] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.884083] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.884187] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.884326] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.884473] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.884566] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.884912] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.885018] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:46 GLK-2-GLKRVP1DDR405 kernel: [ 928.885117] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.500349] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.500457] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.500554] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.500648] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.602605] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.602715] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.602822] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.602966] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.702198] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.702298] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.702396] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.702549] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.702657] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.702760] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.703944] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.704036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.704190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.705507] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.705610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.706578] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.706677] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.707130] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.707250] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.707347] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.707441] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.712331] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.712417] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.712487] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.724237] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.724331] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.724527] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.724626] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.725134] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.725816] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.726325] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.726404] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.726912] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.727018] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.727102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.727192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.727271] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.727804] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.727983] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.728490] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.728574] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.729124] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.729224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.729305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.729386] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.729910] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.730088] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.730590] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.730668] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.731210] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.731295] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.731377] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.731455] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.731988] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.732465] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.732969] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.733047] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.733590] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.733677] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.734097] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.734176] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.734678] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.734987] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.735133] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.735271] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.735353] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.735534] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.735890] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.736544] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.736653] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.736691] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.736725] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.753571] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.753616] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.753687] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.753780] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.753815] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.753874] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.753945] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.753980] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.754037] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.893021] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.893303] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.893456] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.897176] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.914005] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.917962] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.918037] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.918099] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.918622] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 929.918642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.124115] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.125325] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.125375] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.148555] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.148721] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.148875] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.152987] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.171723] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.175669] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.175751] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.175812] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.175828] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.175903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.175934] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:47 GLK-2-GLKRVP1DDR405 kernel: [ 930.179992] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.384340] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.384462] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.390484] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.390588] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.390689] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.442547] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.442646] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.442737] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.442877] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.442984] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.443106] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.443230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.443327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.443420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.443512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.443606] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.443701] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.443793] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.443898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.444005] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.444097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.444245] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.444349] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.444447] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.444556] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.453536] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.453661] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.453845] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.453982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.454083] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.454256] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.470936] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.471469] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.471563] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.471705] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.471834] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.471960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.472057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.472734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.472827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.472919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.473010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.473106] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.473201] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.473294] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.473386] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.486874] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.487000] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.487173] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.487311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.487411] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.487561] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.487665] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.487801] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.504988] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.505143] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.505274] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.505402] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.505535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.505632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.505730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.505823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.505917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.506009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.506108] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.506202] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.506294] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.506385] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.506487] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.506582] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.506695] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.516174] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.522578] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.522599] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.522669] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.522698] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.522715] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.522749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.522789] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.522818] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.522850] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.522885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.522918] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.522948] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.522981] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523040] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523068] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523081] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523109] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523121] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523151] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523179] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523207] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523235] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523263] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523299] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523326] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523357] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523388] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523418] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523449] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523480] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523543] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523579] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523611] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.523956] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524377] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524408] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524440] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524494] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524525] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524730] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524767] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 930.524800] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.068347] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.068455] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.068552] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.068647] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.170606] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.170717] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.170825] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.170999] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.271145] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.271245] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.271344] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.271497] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.271604] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.271710] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.273284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.273378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.273474] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.274188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.274277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.274931] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.275022] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.275984] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.276078] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.277194] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.277313] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.277412] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.277507] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.277607] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.294164] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.294252] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:48 GLK-2-GLKRVP1DDR405 kernel: [ 931.294399] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.544216] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.544359] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.544512] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.544614] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.544786] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.752346] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.752473] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.760527] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.760631] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.760734] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.811106] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.811208] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.811299] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.811448] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.811575] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.811703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.811803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.811901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.811995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.812086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.812225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.812328] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.812431] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.812528] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.812620] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.812730] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.812832] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.812984] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.813094] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.813545] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.813645] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.813745] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.813876] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.822630] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.826825] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.830887] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.835010] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.908401] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.908433] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.908465] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.908499] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990360] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990434] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990464] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990480] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990517] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990557] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990586] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990617] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990652] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990686] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990716] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990750] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990781] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990809] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990837] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990850] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990878] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990891] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990920] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990948] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.990979] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.991007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.991035] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.991071] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.991099] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.991130] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.991163] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.991193] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.991224] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.991255] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.991287] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.991318] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.991354] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.991385] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.992247] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.992279] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993210] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993261] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993585] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993618] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993646] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993699] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993727] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993851] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993888] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:49 GLK-2-GLKRVP1DDR405 kernel: [ 931.993919] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.444343] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.444452] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.444550] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.444645] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.546592] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.546704] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.546809] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.546985] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.647063] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.647163] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.647261] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.647369] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.647477] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.647581] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.649239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.649333] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.649429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.650108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.650198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.650854] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.650946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.651911] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.652006] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.652708] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.652835] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.652932] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.653030] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.653132] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.669778] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.669896] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.670049] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.919718] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.919804] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 932.919865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 933.186293] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 933.186380] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:50 GLK-2-GLKRVP1DDR405 kernel: [ 933.186441] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.452743] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.452829] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.452890] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.719173] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.719366] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.719523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.719626] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.719804] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.924347] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.924474] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.935950] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.936055] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.936223] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.987061] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.987162] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.987256] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.987408] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.987536] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.987663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.987764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.987862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.987955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.988048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.988202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.988305] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.988406] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.988502] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.988598] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.988700] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.988804] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.988914] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.989005] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.989100] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.989209] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.989297] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.989402] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.989492] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.989634] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.989744] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.990211] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.990243] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.991472] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.991576] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.991671] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.992530] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.993792] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.993814] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.993874] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.993918] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.993940] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.993988] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994045] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994089] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994135] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994180] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994224] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994267] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994311] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994353] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994395] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994415] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994457] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994476] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994520] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994563] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994605] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994647] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994689] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994736] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994778] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994820] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994862] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994905] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994947] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.994989] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.995035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.995078] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.995129] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.995174] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.997244] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.997390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.997440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.997491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.997538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.997582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.997627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.997676] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.997722] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.997769] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.997844] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.997891] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.998035] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.998093] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:51 GLK-2-GLKRVP1DDR405 kernel: [ 933.998140] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.620361] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.620470] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.620567] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.620662] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.722602] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.722714] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.722820] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.722991] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.821849] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.821948] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.822046] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.822153] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.822262] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.822366] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.823545] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.823638] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.823733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.824518] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.824615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.825588] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.825685] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.826285] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.826419] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.826516] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.826615] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.832295] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.832357] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.832406] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.843379] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.843467] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 934.843590] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 935.093376] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:52 GLK-2-GLKRVP1DDR405 kernel: [ 935.343174] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 935.379974] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 935.407095] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 935.407116] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 935.659580] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 935.909380] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.159164] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.175702] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.175718] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220519] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220552] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220625] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220654] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220689] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220723] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220753] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220786] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220817] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220844] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220872] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220894] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220922] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220935] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220964] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.220991] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221019] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221046] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221074] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221113] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221140] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221171] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221201] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221232] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221262] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221292] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221324] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221370] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221399] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221430] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221461] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221489] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221516] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221543] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221570] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221583] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221611] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221624] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221655] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221682] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221710] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221737] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221764] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221794] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221822] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221852] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221880] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221910] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221940] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.221970] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.222001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.222032] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.222071] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.222100] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.222133] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.222161] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.222195] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.222223] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:48:53 GLK-2-GLKRVP1DDR405 kernel: [ 936.222438] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.428349] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.428477] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.444528] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.444633] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.444737] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.495133] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.495235] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.495329] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.495471] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.495582] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.495707] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.495807] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.495947] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.496223] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.497146] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.497280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.497377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.497471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.497566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.497660] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.497765] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.497858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.497952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.498056] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.498153] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.498251] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.498354] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.498448] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.498586] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.498682] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.499029] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.499132] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 936.499229] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.116394] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.116502] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.116600] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.116695] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.218592] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.218704] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.218809] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.218946] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.317844] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.317944] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.318041] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.318194] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.318301] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.318405] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.319581] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.319673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.319768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.320714] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.320818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.321800] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.321897] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.322356] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.322472] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.322568] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.322663] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.328340] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.328439] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.328533] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.339379] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.339465] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.339652] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.339743] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.340342] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.341023] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.341525] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.341596] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.342096] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.342193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.342270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.342352] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.342425] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.342949] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.343120] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.343612] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.343683] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.344305] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.344398] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.344474] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.344547] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.345109] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.345297] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.345810] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.345897] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.346452] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.346549] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.346642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.346730] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.347275] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.347760] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.348210] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.348241] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.348732] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.348769] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.349126] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.349158] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.349606] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.349802] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.349869] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.349943] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.349975] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.350099] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.350309] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.350828] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.350865] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.350904] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.350939] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.367889] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.367964] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.368065] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.368247] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.368306] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.368395] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.368488] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.368550] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:54 GLK-2-GLKRVP1DDR405 kernel: [ 937.368645] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.512242] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.512400] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.512474] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.514749] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.532582] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.536551] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.536631] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.536693] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.537204] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.537224] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.755989] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.757485] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.757533] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.761979] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.762108] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.762231] [drm:drm_mode_addfb2 [drm]] [FB:155] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.763982] [drm:drm_mode_addfb2 [drm]] [FB:156] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.776585] [drm:drm_mode_addfb2 [drm]] [FB:157] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.778716] [drm:drm_mode_addfb2 [drm]] [FB:158] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.778834] [drm:drm_mode_addfb2 [drm]] [FB:159] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.778893] [drm:drm_mode_addfb2 [drm]] [FB:160] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.778909] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.778986] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.779020] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.779264] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.984339] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.984462] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.990487] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.990591] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 937.990690] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.041861] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.041959] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.042050] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.042191] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.042298] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.042420] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.042543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.042640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.042733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.042824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.042914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.043004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.043098] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.043192] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.043285] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.043391] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.043547] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.043642] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.043736] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.043896] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.051202] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.051328] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.051514] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.051650] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.051750] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.051924] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.068885] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.069418] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.069512] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.069655] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.069782] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.069906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.070003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.070098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.070190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.070281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.070371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.070466] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.070561] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.070655] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.070747] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.084474] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.084600] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.084771] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.084906] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.085005] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.085149] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.085250] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.085383] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.102102] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.102257] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.102389] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.102515] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.102649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.102746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.102844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.102938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.103030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.103123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.103222] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.103317] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.103410] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.103502] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.103603] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.103698] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.103810] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.103905] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.104000] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.104087] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.104220] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.109861] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115043] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115070] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115157] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115202] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115225] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115335] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115379] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115426] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115477] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115526] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115571] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115620] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115666] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115709] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115751] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115770] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115813] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115832] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115877] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115919] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.115965] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.116007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.116050] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.116113] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.116160] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.116208] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.116257] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.116305] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.116353] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.116402] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.116455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.116505] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.116561] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.116607] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.117381] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.117425] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.118367] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.118415] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.118570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.118601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.118632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.118660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.118691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.118721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.118749] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.118781] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.118809] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.118863] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.118891] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.119016] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.119054] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:55 GLK-2-GLKRVP1DDR405 kernel: [ 938.119084] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.652369] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.652477] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.652573] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.652669] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.754600] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.754710] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.754815] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.754977] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.854222] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.854322] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.854420] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.854527] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.854637] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.854742] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.855956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.856057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.856192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.857408] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.857502] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.858468] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.858564] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.859163] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.859299] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.859396] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.859491] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.864158] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.876192] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.876275] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 938.876393] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 939.126175] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 939.126319] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 939.126471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 939.126571] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 939.126741] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 939.332340] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 939.332465] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 939.343935] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 939.344039] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:56 GLK-2-GLKRVP1DDR405 kernel: [ 939.344204] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.396328] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.396428] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.396522] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.396672] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.396801] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.396929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.397027] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.397124] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.397220] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.397335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.397445] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.397546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.397642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.397736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.397831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.397929] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.398025] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.398119] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.398211] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.398310] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.398417] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.398519] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.398612] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.398702] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.398794] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.398941] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.399051] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.405840] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.412144] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.414895] [drm:drm_mode_addfb2 [drm]] [FB:153] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.418314] [drm:drm_mode_addfb2 [drm]] [FB:161] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579396] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579485] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579515] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579531] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579605] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579634] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579665] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579702] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579735] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579765] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579799] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579828] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579857] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579885] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579898] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579929] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579942] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579971] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.579999] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580030] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580126] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580163] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580195] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580230] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580265] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580301] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580336] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580370] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580441] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580479] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.580510] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.581263] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.581290] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582240] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582274] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582596] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582628] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582657] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582710] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582742] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582864] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582902] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 939.582932] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.028355] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.028463] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.028561] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.028657] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.130597] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.130710] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.130817] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.130997] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.231019] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.231117] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.231216] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.231323] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.231430] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.231534] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.233178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.233272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.233368] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.234045] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.234133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.234790] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.234881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.235844] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.235939] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.236561] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.236630] [drm:intel_edp_backlight_on [i915]] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.236680] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.236730] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.236784] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.253567] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.253655] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:57 GLK-2-GLKRVP1DDR405 kernel: [ 940.253778] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 940.503619] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 940.503694] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 940.503745] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 940.770127] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 940.770213] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 940.770276] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 941.036552] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 941.036639] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 941.036701] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 941.303027] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 941.303222] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 941.303380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 941.303481] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:58 GLK-2-GLKRVP1DDR405 kernel: [ 941.303643] [drm:intel_edp_backlight_off [i915]] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.508347] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.508475] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.519949] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.520054] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.520227] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.571052] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.571151] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.571243] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.571396] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.571524] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.571653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.571754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.571852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.571945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.572038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.572190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.572293] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.572391] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.572488] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.572586] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.572691] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.572796] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.572904] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.572995] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.573091] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.573195] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.573284] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.573387] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.573477] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.573615] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.573735] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.573845] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.574336] Setting dangerous option enable_psr - tainting kernel Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.575518] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.575590] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.576493] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.577848] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.577883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.577983] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578058] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578094] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578174] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578269] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578344] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578499] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578574] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578648] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578722] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578794] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578866] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578899] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.578971] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579004] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579079] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579151] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579223] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579295] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579366] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579445] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579517] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579592] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579670] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579742] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579813] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579887] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.579964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.580039] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.580144] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.580224] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.580506] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.580799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.580875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.580949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.581021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.581094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.581170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.581245] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.581320] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.581397] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.581511] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.581587] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.581974] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.582061] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 941.582141] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 942.204334] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 942.204443] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 942.204541] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 942.204636] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 942.306501] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 942.306612] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 942.306718] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:48:59 GLK-2-GLKRVP1DDR405 kernel: [ 942.306891] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.407058] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.407157] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.407256] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.407363] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.407472] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.407577] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.409228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.409322] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.409417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.410098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.410188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.410841] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.410933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.411895] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.411991] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.412706] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.412848] [drm:intel_edp_backlight_on [i915]] Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.412946] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.413042] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.413300] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.429788] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.429883] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.430015] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.679849] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 942.929539] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.179441] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.196084] Setting dangerous option enable_psr - tainting kernel Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.196104] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.207337] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.207414] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.207497] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.207573] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.207640] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.207717] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.207790] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.207859] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.207931] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.208000] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.208065] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.208211] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.208261] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.208347] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.208385] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.208469] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.208550] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.208633] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.208719] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.208800] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.208897] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.208980] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.209068] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.209152] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.209235] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.209320] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.209402] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.210538] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.210612] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.210661] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.210711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.210761] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.210808] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.210854] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.210899] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.210944] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.210966] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211011] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211032] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211079] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211124] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211169] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211214] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211258] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211308] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211353] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211399] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211444] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211488] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211533] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211578] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211675] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211736] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211782] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211830] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211875] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211926] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.211971] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:49:00 GLK-2-GLKRVP1DDR405 kernel: [ 943.213014] [drm:intel_edp_backlight_off [i915]] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.420357] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.420483] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.429250] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.429355] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.429458] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.480312] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.480412] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.480506] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.480659] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.480787] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.480886] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.481024] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.481294] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.481534] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.481666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.481762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.481860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.481954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.482047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.482140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.482234] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.482327] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.482422] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.482518] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.482614] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.482721] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.482831] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.482967] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.483061] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.483358] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.483449] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 943.483535] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.092349] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.092457] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.092553] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.092649] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.194596] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.194709] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.194814] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.194990] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.293767] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.293868] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.293966] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.294119] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.294226] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.294330] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.295513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.295605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.295697] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.296637] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.296733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.297703] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.297797] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.298256] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.298371] [drm:intel_edp_backlight_on [i915]] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.298469] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.298563] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.304289] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.304352] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.304402] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.315249] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.315308] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.315465] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.315531] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.316003] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.316654] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.317148] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.317216] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.317709] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.317797] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.317866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.317941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.318005] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.318523] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.318688] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.319172] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.319236] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.319763] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.319843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.319908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.319972] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.320485] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.320657] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.321144] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.321208] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.321736] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.321807] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.321876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.321940] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.322458] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.322919] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.323404] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.323468] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.323995] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.324068] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.324492] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.324558] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.325029] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.325246] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.325358] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.325452] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.325500] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.325641] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.325886] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.326411] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.326461] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.326515] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.326560] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.343425] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.343488] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.343589] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.343687] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.343739] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.343815] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.343912] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.343959] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:49:01 GLK-2-GLKRVP1DDR405 kernel: [ 944.344035] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.482866] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.482993] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.483110] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.486440] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.505584] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.509569] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.509649] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.509713] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.510220] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.510240] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.715043] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.716293] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.716341] Setting dangerous option enable_psr - tainting kernel Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.725076] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.725419] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.725599] [drm:drm_mode_addfb2 [drm]] [FB:155] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.729326] [drm:drm_mode_addfb2 [drm]] [FB:156] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.746335] [drm:drm_mode_addfb2 [drm]] [FB:157] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.750411] [drm:drm_mode_addfb2 [drm]] [FB:158] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.750491] [drm:drm_mode_addfb2 [drm]] [FB:159] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.750555] [drm:drm_mode_addfb2 [drm]] [FB:160] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.750571] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.750647] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.750682] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.750923] [drm:intel_edp_backlight_off [i915]] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.956211] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.956333] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.965071] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.965176] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 944.965277] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.016339] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.016436] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.016526] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.016668] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.016775] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.016897] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.017020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.017117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.017211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.017303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.017395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.017486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.017581] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.017678] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.017772] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.017880] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.018175] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.018281] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.018383] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.018531] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.026783] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.026909] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.027099] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.027235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.027335] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.027510] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.044233] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.044769] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.044862] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.045005] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.045131] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.045257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.045353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.045450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.045541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.045631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.045721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.045816] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.045911] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.046005] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.046096] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.060123] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.060289] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.060462] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.060601] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.060702] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.060854] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.060958] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.061095] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.077985] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.078139] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.078270] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.078397] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.078532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.078631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.078729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.078823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.078916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.079009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.079109] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.079205] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.079298] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.079390] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.079492] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.079587] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.079698] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.079794] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.079889] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.079979] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.080069] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.089934] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.093584] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.093606] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.093675] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.093704] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.093722] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.093757] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.093796] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.093825] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.093856] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.093891] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.093924] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.093954] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.093987] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094018] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094046] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094074] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094087] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094115] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094127] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094156] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094184] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094214] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094242] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094270] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094306] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094334] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094366] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094398] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094429] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094460] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094490] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094552] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094588] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.094620] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.095463] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.095490] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.096476] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.096514] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097512] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097544] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097572] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097625] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097654] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097780] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097818] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:49:02 GLK-2-GLKRVP1DDR405 kernel: [ 945.097849] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.628349] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.628458] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.628554] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.628649] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.730584] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.730696] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.730802] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.730978] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.829819] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.829919] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.830017] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.830125] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.830232] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.830336] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.831524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.831615] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.831710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.832517] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.832610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.833591] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.833686] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.834291] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.834420] [drm:intel_edp_backlight_on [i915]] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.834516] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.834611] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.840158] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.851352] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.851449] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 945.851581] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.101413] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.101561] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.101716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.101817] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.101979] [drm:intel_edp_backlight_off [i915]] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.308347] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.308475] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.319939] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.320044] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.320217] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.371273] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.371374] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.371468] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.371619] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.371746] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.371874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.371976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.372074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.372228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.372328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.372428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.372532] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.372635] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.372734] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.372827] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.372934] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.373032] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.373130] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.373229] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.373350] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.373452] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.373545] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.373637] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.373730] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.373875] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.373986] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:49:03 GLK-2-GLKRVP1DDR405 kernel: [ 946.375297] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.382516] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.387187] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.393146] [drm:drm_mode_addfb2 [drm]] [FB:153] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.398459] [drm:drm_mode_addfb2 [drm]] [FB:161] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551403] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551423] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551492] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551522] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551539] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551574] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551613] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551643] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551674] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551710] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551745] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551775] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551841] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551869] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551897] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551910] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551938] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551954] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.551983] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552012] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552060] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552099] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552131] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552169] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552201] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552239] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552273] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552307] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552341] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552375] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552413] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552449] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552489] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.552520] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.553373] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.553400] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554355] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554388] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554715] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554747] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554776] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554830] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554858] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.554983] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.555020] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 946.555051] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.004354] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.004462] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.004559] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.004655] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.106594] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.106706] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.106812] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.106988] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.205781] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.205881] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.205979] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.206088] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.206197] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.206302] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.207477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.207569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.207664] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.208704] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.208801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.209810] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.209905] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.210503] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.210639] [drm:intel_edp_backlight_on [i915]] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.210736] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.210831] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.216183] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.227573] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.227690] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:04 GLK-2-GLKRVP1DDR405 kernel: [ 947.227845] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 947.477631] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 947.477719] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 947.477780] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 947.744055] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 947.744171] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 947.744231] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 948.010529] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 948.010615] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 948.010677] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 948.276926] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 948.277116] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 948.277266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 948.277366] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:49:05 GLK-2-GLKRVP1DDR405 kernel: [ 948.277534] [drm:intel_edp_backlight_off [i915]] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.484333] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.484461] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.493221] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.493326] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.493430] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.545364] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.545465] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.545557] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.545708] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.545836] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.545963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.546063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.546156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.546253] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.546348] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.546442] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.546550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.546659] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.546753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.546845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.546942] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.547037] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.547130] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.547221] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.547320] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.547426] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.547527] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.547620] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.547710] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.547801] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.547947] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.548056] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.548574] Setting dangerous option enable_psr - tainting kernel Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.550424] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.550513] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.551437] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.551824] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.551868] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.551992] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552172] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552248] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552304] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552346] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552436] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552478] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552521] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552605] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552645] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552665] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552705] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552724] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552767] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552808] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552850] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552932] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.552976] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.553018] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.553058] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.553100] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.553140] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.553181] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.553221] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.553266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.553307] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.553357] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.553399] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.555347] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.555605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.555653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.555700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.555744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.555786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.555829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.555874] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.555917] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.555958] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.556028] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.556070] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.556512] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.556565] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 948.556609] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 949.180349] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 949.180457] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 949.180554] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 949.180649] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 949.282598] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 949.282708] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 949.282815] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:49:06 GLK-2-GLKRVP1DDR405 kernel: [ 949.282991] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.381781] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.381881] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.381980] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.382087] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.382194] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.382298] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.383482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.383574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.383669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.384635] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.384729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.385703] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.385797] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.386404] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.386530] [drm:intel_edp_backlight_on [i915]] Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.386626] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.386720] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.392278] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.403450] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.403525] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.403635] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.653550] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 949.903320] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.153075] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.169685] Setting dangerous option enable_psr - tainting kernel Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.169700] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.212452] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.212502] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.212558] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.212607] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.212650] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.212702] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.212752] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.212796] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.212845] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.212890] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.212933] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.212975] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213004] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213047] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213067] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213111] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213154] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213198] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213281] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213337] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213379] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213424] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213469] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213513] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213558] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213602] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213650] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213718] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213762] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213808] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213857] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213899] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213941] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.213983] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214024] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214044] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214086] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214105] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214149] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214191] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214235] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214277] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214318] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214364] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214406] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214451] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214493] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214537] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214582] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214626] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214674] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214720] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214777] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214822] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214870] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214913] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.214964] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.215007] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:49:07 GLK-2-GLKRVP1DDR405 kernel: [ 950.215259] [drm:intel_edp_backlight_off [i915]] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.420348] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.420475] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.437386] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.437490] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.437592] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.488577] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.488677] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.488771] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.488920] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.489048] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.489147] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.489286] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.489509] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.489748] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.489880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.489977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.490075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.490169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.490262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.490353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.490447] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.490543] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.490648] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.490740] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.490837] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.490939] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.491087] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.491189] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.491539] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.491641] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.491744] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 950.491843] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.100352] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.100459] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.100556] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.100651] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.202528] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.202639] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.202745] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.202907] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.302878] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.302932] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.302984] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.303054] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.303111] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.303166] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.304445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.304491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.304542] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.305163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.305207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.305801] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.305848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.306749] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.306799] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.307140] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.307202] [drm:intel_edp_backlight_on [i915]] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.307255] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.307303] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.316265] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.316337] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.316395] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.324173] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.324240] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.324403] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.324476] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.324955] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.325613] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.326101] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.326156] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.326639] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.326713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.326772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.326837] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.326891] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.327416] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.327588] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.328081] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.328182] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.328735] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.328835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.328921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.328996] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.329511] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.329682] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.330169] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.330240] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.330768] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.330847] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.330925] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.330996] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.331515] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.331983] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.332487] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.332567] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.333107] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.333194] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.333612] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.333685] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.334190] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.334468] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.334591] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.334730] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.334806] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.334977] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.335309] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.335893] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.335971] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.336053] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.336153] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.352937] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.352997] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.353085] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.353165] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.353215] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.353289] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.353372] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.353432] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:49:08 GLK-2-GLKRVP1DDR405 kernel: [ 951.353502] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.504493] [drm:drm_mode_addfb2 [drm]] [FB:133] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.504650] [drm:drm_mode_addfb2 [drm]] [FB:134] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.504724] [drm:drm_mode_addfb2 [drm]] [FB:136] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.507001] [drm:drm_mode_addfb2 [drm]] [FB:137] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.524745] [drm:drm_mode_addfb2 [drm]] [FB:147] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.528695] [drm:drm_mode_addfb2 [drm]] [FB:148] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.528774] [drm:drm_mode_addfb2 [drm]] [FB:149] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.528836] [drm:drm_mode_addfb2 [drm]] [FB:150] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.529339] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.529358] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.740662] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.741899] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.741945] Setting dangerous option enable_psr - tainting kernel Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.746314] [drm:drm_mode_addfb2 [drm]] [FB:116] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.746458] [drm:drm_mode_addfb2 [drm]] [FB:152] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.746598] [drm:drm_mode_addfb2 [drm]] [FB:155] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.748571] [drm:drm_mode_addfb2 [drm]] [FB:156] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.761233] [drm:drm_mode_addfb2 [drm]] [FB:157] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.763374] [drm:drm_mode_addfb2 [drm]] [FB:158] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.763439] [drm:drm_mode_addfb2 [drm]] [FB:159] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.763500] [drm:drm_mode_addfb2 [drm]] [FB:160] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.763516] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.763589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.763621] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.763845] [drm:intel_edp_backlight_off [i915]] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.968365] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.968486] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.974513] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.974618] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 951.974718] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.026734] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.026833] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.026924] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.027065] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.027173] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.027295] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.027419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.027517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.027613] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.027709] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.027803] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.027909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.028016] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.028110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.028252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.028350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.028452] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.028552] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.028652] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.028764] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.036204] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.036305] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.036467] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.036577] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.036656] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.036798] [drm:intel_disable_pipe [i915]] disabling pipe B Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.052340] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.052867] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.052963] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.053109] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 59 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.053239] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.053364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.053460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.053556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.053647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.053739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.053829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.053925] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.054020] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.054114] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.054206] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.069568] [drm:intel_power_well_disable [i915]] disabling dpio-common-b Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.069693] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.069868] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.070008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.070108] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.070256] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.070359] [drm:i915_audio_component_get_eld [i915]] Not valid for port C Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.070496] [drm:intel_disable_pipe [i915]] disabling pipe C Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.087043] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.087201] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 75 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.087331] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.087459] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 4 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.087593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.087689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.087787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.087881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.087974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.088064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.088816] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.088912] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.089005] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.089096] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.089198] [drm:intel_power_well_disable [i915]] disabling dpio-common-c Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.089293] [drm:intel_power_well_disable [i915]] disabling power well 2 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.089404] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.089499] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.089594] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.089684] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.089773] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.096438] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100138] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100159] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100234] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100265] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100282] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100361] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100393] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100426] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100464] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100499] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100531] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100566] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100629] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100659] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100673] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100703] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100717] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100749] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100781] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100811] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100841] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100871] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100910] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100940] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.100973] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.101006] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.101039] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.101074] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.101107] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.101140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.101176] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.101214] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.101248] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.102008] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.102037] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.102987] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103023] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103363] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103396] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103427] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103482] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103513] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103640] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103680] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:49:09 GLK-2-GLKRVP1DDR405 kernel: [ 952.103713] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.636361] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.636469] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.636565] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.636660] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.738597] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.738708] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.738813] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.738983] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.837892] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.837991] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.838090] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.838198] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.838306] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.838411] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.839588] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.839679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.839771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.841025] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.841117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.842084] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.842180] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.842779] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.842916] [drm:intel_edp_backlight_on [i915]] Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.843012] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.843107] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.848157] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.859829] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.859936] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 952.860078] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 953.109905] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 953.110047] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 953.110199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 953.110298] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 953.110468] [drm:intel_edp_backlight_off [i915]] Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 953.316353] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 953.316478] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 953.327952] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 953.328058] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:49:10 GLK-2-GLKRVP1DDR405 kernel: [ 953.328201] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.380387] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.380486] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.380579] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.380731] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.380858] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.380985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.381083] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.381179] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.381274] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.381388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.381498] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.381596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.381690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.381782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.381874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.381971] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.382065] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.382158] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.382249] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.382348] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.382453] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.382555] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.382648] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.382738] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.382830] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.382980] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.383090] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.389901] [drm:drm_mode_addfb2 [drm]] [FB:127] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.396196] [drm:drm_mode_addfb2 [drm]] [FB:128] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.398918] [drm:drm_mode_addfb2 [drm]] [FB:153] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.402003] [drm:drm_mode_addfb2 [drm]] [FB:161] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.563739] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.563759] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.563826] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.563857] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.563874] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.563911] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.563951] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.563980] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564011] [drm:intel_dp_compute_config [i915]] PSR disable by flag Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564048] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564107] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564140] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564211] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564242] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564273] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564291] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564323] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564336] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564367] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564397] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564429] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564461] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564491] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564527] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564557] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564592] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564624] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564657] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564689] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564720] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564754] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564789] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564830] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.564861] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.565619] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.565647] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.566594] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.566628] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.566770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.566801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.566832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.566860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.566891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.566921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.566949] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.566981] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.567010] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.567063] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.567094] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.567216] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.567253] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 953.567283] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.012353] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.012460] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.012557] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.012653] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.114593] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.114705] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.114811] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.114985] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.213024] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.213124] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.213222] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.213330] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.213437] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.213541] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.214746] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.214849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.214950] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.215619] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.215713] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.217357] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.217455] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.218054] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.218187] [drm:intel_edp_backlight_on [i915]] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.218285] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.218380] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.224154] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.235056] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.235152] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:11 GLK-2-GLKRVP1DDR405 kernel: [ 954.235285] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 954.485063] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 954.485148] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 954.485206] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 954.751595] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 954.751682] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 954.751742] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 955.018065] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 955.018153] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 955.018215] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 955.284543] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 955.284736] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 955.284890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 955.284990] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:49:12 GLK-2-GLKRVP1DDR405 kernel: [ 955.285163] [drm:intel_edp_backlight_off [i915]] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.492347] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.492472] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.501142] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.501246] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.501349] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.552385] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.552485] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.552579] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.552733] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.552862] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.552988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.553089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.553187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.553281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.553374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.553466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.553563] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.553659] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.553752] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.553843] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.553944] [drm:intel_power_well_disable [i915]] disabling dpio-common-a Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.554048] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.554144] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.554240] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.554336] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.554451] [drm:intel_power_well_disable [i915]] disabling DC off Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.554565] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.554656] [drm:gen9_enable_dc5 [i915]] Enabling DC5 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.554746] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.554839] [drm:intel_power_well_disable [i915]] disabling always-on Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.555000] [drm:drm_mode_setcrtc [drm]] [CRTC:59:pipe B] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.555098] [drm:drm_mode_setcrtc [drm]] [CRTC:75:pipe C] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.555521] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.555551] Setting dangerous option enable_psr - tainting kernel Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.557428] [drm:intel_power_well_enable [i915]] enabling always-on Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.557510] [drm:intel_power_well_enable [i915]] enabling DC off Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.558386] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.558744] [drm:drm_mode_setcrtc [drm]] [CRTC:43:pipe A] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.558784] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:77:eDP-1] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.558895] [drm:intel_atomic_check [i915]] [CONNECTOR:77:eDP-1] checking for sink bpp constrains Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.558979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.559022] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.559112] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.559219] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.559302] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.559391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.559478] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe A][modeset] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.559564] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.559647] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.559732] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.559814] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.559895] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.559934] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.560018] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.560055] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.560171] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.560262] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.560350] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.560442] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.560530] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.560626] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.560711] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.560799] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.560886] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.560975] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 3A] disabled, scaler_id = -1 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.561062] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 4A] disabled, scaler_id = -1 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.561146] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor A] disabled, scaler_id = -1 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.561236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.561321] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 4, actual 4 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.561420] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.561505] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.561984] [drm:intel_power_well_enable [i915]] enabling dpio-common-a Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.562169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.562254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.562337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.562418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.562500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.562583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.562667] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.562752] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.562836] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.562965] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.563048] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.563240] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.563334] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 955.563422] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 956.188359] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 956.188467] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 956.188563] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 956.188658] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 956.290603] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 956.290714] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 956.290820] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:49:13 GLK-2-GLKRVP1DDR405 kernel: [ 956.290995] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.389762] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.389862] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.389960] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.390068] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.390175] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.390278] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.391464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.391555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.391650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.392687] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.392783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.393759] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.393854] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.394461] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.394587] [drm:intel_edp_backlight_on [i915]] Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.394684] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.394778] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.400284] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.400357] [drm:intel_fbc_enable [i915]] reserved 8847360 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.400414] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.411508] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.411583] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.411694] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.661563] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 956.911351] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.161159] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.177848] Setting dangerous option enable_psr - tainting kernel Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.177872] Setting dangerous option enable_fbc - tainting kernel Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.224504] [drm:intel_atomic_check [i915]] [CONNECTOR:84:DP-1] checking for sink bpp constrains Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.224597] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.224695] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.224787] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.224868] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.224960] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.225051] [drm:intel_dump_pipe_config [i915]] [CRTC:59:pipe B][modeset] Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.225135] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80) Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.225223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.225307] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.225386] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.225465] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.225513] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.225593] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.225630] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.225713] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.225794] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.225877] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.225956] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.226034] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.226127] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.226207] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.226290] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1B] disabled, scaler_id = -1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.226372] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 2B] disabled, scaler_id = -1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.226453] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 3B] disabled, scaler_id = -1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.226535] [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 4B] disabled, scaler_id = -1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.226616] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor B] disabled, scaler_id = -1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.226703] [drm:intel_atomic_check [i915]] [CONNECTOR:92:HDMI-A-2] checking for sink bpp constrains Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.226827] [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.226910] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 36 for HDMI Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.226995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.227079] [drm:intel_dump_pipe_config [i915]] [CRTC:75:pipe C][modeset] Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.227159] [drm:intel_dump_pipe_config [i915]] output_types: HDMI (0x40) Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.227239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 36, dithering: 0 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.227317] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.227395] [drm:intel_dump_pipe_config [i915]] requested mode: Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.227433] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.227512] [drm:intel_dump_pipe_config [i915]] adjusted mode: Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.227549] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x48 0x5 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.227631] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1082 1087 1125, type: 0x48 flags: 0x5 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.227710] [drm:intel_dump_pipe_config [i915]] port clock: 222750, pipe src size: 1920x1080, pixel rate 148500 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.227790] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.227869] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.227947] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.228034] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6200, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.228148] [drm:intel_dump_pipe_config [i915]] planes on this crtc Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.228239] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 1C] disabled, scaler_id = -1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.228322] [drm:intel_dump_pipe_config [i915]] [PLANE:63:plane 2C] disabled, scaler_id = -1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.228410] [drm:intel_dump_pipe_config [i915]] [PLANE:66:plane 3C] disabled, scaler_id = -1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.228494] [drm:intel_dump_pipe_config [i915]] [PLANE:69:plane 4C] disabled, scaler_id = -1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.228581] [drm:intel_dump_pipe_config [i915]] [PLANE:72:cursor C] disabled, scaler_id = -1 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.229329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 316800 kHz, actual 316800 kHz Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.229423] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 13, actual 13 Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.229535] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe A] using pre-allocated PORT PLL A Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.229621] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.229710] [drm:bxt_get_dpll [i915]] [CRTC:59:pipe B] using pre-allocated PORT PLL B Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.229797] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.229890] [drm:bxt_get_dpll [i915]] [CRTC:75:pipe C] using pre-allocated PORT PLL C Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.229971] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C Dec 4 14:49:14 GLK-2-GLKRVP1DDR405 kernel: [ 957.230297] [drm:intel_edp_backlight_off [i915]] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.436353] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.436482] [drm:intel_disable_pipe [i915]] disabling pipe A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.445257] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.445363] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.445465] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.496570] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.496670] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.496764] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.496909] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.497019] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 43 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.497144] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.497244] [drm:intel_power_well_enable [i915]] enabling power well 2 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.497384] [drm:intel_power_well_enable [i915]] enabling dpio-common-b Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.497656] [drm:intel_power_well_enable [i915]] enabling dpio-common-c Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.497896] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 316800 kHz, VCO 633600 kHz, ref 19200 kHz, voltage level 13 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.498028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DDI A] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.498126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:83:DDI B] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.498224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:85:DP-MST A] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.498318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DP-MST B] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.498414] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.498513] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.498608] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.498716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:87:DP-MST C] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.498824] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.498919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.499014] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.499109] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.499202] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.499338] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 43 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.499433] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.499847] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.499950] [drm:edp_panel_on [i915]] Turn eDP port A panel power on Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 957.500047] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.108355] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.108462] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.108559] [drm:edp_panel_on [i915]] Wait for panel power on Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.108654] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.210591] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.210702] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.210808] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.211000] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.309750] [drm:wait_panel_status [i915]] Wait complete Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.309851] [drm:intel_power_well_disable [i915]] disabling AUX A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.309949] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.310102] [drm:intel_power_well_enable [i915]] enabling AUX A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.310210] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.310313] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.311486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.311578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.311673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.312684] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.312778] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.313743] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.313837] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:77:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.314288] [drm:intel_enable_pipe [i915]] enabling pipe A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.314402] [drm:intel_edp_backlight_on [i915]] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.314498] [drm:intel_panel_enable_backlight [i915]] pipe A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.314592] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.320279] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.320356] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.320418] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.331348] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 59 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.331444] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.331642] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.331742] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.332381] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.333067] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.333576] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.333654] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.334158] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.334266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.334352] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.334442] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.334521] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.335060] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.335239] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.335734] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.335813] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.336359] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.336461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.336546] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.336630] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.337158] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.337335] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.337831] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.337909] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.338446] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.338532] [drm:intel_dp_start_link_train [i915]] clock recovery OK Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.338616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.338695] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.339222] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.339697] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.340349] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.340431] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.340975] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.341065] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.341488] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:84:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.341568] [drm:intel_power_well_enable [i915]] enabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.342069] [drm:intel_power_well_disable [i915]] disabling AUX B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.342308] [drm:intel_enable_pipe [i915]] enabling pipe B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.342364] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.342434] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 75 Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.342463] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.342580] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.342790] [drm:intel_enable_pipe [i915]] enabling pipe C Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.343320] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:92:HDMI-A-2], [ENCODER:91:DDI C] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.343352] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.343387] [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000) Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.343418] [drm:hsw_audio_config_update [i915]] using automatic N Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.360388] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:77:eDP-1] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.360461] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe A] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.360564] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL A Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.360659] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:84:DP-1] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.360720] [drm:intel_atomic_commit_tail [i915]] [CRTC:59:pipe B] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.360807] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL B Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.360905] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:92:HDMI-A-2] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.360964] [drm:intel_atomic_commit_tail [i915]] [CRTC:75:pipe C] Dec 4 14:49:15 GLK-2-GLKRVP1DDR405 kernel: [ 958.361058] [drm:verify_single_dpll_state.isra.112 [i915]] PORT PLL C Dec 4 14:49:19 GLK-2-GLKRVP1DDR405 kernel: [ 961.500341] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off Dec 4 14:49:19 GLK-2-GLKRVP1DDR405 kernel: [ 961.500449] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067 Dec 4 14:49:19 GLK-2-GLKRVP1DDR405 kernel: [ 961.500540] [drm:intel_power_well_disable [i915]] disabling AUX A