Mesa warning: couldn't open libtxc_dxtn.so, software DXTn compression/decompression unavailable Mesa warning: couldn't open libtxc_dxtn.so, software DXTn compression/decompression unavailable Mesa warning: couldn't open libtxc_dxtn.so, software DXTn compression/decompression unavailable Mesa warning: couldn't open libtxc_dxtn.so, software DXTn compression/decompression unavailable COMP PROPERTY CS_FIXED_BLOCK_WIDTH 6 PROPERTY CS_FIXED_BLOCK_HEIGHT 1 PROPERTY CS_FIXED_BLOCK_DEPTH 1 DCL SV[0], THREAD_ID DCL BUFFER[8] DCL TEMP[0..2], LOCAL DCL TEMP[3..77], ARRAY(1), LOCAL DCL TEMP[78..154], LOCAL DCL ADDR[0] IMM[0] UINT32 {6, 304, 1200, 896} IMM[1] UINT32 {892, 888, 884, 880} IMM[2] UINT32 {876, 872, 868, 864} IMM[3] UINT32 {860, 856, 852, 848} IMM[4] UINT32 {844, 840, 836, 832} IMM[5] UINT32 {828, 824, 820, 816} IMM[6] UINT32 {812, 808, 804, 800} IMM[7] UINT32 {496, 492, 488, 484} IMM[8] UINT32 {480, 476, 472, 468} IMM[9] UINT32 {464, 460, 456, 452} IMM[10] UINT32 {448, 444, 440, 436} IMM[11] UINT32 {432, 428, 424, 420} IMM[12] UINT32 {416, 412, 408, 404} IMM[13] UINT32 {400, 96, 92, 88} IMM[14] UINT32 {84, 80, 76, 72} IMM[15] UINT32 {68, 64, 60, 56} IMM[16] UINT32 {52, 48, 44, 40} IMM[17] UINT32 {36, 32, 28, 24} IMM[18] UINT32 {20, 16, 12, 8} IMM[19] UINT32 {4, 0, 0, 0} 0: UMUL TEMP[0].x, SV[0].yyyy, IMM[0].xxxx 1: UMAD TEMP[1].x, SV[0].zzzz, IMM[0].xxxx, TEMP[0].xxxx 2: UADD TEMP[2].x, TEMP[1].xxxx, SV[0].xxxx 3: UARL ADDR[0].x, TEMP[2].xxxx 4: U2F TEMP[ADDR[0].x+3](1).x, TEMP[2].xxxx 5: UARL ADDR[0].x, TEMP[2].xxxx 6: U2F TEMP[ADDR[0].x+28](1).x, TEMP[2].xxxx 7: UARL ADDR[0].x, TEMP[2].xxxx 8: U2F TEMP[ADDR[0].x+53](1).x, TEMP[2].xxxx 9: UMUL TEMP[78].x, TEMP[2].xxxx, IMM[0].yyyy 10: UADD TEMP[79].x, TEMP[78].xxxx, IMM[0].zzzz 11: U2F TEMP[80].x, TEMP[2].xxxx 12: STORE BUFFER[8].x, TEMP[79].xxxx, TEMP[80].xxxx 13: UADD TEMP[81].x, TEMP[78].xxxx, IMM[0].wwww 14: STORE BUFFER[8].x, TEMP[81].xxxx, TEMP[77] 15: UADD TEMP[82].x, TEMP[78].xxxx, IMM[1].xxxx 16: STORE BUFFER[8].x, TEMP[82].xxxx, TEMP[76] 17: UADD TEMP[83].x, TEMP[78].xxxx, IMM[1].yyyy 18: STORE BUFFER[8].x, TEMP[83].xxxx, TEMP[75] 19: UADD TEMP[84].x, TEMP[78].xxxx, IMM[1].zzzz 20: STORE BUFFER[8].x, TEMP[84].xxxx, TEMP[74] 21: UADD TEMP[85].x, TEMP[78].xxxx, IMM[1].wwww 22: STORE BUFFER[8].x, TEMP[85].xxxx, TEMP[73] 23: UADD TEMP[86].x, TEMP[78].xxxx, IMM[2].xxxx 24: STORE BUFFER[8].x, TEMP[86].xxxx, TEMP[72] 25: UADD TEMP[87].x, TEMP[78].xxxx, IMM[2].yyyy 26: STORE BUFFER[8].x, TEMP[87].xxxx, TEMP[71] 27: UADD TEMP[88].x, TEMP[78].xxxx, IMM[2].zzzz 28: STORE BUFFER[8].x, TEMP[88].xxxx, TEMP[70] 29: UADD TEMP[89].x, TEMP[78].xxxx, IMM[2].wwww 30: STORE BUFFER[8].x, TEMP[89].xxxx, TEMP[69] 31: UADD TEMP[90].x, TEMP[78].xxxx, IMM[3].xxxx 32: STORE BUFFER[8].x, TEMP[90].xxxx, TEMP[68] 33: UADD TEMP[91].x, TEMP[78].xxxx, IMM[3].yyyy 34: STORE BUFFER[8].x, TEMP[91].xxxx, TEMP[67] 35: UADD TEMP[92].x, TEMP[78].xxxx, IMM[3].zzzz 36: STORE BUFFER[8].x, TEMP[92].xxxx, TEMP[66] 37: UADD TEMP[93].x, TEMP[78].xxxx, IMM[3].wwww 38: STORE BUFFER[8].x, TEMP[93].xxxx, TEMP[65] 39: UADD TEMP[94].x, TEMP[78].xxxx, IMM[4].xxxx 40: STORE BUFFER[8].x, TEMP[94].xxxx, TEMP[64] 41: UADD TEMP[95].x, TEMP[78].xxxx, IMM[4].yyyy 42: STORE BUFFER[8].x, TEMP[95].xxxx, TEMP[63] 43: UADD TEMP[96].x, TEMP[78].xxxx, IMM[4].zzzz 44: STORE BUFFER[8].x, TEMP[96].xxxx, TEMP[62] 45: UADD TEMP[97].x, TEMP[78].xxxx, IMM[4].wwww 46: STORE BUFFER[8].x, TEMP[97].xxxx, TEMP[61] 47: UADD TEMP[98].x, TEMP[78].xxxx, IMM[5].xxxx 48: STORE BUFFER[8].x, TEMP[98].xxxx, TEMP[60] 49: UADD TEMP[99].x, TEMP[78].xxxx, IMM[5].yyyy 50: STORE BUFFER[8].x, TEMP[99].xxxx, TEMP[59] 51: UADD TEMP[100].x, TEMP[78].xxxx, IMM[5].zzzz 52: STORE BUFFER[8].x, TEMP[100].xxxx, TEMP[58] 53: UADD TEMP[101].x, TEMP[78].xxxx, IMM[5].wwww 54: STORE BUFFER[8].x, TEMP[101].xxxx, TEMP[57] 55: UADD TEMP[102].x, TEMP[78].xxxx, IMM[6].xxxx 56: STORE BUFFER[8].x, TEMP[102].xxxx, TEMP[56] 57: UADD TEMP[103].x, TEMP[78].xxxx, IMM[6].yyyy 58: STORE BUFFER[8].x, TEMP[103].xxxx, TEMP[55] 59: UADD TEMP[104].x, TEMP[78].xxxx, IMM[6].zzzz 60: STORE BUFFER[8].x, TEMP[104].xxxx, TEMP[54] 61: UADD TEMP[105].x, TEMP[78].xxxx, IMM[6].wwww 62: STORE BUFFER[8].x, TEMP[105].xxxx, TEMP[53] 63: UADD TEMP[106].x, TEMP[78].xxxx, IMM[7].xxxx 64: STORE BUFFER[8].x, TEMP[106].xxxx, TEMP[52] 65: UADD TEMP[107].x, TEMP[78].xxxx, IMM[7].yyyy 66: STORE BUFFER[8].x, TEMP[107].xxxx, TEMP[51] 67: UADD TEMP[108].x, TEMP[78].xxxx, IMM[7].zzzz 68: STORE BUFFER[8].x, TEMP[108].xxxx, TEMP[50] 69: UADD TEMP[109].x, TEMP[78].xxxx, IMM[7].wwww 70: STORE BUFFER[8].x, TEMP[109].xxxx, TEMP[49] 71: UADD TEMP[110].x, TEMP[78].xxxx, IMM[8].xxxx 72: STORE BUFFER[8].x, TEMP[110].xxxx, TEMP[48] 73: UADD TEMP[111].x, TEMP[78].xxxx, IMM[8].yyyy 74: STORE BUFFER[8].x, TEMP[111].xxxx, TEMP[47] 75: UADD TEMP[112].x, TEMP[78].xxxx, IMM[8].zzzz 76: STORE BUFFER[8].x, TEMP[112].xxxx, TEMP[46] 77: UADD TEMP[113].x, TEMP[78].xxxx, IMM[8].wwww 78: STORE BUFFER[8].x, TEMP[113].xxxx, TEMP[45] 79: UADD TEMP[114].x, TEMP[78].xxxx, IMM[9].xxxx 80: STORE BUFFER[8].x, TEMP[114].xxxx, TEMP[44] 81: UADD TEMP[115].x, TEMP[78].xxxx, IMM[9].yyyy 82: STORE BUFFER[8].x, TEMP[115].xxxx, TEMP[43] 83: UADD TEMP[116].x, TEMP[78].xxxx, IMM[9].zzzz 84: STORE BUFFER[8].x, TEMP[116].xxxx, TEMP[42] 85: UADD TEMP[117].x, TEMP[78].xxxx, IMM[9].wwww 86: STORE BUFFER[8].x, TEMP[117].xxxx, TEMP[41] 87: UADD TEMP[118].x, TEMP[78].xxxx, IMM[10].xxxx 88: STORE BUFFER[8].x, TEMP[118].xxxx, TEMP[40] 89: UADD TEMP[119].x, TEMP[78].xxxx, IMM[10].yyyy 90: STORE BUFFER[8].x, TEMP[119].xxxx, TEMP[39] 91: UADD TEMP[120].x, TEMP[78].xxxx, IMM[10].zzzz 92: STORE BUFFER[8].x, TEMP[120].xxxx, TEMP[38] 93: UADD TEMP[121].x, TEMP[78].xxxx, IMM[10].wwww 94: STORE BUFFER[8].x, TEMP[121].xxxx, TEMP[37] 95: UADD TEMP[122].x, TEMP[78].xxxx, IMM[11].xxxx 96: STORE BUFFER[8].x, TEMP[122].xxxx, TEMP[36] 97: UADD TEMP[123].x, TEMP[78].xxxx, IMM[11].yyyy 98: STORE BUFFER[8].x, TEMP[123].xxxx, TEMP[35] 99: UADD TEMP[124].x, TEMP[78].xxxx, IMM[11].zzzz 100: STORE BUFFER[8].x, TEMP[124].xxxx, TEMP[34] 101: UADD TEMP[125].x, TEMP[78].xxxx, IMM[11].wwww 102: STORE BUFFER[8].x, TEMP[125].xxxx, TEMP[33] 103: UADD TEMP[126].x, TEMP[78].xxxx, IMM[12].xxxx 104: STORE BUFFER[8].x, TEMP[126].xxxx, TEMP[32] 105: UADD TEMP[127].x, TEMP[78].xxxx, IMM[12].yyyy 106: STORE BUFFER[8].x, TEMP[127].xxxx, TEMP[31] 107: UADD TEMP[128].x, TEMP[78].xxxx, IMM[12].zzzz 108: STORE BUFFER[8].x, TEMP[128].xxxx, TEMP[30] 109: UADD TEMP[129].x, TEMP[78].xxxx, IMM[12].wwww 110: STORE BUFFER[8].x, TEMP[129].xxxx, TEMP[29] 111: UADD TEMP[130].x, TEMP[78].xxxx, IMM[13].xxxx 112: STORE BUFFER[8].x, TEMP[130].xxxx, TEMP[28] 113: UADD TEMP[131].x, TEMP[78].xxxx, IMM[13].yyyy 114: STORE BUFFER[8].x, TEMP[131].xxxx, TEMP[27] 115: UADD TEMP[132].x, TEMP[78].xxxx, IMM[13].zzzz 116: STORE BUFFER[8].x, TEMP[132].xxxx, TEMP[26] 117: UADD TEMP[133].x, TEMP[78].xxxx, IMM[13].wwww 118: STORE BUFFER[8].x, TEMP[133].xxxx, TEMP[25] 119: UADD TEMP[134].x, TEMP[78].xxxx, IMM[14].xxxx 120: STORE BUFFER[8].x, TEMP[134].xxxx, TEMP[24] 121: UADD TEMP[135].x, TEMP[78].xxxx, IMM[14].yyyy 122: STORE BUFFER[8].x, TEMP[135].xxxx, TEMP[23] 123: UADD TEMP[136].x, TEMP[78].xxxx, IMM[14].zzzz 124: STORE BUFFER[8].x, TEMP[136].xxxx, TEMP[22] 125: UADD TEMP[137].x, TEMP[78].xxxx, IMM[14].wwww 126: STORE BUFFER[8].x, TEMP[137].xxxx, TEMP[21] 127: UADD TEMP[138].x, TEMP[78].xxxx, IMM[15].xxxx 128: STORE BUFFER[8].x, TEMP[138].xxxx, TEMP[20] 129: UADD TEMP[139].x, TEMP[78].xxxx, IMM[15].yyyy 130: STORE BUFFER[8].x, TEMP[139].xxxx, TEMP[19] 131: UADD TEMP[140].x, TEMP[78].xxxx, IMM[15].zzzz 132: STORE BUFFER[8].x, TEMP[140].xxxx, TEMP[18] 133: UADD TEMP[141].x, TEMP[78].xxxx, IMM[15].wwww 134: STORE BUFFER[8].x, TEMP[141].xxxx, TEMP[17] 135: UADD TEMP[142].x, TEMP[78].xxxx, IMM[16].xxxx 136: STORE BUFFER[8].x, TEMP[142].xxxx, TEMP[16] 137: UADD TEMP[143].x, TEMP[78].xxxx, IMM[16].yyyy 138: STORE BUFFER[8].x, TEMP[143].xxxx, TEMP[15] 139: UADD TEMP[144].x, TEMP[78].xxxx, IMM[16].zzzz 140: STORE BUFFER[8].x, TEMP[144].xxxx, TEMP[14] 141: UADD TEMP[145].x, TEMP[78].xxxx, IMM[16].wwww 142: STORE BUFFER[8].x, TEMP[145].xxxx, TEMP[13] 143: UADD TEMP[146].x, TEMP[78].xxxx, IMM[17].xxxx 144: STORE BUFFER[8].x, TEMP[146].xxxx, TEMP[12] 145: UADD TEMP[147].x, TEMP[78].xxxx, IMM[17].yyyy 146: STORE BUFFER[8].x, TEMP[147].xxxx, TEMP[11] 147: UADD TEMP[148].x, TEMP[78].xxxx, IMM[17].zzzz 148: STORE BUFFER[8].x, TEMP[148].xxxx, TEMP[10] 149: UADD TEMP[149].x, TEMP[78].xxxx, IMM[17].wwww 150: STORE BUFFER[8].x, TEMP[149].xxxx, TEMP[9] 151: UADD TEMP[150].x, TEMP[78].xxxx, IMM[18].xxxx 152: STORE BUFFER[8].x, TEMP[150].xxxx, TEMP[8] 153: UADD TEMP[151].x, TEMP[78].xxxx, IMM[18].yyyy 154: STORE BUFFER[8].x, TEMP[151].xxxx, TEMP[7] 155: UADD TEMP[152].x, TEMP[78].xxxx, IMM[18].zzzz 156: STORE BUFFER[8].x, TEMP[152].xxxx, TEMP[6] 157: UADD TEMP[153].x, TEMP[78].xxxx, IMM[18].wwww 158: STORE BUFFER[8].x, TEMP[153].xxxx, TEMP[5] 159: UADD TEMP[154].x, TEMP[78].xxxx, IMM[19].xxxx 160: STORE BUFFER[8].x, TEMP[154].xxxx, TEMP[4] 161: STORE BUFFER[8].x, TEMP[78].xxxx, TEMP[3] 162: END radeonsi: Compiling shader 1 TGSI shader LLVM IR: ; ModuleID = 'tgsi' source_filename = "tgsi" target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" target triple = "amdgcn--" define amdgpu_cs void @main([12 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), <3 x i32>) #0 { main_body: %array = alloca [75 x float], align 4 %4 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 0 %5 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 1 %6 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 2 %7 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 3 %8 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 4 %9 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 5 %10 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 6 %11 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 7 %12 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 8 %13 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 9 %14 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 10 %15 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 11 %16 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 12 %17 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 13 %18 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 14 %19 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 15 %20 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 16 %21 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 17 %22 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 18 %23 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 19 %24 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 20 %25 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 21 %26 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 22 %27 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 23 %28 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 24 %29 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 25 %30 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 26 %31 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 27 %32 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 28 %33 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 29 %34 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 30 %35 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 31 %36 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 32 %37 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 33 %38 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 34 %39 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 35 %40 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 36 %41 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 37 %42 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 38 %43 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 39 %44 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 40 %45 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 41 %46 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 42 %47 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 43 %48 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 44 %49 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 45 %50 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 46 %51 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 47 %52 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 48 %53 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 49 %54 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 50 %55 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 51 %56 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 52 %57 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 53 %58 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 54 %59 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 55 %60 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 56 %61 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 57 %62 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 58 %63 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 59 %64 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 60 %65 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 61 %66 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 62 %67 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 63 %68 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 64 %69 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 65 %70 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 66 %71 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 67 %72 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 68 %73 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 69 %74 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 70 %75 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 71 %76 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 72 %77 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 73 %78 = getelementptr inbounds [75 x float], [75 x float]* %array, i32 0, i32 74 %79 = extractelement <3 x i32> %3, i32 1 %80 = extractelement <3 x i32> %3, i32 2 %81 = add i32 %80, %79 %82 = mul i32 %81, 6 %83 = extractelement <3 x i32> %3, i32 0 %84 = add i32 %82, %83 %85 = uitofp i32 %84 to float %86 = icmp ult i32 %84, 74 %87 = select i1 %86, i32 %84, i32 74 %88 = getelementptr [75 x float], [75 x float]* %array, i32 0, i32 %87 store float %85, float* %88, align 4 %89 = add i32 %84, 25 %90 = icmp ult i32 %89, 74 %91 = select i1 %90, i32 %89, i32 74 %92 = getelementptr [75 x float], [75 x float]* %array, i32 0, i32 %91 store float %85, float* %92, align 4 %93 = add i32 %84, 50 %94 = icmp ult i32 %93, 74 %95 = select i1 %94, i32 %93, i32 74 %96 = getelementptr [75 x float], [75 x float]* %array, i32 0, i32 %95 store float %85, float* %96, align 4 %97 = mul i32 %84, 304 %98 = add i32 %97, 1200 %99 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 7, !amdgpu.uniform !0 %100 = load <4 x i32>, <4 x i32> addrspace(2)* %99, align 16, !invariant.load !0 call void @llvm.amdgcn.buffer.store.f32(float %85, <4 x i32> %100, i32 0, i32 %98, i1 false, i1 false) #2 %101 = add i32 %97, 896 %102 = load float, float* %78, align 4 call void @llvm.amdgcn.buffer.store.f32(float %102, <4 x i32> %100, i32 0, i32 %101, i1 false, i1 false) #2 %103 = add i32 %97, 892 %104 = load float, float* %77, align 4 call void @llvm.amdgcn.buffer.store.f32(float %104, <4 x i32> %100, i32 0, i32 %103, i1 false, i1 false) #2 %105 = add i32 %97, 888 %106 = load float, float* %76, align 4 call void @llvm.amdgcn.buffer.store.f32(float %106, <4 x i32> %100, i32 0, i32 %105, i1 false, i1 false) #2 %107 = add i32 %97, 884 %108 = load float, float* %75, align 4 call void @llvm.amdgcn.buffer.store.f32(float %108, <4 x i32> %100, i32 0, i32 %107, i1 false, i1 false) #2 %109 = add i32 %97, 880 %110 = load float, float* %74, align 4 call void @llvm.amdgcn.buffer.store.f32(float %110, <4 x i32> %100, i32 0, i32 %109, i1 false, i1 false) #2 %111 = add i32 %97, 876 %112 = load float, float* %73, align 4 call void @llvm.amdgcn.buffer.store.f32(float %112, <4 x i32> %100, i32 0, i32 %111, i1 false, i1 false) #2 %113 = add i32 %97, 872 %114 = load float, float* %72, align 4 call void @llvm.amdgcn.buffer.store.f32(float %114, <4 x i32> %100, i32 0, i32 %113, i1 false, i1 false) #2 %115 = add i32 %97, 868 %116 = load float, float* %71, align 4 call void @llvm.amdgcn.buffer.store.f32(float %116, <4 x i32> %100, i32 0, i32 %115, i1 false, i1 false) #2 %117 = add i32 %97, 864 %118 = load float, float* %70, align 4 call void @llvm.amdgcn.buffer.store.f32(float %118, <4 x i32> %100, i32 0, i32 %117, i1 false, i1 false) #2 %119 = add i32 %97, 860 %120 = load float, float* %69, align 4 call void @llvm.amdgcn.buffer.store.f32(float %120, <4 x i32> %100, i32 0, i32 %119, i1 false, i1 false) #2 %121 = add i32 %97, 856 %122 = load float, float* %68, align 4 call void @llvm.amdgcn.buffer.store.f32(float %122, <4 x i32> %100, i32 0, i32 %121, i1 false, i1 false) #2 %123 = add i32 %97, 852 %124 = load float, float* %67, align 4 call void @llvm.amdgcn.buffer.store.f32(float %124, <4 x i32> %100, i32 0, i32 %123, i1 false, i1 false) #2 %125 = add i32 %97, 848 %126 = load float, float* %66, align 4 call void @llvm.amdgcn.buffer.store.f32(float %126, <4 x i32> %100, i32 0, i32 %125, i1 false, i1 false) #2 %127 = add i32 %97, 844 %128 = load float, float* %65, align 4 call void @llvm.amdgcn.buffer.store.f32(float %128, <4 x i32> %100, i32 0, i32 %127, i1 false, i1 false) #2 %129 = add i32 %97, 840 %130 = load float, float* %64, align 4 call void @llvm.amdgcn.buffer.store.f32(float %130, <4 x i32> %100, i32 0, i32 %129, i1 false, i1 false) #2 %131 = add i32 %97, 836 %132 = load float, float* %63, align 4 call void @llvm.amdgcn.buffer.store.f32(float %132, <4 x i32> %100, i32 0, i32 %131, i1 false, i1 false) #2 %133 = add i32 %97, 832 %134 = load float, float* %62, align 4 call void @llvm.amdgcn.buffer.store.f32(float %134, <4 x i32> %100, i32 0, i32 %133, i1 false, i1 false) #2 %135 = add i32 %97, 828 %136 = load float, float* %61, align 4 call void @llvm.amdgcn.buffer.store.f32(float %136, <4 x i32> %100, i32 0, i32 %135, i1 false, i1 false) #2 %137 = add i32 %97, 824 %138 = load float, float* %60, align 4 call void @llvm.amdgcn.buffer.store.f32(float %138, <4 x i32> %100, i32 0, i32 %137, i1 false, i1 false) #2 %139 = add i32 %97, 820 %140 = load float, float* %59, align 4 call void @llvm.amdgcn.buffer.store.f32(float %140, <4 x i32> %100, i32 0, i32 %139, i1 false, i1 false) #2 %141 = add i32 %97, 816 %142 = load float, float* %58, align 4 call void @llvm.amdgcn.buffer.store.f32(float %142, <4 x i32> %100, i32 0, i32 %141, i1 false, i1 false) #2 %143 = add i32 %97, 812 %144 = load float, float* %57, align 4 call void @llvm.amdgcn.buffer.store.f32(float %144, <4 x i32> %100, i32 0, i32 %143, i1 false, i1 false) #2 %145 = add i32 %97, 808 %146 = load float, float* %56, align 4 call void @llvm.amdgcn.buffer.store.f32(float %146, <4 x i32> %100, i32 0, i32 %145, i1 false, i1 false) #2 %147 = add i32 %97, 804 %148 = load float, float* %55, align 4 call void @llvm.amdgcn.buffer.store.f32(float %148, <4 x i32> %100, i32 0, i32 %147, i1 false, i1 false) #2 %149 = add i32 %97, 800 %150 = load float, float* %54, align 4 call void @llvm.amdgcn.buffer.store.f32(float %150, <4 x i32> %100, i32 0, i32 %149, i1 false, i1 false) #2 %151 = add i32 %97, 496 %152 = load float, float* %53, align 4 call void @llvm.amdgcn.buffer.store.f32(float %152, <4 x i32> %100, i32 0, i32 %151, i1 false, i1 false) #2 %153 = add i32 %97, 492 %154 = load float, float* %52, align 4 call void @llvm.amdgcn.buffer.store.f32(float %154, <4 x i32> %100, i32 0, i32 %153, i1 false, i1 false) #2 %155 = add i32 %97, 488 %156 = load float, float* %51, align 4 call void @llvm.amdgcn.buffer.store.f32(float %156, <4 x i32> %100, i32 0, i32 %155, i1 false, i1 false) #2 %157 = add i32 %97, 484 %158 = load float, float* %50, align 4 call void @llvm.amdgcn.buffer.store.f32(float %158, <4 x i32> %100, i32 0, i32 %157, i1 false, i1 false) #2 %159 = add i32 %97, 480 %160 = load float, float* %49, align 4 call void @llvm.amdgcn.buffer.store.f32(float %160, <4 x i32> %100, i32 0, i32 %159, i1 false, i1 false) #2 %161 = add i32 %97, 476 %162 = load float, float* %48, align 4 call void @llvm.amdgcn.buffer.store.f32(float %162, <4 x i32> %100, i32 0, i32 %161, i1 false, i1 false) #2 %163 = add i32 %97, 472 %164 = load float, float* %47, align 4 call void @llvm.amdgcn.buffer.store.f32(float %164, <4 x i32> %100, i32 0, i32 %163, i1 false, i1 false) #2 %165 = add i32 %97, 468 %166 = load float, float* %46, align 4 call void @llvm.amdgcn.buffer.store.f32(float %166, <4 x i32> %100, i32 0, i32 %165, i1 false, i1 false) #2 %167 = add i32 %97, 464 %168 = load float, float* %45, align 4 call void @llvm.amdgcn.buffer.store.f32(float %168, <4 x i32> %100, i32 0, i32 %167, i1 false, i1 false) #2 %169 = add i32 %97, 460 %170 = load float, float* %44, align 4 call void @llvm.amdgcn.buffer.store.f32(float %170, <4 x i32> %100, i32 0, i32 %169, i1 false, i1 false) #2 %171 = add i32 %97, 456 %172 = load float, float* %43, align 4 call void @llvm.amdgcn.buffer.store.f32(float %172, <4 x i32> %100, i32 0, i32 %171, i1 false, i1 false) #2 %173 = add i32 %97, 452 %174 = load float, float* %42, align 4 call void @llvm.amdgcn.buffer.store.f32(float %174, <4 x i32> %100, i32 0, i32 %173, i1 false, i1 false) #2 %175 = add i32 %97, 448 %176 = load float, float* %41, align 4 call void @llvm.amdgcn.buffer.store.f32(float %176, <4 x i32> %100, i32 0, i32 %175, i1 false, i1 false) #2 %177 = add i32 %97, 444 %178 = load float, float* %40, align 4 call void @llvm.amdgcn.buffer.store.f32(float %178, <4 x i32> %100, i32 0, i32 %177, i1 false, i1 false) #2 %179 = add i32 %97, 440 %180 = load float, float* %39, align 4 call void @llvm.amdgcn.buffer.store.f32(float %180, <4 x i32> %100, i32 0, i32 %179, i1 false, i1 false) #2 %181 = add i32 %97, 436 %182 = load float, float* %38, align 4 call void @llvm.amdgcn.buffer.store.f32(float %182, <4 x i32> %100, i32 0, i32 %181, i1 false, i1 false) #2 %183 = add i32 %97, 432 %184 = load float, float* %37, align 4 call void @llvm.amdgcn.buffer.store.f32(float %184, <4 x i32> %100, i32 0, i32 %183, i1 false, i1 false) #2 %185 = add i32 %97, 428 %186 = load float, float* %36, align 4 call void @llvm.amdgcn.buffer.store.f32(float %186, <4 x i32> %100, i32 0, i32 %185, i1 false, i1 false) #2 %187 = add i32 %97, 424 %188 = load float, float* %35, align 4 call void @llvm.amdgcn.buffer.store.f32(float %188, <4 x i32> %100, i32 0, i32 %187, i1 false, i1 false) #2 %189 = add i32 %97, 420 %190 = load float, float* %34, align 4 call void @llvm.amdgcn.buffer.store.f32(float %190, <4 x i32> %100, i32 0, i32 %189, i1 false, i1 false) #2 %191 = add i32 %97, 416 %192 = load float, float* %33, align 4 call void @llvm.amdgcn.buffer.store.f32(float %192, <4 x i32> %100, i32 0, i32 %191, i1 false, i1 false) #2 %193 = add i32 %97, 412 %194 = load float, float* %32, align 4 call void @llvm.amdgcn.buffer.store.f32(float %194, <4 x i32> %100, i32 0, i32 %193, i1 false, i1 false) #2 %195 = add i32 %97, 408 %196 = load float, float* %31, align 4 call void @llvm.amdgcn.buffer.store.f32(float %196, <4 x i32> %100, i32 0, i32 %195, i1 false, i1 false) #2 %197 = add i32 %97, 404 %198 = load float, float* %30, align 4 call void @llvm.amdgcn.buffer.store.f32(float %198, <4 x i32> %100, i32 0, i32 %197, i1 false, i1 false) #2 %199 = add i32 %97, 400 %200 = load float, float* %29, align 4 call void @llvm.amdgcn.buffer.store.f32(float %200, <4 x i32> %100, i32 0, i32 %199, i1 false, i1 false) #2 %201 = add i32 %97, 96 %202 = load float, float* %28, align 4 call void @llvm.amdgcn.buffer.store.f32(float %202, <4 x i32> %100, i32 0, i32 %201, i1 false, i1 false) #2 %203 = add i32 %97, 92 %204 = load float, float* %27, align 4 call void @llvm.amdgcn.buffer.store.f32(float %204, <4 x i32> %100, i32 0, i32 %203, i1 false, i1 false) #2 %205 = add i32 %97, 88 %206 = load float, float* %26, align 4 call void @llvm.amdgcn.buffer.store.f32(float %206, <4 x i32> %100, i32 0, i32 %205, i1 false, i1 false) #2 %207 = add i32 %97, 84 %208 = load float, float* %25, align 4 call void @llvm.amdgcn.buffer.store.f32(float %208, <4 x i32> %100, i32 0, i32 %207, i1 false, i1 false) #2 %209 = add i32 %97, 80 %210 = load float, float* %24, align 4 call void @llvm.amdgcn.buffer.store.f32(float %210, <4 x i32> %100, i32 0, i32 %209, i1 false, i1 false) #2 %211 = add i32 %97, 76 %212 = load float, float* %23, align 4 call void @llvm.amdgcn.buffer.store.f32(float %212, <4 x i32> %100, i32 0, i32 %211, i1 false, i1 false) #2 %213 = add i32 %97, 72 %214 = load float, float* %22, align 4 call void @llvm.amdgcn.buffer.store.f32(float %214, <4 x i32> %100, i32 0, i32 %213, i1 false, i1 false) #2 %215 = add i32 %97, 68 %216 = load float, float* %21, align 4 call void @llvm.amdgcn.buffer.store.f32(float %216, <4 x i32> %100, i32 0, i32 %215, i1 false, i1 false) #2 %217 = add i32 %97, 64 %218 = load float, float* %20, align 4 call void @llvm.amdgcn.buffer.store.f32(float %218, <4 x i32> %100, i32 0, i32 %217, i1 false, i1 false) #2 %219 = add i32 %97, 60 %220 = load float, float* %19, align 4 call void @llvm.amdgcn.buffer.store.f32(float %220, <4 x i32> %100, i32 0, i32 %219, i1 false, i1 false) #2 %221 = add i32 %97, 56 %222 = load float, float* %18, align 4 call void @llvm.amdgcn.buffer.store.f32(float %222, <4 x i32> %100, i32 0, i32 %221, i1 false, i1 false) #2 %223 = add i32 %97, 52 %224 = load float, float* %17, align 4 call void @llvm.amdgcn.buffer.store.f32(float %224, <4 x i32> %100, i32 0, i32 %223, i1 false, i1 false) #2 %225 = add i32 %97, 48 %226 = load float, float* %16, align 4 call void @llvm.amdgcn.buffer.store.f32(float %226, <4 x i32> %100, i32 0, i32 %225, i1 false, i1 false) #2 %227 = add i32 %97, 44 %228 = load float, float* %15, align 4 call void @llvm.amdgcn.buffer.store.f32(float %228, <4 x i32> %100, i32 0, i32 %227, i1 false, i1 false) #2 %229 = add i32 %97, 40 %230 = load float, float* %14, align 4 call void @llvm.amdgcn.buffer.store.f32(float %230, <4 x i32> %100, i32 0, i32 %229, i1 false, i1 false) #2 %231 = add i32 %97, 36 %232 = load float, float* %13, align 4 call void @llvm.amdgcn.buffer.store.f32(float %232, <4 x i32> %100, i32 0, i32 %231, i1 false, i1 false) #2 %233 = add i32 %97, 32 %234 = load float, float* %12, align 4 call void @llvm.amdgcn.buffer.store.f32(float %234, <4 x i32> %100, i32 0, i32 %233, i1 false, i1 false) #2 %235 = add i32 %97, 28 %236 = load float, float* %11, align 4 call void @llvm.amdgcn.buffer.store.f32(float %236, <4 x i32> %100, i32 0, i32 %235, i1 false, i1 false) #2 %237 = add i32 %97, 24 %238 = load float, float* %10, align 4 call void @llvm.amdgcn.buffer.store.f32(float %238, <4 x i32> %100, i32 0, i32 %237, i1 false, i1 false) #2 %239 = add i32 %97, 20 %240 = load float, float* %9, align 4 call void @llvm.amdgcn.buffer.store.f32(float %240, <4 x i32> %100, i32 0, i32 %239, i1 false, i1 false) #2 %241 = add i32 %97, 16 %242 = load float, float* %8, align 4 call void @llvm.amdgcn.buffer.store.f32(float %242, <4 x i32> %100, i32 0, i32 %241, i1 false, i1 false) #2 %243 = or i32 %97, 12 %244 = load float, float* %7, align 4 call void @llvm.amdgcn.buffer.store.f32(float %244, <4 x i32> %100, i32 0, i32 %243, i1 false, i1 false) #2 %245 = or i32 %97, 8 %246 = load float, float* %6, align 4 call void @llvm.amdgcn.buffer.store.f32(float %246, <4 x i32> %100, i32 0, i32 %245, i1 false, i1 false) #2 %247 = or i32 %97, 4 %248 = load float, float* %5, align 4 call void @llvm.amdgcn.buffer.store.f32(float %248, <4 x i32> %100, i32 0, i32 %247, i1 false, i1 false) #2 %249 = load float, float* %4, align 4 call void @llvm.amdgcn.buffer.store.f32(float %249, <4 x i32> %100, i32 0, i32 %97, i1 false, i1 false) #2 ret void } ; Function Attrs: nounwind writeonly declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #1 attributes #0 = { "amdgpu-max-work-group-size"="6" "no-signed-zeros-fp-math"="true" } attributes #1 = { nounwind writeonly } attributes #2 = { inaccessiblememonly nounwind } !0 = !{} SHADER KEY Compute Shader: Shader main disassembly: v_add_i32_e32 v1, vcc, v1, v2 ; 4A020501 v_mul_lo_i32 v1, v1, 6 ; D2D60001 00010D01 s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; BE8803FF 00000000 s_movk_i32 s5, 0x4a ; B005004A s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; BE8903FF 00000000 v_add_i32_e32 v0, vcc, v0, v1 ; 4A000300 v_add_i32_e32 v2, vcc, 25, v0 ; 4A040099 v_cvt_f32_u32_e32 v1, v0 ; 7E020D00 v_min_u32_e32 v3, s5, v0 ; 26060005 v_min_u32_e32 v2, s5, v2 ; 26040405 s_mov_b32 s10, -1 ; BE8A03C1 v_lshlrev_b32_e32 v3, 2, v3 ; 34060682 v_mov_b32_e32 v4, 4 ; 7E080284 v_lshlrev_b32_e32 v2, 2, v2 ; 34040482 s_mov_b32 s11, 0xe8f000 ; BE8B03FF 00E8F000 v_add_i32_e32 v3, vcc, v4, v3 ; 4A060704 s_movk_i32 s4, 0x130 ; B0040130 s_load_dwordx4 s[0:3], s[2:3], 0x1c ; C080031C v_add_i32_e32 v2, vcc, v4, v2 ; 4A040504 buffer_store_dword v1, v3, s[8:11], s6 offen ; E0701000 06020103 buffer_store_dword v1, v2, s[8:11], s6 offen ; E0701000 06020102 v_add_i32_e32 v2, vcc, 50, v0 ; 4A0400B2 v_mul_lo_i32 v0, v0, s4 ; D2D60000 00000900 v_min_u32_e32 v2, s5, v2 ; 26040405 v_lshlrev_b32_e32 v2, 2, v2 ; 34040482 v_add_i32_e32 v2, vcc, v4, v2 ; 4A040504 buffer_store_dword v1, v2, s[8:11], s6 offen ; E0701000 06020102 s_waitcnt lgkmcnt(0) ; BF8C007F buffer_store_dword v1, v0, s[0:3], 0 offen offset:1200 ; E07014B0 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:300 ; E030012C 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:896 ; E0701380 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:296 ; E0300128 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:892 ; E070137C 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:292 ; E0300124 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:888 ; E0701378 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:288 ; E0300120 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:884 ; E0701374 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:284 ; E030011C 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:880 ; E0701370 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:280 ; E0300118 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:876 ; E070136C 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:276 ; E0300114 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:872 ; E0701368 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:272 ; E0300110 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:868 ; E0701364 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:268 ; E030010C 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:864 ; E0701360 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:264 ; E0300108 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:860 ; E070135C 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:260 ; E0300104 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:856 ; E0701358 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:256 ; E0300100 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:852 ; E0701354 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:252 ; E03000FC 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:848 ; E0701350 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:248 ; E03000F8 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:844 ; E070134C 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:244 ; E03000F4 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:840 ; E0701348 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:240 ; E03000F0 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:836 ; E0701344 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:236 ; E03000EC 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:832 ; E0701340 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:232 ; E03000E8 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:828 ; E070133C 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:228 ; E03000E4 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:824 ; E0701338 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:224 ; E03000E0 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:820 ; E0701334 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:220 ; E03000DC 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:816 ; E0701330 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:216 ; E03000D8 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:812 ; E070132C 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:212 ; E03000D4 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:808 ; E0701328 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:208 ; E03000D0 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:804 ; E0701324 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:204 ; E03000CC 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:800 ; E0701320 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:200 ; E03000C8 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:496 ; E07011F0 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:196 ; E03000C4 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:492 ; E07011EC 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:192 ; E03000C0 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:488 ; E07011E8 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:188 ; E03000BC 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:484 ; E07011E4 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:184 ; E03000B8 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:480 ; E07011E0 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:180 ; E03000B4 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:476 ; E07011DC 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:176 ; E03000B0 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:472 ; E07011D8 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:172 ; E03000AC 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:468 ; E07011D4 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:168 ; E03000A8 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:464 ; E07011D0 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:164 ; E03000A4 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:460 ; E07011CC 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:160 ; E03000A0 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:456 ; E07011C8 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:156 ; E030009C 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:452 ; E07011C4 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:152 ; E0300098 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:448 ; E07011C0 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:148 ; E0300094 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:444 ; E07011BC 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:144 ; E0300090 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:440 ; E07011B8 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:140 ; E030008C 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:436 ; E07011B4 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:136 ; E0300088 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:432 ; E07011B0 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:132 ; E0300084 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:428 ; E07011AC 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:128 ; E0300080 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:424 ; E07011A8 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:124 ; E030007C 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:420 ; E07011A4 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:120 ; E0300078 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:416 ; E07011A0 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:116 ; E0300074 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:412 ; E070119C 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:112 ; E0300070 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:408 ; E0701198 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:108 ; E030006C 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:404 ; E0701194 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:104 ; E0300068 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:400 ; E0701190 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:100 ; E0300064 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:96 ; E0701060 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:96 ; E0300060 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:92 ; E070105C 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:92 ; E030005C 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:88 ; E0701058 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:88 ; E0300058 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:84 ; E0701054 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:84 ; E0300054 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:80 ; E0701050 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:80 ; E0300050 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:76 ; E070104C 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:76 ; E030004C 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:72 ; E0701048 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:72 ; E0300048 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:68 ; E0701044 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:68 ; E0300044 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:64 ; E0701040 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:64 ; E0300040 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:60 ; E070103C 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:60 ; E030003C 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:56 ; E0701038 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:56 ; E0300038 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:52 ; E0701034 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:52 ; E0300034 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:48 ; E0701030 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:48 ; E0300030 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:44 ; E070102C 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:44 ; E030002C 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:40 ; E0701028 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:40 ; E0300028 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:36 ; E0701024 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:36 ; E0300024 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:32 ; E0701020 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:32 ; E0300020 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:28 ; E070101C 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:28 ; E030001C 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:24 ; E0701018 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:24 ; E0300018 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:20 ; E0701014 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:20 ; E0300014 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:16 ; E0701010 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:16 ; E0300010 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:12 ; E070100C 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:12 ; E030000C 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:8 ; E0701008 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:8 ; E0300008 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen offset:4 ; E0701004 80000100 s_waitcnt expcnt(0) ; BF8C0F0F buffer_load_dword v1, off, s[8:11], s6 offset:4 ; E0300004 06020100 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_store_dword v1, v0, s[0:3], 0 offen ; E0701000 80000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 8 Spilled SGPRs: 0 Spilled VGPRs: 0 Private memory VGPRs: 76 Code Size: 1956 bytes LDS: 0 blocks Scratch: 19456 bytes per wave Max Waves: 10 ******************** 0: weight -2.82213e+38 (should be 0) 1: weight -nan (should be 1) 2: weight -2.90199e+38 (should be 2) 3: weight -nan (should be 3) 4: weight -nan (should be 4) 5: weight -nan (should be 5)