? Makefile ? dynclocks.patch ? r128.4.html ? r128._man ? radeon.4.html ? radeon._man Index: radeon_driver.c =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v retrieving revision 1.25 diff -u -r1.25 radeon_driver.c --- radeon_driver.c 23 Nov 2004 21:27:43 -0000 1.25 +++ radeon_driver.c 25 Nov 2004 01:33:02 -0000 @@ -7892,7 +7892,34 @@ CARD32 tmp; switch(mode) { case 0: /* Turn everything OFF (ForceON to everything)*/ - if ( !info->HasCRTC2 ) { + /* some non-mobility VE chips seem to have problems with the method of + * forcing everything on as per below; thus we revert to the old + * forceON behavior + */ + if ((info->ChipFamily == CHIP_FAMILY_RV100) && (!info->IsMobility)) { + if (info->HasCRTC2) { + tmp = INPLL(pScrn, RADEON_SCLK_CNTL); + OUTPLL(RADEON_SCLK_CNTL, ((tmp & ~RADEON_DYN_STOP_LAT_MASK) | + RADEON_CP_MAX_DYN_STOP_LAT | + RADEON_SCLK_FORCEON_MASK)); + + if (info->ChipFamily == CHIP_FAMILY_RV200) { + tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); + OUTPLL(RADEON_SCLK_MORE_CNTL, tmp + | RADEON_SCLK_MORE_FORCEON); + } + } + + tmp = INPLL(pScrn, RADEON_MCLK_CNTL); + OUTPLL(RADEON_MCLK_CNTL, (tmp | + RADEON_FORCEON_MCLKA | + RADEON_FORCEON_MCLKB | + RADEON_FORCEON_YCLKA | + RADEON_FORCEON_YCLKB | + RADEON_FORCEON_MC | + RADEON_FORCEON_AIC)); + + } else if ( !info->HasCRTC2 ) { tmp = INPLL(pScrn, RADEON_SCLK_CNTL); tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP | Index: radeon_reg.h =================================================================== RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v retrieving revision 1.11 diff -u -r1.11 radeon_reg.h --- radeon_reg.h 24 Oct 2004 18:17:36 -0000 1.11 +++ radeon_reg.h 25 Nov 2004 01:33:05 -0000 @@ -821,7 +821,7 @@ # define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1<<12) # define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1<<13) # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) -# define RADEON_IO_MCLK_DYN_ENABLE (1 << 14) +# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) #define RADEON_MDGPIO_A_REG 0x01ac #define RADEON_MDGPIO_EN_REG 0x01b0 #define RADEON_MDGPIO_MASK 0x0198