GPU hang report: Device name: AMD Radeon (TM) RX 480 Graphics (AMD RADV POLARIS10 (LLVM 7.0.0) DRM 3.23.0 / 4.15.9-1-ARCH, LLVM 7.0.0) Enabled debug options: allbos, vmfaults, syncshaders, Last 60 lines of dmesg: [ 5.225990] vboxdrv: Successfully loaded version 5.2.8 (interface 0x00290001) [ 5.231223] VBoxPciLinuxInit [ 5.231228] vboxpci: IOMMU not found (not registered) [ 5.232079] VBoxNetAdp: Successfully started. [ 5.239005] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4 [ 5.239952] rtc_cmos 00:03: RTC can wake from S4 [ 5.240085] rtc_cmos 00:03: rtc core: registered rtc_cmos as rtc0 [ 5.240106] rtc_cmos 00:03: alarms up to one month, y3k, 114 bytes nvram, hpet irqs [ 5.240985] VBoxNetFlt: Successfully started. [ 5.253689] piix4_smbus 0000:00:14.0: SMBus Host Controller at 0xb00, revision 0 [ 5.253695] piix4_smbus 0000:00:14.0: Using register 0x2c for SMBus port selection [ 5.253846] piix4_smbus 0000:00:14.0: Auxiliary SMBus Host Controller at 0xb20 [ 5.254882] sp5100_tco: SP5100/SB800 TCO WatchDog Timer Driver v0.05 [ 5.254936] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded [ 5.254945] r8169 0000:02:00.0: can't disable ASPM; OS doesn't have ASPM control [ 5.254950] sp5100_tco: PCI Vendor ID: 0x1002, Device ID: 0x4385, Revision ID: 0x42 [ 5.254952] sp5100_tco: I/O address 0x0cd6 already in use [ 5.255477] r8169 0000:02:00.0 eth0: RTL8168evl/8111evl at 0x00000000af719fa7, 54:04:a6:13:b9:9d, XID 0c900800 IRQ 39 [ 5.255479] r8169 0000:02:00.0 eth0: jumbo features [frames: 9200 bytes, tx checksumming: ko] [ 5.257722] input: PC Speaker as /devices/platform/pcspkr/input/input14 [ 5.297276] kvm: Nested Virtualization enabled [ 5.297279] kvm: Nested Paging enabled [ 5.300206] MCE: In-kernel MCE decoding enabled. [ 5.302114] EDAC amd64: Node 0: DRAM ECC disabled. [ 5.302115] EDAC amd64: ECC disabled in the BIOS or no ECC capability, module will not load. Either enable ECC checking or force module loading by setting 'ecc_enable_override'. (Note that use of the override may cause unknown side effects.) [ 5.311359] EDAC amd64: Node 0: DRAM ECC disabled. [ 5.311361] EDAC amd64: ECC disabled in the BIOS or no ECC capability, module will not load. Either enable ECC checking or force module loading by setting 'ecc_enable_override'. (Note that use of the override may cause unknown side effects.) [ 5.320693] EDAC amd64: Node 0: DRAM ECC disabled. [ 5.320695] EDAC amd64: ECC disabled in the BIOS or no ECC capability, module will not load. Either enable ECC checking or force module loading by setting 'ecc_enable_override'. (Note that use of the override may cause unknown side effects.) [ 5.348509] input: Microsoft X-Box One pad as /devices/pci0000:00/0000:00:12.0/usb6/6-4/6-4:1.0/input/input15 [ 5.348600] usbcore: registered new interface driver xpad [ 5.360293] input: Logitech Logitech G710 Keyboard as /devices/pci0000:00/0000:00:12.0/usb6/6-2/6-2:1.0/0003:046D:C24D.0002/input/input16 [ 5.412161] hid-lg-g710-plus 0003:046D:C24D.0002: input,hidraw0: USB HID v1.11 Keyboard [Logitech Logitech G710 Keyboard] on usb-0000:00:12.0-2/input0 [ 5.414474] Adding 16777212k swap on /dev/sda2. Priority:-2 extents:1 across:16777212k FS [ 5.416781] input: Logitech Logitech G710 Keyboard as /devices/pci0000:00/0000:00:12.0/usb6/6-2/6-2:1.1/0003:046D:C24D.0003/input/input17 [ 5.459196] microcode: CPU0: new patch_level=0x010000dc [ 5.459213] microcode: CPU1: new patch_level=0x010000dc [ 5.459254] microcode: CPU2: new patch_level=0x010000dc [ 5.459294] microcode: CPU3: new patch_level=0x010000dc [ 5.459327] microcode: CPU4: new patch_level=0x010000dc [ 5.459348] microcode: CPU5: new patch_level=0x010000dc [ 5.468333] hid-lg-g710-plus 0003:046D:C24D.0003: input,hiddev0,hidraw1: USB HID v1.11 Keyboard [Logitech Logitech G710 Keyboard] on usb-0000:00:12.0-2/input1 [ 5.468472] usbcore: registered new interface driver usbhid [ 5.468474] usbhid: USB HID core driver [ 5.471261] input: Saitek Cyborg R.A.T.7 Mouse as /devices/pci0000:00/0000:00:12.0/usb6/6-1/6-1:1.0/0003:06A3:0CD7.0001/input/input18 [ 5.471383] saitek 0003:06A3:0CD7.0001: input,hidraw2: USB HID v1.11 Mouse [Saitek Cyborg R.A.T.7 Mouse] on usb-0000:00:12.0-1/input0 [ 5.478195] mousedev: PS/2 mouse device common for all mice [ 5.635082] r8169 0000:02:00.0 eth0: link down [ 5.635085] r8169 0000:02:00.0 eth0: link down [ 5.635151] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready [ 8.964691] r8169 0000:02:00.0 eth0: link up [ 8.964697] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready [ 16.307995] EXT4-fs (sda1): mounted filesystem with ordered data mode. Opts: user_xattr [ 16.726305] fuse init (API version 7.26) Memory-mapped registers: GRBM_STATUS <- ME0PIPE0_CMDFIFO_AVAIL = 8 SRBM_RQ_PENDING = 1 ME0PIPE0_CF_RQ_PENDING = 0 ME0PIPE0_PF_RQ_PENDING = 0 GDS_DMA_RQ_PENDING = 0 DB_CLEAN = 1 CB_CLEAN = 1 TA_BUSY = 0 GDS_BUSY = 0 WD_BUSY_NO_DMA = 0 VGT_BUSY = 0 IA_BUSY_NO_DMA = 0 IA_BUSY = 0 SX_BUSY = 0 WD_BUSY = 0 SPI_BUSY = 1 BCI_BUSY = 0 SC_BUSY = 0 PA_BUSY = 0 DB_BUSY = 0 CP_COHERENCY_BUSY = 0 CP_BUSY = 1 CB_BUSY = 0 GUI_ACTIVE = 1 GRBM_STATUS2 <- ME0PIPE1_CMDFIFO_AVAIL = 8 ME0PIPE1_CF_RQ_PENDING = 0 ME0PIPE1_PF_RQ_PENDING = 0 ME1PIPE0_RQ_PENDING = 0 ME1PIPE1_RQ_PENDING = 0 ME1PIPE2_RQ_PENDING = 0 ME1PIPE3_RQ_PENDING = 0 ME2PIPE0_RQ_PENDING = 0 ME2PIPE1_RQ_PENDING = 0 ME2PIPE2_RQ_PENDING = 0 ME2PIPE3_RQ_PENDING = 0 RLC_RQ_PENDING = 0 RLC_BUSY = 0 TC_BUSY = 0 TCC_CC_RESIDENT = 0 CPF_BUSY = 1 CPC_BUSY = 0 CPG_BUSY = 1 GRBM_STATUS_SE0 <- DB_CLEAN = 1 CB_CLEAN = 1 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 1 SC_BUSY = 0 DB_BUSY = 0 CB_BUSY = 0 GRBM_STATUS_SE1 <- DB_CLEAN = 1 CB_CLEAN = 1 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 1 SC_BUSY = 0 DB_BUSY = 0 CB_BUSY = 0 GRBM_STATUS_SE2 <- DB_CLEAN = 1 CB_CLEAN = 1 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 1 SC_BUSY = 0 DB_BUSY = 0 CB_BUSY = 0 GRBM_STATUS_SE3 <- DB_CLEAN = 1 CB_CLEAN = 1 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 1 SC_BUSY = 0 DB_BUSY = 0 CB_BUSY = 0 SDMA0_STATUS_REG <- IDLE = 1 REG_IDLE = 1 RB_EMPTY = 1 RB_FULL = 0 RB_CMD_IDLE = 1 RB_CMD_FULL = 0 IB_CMD_IDLE = 1 IB_CMD_FULL = 0 BLOCK_IDLE = 1 INSIDE_IB = 0 EX_IDLE = 1 EX_IDLE_POLL_TIMER_EXPIRE = 1 PACKET_READY = 0 MC_WR_IDLE = 1 SRBM_IDLE = 1 CONTEXT_EMPTY = 1 DELTA_RPTR_FULL = 0 RB_MC_RREQ_IDLE = 1 IB_MC_RREQ_IDLE = 1 MC_RD_IDLE = 1 DELTA_RPTR_EMPTY = 1 MC_RD_RET_STALL = 0 MC_RD_NO_POLL_IDLE = 1 PREV_CMD_IDLE = 1 SEM_IDLE = 1 SEM_REQ_STALL = 0 SEM_RESP_STATE = 0 INT_IDLE = 1 INT_REQ_STALL = 0 SDMA1_STATUS_REG <- IDLE = 1 REG_IDLE = 1 RB_EMPTY = 1 RB_FULL = 0 RB_CMD_IDLE = 1 RB_CMD_FULL = 0 IB_CMD_IDLE = 1 IB_CMD_FULL = 0 BLOCK_IDLE = 1 INSIDE_IB = 0 EX_IDLE = 1 EX_IDLE_POLL_TIMER_EXPIRE = 1 PACKET_READY = 0 MC_WR_IDLE = 1 SRBM_IDLE = 1 CONTEXT_EMPTY = 1 DELTA_RPTR_FULL = 0 RB_MC_RREQ_IDLE = 1 IB_MC_RREQ_IDLE = 1 MC_RD_IDLE = 1 DELTA_RPTR_EMPTY = 1 MC_RD_RET_STALL = 0 MC_RD_NO_POLL_IDLE = 1 PREV_CMD_IDLE = 1 SEM_IDLE = 1 SEM_REQ_STALL = 0 SEM_RESP_STATE = 0 INT_IDLE = 1 INT_REQ_STALL = 0 SRBM_STATUS <- UVD_RQ_PENDING = 0 SAMMSP_RQ_PENDING = 0 ACP_RQ_PENDING = 0 SMU_RQ_PENDING = 0 GRBM_RQ_PENDING = 0 HI_RQ_PENDING = 1 VMC_BUSY = 0 MCB_BUSY = 0 MCB_NON_DISPLAY_BUSY = 0 MCC_BUSY = 0 MCD_BUSY = 0 VMC1_BUSY = 0 SEM_BUSY = 0 ACP_BUSY = 0 IH_BUSY = 0 UVD_BUSY = 0 SAMMSP_BUSY = 0 GCATCL2_BUSY = 0 OSATCL2_BUSY = 0 BIF_BUSY = 1 SRBM_STATUS2 <- SDMA_RQ_PENDING = 0 TST_RQ_PENDING = 0 SDMA1_RQ_PENDING = 0 VCE0_RQ_PENDING = 0 VP8_BUSY = 0 SDMA_BUSY = 0 SDMA1_BUSY = 0 VCE0_BUSY = 0 XDMA_BUSY = 0 CHUB_BUSY = 0 SDMA2_BUSY = 0 SDMA3_BUSY = 0 SAMSCP_BUSY = 0 ISP_BUSY = 0 VCE1_BUSY = 0 ODE_BUSY = 0 SDMA2_RQ_PENDING = 0 SDMA3_RQ_PENDING = 0 SAMSCP_RQ_PENDING = 0 ISP_RQ_PENDING = 0 VCE1_RQ_PENDING = 0 SRBM_STATUS3 <- MCC0_BUSY = 0 MCC1_BUSY = 0 MCC2_BUSY = 0 MCC3_BUSY = 0 MCC4_BUSY = 0 MCC5_BUSY = 0 MCC6_BUSY = 0 MCC7_BUSY = 0 MCD0_BUSY = 0 MCD1_BUSY = 0 MCD2_BUSY = 0 MCD3_BUSY = 0 MCD4_BUSY = 0 MCD5_BUSY = 0 MCD6_BUSY = 0 MCD7_BUSY = 0 CP_STAT <- ROQ_RING_BUSY = 1 ROQ_INDIRECT1_BUSY = 1 ROQ_INDIRECT2_BUSY = 0 ROQ_STATE_BUSY = 0 DC_BUSY = 0 ATCL2IU_BUSY = 0 PFP_BUSY = 1 MEQ_BUSY = 1 ME_BUSY = 1 QUERY_BUSY = 0 SEMAPHORE_BUSY = 0 INTERRUPT_BUSY = 0 SURFACE_SYNC_BUSY = 0 DMA_BUSY = 0 RCIU_BUSY = 0 SCRATCH_RAM_BUSY = 1 CPC_CPG_BUSY = 0 CE_BUSY = 0 TCIU_BUSY = 0 ROQ_CE_RING_BUSY = 0 ROQ_CE_INDIRECT1_BUSY = 0 ROQ_CE_INDIRECT2_BUSY = 0 CP_BUSY = 1 CP_STALLED_STAT1 <- RBIU_TO_DMA_NOT_RDY_TO_RCV = 0 RBIU_TO_SEM_NOT_RDY_TO_RCV = 0 RBIU_TO_MEMWR_NOT_RDY_TO_RCV = 0 ME_HAS_ACTIVE_CE_BUFFER_FLAG = 1 ME_HAS_ACTIVE_DE_BUFFER_FLAG = 1 ME_STALLED_ON_TC_WR_CONFIRM = 0 ME_STALLED_ON_ATOMIC_RTN_DATA = 0 ME_WAITING_ON_TC_READ_DATA = 0 ME_WAITING_ON_REG_READ_DATA = 0 RCIU_WAITING_ON_GDS_FREE = 0 RCIU_WAITING_ON_GRBM_FREE = 0 RCIU_WAITING_ON_VGT_FREE = 0 RCIU_STALLED_ON_ME_READ = 0 RCIU_STALLED_ON_DMA_READ = 0 RCIU_STALLED_ON_APPEND_READ = 0 RCIU_HALTED_BY_REG_VIOLATION = 0 CP_STALLED_STAT2 <- PFP_TO_CSF_NOT_RDY_TO_RCV = 0 PFP_TO_MEQ_NOT_RDY_TO_RCV = 0 PFP_TO_RCIU_NOT_RDY_TO_RCV = 0 PFP_TO_VGT_WRITES_PENDING = 0 PFP_RCIU_READ_PENDING = 0 PFP_WAITING_ON_BUFFER_DATA = 0 ME_WAIT_ON_CE_COUNTER = 0 ME_WAIT_ON_AVAIL_BUFFER = 0 GFX_CNTX_NOT_AVAIL_TO_ME = 0 ME_RCIU_NOT_RDY_TO_RCV = 0 ME_TO_CONST_NOT_RDY_TO_RCV = 0 ME_WAITING_DATA_FROM_PFP = 0 ME_WAITING_ON_PARTIAL_FLUSH = 1 MEQ_TO_ME_NOT_RDY_TO_RCV = 1 STQ_TO_ME_NOT_RDY_TO_RCV = 0 ME_WAITING_DATA_FROM_STQ = 0 PFP_STALLED_ON_TC_WR_CONFIRM = 0 PFP_STALLED_ON_ATOMIC_RTN_DATA = 0 EOPD_FIFO_NEEDS_SC_EOP_DONE = 0 EOPD_FIFO_NEEDS_WR_CONFIRM = 0 STRMO_WR_OF_PRIM_DATA_PENDING = 0 PIPE_STATS_WR_DATA_PENDING = 0 APPEND_RDY_WAIT_ON_CS_DONE = 0 APPEND_RDY_WAIT_ON_PS_DONE = 0 APPEND_WAIT_ON_WR_CONFIRM = 0 APPEND_ACTIVE_PARTITION = 0 APPEND_WAITING_TO_SEND_MEMWRITE = 0 SURF_SYNC_NEEDS_IDLE_CNTXS = 0 SURF_SYNC_NEEDS_ALL_CLEAN = 0 CP_STALLED_STAT3 <- CE_TO_CSF_NOT_RDY_TO_RCV = 0 CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV = 0 CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER = 0 CE_TO_RAM_INIT_NOT_RDY = 0 CE_TO_RAM_DUMP_NOT_RDY = 0 CE_TO_RAM_WRITE_NOT_RDY = 0 CE_TO_INC_FIFO_NOT_RDY_TO_RCV = 0 CE_TO_WR_FIFO_NOT_RDY_TO_RCV = 0 CE_WAITING_ON_BUFFER_DATA = 0 CE_WAITING_ON_CE_BUFFER_FLAG = 0 CE_WAITING_ON_DE_COUNTER = 0 CE_WAITING_ON_DE_COUNTER_UNDERFLOW = 0 TCIU_WAITING_ON_FREE = 0 TCIU_WAITING_ON_TAGS = 0 CE_STALLED_ON_TC_WR_CONFIRM = 0 CE_STALLED_ON_ATOMIC_RTN_DATA = 0 ATCL2IU_WAITING_ON_FREE = 0 ATCL2IU_WAITING_ON_TAGS = 0 ATCL1_WAITING_ON_TRANS = 0 CP_CPC_STATUS <- MEC1_BUSY = 0 MEC2_BUSY = 0 DC0_BUSY = 0 DC1_BUSY = 0 RCIU1_BUSY = 0 RCIU2_BUSY = 0 ROQ1_BUSY = 0 ROQ2_BUSY = 0 TCIU_BUSY = 0 SCRATCH_RAM_BUSY = 0 QU_BUSY = 0 ATCL2IU_BUSY = 0 CPG_CPC_BUSY = 0 CPF_CPC_BUSY = 0 CPC_BUSY = 0 CP_CPC_BUSY_STAT <- MEC1_LOAD_BUSY = 0 MEC1_SEMAPOHRE_BUSY = 0 MEC1_MUTEX_BUSY = 0 MEC1_MESSAGE_BUSY = 0 MEC1_EOP_QUEUE_BUSY = 0 MEC1_IQ_QUEUE_BUSY = 0 MEC1_IB_QUEUE_BUSY = 0 MEC1_TC_BUSY = 0 MEC1_DMA_BUSY = 0 MEC1_PARTIAL_FLUSH_BUSY = 0 MEC1_PIPE0_BUSY = 0 MEC1_PIPE1_BUSY = 0 MEC1_PIPE2_BUSY = 0 MEC1_PIPE3_BUSY = 0 MEC2_LOAD_BUSY = 0 MEC2_SEMAPOHRE_BUSY = 0 MEC2_MUTEX_BUSY = 0 MEC2_MESSAGE_BUSY = 0 MEC2_EOP_QUEUE_BUSY = 0 MEC2_IQ_QUEUE_BUSY = 0 MEC2_IB_QUEUE_BUSY = 0 MEC2_TC_BUSY = 0 MEC2_DMA_BUSY = 0 MEC2_PARTIAL_FLUSH_BUSY = 0 MEC2_PIPE0_BUSY = 0 MEC2_PIPE1_BUSY = 0 MEC2_PIPE2_BUSY = 0 MEC2_PIPE3_BUSY = 0 CP_CPC_STALLED_STAT1 <- RCIU_TX_FREE_STALL = 0 RCIU_PRIV_VIOLATION = 0 TCIU_TX_FREE_STALL = 0 MEC1_DECODING_PACKET = 0 MEC1_WAIT_ON_RCIU = 0 MEC1_WAIT_ON_RCIU_READ = 0 MEC1_WAIT_ON_ROQ_DATA = 0 MEC2_DECODING_PACKET = 0 MEC2_WAIT_ON_RCIU = 0 MEC2_WAIT_ON_RCIU_READ = 0 MEC2_WAIT_ON_ROQ_DATA = 0 ATCL2IU_WAITING_ON_FREE = 0 ATCL2IU_WAITING_ON_TAGS = 0 ATCL1_WAITING_ON_TRANS = 0 CP_CPF_STATUS <- POST_WPTR_GFX_BUSY = 1 CSF_BUSY = 1 ROQ_ALIGN_BUSY = 0 ROQ_RING_BUSY = 1 ROQ_INDIRECT1_BUSY = 1 ROQ_INDIRECT2_BUSY = 0 ROQ_STATE_BUSY = 0 ROQ_CE_RING_BUSY = 0 ROQ_CE_INDIRECT1_BUSY = 0 ROQ_CE_INDIRECT2_BUSY = 0 SEMAPHORE_BUSY = 0 INTERRUPT_BUSY = 0 TCIU_BUSY = 0 HQD_BUSY = 0 PRT_BUSY = 0 ATCL2IU_BUSY = 0 CPF_GFX_BUSY = 1 CPF_CMP_BUSY = 0 GRBM_CPF_STAT_BUSY = 3 CPC_CPF_BUSY = 0 CPF_BUSY = 1 CP_CPF_BUSY_STAT <- REG_BUS_FIFO_BUSY = 0 CSF_RING_BUSY = 1 CSF_INDIRECT1_BUSY = 1 CSF_INDIRECT2_BUSY = 0 CSF_STATE_BUSY = 0 CSF_CE_INDR1_BUSY = 0 CSF_CE_INDR2_BUSY = 0 CSF_ARBITER_BUSY = 0 CSF_INPUT_BUSY = 0 OUTSTANDING_READ_TAGS = 0 HPD_PROCESSING_EOP_BUSY = 0 HQD_DISPATCH_BUSY = 0 HQD_IQ_TIMER_BUSY = 0 HQD_DMA_OFFLOAD_BUSY = 0 HQD_WAIT_SEMAPHORE_BUSY = 0 HQD_SIGNAL_SEMAPHORE_BUSY = 0 HQD_MESSAGE_BUSY = 0 HQD_PQ_FETCHER_BUSY = 0 HQD_IB_FETCHER_BUSY = 0 HQD_IQ_FETCHER_BUSY = 0 HQD_EOP_FETCHER_BUSY = 0 HQD_CONSUMED_RPTR_BUSY = 0 HQD_FETCHER_ARB_BUSY = 0 HQD_ROQ_ALIGN_BUSY = 0 HQD_ROQ_EOP_BUSY = 0 HQD_ROQ_IQ_BUSY = 0 HQD_ROQ_PQ_BUSY = 0 HQD_ROQ_IB_BUSY = 0 HQD_WPTR_POLL_BUSY = 0 HQD_PQ_BUSY = 0 HQD_IB_BUSY = 0 CP_CPF_STALLED_STAT1 <- RING_FETCHING_DATA = 1 INDR1_FETCHING_DATA = 1 INDR2_FETCHING_DATA = 0 STATE_FETCHING_DATA = 0 TCIU_WAITING_ON_FREE = 0 TCIU_WAITING_ON_TAGS = 0 ATCL2IU_WAITING_ON_FREE = 0 ATCL2IU_WAITING_ON_TAGS = 0 ATCL1_WAITING_ON_TRANS = 0 Vertex Shader as VS: LLVM IR: ; ModuleID = 'shader' source_filename = "shader" target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5" target triple = "amdgcn-mesa-mesa3d" define amdgpu_vs void @main(i32 inreg, i32 inreg, i32, i32, i32, i32) { main_body: %6 = icmp eq i32 %2, 2 %7 = icmp eq i32 %2, 1 %8 = select i1 %6, float 1.000000e+00, float -1.000000e+00 %9 = select i1 %7, float 1.000000e+00, float -1.000000e+00 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %8, float %9, float 0.000000e+00, float 1.000000e+00, i1 true, i1 false) #1 ret void } ; Function Attrs: nounwind readnone speculatable declare i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr() #0 ; Function Attrs: nounwind declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1 attributes #0 = { nounwind readnone speculatable } attributes #1 = { nounwind } DISASM: main: BB0_0: v_cmp_eq_u32_e32 vcc, 2, v0 ; 7D940082 v_cndmask_b32_e64 v2, -1.0, 1.0, vcc ; D1000002 01A9E4F3 v_cmp_eq_u32_e32 vcc, 1, v0 ; 7D940081 v_mov_b32_e32 v1, 1.0 ; 7E0202F2 v_cndmask_b32_e64 v0, -1.0, 1.0, vcc ; D1000000 01A9E4F3 v_mov_b32_e32 v3, 0 ; 7E060280 exp pos0 v2, v0, v3, v1 done ; C40008CF 01030002 s_endpgm ; BF810000 Vertex Shader as VS: *** SHADER STATS *** SGPRS: 8 VGPRS: 4 Spilled SGPRs: 0 Spilled VGPRs: 0 PrivMem VGPRS: 0 Code Size: 44 bytes LDS: 0 blocks Scratch: 0 bytes per wave Max Waves: 8 ******************** Pixel Shader: LLVM IR: ; ModuleID = 'shader' source_filename = "shader" target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5" target triple = "amdgcn-mesa-mesa3d" define amdgpu_ps void @main(i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, i32, i32) { main_body: call void @llvm.amdgcn.exp.f32(i32 9, i32 0, float undef, float undef, float undef, float undef, i1 true, i1 true) #1 ret void } ; Function Attrs: nounwind readnone speculatable declare i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr() #0 ; Function Attrs: nounwind declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1 attributes #0 = { nounwind readnone speculatable } attributes #1 = { nounwind } DISASM: main: BB0_0: exp null off, off, off, off done vm ; C4001890 00000000 s_endpgm ; BF810000 Pixel Shader: *** SHADER CONFIG *** SPI_PS_INPUT_ADDR = 0x0001 SPI_PS_INPUT_ENA = 0x0001 *** SHADER STATS *** SGPRS: 8 VGPRS: 4 Spilled SGPRs: 0 Spilled VGPRs: 0 PrivMem VGPRS: 0 Code Size: 12 bytes LDS: 0 blocks Scratch: 0 bytes per wave Max Waves: 8 ******************** Compute Shader: SPIRV: ; SPIR-V ; Version: 1.0 ; Generator: Khronos; 0 ; Bound: 586 ; Schema: 0 OpCapability Shader OpCapability ImageQuery OpCapability StorageImageReadWithoutFormat OpCapability StorageImageWriteWithoutFormat %1 = OpExtInstImport "GLSL.std.450" OpMemoryModel Logical GLSL450 OpEntryPoint GLCompute %main "main" %vThreadId OpExecutionMode %main LocalSize 16 16 1 OpName %cs_main "cs_main" OpName %struct_cb0 "struct_cb0" OpMemberName %struct_cb0 0 "m" OpName %cb0 "cb0" OpName %cb0_bound "cb0_bound" OpName %t0 "t0" OpName %t0_bound "t0_bound" OpName %u0 "u0" OpName %u0_bound "u0_bound" OpName %vThreadId "vThreadId" OpName %r0 "r0" OpName %r1 "r1" OpName %r2 "r2" OpName %r3 "r3" OpName %r4 "r4" OpName %r5 "r5" OpName %r6 "r6" OpName %r7 "r7" OpName %r8 "r8" OpName %main "main" OpDecorate %_arr_v4float_uint_23 ArrayStride 16 OpDecorate %struct_cb0 Block OpMemberDecorate %struct_cb0 0 Offset 0 OpDecorate %cb0 DescriptorSet 0 OpDecorate %cb0 Binding 0 OpDecorate %cb0_bound SpecId 0 OpDecorate %t0 DescriptorSet 0 OpDecorate %t0 Binding 1 OpDecorate %t0_bound SpecId 1 OpDecorate %u0 DescriptorSet 0 OpDecorate %u0 Binding 2 OpDecorate %u0_bound SpecId 2 OpDecorate %vThreadId BuiltIn GlobalInvocationId %void = OpTypeVoid %5 = OpTypeFunction %void %uint = OpTypeInt 32 0 %uint_23 = OpConstant %uint 23 %float = OpTypeFloat 32 %v4float = OpTypeVector %float 4 %_arr_v4float_uint_23 = OpTypeArray %v4float %uint_23 %struct_cb0 = OpTypeStruct %_arr_v4float_uint_23 %_ptr_Uniform_struct_cb0 = OpTypePointer Uniform %struct_cb0 %bool = OpTypeBool %cb0_bound = OpSpecConstantTrue %bool %17 = OpTypeImage %float 2D 0 0 0 1 Unknown %_ptr_UniformConstant_17 = OpTypePointer UniformConstant %17 %t0_bound = OpSpecConstantTrue %bool %21 = OpTypeImage %float 2D 1 0 0 1 Unknown %22 = OpTypeImage %float 2D 0 0 0 2 Unknown %_ptr_UniformConstant_22 = OpTypePointer UniformConstant %22 %u0_bound = OpSpecConstantTrue %bool %v3uint = OpTypeVector %uint 3 %_ptr_Input_v3uint = OpTypePointer Input %v3uint %_ptr_Private_v4float = OpTypePointer Private %v4float %v2uint = OpTypeVector %uint 2 %v2float = OpTypeVector %float 2 %uint_0 = OpConstant %uint 0 %uint_0_0 = OpConstant %uint 0 %48 = OpConstantComposite %v2uint %uint_0 %uint_0_0 %int = OpTypeInt 32 1 %v4int = OpTypeVector %int 4 %v2int = OpTypeVector %int 2 %float_0 = OpConstant %float 0 %float_0_0 = OpConstant %float 0 %float_0_1 = OpConstant %float 0 %float_0_2 = OpConstant %float 0 %68 = OpConstantComposite %v4float %float_0 %float_0_0 %float_0_1 %float_0_2 %uint_0_1 = OpConstant %uint 0 %uint_0_2 = OpConstant %uint 0 %72 = OpConstantComposite %v2uint %uint_0_1 %uint_0_2 %uint_0_3 = OpConstant %uint 0 %uint_4294967293 = OpConstant %uint 4294967293 %uint_3 = OpConstant %uint 3 %uint_0_4 = OpConstant %uint 0 %uint_4294967295 = OpConstant %uint 4294967295 %uint_0_5 = OpConstant %uint 0 %uint_0_6 = OpConstant %uint 0 %uint_0_7 = OpConstant %uint 0 %uint_4294967295_0 = OpConstant %uint 4294967295 %uint_4294967293_0 = OpConstant %uint 4294967293 %uint_3_0 = OpConstant %uint 3 %uint_0_8 = OpConstant %uint 0 %uint_4294967295_1 = OpConstant %uint 4294967295 %uint_0_9 = OpConstant %uint 0 %uint_0_10 = OpConstant %uint 0 %uint_0_11 = OpConstant %uint 0 %uint_4294967295_2 = OpConstant %uint 4294967295 %uint_0_12 = OpConstant %uint 0 %uint_1 = OpConstant %uint 1 %uint_0_13 = OpConstant %uint 0 %uint_0_14 = OpConstant %uint 0 %202 = OpConstantComposite %v2uint %uint_0_13 %uint_0_14 %v2bool = OpTypeVector %bool 2 %uint_0_15 = OpConstant %uint 0 %uint_4294967295_3 = OpConstant %uint 4294967295 %208 = OpConstantComposite %v2uint %uint_0_15 %uint_0_15 %209 = OpConstantComposite %v2uint %uint_4294967295_3 %uint_4294967295_3 %int_16 = OpConstant %int 16 %_ptr_Uniform_v4float = OpTypePointer Uniform %v4float %int_0 = OpConstant %int 0 %float_0_3 = OpConstant %float 0 %float_0_4 = OpConstant %float 0 %float_0_5 = OpConstant %float 0 %float_0_6 = OpConstant %float 0 %229 = OpConstantComposite %v4float %float_0_3 %float_0_4 %float_0_5 %float_0_6 %uint_0_16 = OpConstant %uint 0 %uint_4294967295_4 = OpConstant %uint 4294967295 %236 = OpConstantComposite %v2uint %uint_0_16 %uint_0_16 %237 = OpConstantComposite %v2uint %uint_4294967295_4 %uint_4294967295_4 %uint_0_17 = OpConstant %uint 0 %uint_1_0 = OpConstant %uint 1 %float_0_7 = OpConstant %float 0 %float_0_8 = OpConstant %float 0 %float_0_9 = OpConstant %float 0 %float_0_10 = OpConstant %float 0 %293 = OpConstantComposite %v4float %float_0_7 %float_0_8 %float_0_9 %float_0_10 %int_22 = OpConstant %int 22 %int_0_0 = OpConstant %int 0 %float_0_11 = OpConstant %float 0 %float_0_12 = OpConstant %float 0 %float_0_13 = OpConstant %float 0 %float_0_14 = OpConstant %float 0 %308 = OpConstantComposite %v4float %float_0_11 %float_0_12 %float_0_13 %float_0_14 %uint_841731191 = OpConstant %uint 841731191 %uint_1_1 = OpConstant %uint 1 %uint_1597463007 = OpConstant %uint 1597463007 %uint_1065185444 = OpConstant %uint 1065185444 %uint_1065185444_0 = OpConstant %uint 1065185444 %373 = OpConstantComposite %v2uint %uint_1065185444 %uint_1065185444_0 %uint_0_18 = OpConstant %uint 0 %uint_4294967295_5 = OpConstant %uint 4294967295 %413 = OpConstantComposite %v2uint %uint_0_18 %uint_0_18 %414 = OpConstantComposite %v2uint %uint_4294967295_5 %uint_4294967295_5 %uint_0_19 = OpConstant %uint 0 %uint_4294967295_6 = OpConstant %uint 4294967295 %uint_0_20 = OpConstant %uint 0 %462 = OpConstantComposite %v2uint %uint_0_20 %uint_0_20 %uint_0_21 = OpConstant %uint 0 %uint_4294967295_7 = OpConstant %uint 4294967295 %uint_0_22 = OpConstant %uint 0 %500 = OpConstantComposite %v2uint %uint_0_22 %uint_0_22 %v4uint = OpTypeVector %uint 4 %uint_0_23 = OpConstant %uint 0 %v4bool = OpTypeVector %bool 4 %513 = OpConstantComposite %v4uint %uint_0_23 %uint_0_23 %uint_0_23 %uint_0_23 %uint_1_2 = OpConstant %uint 1 %uint_1_3 = OpConstant %uint 1 %int_16_0 = OpConstant %int 16 %int_0_1 = OpConstant %int 0 %float_0_15 = OpConstant %float 0 %float_0_16 = OpConstant %float 0 %float_0_17 = OpConstant %float 0 %float_0_18 = OpConstant %float 0 %548 = OpConstantComposite %v4float %float_0_15 %float_0_16 %float_0_17 %float_0_18 %uint_0_24 = OpConstant %uint 0 %uint_4294967295_8 = OpConstant %uint 4294967295 %555 = OpConstantComposite %v2uint %uint_0_24 %uint_0_24 %556 = OpConstantComposite %v2uint %uint_4294967295_8 %uint_4294967295_8 %uint_0_25 = OpConstant %uint 0 %cb0 = OpVariable %_ptr_Uniform_struct_cb0 Uniform %t0 = OpVariable %_ptr_UniformConstant_17 UniformConstant %u0 = OpVariable %_ptr_UniformConstant_22 UniformConstant %vThreadId = OpVariable %_ptr_Input_v3uint Input %r0 = OpVariable %_ptr_Private_v4float Private %r1 = OpVariable %_ptr_Private_v4float Private %r2 = OpVariable %_ptr_Private_v4float Private %r3 = OpVariable %_ptr_Private_v4float Private %r4 = OpVariable %_ptr_Private_v4float Private %r5 = OpVariable %_ptr_Private_v4float Private %r6 = OpVariable %_ptr_Private_v4float Private %r7 = OpVariable %_ptr_Private_v4float Private %r8 = OpVariable %_ptr_Private_v4float Private %cs_main = OpFunction %void None %5 %6 = OpLabel %39 = OpLoad %v3uint %vThreadId %41 = OpVectorShuffle %v2uint %39 %39 0 1 %43 = OpBitcast %v2float %41 %44 = OpLoad %v4float %r0 %45 = OpVectorShuffle %v4float %44 %43 4 5 2 3 OpStore %r0 %45 %49 = OpBitcast %v2float %48 %50 = OpLoad %v4float %r0 %51 = OpVectorShuffle %v4float %50 %49 0 1 4 5 OpStore %r0 %51 %52 = OpLoad %v4float %r0 %55 = OpBitcast %v4int %52 %56 = OpCompositeExtract %int %55 3 %58 = OpVectorShuffle %v2int %55 %55 0 1 OpSelectionMerge %59 None OpBranchConditional %t0_bound %60 %61 %60 = OpLabel %62 = OpLoad %17 %t0 %63 = OpImageFetch %v4float %62 %58 Lod %56 OpBranch %59 %61 = OpLabel OpBranch %59 %59 = OpLabel %69 = OpPhi %v4float %63 %60 %68 %61 OpStore %r0 %69 %73 = OpBitcast %v2float %72 %74 = OpLoad %v4float %r1 %75 = OpVectorShuffle %v4float %74 %73 0 1 4 5 OpStore %r1 %75 %77 = OpBitcast %float %uint_0_3 %78 = OpLoad %v4float %r2 %79 = OpCompositeInsert %v4float %77 %78 1 OpStore %r2 %79 %80 = OpLoad %v4float %r0 OpStore %r3 %80 %82 = OpBitcast %float %uint_4294967293 %83 = OpLoad %v4float %r2 %84 = OpCompositeInsert %v4float %82 %83 3 OpStore %r2 %84 OpBranch %85 %85 = OpLabel OpLoopMerge %88 %87 None OpBranch %86 %86 = OpLabel %90 = OpBitcast %int %uint_3 %91 = OpLoad %v4float %r2 %92 = OpCompositeExtract %float %91 3 %93 = OpBitcast %int %92 %94 = OpSLessThan %bool %90 %93 %97 = OpSelect %uint %94 %uint_4294967295 %uint_0_4 %98 = OpBitcast %float %97 %99 = OpLoad %v4float %r4 %100 = OpCompositeInsert %v4float %98 %99 0 OpStore %r4 %100 %101 = OpLoad %v4float %r4 %102 = OpCompositeExtract %float %101 0 %103 = OpBitcast %uint %102 %105 = OpINotEqual %bool %103 %uint_0_5 OpSelectionMerge %107 None OpBranchConditional %105 %106 %107 %106 = OpLabel OpBranch %88 %107 = OpLabel %108 = OpLoad %v4float %r2 %109 = OpCompositeExtract %float %108 3 %110 = OpBitcast %int %109 %112 = OpBitcast %int %uint_0_6 %113 = OpIEqual %bool %110 %112 %116 = OpSelect %uint %113 %uint_4294967295_0 %uint_0_7 %117 = OpBitcast %float %116 %118 = OpLoad %v4float %r4 %119 = OpCompositeInsert %v4float %117 %118 0 OpStore %r4 %119 %120 = OpLoad %v4float %r3 OpStore %r5 %120 %122 = OpBitcast %float %uint_4294967293_0 %123 = OpLoad %v4float %r4 %124 = OpCompositeInsert %v4float %122 %123 1 OpStore %r4 %124 OpBranch %125 %125 = OpLabel OpLoopMerge %128 %127 None OpBranch %126 %126 = OpLabel %130 = OpBitcast %int %uint_3_0 %131 = OpLoad %v4float %r4 %132 = OpCompositeExtract %float %131 1 %133 = OpBitcast %int %132 %134 = OpSLessThan %bool %130 %133 %137 = OpSelect %uint %134 %uint_4294967295_1 %uint_0_8 %138 = OpBitcast %float %137 %139 = OpLoad %v4float %r4 %140 = OpCompositeInsert %v4float %138 %139 2 OpStore %r4 %140 %141 = OpLoad %v4float %r4 %142 = OpCompositeExtract %float %141 2 %143 = OpBitcast %uint %142 %145 = OpINotEqual %bool %143 %uint_0_9 OpSelectionMerge %147 None OpBranchConditional %145 %146 %147 %146 = OpLabel OpBranch %128 %147 = OpLabel %148 = OpLoad %v4float %r4 %149 = OpCompositeExtract %float %148 1 %150 = OpBitcast %int %149 %152 = OpBitcast %int %uint_0_10 %153 = OpIEqual %bool %150 %152 %156 = OpSelect %uint %153 %uint_4294967295_2 %uint_0_11 %157 = OpBitcast %float %156 %158 = OpLoad %v4float %r4 %159 = OpCompositeInsert %v4float %157 %158 2 OpStore %r4 %159 %160 = OpLoad %v4float %r4 %161 = OpCompositeExtract %float %160 2 %162 = OpBitcast %uint %161 %163 = OpLoad %v4float %r4 %164 = OpCompositeExtract %float %163 0 %165 = OpBitcast %uint %164 %166 = OpBitwiseAnd %uint %162 %165 %167 = OpBitcast %float %166 %168 = OpLoad %v4float %r4 %169 = OpCompositeInsert %v4float %167 %168 2 OpStore %r4 %169 %170 = OpLoad %v4float %r4 %171 = OpCompositeExtract %float %170 2 %172 = OpBitcast %uint %171 %174 = OpINotEqual %bool %172 %uint_0_12 OpSelectionMerge %177 None OpBranchConditional %174 %175 %176 %175 = OpLabel %179 = OpBitcast %float %uint_1 %180 = OpLoad %v4float %r4 %181 = OpCompositeInsert %v4float %179 %180 1 OpStore %r4 %181 OpBranch %127 %182 = OpLabel OpBranch %177 %176 = OpLabel %183 = OpLoad %v4float %r4 %184 = OpCompositeExtract %float %183 1 %185 = OpLoad %v4float %r2 %186 = OpCompositeInsert %v4float %184 %185 2 OpStore %r2 %186 OpBranch %177 %177 = OpLabel %187 = OpLoad %v4float %r2 %188 = OpVectorShuffle %v2float %187 %187 3 2 %189 = OpBitcast %v2int %188 %190 = OpLoad %v3uint %vThreadId %191 = OpVectorShuffle %v2uint %190 %190 0 1 %192 = OpBitcast %v2int %191 %193 = OpIAdd %v2int %189 %192 %194 = OpBitcast %v2float %193 %195 = OpLoad %v4float %r1 %196 = OpVectorShuffle %v4float %195 %194 4 5 2 3 OpStore %r1 %196 %197 = OpLoad %v4float %r1 %198 = OpVectorShuffle %v2float %197 %197 0 1 %199 = OpBitcast %v2int %198 %203 = OpBitcast %v2int %202 %205 = OpSGreaterThanEqual %v2bool %199 %203 %210 = OpSelect %v2uint %205 %209 %208 %211 = OpBitcast %v2float %210 %212 = OpLoad %v4float %r4 %213 = OpVectorShuffle %v4float %212 %211 0 1 4 5 OpStore %r4 %213 %214 = OpLoad %v4float %r1 %215 = OpVectorShuffle %v2float %214 %214 0 1 %216 = OpBitcast %v2int %215 OpSelectionMerge %217 None OpBranchConditional %cb0_bound %218 %219 %218 = OpLabel %223 = OpAccessChain %_ptr_Uniform_v4float %cb0 %int_0 %int_16 %224 = OpLoad %v4float %223 OpBranch %217 %219 = OpLabel OpBranch %217 %217 = OpLabel %230 = OpPhi %v4float %224 %218 %229 %219 %231 = OpVectorShuffle %v2float %230 %230 2 3 %232 = OpBitcast %v2int %231 %233 = OpSLessThan %v2bool %216 %232 %238 = OpSelect %v2uint %233 %237 %236 %239 = OpBitcast %v2float %238 %240 = OpLoad %v4float %r6 %241 = OpVectorShuffle %v4float %240 %239 4 5 2 3 OpStore %r6 %241 %242 = OpLoad %v4float %r4 %243 = OpVectorShuffle %v2float %242 %242 2 3 %244 = OpBitcast %v2uint %243 %245 = OpLoad %v4float %r6 %246 = OpVectorShuffle %v2float %245 %245 0 1 %247 = OpBitcast %v2uint %246 %248 = OpBitwiseAnd %v2uint %244 %247 %249 = OpBitcast %v2float %248 %250 = OpLoad %v4float %r4 %251 = OpVectorShuffle %v4float %250 %249 0 1 4 5 OpStore %r4 %251 %252 = OpLoad %v4float %r4 %253 = OpCompositeExtract %float %252 3 %254 = OpBitcast %uint %253 %255 = OpLoad %v4float %r4 %256 = OpCompositeExtract %float %255 2 %257 = OpBitcast %uint %256 %258 = OpBitwiseAnd %uint %254 %257 %259 = OpBitcast %float %258 %260 = OpLoad %v4float %r4 %261 = OpCompositeInsert %v4float %259 %260 2 OpStore %r4 %261 %262 = OpLoad %v4float %r4 %263 = OpCompositeExtract %float %262 2 %264 = OpBitcast %uint %263 %266 = OpIEqual %bool %264 %uint_0_17 OpSelectionMerge %269 None OpBranchConditional %266 %267 %268 %267 = OpLabel %270 = OpLoad %v4float %r2 %271 = OpCompositeExtract %float %270 2 %272 = OpBitcast %int %271 %274 = OpBitcast %int %uint_1_0 %275 = OpIAdd %int %272 %274 %276 = OpBitcast %float %275 %277 = OpLoad %v4float %r4 %278 = OpCompositeInsert %v4float %276 %277 1 OpStore %r4 %278 OpBranch %127 %279 = OpLabel OpBranch %269 %268 = OpLabel OpBranch %269 %269 = OpLabel %280 = OpLoad %v4float %r1 %281 = OpBitcast %v4int %280 %282 = OpCompositeExtract %int %281 3 %283 = OpVectorShuffle %v2int %281 %281 0 1 OpSelectionMerge %284 None OpBranchConditional %t0_bound %285 %286 %285 = OpLabel %287 = OpLoad %17 %t0 %288 = OpImageFetch %v4float %287 %283 Lod %282 OpBranch %284 %286 = OpLabel OpBranch %284 %284 = OpLabel %294 = OpPhi %v4float %288 %285 %293 %286 OpStore %r6 %294 %295 = OpLoad %v4float %r6 %296 = OpVectorShuffle %v2float %295 %295 2 3 OpSelectionMerge %297 None OpBranchConditional %cb0_bound %298 %299 %298 = OpLabel %302 = OpAccessChain %_ptr_Uniform_v4float %cb0 %int_0_0 %int_22 %303 = OpLoad %v4float %302 OpBranch %297 %299 = OpLabel OpBranch %297 %297 = OpLabel %309 = OpPhi %v4float %303 %298 %308 %299 %310 = OpVectorShuffle %v2float %309 %309 2 2 %311 = OpFMul %v2float %296 %310 %312 = OpLoad %v4float %r1 %313 = OpVectorShuffle %v4float %312 %311 4 5 2 3 OpStore %r1 %313 %314 = OpLoad %v4float %r1 %315 = OpVectorShuffle %v2float %314 %314 0 1 %316 = OpLoad %v4float %r1 %317 = OpVectorShuffle %v2float %316 %316 0 1 %318 = OpDot %float %315 %317 %319 = OpLoad %v4float %r4 %320 = OpCompositeInsert %v4float %318 %319 2 OpStore %r4 %320 %321 = OpLoad %v4float %r4 %322 = OpCompositeExtract %float %321 2 %324 = OpBitcast %float %uint_841731191 %325 = OpFAdd %float %322 %324 %326 = OpLoad %v4float %r4 %327 = OpCompositeInsert %v4float %325 %326 3 OpStore %r4 %327 %328 = OpLoad %v4float %r4 %329 = OpCompositeExtract %float %328 3 %330 = OpBitcast %int %329 %332 = OpShiftRightArithmetic %int %330 %uint_1_1 %333 = OpBitcast %float %332 %334 = OpLoad %v4float %r4 %335 = OpCompositeInsert %v4float %333 %334 3 OpStore %r4 %335 %336 = OpLoad %v4float %r4 %337 = OpCompositeExtract %float %336 3 %338 = OpBitcast %int %337 %339 = OpSNegate %int %338 %341 = OpBitcast %int %uint_1597463007 %342 = OpIAdd %int %339 %341 %343 = OpBitcast %float %342 %344 = OpLoad %v4float %r4 %345 = OpCompositeInsert %v4float %343 %344 3 OpStore %r4 %345 %346 = OpLoad %v4float %r4 %347 = OpCompositeExtract %float %346 3 %348 = OpLoad %v4float %r4 %349 = OpCompositeExtract %float %348 2 %350 = OpFMul %float %347 %349 %351 = OpLoad %v4float %r2 %352 = OpCompositeInsert %v4float %350 %351 0 OpStore %r2 %352 %353 = OpLoad %v4float %r1 %354 = OpVectorShuffle %v2float %353 %353 0 1 %355 = OpLoad %v4float %r4 %356 = OpVectorShuffle %v2float %355 %355 3 3 %357 = OpFMul %v2float %354 %356 %358 = OpLoad %v4float %r7 %359 = OpVectorShuffle %v4float %358 %357 4 5 2 3 OpStore %r7 %359 %360 = OpLoad %v4float %r7 %361 = OpCompositeExtract %float %360 1 %362 = OpExtInst %float %1 FAbs %361 %363 = OpLoad %v4float %r7 %364 = OpCompositeExtract %float %363 0 %365 = OpExtInst %float %1 FAbs %364 %366 = OpFAdd %float %362 %365 %367 = OpLoad %v4float %r1 %368 = OpCompositeInsert %v4float %366 %367 0 OpStore %r1 %368 %369 = OpLoad %v4float %r1 %370 = OpVectorShuffle %v2float %369 %369 0 0 %374 = OpBitcast %v2float %373 %375 = OpLoad %v4float %r2 %376 = OpVectorShuffle %v2float %375 %375 0 1 %377 = OpExtInst %v2float %1 Fma %370 %374 %376 %378 = OpLoad %v4float %r1 %379 = OpVectorShuffle %v4float %378 %377 4 5 2 3 OpStore %r1 %379 %380 = OpLoad %v4float %r2 %381 = OpVectorShuffle %v2float %380 %380 3 2 %382 = OpBitcast %v2int %381 %383 = OpConvertSToF %v2float %382 %384 = OpLoad %v4float %r4 %385 = OpVectorShuffle %v4float %384 %383 0 1 4 5 OpStore %r4 %385 %386 = OpLoad %v4float %r7 %387 = OpVectorShuffle %v2float %386 %386 0 1 %388 = OpLoad %v4float %r4 %389 = OpVectorShuffle %v2float %388 %388 2 3 %390 = OpDot %float %387 %389 %391 = OpLoad %v4float %r8 %392 = OpCompositeInsert %v4float %390 %391 0 OpStore %r8 %392 %393 = OpLoad %v4float %r7 %394 = OpCompositeExtract %float %393 1 %395 = OpFNegate %float %394 %396 = OpLoad %v4float %r7 %397 = OpCompositeInsert %v4float %395 %396 2 OpStore %r7 %397 %398 = OpLoad %v4float %r7 %399 = OpVectorShuffle %v2float %398 %398 2 0 %400 = OpLoad %v4float %r4 %401 = OpVectorShuffle %v2float %400 %400 2 3 %402 = OpDot %float %399 %401 %403 = OpLoad %v4float %r8 %404 = OpCompositeInsert %v4float %402 %403 1 OpStore %r8 %404 %405 = OpLoad %v4float %r8 %406 = OpVectorShuffle %v2float %405 %405 0 1 %407 = OpExtInst %v2float %1 FAbs %406 %408 = OpLoad %v4float %r1 %409 = OpVectorShuffle %v2float %408 %408 0 1 %410 = OpFOrdLessThan %v2bool %407 %409 %415 = OpSelect %v2uint %410 %414 %413 %416 = OpBitcast %v2float %415 %417 = OpLoad %v4float %r1 %418 = OpVectorShuffle %v4float %417 %416 4 5 2 3 OpStore %r1 %418 %419 = OpLoad %v4float %r1 %420 = OpCompositeExtract %float %419 1 %421 = OpBitcast %uint %420 %422 = OpLoad %v4float %r1 %423 = OpCompositeExtract %float %422 0 %424 = OpBitcast %uint %423 %425 = OpBitwiseAnd %uint %421 %424 %426 = OpBitcast %float %425 %427 = OpLoad %v4float %r1 %428 = OpCompositeInsert %v4float %426 %427 0 OpStore %r1 %428 %429 = OpLoad %v4float %r5 %430 = OpVectorShuffle %v2float %429 %429 0 1 %431 = OpLoad %v4float %r5 %432 = OpVectorShuffle %v2float %431 %431 0 1 %433 = OpDot %float %430 %432 %434 = OpLoad %v4float %r1 %435 = OpCompositeInsert %v4float %433 %434 1 OpStore %r1 %435 %436 = OpLoad %v4float %r6 %437 = OpVectorShuffle %v2float %436 %436 0 1 %438 = OpLoad %v4float %r6 %439 = OpVectorShuffle %v2float %438 %438 0 1 %440 = OpDot %float %437 %439 %441 = OpLoad %v4float %r2 %442 = OpCompositeInsert %v4float %440 %441 0 OpStore %r2 %442 %443 = OpLoad %v4float %r1 %444 = OpCompositeExtract %float %443 1 %445 = OpLoad %v4float %r2 %446 = OpCompositeExtract %float %445 0 %447 = OpFOrdLessThan %bool %444 %446 %450 = OpSelect %uint %447 %uint_4294967295_6 %uint_0_19 %451 = OpBitcast %float %450 %452 = OpLoad %v4float %r1 %453 = OpCompositeInsert %v4float %451 %452 1 OpStore %r1 %453 %454 = OpLoad %v4float %r1 %455 = OpVectorShuffle %v2float %454 %454 1 1 %456 = OpBitcast %v2uint %455 %457 = OpLoad %v4float %r5 %458 = OpVectorShuffle %v2float %457 %457 0 1 %459 = OpLoad %v4float %r6 %460 = OpVectorShuffle %v2float %459 %459 0 1 %463 = OpINotEqual %v2bool %456 %462 %464 = OpSelect %v2float %463 %458 %460 %465 = OpLoad %v4float %r7 %466 = OpVectorShuffle %v4float %465 %464 4 5 2 3 OpStore %r7 %466 %467 = OpLoad %v4float %r5 %468 = OpVectorShuffle %v2float %467 %467 2 3 %469 = OpLoad %v4float %r5 %470 = OpVectorShuffle %v2float %469 %469 2 3 %471 = OpDot %float %468 %470 %472 = OpLoad %v4float %r1 %473 = OpCompositeInsert %v4float %471 %472 1 OpStore %r1 %473 %474 = OpLoad %v4float %r6 %475 = OpVectorShuffle %v2float %474 %474 2 3 %476 = OpLoad %v4float %r6 %477 = OpVectorShuffle %v2float %476 %476 2 3 %478 = OpDot %float %475 %477 %479 = OpLoad %v4float %r2 %480 = OpCompositeInsert %v4float %478 %479 0 OpStore %r2 %480 %481 = OpLoad %v4float %r2 %482 = OpCompositeExtract %float %481 0 %483 = OpLoad %v4float %r1 %484 = OpCompositeExtract %float %483 1 %485 = OpFOrdLessThan %bool %482 %484 %488 = OpSelect %uint %485 %uint_4294967295_7 %uint_0_21 %489 = OpBitcast %float %488 %490 = OpLoad %v4float %r1 %491 = OpCompositeInsert %v4float %489 %490 1 OpStore %r1 %491 %492 = OpLoad %v4float %r1 %493 = OpVectorShuffle %v2float %492 %492 1 1 %494 = OpBitcast %v2uint %493 %495 = OpLoad %v4float %r5 %496 = OpVectorShuffle %v2float %495 %495 2 3 %497 = OpLoad %v4float %r6 %498 = OpVectorShuffle %v2float %497 %497 2 3 %501 = OpINotEqual %v2bool %494 %500 %502 = OpSelect %v2float %501 %496 %498 %503 = OpLoad %v4float %r7 %504 = OpVectorShuffle %v4float %503 %502 0 1 4 5 OpStore %r7 %504 %505 = OpLoad %v4float %r1 %506 = OpVectorShuffle %v4float %505 %505 0 0 0 0 %508 = OpBitcast %v4uint %506 %509 = OpLoad %v4float %r7 %510 = OpLoad %v4float %r5 %514 = OpINotEqual %v4bool %508 %513 %515 = OpSelect %v4float %514 %509 %510 OpStore %r5 %515 %516 = OpLoad %v4float %r2 %517 = OpCompositeExtract %float %516 2 %518 = OpBitcast %int %517 %520 = OpBitcast %int %uint_1_2 %521 = OpIAdd %int %518 %520 %522 = OpBitcast %float %521 %523 = OpLoad %v4float %r4 %524 = OpCompositeInsert %v4float %522 %523 1 OpStore %r4 %524 OpBranch %127 %127 = OpLabel OpBranch %125 %128 = OpLabel %525 = OpLoad %v4float %r5 OpStore %r3 %525 %526 = OpLoad %v4float %r2 %527 = OpCompositeExtract %float %526 3 %528 = OpBitcast %int %527 %530 = OpBitcast %int %uint_1_3 %531 = OpIAdd %int %528 %530 %532 = OpBitcast %float %531 %533 = OpLoad %v4float %r2 %534 = OpCompositeInsert %v4float %532 %533 3 OpStore %r2 %534 OpBranch %87 %87 = OpLabel OpBranch %85 %88 = OpLabel %535 = OpLoad %v3uint %vThreadId %536 = OpVectorShuffle %v2uint %535 %535 0 1 OpSelectionMerge %537 None OpBranchConditional %cb0_bound %538 %539 %538 = OpLabel %542 = OpAccessChain %_ptr_Uniform_v4float %cb0 %int_0_1 %int_16_0 %543 = OpLoad %v4float %542 OpBranch %537 %539 = OpLabel OpBranch %537 %537 = OpLabel %549 = OpPhi %v4float %543 %538 %548 %539 %550 = OpVectorShuffle %v2float %549 %549 2 3 %551 = OpBitcast %v2uint %550 %552 = OpULessThan %v2bool %536 %551 %557 = OpSelect %v2uint %552 %556 %555 %558 = OpBitcast %v2float %557 %559 = OpLoad %v4float %r0 %560 = OpVectorShuffle %v4float %559 %558 4 5 2 3 OpStore %r0 %560 %561 = OpLoad %v4float %r0 %562 = OpCompositeExtract %float %561 1 %563 = OpBitcast %uint %562 %564 = OpLoad %v4float %r0 %565 = OpCompositeExtract %float %564 0 %566 = OpBitcast %uint %565 %567 = OpBitwiseAnd %uint %563 %566 %568 = OpBitcast %float %567 %569 = OpLoad %v4float %r0 %570 = OpCompositeInsert %v4float %568 %569 0 OpStore %r0 %570 %571 = OpLoad %v4float %r0 %572 = OpCompositeExtract %float %571 0 %573 = OpBitcast %uint %572 %575 = OpINotEqual %bool %573 %uint_0_25 OpSelectionMerge %578 None OpBranchConditional %575 %576 %577 %576 = OpLabel %579 = OpLoad %v3uint %vThreadId %580 = OpVectorShuffle %v2uint %579 %579 0 1 %581 = OpBitcast %v2int %580 %582 = OpLoad %v4float %r3 %583 = OpLoad %22 %u0 OpImageWrite %583 %581 %582 OpBranch %578 %577 = OpLabel OpBranch %578 %578 = OpLabel OpReturn OpFunctionEnd %main = OpFunction %void None %5 %584 = OpLabel %585 = OpFunctionCall %void %cs_main OpReturn OpFunctionEnd NIR: shader: MESA_SHADER_COMPUTE local-size: 16, 16, 1 shared-size: 1 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE sampler2D t0 (0, 0, 1) decl_var uniform INTERP_MODE_NONE image2D u0 (0, 0, 2) decl_function main returning void impl main { decl_var INTERP_MODE_NONE vec4 r7 decl_var INTERP_MODE_NONE vec4 r1 decl_var INTERP_MODE_NONE vec4 r4 decl_var INTERP_MODE_NONE vec4 r6 decl_var INTERP_MODE_NONE vec4 r2 decl_var INTERP_MODE_NONE vec4 r5 decl_var INTERP_MODE_NONE vec4 r0 decl_var INTERP_MODE_NONE vec4 r3 decl_var INTERP_MODE_NONE vec4 r8 block block_0: /* preds: */ vec1 32 ssa_0 = undefined vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_2 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000001 /* 0.000000 */) vec2 32 ssa_4 = load_const (0x3f7d70a4 /* 0.990000 */, 0x3f7d70a4 /* 0.990000 */) vec1 32 ssa_5 = load_const (0x5f3759df /* 13211836172961054720.000000 */) vec1 32 ssa_6 = load_const (0x322bcc77 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = load_const (0xfffffffd /* -nan */) vec3 32 ssa_9 = intrinsic load_work_group_id () () () vec3 32 ssa_10 = intrinsic load_local_invocation_id () () () vec1 32 ssa_11 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_12 = ishl ssa_9.x, ssa_11 vec1 32 ssa_13 = ishl ssa_9.y, ssa_11 vec1 32 ssa_14 = iadd ssa_12, ssa_10.x vec1 32 ssa_15 = iadd ssa_13, ssa_10.y vec2 32 ssa_16 = vec2 ssa_14, ssa_15 vec4 32 ssa_17 = txf ssa_16 (coord), ssa_1 (lod), t0 (texture) vec1 32 ssa_18 = imov ssa_17.w vec1 32 ssa_19 = imov ssa_17.z vec1 32 ssa_20 = imov ssa_17.y vec1 32 ssa_21 = imov ssa_17.x /* succs: block_1 */ loop { block block_1: /* preds: block_0 block_15 */ vec1 32 ssa_22 = phi block_0: ssa_21, block_15: ssa_33 vec1 32 ssa_23 = phi block_0: ssa_20, block_15: ssa_32 vec1 32 ssa_24 = phi block_0: ssa_19, block_15: ssa_31 vec1 32 ssa_25 = phi block_0: ssa_18, block_15: ssa_30 vec1 32 ssa_26 = phi block_0: ssa_8, block_15: ssa_126 vec1 32 ssa_27 = ilt ssa_7, ssa_26 /* succs: block_2 block_3 */ if ssa_27 { block block_2: /* preds: block_1 */ break /* succs: block_16 */ } else { block block_3: /* preds: block_1 */ /* succs: block_4 */ } block block_4: /* preds: block_3 */ vec1 32 ssa_28 = ieq ssa_26, ssa_1 /* succs: block_5 */ loop { block block_5: /* preds: block_4 block_9 block_12 block_14 */ vec1 32 ssa_29 = phi block_4: ssa_8, block_9: ssa_3, block_12: ssa_50, block_14: ssa_125 vec1 32 ssa_30 = phi block_4: ssa_25, block_9: ssa_30, block_12: ssa_30, block_14: ssa_124 vec1 32 ssa_31 = phi block_4: ssa_24, block_9: ssa_31, block_12: ssa_31, block_14: ssa_123 vec1 32 ssa_32 = phi block_4: ssa_23, block_9: ssa_32, block_12: ssa_32, block_14: ssa_122 vec1 32 ssa_33 = phi block_4: ssa_22, block_9: ssa_33, block_12: ssa_33, block_14: ssa_121 vec1 32 ssa_34 = ilt ssa_7, ssa_29 /* succs: block_6 block_7 */ if ssa_34 { block block_6: /* preds: block_5 */ break /* succs: block_15 */ } else { block block_7: /* preds: block_5 */ /* succs: block_8 */ } block block_8: /* preds: block_7 */ vec1 32 ssa_35 = ieq ssa_29, ssa_1 vec1 32 ssa_36 = iand ssa_35, ssa_28 /* succs: block_9 block_10 */ if ssa_36 { block block_9: /* preds: block_8 */ continue /* succs: block_5 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 */ } block block_11: /* preds: block_10 */ vec1 32 ssa_37 = iadd ssa_26, ssa_14 vec1 32 ssa_38 = iadd ssa_29, ssa_15 vec1 32 ssa_39 = ige ssa_37, ssa_2.x vec1 32 ssa_40 = ige ssa_38, ssa_2.y vec1 32 ssa_41 = intrinsic vulkan_resource_index (ssa_1) () (0, 0) /* desc-set=0 */ /* binding=0 */ vec1 32 ssa_42 = load_const (0x00000100 /* 0.000000 */) vec4 32 ssa_43 = intrinsic load_ubo (ssa_41, ssa_42) () () vec1 32 ssa_44 = ilt ssa_37, ssa_43.z vec1 32 ssa_45 = ilt ssa_38, ssa_43.w vec1 32 ssa_46 = iand ssa_39, ssa_44 vec1 32 ssa_47 = iand ssa_40, ssa_45 vec1 32 ssa_48 = iand ssa_47, ssa_46 vec1 32 ssa_49 = ieq ssa_48, ssa_1 /* succs: block_12 block_13 */ if ssa_49 { block block_12: /* preds: block_11 */ vec1 32 ssa_50 = iadd ssa_29, ssa_3 continue /* succs: block_5 */ } else { block block_13: /* preds: block_11 */ /* succs: block_14 */ } block block_14: /* preds: block_13 */ vec2 32 ssa_51 = vec2 ssa_37, ssa_38 vec4 32 ssa_52 = txf ssa_51 (coord), ssa_1 (lod), t0 (texture) vec1 32 ssa_53 = load_const (0x00000160 /* 0.000000 */) vec4 32 ssa_54 = intrinsic load_ubo (ssa_41, ssa_53) () () vec1 32 ssa_55 = fmul ssa_52.z, ssa_54.z vec1 32 ssa_56 = fmul ssa_52.w, ssa_54.z vec1 32 ssa_57 = fmul ssa_55, ssa_55 vec1 32 ssa_58 = fmul ssa_56, ssa_56 vec1 32 ssa_59 = fadd ssa_57, ssa_58 vec1 32 ssa_60 = fadd ssa_59, ssa_6 vec1 32 ssa_61 = ishr ssa_60, ssa_3 vec1 32 ssa_62 = ineg ssa_61 vec1 32 ssa_63 = iadd ssa_62, ssa_5 vec1 32 ssa_64 = fmul ssa_63, ssa_59 vec1 32 ssa_65 = fmul ssa_55, ssa_63 vec1 32 ssa_66 = fmul ssa_56, ssa_63 vec1 32 ssa_67 = fabs ssa_66 vec1 32 ssa_68 = fabs ssa_65 vec1 32 ssa_69 = fadd ssa_67, ssa_68 vec1 32 ssa_70 = fmul ssa_69, ssa_4.x vec1 32 ssa_71 = fadd ssa_70, ssa_64 vec1 32 ssa_72 = fmul ssa_69, ssa_4.y vec1 32 ssa_73 = i2f32 ssa_26 vec1 32 ssa_74 = i2f32 ssa_29 vec1 32 ssa_75 = fmul ssa_65, ssa_73 vec1 32 ssa_76 = fmul ssa_66, ssa_74 vec1 32 ssa_77 = fadd ssa_75, ssa_76 vec1 32 ssa_78 = fmul ssa_66, ssa_73 vec1 32 ssa_79 = fneg ssa_78 vec1 32 ssa_80 = fmul ssa_65, ssa_74 vec1 32 ssa_81 = fadd ssa_79, ssa_80 vec1 32 ssa_82 = fabs ssa_77 vec1 32 ssa_83 = fabs ssa_81 vec1 32 ssa_84 = feq ssa_71, ssa_71 vec1 32 ssa_85 = feq ssa_72, ssa_72 vec1 32 ssa_86 = feq ssa_82, ssa_82 vec1 32 ssa_87 = feq ssa_83, ssa_83 vec1 32 ssa_88 = iand ssa_86, ssa_84 vec1 32 ssa_89 = iand ssa_87, ssa_85 vec1 32 ssa_90 = flt ssa_82, ssa_71 vec1 32 ssa_91 = flt ssa_83, ssa_72 vec1 32 ssa_92 = iand ssa_90, ssa_88 vec1 32 ssa_93 = iand ssa_91, ssa_89 vec1 32 ssa_94 = iand ssa_93, ssa_92 vec1 32 ssa_95 = fmul ssa_33, ssa_33 vec1 32 ssa_96 = fmul ssa_32, ssa_32 vec1 32 ssa_97 = fadd ssa_95, ssa_96 vec1 32 ssa_98 = fmul ssa_52.x, ssa_52.x vec1 32 ssa_99 = fmul ssa_52.y, ssa_52.y vec1 32 ssa_100 = fadd ssa_98, ssa_99 vec1 32 ssa_101 = feq ssa_100, ssa_100 vec1 32 ssa_102 = feq ssa_97, ssa_97 vec1 32 ssa_103 = iand ssa_102, ssa_101 vec1 32 ssa_104 = flt ssa_97, ssa_100 vec1 32 ssa_105 = iand ssa_104, ssa_103 vec1 32 ssa_106 = bcsel ssa_105, ssa_33, ssa_52.x vec1 32 ssa_107 = bcsel ssa_105, ssa_32, ssa_52.y vec1 32 ssa_108 = fmul ssa_31, ssa_31 vec1 32 ssa_109 = fmul ssa_30, ssa_30 vec1 32 ssa_110 = fadd ssa_108, ssa_109 vec1 32 ssa_111 = fmul ssa_52.z, ssa_52.z vec1 32 ssa_112 = fmul ssa_52.w, ssa_52.w vec1 32 ssa_113 = fadd ssa_111, ssa_112 vec1 32 ssa_114 = feq ssa_110, ssa_110 vec1 32 ssa_115 = feq ssa_113, ssa_113 vec1 32 ssa_116 = iand ssa_115, ssa_114 vec1 32 ssa_117 = flt ssa_113, ssa_110 vec1 32 ssa_118 = iand ssa_117, ssa_116 vec1 32 ssa_119 = bcsel ssa_118, ssa_31, ssa_52.z vec1 32 ssa_120 = bcsel ssa_118, ssa_30, ssa_52.w vec1 32 ssa_121 = bcsel ssa_94, ssa_106, ssa_33 vec1 32 ssa_122 = bcsel ssa_94, ssa_107, ssa_32 vec1 32 ssa_123 = bcsel ssa_94, ssa_119, ssa_31 vec1 32 ssa_124 = bcsel ssa_94, ssa_120, ssa_30 vec1 32 ssa_125 = iadd ssa_29, ssa_3 /* succs: block_5 */ } block block_15: /* preds: block_6 */ vec1 32 ssa_126 = iadd ssa_26, ssa_3 /* succs: block_1 */ } block block_16: /* preds: block_2 */ vec1 32 ssa_127 = intrinsic vulkan_resource_index (ssa_1) () (0, 0) /* desc-set=0 */ /* binding=0 */ vec1 32 ssa_128 = load_const (0x00000100 /* 0.000000 */) vec4 32 ssa_129 = intrinsic load_ubo (ssa_127, ssa_128) () () vec1 32 ssa_130 = ult ssa_14, ssa_129.z vec1 32 ssa_131 = ult ssa_15, ssa_129.w vec1 32 ssa_132 = iand ssa_131, ssa_130 /* succs: block_17 block_18 */ if ssa_132 { block block_17: /* preds: block_16 */ vec4 32 ssa_133 = vec4 ssa_22, ssa_23, ssa_24, ssa_25 vec4 32 ssa_134 = vec4 ssa_14, ssa_15, ssa_15, ssa_15 intrinsic image_store (ssa_134, ssa_0, ssa_133) (u0) () /* succs: block_19 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 */ } block block_19: /* preds: block_17 block_18 */ /* succs: block_0 */ block block_0: } LLVM IR: ; ModuleID = 'shader' source_filename = "shader" target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5" target triple = "amdgcn-mesa-mesa3d" define amdgpu_cs void @main([0 x i8] addrspace(4)* inreg noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, <3 x i32>) #0 { main_body: %4 = shl i32 %1, 4 %5 = shl i32 %2, 4 %6 = extractelement <3 x i32> %3, i32 0 %7 = add i32 %4, %6 %8 = extractelement <3 x i32> %3, i32 1 %9 = add i32 %5, %8 %10 = getelementptr [0 x i8], [0 x i8] addrspace(4)* %0, i64 0, i64 32 %11 = bitcast i8 addrspace(4)* %10 to <8 x i32> addrspace(4)* %12 = load <8 x i32>, <8 x i32> addrspace(4)* %11, align 32, !invariant.load !0 %13 = insertelement <2 x i32> undef, i32 %7, i32 0 %14 = insertelement <2 x i32> %13, i32 %9, i32 1 %15 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %14, <8 x i32> %12, i32 15, i1 false, i1 false, i1 false, i1 false) #3 %16 = bitcast <4 x float> %15 to <4 x i32> %17 = extractelement <4 x i32> %16, i32 3 %18 = extractelement <4 x i32> %16, i32 2 %19 = extractelement <4 x i32> %16, i32 1 %20 = extractelement <4 x i32> %16, i32 0 %21 = bitcast [0 x i8] addrspace(4)* %0 to <4 x i32> addrspace(4)* %22 = getelementptr [0 x i8], [0 x i8] addrspace(4)* %0, i64 0, i64 32 %23 = bitcast i8 addrspace(4)* %22 to <8 x i32> addrspace(4)* br label %loop1 loop1: ; preds = %endloop5, %main_body %24 = phi i32 [ %20, %main_body ], [ %.ph40, %endloop5 ] %25 = phi i32 [ %19, %main_body ], [ %.ph39, %endloop5 ] %26 = phi i32 [ %18, %main_body ], [ %.ph38, %endloop5 ] %27 = phi i32 [ %17, %main_body ], [ %.ph37, %endloop5 ] %28 = phi i32 [ -3, %main_body ], [ %135, %endloop5 ] %29 = icmp sgt i32 %28, 3 br i1 %29, label %endloop1, label %endif2 endif2: ; preds = %loop1 %30 = add i32 %28, %7 %.lobit = ashr i32 %30, 31 %.lobit.not = xor i32 %.lobit, -1 %31 = sitofp i32 %28 to float br label %loop5.outer loop5.outer: ; preds = %else13, %endif2 %.ph = phi i32 [ %134, %else13 ], [ -3, %endif2 ] %.ph37 = phi i32 [ %133, %else13 ], [ %27, %endif2 ] %.ph38 = phi i32 [ %132, %else13 ], [ %26, %endif2 ] %.ph39 = phi i32 [ %131, %else13 ], [ %25, %endif2 ] %.ph40 = phi i32 [ %130, %else13 ], [ %24, %endif2 ] br label %loop5 loop5: ; preds = %loop5.backedge, %loop5.outer %32 = phi i32 [ %.ph, %loop5.outer ], [ %.be, %loop5.backedge ] %33 = icmp sgt i32 %32, 3 br i1 %33, label %endloop5, label %endif6 endif6: ; preds = %loop5 %34 = or i32 %32, %28 %35 = icmp eq i32 %34, 0 br i1 %35, label %loop5.backedge, label %endif9 loop5.backedge: ; preds = %endif6, %if12 %.be = phi i32 [ %48, %if12 ], [ 1, %endif6 ] br label %loop5 endif9: ; preds = %endif6 %36 = add i32 %32, %9 %.lobit49 = ashr i32 %36, 31 %.lobit49.not = xor i32 %.lobit49, -1 %37 = load <4 x i32>, <4 x i32> addrspace(4)* %21, align 16, !invariant.load !0 %38 = call float @llvm.SI.load.const.v4i32(<4 x i32> %37, i32 264) %39 = call float @llvm.SI.load.const.v4i32(<4 x i32> %37, i32 268) %40 = bitcast float %38 to i32 %41 = icmp slt i32 %30, %40 %42 = bitcast float %39 to i32 %43 = icmp slt i32 %36, %42 %44 = select i1 %41, i32 %.lobit.not, i32 0 %45 = select i1 %43, i32 %.lobit49.not, i32 0 %46 = and i32 %45, %44 %47 = icmp eq i32 %46, 0 br i1 %47, label %if12, label %else13 if12: ; preds = %endif9 %48 = add i32 %32, 1 br label %loop5.backedge else13: ; preds = %endif9 %49 = bitcast [0 x i8] addrspace(4)* %0 to <4 x i32> addrspace(4)*, !amdgpu.uniform !0 %50 = load <8 x i32>, <8 x i32> addrspace(4)* %23, align 32, !invariant.load !0 %51 = insertelement <2 x i32> undef, i32 %30, i32 0 %52 = insertelement <2 x i32> %51, i32 %36, i32 1 %53 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %52, <8 x i32> %50, i32 15, i1 false, i1 false, i1 false, i1 false) #3 %54 = bitcast <4 x float> %53 to <4 x i32> %55 = load <4 x i32>, <4 x i32> addrspace(4)* %49, align 16, !invariant.load !0 %56 = call float @llvm.SI.load.const.v4i32(<4 x i32> %55, i32 360) %57 = extractelement <4 x float> %53, i32 2 %58 = fmul float %57, %56 %59 = extractelement <4 x float> %53, i32 3 %60 = fmul float %59, %56 %61 = fmul float %58, %58 %62 = fmul float %60, %60 %63 = fadd float %61, %62 %64 = fadd float %63, 0x3E45798EE0000000 %65 = bitcast float %64 to i32 %66 = ashr i32 %65, 1 %67 = sub i32 1597463007, %66 %68 = bitcast i32 %67 to float %69 = fmul float %63, %68 %70 = bitcast i32 %67 to float %71 = fmul float %58, %70 %72 = bitcast i32 %67 to float %73 = fmul float %60, %72 %74 = call float @llvm.fabs.f32(float %73) #3 %75 = call float @llvm.fabs.f32(float %71) #3 %76 = fadd float %74, %75 %77 = fmul float %76, 0x3FEFAE1480000000 %78 = fadd float %77, %69 %79 = fmul float %76, 0x3FEFAE1480000000 %80 = sitofp i32 %32 to float %81 = fmul float %71, %31 %82 = fmul float %73, %80 %83 = fadd float %81, %82 %84 = fmul float %73, %31 %85 = fmul float %71, %80 %86 = fsub float %85, %84 %87 = call float @llvm.fabs.f32(float %83) #3 %88 = call float @llvm.fabs.f32(float %86) #3 %89 = fcmp olt float %87, %78 %90 = fcmp olt float %88, %79 %91 = and i1 %90, %89 %92 = bitcast i32 %.ph40 to float %93 = bitcast i32 %.ph40 to float %94 = fmul float %92, %93 %95 = bitcast i32 %.ph39 to float %96 = bitcast i32 %.ph39 to float %97 = fmul float %95, %96 %98 = fadd float %94, %97 %99 = extractelement <4 x float> %53, i32 0 %100 = extractelement <4 x float> %53, i32 0 %101 = fmul float %99, %100 %102 = extractelement <4 x float> %53, i32 1 %103 = extractelement <4 x float> %53, i32 1 %104 = fmul float %102, %103 %105 = fadd float %101, %104 %106 = fcmp olt float %98, %105 %107 = extractelement <4 x i32> %54, i32 0 %108 = select i1 %106, i32 %.ph40, i32 %107 %109 = extractelement <4 x i32> %54, i32 1 %110 = select i1 %106, i32 %.ph39, i32 %109 %111 = bitcast i32 %.ph38 to float %112 = bitcast i32 %.ph38 to float %113 = fmul float %111, %112 %114 = bitcast i32 %.ph37 to float %115 = bitcast i32 %.ph37 to float %116 = fmul float %114, %115 %117 = fadd float %113, %116 %118 = extractelement <4 x float> %53, i32 2 %119 = extractelement <4 x float> %53, i32 2 %120 = fmul float %118, %119 %121 = extractelement <4 x float> %53, i32 3 %122 = extractelement <4 x float> %53, i32 3 %123 = fmul float %121, %122 %124 = fadd float %120, %123 %125 = fcmp olt float %124, %117 %126 = extractelement <4 x i32> %54, i32 2 %127 = select i1 %125, i32 %.ph38, i32 %126 %128 = extractelement <4 x i32> %54, i32 3 %129 = select i1 %125, i32 %.ph37, i32 %128 %130 = select i1 %91, i32 %108, i32 %.ph40 %131 = select i1 %91, i32 %110, i32 %.ph39 %132 = select i1 %91, i32 %127, i32 %.ph38 %133 = select i1 %91, i32 %129, i32 %.ph37 %134 = add i32 %32, 1 br label %loop5.outer endloop5: ; preds = %loop5 %135 = add i32 %28, 1 br label %loop1 endloop1: ; preds = %loop1 %136 = bitcast [0 x i8] addrspace(4)* %0 to <4 x i32> addrspace(4)*, !amdgpu.uniform !0 %137 = load <4 x i32>, <4 x i32> addrspace(4)* %136, align 16, !invariant.load !0 %138 = call float @llvm.SI.load.const.v4i32(<4 x i32> %137, i32 264) %139 = call float @llvm.SI.load.const.v4i32(<4 x i32> %137, i32 268) %140 = bitcast float %138 to i32 %141 = icmp ult i32 %7, %140 %142 = bitcast float %139 to i32 %143 = icmp ult i32 %9, %142 %144 = and i1 %143, %141 br i1 %144, label %if17, label %endif17 if17: ; preds = %endloop1 %145 = insertelement <4 x i32> undef, i32 %24, i32 0 %146 = insertelement <4 x i32> %145, i32 %25, i32 1 %147 = insertelement <4 x i32> %146, i32 %26, i32 2 %148 = insertelement <4 x i32> %147, i32 %27, i32 3 %149 = bitcast <4 x i32> %148 to <4 x float> %150 = insertelement <2 x i32> undef, i32 %7, i32 0 %151 = insertelement <2 x i32> %150, i32 %9, i32 1 %152 = getelementptr [0 x i8], [0 x i8] addrspace(4)* %0, i64 0, i64 96 %153 = bitcast i8 addrspace(4)* %152 to <8 x i32> addrspace(4)* %154 = load <8 x i32>, <8 x i32> addrspace(4)* %153, align 32, !invariant.load !0 call void @llvm.amdgcn.image.store.v4f32.v2i32.v8i32(<4 x float> %149, <2 x i32> %151, <8 x i32> %154, i32 15, i1 false, i1 false, i1 false, i1 false) #5 br label %endif17 endif17: ; preds = %endloop1, %if17 ret void } ; Function Attrs: nounwind readnone speculatable declare i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr() #1 ; Function Attrs: nounwind readonly declare <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #2 ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #3 ; Function Attrs: nounwind readnone speculatable declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind writeonly declare void @llvm.amdgcn.image.store.v4f32.v2i32.v8i32(<4 x float>, <2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #4 attributes #0 = { "amdgpu-max-work-group-size"="0x100" } attributes #1 = { nounwind readnone speculatable } attributes #2 = { nounwind readonly } attributes #3 = { nounwind readnone } attributes #4 = { nounwind writeonly } attributes #5 = { nounwind } !0 = !{} DISASM: main: BB0_0: s_load_dwordx8 s[8:15], s[2:3], 0x20 ; C00E0201 00000020 s_lshl_b32 s0, s4, 4 ; 8E008404 s_lshl_b32 s1, s5, 4 ; 8E018405 v_add_u32_e32 v0, vcc, s0, v0 ; 32000000 v_add_u32_e32 v1, vcc, s1, v1 ; 32020201 s_waitcnt lgkmcnt(0) ; BF8C007F image_load v[7:10], v[0:1], s[8:15] dmask:0xf unorm ; F0001F00 00020700 s_mov_b32 s4, -3 ; BE8400C3 BB0_1: s_waitcnt vmcnt(0) ; BF8C0F70 v_mov_b32_e32 v5, v10 ; 7E0A030A v_mov_b32_e32 v4, v9 ; 7E080309 v_mov_b32_e32 v3, v8 ; 7E060308 v_mov_b32_e32 v2, v7 ; 7E040307 s_cmp_gt_i32 s4, 3 ; BF028304 v_mov_b32_e32 v15, -1 ; 7E1E02C1 s_cbranch_scc1 BB0_15 ; BF850000 v_cvt_f32_i32_e32 v18, s4 ; 7E240A04 v_add_u32_e32 v15, vcc, s4, v0 ; 321E0004 v_ashrrev_i32_e32 v7, 31, v15 ; 220E1E9F v_not_b32_e32 v17, v7 ; 7E225707 s_mov_b64 s[6:7], 0 ; BE860180 v_mov_b32_e32 v16, -3 ; 7E2002C3 v_mov_b32_e32 v20, v5 ; 7E280305 v_mov_b32_e32 v21, v4 ; 7E2A0304 v_mov_b32_e32 v22, v3 ; 7E2C0303 v_mov_b32_e32 v23, v2 ; 7E2E0302 BB0_3: v_mov_b32_e32 v7, v23 ; 7E0E0317 v_mov_b32_e32 v8, v22 ; 7E100316 v_mov_b32_e32 v9, v21 ; 7E120315 v_mov_b32_e32 v10, v20 ; 7E140314 s_mov_b64 s[0:1], 0 ; BE800180 BB0_4: v_mov_b32_e32 v19, v16 ; 7E260310 v_cmp_gt_i32_e32 vcc, 4, v19 ; 7D882684 v_mov_b32_e32 v20, 0 ; 7E280280 s_and_saveexec_b64 s[16:17], vcc ; BE90206A s_xor_b64 s[16:17], exec, s[16:17] ; 8890107E s_cbranch_execz BB0_10 ; BF880000 BB0_5: v_or_b32_e32 v16, s4, v19 ; 28202604 v_cmp_ne_u32_e32 vcc, 0, v16 ; 7D9A2080 v_mov_b32_e32 v20, 0 ; 7E280280 s_or_b64 s[18:19], vcc, s[0:1] ; 8792006A v_mov_b32_e32 v16, 1 ; 7E200281 s_and_saveexec_b64 s[20:21], vcc ; BE94206A s_cbranch_execz BB0_9 ; BF880000 BB0_6: s_load_dwordx4 s[24:27], s[2:3], 0x0 ; C00A0601 00000000 v_add_u32_e32 v6, vcc, v19, v1 ; 320C0313 v_ashrrev_i32_e32 v11, 31, v6 ; 22160C9F v_not_b32_e32 v11, v11 ; 7E16570B v_mov_b32_e32 v20, -1 ; 7E2802C1 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dwordx2 s[22:23], s[24:27], 0x108 ; C026058C 00000108 v_mov_b32_e32 v16, 1 ; 7E200281 s_waitcnt lgkmcnt(0) ; BF8C007F v_cmp_gt_i32_e32 vcc, s22, v15 ; 7D881E16 v_cndmask_b32_e32 v12, 0, v17, vcc ; 00182280 v_cmp_gt_i32_e32 vcc, s23, v6 ; 7D880C17 v_cndmask_b32_e32 v11, 0, v11, vcc ; 00161680 v_and_b32_e32 v11, v11, v12 ; 2616190B v_cmp_eq_u32_e32 vcc, 0, v11 ; 7D941680 s_and_saveexec_b64 s[22:23], vcc ; BE96206A BB0_7: v_add_u32_e32 v16, vcc, 1, v19 ; 32202681 v_mov_b32_e32 v20, 0 ; 7E280280 s_mov_b64 s[18:19], s[0:1] ; BE920100 BB0_8: s_or_b64 exec, exec, s[22:23] ; 87FE167E v_mov_b32_e32 v11, s24 ; 7E160218 v_mov_b32_e32 v12, s25 ; 7E180219 v_mov_b32_e32 v13, s26 ; 7E1A021A v_mov_b32_e32 v14, s27 ; 7E1C021B BB0_9: s_or_b64 exec, exec, s[20:21] ; 87FE147E s_mov_b64 s[0:1], s[18:19] ; BE800112 BB0_10: s_or_b64 exec, exec, s[16:17] ; 87FE107E s_or_b64 s[0:1], s[16:17], s[0:1] ; 87800010 s_andn2_b64 exec, exec, s[0:1] ; 89FE007E s_cbranch_execnz BB0_4 ; BF890000 s_or_b64 exec, exec, s[0:1] ; 87FE007E v_cmp_ne_u32_e32 vcc, 0, v20 ; 7D9A2880 s_and_saveexec_b64 s[0:1], vcc ; BE80206A s_xor_b64 s[16:17], exec, s[0:1] ; 8890007E s_cbranch_execz BB0_13 ; BF880000 BB0_12: v_mov_b32_e32 v16, v6 ; 7E200306 image_load v[20:23], v[15:16], s[8:15] dmask:0xf unorm ; F0001F00 0002140F v_readfirstlane_b32 s20, v11 ; 7E28050B v_readfirstlane_b32 s21, v12 ; 7E2A050C v_readfirstlane_b32 s22, v13 ; 7E2C050D v_readfirstlane_b32 s23, v14 ; 7E2E050E s_buffer_load_dword s0, s[20:23], 0x168 ; C022000A 00000168 v_mul_f32_e32 v16, v8, v8 ; 0A201108 v_mul_f32_e32 v24, v10, v10 ; 0A30150A v_mac_f32_e32 v16, v7, v7 ; 2C200F07 v_mac_f32_e32 v24, v9, v9 ; 2C301309 v_cvt_f32_i32_e32 v25, v19 ; 7E320B13 s_waitcnt vmcnt(0) ; BF8C0F70 v_mul_f32_e32 v26, v23, v23 ; 0A342F17 v_mul_f32_e32 v28, v21, v21 ; 0A382B15 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v29, s0, v23 ; 0A3A2E00 v_mac_f32_e32 v28, v20, v20 ; 2C382914 v_mul_f32_e32 v27, s0, v22 ; 0A362C00 v_mul_f32_e32 v30, v29, v29 ; 0A3C3B1D v_mac_f32_e32 v26, v22, v22 ; 2C342D16 v_cmp_lt_f32_e32 vcc, v16, v28 ; 7C823910 v_cmp_lt_f32_e64 s[0:1], v26, v24 ; D0410000 0002311A v_mac_f32_e32 v30, v27, v27 ; 2C3C371B v_cndmask_b32_e32 v16, v20, v7, vcc ; 00200F14 v_cndmask_b32_e64 v20, v22, v9, s[0:1] ; D1000014 00021316 v_add_f32_e32 v22, 0x322bcc77, v30 ; 022C3CFF 322BCC77 v_ashrrev_i32_e32 v22, 1, v22 ; 222C2C81 v_cndmask_b32_e32 v21, v21, v8, vcc ; 002A1115 v_sub_u32_e32 v22, vcc, 0x5f3759df, v22 ; 342C2CFF 5F3759DF v_cndmask_b32_e64 v24, v23, v10, s[0:1] ; D1000018 00021517 v_mul_f32_e32 v26, v29, v22 ; 0A342D1D v_mul_f32_e32 v23, v27, v22 ; 0A2E2D1B v_add_f32_e64 v27, |v26|, |v23| ; D101031B 00022F1A v_mul_f32_e32 v28, v26, v18 ; 0A38251A v_mul_f32_e32 v26, v26, v25 ; 0A34331A v_mul_f32_e32 v27, 0x3f7d70a4, v27 ; 0A3636FF 3F7D70A4 v_mad_f32 v25, v23, v25, -v28 ; D1C10019 84723317 v_mac_f32_e32 v26, v23, v18 ; 2C342517 v_mad_f32 v22, v30, v22, v27 ; D1C10016 046E2D1E v_cmp_lt_f32_e64 s[0:1], |v25|, v27 ; D0410100 00023719 v_cmp_lt_f32_e64 s[18:19], |v26|, v22 ; D0410112 00022D1A s_and_b64 vcc, s[0:1], s[18:19] ; 86EA1200 v_cndmask_b32_e32 v22, v8, v21, vcc ; 002C2B08 v_cndmask_b32_e32 v21, v9, v20, vcc ; 002A2909 v_cndmask_b32_e32 v23, v7, v16, vcc ; 002E2107 v_cndmask_b32_e32 v20, v10, v24, vcc ; 0028310A v_add_u32_e32 v16, vcc, 1, v19 ; 32202681 BB0_13: s_or_b64 exec, exec, s[16:17] ; 87FE107E s_or_b64 s[6:7], s[16:17], s[6:7] ; 87860610 s_andn2_b64 exec, exec, s[6:7] ; 89FE067E s_cbranch_execnz BB0_3 ; BF890000 s_or_b64 exec, exec, s[6:7] ; 87FE067E s_add_i32 s4, s4, 1 ; 81048104 v_mov_b32_e32 v15, 0 ; 7E1E0280 s_branch BB0_16 ; BF820000 BB0_15: BB0_16: v_cmp_ne_u32_e32 vcc, 0, v15 ; 7D9A1E80 s_and_b64 vcc, exec, vcc ; 86EA6A7E s_cbranch_vccz BB0_1 ; BF860000 s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dwordx2 s[0:1], s[4:7], 0x108 ; C0260002 00000108 s_waitcnt lgkmcnt(0) ; BF8C007F v_cmp_gt_u32_e32 vcc, s0, v0 ; 7D980000 v_cmp_gt_u32_e64 s[0:1], s1, v1 ; D0CC0000 00020201 s_and_b64 s[0:1], s[0:1], vcc ; 86806A00 s_and_saveexec_b64 s[4:5], s[0:1] ; BE842000 BB0_18: s_load_dwordx8 s[0:7], s[2:3], 0x60 ; C00E0001 00000060 s_waitcnt lgkmcnt(0) ; BF8C007F image_store v[2:5], v[0:1], s[0:7] dmask:0xf unorm ; F0201F00 00000200 BB0_19: s_endpgm ; BF810000 Compute Shader: *** SHADER STATS *** SGPRS: 32 VGPRS: 32 Spilled SGPRs: 0 Spilled VGPRs: 0 PrivMem VGPRS: 0 Code Size: 688 bytes LDS: 0 blocks Scratch: 0 bytes per wave Max Waves: 8 ******************** sh: umr: Kommando nicht gefunden. The number of active waves = 0 List of descriptors: ** descriptor set (0) ** va: 0x3037047e0 size: 160 mapped_ptr: [0x0] = 0x01df1300 [0x1] = 0x00000003 [0x2] = 0x00001000 [0x3] = 0x00027fac [0x4] = 0x00000000 [0x5] = 0x00000000 [0x6] = 0x00000000 [0x7] = 0x00000000 [0x8] = 0x03008bdd [0x9] = 0x1cc00000 [0xa] = 0x4010c077 [0xb] = 0x90d00fac [0xc] = 0x000ee000 [0xd] = 0x00000000 [0xe] = 0x00000000 [0xf] = 0x00000000 [0x10] = 0x00000000 [0x11] = 0x00000000 [0x12] = 0x00000000 [0x13] = 0x00000000 [0x14] = 0x00000000 [0x15] = 0x00000000 [0x16] = 0x00000000 [0x17] = 0x00000000 [0x18] = 0x03008ceb [0x19] = 0x1cc00000 [0x1a] = 0x4010c077 [0x1b] = 0x90d00fac [0x1c] = 0x000ee000 [0x1d] = 0x00000000 [0x1e] = 0x00000000 [0x1f] = 0x00000000 [0x20] = 0x00000000 [0x21] = 0x00000000 [0x22] = 0x00000000 [0x23] = 0x00000000 [0x24] = 0x00000000 [0x25] = 0x00000000 [0x26] = 0x00000000 [0x27] = 0x00000000 *** layout *** binding_count: 3 size: 160 shader_stages: 20 dynamic_shader_stages: 0 buffer_count: 3 dynamic_offset_count: 0 **** binding layout (0) **** type: UNIFORM_BUFFER array_size: 1 offset: 0 buffer_offset: 0 dynamic_offset_offset: 0 dynamic_offset_count: 0 size: 16 immutable_samplers_offset: 0 immutable_samplers_equal: 0  Buffer: SQ_BUF_RSRC_WORD0 <- 0x01df1300 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 3 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 4096 (0x00001000) SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_Y DST_SEL_Z = SQ_SEL_Z DST_SEL_W = SQ_SEL_W NUM_FORMAT = BUF_NUM_FORMAT_FLOAT DATA_FORMAT = BUF_DATA_FORMAT_32 ELEMENT_SIZE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 ATC = 0 HASH_ENABLE = 0 HEAP = 0 MTYPE = 0 TYPE = SQ_RSRC_BUF **** binding layout (1) **** type: SAMPLED_IMAGE array_size: 1 offset: 32 buffer_offset: 1 dynamic_offset_offset: 0 dynamic_offset_count: 0 size: 64 immutable_samplers_offset: 0 immutable_samplers_equal: 0  Image: SQ_IMG_RSRC_WORD0 <- 0x03008bdd SQ_IMG_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 MIN_LOD = 0 DATA_FORMAT_GFX6 = IMG_DATA_FORMAT_16_16_16_16 NUM_FORMAT_GFX6 = IMG_NUM_FORMAT_FLOAT MTYPE = 0 SQ_IMG_RSRC_WORD2 <- WIDTH = 119 (0x077) HEIGHT = 67 (0x043) PERF_MOD = 4 INTERLACED = 0 SQ_IMG_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_Y DST_SEL_Z = SQ_SEL_Z DST_SEL_W = SQ_SEL_W BASE_LEVEL = 0 LAST_LEVEL = 0 TILING_INDEX = 13 (0xd) POW2_PAD = 0 MTYPE = 0 ATC = 0 TYPE = SQ_RSRC_IMG_2D SQ_IMG_RSRC_WORD4 <- DEPTH = 0 PITCH_GFX6 = 119 (0x077) SQ_IMG_RSRC_WORD5 <- BASE_ARRAY = 0 LAST_ARRAY = 0 SQ_IMG_RSRC_WORD6 <- MIN_LOD_WARN = 0 COUNTER_BANK_ID = 0 LOD_HDW_CNT_EN = 0 COMPRESSION_EN = 0 ALPHA_IS_ON_MSB = 0 COLOR_TRANSFORM = 0 LOST_ALPHA_BITS = 0 LOST_COLOR_BITS = 0 SQ_IMG_RSRC_WORD7 <- 0  FMASK: SQ_IMG_RSRC_WORD0 <- 0 SQ_IMG_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 MIN_LOD = 0 DATA_FORMAT_GFX6 = IMG_DATA_FORMAT_INVALID NUM_FORMAT_GFX6 = IMG_NUM_FORMAT_UNORM MTYPE = 0 SQ_IMG_RSRC_WORD2 <- WIDTH = 0 HEIGHT = 0 PERF_MOD = 0 INTERLACED = 0 SQ_IMG_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 BASE_LEVEL = 0 LAST_LEVEL = 0 TILING_INDEX = 0 POW2_PAD = 0 MTYPE = 0 ATC = 0 TYPE = SQ_RSRC_IMG_RSVD_0 SQ_IMG_RSRC_WORD4 <- DEPTH = 0 PITCH_GFX6 = 0 SQ_IMG_RSRC_WORD5 <- BASE_ARRAY = 0 LAST_ARRAY = 0 SQ_IMG_RSRC_WORD6 <- MIN_LOD_WARN = 0 COUNTER_BANK_ID = 0 LOD_HDW_CNT_EN = 0 COMPRESSION_EN = 0 ALPHA_IS_ON_MSB = 0 COLOR_TRANSFORM = 0 LOST_ALPHA_BITS = 0 LOST_COLOR_BITS = 0 SQ_IMG_RSRC_WORD7 <- 0 **** binding layout (2) **** type: STORAGE_IMAGE array_size: 1 offset: 96 buffer_offset: 2 dynamic_offset_offset: 0 dynamic_offset_count: 0 size: 64 immutable_samplers_offset: 0 immutable_samplers_equal: 0  Image: SQ_IMG_RSRC_WORD0 <- 0x03008ceb SQ_IMG_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 MIN_LOD = 0 DATA_FORMAT_GFX6 = IMG_DATA_FORMAT_16_16_16_16 NUM_FORMAT_GFX6 = IMG_NUM_FORMAT_FLOAT MTYPE = 0 SQ_IMG_RSRC_WORD2 <- WIDTH = 119 (0x077) HEIGHT = 67 (0x043) PERF_MOD = 4 INTERLACED = 0 SQ_IMG_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_Y DST_SEL_Z = SQ_SEL_Z DST_SEL_W = SQ_SEL_W BASE_LEVEL = 0 LAST_LEVEL = 0 TILING_INDEX = 13 (0xd) POW2_PAD = 0 MTYPE = 0 ATC = 0 TYPE = SQ_RSRC_IMG_2D SQ_IMG_RSRC_WORD4 <- DEPTH = 0 PITCH_GFX6 = 119 (0x077) SQ_IMG_RSRC_WORD5 <- BASE_ARRAY = 0 LAST_ARRAY = 0 SQ_IMG_RSRC_WORD6 <- MIN_LOD_WARN = 0 COUNTER_BANK_ID = 0 LOD_HDW_CNT_EN = 0 COMPRESSION_EN = 0 ALPHA_IS_ON_MSB = 0 COLOR_TRANSFORM = 0 LOST_ALPHA_BITS = 0 LOST_COLOR_BITS = 0 SQ_IMG_RSRC_WORD7 <- 0  FMASK: SQ_IMG_RSRC_WORD0 <- 0 SQ_IMG_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 MIN_LOD = 0 DATA_FORMAT_GFX6 = IMG_DATA_FORMAT_INVALID NUM_FORMAT_GFX6 = IMG_NUM_FORMAT_UNORM MTYPE = 0 SQ_IMG_RSRC_WORD2 <- WIDTH = 0 HEIGHT = 0 PERF_MOD = 0 INTERLACED = 0 SQ_IMG_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 BASE_LEVEL = 0 LAST_LEVEL = 0 TILING_INDEX = 0 POW2_PAD = 0 MTYPE = 0 ATC = 0 TYPE = SQ_RSRC_IMG_RSVD_0 SQ_IMG_RSRC_WORD4 <- DEPTH = 0 PITCH_GFX6 = 0 SQ_IMG_RSRC_WORD5 <- BASE_ARRAY = 0 LAST_ARRAY = 0 SQ_IMG_RSRC_WORD6 <- MIN_LOD_WARN = 0 COUNTER_BANK_ID = 0 LOD_HDW_CNT_EN = 0 COMPRESSION_EN = 0 ALPHA_IS_ON_MSB = 0 COLOR_TRANSFORM = 0 LOST_ALPHA_BITS = 0 LOST_COLOR_BITS = 0 SQ_IMG_RSRC_WORD7 <- 0 wine: Assertion failed at address 0x7fa8d53ef860 (thread 004f), starting debugger...