[0531/161751:ERROR:network_change_notifier_win.cc(170)] WSALookupServiceBegin failed with: 8 libGL: pci id for fd 13: 1002:687f, driver radeonsi libGL: OpenDriver: trying /opt/mesa-gitlast-llvm7/x86_64/gallium/tls/radeonsi_dri.so libGL: OpenDriver: trying /opt/mesa-gitlast-llvm7/x86_64/gallium/radeonsi_dri.so ATTENTION: default value of option mesa_glthread overridden by environment. ATTENTION: option value of option mesa_glthread ignored. /usr/share/libdrm/amdgpu.ids version: 1.0.0 libGL: Using DRI3 for screen 0 006b:trace:fps:wglSwapBuffers @ approx 0.00fps, total 0.00fps libGL: pci id for fd 13: 1002:687f, driver radeonsi libGL: OpenDriver: trying /opt/mesa-gitlast-llvm7/x86_64/gallium/tls/radeonsi_dri.so libGL: OpenDriver: trying /opt/mesa-gitlast-llvm7/x86_64/gallium/radeonsi_dri.so libGL: dlopen /opt/mesa-gitlast-llvm7/x86_64/gallium/radeonsi_dri.so failed (/opt/mesa-gitlast-llvm7/x86_64/gallium/radeonsi_dri.so: wrong ELF class: ELFCLASS64) libGL: OpenDriver: trying /opt/mesa-gitlast-llvm6/x86/gallium/tls/radeonsi_dri.so libGL: OpenDriver: trying /opt/mesa-gitlast-llvm6/x86/gallium/radeonsi_dri.so ATTENTION: default value of option mesa_glthread overridden by environment. ATTENTION: option value of option mesa_glthread ignored. /usr/share/libdrm/amdgpu.ids version: 1.0.0 libGL: Using DRI3 for screen 0 006f:trace:fps:wglSwapBuffers @ approx 0.00fps, total 0.00fps libGL: pci id for fd 192: 1002:687f, driver radeonsi libGL: OpenDriver: trying /opt/mesa-gitlast-llvm7/x86_64/gallium/tls/radeonsi_dri.so libGL: OpenDriver: trying /opt/mesa-gitlast-llvm7/x86_64/gallium/radeonsi_dri.so libGL: dlopen /opt/mesa-gitlast-llvm7/x86_64/gallium/radeonsi_dri.so failed (/opt/mesa-gitlast-llvm7/x86_64/gallium/radeonsi_dri.so: wrong ELF class: ELFCLASS64) libGL: OpenDriver: trying /opt/mesa-gitlast-llvm6/x86/gallium/tls/radeonsi_dri.so libGL: OpenDriver: trying /opt/mesa-gitlast-llvm6/x86/gallium/radeonsi_dri.so ATTENTION: default value of option mesa_glthread overridden by environment. ATTENTION: option value of option mesa_glthread ignored. /usr/share/libdrm/amdgpu.ids version: 1.0.0 libGL: Using DRI3 for screen 0 info: Enabled instance extensions: info: VK_KHR_win32_surface info: VK_KHR_surface /usr/share/libdrm/amdgpu.ids version: 1.0.0 info: AMD RADV VEGA10 (LLVM 7.0.0): info: Driver: 18.1.99 info: Vulkan: 1.1.70 info: Memory Heap[0]: info: Size: 7911 MiB info: Flags: 0x1 info: Memory Type[0]: Property Flags = 0x1 info: Memory Heap[1]: info: Size: 235 MiB info: Flags: 0x1 info: Memory Type[2]: Property Flags = 0x7 info: Memory Heap[2]: info: Size: 8171 MiB info: Flags: 0x0 info: Memory Type[1]: Property Flags = 0x6 info: Memory Type[3]: Property Flags = 0xe warn: DXGI: VK_FORMAT_D24_UNORM_S8_UINT -> VK_FORMAT_D32_SFLOAT_S8_UINT info: D3D11CoreCreateDevice: Probing D3D_FEATURE_LEVEL_11_0 info: D3D11CoreCreateDevice: Using feature level D3D_FEATURE_LEVEL_11_0 warn: Vulkan extension VK_EXT_vertex_attribute_divisor not supported warn: Vulkan extension VK_KHR_maintenance2 not supported info: Enabled device extensions: info: VK_KHR_swapchain info: VK_KHR_shader_draw_parameters info: VK_KHR_descriptor_update_template info: VK_KHR_maintenance1 info: VK_KHR_sampler_mirror_clamp_to_edge warn: DXGI: MakeWindowAssociation: Ignoring flags info: DxgiVkPresenter: Recreating swap chain: Format: VK_FORMAT_B8G8R8A8_UNORM Present mode: VK_PRESENT_MODE_FIFO_KHR Buffer size: 1600x900 shader: MESA_SHADER_VERTEX inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_out INTERP_MODE_NONE float o0 (VARYING_SLOT_VAR0.x, 0, 0) decl_function main returning void impl main { decl_var INTERP_MODE_NONE vec4[32] shader_in decl_var INTERP_MODE_NONE vec4 out@o0-temp block block_0: /* preds: */ vec1 32 ssa_0 = intrinsic load_vertex_id_zero_base () () () intrinsic store_var (ssa_0) (o0) (1) /* wrmask=x */ /* succs: block_0 */ block block_0: } shader: MESA_SHADER_TESS_CTRL inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE usamplerBuffer t0 (0, 0, 2) decl_var shader_in INTERP_MODE_NONE float[3] v0 (31.x, 0, 0) decl_var patch shader_out INTERP_MODE_NONE float[4] bTessLevelOuter (26.x, 0, 0) compact decl_var patch shader_out INTERP_MODE_NONE float[2] bTessLevelInner (27.x, 0, 0) compact decl_var shader_out INTERP_MODE_NONE float[3] oVertex (31.y, 0, 0) decl_var shader_out INTERP_MODE_NONE float[3] oVertex@0 (31.z, 0, 0) decl_var shader_out INTERP_MODE_NONE float[3] oVertex@1 (31.w, 0, 0) decl_var shader_out INTERP_MODE_NONE float[3] oVertex@2 (31.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float[3] oVertex@3 (32.y, 0, 0) decl_var shader_out INTERP_MODE_NONE float[3] oVertex@4 (32.z, 0, 0) decl_var shader_out INTERP_MODE_NONE float[3] oVertex@5 (32.w, 0, 0) decl_var shader_out INTERP_MODE_NONE float[3] oVertex@6 (32.x, 0, 0) decl_var patch shader_out INTERP_MODE_NONE vec4 oPatch (63, 0, 0) decl_var patch shader_out INTERP_MODE_NONE vec4 oPatch@7 (64, 0, 0) decl_var patch shader_out INTERP_MODE_NONE vec4 oPatch@8 (65, 0, 0) decl_var patch shader_out INTERP_MODE_NONE vec4 oPatch@9 (66, 0, 0) decl_function main returning void impl main { decl_var INTERP_MODE_NONE vec4 r0 decl_var INTERP_MODE_NONE vec4[3][32] shader_in decl_var INTERP_MODE_NONE vec4 r2 decl_var INTERP_MODE_NONE vec4 r1 block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x42800000 /* 64.000000 */) vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_2 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_4 = intrinsic load_var () (v0[0]) () vec1 32 ssa_5 = intrinsic load_var () (v0[1]) () vec1 32 ssa_6 = intrinsic load_var () (v0[2]) () vec1 32 ssa_7 = load_const (0x3f800000 /* 1.000000 */) vec3 32 ssa_8 = load_const (0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */) vec1 32 ssa_9 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = intrinsic load_invocation_id () () () vec1 32 ssa_12 = ilt ssa_11, ssa_3 vec1 32 ssa_13 = ilt ssa_11, ssa_2 vec1 32 ssa_14 = bcsel ssa_13, ssa_5, ssa_6 vec1 32 ssa_15 = bcsel ssa_12, ssa_4, ssa_14 vec1 32 ssa_182 = intrinsic load_var () (oVertex[ssa_11]) () vec1 32 ssa_183 = intrinsic load_var () (oVertex@0[ssa_11]) () vec1 32 ssa_184 = intrinsic load_var () (oVertex@1[ssa_11]) () intrinsic store_var (ssa_15) (oVertex@2[ssa_11]) (1) /* wrmask=x */ intrinsic store_var (ssa_182) (oVertex[ssa_11]) (1) /* wrmask=x */ intrinsic store_var (ssa_183) (oVertex@0[ssa_11]) (1) /* wrmask=x */ intrinsic store_var (ssa_184) (oVertex@1[ssa_11]) (1) /* wrmask=x */ vec1 32 ssa_19 = intrinsic vulkan_resource_index (ssa_1) () (0, 1) /* desc-set=0 */ /* binding=1 */ vec1 32 ssa_20 = load_const (0x000000d0 /* 0.000000 */) vec4 32 ssa_21 = intrinsic load_ubo (ssa_19, ssa_20) () () vec1 32 ssa_22 = imul ssa_15, ssa_21.x vec1 32 ssa_23 = iadd ssa_22, ssa_21.z vec1 32 ssa_24 = idiv ssa_23, ssa_9 vec4 32 ssa_25 = txf ssa_24 (coord), ssa_1 (lod), t0 (texture) vec1 32 ssa_26 = iadd ssa_24, ssa_3 vec4 32 ssa_27 = txf ssa_26 (coord), ssa_1 (lod), t0 (texture) vec1 32 ssa_28 = iadd ssa_24, ssa_2 vec4 32 ssa_29 = txf ssa_28 (coord), ssa_1 (lod), t0 (texture) vec1 32 ssa_30 = iadd ssa_11, ssa_3 vec1 32 ssa_31 = umod ssa_30, ssa_10 vec1 32 ssa_32 = ilt ssa_31, ssa_3 vec1 32 ssa_33 = ilt ssa_31, ssa_2 vec1 32 ssa_34 = bcsel ssa_33, ssa_5, ssa_6 vec1 32 ssa_35 = bcsel ssa_32, ssa_4, ssa_34 vec1 32 ssa_36 = imul ssa_35, ssa_21.x vec1 32 ssa_37 = iadd ssa_36, ssa_21.z vec1 32 ssa_38 = idiv ssa_37, ssa_9 vec4 32 ssa_39 = txf ssa_38 (coord), ssa_1 (lod), t0 (texture) vec1 32 ssa_40 = iadd ssa_38, ssa_3 vec4 32 ssa_41 = txf ssa_40 (coord), ssa_1 (lod), t0 (texture) vec1 32 ssa_42 = iadd ssa_38, ssa_2 vec4 32 ssa_43 = txf ssa_42 (coord), ssa_1 (lod), t0 (texture) vec1 32 ssa_44 = fadd ssa_25.x, ssa_39.x vec1 32 ssa_45 = fadd ssa_27.x, ssa_41.x vec1 32 ssa_46 = fadd ssa_29.x, ssa_43.x vec1 32 ssa_47 = fneg ssa_39.x vec1 32 ssa_48 = fneg ssa_41.x vec1 32 ssa_49 = fneg ssa_43.x vec1 32 ssa_50 = fadd ssa_25.x, ssa_47 vec1 32 ssa_51 = fadd ssa_27.x, ssa_48 vec1 32 ssa_52 = fadd ssa_29.x, ssa_49 vec1 32 ssa_53 = fmul ssa_50, ssa_50 vec1 32 ssa_54 = fmul ssa_51, ssa_51 vec1 32 ssa_55 = fadd ssa_53, ssa_54 vec1 32 ssa_56 = fmul ssa_52, ssa_52 vec1 32 ssa_57 = fadd ssa_55, ssa_56 vec1 32 ssa_58 = fsqrt ssa_57 vec1 32 ssa_59 = fmul ssa_44, ssa_8.x vec1 32 ssa_60 = fmul ssa_45, ssa_8.y vec1 32 ssa_61 = fmul ssa_46, ssa_8.z vec1 32 ssa_62 = load_const (0x00000020 /* 0.000000 */) vec4 32 ssa_63 = intrinsic load_ubo (ssa_19, ssa_62) () () vec1 32 ssa_64 = fmul ssa_60, ssa_63.x vec1 32 ssa_65 = fmul ssa_60, ssa_63.y vec1 32 ssa_66 = fmul ssa_60, ssa_63.z vec1 32 ssa_67 = load_const (0x00000010 /* 0.000000 */) vec4 32 ssa_68 = intrinsic load_ubo (ssa_19, ssa_67) () () vec1 32 ssa_69 = fmul ssa_68.x, ssa_59 vec1 32 ssa_70 = fadd ssa_69, ssa_64 vec1 32 ssa_71 = fmul ssa_68.y, ssa_59 vec1 32 ssa_72 = fadd ssa_71, ssa_65 vec1 32 ssa_73 = fmul ssa_68.z, ssa_59 vec1 32 ssa_74 = fadd ssa_73, ssa_66 vec1 32 ssa_75 = load_const (0x00000030 /* 0.000000 */) vec4 32 ssa_76 = intrinsic load_ubo (ssa_19, ssa_75) () () vec1 32 ssa_77 = fmul ssa_76.x, ssa_61 vec1 32 ssa_78 = fadd ssa_77, ssa_70 vec1 32 ssa_79 = fmul ssa_76.y, ssa_61 vec1 32 ssa_80 = fadd ssa_79, ssa_72 vec1 32 ssa_81 = fmul ssa_76.z, ssa_61 vec1 32 ssa_82 = fadd ssa_81, ssa_74 vec1 32 ssa_83 = load_const (0x00000040 /* 0.000000 */) vec4 32 ssa_84 = intrinsic load_ubo (ssa_19, ssa_83) () () vec1 32 ssa_85 = fadd ssa_78, ssa_84.x vec1 32 ssa_86 = fadd ssa_80, ssa_84.y vec1 32 ssa_87 = fadd ssa_82, ssa_84.z vec1 32 ssa_88 = intrinsic vulkan_resource_index (ssa_1) () (0, 0) /* desc-set=0 */ /* binding=0 */ vec1 32 ssa_89 = load_const (0x000006c0 /* 0.000000 */) vec4 32 ssa_90 = intrinsic load_ubo (ssa_88, ssa_89) () () vec1 32 ssa_91 = fmul ssa_86, ssa_90.w vec1 32 ssa_92 = load_const (0x000006b0 /* 0.000000 */) vec4 32 ssa_93 = intrinsic load_ubo (ssa_88, ssa_92) () () vec1 32 ssa_94 = fmul ssa_93.w, ssa_85 vec1 32 ssa_95 = fadd ssa_94, ssa_91 vec1 32 ssa_96 = load_const (0x000006d0 /* 0.000000 */) vec4 32 ssa_97 = intrinsic load_ubo (ssa_88, ssa_96) () () vec1 32 ssa_98 = fmul ssa_97.w, ssa_87 vec1 32 ssa_99 = fadd ssa_98, ssa_95 vec1 32 ssa_100 = load_const (0x000006f0 /* 0.000000 */) vec4 32 ssa_101 = intrinsic load_ubo (ssa_88, ssa_100) () () vec1 32 ssa_102 = fneg ssa_101.x vec1 32 ssa_103 = fneg ssa_101.y vec1 32 ssa_104 = fneg ssa_101.z vec1 32 ssa_105 = fadd ssa_85, ssa_102 vec1 32 ssa_106 = fadd ssa_86, ssa_103 vec1 32 ssa_107 = fadd ssa_87, ssa_104 vec1 32 ssa_108 = load_const (0x000006e0 /* 0.000000 */) vec4 32 ssa_109 = intrinsic load_ubo (ssa_88, ssa_108) () () vec1 32 ssa_110 = fadd ssa_99, ssa_109.w vec1 32 ssa_111 = load_const (0x00000700 /* 0.000000 */) vec4 32 ssa_112 = intrinsic load_ubo (ssa_88, ssa_111) () () vec1 32 ssa_113 = fmul ssa_58, ssa_112.w vec1 32 ssa_114 = load_const (0x000006a0 /* 0.000000 */) vec4 32 ssa_115 = intrinsic load_ubo (ssa_88, ssa_114) () () vec1 32 ssa_116 = frcp ssa_115.y vec1 32 ssa_117 = fmul ssa_58, ssa_116 vec1 32 ssa_118 = frcp ssa_110 vec1 32 ssa_119 = fmul ssa_113, ssa_118 vec1 32 ssa_120 = fabs ssa_119 vec1 32 ssa_121 = fmul ssa_120, ssa_115.x vec1 32 ssa_122 = fmul ssa_105, ssa_105 vec1 32 ssa_123 = fmul ssa_106, ssa_106 vec1 32 ssa_124 = fadd ssa_122, ssa_123 vec1 32 ssa_125 = fmul ssa_107, ssa_107 vec1 32 ssa_126 = fadd ssa_124, ssa_125 vec1 32 ssa_127 = fsqrt ssa_126 vec1 32 ssa_128 = frsq ssa_126 vec1 32 ssa_129 = fmul ssa_105, ssa_128 vec1 32 ssa_130 = fmul ssa_106, ssa_128 vec1 32 ssa_131 = fmul ssa_107, ssa_128 vec1 32 ssa_132 = fmul ssa_112.x, ssa_129 vec1 32 ssa_133 = fmul ssa_112.y, ssa_130 vec1 32 ssa_134 = fadd ssa_132, ssa_133 vec1 32 ssa_135 = fmul ssa_112.z, ssa_131 vec1 32 ssa_136 = fadd ssa_134, ssa_135 vec1 32 ssa_137 = fneg ssa_115.z vec1 32 ssa_138 = fadd ssa_127, ssa_137 vec1 32 ssa_139 = fadd ssa_137, ssa_115.w vec1 32 ssa_140 = frcp ssa_139 vec1 32 ssa_141 = fmul ssa_140, ssa_138 vec1 32 ssa_142 = fmax ssa_141, ssa_1 vec1 32 ssa_143 = fmin ssa_142, ssa_7 vec1 32 ssa_144 = fneg ssa_143 vec1 32 ssa_145 = fadd ssa_144, ssa_7 vec1 32 ssa_146 = fmul ssa_145, ssa_121 vec1 32 ssa_147 = fmul ssa_136, ssa_146 vec1 32 ssa_148 = fmax ssa_147, ssa_7 vec1 32 ssa_149 = fmin ssa_117, ssa_148 vec1 32 ssa_185 = intrinsic load_var () (oVertex@3[ssa_11]) () vec1 32 ssa_186 = intrinsic load_var () (oVertex@4[ssa_11]) () vec1 32 ssa_187 = intrinsic load_var () (oVertex@5[ssa_11]) () intrinsic store_var (ssa_149) (oVertex@6[ssa_11]) (1) /* wrmask=x */ intrinsic store_var (ssa_185) (oVertex@3[ssa_11]) (1) /* wrmask=x */ intrinsic store_var (ssa_186) (oVertex@4[ssa_11]) (1) /* wrmask=x */ intrinsic store_var (ssa_187) (oVertex@5[ssa_11]) (1) /* wrmask=x */ intrinsic barrier () () () vec1 32 ssa_153 = ult ssa_11, ssa_3 /* succs: block_1 block_2 */ if ssa_153 { block block_1: /* preds: block_0 */ vec1 32 ssa_188 = intrinsic load_var () (oVertex@6[2]) () vec4 32 ssa_189 = intrinsic load_var () (oPatch) () vec4 32 ssa_156 = vec4 ssa_188, ssa_189.y, ssa_189.z, ssa_189.w intrinsic store_var (ssa_156) (oPatch) (15) /* wrmask=xyzw */ vec1 32 ssa_190 = intrinsic load_var () (oVertex@6[0]) () vec4 32 ssa_191 = intrinsic load_var () (oPatch@7) () vec4 32 ssa_159 = vec4 ssa_190, ssa_191.y, ssa_191.z, ssa_191.w intrinsic store_var (ssa_159) (oPatch@7) (15) /* wrmask=xyzw */ vec1 32 ssa_192 = intrinsic load_var () (oVertex@6[1]) () vec4 32 ssa_193 = intrinsic load_var () (oPatch@8) () vec4 32 ssa_162 = vec4 ssa_192, ssa_193.y, ssa_193.z, ssa_193.w intrinsic store_var (ssa_162) (oPatch@8) (15) /* wrmask=xyzw */ vec1 32 ssa_194 = intrinsic load_var () (oVertex@6[0]) () vec1 32 ssa_195 = intrinsic load_var () (oVertex@6[2]) () vec1 32 ssa_165 = fmax ssa_194, ssa_195 vec1 32 ssa_196 = intrinsic load_var () (oVertex@6[1]) () vec1 32 ssa_167 = fmax ssa_165, ssa_196 vec4 32 ssa_197 = intrinsic load_var () (oPatch@9) () vec4 32 ssa_169 = vec4 ssa_167, ssa_197.y, ssa_197.z, ssa_197.w intrinsic store_var (ssa_169) (oPatch@9) (15) /* wrmask=xyzw */ vec4 32 ssa_198 = intrinsic load_var () (oPatch) () vec1 32 ssa_171 = fmax ssa_198.x, ssa_1 vec1 32 ssa_172 = fmin ssa_171, ssa_0 intrinsic store_var (ssa_172) (bTessLevelOuter[0]) (1) /* wrmask=x */ vec4 32 ssa_199 = intrinsic load_var () (oPatch@7) () vec1 32 ssa_174 = fmax ssa_199.x, ssa_1 vec1 32 ssa_175 = fmin ssa_174, ssa_0 intrinsic store_var (ssa_175) (bTessLevelOuter[1]) (1) /* wrmask=x */ vec4 32 ssa_200 = intrinsic load_var () (oPatch@8) () vec1 32 ssa_177 = fmax ssa_200.x, ssa_1 vec1 32 ssa_178 = fmin ssa_177, ssa_0 intrinsic store_var (ssa_178) (bTessLevelOuter[2]) (1) /* wrmask=x */ vec4 32 ssa_201 = intrinsic load_var () (oPatch@9) () vec1 32 ssa_180 = fmax ssa_201.x, ssa_1 vec1 32 ssa_181 = fmin ssa_180, ssa_0 intrinsic store_var (ssa_181) (bTessLevelInner[0]) (1) /* wrmask=x */ /* succs: block_3 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 */ } block block_3: /* preds: block_1 block_2 */ /* succs: block_0 */ block block_0: } shader: MESA_SHADER_TESS_EVAL inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE sampler s0 (0, 0, 6) decl_var uniform INTERP_MODE_NONE sampler2D t0 (0, 0, 7) decl_var uniform INTERP_MODE_NONE usamplerBuffer t1 (0, 0, 8) decl_var shader_in INTERP_MODE_NONE float[3] vVertex (31.x, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 ds_vertex_out.0 (0, 0, 0) decl_var shader_out INTERP_MODE_NONE float o1 (32.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float o1@0 (32.y, 0, 0) decl_var shader_out INTERP_MODE_NONE float o1@1 (32.z, 0, 0) decl_var shader_out INTERP_MODE_NONE float o1@2 (32.w, 0, 0) decl_var shader_out INTERP_MODE_NONE float o2 (33.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float o2@3 (33.w, 0, 0) decl_var shader_out INTERP_MODE_NONE float o3 (34.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float o3@4 (34.y, 0, 0) decl_var shader_out INTERP_MODE_NONE float o3@5 (34.z, 0, 0) decl_var shader_out INTERP_MODE_NONE float o3@6 (34.w, 0, 0) decl_var shader_out INTERP_MODE_NONE float o4 (35.x, 0, 0) decl_var shader_out INTERP_MODE_NONE float o4@7 (35.y, 0, 0) decl_var shader_out INTERP_MODE_NONE float o4@8 (35.z, 0, 0) decl_var shader_out INTERP_MODE_NONE float o4@9 (35.w, 0, 0) decl_function main returning void impl main { decl_var INTERP_MODE_NONE vec4 r4 decl_var INTERP_MODE_NONE vec4 out@o5-temp decl_var INTERP_MODE_NONE vec4 out@o1-temp decl_var INTERP_MODE_NONE vec4 r5 decl_var INTERP_MODE_NONE vec4 r3 decl_var INTERP_MODE_NONE vec4 out@o2-temp decl_var INTERP_MODE_NONE vec4 r2 decl_var INTERP_MODE_NONE vec4 out@o4-temp decl_var INTERP_MODE_NONE vec4 r0 decl_var INTERP_MODE_NONE vec4 out@ds_vertex_out.0-temp decl_var INTERP_MODE_NONE vec4 out@o3-temp decl_var INTERP_MODE_NONE vec4 out@o0-temp decl_var INTERP_MODE_NONE vec4 r1 decl_var INTERP_MODE_NONE float o2@10 decl_var INTERP_MODE_NONE float o5 decl_var INTERP_MODE_NONE float o2@11 decl_var INTERP_MODE_NONE float o5@12 decl_var INTERP_MODE_NONE float o0 decl_var INTERP_MODE_NONE float o0@13 decl_var INTERP_MODE_NONE float o5@14 decl_var INTERP_MODE_NONE float o0@15 decl_var INTERP_MODE_NONE float o0@16 decl_var INTERP_MODE_NONE float o5@17 block block_0: /* preds: */ vec4 32 ssa_0 = load_const (0xbf800000 /* -1.000000 */, 0xbf800000 /* -1.000000 */, 0xbf800000 /* -1.000000 */, 0xbf800000 /* -1.000000 */) vec4 32 ssa_1 = load_const (0x3c008081 /* 0.007843 */, 0x3c008081 /* 0.007843 */, 0x3c008081 /* 0.007843 */, 0x3c008081 /* 0.007843 */) vec1 32 ssa_2 = load_const (0x00000018 /* 0.000000 */) vec1 32 ssa_3 = load_const (0x000000ff /* 0.000000 */) vec2 32 ssa_4 = load_const (0x00000010 /* 0.000000 */, 0x00000008 /* 0.000000 */) vec2 32 ssa_5 = load_const (0x00000008 /* 0.000000 */, 0x00000008 /* 0.000000 */) vec2 32 ssa_6 = load_const (0x00000010 /* 0.000000 */, 0x00000010 /* 0.000000 */) vec2 32 ssa_7 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_8 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_11 = load_const (0x00000010 /* 0.000000 */) vec1 32 ssa_12 = load_const (0x3f800000 /* 1.000000 */) vec2 32 ssa_13 = load_const (0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */) vec1 32 ssa_14 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_489 = intrinsic load_var () (vVertex[1]) () vec1 32 ssa_16 = intrinsic vulkan_resource_index (ssa_8) () (0, 4) /* desc-set=0 */ /* binding=4 */ vec1 32 ssa_17 = load_const (0x000000d0 /* 0.000000 */) vec4 32 ssa_18 = intrinsic load_ubo (ssa_16, ssa_17) () () vec1 32 ssa_19 = imul ssa_489, ssa_18.x vec1 32 ssa_20 = iadd ssa_19, ssa_18.z vec1 32 ssa_21 = idiv ssa_20, ssa_9 vec4 32 ssa_22 = txf ssa_21 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_23 = iadd ssa_21, ssa_10 vec4 32 ssa_24 = txf ssa_23 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_25 = iadd ssa_21, ssa_14 vec4 32 ssa_26 = txf ssa_25 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_490 = intrinsic load_var () (vVertex[0]) () vec1 32 ssa_28 = imul ssa_490, ssa_18.x vec1 32 ssa_29 = iadd ssa_28, ssa_18.z vec1 32 ssa_30 = idiv ssa_29, ssa_9 vec4 32 ssa_31 = txf ssa_30 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_32 = iadd ssa_30, ssa_10 vec4 32 ssa_33 = txf ssa_32 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_34 = iadd ssa_30, ssa_14 vec4 32 ssa_35 = txf ssa_34 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_36 = fneg ssa_31.x vec1 32 ssa_37 = fneg ssa_33.x vec1 32 ssa_38 = fneg ssa_35.x vec1 32 ssa_39 = fadd ssa_22.x, ssa_36 vec1 32 ssa_40 = fadd ssa_24.x, ssa_37 vec1 32 ssa_41 = fadd ssa_26.x, ssa_38 vec3 32 ssa_42 = intrinsic load_tess_coord () () () vec1 32 ssa_43 = fmul ssa_42.x, ssa_39 vec1 32 ssa_44 = fadd ssa_43, ssa_31.x vec1 32 ssa_45 = fmul ssa_42.x, ssa_40 vec1 32 ssa_46 = fadd ssa_45, ssa_33.x vec1 32 ssa_47 = fmul ssa_42.x, ssa_41 vec1 32 ssa_48 = fadd ssa_47, ssa_35.x vec1 32 ssa_491 = intrinsic load_var () (vVertex[2]) () vec1 32 ssa_50 = imul ssa_491, ssa_18.x vec1 32 ssa_51 = iadd ssa_50, ssa_18.z vec1 32 ssa_52 = idiv ssa_51, ssa_9 vec4 32 ssa_53 = txf ssa_52 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_54 = iadd ssa_52, ssa_10 vec4 32 ssa_55 = txf ssa_54 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_56 = iadd ssa_52, ssa_14 vec4 32 ssa_57 = txf ssa_56 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_58 = fadd ssa_36, ssa_53.x vec1 32 ssa_59 = fadd ssa_37, ssa_55.x vec1 32 ssa_60 = fadd ssa_38, ssa_57.x vec1 32 ssa_61 = fmul ssa_42.y, ssa_58 vec1 32 ssa_62 = fadd ssa_61, ssa_44 vec1 32 ssa_63 = fmul ssa_42.y, ssa_59 vec1 32 ssa_64 = fadd ssa_63, ssa_46 vec1 32 ssa_65 = fmul ssa_42.y, ssa_60 vec1 32 ssa_66 = fadd ssa_65, ssa_48 vec1 32 ssa_67 = load_const (0x00000060 /* 0.000000 */) vec4 32 ssa_68 = intrinsic load_ubo (ssa_16, ssa_67) () () vec1 32 ssa_69 = fmul ssa_64, ssa_68.x vec1 32 ssa_70 = fmul ssa_64, ssa_68.y vec1 32 ssa_71 = fmul ssa_64, ssa_68.z vec1 32 ssa_72 = load_const (0x00000050 /* 0.000000 */) vec4 32 ssa_73 = intrinsic load_ubo (ssa_16, ssa_72) () () vec1 32 ssa_74 = fmul ssa_73.x, ssa_62 vec1 32 ssa_75 = fadd ssa_74, ssa_69 vec1 32 ssa_76 = fmul ssa_73.y, ssa_62 vec1 32 ssa_77 = fadd ssa_76, ssa_70 vec1 32 ssa_78 = fmul ssa_73.z, ssa_62 vec1 32 ssa_79 = fadd ssa_78, ssa_71 vec1 32 ssa_80 = load_const (0x00000070 /* 0.000000 */) vec4 32 ssa_81 = intrinsic load_ubo (ssa_16, ssa_80) () () vec1 32 ssa_82 = fmul ssa_81.x, ssa_66 vec1 32 ssa_83 = fadd ssa_82, ssa_75 vec1 32 ssa_84 = fmul ssa_81.y, ssa_66 vec1 32 ssa_85 = fadd ssa_84, ssa_77 vec1 32 ssa_86 = fmul ssa_81.z, ssa_66 vec1 32 ssa_87 = fadd ssa_86, ssa_79 vec1 32 ssa_88 = load_const (0x00000080 /* 0.000000 */) vec4 32 ssa_89 = intrinsic load_ubo (ssa_16, ssa_88) () () vec1 32 ssa_90 = fadd ssa_83, ssa_89.x vec1 32 ssa_91 = fadd ssa_85, ssa_89.y vec1 32 ssa_92 = fadd ssa_87, ssa_89.z vec1 32 ssa_93 = intrinsic vulkan_resource_index (ssa_8) () (0, 3) /* desc-set=0 */ /* binding=3 */ vec1 32 ssa_94 = load_const (0x00000540 /* 0.000000 */) vec4 32 ssa_95 = intrinsic load_ubo (ssa_93, ssa_94) () () vec1 32 ssa_96 = fmul ssa_91, ssa_95.x vec1 32 ssa_97 = fmul ssa_91, ssa_95.y vec1 32 ssa_98 = fmul ssa_91, ssa_95.w vec1 32 ssa_99 = load_const (0x00000530 /* 0.000000 */) vec4 32 ssa_100 = intrinsic load_ubo (ssa_93, ssa_99) () () vec1 32 ssa_101 = fmul ssa_100.x, ssa_90 vec1 32 ssa_102 = fadd ssa_101, ssa_96 vec1 32 ssa_103 = fmul ssa_100.y, ssa_90 vec1 32 ssa_104 = fadd ssa_103, ssa_97 vec1 32 ssa_105 = fmul ssa_100.w, ssa_90 vec1 32 ssa_106 = fadd ssa_105, ssa_98 vec1 32 ssa_107 = load_const (0x00000550 /* 0.000000 */) vec4 32 ssa_108 = intrinsic load_ubo (ssa_93, ssa_107) () () vec1 32 ssa_109 = fmul ssa_108.x, ssa_92 vec1 32 ssa_110 = fadd ssa_109, ssa_102 vec1 32 ssa_111 = fmul ssa_108.y, ssa_92 vec1 32 ssa_112 = fadd ssa_111, ssa_104 vec1 32 ssa_113 = fmul ssa_108.w, ssa_92 vec1 32 ssa_114 = fadd ssa_113, ssa_106 vec1 32 ssa_115 = load_const (0x00000560 /* 0.000000 */) vec4 32 ssa_116 = intrinsic load_ubo (ssa_93, ssa_115) () () vec1 32 ssa_117 = fadd ssa_110, ssa_116.x vec1 32 ssa_118 = fadd ssa_112, ssa_116.y vec1 32 ssa_119 = fadd ssa_114, ssa_116.w vec1 32 ssa_120 = frcp ssa_119 vec1 32 ssa_121 = fmul ssa_117, ssa_13.x vec1 32 ssa_122 = fmul ssa_121, ssa_120 vec1 32 ssa_123 = fadd ssa_122, ssa_13.x vec1 32 ssa_124 = fmul ssa_118, ssa_13.y vec1 32 ssa_125 = fmul ssa_124, ssa_120 vec1 32 ssa_126 = fadd ssa_125, ssa_13.y vec2 32 ssa_127 = vec2 ssa_123, ssa_126 vec4 32 ssa_128 = txl ssa_127 (coord), ssa_8 (lod), t0 (texture)s0 (sampler) vec1 32 ssa_129 = load_const (0x00000510 /* 0.000000 */) vec4 32 ssa_130 = intrinsic load_ubo (ssa_93, ssa_129) () () vec1 32 ssa_131 = fmul ssa_128.x, ssa_130.x vec1 32 ssa_132 = fmul ssa_128.x, ssa_130.y vec1 32 ssa_133 = fmul ssa_128.x, ssa_130.z vec1 32 ssa_134 = load_const (0x000004f0 /* 0.000000 */) vec4 32 ssa_135 = intrinsic load_ubo (ssa_93, ssa_134) () () vec1 32 ssa_136 = fneg ssa_135.x vec1 32 ssa_137 = fneg ssa_135.y vec1 32 ssa_138 = fneg ssa_135.z vec1 32 ssa_139 = fadd ssa_90, ssa_136 vec1 32 ssa_140 = fadd ssa_91, ssa_137 vec1 32 ssa_141 = fadd ssa_92, ssa_138 vec1 32 ssa_142 = fmul ssa_139, ssa_139 vec1 32 ssa_143 = fmul ssa_140, ssa_140 vec1 32 ssa_144 = fadd ssa_142, ssa_143 vec1 32 ssa_145 = fmul ssa_141, ssa_141 vec1 32 ssa_146 = fadd ssa_144, ssa_145 vec1 32 ssa_147 = fsqrt ssa_146 vec1 32 ssa_148 = load_const (0x000004e0 /* 0.000000 */) vec4 32 ssa_149 = intrinsic load_ubo (ssa_93, ssa_148) () () vec1 32 ssa_150 = fneg ssa_149.x vec1 32 ssa_151 = fadd ssa_147, ssa_150 vec1 32 ssa_152 = fadd ssa_150, ssa_149.y vec1 32 ssa_153 = frcp ssa_152 vec1 32 ssa_154 = fmul ssa_151, ssa_153 vec1 32 ssa_155 = fmax ssa_154, ssa_8 vec1 32 ssa_156 = fmin ssa_155, ssa_12 vec1 32 ssa_157 = fmul ssa_131, ssa_156 vec1 32 ssa_158 = fmul ssa_132, ssa_156 vec1 32 ssa_159 = fmul ssa_133, ssa_156 vec1 32 ssa_160 = fmul ssa_157, ssa_149.z vec1 32 ssa_161 = fadd ssa_160, ssa_90 vec1 32 ssa_162 = fmul ssa_158, ssa_149.z vec1 32 ssa_163 = fadd ssa_162, ssa_91 vec1 32 ssa_164 = fmul ssa_159, ssa_149.z vec1 32 ssa_165 = fadd ssa_164, ssa_92 vec1 32 ssa_166 = load_const (0x000000b0 /* 0.000000 */) vec4 32 ssa_167 = intrinsic load_ubo (ssa_93, ssa_166) () () vec1 32 ssa_168 = fmul ssa_163, ssa_167.x vec1 32 ssa_169 = fmul ssa_163, ssa_167.y vec1 32 ssa_170 = fmul ssa_163, ssa_167.z vec1 32 ssa_171 = fmul ssa_163, ssa_167.w vec1 32 ssa_172 = load_const (0x000000a0 /* 0.000000 */) vec4 32 ssa_173 = intrinsic load_ubo (ssa_93, ssa_172) () () vec1 32 ssa_174 = fmul ssa_173.x, ssa_161 vec1 32 ssa_175 = fadd ssa_174, ssa_168 vec1 32 ssa_176 = fmul ssa_173.y, ssa_161 vec1 32 ssa_177 = fadd ssa_176, ssa_169 vec1 32 ssa_178 = fmul ssa_173.z, ssa_161 vec1 32 ssa_179 = fadd ssa_178, ssa_170 vec1 32 ssa_180 = fmul ssa_173.w, ssa_161 vec1 32 ssa_181 = fadd ssa_180, ssa_171 vec1 32 ssa_182 = load_const (0x000000c0 /* 0.000000 */) vec4 32 ssa_183 = intrinsic load_ubo (ssa_93, ssa_182) () () vec1 32 ssa_184 = fmul ssa_183.x, ssa_165 vec1 32 ssa_185 = fadd ssa_184, ssa_175 vec1 32 ssa_186 = fmul ssa_183.y, ssa_165 vec1 32 ssa_187 = fadd ssa_186, ssa_177 vec1 32 ssa_188 = fmul ssa_183.z, ssa_165 vec1 32 ssa_189 = fadd ssa_188, ssa_179 vec1 32 ssa_190 = fmul ssa_183.w, ssa_165 vec1 32 ssa_191 = fadd ssa_190, ssa_181 vec4 32 ssa_192 = intrinsic load_ubo (ssa_93, ssa_17) () () vec1 32 ssa_193 = fadd ssa_185, ssa_192.x vec1 32 ssa_194 = fadd ssa_187, ssa_192.y vec1 32 ssa_195 = fadd ssa_189, ssa_192.z vec1 32 ssa_196 = fadd ssa_191, ssa_192.w vec1 32 ssa_197 = load_const (0x00000100 /* 0.000000 */) vec4 32 ssa_198 = intrinsic load_ubo (ssa_16, ssa_197) () () vec1 32 ssa_199 = iadd ssa_20, ssa_198.x vec1 32 ssa_200 = iadd ssa_20, ssa_198.y vec1 32 ssa_201 = iadd ssa_20, ssa_198.z vec1 32 ssa_202 = load_const (0x000000e0 /* 0.000000 */) vec4 32 ssa_203 = intrinsic load_ubo (ssa_16, ssa_202) () () vec1 32 ssa_204 = iadd ssa_20, ssa_203.x vec1 32 ssa_205 = idiv ssa_204, ssa_9 vec4 32 ssa_206 = txf ssa_205 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_207 = iadd ssa_199, ssa_9 vec1 32 ssa_208 = idiv ssa_207, ssa_9 vec4 32 ssa_209 = txf ssa_208 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_210 = ibitfield_extract ssa_209.x, ssa_8, ssa_11 vec1 32 ssa_211 = ishr ssa_209.x, ssa_11 vec1 32 ssa_212 = i2f32 ssa_210 vec1 32 ssa_213 = i2f32 ssa_211 vec1 32 ssa_214 = idiv ssa_199, ssa_9 vec4 32 ssa_215 = txf ssa_214 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_216 = ibitfield_extract ssa_215.x, ssa_8, ssa_11 vec1 32 ssa_217 = ishr ssa_215.x, ssa_11 vec1 32 ssa_218 = i2f32 ssa_217 vec1 32 ssa_219 = i2f32 ssa_216 vec1 32 ssa_220 = iadd ssa_29, ssa_198.x vec1 32 ssa_221 = iadd ssa_29, ssa_198.y vec1 32 ssa_222 = iadd ssa_29, ssa_198.z vec1 32 ssa_223 = iadd ssa_29, ssa_203.x vec1 32 ssa_224 = idiv ssa_223, ssa_9 vec4 32 ssa_225 = txf ssa_224 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_226 = iadd ssa_220, ssa_9 vec1 32 ssa_227 = idiv ssa_226, ssa_9 vec4 32 ssa_228 = txf ssa_227 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_229 = ibitfield_extract ssa_228.x, ssa_8, ssa_11 vec1 32 ssa_230 = ishr ssa_228.x, ssa_11 vec1 32 ssa_231 = i2f32 ssa_230 vec1 32 ssa_232 = i2f32 ssa_229 vec1 32 ssa_233 = idiv ssa_220, ssa_9 vec4 32 ssa_234 = txf ssa_233 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_235 = ibitfield_extract ssa_234.x, ssa_8, ssa_11 vec1 32 ssa_236 = ishr ssa_234.x, ssa_11 vec1 32 ssa_237 = i2f32 ssa_235 vec1 32 ssa_238 = i2f32 ssa_236 vec1 32 ssa_239 = fneg ssa_237 vec1 32 ssa_240 = fneg ssa_238 vec1 32 ssa_241 = fneg ssa_232 vec1 32 ssa_242 = fneg ssa_231 vec1 32 ssa_243 = fadd ssa_219, ssa_239 vec1 32 ssa_244 = fadd ssa_218, ssa_240 vec1 32 ssa_245 = fadd ssa_212, ssa_241 vec1 32 ssa_246 = fadd ssa_213, ssa_242 vec1 32 ssa_247 = fmul ssa_42.x, ssa_243 vec1 32 ssa_248 = fadd ssa_247, ssa_237 vec1 32 ssa_249 = fmul ssa_42.x, ssa_244 vec1 32 ssa_250 = fadd ssa_249, ssa_238 vec1 32 ssa_251 = fmul ssa_42.x, ssa_245 vec1 32 ssa_252 = fadd ssa_251, ssa_232 vec1 32 ssa_253 = fmul ssa_42.x, ssa_246 vec1 32 ssa_254 = fadd ssa_253, ssa_231 vec1 32 ssa_255 = iadd ssa_51, ssa_198.x vec1 32 ssa_256 = iadd ssa_51, ssa_198.y vec1 32 ssa_257 = iadd ssa_51, ssa_198.z vec1 32 ssa_258 = iadd ssa_51, ssa_203.x vec1 32 ssa_259 = idiv ssa_258, ssa_9 vec4 32 ssa_260 = txf ssa_259 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_261 = iadd ssa_255, ssa_9 vec1 32 ssa_262 = idiv ssa_261, ssa_9 vec4 32 ssa_263 = txf ssa_262 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_264 = ibitfield_extract ssa_263.x, ssa_8, ssa_11 vec1 32 ssa_265 = ishr ssa_263.x, ssa_11 vec1 32 ssa_266 = i2f32 ssa_265 vec1 32 ssa_267 = i2f32 ssa_264 vec1 32 ssa_268 = idiv ssa_255, ssa_9 vec4 32 ssa_269 = txf ssa_268 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_270 = ibitfield_extract ssa_269.x, ssa_8, ssa_11 vec1 32 ssa_271 = ishr ssa_269.x, ssa_11 vec1 32 ssa_272 = i2f32 ssa_271 vec1 32 ssa_273 = i2f32 ssa_270 vec1 32 ssa_274 = fadd ssa_239, ssa_273 vec1 32 ssa_275 = fadd ssa_240, ssa_272 vec1 32 ssa_276 = fadd ssa_241, ssa_267 vec1 32 ssa_277 = fadd ssa_242, ssa_266 vec1 32 ssa_278 = fmul ssa_42.y, ssa_274 vec1 32 ssa_279 = fadd ssa_278, ssa_248 vec1 32 ssa_280 = fmul ssa_42.y, ssa_275 vec1 32 ssa_281 = fadd ssa_280, ssa_250 vec1 32 ssa_282 = fmul ssa_42.y, ssa_276 vec1 32 ssa_283 = fadd ssa_282, ssa_252 vec1 32 ssa_284 = fmul ssa_42.y, ssa_277 vec1 32 ssa_285 = fadd ssa_284, ssa_254 vec1 32 ssa_286 = intrinsic vulkan_resource_index (ssa_8) () (0, 5) /* desc-set=0 */ /* binding=5 */ vec4 32 ssa_287 = intrinsic load_ubo (ssa_286, ssa_8) () () vec1 32 ssa_288 = fmul ssa_279, ssa_287.x vec1 32 ssa_289 = fmul ssa_281, ssa_287.y vec1 32 ssa_290 = fmul ssa_283, ssa_287.z vec1 32 ssa_291 = fmul ssa_285, ssa_287.w vec1 32 ssa_292 = idiv ssa_200, ssa_9 vec1 32 ssa_293 = iadd ssa_292, ssa_10 vec4 32 ssa_294 = txf ssa_293 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_295 = idiv ssa_201, ssa_9 vec4 32 ssa_296 = txf ssa_295 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_297 = ibitfield_extract ssa_294.x, ssa_7.y, ssa_6.y vec1 32 ssa_298 = ishr ssa_294.x, ssa_6.y vec1 32 ssa_299 = i2f32 ssa_298 vec1 32 ssa_300 = i2f32 ssa_297 vec1 32 ssa_301 = idiv ssa_221, ssa_9 vec1 32 ssa_302 = iadd ssa_301, ssa_10 vec4 32 ssa_303 = txf ssa_302 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_304 = idiv ssa_222, ssa_9 vec4 32 ssa_305 = txf ssa_304 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_306 = ibitfield_extract ssa_303.x, ssa_7.y, ssa_6.y vec1 32 ssa_307 = ishr ssa_303.x, ssa_6.y vec1 32 ssa_308 = i2f32 ssa_307 vec1 32 ssa_309 = i2f32 ssa_306 vec1 32 ssa_310 = fneg ssa_309 vec1 32 ssa_311 = fneg ssa_308 vec1 32 ssa_312 = fadd ssa_310, ssa_300 vec1 32 ssa_313 = fadd ssa_311, ssa_299 vec1 32 ssa_314 = fmul ssa_42.x, ssa_312 vec1 32 ssa_315 = fadd ssa_314, ssa_309 vec1 32 ssa_316 = fmul ssa_42.x, ssa_313 vec1 32 ssa_317 = fadd ssa_316, ssa_308 vec1 32 ssa_318 = idiv ssa_256, ssa_9 vec1 32 ssa_319 = iadd ssa_318, ssa_10 vec4 32 ssa_320 = txf ssa_319 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_321 = idiv ssa_257, ssa_9 vec4 32 ssa_322 = txf ssa_321 (coord), ssa_8 (lod), t1 (texture) vec1 32 ssa_323 = ibitfield_extract ssa_320.x, ssa_7.y, ssa_6.y vec1 32 ssa_324 = ishr ssa_320.x, ssa_6.y vec1 32 ssa_325 = i2f32 ssa_324 vec1 32 ssa_326 = i2f32 ssa_323 vec1 32 ssa_327 = fadd ssa_310, ssa_326 vec1 32 ssa_328 = fadd ssa_311, ssa_325 vec1 32 ssa_329 = fmul ssa_42.y, ssa_327 vec1 32 ssa_330 = fadd ssa_329, ssa_315 vec1 32 ssa_331 = fmul ssa_42.y, ssa_328 vec1 32 ssa_332 = fadd ssa_331, ssa_317 vec4 32 ssa_333 = intrinsic load_ubo (ssa_286, ssa_11) () () vec1 32 ssa_334 = fmul ssa_330, ssa_333.z vec1 32 ssa_335 = fmul ssa_332, ssa_333.w vec1 32 ssa_336 = ubitfield_extract ssa_206.x, ssa_4.x, ssa_5.x vec1 32 ssa_337 = ubitfield_extract ssa_206.x, ssa_4.y, ssa_5.y vec1 32 ssa_338 = u2f32 ssa_336 vec1 32 ssa_339 = u2f32 ssa_337 vec1 32 ssa_340 = iand ssa_206.x, ssa_3 vec1 32 ssa_341 = ushr ssa_206.x, ssa_2 vec1 32 ssa_342 = u2f32 ssa_341 vec1 32 ssa_343 = u2f32 ssa_340 vec1 32 ssa_344 = fmul ssa_338, ssa_1.x vec1 32 ssa_345 = fadd ssa_344, ssa_0.x vec1 32 ssa_346 = fmul ssa_339, ssa_1.y vec1 32 ssa_347 = fadd ssa_346, ssa_0.y vec1 32 ssa_348 = fmul ssa_343, ssa_1.z vec1 32 ssa_349 = fadd ssa_348, ssa_0.z vec1 32 ssa_350 = fmul ssa_342, ssa_1.w vec1 32 ssa_351 = fadd ssa_350, ssa_0.w vec1 32 ssa_352 = ubitfield_extract ssa_225.x, ssa_4.x, ssa_5.x vec1 32 ssa_353 = ubitfield_extract ssa_225.x, ssa_4.y, ssa_5.y vec1 32 ssa_354 = u2f32 ssa_352 vec1 32 ssa_355 = u2f32 ssa_353 vec1 32 ssa_356 = iand ssa_225.x, ssa_3 vec1 32 ssa_357 = ushr ssa_225.x, ssa_2 vec1 32 ssa_358 = u2f32 ssa_356 vec1 32 ssa_359 = u2f32 ssa_357 vec1 32 ssa_360 = fmul ssa_354, ssa_1.x vec1 32 ssa_361 = fadd ssa_360, ssa_0.x vec1 32 ssa_362 = fmul ssa_355, ssa_1.y vec1 32 ssa_363 = fadd ssa_362, ssa_0.y vec1 32 ssa_364 = fmul ssa_358, ssa_1.z vec1 32 ssa_365 = fadd ssa_364, ssa_0.z vec1 32 ssa_366 = fmul ssa_359, ssa_1.w vec1 32 ssa_367 = fadd ssa_366, ssa_0.w vec1 32 ssa_368 = fneg ssa_361 vec1 32 ssa_369 = fneg ssa_363 vec1 32 ssa_370 = fneg ssa_365 vec1 32 ssa_371 = fneg ssa_367 vec1 32 ssa_372 = fadd ssa_345, ssa_368 vec1 32 ssa_373 = fadd ssa_347, ssa_369 vec1 32 ssa_374 = fadd ssa_349, ssa_370 vec1 32 ssa_375 = fadd ssa_351, ssa_371 vec1 32 ssa_376 = fmul ssa_42.x, ssa_372 vec1 32 ssa_377 = fadd ssa_376, ssa_361 vec1 32 ssa_378 = fmul ssa_42.x, ssa_373 vec1 32 ssa_379 = fadd ssa_378, ssa_363 vec1 32 ssa_380 = fmul ssa_42.x, ssa_374 vec1 32 ssa_381 = fadd ssa_380, ssa_365 vec1 32 ssa_382 = fmul ssa_42.x, ssa_375 vec1 32 ssa_383 = fadd ssa_382, ssa_367 vec1 32 ssa_384 = ubitfield_extract ssa_260.x, ssa_4.x, ssa_5.x vec1 32 ssa_385 = ubitfield_extract ssa_260.x, ssa_4.y, ssa_5.y vec1 32 ssa_386 = u2f32 ssa_384 vec1 32 ssa_387 = u2f32 ssa_385 vec1 32 ssa_388 = iand ssa_260.x, ssa_3 vec1 32 ssa_389 = ushr ssa_260.x, ssa_2 vec1 32 ssa_390 = u2f32 ssa_388 vec1 32 ssa_391 = u2f32 ssa_389 vec1 32 ssa_392 = fmul ssa_386, ssa_1.x vec1 32 ssa_393 = fadd ssa_392, ssa_0.x vec1 32 ssa_394 = fmul ssa_387, ssa_1.y vec1 32 ssa_395 = fadd ssa_394, ssa_0.y vec1 32 ssa_396 = fmul ssa_390, ssa_1.z vec1 32 ssa_397 = fadd ssa_396, ssa_0.z vec1 32 ssa_398 = fmul ssa_391, ssa_1.w vec1 32 ssa_399 = fadd ssa_398, ssa_0.w vec1 32 ssa_400 = fadd ssa_368, ssa_393 vec1 32 ssa_401 = fadd ssa_369, ssa_395 vec1 32 ssa_402 = fadd ssa_370, ssa_397 vec1 32 ssa_403 = fadd ssa_371, ssa_399 vec1 32 ssa_404 = fmul ssa_42.y, ssa_400 vec1 32 ssa_405 = fadd ssa_404, ssa_377 vec1 32 ssa_406 = fmul ssa_42.y, ssa_401 vec1 32 ssa_407 = fadd ssa_406, ssa_379 vec1 32 ssa_408 = fmul ssa_42.y, ssa_402 vec1 32 ssa_409 = fadd ssa_408, ssa_381 vec1 32 ssa_410 = fmul ssa_42.y, ssa_403 vec1 32 ssa_411 = fadd ssa_410, ssa_383 vec1 32 ssa_412 = ubitfield_extract ssa_296.x, ssa_4.x, ssa_5.x vec1 32 ssa_413 = ubitfield_extract ssa_296.x, ssa_4.y, ssa_5.y vec1 32 ssa_414 = u2f32 ssa_412 vec1 32 ssa_415 = u2f32 ssa_413 vec1 32 ssa_416 = iand ssa_296.x, ssa_3 vec1 32 ssa_417 = ushr ssa_296.x, ssa_2 vec1 32 ssa_418 = u2f32 ssa_416 vec1 32 ssa_419 = u2f32 ssa_417 vec1 32 ssa_420 = fmul ssa_414, ssa_1.x vec1 32 ssa_421 = fadd ssa_420, ssa_0.x vec1 32 ssa_422 = fmul ssa_415, ssa_1.y vec1 32 ssa_423 = fadd ssa_422, ssa_0.y vec1 32 ssa_424 = fmul ssa_418, ssa_1.z vec1 32 ssa_425 = fadd ssa_424, ssa_0.z vec1 32 ssa_426 = fmul ssa_419, ssa_1.w vec1 32 ssa_427 = fadd ssa_426, ssa_0.w vec1 32 ssa_428 = ubitfield_extract ssa_305.x, ssa_4.x, ssa_5.x vec1 32 ssa_429 = ubitfield_extract ssa_305.x, ssa_4.y, ssa_5.y vec1 32 ssa_430 = u2f32 ssa_428 vec1 32 ssa_431 = u2f32 ssa_429 vec1 32 ssa_432 = iand ssa_305.x, ssa_3 vec1 32 ssa_433 = ushr ssa_305.x, ssa_2 vec1 32 ssa_434 = u2f32 ssa_432 vec1 32 ssa_435 = u2f32 ssa_433 vec1 32 ssa_436 = fmul ssa_430, ssa_1.x vec1 32 ssa_437 = fadd ssa_436, ssa_0.x vec1 32 ssa_438 = fmul ssa_431, ssa_1.y vec1 32 ssa_439 = fadd ssa_438, ssa_0.y vec1 32 ssa_440 = fmul ssa_434, ssa_1.z vec1 32 ssa_441 = fadd ssa_440, ssa_0.z vec1 32 ssa_442 = fmul ssa_435, ssa_1.w vec1 32 ssa_443 = fadd ssa_442, ssa_0.w vec1 32 ssa_444 = fneg ssa_437 vec1 32 ssa_445 = fneg ssa_439 vec1 32 ssa_446 = fneg ssa_441 vec1 32 ssa_447 = fneg ssa_443 vec1 32 ssa_448 = fadd ssa_444, ssa_421 vec1 32 ssa_449 = fadd ssa_445, ssa_423 vec1 32 ssa_450 = fadd ssa_446, ssa_425 vec1 32 ssa_451 = fadd ssa_447, ssa_427 vec1 32 ssa_452 = fmul ssa_42.x, ssa_448 vec1 32 ssa_453 = fadd ssa_452, ssa_437 vec1 32 ssa_454 = fmul ssa_42.x, ssa_449 vec1 32 ssa_455 = fadd ssa_454, ssa_439 vec1 32 ssa_456 = fmul ssa_42.x, ssa_450 vec1 32 ssa_457 = fadd ssa_456, ssa_441 vec1 32 ssa_458 = fmul ssa_42.x, ssa_451 vec1 32 ssa_459 = fadd ssa_458, ssa_443 vec1 32 ssa_460 = ubitfield_extract ssa_322.x, ssa_4.x, ssa_5.x vec1 32 ssa_461 = ubitfield_extract ssa_322.x, ssa_4.y, ssa_5.y vec1 32 ssa_462 = u2f32 ssa_460 vec1 32 ssa_463 = u2f32 ssa_461 vec1 32 ssa_464 = iand ssa_322.x, ssa_3 vec1 32 ssa_465 = ushr ssa_322.x, ssa_2 vec1 32 ssa_466 = u2f32 ssa_464 vec1 32 ssa_467 = u2f32 ssa_465 vec1 32 ssa_468 = fmul ssa_462, ssa_1.x vec1 32 ssa_469 = fadd ssa_468, ssa_0.x vec1 32 ssa_470 = fmul ssa_463, ssa_1.y vec1 32 ssa_471 = fadd ssa_470, ssa_0.y vec1 32 ssa_472 = fmul ssa_466, ssa_1.z vec1 32 ssa_473 = fadd ssa_472, ssa_0.z vec1 32 ssa_474 = fmul ssa_467, ssa_1.w vec1 32 ssa_475 = fadd ssa_474, ssa_0.w vec1 32 ssa_476 = fadd ssa_444, ssa_469 vec1 32 ssa_477 = fadd ssa_445, ssa_471 vec1 32 ssa_478 = fadd ssa_446, ssa_473 vec1 32 ssa_479 = fadd ssa_447, ssa_475 vec1 32 ssa_480 = fmul ssa_42.y, ssa_476 vec1 32 ssa_481 = fadd ssa_480, ssa_453 vec1 32 ssa_482 = fmul ssa_42.y, ssa_477 vec1 32 ssa_483 = fadd ssa_482, ssa_455 vec1 32 ssa_484 = fmul ssa_42.y, ssa_478 vec1 32 ssa_485 = fadd ssa_484, ssa_457 vec1 32 ssa_486 = fmul ssa_42.y, ssa_479 vec1 32 ssa_487 = fadd ssa_486, ssa_459 vec4 32 ssa_488 = vec4 ssa_193, ssa_194, ssa_195, ssa_196 intrinsic store_var (ssa_488) (ds_vertex_out.0) (15) /* wrmask=xyzw */ intrinsic store_var (ssa_288) (o1) (1) /* wrmask=x */ intrinsic store_var (ssa_289) (o1@0) (1) /* wrmask=x */ intrinsic store_var (ssa_290) (o1@1) (1) /* wrmask=x */ intrinsic store_var (ssa_291) (o1@2) (1) /* wrmask=x */ intrinsic store_var (ssa_334) (o2) (1) /* wrmask=x */ intrinsic store_var (ssa_335) (o2@3) (1) /* wrmask=x */ intrinsic store_var (ssa_405) (o3) (1) /* wrmask=x */ intrinsic store_var (ssa_407) (o3@4) (1) /* wrmask=x */ intrinsic store_var (ssa_409) (o3@5) (1) /* wrmask=x */ intrinsic store_var (ssa_411) (o3@6) (1) /* wrmask=x */ intrinsic store_var (ssa_481) (o4) (1) /* wrmask=x */ intrinsic store_var (ssa_483) (o4@7) (1) /* wrmask=x */ intrinsic store_var (ssa_485) (o4@8) (1) /* wrmask=x */ intrinsic store_var (ssa_487) (o4@9) (1) /* wrmask=x */ /* succs: block_0 */ block block_0: } shader: MESA_SHADER_FRAGMENT inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE sampler s1 (0, 0, 13) decl_var uniform INTERP_MODE_NONE sampler s2 (0, 0, 14) decl_var uniform INTERP_MODE_NONE sampler s3 (0, 0, 15) decl_var uniform INTERP_MODE_NONE sampler s4 (0, 0, 16) decl_var uniform INTERP_MODE_NONE sampler s5 (0, 0, 17) decl_var uniform INTERP_MODE_NONE sampler s6 (0, 0, 18) decl_var uniform INTERP_MODE_NONE sampler s7 (0, 0, 19) decl_var uniform INTERP_MODE_NONE sampler s8 (0, 0, 20) decl_var uniform INTERP_MODE_NONE sampler s9 (0, 0, 21) decl_var uniform INTERP_MODE_NONE sampler2D t0 (0, 0, 22) decl_var uniform INTERP_MODE_NONE sampler2D t1 (0, 0, 23) decl_var uniform INTERP_MODE_NONE sampler2D t2 (0, 0, 24) decl_var uniform INTERP_MODE_NONE sampler2D t3 (0, 0, 25) decl_var uniform INTERP_MODE_NONE sampler2D t4 (0, 0, 26) decl_var uniform INTERP_MODE_NONE sampler2D t5 (0, 0, 27) decl_var uniform INTERP_MODE_NONE sampler2D t7 (0, 0, 28) decl_var uniform INTERP_MODE_NONE sampler2D t8 (0, 0, 29) decl_var uniform INTERP_MODE_NONE sampler2D t9 (0, 0, 30) decl_var shader_in INTERP_MODE_NONE float v1 (VARYING_SLOT_VAR1.x, 0, 0) decl_var shader_in INTERP_MODE_NONE float v1@0 (VARYING_SLOT_VAR1.y, 0, 0) decl_var shader_in INTERP_MODE_NONE float v1@1 (VARYING_SLOT_VAR1.z, 0, 0) decl_var shader_in INTERP_MODE_NONE float v1@2 (VARYING_SLOT_VAR1.w, 0, 0) decl_var shader_in INTERP_MODE_NONE float v2 (VARYING_SLOT_VAR2.x, 0, 0) decl_var shader_in INTERP_MODE_NONE float v2@3 (VARYING_SLOT_VAR2.w, 0, 0) decl_var shader_in INTERP_MODE_NONE float v3 (VARYING_SLOT_VAR3.x, 0, 0) decl_var shader_in INTERP_MODE_NONE float v3@4 (VARYING_SLOT_VAR3.y, 0, 0) decl_var shader_in INTERP_MODE_NONE float v3@5 (VARYING_SLOT_VAR3.z, 0, 0) decl_var shader_in INTERP_MODE_NONE float v3@6 (VARYING_SLOT_VAR3.w, 0, 0) decl_var shader_in INTERP_MODE_NONE float v4 (VARYING_SLOT_VAR4.x, 0, 0) decl_var shader_in INTERP_MODE_NONE float v4@7 (VARYING_SLOT_VAR4.y, 0, 0) decl_var shader_in INTERP_MODE_NONE float v4@8 (VARYING_SLOT_VAR4.z, 0, 0) decl_var shader_in INTERP_MODE_NONE float v4@9 (VARYING_SLOT_VAR4.w, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 o0 (FRAG_RESULT_DATA0, 0, 0) decl_var shader_out INTERP_MODE_NONE vec4 o1 (FRAG_RESULT_DATA1, 0, 0) decl_function main returning void impl main { decl_var INTERP_MODE_NONE vec4 r3 decl_var INTERP_MODE_NONE vec4 r4 decl_var INTERP_MODE_NONE vec4 r5 decl_var INTERP_MODE_NONE vec4 r2 decl_var INTERP_MODE_NONE vec4 r1 decl_var INTERP_MODE_NONE vec4 r6 decl_var INTERP_MODE_NONE vec4[32] shader_in decl_var INTERP_MODE_NONE vec4 out@o0-temp decl_var INTERP_MODE_NONE vec4 out@o1-temp decl_var INTERP_MODE_NONE vec4 r0 block block_0: /* preds: */ vec1 32 ssa_0 = intrinsic load_var () (v1) () vec1 32 ssa_1 = intrinsic load_var () (v1@0) () vec1 32 ssa_2 = intrinsic load_var () (v1@1) () vec1 32 ssa_3 = intrinsic load_var () (v1@2) () vec1 32 ssa_4 = intrinsic load_var () (v2) () vec1 32 ssa_5 = intrinsic load_var () (v2@3) () vec1 32 ssa_6 = intrinsic load_var () (v3) () vec1 32 ssa_7 = intrinsic load_var () (v3@4) () vec1 32 ssa_8 = intrinsic load_var () (v3@5) () vec1 32 ssa_9 = intrinsic load_var () (v3@6) () vec1 32 ssa_10 = intrinsic load_var () (v4) () vec1 32 ssa_11 = intrinsic load_var () (v4@7) () vec1 32 ssa_12 = intrinsic load_var () (v4@8) () vec1 32 ssa_13 = intrinsic load_var () (v4@9) () vec1 32 ssa_14 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_15 = load_const (0x3b808081 /* 0.003922 */) vec1 32 ssa_16 = load_const (0x000000ff /* 0.000000 */) vec1 32 ssa_17 = load_const (0x00000008 /* 0.000000 */) vec3 32 ssa_18 = load_const (0x3b808081 /* 0.003922 */, 0x3b808081 /* 0.003922 */, 0x3b808081 /* 0.003922 */) vec1 32 ssa_19 = load_const (0x41800000 /* 16.000000 */) vec2 32 ssa_20 = load_const (0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */) vec2 32 ssa_21 = load_const (0x41700000 /* 15.000000 */, 0x40e00000 /* 7.000000 */) vec2 32 ssa_22 = load_const (0x437f0000 /* 255.000000 */, 0x437f0000 /* 255.000000 */) vec1 32 ssa_23 = load_const (0x3fa66666 /* 1.300000 */) vec1 32 ssa_24 = load_const (0x3f800000 /* 1.000000 */) vec2 32 ssa_25 = load_const (0xbf800000 /* -1.000000 */, 0xbf800000 /* -1.000000 */) vec2 32 ssa_26 = load_const (0x40000000 /* 2.000000 */, 0x40000000 /* 2.000000 */) vec3 32 ssa_27 = load_const (0x3e9e00d2 /* 0.308600 */, 0x3f1c01a3 /* 0.609400 */, 0x3da7ef9e /* 0.082000 */) vec1 32 ssa_28 = load_const (0x38d1b717 /* 0.000100 */) vec1 32 ssa_29 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_30 = load_const (0xbf000000 /* -0.500000 */) vec3 32 ssa_31 = load_const (0xbf800000 /* -1.000000 */, 0xbf800000 /* -1.000000 */, 0xbf800000 /* -1.000000 */) vec3 32 ssa_32 = load_const (0x40000000 /* 2.000000 */, 0x40000000 /* 2.000000 */, 0x40000000 /* 2.000000 */) vec2 32 ssa_33 = vec2 ssa_4, ssa_5 vec4 32 ssa_34 = tex ssa_33 (coord), t8 (texture)s8 (sampler) vec1 32 ssa_35 = fmul ssa_34.x, ssa_32.x vec1 32 ssa_36 = fadd ssa_35, ssa_31.x vec1 32 ssa_37 = fmul ssa_34.y, ssa_32.y vec1 32 ssa_38 = fadd ssa_37, ssa_31.y vec1 32 ssa_39 = fmul ssa_34.z, ssa_32.z vec1 32 ssa_40 = fadd ssa_39, ssa_31.z vec4 32 ssa_41 = tex ssa_33 (coord), t9 (texture)s9 (sampler) vec2 32 ssa_42 = vec2 ssa_0, ssa_1 vec4 32 ssa_43 = tex ssa_42 (coord), t0 (texture)s2 (sampler) vec1 32 ssa_44 = fmul ssa_40, ssa_7 vec1 32 ssa_45 = fmul ssa_36, ssa_8 vec1 32 ssa_46 = fmul ssa_38, ssa_6 vec1 32 ssa_47 = fneg ssa_44 vec1 32 ssa_48 = fneg ssa_45 vec1 32 ssa_49 = fneg ssa_46 vec1 32 ssa_50 = fmul ssa_38, ssa_8 vec1 32 ssa_51 = fadd ssa_50, ssa_47 vec1 32 ssa_52 = fmul ssa_40, ssa_6 vec1 32 ssa_53 = fadd ssa_52, ssa_48 vec1 32 ssa_54 = fmul ssa_36, ssa_7 vec1 32 ssa_55 = fadd ssa_54, ssa_49 vec1 32 ssa_56 = fmul ssa_51, ssa_9 vec1 32 ssa_57 = fmul ssa_53, ssa_9 vec1 32 ssa_58 = fmul ssa_55, ssa_9 vec4 32 ssa_59 = tex ssa_42 (coord), t2 (texture)s4 (sampler) vec1 32 ssa_60 = intrinsic vulkan_resource_index (ssa_14) () (0, 11) /* desc-set=0 */ /* binding=11 */ vec1 32 ssa_61 = load_const (0x00000030 /* 0.000000 */) vec4 32 ssa_62 = intrinsic load_ubo (ssa_60, ssa_61) () () vec1 32 ssa_63 = fneg ssa_62.x vec1 32 ssa_64 = fadd ssa_63, ssa_62.y vec1 32 ssa_65 = fmul ssa_59.x, ssa_64 vec1 32 ssa_66 = fadd ssa_65, ssa_62.x vec4 32 ssa_67 = tex ssa_42 (coord), t4 (texture)s6 (sampler) vec1 32 ssa_68 = load_const (0x00000060 /* 0.000000 */) vec4 32 ssa_69 = intrinsic load_ubo (ssa_60, ssa_68) () () vec1 32 ssa_70 = fmul ssa_69.x, ssa_27.x vec1 32 ssa_71 = fmul ssa_69.y, ssa_27.y vec1 32 ssa_72 = fadd ssa_70, ssa_71 vec1 32 ssa_73 = fmul ssa_69.z, ssa_27.z vec1 32 ssa_74 = fadd ssa_72, ssa_73 vec1 32 ssa_75 = fmul ssa_74, ssa_67.x vec2 32 ssa_76 = vec2 ssa_2, ssa_3 vec4 32 ssa_77 = tex ssa_76 (coord), t7 (texture)s1 (sampler) vec1 32 ssa_78 = intrinsic vulkan_resource_index (ssa_14) () (0, 12) /* desc-set=0 */ /* binding=12 */ vec4 32 ssa_79 = intrinsic load_ubo (ssa_78, ssa_14) () () vec1 32 ssa_80 = fneg ssa_79.y vec1 32 ssa_81 = fadd ssa_41.x, ssa_80 vec1 32 ssa_82 = fneg ssa_79.w vec1 32 ssa_83 = fadd ssa_77.w, ssa_82 vec1 32 ssa_84 = fmul ssa_83, ssa_79.z vec1 32 ssa_85 = fneg ssa_84 vec1 32 ssa_86 = fmul ssa_81, ssa_79.x vec1 32 ssa_87 = fadd ssa_86, ssa_85 vec1 32 ssa_88 = fmax ssa_87, ssa_30 vec1 32 ssa_89 = fmin ssa_88, ssa_29 vec1 32 ssa_90 = fadd ssa_89, ssa_29 vec1 32 ssa_91 = flt ssa_28, ssa_90 /* succs: block_1 block_2 */ if ssa_91 { block block_1: /* preds: block_0 */ vec4 32 ssa_92 = tex ssa_76 (coord), t1 (texture)s3 (sampler) vec1 32 ssa_93 = fneg ssa_43.x vec1 32 ssa_94 = fneg ssa_43.y vec1 32 ssa_95 = fadd ssa_93, ssa_92.x vec1 32 ssa_96 = fadd ssa_94, ssa_92.y vec1 32 ssa_97 = fmul ssa_90, ssa_95 vec1 32 ssa_98 = fadd ssa_97, ssa_43.x vec1 32 ssa_99 = fmul ssa_90, ssa_96 vec1 32 ssa_100 = fadd ssa_99, ssa_43.y vec1 32 ssa_101 = fneg ssa_6 vec1 32 ssa_102 = fneg ssa_7 vec1 32 ssa_103 = fneg ssa_8 vec1 32 ssa_104 = fadd ssa_101, ssa_10 vec1 32 ssa_105 = fadd ssa_102, ssa_11 vec1 32 ssa_106 = fadd ssa_103, ssa_12 vec1 32 ssa_107 = fmul ssa_90, ssa_104 vec1 32 ssa_108 = fadd ssa_107, ssa_6 vec1 32 ssa_109 = fmul ssa_90, ssa_105 vec1 32 ssa_110 = fadd ssa_109, ssa_7 vec1 32 ssa_111 = fmul ssa_90, ssa_106 vec1 32 ssa_112 = fadd ssa_111, ssa_8 vec1 32 ssa_113 = fmul ssa_40, ssa_11 vec1 32 ssa_114 = fmul ssa_36, ssa_12 vec1 32 ssa_115 = fmul ssa_38, ssa_10 vec1 32 ssa_116 = fneg ssa_113 vec1 32 ssa_117 = fneg ssa_114 vec1 32 ssa_118 = fneg ssa_115 vec1 32 ssa_119 = fmul ssa_38, ssa_12 vec1 32 ssa_120 = fadd ssa_119, ssa_116 vec1 32 ssa_121 = fmul ssa_40, ssa_10 vec1 32 ssa_122 = fadd ssa_121, ssa_117 vec1 32 ssa_123 = fmul ssa_36, ssa_11 vec1 32 ssa_124 = fadd ssa_123, ssa_118 vec1 32 ssa_125 = fneg ssa_56 vec1 32 ssa_126 = fneg ssa_57 vec1 32 ssa_127 = fneg ssa_58 vec1 32 ssa_128 = fmul ssa_120, ssa_13 vec1 32 ssa_129 = fadd ssa_128, ssa_125 vec1 32 ssa_130 = fmul ssa_122, ssa_13 vec1 32 ssa_131 = fadd ssa_130, ssa_126 vec1 32 ssa_132 = fmul ssa_124, ssa_13 vec1 32 ssa_133 = fadd ssa_132, ssa_127 vec1 32 ssa_134 = fmul ssa_90, ssa_129 vec1 32 ssa_135 = fadd ssa_134, ssa_56 vec1 32 ssa_136 = fmul ssa_90, ssa_131 vec1 32 ssa_137 = fadd ssa_136, ssa_57 vec1 32 ssa_138 = fmul ssa_90, ssa_133 vec1 32 ssa_139 = fadd ssa_138, ssa_58 vec4 32 ssa_140 = tex ssa_76 (coord), t3 (texture)s5 (sampler) vec1 32 ssa_141 = load_const (0x00000040 /* 0.000000 */) vec4 32 ssa_142 = intrinsic load_ubo (ssa_60, ssa_141) () () vec1 32 ssa_143 = fneg ssa_142.x vec1 32 ssa_144 = fadd ssa_143, ssa_142.y vec1 32 ssa_145 = fmul ssa_140.x, ssa_144 vec1 32 ssa_146 = fadd ssa_145, ssa_142.x vec1 32 ssa_147 = fneg ssa_66 vec1 32 ssa_148 = fadd ssa_147, ssa_146 vec1 32 ssa_149 = fmul ssa_90, ssa_148 vec1 32 ssa_150 = fadd ssa_149, ssa_66 vec4 32 ssa_151 = tex ssa_76 (coord), t5 (texture)s7 (sampler) vec1 32 ssa_152 = load_const (0x00000070 /* 0.000000 */) vec4 32 ssa_153 = intrinsic load_ubo (ssa_60, ssa_152) () () vec1 32 ssa_154 = fmul ssa_153.x, ssa_27.x vec1 32 ssa_155 = fmul ssa_153.y, ssa_27.y vec1 32 ssa_156 = fadd ssa_154, ssa_155 vec1 32 ssa_157 = fmul ssa_153.z, ssa_27.z vec1 32 ssa_158 = fadd ssa_156, ssa_157 vec1 32 ssa_159 = fneg ssa_75 vec1 32 ssa_160 = fmul ssa_151.x, ssa_158 vec1 32 ssa_161 = fadd ssa_160, ssa_159 vec1 32 ssa_162 = fmul ssa_90, ssa_161 vec1 32 ssa_163 = fadd ssa_162, ssa_75 /* succs: block_3 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_164 = imov ssa_43.x vec1 32 ssa_165 = imov ssa_43.y /* succs: block_3 */ } block block_3: /* preds: block_1 block_2 */ vec1 32 ssa_166 = phi block_1: ssa_108, block_2: ssa_6 vec1 32 ssa_167 = phi block_1: ssa_110, block_2: ssa_7 vec1 32 ssa_168 = phi block_1: ssa_112, block_2: ssa_8 vec1 32 ssa_169 = phi block_1: ssa_163, block_2: ssa_75 vec1 32 ssa_170 = phi block_1: ssa_150, block_2: ssa_66 vec1 32 ssa_171 = phi block_1: ssa_135, block_2: ssa_56 vec1 32 ssa_172 = phi block_1: ssa_137, block_2: ssa_57 vec1 32 ssa_173 = phi block_1: ssa_139, block_2: ssa_58 vec1 32 ssa_174 = phi block_1: ssa_98, block_2: ssa_164 vec1 32 ssa_175 = phi block_1: ssa_100, block_2: ssa_165 vec1 32 ssa_176 = fmul ssa_174, ssa_26.x vec1 32 ssa_177 = fadd ssa_176, ssa_25.x vec1 32 ssa_178 = fmul ssa_175, ssa_26.y vec1 32 ssa_179 = fadd ssa_178, ssa_25.y vec1 32 ssa_180 = fmul ssa_177, ssa_177 vec1 32 ssa_181 = fneg ssa_180 vec1 32 ssa_182 = fadd ssa_181, ssa_24 vec1 32 ssa_183 = fmul ssa_179, ssa_179 vec1 32 ssa_184 = fneg ssa_183 vec1 32 ssa_185 = fadd ssa_184, ssa_182 vec1 32 ssa_186 = flt ssa_14, ssa_185 vec1 32 ssa_187 = fsqrt ssa_185 vec1 32 ssa_188 = iand ssa_187, ssa_186 vec1 32 ssa_189 = fmul ssa_166, ssa_166 vec1 32 ssa_190 = fmul ssa_167, ssa_167 vec1 32 ssa_191 = fadd ssa_189, ssa_190 vec1 32 ssa_192 = fmul ssa_168, ssa_168 vec1 32 ssa_193 = fadd ssa_191, ssa_192 vec1 32 ssa_194 = frsq ssa_193 vec1 32 ssa_195 = fmul ssa_194, ssa_166 vec1 32 ssa_196 = fmul ssa_194, ssa_167 vec1 32 ssa_197 = fmul ssa_194, ssa_168 vec1 32 ssa_198 = fmul ssa_171, ssa_171 vec1 32 ssa_199 = fmul ssa_172, ssa_172 vec1 32 ssa_200 = fadd ssa_198, ssa_199 vec1 32 ssa_201 = fmul ssa_173, ssa_173 vec1 32 ssa_202 = fadd ssa_200, ssa_201 vec1 32 ssa_203 = frsq ssa_202 vec1 32 ssa_204 = fmul ssa_203, ssa_171 vec1 32 ssa_205 = fmul ssa_203, ssa_172 vec1 32 ssa_206 = fmul ssa_203, ssa_173 vec1 32 ssa_207 = fmul ssa_179, ssa_204 vec1 32 ssa_208 = fmul ssa_179, ssa_205 vec1 32 ssa_209 = fmul ssa_179, ssa_206 vec1 32 ssa_210 = fmul ssa_177, ssa_195 vec1 32 ssa_211 = fadd ssa_210, ssa_207 vec1 32 ssa_212 = fmul ssa_177, ssa_196 vec1 32 ssa_213 = fadd ssa_212, ssa_208 vec1 32 ssa_214 = fmul ssa_177, ssa_197 vec1 32 ssa_215 = fadd ssa_214, ssa_209 vec1 32 ssa_216 = fmul ssa_36, ssa_36 vec1 32 ssa_217 = fmul ssa_38, ssa_38 vec1 32 ssa_218 = fadd ssa_216, ssa_217 vec1 32 ssa_219 = fmul ssa_40, ssa_40 vec1 32 ssa_220 = fadd ssa_218, ssa_219 vec1 32 ssa_221 = frsq ssa_220 vec1 32 ssa_222 = fmul ssa_36, ssa_221 vec1 32 ssa_223 = fmul ssa_38, ssa_221 vec1 32 ssa_224 = fmul ssa_40, ssa_221 vec1 32 ssa_225 = fmul ssa_188, ssa_222 vec1 32 ssa_226 = fadd ssa_225, ssa_211 vec1 32 ssa_227 = fmul ssa_188, ssa_223 vec1 32 ssa_228 = fadd ssa_227, ssa_213 vec1 32 ssa_229 = fmul ssa_188, ssa_224 vec1 32 ssa_230 = fadd ssa_229, ssa_215 vec1 32 ssa_231 = fmul ssa_226, ssa_226 vec1 32 ssa_232 = fmul ssa_228, ssa_228 vec1 32 ssa_233 = fadd ssa_231, ssa_232 vec1 32 ssa_234 = fmul ssa_230, ssa_230 vec1 32 ssa_235 = fadd ssa_233, ssa_234 vec1 32 ssa_236 = frsq ssa_235 vec1 32 ssa_237 = fmul ssa_236, ssa_226 vec1 32 ssa_238 = fmul ssa_236, ssa_228 vec1 32 ssa_239 = fmul ssa_236, ssa_230 vec1 32 ssa_240 = intrinsic vulkan_resource_index (ssa_14) () (0, 9) /* desc-set=0 */ /* binding=9 */ vec4 32 ssa_241 = intrinsic load_ubo (ssa_240, ssa_61) () () vec1 32 ssa_242 = fmul ssa_238, ssa_241.x vec1 32 ssa_243 = fmul ssa_238, ssa_241.y vec1 32 ssa_244 = fmul ssa_238, ssa_241.z vec1 32 ssa_245 = load_const (0x00000020 /* 0.000000 */) vec4 32 ssa_246 = intrinsic load_ubo (ssa_240, ssa_245) () () vec1 32 ssa_247 = fmul ssa_246.x, ssa_237 vec1 32 ssa_248 = fadd ssa_247, ssa_242 vec1 32 ssa_249 = fmul ssa_246.y, ssa_237 vec1 32 ssa_250 = fadd ssa_249, ssa_243 vec1 32 ssa_251 = fmul ssa_246.z, ssa_237 vec1 32 ssa_252 = fadd ssa_251, ssa_244 vec1 32 ssa_253 = load_const (0x00000040 /* 0.000000 */) vec4 32 ssa_254 = intrinsic load_ubo (ssa_240, ssa_253) () () vec1 32 ssa_255 = fmul ssa_254.x, ssa_239 vec1 32 ssa_256 = fadd ssa_255, ssa_248 vec1 32 ssa_257 = fmul ssa_254.y, ssa_239 vec1 32 ssa_258 = fadd ssa_257, ssa_250 vec1 32 ssa_259 = fmul ssa_254.z, ssa_239 vec1 32 ssa_260 = fadd ssa_259, ssa_252 vec1 32 ssa_261 = fneg ssa_260 vec1 32 ssa_262 = fadd ssa_261, ssa_24 vec1 32 ssa_263 = fmul ssa_262, ssa_23 vec1 32 ssa_264 = frcp ssa_263 vec1 32 ssa_265 = fmul ssa_258, ssa_20.x vec1 32 ssa_266 = fmul ssa_265, ssa_264 vec1 32 ssa_267 = fadd ssa_266, ssa_20.x vec1 32 ssa_268 = fmul ssa_256, ssa_20.y vec1 32 ssa_269 = fmul ssa_268, ssa_264 vec1 32 ssa_270 = fadd ssa_269, ssa_20.y vec1 32 ssa_271 = fmul ssa_267, ssa_22.x vec1 32 ssa_272 = fmul ssa_270, ssa_22.y vec1 32 ssa_273 = ftrunc ssa_272 vec1 32 ssa_274 = ftrunc ssa_271 vec1 32 ssa_275 = fneg ssa_274 vec1 32 ssa_276 = fneg ssa_273 vec1 32 ssa_277 = fadd ssa_271, ssa_275 vec1 32 ssa_278 = fadd ssa_272, ssa_276 vec1 32 ssa_279 = fmul ssa_277, ssa_21.x vec1 32 ssa_280 = fadd ssa_279, ssa_20.x vec1 32 ssa_281 = fmul ssa_278, ssa_21.y vec1 32 ssa_282 = fadd ssa_281, ssa_20.y vec1 32 ssa_283 = ftrunc ssa_280 vec1 32 ssa_284 = ftrunc ssa_282 vec1 32 ssa_285 = fadd ssa_284, ssa_284 vec1 32 ssa_286 = fmul ssa_283, ssa_19 vec1 32 ssa_287 = fadd ssa_286, ssa_285 vec1 32 ssa_288 = fmul ssa_273, ssa_18.x vec1 32 ssa_289 = fmul ssa_274, ssa_18.y vec1 32 ssa_290 = fmul ssa_287, ssa_18.z vec1 32 ssa_291 = intrinsic vulkan_resource_index (ssa_14) () (0, 10) /* desc-set=0 */ /* binding=10 */ vec4 32 ssa_292 = intrinsic load_ubo (ssa_291, ssa_14) () () vec1 32 ssa_293 = ushr ssa_292.x, ssa_17 vec1 32 ssa_294 = u2f32 ssa_293 vec1 32 ssa_295 = fmul ssa_294, ssa_15 vec1 32 ssa_296 = iand ssa_292.x, ssa_16 vec1 32 ssa_297 = u2f32 ssa_296 vec1 32 ssa_298 = fmul ssa_297, ssa_15 vec4 32 ssa_299 = vec4 ssa_288, ssa_289, ssa_170, ssa_290 intrinsic store_var (ssa_299) (o0) (15) /* wrmask=xyzw */ vec4 32 ssa_300 = vec4 ssa_14, ssa_169, ssa_295, ssa_298 intrinsic store_var (ssa_300) (o1) (15) /* wrmask=xyzw */ /* succs: block_0 */ block block_0: } ; ModuleID = 'shader' source_filename = "shader" target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" target triple = "amdgcn-mesa-mesa3d" define amdgpu_ps void @main([0 x i8] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, i32, i32) #0 { main_body: %18 = bitcast <2 x i32> %3 to <2 x float> %19 = extractelement <2 x float> %18, i32 0 %20 = extractelement <2 x float> %18, i32 1 %21 = call float @llvm.amdgcn.interp.p1(float %19, i32 0, i32 0, i32 %1) #3 %22 = call float @llvm.amdgcn.interp.p2(float %21, float %20, i32 0, i32 0, i32 %1) #3 %23 = call float @llvm.amdgcn.interp.p1(float %19, i32 1, i32 0, i32 %1) #3 %24 = call float @llvm.amdgcn.interp.p2(float %23, float %20, i32 1, i32 0, i32 %1) #3 %25 = call float @llvm.amdgcn.interp.p1(float %19, i32 2, i32 0, i32 %1) #3 %26 = call float @llvm.amdgcn.interp.p2(float %25, float %20, i32 2, i32 0, i32 %1) #3 %27 = call float @llvm.amdgcn.interp.p1(float %19, i32 3, i32 0, i32 %1) #3 %28 = call float @llvm.amdgcn.interp.p2(float %27, float %20, i32 3, i32 0, i32 %1) #3 %29 = call float @llvm.amdgcn.interp.p1(float %19, i32 0, i32 1, i32 %1) #3 %30 = call float @llvm.amdgcn.interp.p2(float %29, float %20, i32 0, i32 1, i32 %1) #3 %31 = call float @llvm.amdgcn.interp.p1(float %19, i32 3, i32 1, i32 %1) #3 %32 = call float @llvm.amdgcn.interp.p2(float %31, float %20, i32 3, i32 1, i32 %1) #3 %33 = call float @llvm.amdgcn.interp.p1(float %19, i32 0, i32 2, i32 %1) #3 %34 = call float @llvm.amdgcn.interp.p2(float %33, float %20, i32 0, i32 2, i32 %1) #3 %35 = call float @llvm.amdgcn.interp.p1(float %19, i32 1, i32 2, i32 %1) #3 %36 = call float @llvm.amdgcn.interp.p2(float %35, float %20, i32 1, i32 2, i32 %1) #3 %37 = call float @llvm.amdgcn.interp.p1(float %19, i32 2, i32 2, i32 %1) #3 %38 = call float @llvm.amdgcn.interp.p2(float %37, float %20, i32 2, i32 2, i32 %1) #3 %39 = call float @llvm.amdgcn.interp.p1(float %19, i32 3, i32 2, i32 %1) #3 %40 = call float @llvm.amdgcn.interp.p2(float %39, float %20, i32 3, i32 2, i32 %1) #3 %41 = call float @llvm.amdgcn.interp.p1(float %19, i32 0, i32 3, i32 %1) #3 %42 = call float @llvm.amdgcn.interp.p2(float %41, float %20, i32 0, i32 3, i32 %1) #3 %43 = call float @llvm.amdgcn.interp.p1(float %19, i32 1, i32 3, i32 %1) #3 %44 = call float @llvm.amdgcn.interp.p2(float %43, float %20, i32 1, i32 3, i32 %1) #3 %45 = call float @llvm.amdgcn.interp.p1(float %19, i32 2, i32 3, i32 %1) #3 %46 = call float @llvm.amdgcn.interp.p2(float %45, float %20, i32 2, i32 3, i32 %1) #3 %47 = call float @llvm.amdgcn.interp.p1(float %19, i32 3, i32 3, i32 %1) #3 %48 = call float @llvm.amdgcn.interp.p2(float %47, float %20, i32 3, i32 3, i32 %1) #3 %49 = bitcast float %22 to i32 %50 = bitcast float %24 to i32 %51 = bitcast float %26 to i32 %52 = bitcast float %28 to i32 %53 = bitcast float %30 to i32 %54 = bitcast float %32 to i32 %55 = insertelement <2 x i32> undef, i32 %53, i32 0 %56 = insertelement <2 x i32> %55, i32 %54, i32 1 %57 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 864 %58 = bitcast i8 addrspace(6)* %57 to <8 x i32> addrspace(6)* %59 = load <8 x i32>, <8 x i32> addrspace(6)* %58, align 32, !invariant.load !0 %60 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 384 %61 = bitcast i8 addrspace(6)* %60 to <4 x i32> addrspace(6)* %62 = load <4 x i32>, <4 x i32> addrspace(6)* %61, align 16, !invariant.load !0 %63 = bitcast <2 x i32> %56 to <2 x float> %64 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %63, <8 x i32> %59, <4 x i32> %62, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #3 %65 = extractelement <4 x float> %64, i32 0 %66 = fmul float %65, 2.000000e+00 %67 = fadd float %66, -1.000000e+00 %68 = extractelement <4 x float> %64, i32 1 %69 = fmul float %68, 2.000000e+00 %70 = fadd float %69, -1.000000e+00 %71 = extractelement <4 x float> %64, i32 2 %72 = fmul float %71, 2.000000e+00 %73 = fadd float %72, -1.000000e+00 %74 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 928 %75 = bitcast i8 addrspace(6)* %74 to <8 x i32> addrspace(6)* %76 = load <8 x i32>, <8 x i32> addrspace(6)* %75, align 32, !invariant.load !0 %77 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 400 %78 = bitcast i8 addrspace(6)* %77 to <4 x i32> addrspace(6)* %79 = load <4 x i32>, <4 x i32> addrspace(6)* %78, align 16, !invariant.load !0 %80 = call float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float> %63, <8 x i32> %76, <4 x i32> %79, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false) %81 = insertelement <2 x i32> undef, i32 %49, i32 0 %82 = insertelement <2 x i32> %81, i32 %50, i32 1 %83 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 416 %84 = bitcast i8 addrspace(6)* %83 to <8 x i32> addrspace(6)* %85 = load <8 x i32>, <8 x i32> addrspace(6)* %84, align 32, !invariant.load !0 %86 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 288 %87 = bitcast i8 addrspace(6)* %86 to <4 x i32> addrspace(6)* %88 = load <4 x i32>, <4 x i32> addrspace(6)* %87, align 16, !invariant.load !0 %89 = bitcast <2 x i32> %82 to <2 x float> %90 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %89, <8 x i32> %85, <4 x i32> %88, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #3 %91 = bitcast <4 x float> %90 to <4 x i32> %92 = fmul float %73, %36 %93 = fmul float %67, %38 %94 = fmul float %70, %34 %95 = fmul float %70, %38 %96 = fsub float %95, %92 %97 = fmul float %73, %34 %98 = fsub float %97, %93 %99 = fmul float %67, %36 %100 = fsub float %99, %94 %101 = fmul float %96, %40 %102 = fmul float %98, %40 %103 = fmul float %100, %40 %104 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 544 %105 = bitcast i8 addrspace(6)* %104 to <8 x i32> addrspace(6)* %106 = load <8 x i32>, <8 x i32> addrspace(6)* %105, align 32, !invariant.load !0 %107 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 320 %108 = bitcast i8 addrspace(6)* %107 to <4 x i32> addrspace(6)* %109 = load <4 x i32>, <4 x i32> addrspace(6)* %108, align 16, !invariant.load !0 %110 = call float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float> %89, <8 x i32> %106, <4 x i32> %109, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false) %111 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 240 %112 = bitcast i8 addrspace(6)* %111 to <4 x i32> addrspace(6)*, !amdgpu.uniform !0 %113 = load <4 x i32>, <4 x i32> addrspace(6)* %112, align 16, !invariant.load !0 %114 = call float @llvm.SI.load.const.v4i32(<4 x i32> %113, i32 48) %115 = call float @llvm.SI.load.const.v4i32(<4 x i32> %113, i32 52) %116 = fsub float %115, %114 %117 = fmul float %110, %116 %118 = fadd float %117, %114 %119 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 672 %120 = bitcast i8 addrspace(6)* %119 to <8 x i32> addrspace(6)* %121 = load <8 x i32>, <8 x i32> addrspace(6)* %120, align 32, !invariant.load !0 %122 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 352 %123 = bitcast i8 addrspace(6)* %122 to <4 x i32> addrspace(6)* %124 = load <4 x i32>, <4 x i32> addrspace(6)* %123, align 16, !invariant.load !0 %125 = call float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float> %89, <8 x i32> %121, <4 x i32> %124, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false) %126 = call float @llvm.SI.load.const.v4i32(<4 x i32> %113, i32 96) %127 = call float @llvm.SI.load.const.v4i32(<4 x i32> %113, i32 100) %128 = call float @llvm.SI.load.const.v4i32(<4 x i32> %113, i32 104) %129 = fmul float %126, 0x3FD3C01A40000000 %130 = fmul float %127, 0x3FE3803460000000 %131 = fadd float %129, %130 %132 = fmul float %128, 0x3FB4FDF3C0000000 %133 = fadd float %131, %132 %134 = fmul float %133, %125 %135 = insertelement <2 x i32> undef, i32 %51, i32 0 %136 = insertelement <2 x i32> %135, i32 %52, i32 1 %137 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 800 %138 = bitcast i8 addrspace(6)* %137 to <8 x i32> addrspace(6)* %139 = load <8 x i32>, <8 x i32> addrspace(6)* %138, align 32, !invariant.load !0 %140 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 272 %141 = bitcast i8 addrspace(6)* %140 to <4 x i32> addrspace(6)* %142 = load <4 x i32>, <4 x i32> addrspace(6)* %141, align 16, !invariant.load !0 %143 = bitcast <2 x i32> %136 to <2 x float> %144 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %143, <8 x i32> %139, <4 x i32> %142, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #3 %145 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 256 %146 = bitcast i8 addrspace(6)* %145 to <4 x i32> addrspace(6)*, !amdgpu.uniform !0 %147 = load <4 x i32>, <4 x i32> addrspace(6)* %146, align 16, !invariant.load !0 %148 = call float @llvm.SI.load.const.v4i32(<4 x i32> %147, i32 0) %149 = call float @llvm.SI.load.const.v4i32(<4 x i32> %147, i32 4) %150 = call float @llvm.SI.load.const.v4i32(<4 x i32> %147, i32 8) %151 = call float @llvm.SI.load.const.v4i32(<4 x i32> %147, i32 12) %152 = fsub float %80, %149 %153 = extractelement <4 x float> %144, i32 3 %154 = fsub float %153, %151 %155 = fmul float %154, %150 %156 = fmul float %152, %148 %157 = fsub float %156, %155 %158 = call float @llvm.maxnum.f32(float %157, float -5.000000e-01) #3 %159 = call float @llvm.minnum.f32(float %158, float 5.000000e-01) #3 %160 = fadd float %159, 5.000000e-01 %161 = fcmp ogt float %160, 0x3F1A36E2E0000000 br i1 %161, label %if1, label %else2 if1: ; preds = %main_body %162 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 480 %163 = bitcast i8 addrspace(6)* %162 to <8 x i32> addrspace(6)* %164 = load <8 x i32>, <8 x i32> addrspace(6)* %163, align 32, !invariant.load !0 %165 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 304 %166 = bitcast i8 addrspace(6)* %165 to <4 x i32> addrspace(6)* %167 = load <4 x i32>, <4 x i32> addrspace(6)* %166, align 16, !invariant.load !0 %168 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %143, <8 x i32> %164, <4 x i32> %167, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #3 %169 = extractelement <4 x float> %90, i32 0 %170 = extractelement <4 x float> %90, i32 1 %171 = extractelement <4 x float> %168, i32 0 %172 = fsub float %171, %169 %173 = extractelement <4 x float> %168, i32 1 %174 = fsub float %173, %170 %175 = fmul float %160, %172 %176 = fadd float %175, %169 %177 = bitcast float %176 to i32 %178 = fmul float %160, %174 %179 = fadd float %178, %170 %180 = bitcast float %179 to i32 %181 = fsub float %42, %34 %182 = fsub float %44, %36 %183 = fsub float %46, %38 %184 = fmul float %160, %181 %185 = fadd float %184, %34 %186 = fmul float %160, %182 %187 = fadd float %186, %36 %188 = fmul float %160, %183 %189 = fadd float %188, %38 %190 = fmul float %73, %44 %191 = fmul float %67, %46 %192 = fmul float %70, %42 %193 = fmul float %70, %46 %194 = fsub float %193, %190 %195 = fmul float %73, %42 %196 = fsub float %195, %191 %197 = fmul float %67, %44 %198 = fsub float %197, %192 %199 = fmul float %194, %48 %200 = fsub float %199, %101 %201 = fmul float %196, %48 %202 = fsub float %201, %102 %203 = fmul float %198, %48 %204 = fsub float %203, %103 %205 = fmul float %160, %200 %206 = fadd float %205, %101 %207 = fmul float %160, %202 %208 = fadd float %207, %102 %209 = fmul float %160, %204 %210 = fadd float %209, %103 %211 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 608 %212 = bitcast i8 addrspace(6)* %211 to <8 x i32> addrspace(6)* %213 = load <8 x i32>, <8 x i32> addrspace(6)* %212, align 32, !invariant.load !0 %214 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 336 %215 = bitcast i8 addrspace(6)* %214 to <4 x i32> addrspace(6)* %216 = load <4 x i32>, <4 x i32> addrspace(6)* %215, align 16, !invariant.load !0 %217 = call float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float> %143, <8 x i32> %213, <4 x i32> %216, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false) %218 = call float @llvm.SI.load.const.v4i32(<4 x i32> %113, i32 64) %219 = call float @llvm.SI.load.const.v4i32(<4 x i32> %113, i32 68) %220 = fsub float %219, %218 %221 = fmul float %217, %220 %222 = fadd float %221, %218 %223 = fsub float %222, %118 %224 = fmul float %160, %223 %225 = fadd float %224, %118 %226 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 736 %227 = bitcast i8 addrspace(6)* %226 to <8 x i32> addrspace(6)* %228 = load <8 x i32>, <8 x i32> addrspace(6)* %227, align 32, !invariant.load !0 %229 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 368 %230 = bitcast i8 addrspace(6)* %229 to <4 x i32> addrspace(6)* %231 = load <4 x i32>, <4 x i32> addrspace(6)* %230, align 16, !invariant.load !0 %232 = call float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float> %143, <8 x i32> %228, <4 x i32> %231, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false) %233 = call float @llvm.SI.load.const.v4i32(<4 x i32> %113, i32 112) %234 = call float @llvm.SI.load.const.v4i32(<4 x i32> %113, i32 116) %235 = call float @llvm.SI.load.const.v4i32(<4 x i32> %113, i32 120) %236 = fmul float %233, 0x3FD3C01A40000000 %237 = fmul float %234, 0x3FE3803460000000 %238 = fadd float %236, %237 %239 = fmul float %235, 0x3FB4FDF3C0000000 %240 = fadd float %238, %239 %241 = fmul float %232, %240 %242 = fsub float %241, %134 %243 = fmul float %160, %242 %244 = fadd float %243, %134 br label %endif1 else2: ; preds = %main_body %245 = extractelement <4 x i32> %91, i32 0 %246 = extractelement <4 x i32> %91, i32 1 br label %endif1 endif1: ; preds = %else2, %if1 %.in = phi float [ %185, %if1 ], [ %34, %else2 ] %.in164 = phi float [ %187, %if1 ], [ %36, %else2 ] %.in165 = phi float [ %189, %if1 ], [ %38, %else2 ] %.in166 = phi float [ %244, %if1 ], [ %134, %else2 ] %.in167 = phi float [ %225, %if1 ], [ %118, %else2 ] %.in168 = phi float [ %206, %if1 ], [ %101, %else2 ] %.in169 = phi float [ %208, %if1 ], [ %102, %else2 ] %.in170 = phi float [ %210, %if1 ], [ %103, %else2 ] %247 = phi i32 [ %177, %if1 ], [ %245, %else2 ] %248 = phi i32 [ %180, %if1 ], [ %246, %else2 ] %249 = bitcast i32 %247 to float %250 = fmul float %249, 2.000000e+00 %251 = fadd float %250, -1.000000e+00 %252 = bitcast i32 %248 to float %253 = fmul float %252, 2.000000e+00 %254 = fadd float %253, -1.000000e+00 %255 = fmul float %251, %251 %256 = fsub float 1.000000e+00, %255 %257 = fmul float %254, %254 %258 = fsub float %256, %257 %259 = fcmp ogt float %258, 0.000000e+00 %260 = call float @llvm.sqrt.f32(float %258) #3 %261 = fmul float %.in, %.in %262 = fmul float %.in164, %.in164 %263 = fadd float %261, %262 %264 = fmul float %.in165, %.in165 %265 = fadd float %263, %264 %266 = call float @llvm.sqrt.f32(float %265) #3 %267 = fdiv float 1.000000e+00, %266, !fpmath !1 %268 = fmul float %267, %.in %269 = fmul float %267, %.in164 %270 = fmul float %267, %.in165 %271 = fmul float %.in168, %.in168 %272 = fmul float %.in169, %.in169 %273 = fadd float %271, %272 %274 = fmul float %.in170, %.in170 %275 = fadd float %273, %274 %276 = call float @llvm.sqrt.f32(float %275) #3 %277 = fdiv float 1.000000e+00, %276, !fpmath !1 %278 = fmul float %277, %.in168 %279 = fmul float %277, %.in169 %280 = fmul float %277, %.in170 %281 = fmul float %254, %278 %282 = fmul float %254, %279 %283 = fmul float %254, %280 %284 = fmul float %251, %268 %285 = fadd float %284, %281 %286 = fmul float %251, %269 %287 = fadd float %286, %282 %288 = fmul float %251, %270 %289 = fadd float %288, %283 %290 = fmul float %67, %67 %291 = fmul float %70, %70 %292 = fadd float %290, %291 %293 = fmul float %73, %73 %294 = fadd float %292, %293 %295 = call float @llvm.sqrt.f32(float %294) #3 %296 = fdiv float 1.000000e+00, %295, !fpmath !1 %297 = fmul float %67, %296 %298 = fmul float %70, %296 %299 = fmul float %73, %296 %300 = select i1 %259, float %260, float 0.000000e+00 %301 = fmul float %300, %297 %302 = fadd float %301, %285 %303 = fmul float %300, %298 %304 = fadd float %303, %287 %305 = fmul float %300, %299 %306 = fadd float %305, %289 %307 = fmul float %302, %302 %308 = fmul float %304, %304 %309 = fadd float %307, %308 %310 = fmul float %306, %306 %311 = fadd float %309, %310 %312 = call float @llvm.sqrt.f32(float %311) #3 %313 = fdiv float 1.000000e+00, %312, !fpmath !1 %314 = fmul float %313, %302 %315 = fmul float %313, %304 %316 = fmul float %313, %306 %317 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 208 %318 = bitcast i8 addrspace(6)* %317 to <4 x i32> addrspace(6)*, !amdgpu.uniform !0 %319 = load <4 x i32>, <4 x i32> addrspace(6)* %318, align 16, !invariant.load !0 %320 = call float @llvm.SI.load.const.v4i32(<4 x i32> %319, i32 48) %321 = call float @llvm.SI.load.const.v4i32(<4 x i32> %319, i32 52) %322 = call float @llvm.SI.load.const.v4i32(<4 x i32> %319, i32 56) %323 = fmul float %315, %320 %324 = fmul float %315, %321 %325 = fmul float %315, %322 %326 = call float @llvm.SI.load.const.v4i32(<4 x i32> %319, i32 32) %327 = call float @llvm.SI.load.const.v4i32(<4 x i32> %319, i32 36) %328 = call float @llvm.SI.load.const.v4i32(<4 x i32> %319, i32 40) %329 = fmul float %326, %314 %330 = fadd float %329, %323 %331 = fmul float %327, %314 %332 = fadd float %331, %324 %333 = fmul float %328, %314 %334 = fadd float %333, %325 %335 = call float @llvm.SI.load.const.v4i32(<4 x i32> %319, i32 64) %336 = call float @llvm.SI.load.const.v4i32(<4 x i32> %319, i32 68) %337 = call float @llvm.SI.load.const.v4i32(<4 x i32> %319, i32 72) %338 = fmul float %335, %316 %339 = fadd float %338, %330 %340 = fmul float %336, %316 %341 = fadd float %340, %332 %342 = fmul float %337, %316 %343 = fadd float %342, %334 %344 = fsub float 1.000000e+00, %343 %345 = fmul float %344, 0x3FF4CCCCC0000000 %346 = fdiv float 1.000000e+00, %345, !fpmath !1 %347 = fmul float %341, 5.000000e-01 %348 = fmul float %347, %346 %349 = fadd float %348, 5.000000e-01 %350 = fmul float %339, 5.000000e-01 %351 = fmul float %350, %346 %352 = fadd float %351, 5.000000e-01 %353 = fmul float %349, 2.550000e+02 %354 = fmul float %352, 2.550000e+02 %355 = call float @llvm.trunc.f32(float %354) #3 %356 = call float @llvm.trunc.f32(float %353) #3 %357 = fsub float %353, %356 %358 = fsub float %354, %355 %359 = fmul float %357, 1.500000e+01 %360 = fadd float %359, 5.000000e-01 %361 = fmul float %358, 7.000000e+00 %362 = fadd float %361, 5.000000e-01 %363 = call float @llvm.trunc.f32(float %360) #3 %364 = call float @llvm.trunc.f32(float %362) #3 %365 = fadd float %364, %364 %366 = fmul float %363, 1.600000e+01 %367 = fadd float %366, %365 %368 = fmul float %355, 0x3F70101020000000 %369 = fmul float %356, 0x3F70101020000000 %370 = fmul float %367, 0x3F70101020000000 %371 = getelementptr [0 x i8], [0 x i8] addrspace(6)* %0, i32 0, i32 224 %372 = bitcast i8 addrspace(6)* %371 to <4 x i32> addrspace(6)*, !amdgpu.uniform !0 %373 = load <4 x i32>, <4 x i32> addrspace(6)* %372, align 16, !invariant.load !0 %374 = call float @llvm.SI.load.const.v4i32(<4 x i32> %373, i32 0) %375 = bitcast float %374 to i32 %376 = lshr i32 %375, 8 %377 = uitofp i32 %376 to float %378 = fmul float %377, 0x3F70101020000000 %379 = and i32 %375, 255 %380 = uitofp i32 %379 to float %381 = fmul float %380, 0x3F70101020000000 %382 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %368, float %369) #3 %383 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %.in167, float %370) #3 %384 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 0.000000e+00, float %.in166) #3 %385 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %378, float %381) #3 %386 = bitcast <2 x half> %382 to <2 x i16> %387 = bitcast <2 x half> %383 to <2 x i16> call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 5, <2 x i16> %386, <2 x i16> %387, i1 false, i1 false) #4 %388 = bitcast <2 x half> %384 to <2 x i16> %389 = bitcast <2 x half> %385 to <2 x i16> call void @llvm.amdgcn.exp.compr.v2i16(i32 1, i32 5, <2 x i16> %388, <2 x i16> %389, i1 true, i1 true) #4 ret void } ; Function Attrs: nounwind readnone speculatable declare i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr() #1 ; Function Attrs: nounwind readnone speculatable declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1 ; Function Attrs: nounwind readnone speculatable declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1 ; Function Attrs: nounwind readonly declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #2 ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #3 ; Function Attrs: nounwind readnone speculatable declare float @llvm.maxnum.f32(float, float) #1 ; Function Attrs: nounwind readnone speculatable declare float @llvm.minnum.f32(float, float) #1 ; Function Attrs: nounwind readnone speculatable declare float @llvm.sqrt.f32(float) #1 ; Function Attrs: nounwind readnone speculatable declare float @llvm.trunc.f32(float) #1 ; Function Attrs: nounwind readnone speculatable declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1 ; Function Attrs: nounwind declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1) #4 ; Function Attrs: nounwind readonly declare float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #2 attributes #0 = { "amdgpu-32bit-address-high-bits"="0xffff8000" } attributes #1 = { nounwind readnone speculatable } attributes #2 = { nounwind readonly } attributes #3 = { nounwind readnone } attributes #4 = { nounwind } !0 = !{} !1 = !{float 2.500000e+00} disasm: main: BB0_0: s_mov_b64 s[4:5], exec ; BE84017E s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 s0, s3 ; BE800003 s_movk_i32 s3, 0x8000 ; B0038000 s_load_dwordx4 s[8:11], s[2:3], 0x110 ; C00A0201 00000110 s_load_dwordx4 s[12:15], s[2:3], 0x120 ; C00A0301 00000120 s_load_dwordx8 s[16:23], s[2:3], 0x320 ; C00E0401 00000320 s_load_dwordx4 s[60:63], s[2:3], 0x180 ; C00A0F01 00000180 s_load_dwordx4 s[64:67], s[2:3], 0x190 ; C00A1001 00000190 s_load_dwordx8 s[36:43], s[2:3], 0x3a0 ; C00E0901 000003A0 s_load_dwordx8 s[44:51], s[2:3], 0x360 ; C00E0B01 00000360 s_mov_b32 m0, s0 ; BEFC0000 s_load_dwordx8 s[52:59], s[2:3], 0x220 ; C00E0D01 00000220 s_load_dwordx4 s[68:71], s[2:3], 0x140 ; C00A1101 00000140 s_load_dwordx4 s[24:27], s[2:3], 0x160 ; C00A0601 00000160 s_load_dwordx8 s[28:35], s[2:3], 0x2a0 ; C00E0701 000002A0 v_interp_p1_f32_e32 v6, v0, attr0.z ; D4180200 v_interp_p1_f32_e32 v7, v0, attr0.w ; D41C0300 v_interp_p1_f32_e32 v2, v0, attr1.x ; D4080400 v_interp_p1_f32_e32 v3, v0, attr1.w ; D40C0700 v_interp_p2_f32_e32 v6, v1, attr0.z ; D4190201 v_interp_p2_f32_e32 v7, v1, attr0.w ; D41D0301 v_interp_p1_f32_e32 v15, v0, attr0.x ; D43C0000 v_interp_p1_f32_e32 v16, v0, attr0.y ; D4400100 v_interp_p2_f32_e32 v2, v1, attr1.x ; D4090401 v_interp_p2_f32_e32 v3, v1, attr1.w ; D40D0701 s_waitcnt lgkmcnt(0) ; BF8CC07F image_sample v12, v[6:7], s[16:23], s[8:11] dmask:0x8 ; F0800800 00440C06 image_sample v[8:10], v[2:3], s[44:51], s[60:63] dmask:0x7 ; F0800700 01EB0802 image_sample v13, v[2:3], s[36:43], s[64:67] dmask:0x1 ; F0800100 02090D02 v_interp_p2_f32_e32 v15, v1, attr0.x ; D43D0001 v_interp_p2_f32_e32 v16, v1, attr0.y ; D4410101 image_sample v2, v[15:16], s[52:59], s[68:71] dmask:0x1 ; F0800100 022D020F image_sample v20, v[15:16], s[28:35], s[24:27] dmask:0x1 ; F0800100 00C7140F s_load_dwordx4 s[8:11], s[2:3], 0xf0 ; C00A0201 000000F0 s_load_dwordx4 s[36:39], s[2:3], 0x100 ; C00A0901 00000100 v_mov_b32_e32 v3, 0x3f1c01a3 ; 7E0602FF 3F1C01A3 v_mov_b32_e32 v14, 0x3e9e00d2 ; 7E1C02FF 3E9E00D2 v_interp_p1_f32_e32 v4, v0, attr2.x ; D4100800 s_waitcnt lgkmcnt(0) ; BF8CC07F s_buffer_load_dwordx2 s[6:7], s[8:11], 0x30 ; C0260184 00000030 s_buffer_load_dwordx2 s[40:41], s[8:11], 0x60 ; C0260A04 00000060 s_buffer_load_dwordx4 s[24:27], s[36:39], 0x0 ; C02A0612 00000000 s_buffer_load_dword s1, s[8:11], 0x68 ; C0220044 00000068 v_interp_p1_f32_e32 v5, v0, attr2.y ; D4140900 v_interp_p1_f32_e32 v11, v0, attr2.z ; D42C0A00 s_waitcnt lgkmcnt(0) ; BF8CC07F v_mul_f32_e32 v21, s41, v3 ; 0A2A0629 v_mov_b32_e32 v3, s6 ; 7E060206 s_load_dwordx8 s[16:23], s[2:3], 0x1a0 ; C00E0401 000001A0 v_mov_b32_e32 v17, 0x3da7ef9e ; 7E2202FF 3DA7EF9E v_mac_f32_e32 v21, s40, v14 ; 2C2A1C28 v_sub_f32_e32 v3, s7, v3 ; 04060607 v_interp_p2_f32_e32 v4, v1, attr2.x ; D4110801 v_interp_p2_f32_e32 v5, v1, attr2.y ; D4150901 v_interp_p2_f32_e32 v11, v1, attr2.z ; D42D0A01 v_mac_f32_e32 v21, s1, v17 ; 2C2A2201 v_interp_p1_f32_e32 v19, v0, attr2.w ; D44C0B00 v_interp_p2_f32_e32 v19, v1, attr2.w ; D44D0B01 v_mov_b32_e32 v18, 0x38d1b717 ; 7E2402FF 38D1B717 s_waitcnt vmcnt(4) ; BF8C0F74 v_subrev_f32_e32 v12, s27, v12 ; 0618181B s_waitcnt vmcnt(3) ; BF8C0F73 v_mad_f32 v8, v8, 2.0, -1.0 ; D1C10008 03CDE908 v_mad_f32 v10, v10, 2.0, -1.0 ; D1C1000A 03CDE90A v_mad_f32 v9, v9, 2.0, -1.0 ; D1C10009 03CDE909 s_waitcnt vmcnt(2) ; BF8C0F72 v_subrev_f32_e32 v13, s25, v13 ; 061A1A19 v_mul_f32_e32 v12, s26, v12 ; 0A18181A s_waitcnt vmcnt(1) ; BF8C0F71 v_mad_f32 v3, v2, v3, s6 ; D1C10003 001A0702 s_waitcnt vmcnt(0) ; BF8C0F70 v_mul_f32_e32 v2, v21, v20 ; 0A042915 v_mul_f32_e32 v14, v10, v5 ; 0A1C0B0A v_mad_f32 v21, v13, s24, -v12 ; D1C10015 8430310D v_mul_f32_e32 v17, v8, v11 ; 0A221708 v_mul_f32_e32 v20, v9, v4 ; 0A280909 v_mad_f32 v12, v9, v11, -v14 ; D1C1000C 843A1709 v_mad_f32 v13, v10, v4, -v17 ; D1C1000D 8446090A v_mad_f32 v14, v8, v5, -v20 ; D1C1000E 84520B08 v_med3_f32 v17, v21, -0.5, 0.5 ; D1D60011 03C1E315 v_mul_f32_e32 v12, v12, v19 ; 0A18270C v_mul_f32_e32 v13, v13, v19 ; 0A1A270D v_mul_f32_e32 v14, v14, v19 ; 0A1C270E v_add_f32_e32 v19, 0.5, v17 ; 022622F0 v_cmp_ngt_f32_e32 vcc, v19, v18 ; 7C962513 s_waitcnt lgkmcnt(0) ; BF8CC07F image_sample v[15:18], v[15:16], s[16:23], s[12:15] dmask:0xf ; F0800F00 00640F0F s_and_saveexec_b64 s[6:7], vcc ; BE86206A s_xor_b64 s[6:7], exec, s[6:7] ; 8886067E BB0_1: s_or_saveexec_b64 s[6:7], s[6:7] ; BE862106 s_xor_b64 exec, exec, s[6:7] ; 88FE067E s_cbranch_execz BB0_3 ; BF880000 BB0_2: s_mov_b32 m0, s0 ; BEFC0000 s_movk_i32 s1, 0x8000 ; B0018000 s_waitcnt vmcnt(0) ; BF8C0F70 v_interp_p1_f32_e32 v18, v0, attr3.x ; D4480C00 s_mov_b32 s0, s2 ; BE800002 v_interp_p1_f32_e32 v20, v0, attr3.y ; D4500D00 v_interp_p2_f32_e32 v18, v1, attr3.x ; D4490C01 v_interp_p1_f32_e32 v21, v0, attr3.z ; D4540E00 v_interp_p1_f32_e32 v22, v0, attr3.w ; D4580F00 v_sub_f32_e32 v0, v18, v4 ; 04000912 s_load_dwordx4 s[36:39], s[0:1], 0x130 ; C00A0900 00000130 s_load_dwordx4 s[40:43], s[0:1], 0x150 ; C00A0A00 00000150 s_load_dwordx8 s[12:19], s[0:1], 0x260 ; C00E0300 00000260 v_interp_p2_f32_e32 v20, v1, attr3.y ; D4510D01 s_load_dwordx8 s[20:27], s[0:1], 0x2e0 ; C00E0500 000002E0 s_load_dwordx4 s[44:47], s[0:1], 0x170 ; C00A0B00 00000170 s_load_dwordx8 s[28:35], s[0:1], 0x1e0 ; C00E0700 000001E0 v_mac_f32_e32 v4, v19, v0 ; 2C080113 v_sub_f32_e32 v0, v20, v5 ; 04000B14 v_interp_p2_f32_e32 v21, v1, attr3.z ; D4550E01 v_mac_f32_e32 v5, v19, v0 ; 2C0A0113 v_sub_f32_e32 v0, v21, v11 ; 04001715 v_mac_f32_e32 v11, v19, v0 ; 2C160113 v_mul_f32_e32 v0, v10, v20 ; 0A00290A v_mad_f32 v23, v9, v21, -v0 ; D1C10017 84022B09 v_mul_f32_e32 v0, v8, v21 ; 0A002B08 s_waitcnt lgkmcnt(0) ; BF8CC07F image_sample v17, v[6:7], s[12:19], s[40:43] dmask:0x1 ; F0800100 01431106 v_mad_f32 v21, v10, v18, -v0 ; D1C10015 8402250A v_mul_f32_e32 v0, v9, v18 ; 0A002509 v_interp_p2_f32_e32 v22, v1, attr3.w ; D4590F01 v_mad_f32 v18, v8, v20, -v0 ; D1C10012 84022908 image_sample v20, v[6:7], s[20:27], s[44:47] dmask:0x1 ; F0800100 01651406 image_sample v[0:1], v[6:7], s[28:35], s[36:39] dmask:0x3 ; F0800300 01270006 s_buffer_load_dwordx2 s[0:1], s[8:11], 0x40 ; C0260004 00000040 s_buffer_load_dwordx2 s[12:13], s[8:11], 0x70 ; C0260304 00000070 s_buffer_load_dword s3, s[8:11], 0x78 ; C02200C4 00000078 v_mad_f32 v7, v21, v22, -v13 ; D1C10007 84362D15 v_mad_f32 v6, v23, v22, -v12 ; D1C10006 84322D17 v_mad_f32 v18, v18, v22, -v14 ; D1C10012 843A2D12 v_mov_b32_e32 v21, 0x3f1c01a3 ; 7E2A02FF 3F1C01A3 v_mac_f32_e32 v12, v19, v6 ; 2C180D13 v_mac_f32_e32 v14, v19, v18 ; 2C1C2513 s_waitcnt lgkmcnt(0) ; BF8CC07F v_mov_b32_e32 v18, s0 ; 7E240200 v_mov_b32_e32 v6, 0x3e9e00d2 ; 7E0C02FF 3E9E00D2 v_mul_f32_e32 v21, s13, v21 ; 0A2A2A0D v_mac_f32_e32 v13, v19, v7 ; 2C1A0F13 v_mov_b32_e32 v7, 0x3da7ef9e ; 7E0E02FF 3DA7EF9E v_mac_f32_e32 v21, s12, v6 ; 2C2A0C0C v_sub_f32_e32 v18, s1, v18 ; 04242401 v_mac_f32_e32 v21, s3, v7 ; 2C2A0E03 s_waitcnt vmcnt(2) ; BF8C0F72 v_mad_f32 v6, v17, v18, s0 ; D1C10006 00022511 v_sub_f32_e32 v6, v6, v3 ; 040C0706 v_mac_f32_e32 v3, v19, v6 ; 2C060D13 s_waitcnt vmcnt(1) ; BF8C0F71 v_mad_f32 v7, v20, v21, -v2 ; D1C10007 840A2B14 s_waitcnt vmcnt(0) ; BF8C0F70 v_sub_f32_e32 v0, v0, v15 ; 04001F00 v_sub_f32_e32 v1, v1, v16 ; 04022101 v_mad_f32 v15, v19, v0, v15 ; D1C1000F 043E0113 v_mad_f32 v16, v19, v1, v16 ; D1C10010 04420313 v_mac_f32_e32 v2, v19, v7 ; 2C040F13 BB0_3: s_or_b64 exec, exec, s[6:7] ; 87FE067E s_and_b64 exec, exec, s[4:5] ; 86FE047E s_waitcnt vmcnt(0) ; BF8C0F70 v_mad_f32 v1, v16, 2.0, -1.0 ; D1C10001 03CDE910 v_mul_f32_e32 v16, v13, v13 ; 0A201B0D v_mac_f32_e32 v16, v12, v12 ; 2C20190C v_mac_f32_e32 v16, v14, v14 ; 2C201D0E v_rsq_f32_e32 v16, v16 ; 7E204910 v_mad_f32 v0, v15, 2.0, -1.0 ; D1C10000 03CDE90F v_mad_f32 v6, -v0, v0, 1.0 ; D1C10006 23CA0100 v_mul_f32_e32 v15, v5, v5 ; 0A1E0B05 v_mul_f32_e32 v12, v16, v12 ; 0A181910 v_mul_f32_e32 v13, v16, v13 ; 0A1A1B10 v_mul_f32_e32 v14, v16, v14 ; 0A1C1D10 v_mad_f32 v6, -v1, v1, v6 ; D1C10006 241A0301 v_mac_f32_e32 v15, v4, v4 ; 2C1E0904 v_mul_f32_e32 v12, v1, v12 ; 0A181901 v_mul_f32_e32 v13, v1, v13 ; 0A1A1B01 v_mul_f32_e32 v1, v1, v14 ; 0A021D01 v_mul_f32_e32 v14, v9, v9 ; 0A1C1309 v_mac_f32_e32 v15, v11, v11 ; 2C1E170B v_mac_f32_e32 v14, v8, v8 ; 2C1C1108 v_rsq_f32_e32 v15, v15 ; 7E1E490F v_mac_f32_e32 v14, v10, v10 ; 2C1C150A v_sqrt_f32_e32 v7, v6 ; 7E0E4F06 v_rsq_f32_e32 v14, v14 ; 7E1C490E v_cmp_lt_f32_e32 vcc, 0, v6 ; 7C820C80 s_movk_i32 s3, 0x8000 ; B0038000 v_mul_f32_e32 v4, v15, v4 ; 0A08090F v_mul_f32_e32 v5, v15, v5 ; 0A0A0B0F s_load_dwordx4 s[4:7], s[2:3], 0xd0 ; C00A0101 000000D0 v_mul_f32_e32 v11, v15, v11 ; 0A16170F v_mac_f32_e32 v12, v0, v4 ; 2C180900 v_mac_f32_e32 v13, v0, v5 ; 2C1A0B00 v_mul_f32_e32 v4, v9, v14 ; 0A081D09 v_cndmask_b32_e32 v6, 0, v7, vcc ; 000C0E80 v_mac_f32_e32 v1, v0, v11 ; 2C021700 v_mul_f32_e32 v0, v8, v14 ; 0A001D08 v_mac_f32_e32 v13, v6, v4 ; 2C1A0906 v_mul_f32_e32 v5, v10, v14 ; 0A0A1D0A v_mac_f32_e32 v12, v6, v0 ; 2C180106 v_mul_f32_e32 v0, v13, v13 ; 0A001B0D v_mac_f32_e32 v1, v6, v5 ; 2C020B06 v_mac_f32_e32 v0, v12, v12 ; 2C00190C v_mac_f32_e32 v0, v1, v1 ; 2C000301 v_rsq_f32_e32 v0, v0 ; 7E004900 s_load_dwordx4 s[0:3], s[2:3], 0xe0 ; C00A0001 000000E0 s_waitcnt lgkmcnt(0) ; BF8CC07F s_buffer_load_dwordx2 s[8:9], s[4:7], 0x20 ; C0260202 00000020 s_buffer_load_dword s12, s[4:7], 0x28 ; C0220302 00000028 s_buffer_load_dwordx2 s[10:11], s[4:7], 0x30 ; C0260282 00000030 v_mul_f32_e32 v5, v0, v13 ; 0A0A1B00 v_mul_f32_e32 v4, v0, v12 ; 0A081900 v_mul_f32_e32 v0, v0, v1 ; 0A000300 s_buffer_load_dword s0, s[0:3], 0x0 ; C0220000 00000000 s_waitcnt lgkmcnt(0) ; BF8CC07F v_mul_f32_e32 v1, s10, v5 ; 0A020A0A v_mul_f32_e32 v6, s11, v5 ; 0A0C0A0B s_buffer_load_dword s13, s[4:7], 0x38 ; C0220342 00000038 s_buffer_load_dwordx2 s[10:11], s[4:7], 0x40 ; C0260282 00000040 s_buffer_load_dword s4, s[4:7], 0x48 ; C0220102 00000048 v_mac_f32_e32 v1, s8, v4 ; 2C020808 v_mac_f32_e32 v6, s9, v4 ; 2C0C0809 s_waitcnt lgkmcnt(0) ; BF8CC07F v_mul_f32_e32 v5, s13, v5 ; 0A0A0A0D v_mac_f32_e32 v5, s12, v4 ; 2C0A080C v_mac_f32_e32 v5, s4, v0 ; 2C0A0004 v_sub_f32_e32 v4, 1.0, v5 ; 04080AF2 v_mul_f32_e32 v4, 0x3fa66666, v4 ; 0A0808FF 3FA66666 v_rcp_f32_e32 v4, v4 ; 7E084504 v_mac_f32_e32 v1, s10, v0 ; 2C02000A v_mac_f32_e32 v6, s11, v0 ; 2C0C000B v_mul_f32_e32 v0, 0.5, v6 ; 0A000CF0 v_mul_f32_e32 v1, 0.5, v1 ; 0A0202F0 v_mad_f32 v0, v0, v4, 0.5 ; D1C10000 03C20900 v_mad_f32 v1, v1, v4, 0.5 ; D1C10001 03C20901 v_mov_b32_e32 v4, 0x437f0000 ; 7E0802FF 437F0000 v_mul_f32_e32 v5, v0, v4 ; 0A0A0900 v_mul_f32_e32 v6, v1, v4 ; 0A0C0901 v_trunc_f32_e32 v6, v6 ; 7E0C3906 v_trunc_f32_e32 v5, v5 ; 7E0A3905 v_mad_f32 v0, v0, v4, -v5 ; D1C10000 84160900 v_mad_f32 v1, v1, v4, -v6 ; D1C10001 841A0901 v_mov_b32_e32 v4, 0x41700000 ; 7E0802FF 41700000 v_mad_f32 v0, v0, v4, 0.5 ; D1C10000 03C20900 v_mov_b32_e32 v4, 0x40e00000 ; 7E0802FF 40E00000 v_mad_f32 v1, v1, v4, 0.5 ; D1C10001 03C20901 v_trunc_f32_e32 v1, v1 ; 7E023901 v_trunc_f32_e32 v0, v0 ; 7E003900 v_add_f32_e32 v1, v1, v1 ; 02020301 v_mac_f32_e32 v1, 0x41800000, v0 ; 2C0200FF 41800000 v_mov_b32_e32 v0, 0x3b808081 ; 7E0002FF 3B808081 s_lshr_b32 s1, s0, 8 ; 8F018800 v_mul_f32_e32 v4, v6, v0 ; 0A080106 v_cvt_f32_u32_e32 v6, s1 ; 7E0C0C01 v_cvt_f32_ubyte0_e32 v7, s0 ; 7E0E2200 v_mul_f32_e32 v1, v1, v0 ; 0A020101 v_mul_f32_e32 v5, v5, v0 ; 0A0A0105 v_mul_f32_e32 v6, v6, v0 ; 0A0C0106 v_mul_f32_e32 v0, v7, v0 ; 0A000107 v_cvt_pkrtz_f16_f32 v4, v4, v5 ; D2960004 00020B04 v_cvt_pkrtz_f16_f32 v1, v3, v1 ; D2960001 00020303 v_cvt_pkrtz_f16_f32 v0, v6, v0 ; D2960000 00020106 v_cvt_pkrtz_f16_f32 v2, 0, v2 ; D2960002 00020480 exp mrt0 v4, off, v1, off compr ; C4000405 00000104 exp mrt1 v2, off, v0, off done compr vm ; C4001C15 00000002 s_endpgm ; BF810000 wine: Unhandled page fault on read access to 0x00000000 at address 0x7f2a3f973d43 (thread 00b1), starting debugger... Unhandled exception: page fault on read access to 0x00000000 in 64-bit code (0x00007f2a3f973d43). Register dump: rip:00007f2a3f973d43 rsp:000000003461cc38 rbp:00007f2a30758278 eflags:00010206 ( R- -- I - -P- ) rax:000000000000000b rbx:00007f2a3082dbb8 rcx:00007f2a308875f0 rdx:0000000000000000 rsi:00007f2a30758278 rdi:00007f2a30759fe0 r8:0000000000000000 r9:0000000000000000 r10:00007f2a3082db70 r11:00007f2a62036450 r12:00007f2a30759fe0 r13:00007f2a30445700 r14:0000000000000000 r15:000000003461cc50 Stack dump: 0x000000003461cc38: 00007f2a3f8f6cda 000000003461cc70 0x000000003461cc48: 00007f2a3082db70 000000003461e630 0x000000003461cc58: 6119ea08e9e0e100 0000000034610101 0x000000003461cc68: 000000003461e620 00007f2a30403a40 0x000000003461cc78: 00007f2a30752fb8 0000000034610101 0x000000003461cc88: 000000003461cd50 0000000000000002 0x000000003461cc98: 000000003461e620 00007f2a30759fe0 0x000000003461cca8: 00007f2a30752fb8 000000003461e630 0x000000003461ccb8: 000000003461cd50 0000000000000002 0x000000003461ccc8: 00007f2a507a0b07 202c343176202c36 0x000000003461ccd8: 2020202020343176 2020202020202020 0x000000003461cce8: 2020202020202020 2020202020202020 Backtrace: =>0 0x00007f2a3f973d43 _ZN4llvm10SelectInst18areInvalidOperandsEPNS_5ValueES2_S2_+0x3() in libllvmcore.so.7 (0x00007f2a30758278) 1 0x00007f2a3f8f6cda LLVMBuildSelect+0xb9() in libllvmcore.so.7 (0x00007f2a30758278) 2 0x00007f2a507a0b07 ac_translate_nir_to_llvm+0x1586() in libvulkan_radeon.so (0x00007f2a30759fe0) 3 0x00007f2a507a2135 radv_compile_nir_shader+0x34() in libvulkan_radeon.so (0x000000003461e3c0) 4 0x00007f2a507ab075 shader_variant_create+0x334() in libvulkan_radeon.so (0x0000000000000000) 5 0x00007f2a507ab44a radv_shader_variant_create+0x119() in libvulkan_radeon.so (0x000000003461e534) 6 0x00007f2a507a4232 radv_create_shaders+0xd31() in libvulkan_radeon.so (0x00007f2a441154b0) 7 0x00007f2a507a6f35 radv_pipeline_init.isra+0xb44() in libvulkan_radeon.so (0x000000003461f380) 8 0x00007f2a507a8d80 radv_graphics_pipeline_create+0x8f() in libvulkan_radeon.so (0x00007f2a441154b0) 9 0x00007f2a507a8e3e radv_CreateGraphicsPipelines+0x4d() in libvulkan_radeon.so (0x00007f2a441154b0) 10 0x00007f2a50dfe4f4 wine_vkCreateGraphicsPipelines+0xe3() in winevulkan (0x000000003461f170) 11 0x000000006a415606 in d3d11 (+0xd5605) (0x000000003461f1b0) 12 0x000000006a385bf7 in d3d11 (+0x45bf6) (0x000000003461f240) 13 0x000000006a384caf in d3d11 (+0x44cae) (0x000000003461fa40) 14 0x000000006a37d372 in d3d11 (+0x3d371) (0x000000003461faa0) 15 0x000000006a37eb4d in d3d11 (+0x3eb4c) (0x000000003461fae0) 16 0x000000006a37a1fa in d3d11 (+0x3a1f9) (0x000000003461fb20) 17 0x000000006a349567 in d3d11 (+0x9566) (0x000000003461fb60) 18 0x000000006a357bde in d3d11 (+0x17bdd) (0x000000003461fb90) 19 0x000000006a37f699 in d3d11 (+0x3f698) (0x000000003461fbd0) 20 0x000000006a37fbc7 in d3d11 (+0x3fbc6) (0x000000003461fc60) 21 0x000000006a37f709 in d3d11 (+0x3f708) (0x000000003461fc60) 22 0x000000006a37fe92 in d3d11 (+0x3fe91) (0x000000003461fc90) 23 0x000000006a37fc40 in d3d11 (+0x3fc3f) (0x000000003461fd20) 24 0x000000006a38012b in d3d11 (+0x4012a) (0x000000003461fd00) 25 0x000000006a3800f9 in d3d11 (+0x400f8) (0x000000003461fd30) 26 0x000000006a3800da in d3d11 (+0x400d9) (0x000000003461fd60) 27 0x000000006a4f653f in d3d11 (+0x1b653e) (0x000000003461fdd8) 28 0x000000006a3da884 in d3d11 (+0x9a883) (0x000000003461fdd8) 29 0x000000007bcac689 call_thread_func+0xc8() in ntdll (0x000000003461ffd0) 0x00007f2a3f973d43 _ZN4llvm10SelectInst18areInvalidOperandsEPNS_5ValueES2_S2_+0x3 in libllvmcore.so.7: cmpq (%rdx),%rcx Modules: Module Address Debug info Name (295 modules) PE 260000- 92d000 Deferred ai_x64_f PE 930000- a37000 Deferred dm_x64_f PE a40000- df1000 Deferred rl_x64_f PE e00000- 28be000 Deferred physics_x64_f PE 28c0000- 3028000 Deferred renderer_x64_f PE 3030000- 312c000 Deferred d3d_x64_f PE 3130000- 321f000 Deferred vulkan-1 PE 3220000- 6ade000 Deferred dxgi PE 6ae0000- 6b1b000 Deferred app_x64_f PE 6b20000- 6b3b000 Deferred loc_x64_f PE 6b40000- 6de6000 Deferred snd_x64_f PE 6df0000- 6f0c000 Deferred videostreamer_x64_f PE 9f80000- a105000 Deferred gameoverlayrenderer64 PE ed10000- ee07000 Deferred animationinputlogic_r PE ee10000- ee58000 Deferred particle_simulation_r PE 222c0000- 22392000 Deferred camerasystem_r PE 224b0000- 2253d000 Deferred hud_r PE 22760000- 22c4f000 Deferred wedrendering_r PE 38000000- 38e45000 Deferred steamclient64 PE 3b400000- 3b43f000 Deferred steam_api64 PE 3c440000- 3c88c000 Deferred d3dcompiler_47 PE 3f000000- 3f172000 Deferred tier0_s64 PE 3f600000- 3f679000 Deferred vstdlib_s64 PE 6a340000- 6f5a6000 Dwarf d3d11 ELF 7a800000- 7a9dd000 Deferred opengl32 \-PE 7a850000- 7a9dd000 \ opengl32 ELF 7b400000- 7b809000 Deferred kernel32 \-PE 7b420000- 7b809000 \ kernel32 ELF 7bc00000- 7bd39000 Dwarf ntdll \-PE 7bc40000- 7bd39000 \ ntdll ELF 7c000000- 7c004000 Deferred PE 140000000- 141316000 Deferred quantumbreak PE 180000000- 180064000 Deferred bink2w64 ELF 7f2a234bf000- 7f2a23768000 Deferred libvorbisenc.so.2 ELF 7f2a23768000- 7f2a23994000 Deferred libvorbis.so.0 ELF 7f2a23994000- 7f2a23b9b000 Deferred libogg.so.0 ELF 7f2a23b9b000- 7f2a23df4000 Deferred libflac.so.8 ELF 7f2a23df4000- 7f2a24000000 Deferred libgsm.so.1 ELF 7f2a34105000- 7f2a3431d000 Deferred libnsl.so.1 ELF 7f2a3431d000- 7f2a34522000 Deferred libuuid.so.1 ELF 7f2a34522000- 7f2a34727000 Deferred libcap.so.2 ELF 7f2a34727000- 7f2a3492d000 Deferred libasyncns.so.0 ELF 7f2a3492d000- 7f2a34b9d000 Deferred libsndfile.so.1 ELF 7f2a34b9d000- 7f2a34da8000 Deferred libwrap.so.0 ELF 7f2a34da8000- 7f2a34fae000 Deferred libxtst.so.6 ELF 7f2a34fae000- 7f2a351b6000 Deferred libsm.so.6 ELF 7f2a351b6000- 7f2a353d2000 Deferred libice.so.6 ELF 7f2a353d2000- 7f2a35656000 Deferred libpulsecommon-11.1.so ELF 7f2a35656000- 7f2a358a7000 Deferred libpulse.so.0 ELF 7f2a358c5000- 7f2a358ef000 Deferred xaudio2_8 \-PE 7f2a358d0000- 7f2a358ef000 \ xaudio2_8 ELF 7f2a358ef000- 7f2a3591d000 Deferred winepulse \-PE 7f2a35900000- 7f2a3591d000 \ winepulse ELF 7f2a3591d000- 7f2a35bb8000 Deferred libopenal.so.1 ELF 7f2a35bda000- 7f2a35c00000 Deferred mmdevapi \-PE 7f2a35be0000- 7f2a35c00000 \ mmdevapi ELF 7f2a3c01d000- 7f2a3c049000 Deferred xaudio2_7 \-PE 7f2a3c020000- 7f2a3c049000 \ xaudio2_7 ELF 7f2a3c849000- 7f2a3c863000 Deferred hid \-PE 7f2a3c850000- 7f2a3c863000 \ hid ELF 7f2a3d879000- 7f2a3daa5000 Deferred libtinfo.so.6 ELF 7f2a3de2c000- 7f2a3e02f000 Deferred libxshmfence.so.1 ELF 7f2a3e02f000- 7f2a3e236000 Deferred libxcb-sync.so.1 ELF 7f2a3e236000- 7f2a3e439000 Deferred libxcb-present.so.0 ELF 7f2a3e439000- 7f2a3e641000 Deferred libxcb-xfixes.so.0 ELF 7f2a3e641000- 7f2a3e844000 Deferred libxcb-dri3.so.0 ELF 7f2a3e844000- 7f2a3ea46000 Deferred libx11-xcb.so.1 ELF 7f2a3ea46000- 7f2a3ec58000 Deferred libdrm.so.2 ELF 7f2a3ec58000- 7f2a3ee62000 Deferred libdrm_amdgpu.so.1 ELF 7f2a3ee62000- 7f2a3f07a000 Deferred libelf.so.1 ELF 7f2a3f07a000- 7f2a3f295000 Deferred libllvmdemangle.so.7 ELF 7f2a3f295000- 7f2a3f5e6000 Deferred libllvmsupport.so.7 ELF 7f2a3f5e6000- 7f2a3f7f8000 Deferred libllvmbinaryformat.so.7 ELF 7f2a3f7f8000- 7f2a3fdd5000 Dwarf libllvmcore.so.7 ELF 7f2a3fdd5000- 7f2a3ffe9000 Deferred libllvmdebuginfomsf.so.7 ELF 7f2a3ffe9000- 7f2a4029e000 Deferred libllvmdebuginfocodeview.so.7 ELF 7f2a4029e000- 7f2a40589000 Deferred libllvmmc.so.7 ELF 7f2a40589000- 7f2a407ca000 Deferred libllvmamdgpuutils.so.7 ELF 7f2a407ca000- 7f2a40a0e000 Deferred libllvmamdgpuasmprinter.so.7 ELF 7f2a40a0e000- 7f2a40c10000 Deferred libllvmamdgpuinfo.so.7 ELF 7f2a40c10000- 7f2a41058000 Deferred libllvmamdgpudesc.so.7 ELF 7f2a41058000- 7f2a412a0000 Deferred libllvmmcparser.so.7 ELF 7f2a412a0000- 7f2a41593000 Deferred libllvmamdgpuasmparser.so.7 ELF 7f2a41593000- 7f2a41808000 Deferred libllvmbitreader.so.7 ELF 7f2a41808000- 7f2a41ae5000 Deferred libllvmobject.so.7 ELF 7f2a41ae5000- 7f2a41d41000 Deferred libllvmprofiledata.so.7 ELF 7f2a41d41000- 7f2a42428000 Deferred libllvmanalysis.so.7 ELF 7f2a42428000- 7f2a42680000 Deferred libllvmbitwriter.so.7 ELF 7f2a42680000- 7f2a42b24000 Deferred libllvmtransformutils.so.7 ELF 7f2a42b24000- 7f2a42d3f000 Deferred libllvmaggressiveinstcombine.so.7 ELF 7f2a42d3f000- 7f2a43059000 Deferred libllvminstcombine.so.7 ELF 7f2a43059000- 7f2a43737000 Deferred libllvmscalaropts.so.7 ELF 7f2a43737000- 7f2a44000000 Deferred libllvmcodegen.so.7 ELF 7f2a4812f000- 7f2a4833e000 Deferred libllvmtarget.so.7 ELF 7f2a4833e000- 7f2a48649000 Deferred libllvmasmprinter.so.7 ELF 7f2a48649000- 7f2a488a8000 Deferred libllvmasmparser.so.7 ELF 7f2a488a8000- 7f2a48ab0000 Deferred libllvmirreader.so.7 ELF 7f2a48ab0000- 7f2a48cde000 Deferred libllvmlinker.so.7 ELF 7f2a48cde000- 7f2a48ff5000 Deferred libllvmvectorize.so.7 ELF 7f2a48ff5000- 7f2a49315000 Deferred libllvminstrumentation.so.7 ELF 7f2a49315000- 7f2a496dd000 Deferred libllvmipo.so.7 ELF 7f2a496dd000- 7f2a49bfb000 Deferred libllvmselectiondag.so.7 ELF 7f2a49bfb000- 7f2a49e8a000 Deferred libllvmglobalisel.so.7 ELF 7f2a49e8a000- 7f2a4a43e000 Deferred libllvmamdgpucodegen.so.7 ELF 7f2a4a43e000- 7f2a4a645000 Deferred libllvmmcdisassembler.so.7 ELF 7f2a4a645000- 7f2a4a878000 Deferred libllvmamdgpudisassembler.so.7 ELF 7f2a4a878000- 7f2a4aafd000 Deferred libllvmruntimedyld.so.7 ELF 7f2a4aafd000- 7f2a4ad26000 Deferred libllvmexecutionengine.so.7 ELF 7f2a4ad26000- 7f2a4af38000 Deferred libllvmmcjit.so.7 ELF 7f2a4af38000- 7f2a4b13e000 Deferred libllvmx86utils.so.7 ELF 7f2a4b13e000- 7f2a4b398000 Deferred libllvmx86asmprinter.so.7 ELF 7f2a4b398000- 7f2a4b59a000 Deferred libllvmx86info.so.7 ELF 7f2a4b59a000- 7f2a4ba0b000 Deferred libllvmx86desc.so.7 ELF 7f2a4ba0b000- 7f2a4c000000 Deferred libllvmx86codegen.so.7 ELF 7f2a50030000- 7f2a502d8000 Deferred libllvmx86asmparser.so.7 ELF 7f2a502d8000- 7f2a5066f000 Deferred libllvmx86disassembler.so.7 ELF 7f2a50729000- 7f2a50b45000 Dwarf libvulkan_radeon.so ELF 7f2a50b45000- 7f2a50d91000 Deferred libvulkan.so.1 ELF 7f2a50dd9000- 7f2a50e11000 Dwarf winevulkan \-PE 7f2a50de0000- 7f2a50e11000 \ winevulkan ELF 7f2a51401000- 7f2a5141a000 Deferred xinput1_4 \-PE 7f2a51410000- 7f2a5141a000 \ xinput1_4 ELF 7f2a5141a000- 7f2a51435000 Deferred kerberos \-PE 7f2a51420000- 7f2a51435000 \ kerberos ELF 7f2a51435000- 7f2a5146b000 Deferred netapi32 \-PE 7f2a51440000- 7f2a5146b000 \ netapi32 ELF 7f2a5146b000- 7f2a514a8000 Deferred secur32 \-PE 7f2a51470000- 7f2a514a8000 \ secur32 ELF 7f2a514a8000- 7f2a514bd000 Deferred mswsock \-PE 7f2a514b0000- 7f2a514bd000 \ mswsock ELF 7f2a514bd000- 7f2a51633000 Deferred oleaut32 \-PE 7f2a514e0000- 7f2a51633000 \ oleaut32 ELF 7f2a51633000- 7f2a516a1000 Deferred dbghelp \-PE 7f2a51640000- 7f2a516a1000 \ dbghelp ELF 7f2a516a1000- 7f2a516bd000 Deferred imagehlp \-PE 7f2a516b0000- 7f2a516bd000 \ imagehlp ELF 7f2a516bd000- 7f2a517a0000 Deferred crypt32 \-PE 7f2a516d0000- 7f2a517a0000 \ crypt32 ELF 7f2a517a0000- 7f2a517b5000 Deferred api-ms-win-core-sysinfo-l1-2-1 \-PE 7f2a517b0000- 7f2a517b5000 \ api-ms-win-core-sysinfo-l1-2-1 ELF 7f2a517b5000- 7f2a519ba000 Deferred libtxc_dxtn.so ELF 7f2a519c5000- 7f2a519d9000 Deferred psapi \-PE 7f2a519d0000- 7f2a519d9000 \ psapi ELF 7f2a519d9000- 7f2a519ee000 Deferred api-ms-win-core-localization-l1-2-1 \-PE 7f2a519e0000- 7f2a519ee000 \ api-ms-win-core-localization-l1-2-1 ELF 7f2a519ee000- 7f2a51a02000 Deferred api-ms-win-core-fibers-l1-1-1 \-PE 7f2a519f0000- 7f2a51a02000 \ api-ms-win-core-fibers-l1-1-1 ELF 7f2a51a02000- 7f2a51c17000 Deferred libgpg-error.so.0 ELF 7f2a51c17000- 7f2a51e2c000 Deferred liblz4.so.1 ELF 7f2a51e2c000- 7f2a52052000 Deferred liblzma.so.5 ELF 7f2a52052000- 7f2a5225a000 Deferred librt.so.1 ELF 7f2a5225a000- 7f2a52574000 Deferred libgcrypt.so.20 ELF 7f2a52574000- 7f2a527f6000 Deferred libpcre2-8.so.0 ELF 7f2a527f6000- 7f2a52a80000 Deferred libsystemd.so.0 ELF 7f2a52a80000- 7f2a52c88000 Deferred libffi.so.6 ELF 7f2a52c88000- 7f2a52eb1000 Deferred libselinux.so.1 ELF 7f2a52eb1000- 7f2a530b4000 Deferred libfreebl3.so ELF 7f2a530b4000- 7f2a53305000 Deferred libdbus-1.so.3 ELF 7f2a53305000- 7f2a5357d000 Deferred libgmp.so.10 ELF 7f2a5357d000- 7f2a537ab000 Deferred libhogweed.so.4 ELF 7f2a537ab000- 7f2a539e3000 Deferred libnettle.so.6 ELF 7f2a539e3000- 7f2a53bf6000 Deferred libtasn1.so.6 ELF 7f2a53bf6000- 7f2a53f76000 Deferred libunistring.so.2 ELF 7f2a53f76000- 7f2a54193000 Deferred libidn2.so.0 ELF 7f2a54193000- 7f2a544c0000 Deferred libp11-kit.so.0 ELF 7f2a544c0000- 7f2a546c4000 Deferred libkeyutils.so.1 ELF 7f2a546c4000- 7f2a54b4c000 Deferred libcrypto.so.1.1 ELF 7f2a54b4c000- 7f2a54d5b000 Deferred libkrb5support.so.0 ELF 7f2a54d5b000- 7f2a54f91000 Deferred libcrypt.so.1 ELF 7f2a54f91000- 7f2a551a2000 Deferred libavahi-client.so.3 ELF 7f2a551a2000- 7f2a553af000 Deferred libavahi-common.so.3 ELF 7f2a553af000- 7f2a5571f000 Deferred libgnutls.so.30 ELF 7f2a5571f000- 7f2a55923000 Deferred libcom_err.so.2 ELF 7f2a55923000- 7f2a55b3e000 Deferred libk5crypto.so.3 ELF 7f2a55b3e000- 7f2a55e25000 Deferred libkrb5.so.3 ELF 7f2a55e25000- 7f2a56072000 Deferred libgssapi_krb5.so.2 ELF 7f2a56072000- 7f2a56306000 Deferred libcups.so.2 ELF 7f2a56319000- 7f2a5632e000 Deferred api-ms-win-core-synch-l1-2-0 \-PE 7f2a56320000- 7f2a5632e000 \ api-ms-win-core-synch-l1-2-0 ELF 7f2a5632e000- 7f2a5634e000 Deferred concrt140 \-PE 7f2a56330000- 7f2a5634e000 \ concrt140 ELF 7f2a5634e000- 7f2a56554000 Deferred libxfixes.so.3 ELF 7f2a56554000- 7f2a5675f000 Deferred libxcursor.so.1 ELF 7f2a56768000- 7f2a567a5000 Deferred uxtheme \-PE 7f2a56770000- 7f2a567a5000 \ uxtheme ELF 7f2a56825000- 7f2a56a57000 Deferred libexpat.so.1 ELF 7f2a56a57000- 7f2a56c9c000 Deferred libfontconfig.so.1 ELF 7f2a56c9c000- 7f2a56eb3000 Deferred libz.so.1 ELF 7f2a56eb3000- 7f2a570e6000 Deferred libpng16.so.16 ELF 7f2a570e6000- 7f2a572f7000 Deferred libbz2.so.1 ELF 7f2a572f7000- 7f2a575ac000 Deferred libfreetype.so.6 ELF 7f2a575ac000- 7f2a577bd000 Deferred libxi.so.6 ELF 7f2a577bd000- 7f2a579c0000 Deferred libxcomposite.so.1 ELF 7f2a579c0000- 7f2a57bcb000 Deferred libxrandr.so.2 ELF 7f2a57bcb000- 7f2a57dd5000 Deferred libxrender.so.1 ELF 7f2a57dd5000- 7f2a57fdb000 Deferred libxxf86vm.so.1 ELF 7f2a57fdb000- 7f2a581de000 Deferred libxinerama.so.1 ELF 7f2a581de000- 7f2a583e2000 Deferred libxau.so.6 ELF 7f2a583e2000- 7f2a5860a000 Deferred libxcb.so.1 ELF 7f2a5860a000- 7f2a58948000 Deferred libx11.so.6 ELF 7f2a58948000- 7f2a58b5a000 Deferred libxext.so.6 ELF 7f2a58ba2000- 7f2a58c44000 Deferred winex11 \-PE 7f2a58bb0000- 7f2a58c44000 \ winex11 ELF 7f2a58c44000- 7f2a58c71000 Deferred msvfw32 \-PE 7f2a58c50000- 7f2a58c71000 \ msvfw32 ELF 7f2a58c71000- 7f2a58c9e000 Deferred msacm32 \-PE 7f2a58c80000- 7f2a58c9e000 \ msacm32 ELF 7f2a58c9e000- 7f2a58cf7000 Deferred avifil32 \-PE 7f2a58cb0000- 7f2a58cf7000 \ avifil32 ELF 7f2a58cf7000- 7f2a58d19000 Deferred bcrypt \-PE 7f2a58d00000- 7f2a58d19000 \ bcrypt ELF 7f2a58d19000- 7f2a58d2e000 Deferred api-ms-win-crt-filesystem-l1-1-0 \-PE 7f2a58d20000- 7f2a58d2e000 \ api-ms-win-crt-filesystem-l1-1-0 ELF 7f2a58d2e000- 7f2a58d42000 Deferred api-ms-win-crt-locale-l1-1-0 \-PE 7f2a58d30000- 7f2a58d42000 \ api-ms-win-crt-locale-l1-1-0 ELF 7f2a58d42000- 7f2a58d70000 Deferred mfplat \-PE 7f2a58d50000- 7f2a58d70000 \ mfplat ELF 7f2a58d70000- 7f2a58e39000 Deferred msvcrt \-PE 7f2a58d90000- 7f2a58e39000 \ msvcrt ELF 7f2a58e39000- 7f2a58eb4000 Deferred setupapi \-PE 7f2a58e50000- 7f2a58eb4000 \ setupapi ELF 7f2a58eb4000- 7f2a58ece000 Deferred cfgmgr32 \-PE 7f2a58ec0000- 7f2a58ece000 \ cfgmgr32 ELF 7f2a58ece000- 7f2a5903f000 Deferred wined3d \-PE 7f2a58ef0000- 7f2a5903f000 \ wined3d ELF 7f2a5903f000- 7f2a5908d000 Deferred d3d9 \-PE 7f2a59050000- 7f2a5908d000 \ d3d9 ELF 7f2a5908d000- 7f2a590a2000 Deferred api-ms-win-crt-time-l1-1-0 \-PE 7f2a59090000- 7f2a590a2000 \ api-ms-win-crt-time-l1-1-0 ELF 7f2a590a2000- 7f2a590bc000 Deferred api-ms-win-crt-math-l1-1-0 \-PE 7f2a590b0000- 7f2a590bc000 \ api-ms-win-crt-math-l1-1-0 ELF 7f2a590bc000- 7f2a590d1000 Deferred api-ms-win-crt-heap-l1-1-0 \-PE 7f2a590c0000- 7f2a590d1000 \ api-ms-win-crt-heap-l1-1-0 ELF 7f2a590d1000- 7f2a590e7000 Deferred api-ms-win-crt-runtime-l1-1-0 \-PE 7f2a590e0000- 7f2a590e7000 \ api-ms-win-crt-runtime-l1-1-0 ELF 7f2a590e7000- 7f2a590fd000 Deferred api-ms-win-crt-stdio-l1-1-0 \-PE 7f2a590f0000- 7f2a590fd000 \ api-ms-win-crt-stdio-l1-1-0 ELF 7f2a590fd000- 7f2a59113000 Deferred api-ms-win-crt-convert-l1-1-0 \-PE 7f2a59100000- 7f2a59113000 \ api-ms-win-crt-convert-l1-1-0 ELF 7f2a59113000- 7f2a5932a000 Deferred libresolv.so.2 ELF 7f2a5932f000- 7f2a59344000 Deferred api-ms-win-crt-utility-l1-1-0 \-PE 7f2a59330000- 7f2a59344000 \ api-ms-win-crt-utility-l1-1-0 ELF 7f2a59344000- 7f2a5935b000 Deferred api-ms-win-crt-string-l1-1-0 \-PE 7f2a59350000- 7f2a5935b000 \ api-ms-win-crt-string-l1-1-0 ELF 7f2a5935b000- 7f2a59372000 Deferred vcruntime140 \-PE 7f2a59360000- 7f2a59372000 \ vcruntime140 ELF 7f2a59372000- 7f2a593a1000 Deferred iphlpapi \-PE 7f2a59380000- 7f2a593a1000 \ iphlpapi ELF 7f2a593a1000- 7f2a594a3000 Deferred msvcr120 \-PE 7f2a593d0000- 7f2a594a3000 \ msvcr120 ELF 7f2a594a3000- 7f2a595b2000 Deferred ucrtbase \-PE 7f2a594d0000- 7f2a595b2000 \ ucrtbase ELF 7f2a595b2000- 7f2a596ed000 Deferred msvcp140 \-PE 7f2a595f0000- 7f2a596ed000 \ msvcp140 ELF 7f2a596ed000- 7f2a5972f000 Deferred ws2_32 \-PE 7f2a59700000- 7f2a5972f000 \ ws2_32 ELF 7f2a5972f000- 7f2a59777000 Deferred winspool \-PE 7f2a59740000- 7f2a59777000 \ winspool ELF 7f2a59777000- 7f2a5979e000 Deferred imm32 \-PE 7f2a59780000- 7f2a5979e000 \ imm32 ELF 7f2a5979e000- 7f2a597ec000 Deferred usp10 \-PE 7f2a597b0000- 7f2a597ec000 \ usp10 ELF 7f2a597ec000- 7f2a59937000 Deferred comctl32 \-PE 7f2a59800000- 7f2a59937000 \ comctl32 ELF 7f2a59937000- 7f2a599c1000 Deferred shlwapi \-PE 7f2a59950000- 7f2a599c1000 \ shlwapi ELF 7f2a599c1000- 7f2a59d24000 Deferred shell32 \-PE 7f2a599e0000- 7f2a59d24000 \ shell32 ELF 7f2a59d24000- 7f2a59e22000 Deferred comdlg32 \-PE 7f2a59d30000- 7f2a59e22000 \ comdlg32 ELF 7f2a59e22000- 7f2a59eb6000 Deferred rpcrt4 \-PE 7f2a59e30000- 7f2a59eb6000 \ rpcrt4 ELF 7f2a59eb6000- 7f2a5a044000 Deferred ole32 \-PE 7f2a59ee0000- 7f2a5a044000 \ ole32 ELF 7f2a5a044000- 7f2a5a108000 Deferred winmm \-PE 7f2a5a050000- 7f2a5a108000 \ winmm ELF 7f2a5a108000- 7f2a5a195000 Deferred advapi32 \-PE 7f2a5a120000- 7f2a5a195000 \ advapi32 ELF 7f2a5a195000- 7f2a5a30e000 Deferred gdi32 \-PE 7f2a5a1b0000- 7f2a5a30e000 \ gdi32 ELF 7f2a5a40e000- 7f2a5a66b000 Deferred user32 \-PE 7f2a5a430000- 7f2a5a66b000 \ user32 ELF 7f2a5a76b000- 7f2a5a97d000 Deferred libnss_files.so.2 ELF 7f2a6174c000- 7f2a61963000 Deferred libgcc_s.so.1 ELF 7f2a61963000- 7f2a61cae000 Deferred libm.so.6 ELF 7f2a61cb0000- 7f2a61eb4000 Deferred libdl.so.2 ELF 7f2a61eb4000- 7f2a6226a000 Deferred libc.so.6 ELF 7f2a6226a000- 7f2a62488000 Deferred libpthread.so.0 ELF 7f2a62499000- 7f2a624b5000 Deferred aclui \-PE 7f2a624a0000- 7f2a624b5000 \ aclui ELF 7f2a624b5000- 7f2a624d0000 Deferred version \-PE 7f2a624c0000- 7f2a624d0000 \ version ELF 7f2a624d0000- 7f2a62894000 Dwarf libwine.so.1 ELF 7f2a62896000- 7f2a62abd000 Deferred ld-linux-x86-64.so.2 ELF 7ffd9eacb000- 7ffd9eacc000 Deferred [vdso].so Threads: process tid prio (all id:s are in hex) 0000000e services.exe [C:\windows\system32\services.exe] 00000033 0 00000030 0 0000002b 0 00000023 0 0000001f 0 00000012 0 0000000f 0 00000010 explorer.exe [C:\windows\system32\explorer.exe /desktop] 00000037 0 00000027 0 00000026 0 00000022 0 00000011 0 0000001d winedevice.exe [C:\windows\system32\winedevice.exe] 00000028 0 00000021 0 00000020 0 0000001e 0 00000029 plugplay.exe [C:\windows\system32\plugplay.exe] 0000002d 0 0000002c 0 0000002a 0 0000002e winedevice.exe [C:\windows\system32\winedevice.exe] 00000038 0 00000036 0 00000032 0 00000031 0 0000002f 0 0000003b steam.exe [F:\LAURA_LINIX_STEAM\Steam\steam.exe -no-dwrite -no-cef-sandbox -applaunch 474960] 00000086 0 00000083 0 00000082 0 00000077 0 00000076 0 00000073 0 00000072 0 00000071 0 00000070 0 0000006d 0 0000006c 0 00000069 0 00000068 0 00000067 0 00000066 0 00000065 0 00000064 0 00000062 1 00000061 1 0000005e 0 0000005c 0 0000005b 0 00000046 0 00000045 0 00000044 0 00000043 0 00000040 0 0000003f 0 0000003e 0 0000003d 0 0000003c 0 00000041 steamwebhelper.exe [F:\LAURA_LINIX_STEAM\Steam\bin\cef\cef.winxp\steamwebhelper.exe "-lang=it_IT" "-cachedir=C:\users\laura\Local Settings\Application Data\Steam\htmlcache" "-steampid=59" "-buildid=1526683293" "-steamid=0" "-clientui=F:\LAURA_LINIX_STEAM\Steam\clientui" --disable-spell-checking --disable-out-of-process-pac --disable-smooth-scrolling --disable-gpu-compositing --disable-gpu --disable-direct-write --no-sandbox "--log-file=F:\LAURA_LINIX_STEAM\Steam\logs\cef_log.txt"] 00000084 0 0000005a 0 00000059 0 00000058 0 00000057 0 00000056 0 00000055 0 00000054 0 00000053 0 00000052 0 00000051 0 00000050 0 0000004f 0 0000004e 0 0000004d 0 0000004c 0 0000004b 0 0000004a 0 00000049 0 00000048 0 00000047 0 00000042 0 00000096 (D) Z:\run\media\laura\delta\LAURA_LINIX_STEAM_2\steamapps\common\QuantumBreak\dx11\QuantumBreak.exe [Z:\run\media\laura\delta\LAURA_LINIX_STEAM_2\steamapps\common\QuantumBreak\dx11\QuantumBreak.exe] 000000ca 0 000000c8 0 000000c7 0 000000c6 0 000000c5 1 000000c4 0 000000c3 15 000000c2 0 000000c1 0 000000c0 1 000000bf 0 000000be 1 000000bd 0 000000bc 0 000000bb 0 000000ba 0 000000b9 0 000000b8 0 000000b7 0 000000b6 0 000000b5 0 000000b4 0 000000b3 0 000000b2 -1 000000b1 0 <== 000000b0 0 000000af 0 000000ae 0 000000ad 2 000000ac 0 000000ab 0 000000aa 0 000000a9 0 000000a8 -1 000000a7 -1 000000a6 -1 000000a5 -2 000000a4 -2 000000a3 -2 000000a2 -2 000000a1 -2 000000a0 -2 0000009f -2 0000009e 0 00000097 0 System information: Wine build: wine-3.9 (Staging) Platform: x86_64 Version: Windows 7 Host system: Linux Host version: 4.16.12-200.fc27.x86_64 AL lib: (EE) ReleaseThreadCtx: Context 0x7d7ea3a0 current for thread being destroyed, possible leak!