diff --git a/src/via_display.c b/src/via_display.c
index 79887fa..2966565 100644
--- a/src/via_display.c
+++ b/src/via_display.c
@@ -952,6 +952,17 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
      *               11: Clock on/off according to each engine IDLE status */
     ViaSeqMask(hwp, 0x3F, 0xFF, 0xFF);
 
+    /* Frame buffer size and GTI for
+     * VX800, VX855, and VX900 chipsets.*/
+    if ((pVia->Chipset == VIA_VX800) ||
+        (pVia->Chipset == VIA_VX855) ||
+        (pVia->Chipset == VIA_VX900)) {
+        ViaSeqMask(hwp, 0x14, pVIADisplay->originalSR14, 0xFF);
+        ViaSeqMask(hwp, 0x68, pVIADisplay->originalSR68, 0xFF);
+        ViaSeqMask(hwp, 0x6D, pVIADisplay->originalSR6D, 0xFF);
+        ViaSeqMask(hwp, 0x6E, pVIADisplay->originalSR6E, 0xFF);
+    }
+
     /* 3X5.36[7]   - DPMS VSYNC Output
      * 3X5.36[6]   - DPMS HSYNC Output
      * 3X5.36[5:4] - DPMS Control
diff --git a/src/via_ums.c b/src/via_ums.c
index 9b0e3d8..319ffab 100644
--- a/src/via_ums.c
+++ b/src/via_ums.c
@@ -1083,6 +1083,17 @@ umsCrtcInit(ScrnInfoPtr pScrn)
     int max_pitch, max_height;
     xf86CrtcPtr iga1, iga2;
 
+    /* Frame buffer size and GTI for
+     * VX800, VX855, and VX900 chipsets.*/
+    if ((pVia->Chipset == VIA_VX800) ||
+        (pVia->Chipset == VIA_VX855) ||
+        (pVia->Chipset == VIA_VX900)) {
+        pVIADisplay->originalSR14 = hwp->readSeq(hwp, 0x14);
+        pVIADisplay->originalSR68 = hwp->readSeq(hwp, 0x68);
+        pVIADisplay->originalSR6D = hwp->readSeq(hwp, 0x6D);
+        pVIADisplay->originalSR6E = hwp->readSeq(hwp, 0x6E);
+    }
+
     /* 3X5.3B through 3X5.3F are scratch pad registers. */
     pVIADisplay->originalCR3B = hwp->readCrtc(hwp, 0x3B);
     pVIADisplay->originalCR3C = hwp->readCrtc(hwp, 0x3C);
diff --git a/src/via_ums.h b/src/via_ums.h
index 14fb18e..27428cb 100644
--- a/src/via_ums.h
+++ b/src/via_ums.h
@@ -223,6 +223,14 @@ typedef struct _VIADISPLAY {
     /* OLPC XO-1.5 */
     Bool                isOLPCXO15;
 
+    /* Shadow copy of the frame buffer size of
+     * VX800, VX855, and VX900 chipsets. */
+    CARD8       originalSR14;
+
+    /* Shadow copy of GTI registers of
+     * VX800, VX855, and VX900 chipsets.*/
+    CARD8       originalSR68, originalSR6D, originalSR6E;
+
     /* Shadow copy of CR3B through CR3F. */
     CARD8       originalCR3B, originalCR3C, originalCR3D,
                 originalCR3E, originalCR3F;