From 18bf888c518a9a47f7c3585700548a2259cef12f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Thu, 14 Jun 2018 17:12:56 +0200 Subject: [PATCH] drm/amdgpu: Add debugging output related to bogus pin_size values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michel Dänzer --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 68 ++++++++++++++++++++-- 1 file changed, 62 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 512f59836436..7a8fa37dd074 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -67,6 +67,14 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) { struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); + int i; + + for (i = 0; i < bo->placement.num_placement; i++) { + if (bo->placements[i].flags & TTM_PL_FLAG_NO_EVICT) { + DRM_WARN_ONCE("Destroying pinned BO of size %lu\n", + amdgpu_bo_size(bo)); + } + } if (bo->kfd_bo) amdgpu_amdkfd_unreserve_system_memory_limit(bo); @@ -917,10 +925,34 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); if (domain == AMDGPU_GEM_DOMAIN_VRAM) { - adev->vram_pin_size += amdgpu_bo_size(bo); - adev->invisible_pin_size += amdgpu_vram_mgr_bo_invisible_size(bo); + u64 old, old_invisible; + u64 new, new_invisible; + + old = adev->vram_pin_size; + old_invisible = adev->invisible_pin_size; + new = adev->vram_pin_size += amdgpu_bo_size(bo); + new_invisible = adev->invisible_pin_size += amdgpu_vram_mgr_bo_invisible_size(bo); + + if (new != old + amdgpu_bo_size(bo)) { + DRM_WARN_ONCE("VRAM new = %llu != %llu + %lu\n", + new, old, amdgpu_bo_size(bo)); + } + + if (new_invisible != old_invisible + amdgpu_vram_mgr_bo_invisible_size(bo)) { + DRM_WARN_ONCE("new_invisible = %llu != %llu + %llu\n", + new_invisible, old_invisible, + amdgpu_vram_mgr_bo_invisible_size(bo)); + } } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { - adev->gart_pin_size += amdgpu_bo_size(bo); + u64 old, new; + + old = adev->gart_pin_size; + new = adev->gart_pin_size += amdgpu_bo_size(bo); + + if (new != old + amdgpu_bo_size(bo)) { + DRM_WARN_ONCE("GART new = %llu != %llu + %lu\n", + new, old, amdgpu_bo_size(bo)); + } } error: @@ -970,10 +1002,34 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo) return 0; if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { - adev->vram_pin_size -= amdgpu_bo_size(bo); - adev->invisible_pin_size -= amdgpu_vram_mgr_bo_invisible_size(bo); + u64 old, old_invisible; + u64 new, new_invisible; + + old = adev->vram_pin_size; + old_invisible = adev->invisible_pin_size; + new = adev->vram_pin_size -= amdgpu_bo_size(bo); + new_invisible = adev->invisible_pin_size -= amdgpu_vram_mgr_bo_invisible_size(bo); + + if (new != old - amdgpu_bo_size(bo)) { + DRM_WARN_ONCE("new = %llu != %llu - %lu\n", new, old, + amdgpu_bo_size(bo)); + } + + if (new_invisible != old_invisible - amdgpu_vram_mgr_bo_invisible_size(bo)) { + DRM_WARN_ONCE("new_invisible = %llu != %llu - %llu\n", + new_invisible, old_invisible, + amdgpu_vram_mgr_bo_invisible_size(bo)); + } } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { - adev->gart_pin_size -= amdgpu_bo_size(bo); + u64 old, new; + + old = adev->gart_pin_size; + new = adev->gart_pin_size -= amdgpu_bo_size(bo); + + if (new != old - amdgpu_bo_size(bo)) { + DRM_WARN_ONCE("GART new = %llu != %llu - %lu\n", + new, old, amdgpu_bo_size(bo)); + } } for (i = 0; i < bo->placement.num_placement; i++) { -- 2.17.1