==============================================================
   Mesa 18.1.4: src/gallium/drivers/llvmpipe/test-suite.log
==============================================================

# TOTAL: 5
# PASS:  1
# SKIP:  0
# XFAIL: 0
# FAIL:  4
# XPASS: 0
# ERROR: 0

.. contents:: :depth: 2

FAIL: lp_test_format
====================


define void @fetch_b8g8r8a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 24, i32 16, i32 8, i32 0>
  %11 = and <4 x i32> %10, <i32 255, i32 255, i32 255, i32 255>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "llc [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>] -o - ir_test_module_float.bc"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: 970
fetch_b8g8r8a8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B8G8R8A8_UNORM (float) ...
FAIL lp_test_format (exit status: 132)

FAIL: lp_test_arit
==================


; Function Attrs: nounwind readnone speculatable
declare float @llvm.fabs.f32(float) #0

define void @abs.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = call float @llvm.fabs.f32(float %2) #1
  store float %3, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "llc [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>] -o - ir_test_module.bc"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: 970
abs.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0

define void @abs.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1
  store <2 x float> %3, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "llc [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>] -o - ir_test_module.bc"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: 970
abs.v2:
     0:	invalid


FAIL lp_test_arit (exit status: 132)

FAIL: lp_test_blend
===================


; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0

define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) {
entry:
  %src = load <16 x i8>, <16 x i8>* %0
  %src1 = load <16 x i8>, <16 x i8>* %1
  %dst = load <16 x i8>, <16 x i8>* %2
  %const = load <16 x i8>, <16 x i8>* %3
  %5 = and <16 x i8> %src, <i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1>
  %6 = bitcast <16 x i8> %5 to <4 x i32>
  %7 = shl <4 x i32> %6, <i32 8, i32 8, i32 8, i32 8>
  %8 = or <4 x i32> %6, %7
  %9 = shl <4 x i32> %8, <i32 16, i32 16, i32 16, i32 16>
  %10 = or <4 x i32> %8, %9
  %11 = bitcast <4 x i32> %10 to <16 x i8>
  %12 = xor <16 x i8> %src, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
  %13 = select <16 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true>, <16 x i8> %12, <16 x i8> %src1
  %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
  %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
  %16 = bitcast <16 x i8> %14 to <8 x i16>
  %17 = bitcast <16 x i8> %15 to <8 x i16>
  %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
  %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
  %20 = bitcast <16 x i8> %18 to <8 x i16>
  %21 = bitcast <16 x i8> %19 to <8 x i16>
  %22 = mul <8 x i16> %16, %20
  %23 = lshr <8 x i16> %22, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %24 = add <8 x i16> %22, %23
  %25 = add <8 x i16> %24, <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>
  %26 = lshr <8 x i16> %25, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %27 = mul <8 x i16> %17, %21
  %28 = lshr <8 x i16> %27, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %29 = add <8 x i16> %27, %28
  %30 = add <8 x i16> %29, <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>
  %31 = lshr <8 x i16> %30, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1
  %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
  %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
  %35 = bitcast <16 x i8> %33 to <8 x i16>
  %36 = bitcast <16 x i8> %34 to <8 x i16>
  %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
  %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
  %39 = bitcast <16 x i8> %37 to <8 x i16>
  %40 = bitcast <16 x i8> %38 to <8 x i16>
  %41 = mul <8 x i16> %35, %39
  %42 = lshr <8 x i16> %41, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %43 = add <8 x i16> %41, %42
  %44 = add <8 x i16> %43, <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>
  %45 = lshr <8 x i16> %44, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %46 = mul <8 x i16> %36, %40
  %47 = lshr <8 x i16> %46, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %48 = add <8 x i16> %46, %47
  %49 = add <8 x i16> %48, <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>
  %50 = lshr <8 x i16> %49, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1
  %52 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %32, <16 x i8> %51) #1
  %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
  %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
  %55 = bitcast <16 x i8> %53 to <8 x i16>
  %56 = bitcast <16 x i8> %54 to <8 x i16>
  %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
  %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
  %59 = bitcast <16 x i8> %57 to <8 x i16>
  %60 = bitcast <16 x i8> %58 to <8 x i16>
  %61 = mul <8 x i16> %55, %59
  %62 = lshr <8 x i16> %61, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %63 = add <8 x i16> %61, %62
  %64 = add <8 x i16> %63, <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>
  %65 = lshr <8 x i16> %64, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %66 = mul <8 x i16> %56, %60
  %67 = lshr <8 x i16> %66, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %68 = add <8 x i16> %66, %67
  %69 = add <8 x i16> %68, <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>
  %70 = lshr <8 x i16> %69, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1
  %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
  %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
  %74 = bitcast <16 x i8> %72 to <8 x i16>
  %75 = bitcast <16 x i8> %73 to <8 x i16>
  %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
  %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
  %78 = bitcast <16 x i8> %76 to <8 x i16>
  %79 = bitcast <16 x i8> %77 to <8 x i16>
  %80 = mul <8 x i16> %74, %78
  %81 = lshr <8 x i16> %80, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %82 = add <8 x i16> %80, %81
  %83 = add <8 x i16> %82, <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>
  %84 = lshr <8 x i16> %83, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %85 = mul <8 x i16> %75, %79
  %86 = lshr <8 x i16> %85, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %87 = add <8 x i16> %85, %86
  %88 = add <8 x i16> %87, <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>
  %89 = lshr <8 x i16> %88, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
  %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1
  %91 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %71, <16 x i8> %90) #1
  %res = select <16 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true>, <16 x i8> %91, <16 x i8> %52
  store <16 x i8> %res, <16 x i8>* %4
  ret void
}

ir_test_module.bc written
Invoke as "llc [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>] -o - ir_test_module.bc"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: 970
test:
     0:	invalid


FAIL lp_test_blend (exit status: 132)

FAIL: lp_test_conv
==================


define void @test(<4 x i32>*, <4 x i32>*) {
entry:
  %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0
  %3 = load <4 x i32>, <4 x i32>* %2
  %4 = lshr <4 x i32> %3, <i32 16, i32 16, i32 16, i32 16>
  %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0
  store <4 x i32> %4, <4 x i32>* %5
  ret void
}

ir_test_module.bc written
Invoke as "llc [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>] -o - ir_test_module.bc"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: 970
test:
     0:	invalid


FAIL lp_test_conv (exit status: 132)