FRAG PROPERTY FS_COORD_ORIGIN UPPER_LEFT PROPERTY FS_COORD_PIXEL_CENTER INTEGER DCL IN[0], TEXCOORD[0], PERSPECTIVE DCL IN[1], TEXCOORD[1], PERSPECTIVE DCL IN[2], TEXCOORD[2], PERSPECTIVE DCL IN[3], COLOR, COLOR, CENTROID DCL IN[4], COLOR[1], COLOR, CENTROID DCL IN[5], TEXCOORD[6], PERSPECTIVE DCL IN[6], TEXCOORD[7], PERSPECTIVE DCL OUT[0], COLOR DCL OUT[1], COLOR[1] DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL CONST[0][0..2] DCL TEMP[0] DCL TEMP[1], LOCAL DCL TEMP[2..6] IMM[0] FLT32 { -0.9000, 0.0000, 1.0000, -0.8000} IMM[1] FLT32 { 0.3300, 2.0000, -1.0000, 1.0000} IMM[2] FLT32 { 8.0000, 4.0000, 0.5000, -0.5000} IMM[3] FLT32 { 20.0000, 0.5000, -0.0000, 0.0000} IMM[4] FLT32 {340282346638528859811704183484516925440.0000, -340282346638528859811704183484516925440.0000, 0.0000, 0.0000} 0: MOV TEMP[0], IN[4].wwww 1: KILL_IF TEMP[0] 2: ADD TEMP[0].xyz, -CONST[0][0], IN[1] 3: DP3 TEMP[1].x, TEMP[0], TEMP[0] 4: RSQ TEMP[1].x, TEMP[1].xxxx 5: MIN TEMP[1].x, IMM[4].xxxx, TEMP[1].xxxx 6: MUL TEMP[2].xyz, TEMP[0], TEMP[1].xxxx 7: TEX TEMP[0], IN[0], SAMP[1], 2D 8: MAD TEMP[0].xy, TEMP[0], IMM[1].yyyy, IMM[1].zzzz 9: DP2 TEMP[1].x, TEMP[0], -TEMP[0] 10: ADD TEMP[2].w, IMM[0].zzzz, TEMP[1].xxxx 11: RSQ TEMP[1], |TEMP[2].wwww| 12: MIN TEMP[2].w, IMM[4].xxxx, TEMP[1] 13: RCP TEMP[1], TEMP[2].wwww 14: MIN TEMP[1], IMM[4].xxxx, TEMP[1] 15: MAX TEMP[2].w, IMM[4].yyyy, TEMP[1] 16: MUL TEMP[3].xyz, TEMP[0].xxxx, IN[5] 17: MAD TEMP[3].xyz, IN[2], TEMP[2].wwww, TEMP[3] 18: MAD TEMP[3].xyz, IN[6], TEMP[0].yyyy, TEMP[3] 19: DP3 TEMP[0].x, TEMP[2], TEMP[3] 20: ADD TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx 21: MAD TEMP[2].xyz, TEMP[3], -TEMP[0].xxxx, TEMP[2] 22: MAD TEMP[0].x, TEMP[0].zzzz, -TEMP[0].zzzz, IMM[0].zzzz 23: MUL TEMP[2].w, TEMP[0].xxxx, IMM[2].xxxx 24: TXL TEMP[2], TEMP[2], SAMP[3], CUBE 25: MUL TEMP[0].xyz, TEMP[0].zzzz, TEMP[2] 26: MUL TEMP[0].xyz, TEMP[0], IMM[2].yyyy 27: DP3 TEMP[2].x, IN[3], IMM[1].xxxx 28: ADD TEMP[2].xyz, TEMP[2].xxxx, -IN[3] 29: ADD TEMP[2].w, IMM[0].xxxx, IN[5].wwww 30: CMP TEMP[3].w, -TEMP[2].wwww, IMM[0].zzzz, IMM[0].yyyy 31: CMP TEMP[2].w, TEMP[2].wwww, -IMM[0].zzzz, -IMM[0].yyyy 32: ADD TEMP[2].w, TEMP[2].wwww, TEMP[3].wwww 33: MUL TEMP[3].w, TEMP[2].wwww, IN[5].wwww 34: CMP_SAT TEMP[2].w, TEMP[2].wwww, IMM[0].yyyy, TEMP[3].wwww 35: TEX TEMP[4], IN[0], SAMP[0], 2D 36: ADD TEMP[5].xyz, TEMP[4], IMM[0].wwww 37: DP3 TEMP[3].w, TEMP[5], TEMP[5] 38: RSQ TEMP[1], |TEMP[3].wwww| 39: MIN TEMP[3].w, IMM[4].xxxx, TEMP[1] 40: RCP TEMP[1], TEMP[3].wwww 41: MIN TEMP[1], IMM[4].xxxx, TEMP[1] 42: MAX_SAT TEMP[3].w, IMM[4].yyyy, TEMP[1] 43: ADD TEMP[3].w, -TEMP[2].wwww, TEMP[3].wwww 44: MAD TEMP[2].xyz, TEMP[3].wwww, TEMP[2], IN[3] 45: MAX TEMP[3].w, TEMP[4].yyyy, TEMP[4].zzzz 46: MAX TEMP[5].x, TEMP[4].xxxx, TEMP[3].wwww 47: LRP TEMP[6].xyz, TEMP[2].wwww, TEMP[5].xxxx, TEMP[4] 48: ADD TEMP[3].w, TEMP[4].wwww, -IN[3].wwww 49: ADD TEMP[3].w, TEMP[3].wwww, IMM[2].wwww 50: MAD_SAT TEMP[3].w, TEMP[3].wwww, IMM[3].xxxx, IMM[3].yyyy 51: MUL OUT[0].w, TEMP[3].wwww, IMM[2].zzzz 52: MAD TEMP[0].xyz, TEMP[6], TEMP[2], TEMP[0] 53: ADD TEMP[2].xyz, -TEMP[0], IMM[0].zzzz 54: MUL TEMP[4].xy, IMM[1].wzzw, IN[1].xzzw 55: MUL TEMP[4].xy, TEMP[4], CONST[0][2].xxxx 56: TEX TEMP[4], TEMP[4], SAMP[2], 2D 57: ADD TEMP[3].w, -TEMP[4].zzzz, IMM[0].zzzz 58: ADD TEMP[0].w, TEMP[0].wwww, -TEMP[3].wwww 59: ADD_SAT TEMP[0].w, -TEMP[2].wwww, TEMP[0].wwww 60: ADD TEMP[2].w, TEMP[0].wwww, TEMP[0].wwww 61: MAD TEMP[0].w, TEMP[0].wwww, IMM[1].yyyy, IMM[1].zzzz 62: MAX TEMP[3].w, TEMP[0].wwww, IMM[0].yyyy 63: MOV_SAT TEMP[2].w, TEMP[2].wwww 64: MOV_SAT TEMP[0].w, TEMP[3].yyyy 65: MAD TEMP[0].w, TEMP[0].wwww, TEMP[2].wwww, TEMP[3].wwww 66: ADD TEMP[2].w, -CONST[0][1].xxxx, IN[1].yyyy 67: ADD TEMP[2].w, TEMP[2].wwww, IMM[2].zzzz 68: MAD TEMP[2].w, TEMP[2].wwww, IMM[2].zzzz, IMM[2].wwww 69: MUL_SAT TEMP[0].w, TEMP[0].wwww, TEMP[2].wwww 70: ADD TEMP[0].w, TEMP[0].wwww, IMM[2].wwww 71: MAD_SAT TEMP[0].w, TEMP[0].wwww, IMM[2].yyyy, IMM[2].zzzz 72: MAD OUT[0].xyz, TEMP[0].wwww, TEMP[2], TEMP[0] 73: DP2 TEMP[1].x, TEMP[3].xzzw, TEMP[3].xzzw 74: ADD TEMP[0].x, IMM[0].yyyy, TEMP[1].xxxx 75: RSQ TEMP[1], |TEMP[0].xxxx| 76: MIN TEMP[0].x, IMM[4].xxxx, TEMP[1] 77: MUL TEMP[0].xy, TEMP[0].xxxx, TEMP[3].xzzw 78: MAD TEMP[0].z, TEMP[3].yyyy, IMM[2].zzzz, IMM[2].zzzz 79: DP2 TEMP[1].x, TEMP[3].xzzw, TEMP[3].xzzw 80: ADD TEMP[0].w, IMM[3].zzzz, TEMP[1].xxxx 81: RSQ TEMP[1], |TEMP[0].zzzz| 82: MIN TEMP[0].z, IMM[4].xxxx, TEMP[1] 83: RCP TEMP[1], TEMP[0].zzzz 84: MIN TEMP[1], IMM[4].xxxx, TEMP[1] 85: MAX TEMP[0].z, IMM[4].yyyy, TEMP[1] 86: MUL TEMP[0].xy, TEMP[0].zzzz, TEMP[0] 87: MAD TEMP[0].xy, TEMP[0], IMM[2].zzzz, IMM[2].zzzz 88: CMP OUT[1].yz, TEMP[0].wwww, IMM[0].zzzz, TEMP[0].xxyw 89: MOV OUT[1].x, -IN[0].zzzz 90: MOV OUT[1].w, IMM[0].zzzz 91: END radeonsi: Compiling shader 57 TGSI shader LLVM IR: ; ModuleID = 'mesa-shader' source_filename = "mesa-shader" target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" target triple = "amdgcn--" ; Function Attrs: nounwind readnone speculatable declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #0 ; Function Attrs: nounwind readnone speculatable declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #0 ; Function Attrs: nounwind declare void @llvm.amdgcn.kill(i1) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2 ; Function Attrs: nounwind readnone speculatable declare float @llvm.sqrt.f32(float) #0 ; Function Attrs: nounwind readnone speculatable declare float @llvm.minnum.f32(float, float) #0 ; Function Attrs: nounwind readonly declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #3 ; Function Attrs: nounwind readnone speculatable declare float @llvm.fabs.f32(float) #0 ; Function Attrs: nounwind readnone speculatable declare float @llvm.maxnum.f32(float, float) #0 ; Function Attrs: nounwind readnone speculatable declare float @llvm.amdgcn.cubetc(float, float, float) #0 ; Function Attrs: nounwind readnone speculatable declare float @llvm.amdgcn.cubesc(float, float, float) #0 ; Function Attrs: nounwind readnone speculatable declare float @llvm.amdgcn.cubema(float, float, float) #0 ; Function Attrs: nounwind readnone speculatable declare float @llvm.amdgcn.cubeid(float, float, float) #0 ; Function Attrs: nounwind readonly declare <4 x float> @llvm.amdgcn.image.sample.l.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #3 ; Function Attrs: nounwind readnone speculatable declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #0 ; Function Attrs: nounwind declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1) #1 ; Function Attrs: nounwind declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1 define amdgpu_ps void @wrapper([0 x <4 x i32>] addrspace(2)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(2)* inreg noalias dereferenceable(18446744073709551615), [0 x float] addrspace(2)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(2)* inreg noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #4 { main_body: %22 = ptrtoint [0 x float] addrspace(2)* %2 to i64 %23 = bitcast i64 %22 to <2 x i32> %24 = extractelement <2 x i32> %23, i32 0 %25 = extractelement <2 x i32> %23, i32 1 %26 = bitcast <2 x i32> %7 to <2 x float> %27 = extractelement <2 x float> %26, i32 0 %28 = extractelement <2 x float> %26, i32 1 %29 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 0, i32 3, i32 %5) #2 %30 = call nsz float @llvm.amdgcn.interp.p2(float %29, float %28, i32 0, i32 3, i32 %5) #2 %31 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 1, i32 3, i32 %5) #2 %32 = call nsz float @llvm.amdgcn.interp.p2(float %31, float %28, i32 1, i32 3, i32 %5) #2 %33 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 2, i32 3, i32 %5) #2 %34 = call nsz float @llvm.amdgcn.interp.p2(float %33, float %28, i32 2, i32 3, i32 %5) #2 %35 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 3, i32 3, i32 %5) #2 %36 = call nsz float @llvm.amdgcn.interp.p2(float %35, float %28, i32 3, i32 3, i32 %5) #2 %37 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 3, i32 4, i32 %5) #2 %38 = call nsz float @llvm.amdgcn.interp.p2(float %37, float %28, i32 3, i32 4, i32 %5) #2 %39 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 0, i32 0, i32 %5) #2 %40 = call nsz float @llvm.amdgcn.interp.p2(float %39, float %28, i32 0, i32 0, i32 %5) #2 %41 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 1, i32 0, i32 %5) #2 %42 = call nsz float @llvm.amdgcn.interp.p2(float %41, float %28, i32 1, i32 0, i32 %5) #2 %43 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 2, i32 0, i32 %5) #2 %44 = call nsz float @llvm.amdgcn.interp.p2(float %43, float %28, i32 2, i32 0, i32 %5) #2 %45 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 0, i32 1, i32 %5) #2 %46 = call nsz float @llvm.amdgcn.interp.p2(float %45, float %28, i32 0, i32 1, i32 %5) #2 %47 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 1, i32 1, i32 %5) #2 %48 = call nsz float @llvm.amdgcn.interp.p2(float %47, float %28, i32 1, i32 1, i32 %5) #2 %49 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 2, i32 1, i32 %5) #2 %50 = call nsz float @llvm.amdgcn.interp.p2(float %49, float %28, i32 2, i32 1, i32 %5) #2 %51 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 0, i32 2, i32 %5) #2 %52 = call nsz float @llvm.amdgcn.interp.p2(float %51, float %28, i32 0, i32 2, i32 %5) #2 %53 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 1, i32 2, i32 %5) #2 %54 = call nsz float @llvm.amdgcn.interp.p2(float %53, float %28, i32 1, i32 2, i32 %5) #2 %55 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 2, i32 2, i32 %5) #2 %56 = call nsz float @llvm.amdgcn.interp.p2(float %55, float %28, i32 2, i32 2, i32 %5) #2 %57 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 0, i32 5, i32 %5) #2 %58 = call nsz float @llvm.amdgcn.interp.p2(float %57, float %28, i32 0, i32 5, i32 %5) #2 %59 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 1, i32 5, i32 %5) #2 %60 = call nsz float @llvm.amdgcn.interp.p2(float %59, float %28, i32 1, i32 5, i32 %5) #2 %61 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 2, i32 5, i32 %5) #2 %62 = call nsz float @llvm.amdgcn.interp.p2(float %61, float %28, i32 2, i32 5, i32 %5) #2 %63 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 3, i32 5, i32 %5) #2 %64 = call nsz float @llvm.amdgcn.interp.p2(float %63, float %28, i32 3, i32 5, i32 %5) #2 %65 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 0, i32 6, i32 %5) #2 %66 = call nsz float @llvm.amdgcn.interp.p2(float %65, float %28, i32 0, i32 6, i32 %5) #2 %67 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 1, i32 6, i32 %5) #2 %68 = call nsz float @llvm.amdgcn.interp.p2(float %67, float %28, i32 1, i32 6, i32 %5) #2 %69 = call nsz float @llvm.amdgcn.interp.p1(float %27, i32 2, i32 6, i32 %5) #2 %70 = call nsz float @llvm.amdgcn.interp.p2(float %69, float %28, i32 2, i32 6, i32 %5) #2 %71 = fcmp nsz oge float %38, 0.000000e+00 call void @llvm.amdgcn.kill(i1 %71) #1, !noalias !0 %72 = and i32 %25, 65535 %73 = insertelement <4 x i32> , i32 %24, i32 0 %74 = insertelement <4 x i32> %73, i32 %72, i32 1 %75 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %74, i32 0) %76 = fsub nsz float %46, %75 %77 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %74, i32 4) %78 = fsub nsz float %48, %77 %79 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %74, i32 8) %80 = fsub nsz float %50, %79 %81 = fmul nsz float %76, %76 %82 = fmul nsz float %78, %78 %83 = fadd nsz float %82, %81 %84 = fmul nsz float %80, %80 %85 = fadd nsz float %83, %84 %86 = call nsz float @llvm.sqrt.f32(float %85) #2 %87 = fdiv nsz float 1.000000e+00, %86, !fpmath !4 %88 = call nsz float @llvm.minnum.f32(float %87, float 0x47EFFFFFE0000000) #2 %89 = fmul nsz float %76, %88 %90 = fmul nsz float %78, %88 %91 = fmul nsz float %80, %88 %92 = getelementptr [0 x <8 x i32>], [0 x <8 x i32>] addrspace(2)* %3, i64 0, i64 18, !amdgpu.uniform !5 %93 = load <8 x i32>, <8 x i32> addrspace(2)* %92, align 32, !invariant.load !5, !alias.scope !6, !noalias !7 %94 = bitcast [0 x <8 x i32>] addrspace(2)* %3 to [0 x <4 x i32>] addrspace(2)* %95 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %94, i64 0, i64 39, !amdgpu.uniform !5 %96 = load <4 x i32>, <4 x i32> addrspace(2)* %95, align 16, !invariant.load !5, !alias.scope !6, !noalias !7 %97 = bitcast float %40 to i32 %98 = bitcast float %42 to i32 %99 = insertelement <2 x i32> undef, i32 %97, i32 0 %100 = insertelement <2 x i32> %99, i32 %98, i32 1 %101 = bitcast <2 x i32> %100 to <2 x float> %102 = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %101, <8 x i32> %93, <4 x i32> %96, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #2 %103 = extractelement <4 x float> %102, i32 0 %104 = extractelement <4 x float> %102, i32 1 %105 = extractelement <4 x float> %102, i32 2 %106 = extractelement <4 x float> %102, i32 3 %107 = fmul nsz float %103, 2.000000e+00 %108 = fadd nsz float %107, -1.000000e+00 %109 = fmul nsz float %104, 2.000000e+00 %110 = fadd nsz float %109, -1.000000e+00 %111 = fmul nsz float %108, %108 %112 = fmul nsz float %110, %110 %113 = fsub nsz float -0.000000e+00, %112 %114 = fsub nsz float %113, %111 %115 = fadd nsz float %114, 1.000000e+00 %116 = call nsz float @llvm.fabs.f32(float %115) #1 %117 = call nsz float @llvm.sqrt.f32(float %116) #2 %118 = fdiv nsz float 1.000000e+00, %117, !fpmath !4 %119 = call nsz float @llvm.minnum.f32(float %118, float 0x47EFFFFFE0000000) #2 %120 = fdiv nsz float 1.000000e+00, %119, !fpmath !4 %121 = call nsz float @llvm.minnum.f32(float %120, float 0x47EFFFFFE0000000) #2 %122 = call nsz float @llvm.maxnum.f32(float %121, float 0xC7EFFFFFE0000000) #2 %123 = fmul nsz float %108, %58 %124 = fmul nsz float %108, %60 %125 = fmul nsz float %108, %62 %126 = fmul nsz float %52, %122 %127 = fadd nsz float %126, %123 %128 = fmul nsz float %54, %122 %129 = fadd nsz float %128, %124 %130 = fmul nsz float %56, %122 %131 = fadd nsz float %130, %125 %132 = fmul nsz float %66, %110 %133 = fadd nsz float %132, %127 %134 = fmul nsz float %68, %110 %135 = fadd nsz float %134, %129 %136 = fmul nsz float %70, %110 %137 = fadd nsz float %136, %131 %138 = fmul nsz float %89, %133 %139 = fmul nsz float %90, %135 %140 = fadd nsz float %139, %138 %141 = fmul nsz float %91, %137 %142 = fadd nsz float %140, %141 %143 = fadd nsz float %142, %142 %144 = fsub nsz float -0.000000e+00, %143 %145 = fmul nsz float %133, %144 %146 = fadd nsz float %145, %89 %147 = fmul nsz float %135, %144 %148 = fadd nsz float %147, %90 %149 = fmul nsz float %137, %144 %150 = fadd nsz float %149, %91 %151 = fmul nsz float %105, %105 %152 = fsub nsz float 1.000000e+00, %151 %153 = fmul nsz float %152, 8.000000e+00 %154 = getelementptr [0 x <8 x i32>], [0 x <8 x i32>] addrspace(2)* %3, i64 0, i64 22, !amdgpu.uniform !5 %155 = load <8 x i32>, <8 x i32> addrspace(2)* %154, align 32, !invariant.load !5, !alias.scope !6, !noalias !7 %156 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %94, i64 0, i64 47, !amdgpu.uniform !5 %157 = load <4 x i32>, <4 x i32> addrspace(2)* %156, align 16, !invariant.load !5, !alias.scope !6, !noalias !7 %158 = call nsz float @llvm.amdgcn.cubetc(float %146, float %148, float %150) #2 %159 = call nsz float @llvm.amdgcn.cubesc(float %146, float %148, float %150) #2 %160 = call nsz float @llvm.amdgcn.cubema(float %146, float %148, float %150) #2 %161 = call nsz float @llvm.amdgcn.cubeid(float %146, float %148, float %150) #2 %162 = call nsz float @llvm.fabs.f32(float %160) #2 %163 = fdiv nsz float 1.000000e+00, %162, !fpmath !4 %164 = fmul nsz float %159, %163 %165 = fmul nsz float %158, %163 %166 = fadd nsz float %164, 1.500000e+00 %167 = fadd nsz float %165, 1.500000e+00 %168 = bitcast float %166 to i32 %169 = bitcast float %167 to i32 %170 = bitcast float %161 to i32 %171 = bitcast float %153 to i32 %172 = insertelement <4 x i32> undef, i32 %168, i32 0 %173 = insertelement <4 x i32> %172, i32 %169, i32 1 %174 = insertelement <4 x i32> %173, i32 %170, i32 2 %175 = insertelement <4 x i32> %174, i32 %171, i32 3 %176 = bitcast <4 x i32> %175 to <4 x float> %177 = call nsz <4 x float> @llvm.amdgcn.image.sample.l.v4f32.v4f32.v8i32(<4 x float> %176, <8 x i32> %155, <4 x i32> %157, i32 15, i1 false, i1 false, i1 false, i1 false, i1 true) #2 %178 = extractelement <4 x float> %177, i32 0 %179 = extractelement <4 x float> %177, i32 1 %180 = extractelement <4 x float> %177, i32 2 %181 = fmul nsz float %105, %178 %182 = fmul nsz float %105, %179 %183 = fmul nsz float %105, %180 %184 = fmul nsz float %181, 4.000000e+00 %185 = fmul nsz float %182, 4.000000e+00 %186 = fmul nsz float %183, 4.000000e+00 %187 = fmul nsz float %30, 0x3FD51EB860000000 %188 = fmul nsz float %32, 0x3FD51EB860000000 %189 = fadd nsz float %188, %187 %190 = fmul nsz float %34, 0x3FD51EB860000000 %191 = fadd nsz float %189, %190 %192 = fsub nsz float %191, %30 %193 = fsub nsz float %191, %32 %194 = fsub nsz float %191, %34 %195 = fadd nsz float %64, 0xBFECCCCCC0000000 %196 = fcmp ogt float %195, -0.000000e+00 %197 = select i1 %196, float 1.000000e+00, float 0.000000e+00 %198 = fcmp nsz olt float %195, 0.000000e+00 %199 = select i1 %198, float -1.000000e+00, float -0.000000e+00 %200 = fadd nsz float %199, %197 %201 = fmul nsz float %200, %64 %202 = fcmp nsz olt float %200, 0.000000e+00 %203 = select i1 %202, float 0.000000e+00, float %201 %204 = call nsz float @llvm.maxnum.f32(float %203, float 0.000000e+00) #2 %205 = call nsz float @llvm.minnum.f32(float %204, float 1.000000e+00) #2 %206 = getelementptr [0 x <8 x i32>], [0 x <8 x i32>] addrspace(2)* %3, i64 0, i64 16, !amdgpu.uniform !5 %207 = load <8 x i32>, <8 x i32> addrspace(2)* %206, align 32, !invariant.load !5, !alias.scope !6, !noalias !7 %208 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %94, i64 0, i64 35, !amdgpu.uniform !5 %209 = load <4 x i32>, <4 x i32> addrspace(2)* %208, align 16, !invariant.load !5, !alias.scope !6, !noalias !7 %210 = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %101, <8 x i32> %207, <4 x i32> %209, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #2 %211 = extractelement <4 x float> %210, i32 0 %212 = extractelement <4 x float> %210, i32 1 %213 = extractelement <4 x float> %210, i32 2 %214 = extractelement <4 x float> %210, i32 3 %215 = fadd nsz float %211, 0xBFE99999A0000000 %216 = fadd nsz float %212, 0xBFE99999A0000000 %217 = fadd nsz float %213, 0xBFE99999A0000000 %218 = fmul nsz float %215, %215 %219 = fmul nsz float %216, %216 %220 = fadd nsz float %219, %218 %221 = fmul nsz float %217, %217 %222 = fadd nsz float %220, %221 %223 = call nsz float @llvm.fabs.f32(float %222) #1 %224 = call nsz float @llvm.sqrt.f32(float %223) #2 %225 = fdiv nsz float 1.000000e+00, %224, !fpmath !4 %226 = call nsz float @llvm.minnum.f32(float %225, float 0x47EFFFFFE0000000) #2 %227 = fdiv nsz float 1.000000e+00, %226, !fpmath !4 %228 = call nsz float @llvm.minnum.f32(float %227, float 0x47EFFFFFE0000000) #2 %229 = call nsz float @llvm.maxnum.f32(float %228, float 0xC7EFFFFFE0000000) #2 %230 = call nsz float @llvm.maxnum.f32(float %229, float 0.000000e+00) #2 %231 = call nsz float @llvm.minnum.f32(float %230, float 1.000000e+00) #2 %232 = fsub nsz float %231, %205 %233 = fmul nsz float %232, %192 %234 = fadd nsz float %233, %30 %235 = fmul nsz float %232, %193 %236 = fadd nsz float %235, %32 %237 = fmul nsz float %232, %194 %238 = fadd nsz float %237, %34 %239 = call nsz float @llvm.maxnum.f32(float %212, float %213) #2 %240 = call nsz float @llvm.maxnum.f32(float %211, float %239) #2 %241 = fsub nsz float 1.000000e+00, %205 %242 = fmul nsz float %240, %205 %243 = fmul nsz float %211, %241 %244 = fadd nsz float %242, %243 %245 = fmul nsz float %212, %241 %246 = fadd nsz float %242, %245 %247 = fmul nsz float %213, %241 %248 = fadd nsz float %242, %247 %249 = fsub nsz float %214, %36 %250 = fadd nsz float %249, -5.000000e-01 %251 = fmul nsz float %250, 2.000000e+01 %252 = fadd nsz float %251, 5.000000e-01 %253 = call nsz float @llvm.maxnum.f32(float %252, float 0.000000e+00) #2 %254 = call nsz float @llvm.minnum.f32(float %253, float 1.000000e+00) #2 %255 = fmul nsz float %254, 5.000000e-01 %256 = fmul nsz float %244, %234 %257 = fadd nsz float %256, %184 %258 = fmul nsz float %246, %236 %259 = fadd nsz float %258, %185 %260 = fmul nsz float %248, %238 %261 = fadd nsz float %260, %186 %262 = fsub nsz float 1.000000e+00, %257 %263 = fsub nsz float 1.000000e+00, %259 %264 = fsub nsz float 1.000000e+00, %261 %265 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %74, i32 32) %266 = fmul nsz float %46, %265 %267 = fmul nsz float %50, %265 %268 = fsub nsz float -0.000000e+00, %267 %269 = getelementptr [0 x <8 x i32>], [0 x <8 x i32>] addrspace(2)* %3, i64 0, i64 20, !amdgpu.uniform !5 %270 = load <8 x i32>, <8 x i32> addrspace(2)* %269, align 32, !invariant.load !5, !alias.scope !6, !noalias !7 %271 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %94, i64 0, i64 43, !amdgpu.uniform !5 %272 = load <4 x i32>, <4 x i32> addrspace(2)* %271, align 16, !invariant.load !5, !alias.scope !6, !noalias !7 %273 = bitcast float %266 to i32 %274 = bitcast float %268 to i32 %275 = insertelement <2 x i32> undef, i32 %273, i32 0 %276 = insertelement <2 x i32> %275, i32 %274, i32 1 %277 = bitcast <2 x i32> %276 to <2 x float> %278 = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %277, <8 x i32> %270, <4 x i32> %272, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #2 %279 = extractelement <4 x float> %278, i32 2 %280 = fsub nsz float 1.000000e+00, %279 %281 = fsub nsz float %106, %280 %282 = fsub nsz float %281, %205 %283 = call nsz float @llvm.maxnum.f32(float %282, float 0.000000e+00) #2 %284 = call nsz float @llvm.minnum.f32(float %283, float 1.000000e+00) #2 %285 = fadd nsz float %284, %284 %286 = fmul nsz float %284, 2.000000e+00 %287 = fadd nsz float %286, -1.000000e+00 %288 = call nsz float @llvm.maxnum.f32(float %287, float 0.000000e+00) #2 %289 = call nsz float @llvm.maxnum.f32(float %285, float 0.000000e+00) #2 %290 = call nsz float @llvm.minnum.f32(float %289, float 1.000000e+00) #2 %291 = call nsz float @llvm.maxnum.f32(float %135, float 0.000000e+00) #2 %292 = call nsz float @llvm.minnum.f32(float %291, float 1.000000e+00) #2 %293 = fmul nsz float %292, %290 %294 = fadd nsz float %293, %288 %295 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %74, i32 16) %296 = fsub nsz float %48, %295 %297 = fadd nsz float %296, 5.000000e-01 %298 = fmul nsz float %297, 5.000000e-01 %299 = fadd nsz float %298, -5.000000e-01 %300 = fmul nsz float %294, %299 %301 = call nsz float @llvm.maxnum.f32(float %300, float 0.000000e+00) #2 %302 = call nsz float @llvm.minnum.f32(float %301, float 1.000000e+00) #2 %303 = fadd nsz float %302, -5.000000e-01 %304 = fmul nsz float %303, 4.000000e+00 %305 = fadd nsz float %304, 5.000000e-01 %306 = call nsz float @llvm.maxnum.f32(float %305, float 0.000000e+00) #2 %307 = call nsz float @llvm.minnum.f32(float %306, float 1.000000e+00) #2 %308 = fmul nsz float %307, %262 %309 = fadd nsz float %308, %257 %310 = fmul nsz float %307, %263 %311 = fadd nsz float %310, %259 %312 = fmul nsz float %307, %264 %313 = fadd nsz float %312, %261 %314 = fmul nsz float %133, %133 %315 = fmul nsz float %137, %137 %316 = fadd nsz float %314, %315 %317 = call nsz float @llvm.fabs.f32(float %316) #1 %318 = call nsz float @llvm.sqrt.f32(float %317) #2 %319 = fdiv nsz float 1.000000e+00, %318, !fpmath !4 %320 = call nsz float @llvm.minnum.f32(float %319, float 0x47EFFFFFE0000000) #2 %321 = fmul nsz float %320, %133 %322 = fmul nsz float %320, %137 %323 = fmul nsz float %135, 5.000000e-01 %324 = fadd nsz float %323, 5.000000e-01 %325 = fadd nsz float %316, 0xBEE4F8B580000000 %326 = call nsz float @llvm.fabs.f32(float %324) #1 %327 = call nsz float @llvm.sqrt.f32(float %326) #2 %328 = fdiv nsz float 1.000000e+00, %327, !fpmath !4 %329 = call nsz float @llvm.minnum.f32(float %328, float 0x47EFFFFFE0000000) #2 %330 = fdiv nsz float 1.000000e+00, %329, !fpmath !4 %331 = call nsz float @llvm.minnum.f32(float %330, float 0x47EFFFFFE0000000) #2 %332 = call nsz float @llvm.maxnum.f32(float %331, float 0xC7EFFFFFE0000000) #2 %333 = fmul nsz float %332, %321 %334 = fmul nsz float %332, %322 %335 = fmul nsz float %333, 5.000000e-01 %336 = fadd nsz float %335, 5.000000e-01 %337 = fmul nsz float %334, 5.000000e-01 %338 = fadd nsz float %337, 5.000000e-01 %339 = fcmp nsz olt float %325, 0.000000e+00 %340 = select i1 %339, float 1.000000e+00, float %336 %341 = select i1 %339, float 1.000000e+00, float %338 %342 = fsub nsz float -0.000000e+00, %44 %343 = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float %309, float %311) #2 %344 = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float %313, float %255) #2 %345 = bitcast <2 x half> %343 to <2 x i16> %346 = bitcast <2 x half> %344 to <2 x i16> call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 15, <2 x i16> %345, <2 x i16> %346, i1 false, i1 false) #1 call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %342, float %340, float %341, float 1.000000e+00, i1 true, i1 true) #1 ret void } ; Function Attrs: argmemonly nounwind declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #5 ; Function Attrs: argmemonly nounwind declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #5 attributes #0 = { nounwind readnone speculatable } attributes #1 = { nounwind } attributes #2 = { nounwind readnone } attributes #3 = { nounwind readonly } attributes #4 = { "no-signed-zeros-fp-math"="true" } attributes #5 = { argmemonly nounwind } !0 = !{!1, !3} !1 = distinct !{!1, !2, !"main: argument 0"} !2 = distinct !{!2, !"main"} !3 = distinct !{!3, !2, !"main: argument 1"} !4 = !{float 2.500000e+00} !5 = !{} !6 = !{!3} !7 = !{!1} SHADER KEY part.ps.prolog.color_two_side = 0 part.ps.prolog.flatshade_colors = 0 part.ps.prolog.poly_stipple = 0 part.ps.prolog.force_persp_sample_interp = 0 part.ps.prolog.force_linear_sample_interp = 0 part.ps.prolog.force_persp_center_interp = 1 part.ps.prolog.force_linear_center_interp = 0 part.ps.prolog.bc_optimize_for_persp = 0 part.ps.prolog.bc_optimize_for_linear = 0 part.ps.epilog.spi_shader_col_format = 0x94 part.ps.epilog.color_is_int8 = 0x0 part.ps.epilog.color_is_int10 = 0x0 part.ps.epilog.last_cbuf = 0 part.ps.epilog.alpha_func = 7 part.ps.epilog.alpha_to_one = 0 part.ps.epilog.poly_line_smoothing = 0 part.ps.epilog.clamp_color = 0 Pixel Shader: Shader main disassembly: wrapper: BB56_0: s_mov_b64 s[2:3], exec ; BE82017E s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s9 ; BEFC0009 v_interp_p1_f32 v4, v0, attr3.x ; D4100C00 v_interp_p1_f32 v5, v0, attr3.y ; D4140D00 v_interp_p1_f32 v6, v0, attr3.z ; D4180E00 v_interp_p1_f32 v10, v0, attr3.w ; D4280F00 v_interp_p1_f32 v21, v0, attr4.w ; D4541300 v_interp_p1_f32 v13, v0, attr0.x ; D4340000 v_interp_p1_f32 v14, v0, attr0.y ; D4380100 v_interp_p1_f32 v3, v0, attr0.z ; D40C0200 v_interp_p1_f32 v7, v0, attr1.x ; D41C0400 v_interp_p1_f32 v2, v0, attr1.y ; D4080500 v_interp_p1_f32 v8, v0, attr1.z ; D4200600 v_interp_p1_f32 v9, v0, attr2.x ; D4240800 v_interp_p1_f32 v11, v0, attr2.y ; D42C0900 v_interp_p1_f32 v12, v0, attr2.z ; D4300A00 v_interp_p1_f32 v17, v0, attr5.x ; D4441400 v_interp_p1_f32 v18, v0, attr5.y ; D4481500 v_interp_p1_f32 v19, v0, attr5.z ; D44C1600 v_interp_p1_f32 v20, v0, attr5.w ; D4501700 v_interp_p1_f32 v15, v0, attr6.x ; D43C1800 v_interp_p1_f32 v16, v0, attr6.y ; D4401900 v_interp_p1_f32 v0, v0, attr6.z ; D4001A00 s_mov_b64 s[0:1], s[6:7] ; BE800106 v_interp_p2_f32 v4, v1, attr3.x ; D4110C01 v_interp_p2_f32 v5, v1, attr3.y ; D4150D01 v_interp_p2_f32 v6, v1, attr3.z ; D4190E01 v_interp_p2_f32 v10, v1, attr3.w ; D4290F01 v_interp_p2_f32 v21, v1, attr4.w ; D4551301 v_interp_p2_f32 v13, v1, attr0.x ; D4350001 v_interp_p2_f32 v14, v1, attr0.y ; D4390101 v_interp_p2_f32 v3, v1, attr0.z ; D40D0201 v_interp_p2_f32 v7, v1, attr1.x ; D41D0401 v_interp_p2_f32 v2, v1, attr1.y ; D4090501 v_interp_p2_f32 v8, v1, attr1.z ; D4210601 v_interp_p2_f32 v9, v1, attr2.x ; D4250801 v_interp_p2_f32 v11, v1, attr2.y ; D42D0901 v_interp_p2_f32 v12, v1, attr2.z ; D4310A01 v_interp_p2_f32 v17, v1, attr5.x ; D4451401 v_interp_p2_f32 v18, v1, attr5.y ; D4491501 v_interp_p2_f32 v19, v1, attr5.z ; D44D1601 v_interp_p2_f32 v20, v1, attr5.w ; D4511701 v_interp_p2_f32 v15, v1, attr6.x ; D43D1801 v_interp_p2_f32 v16, v1, attr6.y ; D4411901 v_interp_p2_f32 v0, v1, attr6.z ; D4011A01 v_cmpx_le_f32_e32 vcc, 0, v21 ; 7CA62A80 s_cbranch_execnz BB56_2 ; BF890000 exp null off, off, off, off done vm ; C4001890 00000000 s_endpgm ; BF810000 BB56_2: v_add_f32_e32 v21, 0xbf666666, v20 ; 022A28FF BF666666 v_bfrev_b32_e32 v25, 1 ; 7E325881 v_cmp_gt_f32_e32 vcc, v21, v25 ; 7C883315 s_load_dwordx4 s[16:19], s[0:1], 0x270 ; C00A0400 00000270 s_load_dwordx8 s[8:15], s[0:1], 0x280 ; C00E0200 00000280 s_load_dwordx4 s[36:39], s[0:1], 0x230 ; C00A0900 00000230 v_cndmask_b32_e64 v22, 0, 1.0, vcc ; D1000016 01A9E480 v_cmp_gt_f32_e32 vcc, 0, v21 ; 7C882A80 s_load_dwordx8 s[28:35], s[0:1], 0x200 ; C00E0700 00000200 v_cndmask_b32_e64 v21, v25, -1.0, vcc ; D1000015 01A9E719 v_add_f32_e32 v21, v21, v22 ; 022A2D15 v_mov_b32_e32 v23, 0x3ea8f5c3 ; 7E2E02FF 3EA8F5C3 v_mul_f32_e32 v26, v4, v23 ; 0A342F04 v_mul_f32_e32 v20, v21, v20 ; 0A282915 v_cmp_ngt_f32_e32 vcc, 0, v21 ; 7C962A80 v_mac_f32_e32 v26, v5, v23 ; 2C342F05 v_cndmask_b32_e32 v20, 0, v20, vcc ; 00282880 v_max_f32_e64 v27, v20, v20 clamp ; D10B801B 00022914 s_load_dwordx8 s[20:27], s[0:1], 0x240 ; C00E0500 00000240 v_mac_f32_e32 v26, v6, v23 ; 2C342F06 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[20:23], v[13:14], s[28:35], s[36:39] dmask:0xf ; F0800F00 0127140D v_mov_b32_e32 v1, 0xbf4ccccd ; 7E0202FF BF4CCCCD v_sub_f32_e32 v28, 1.0, v27 ; 043836F2 v_mov_b32_e32 v24, 0x7f7fffff ; 7E3002FF 7F7FFFFF s_and_b32 s5, s5, 0xffff ; 8605FF05 0000FFFF s_mov_b32 s7, 0x27fac ; BE8700FF 00027FAC s_mov_b32 s6, 48 ; BE8600B0 s_waitcnt vmcnt(0) ; BF8C0F70 v_max3_f32 v30, v20, v21, v22 ; D1D3001E 045A2B14 v_mul_f32_e32 v30, v30, v27 ; 0A3C371E v_add_f32_e32 v29, v20, v1 ; 023A0314 v_mad_f32 v31, v20, v28, v30 ; D1C1001F 047A3914 v_mad_f32 v32, v21, v28, v30 ; D1C10020 047A3915 v_mac_f32_e32 v30, v22, v28 ; 2C3C3916 v_add_f32_e32 v28, v21, v1 ; 02380315 v_add_f32_e32 v1, v22, v1 ; 02020316 v_sub_f32_e32 v33, v23, v10 ; 04421517 image_sample v[20:23], v[13:14], s[20:27], s[16:19] dmask:0xf ; F0800F00 0085140D s_load_dwordx4 s[16:19], s[0:1], 0x2b0 ; C00A0400 000002B0 s_load_dwordx8 s[20:27], s[0:1], 0x2c0 ; C00E0500 000002C0 s_load_dwordx4 s[28:31], s[0:1], 0x2f0 ; C00A0700 000002F0 s_buffer_load_dwordx2 s[0:1], s[4:7], 0x0 ; C0260002 00000000 s_buffer_load_dword s32, s[4:7], 0x8 ; C0220802 00000008 s_buffer_load_dword s33, s[4:7], 0x20 ; C0220842 00000020 s_waitcnt vmcnt(0) ; BF8C0F70 v_mad_f32 v10, v20, 2.0, -1.0 ; D1C1000A 03CDE914 v_mad_f32 v13, v21, 2.0, -1.0 ; D1C1000D 03CDE915 v_mul_f32_e32 v14, v10, v17 ; 0A1C230A v_mul_f32_e32 v17, v10, v18 ; 0A22250A v_mul_f32_e32 v18, v10, v19 ; 0A24270A v_mul_f32_e32 v10, v10, v10 ; 0A14150A v_mad_f32 v10, v13, -v13, -v10 ; D1C1000A C42A1B0D v_mul_f32_e32 v19, v29, v29 ; 0A263B1D v_add_f32_e32 v10, 1.0, v10 ; 021414F2 v_mac_f32_e32 v19, v28, v28 ; 2C26391C v_rsq_f32_e64 v10, |v10| ; D164010A 0000010A v_mac_f32_e32 v19, v1, v1 ; 2C260301 v_rsq_f32_e64 v1, |v19| ; D1640101 00000113 v_mov_b32_e32 v20, 0xff7fffff ; 7E2802FF FF7FFFFF v_min_f32_e32 v10, v10, v24 ; 1414310A v_rcp_f32_e32 v10, v10 ; 7E14450A v_min_f32_e32 v1, v1, v24 ; 14023101 v_rcp_f32_e32 v1, v1 ; 7E024501 v_mov_b32_e32 v21, 1.0 ; 7E2A02F2 v_min_f32_e32 v10, v10, v24 ; 1414310A v_max_f32_e32 v10, v10, v20 ; 1614290A v_min_f32_e32 v1, v1, v24 ; 14023101 v_mac_f32_e32 v18, v12, v10 ; 2C24150C v_max_f32_e64 v1, v1, v20 clamp ; D10B8001 00022901 v_mac_f32_e32 v14, v9, v10 ; 2C1C1509 v_mac_f32_e32 v17, v11, v10 ; 2C22150B v_mac_f32_e32 v18, v0, v13 ; 2C241B00 v_sub_f32_e32 v11, v26, v5 ; 04160B1A v_sub_f32_e32 v1, v1, v27 ; 04023701 s_waitcnt lgkmcnt(0) ; BF8C007F v_subrev_f32_e32 v0, s0, v7 ; 06000E00 v_sub_f32_e32 v9, v26, v4 ; 0412091A v_mac_f32_e32 v17, v16, v13 ; 2C221B10 v_mac_f32_e32 v14, v15, v13 ; 2C1C1B0F v_mac_f32_e32 v5, v1, v11 ; 2C0A1701 v_subrev_f32_e32 v13, s1, v2 ; 061A0401 v_mul_f32_e32 v11, v0, v0 ; 0A160100 v_mac_f32_e32 v4, v1, v9 ; 2C081301 v_subrev_f32_e32 v9, s32, v8 ; 06121020 v_mac_f32_e32 v11, v13, v13 ; 2C161B0D v_mac_f32_e32 v11, v9, v9 ; 2C161309 v_rsq_f32_e32 v11, v11 ; 7E16490B v_sub_f32_e32 v12, v26, v6 ; 04180D1A v_mac_f32_e32 v6, v1, v12 ; 2C0C1901 v_mov_b32_e32 v1, 0x41a00000 ; 7E0202FF 41A00000 v_min_f32_e32 v11, v11, v24 ; 1416310B v_mul_f32_e32 v15, v0, v11 ; 0A1E1700 v_add_f32_e32 v16, -0.5, v33 ; 022042F1 v_mad_f32 v1, v16, v1, 0.5 clamp ; D1C18001 03C20310 v_mul_f32_e32 v16, v13, v11 ; 0A20170D v_mul_f32_e32 v15, v15, v14 ; 0A1E1D0F v_mac_f32_e32 v15, v16, v17 ; 2C1E2310 v_mul_f32_e32 v16, v9, v11 ; 0A201709 v_mac_f32_e64 v15, v16, v18 mul:2 ; D116000F 08022510 v_mul_f32_e32 v19, 0.5, v1 ; 0A2602F0 v_mul_f32_e32 v1, v14, v15 ; 0A021F0E v_mad_f32 v0, v0, v11, -v1 ; D1C10000 84061700 v_mul_f32_e32 v1, v17, v15 ; 0A021F11 v_mul_f32_e32 v15, v18, v15 ; 0A1E1F12 v_mad_f32 v1, v13, v11, -v1 ; D1C10001 8406170D v_mad_f32 v9, v9, v11, -v15 ; D1C10009 843E1709 v_cubema_f32 v11, v0, v1, v9 ; D1C7000B 04260300 v_rcp_f32_e64 v13, |v11| ; D162010D 0000010B v_mad_f32 v12, -v22, v22, 1.0 ; D1C1000C 23CA2D16 v_mov_b32_e32 v10, 0x3fc00000 ; 7E1402FF 3FC00000 v_cubetc_f32 v15, v0, v1, v9 ; D1C6000F 04260300 v_cubesc_f32 v16, v0, v1, v9 ; D1C50010 04260300 v_cubeid_f32 v11, v0, v1, v9 ; D1C4000B 04260300 v_mul_f32_e32 v12, 0x41000000, v12 ; 0A1818FF 41000000 v_madak_f32 v9, v16, v13, 0x3fc00000 ; 30121B10 3FC00000 v_mac_f32_e32 v10, v15, v13 ; 2C141B0F image_sample_l v[9:11], v[9:12], s[20:27], s[28:31] dmask:0x7 da ; F0904700 00E50909 v_mul_f32_e32 v0, s33, v7 ; 0A000E21 v_mul_f32_e64 v1, v8, -s33 ; D1050001 40004308 s_waitcnt vmcnt(0) ; BF8C0F70 v_mul_f32_e64 v7, v22, v9 mul:4 ; D1050007 10021316 v_mul_f32_e64 v9, v22, v10 mul:4 ; D1050009 10021516 v_mul_f32_e64 v10, v22, v11 mul:4 ; D105000A 10021716 v_mac_f32_e32 v7, v31, v4 ; 2C0E091F v_mac_f32_e32 v9, v32, v5 ; 2C120B20 v_mac_f32_e32 v10, v30, v6 ; 2C140D1E v_sub_f32_e32 v4, 1.0, v7 ; 04080EF2 v_sub_f32_e32 v5, 1.0, v9 ; 040A12F2 v_sub_f32_e32 v6, 1.0, v10 ; 040C14F2 s_and_b64 exec, exec, s[2:3] ; 86FE027E image_sample v0, v[0:1], s[8:15], s[16:19] dmask:0x4 ; F0800400 00820000 v_mad_f32 v11, v17, 0.5, 0.5 ; D1C1000B 03C1E111 v_rsq_f32_e64 v11, |v11| ; D164010B 0000010B v_mul_f32_e32 v8, v18, v18 ; 0A102512 v_mac_f32_e32 v8, v14, v14 ; 2C101D0E v_rsq_f32_e64 v12, |v8| ; D164010C 00000108 v_min_f32_e32 v11, v11, v24 ; 1416310B v_rcp_f32_e32 v11, v11 ; 7E16450B s_buffer_load_dword s0, s[4:7], 0x10 ; C0220002 00000010 v_min_f32_e32 v12, v12, v24 ; 1418310C v_mul_f32_e32 v13, v12, v14 ; 0A1A1D0C v_min_f32_e32 v11, v11, v24 ; 1416310B v_max_f32_e32 v11, v11, v20 ; 1616290B v_add_f32_e32 v8, 0xb727c5ac, v8 ; 021010FF B727C5AC v_mul_f32_e32 v12, v12, v18 ; 0A18250C v_mul_f32_e32 v13, v11, v13 ; 0A1A1B0B v_mul_f32_e32 v11, v11, v12 ; 0A16190B v_mad_f32 v12, v13, 0.5, 0.5 ; D1C1000C 03C1E10D v_cmp_gt_f32_e32 vcc, 0, v8 ; 7C881080 s_waitcnt lgkmcnt(0) ; BF8C007F v_subrev_f32_e32 v2, s0, v2 ; 06040400 v_cndmask_b32_e64 v8, v12, 1.0, vcc ; D1000008 01A9E50C v_add_f32_e32 v2, 0.5, v2 ; 020404F0 v_xor_b32_e32 v1, v3, v25 ; 2A023303 v_max_f32_e64 v3, v17, v17 clamp ; D10B8003 00022311 v_mad_f32 v2, v2, 0.5, -0.5 ; D1C10002 03C5E102 v_mad_f32 v11, v11, 0.5, 0.5 ; D1C1000B 03C1E10B v_cndmask_b32_e64 v11, v11, 1.0, vcc ; D100000B 01A9E50B s_waitcnt vmcnt(0) ; BF8C0F70 v_subrev_f32_e32 v0, 1.0, v0 ; 060000F2 v_add_f32_e32 v0, v23, v0 ; 02000117 v_sub_f32_e64 v0, v0, v27 clamp ; D1028000 00023700 v_add_f32_e64 v12, v0, v0 clamp ; D101800C 00020100 v_mad_f32 v0, v0, 2.0, -1.0 ; D1C10000 03CDE900 v_max_f32_e32 v0, 0, v0 ; 16000080 v_mac_f32_e32 v0, v3, v12 ; 2C001903 v_mul_f32_e64 v0, v0, v2 clamp ; D1058000 00020500 v_add_f32_e32 v0, -0.5, v0 ; 020000F1 v_mad_f32 v0, v0, 4.0, 0.5 clamp ; D1C18000 03C1ED00 v_mac_f32_e32 v10, v0, v6 ; 2C140D00 v_mac_f32_e32 v7, v0, v4 ; 2C0E0900 v_mac_f32_e32 v9, v0, v5 ; 2C120B00 v_cvt_pkrtz_f16_f32 v0, v7, v9 ; D2960000 00021307 v_cvt_pkrtz_f16_f32 v2, v10, v19 ; D2960002 0002270A exp mrt0 v0, v0, v2, v2 compr ; C400040F 00000200 exp mrt1 v1, v8, v11, v21 done vm ; C400181F 150B0801 s_endpgm ; BF810000 *** SHADER CONFIG *** SPI_PS_INPUT_ADDR = 0x0002 SPI_PS_INPUT_ENA = 0x0002 *** SHADER STATS *** SGPRS: 48 VGPRS: 36 Spilled SGPRs: 0 Spilled VGPRs: 0 Private memory VGPRs: 0 Code Size: 1228 bytes LDS: 0 blocks Scratch: 0 bytes per wave Max Waves: 7 ********************