Oct 25 01:28:02 Linux version 4.19.0-rc8-drm (...) (gcc version 8.2.1 20181011 (Red Hat 8.2.1-4) (GCC)) #14 SMP Thu Oct 25 01:03:10 PDT 2018 Oct 25 01:28:02 Command line: BOOT_IMAGE=/vmlinuz-4.19.0-rc8-drm root=/dev/mapper/luks-7d238e07-c0ca-40f5-b0b8-5272c02bd87b ro rd.luks.uuid=luks-7d238e07-c0ca-40f5-b0b8-5272c02bd87b rhgb quiet intel_iommu=on LANG=en_US.UTF-8 i915.fastboot=1 drm.debug=0x1e Oct 25 01:28:02 x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers' Oct 25 01:28:02 x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers' Oct 25 01:28:02 x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers' Oct 25 01:28:02 x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers' Oct 25 01:28:02 x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR' Oct 25 01:28:02 x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256 Oct 25 01:28:02 x86/fpu: xstate_offset[3]: 832, xstate_sizes[3]: 64 Oct 25 01:28:02 x86/fpu: xstate_offset[4]: 896, xstate_sizes[4]: 64 Oct 25 01:28:02 x86/fpu: Enabled xstate features 0x1f, context size is 960 bytes, using 'compacted' format. Oct 25 01:28:02 BIOS-provided physical RAM map: Oct 25 01:28:02 BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable Oct 25 01:28:02 BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved Oct 25 01:28:02 BIOS-e820: [mem 0x0000000000059000-0x000000000009dfff] usable Oct 25 01:28:02 BIOS-e820: [mem 0x000000000009e000-0x00000000000fffff] reserved Oct 25 01:28:02 BIOS-e820: [mem 0x0000000000100000-0x0000000074024fff] usable Oct 25 01:28:02 BIOS-e820: [mem 0x0000000074025000-0x0000000074376fff] reserved Oct 25 01:28:02 BIOS-e820: [mem 0x0000000074377000-0x0000000074e07fff] usable Oct 25 01:28:02 BIOS-e820: [mem 0x0000000074e08000-0x0000000074e08fff] ACPI NVS Oct 25 01:28:02 BIOS-e820: [mem 0x0000000074e09000-0x0000000074e52fff] reserved Oct 25 01:28:02 BIOS-e820: [mem 0x0000000074e53000-0x000000007507dfff] usable Oct 25 01:28:02 BIOS-e820: [mem 0x000000007507e000-0x000000007507efff] reserved Oct 25 01:28:02 BIOS-e820: [mem 0x000000007507f000-0x000000007ac7efff] usable Oct 25 01:28:02 BIOS-e820: [mem 0x000000007ac7f000-0x000000007af4efff] reserved Oct 25 01:28:02 BIOS-e820: [mem 0x000000007af4f000-0x000000007af9efff] ACPI NVS Oct 25 01:28:02 BIOS-e820: [mem 0x000000007af9f000-0x000000007affefff] ACPI data Oct 25 01:28:02 BIOS-e820: [mem 0x000000007afff000-0x000000007affffff] usable Oct 25 01:28:02 BIOS-e820: [mem 0x000000007b000000-0x000000007fffffff] reserved Oct 25 01:28:02 BIOS-e820: [mem 0x00000000e00fa000-0x00000000e00fafff] reserved Oct 25 01:28:02 BIOS-e820: [mem 0x00000000e00fd000-0x00000000e00fdfff] reserved Oct 25 01:28:02 BIOS-e820: [mem 0x00000000fe000000-0x00000000fe010fff] reserved Oct 25 01:28:02 BIOS-e820: [mem 0x00000000ff939000-0x00000000ff968fff] reserved Oct 25 01:28:02 BIOS-e820: [mem 0x0000000100000000-0x000000047effffff] usable Oct 25 01:28:02 NX (Execute Disable) protection: active Oct 25 01:28:02 e820: update [mem 0x72425018-0x72433c57] usable ==> usable Oct 25 01:28:02 e820: update [mem 0x72425018-0x72433c57] usable ==> usable Oct 25 01:28:02 e820: update [mem 0x72413018-0x724240d5] usable ==> usable Oct 25 01:28:02 e820: update [mem 0x72413018-0x724240d5] usable ==> usable Oct 25 01:28:02 extended physical RAM map: Oct 25 01:28:02 reserve setup_data: [mem 0x0000000000000000-0x0000000000057fff] usable Oct 25 01:28:02 reserve setup_data: [mem 0x0000000000058000-0x0000000000058fff] reserved Oct 25 01:28:02 reserve setup_data: [mem 0x0000000000059000-0x000000000009dfff] usable Oct 25 01:28:02 reserve setup_data: [mem 0x000000000009e000-0x00000000000fffff] reserved Oct 25 01:28:02 reserve setup_data: [mem 0x0000000000100000-0x0000000072413017] usable Oct 25 01:28:02 reserve setup_data: [mem 0x0000000072413018-0x00000000724240d5] usable Oct 25 01:28:02 reserve setup_data: [mem 0x00000000724240d6-0x0000000072425017] usable Oct 25 01:28:02 reserve setup_data: [mem 0x0000000072425018-0x0000000072433c57] usable Oct 25 01:28:02 reserve setup_data: [mem 0x0000000072433c58-0x0000000074024fff] usable Oct 25 01:28:02 reserve setup_data: [mem 0x0000000074025000-0x0000000074376fff] reserved Oct 25 01:28:02 reserve setup_data: [mem 0x0000000074377000-0x0000000074e07fff] usable Oct 25 01:28:02 reserve setup_data: [mem 0x0000000074e08000-0x0000000074e08fff] ACPI NVS Oct 25 01:28:02 reserve setup_data: [mem 0x0000000074e09000-0x0000000074e52fff] reserved Oct 25 01:28:02 reserve setup_data: [mem 0x0000000074e53000-0x000000007507dfff] usable Oct 25 01:28:02 reserve setup_data: [mem 0x000000007507e000-0x000000007507efff] reserved Oct 25 01:28:02 reserve setup_data: [mem 0x000000007507f000-0x000000007ac7efff] usable Oct 25 01:28:02 reserve setup_data: [mem 0x000000007ac7f000-0x000000007af4efff] reserved Oct 25 01:28:02 reserve setup_data: [mem 0x000000007af4f000-0x000000007af9efff] ACPI NVS Oct 25 01:28:02 reserve setup_data: [mem 0x000000007af9f000-0x000000007affefff] ACPI data Oct 25 01:28:02 reserve setup_data: [mem 0x000000007afff000-0x000000007affffff] usable Oct 25 01:28:02 reserve setup_data: [mem 0x000000007b000000-0x000000007fffffff] reserved Oct 25 01:28:02 reserve setup_data: [mem 0x00000000e00fa000-0x00000000e00fafff] reserved Oct 25 01:28:02 reserve setup_data: [mem 0x00000000e00fd000-0x00000000e00fdfff] reserved Oct 25 01:28:02 reserve setup_data: [mem 0x00000000fe000000-0x00000000fe010fff] reserved Oct 25 01:28:02 reserve setup_data: [mem 0x00000000ff939000-0x00000000ff968fff] reserved Oct 25 01:28:02 reserve setup_data: [mem 0x0000000100000000-0x000000047effffff] usable Oct 25 01:28:02 efi: EFI v2.40 by Apple Oct 25 01:28:02 efi: ACPI=0x7affe000 ACPI 2.0=0x7affe014 SMBIOS=0x7aeff000 SMBIOS 3.0=0x7aefd000 Oct 25 01:28:02 SMBIOS 3.0.0 present. Oct 25 01:28:02 DMI: Apple Inc. MacBookPro13,3/Mac-A5C67F76ED83108C, BIOS MBP133.88Z.0247.B00.1806261159 06/26/2018 Oct 25 01:28:02 tsc: Detected 2900.000 MHz processor Oct 25 01:28:02 tsc: Detected 2904.000 MHz TSC Oct 25 01:28:02 e820: update [mem 0x00000000-0x00000fff] usable ==> reserved Oct 25 01:28:02 e820: remove [mem 0x000a0000-0x000fffff] usable Oct 25 01:28:02 last_pfn = 0x47f000 max_arch_pfn = 0x400000000 Oct 25 01:28:02 MTRR default type: write-back Oct 25 01:28:02 MTRR fixed ranges enabled: Oct 25 01:28:02 00000-9FFFF write-back Oct 25 01:28:02 A0000-BFFFF uncachable Oct 25 01:28:02 C0000-DFFFF write-protect Oct 25 01:28:02 E0000-FFFFF uncachable Oct 25 01:28:02 MTRR variable ranges enabled: Oct 25 01:28:02 0 base 0080000000 mask 7F80000000 uncachable Oct 25 01:28:02 1 base 007C000000 mask 7FFC000000 uncachable Oct 25 01:28:02 2 base 007B000000 mask 7FFF000000 uncachable Oct 25 01:28:02 3 base 4000000000 mask 4000000000 uncachable Oct 25 01:28:02 4 disabled Oct 25 01:28:02 5 disabled Oct 25 01:28:02 6 disabled Oct 25 01:28:02 7 disabled Oct 25 01:28:02 8 disabled Oct 25 01:28:02 9 disabled Oct 25 01:28:02 x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT Oct 25 01:28:02 last_pfn = 0x7b000 max_arch_pfn = 0x400000000 Oct 25 01:28:02 Base memory trampoline at [(____ptrval____)] 98000 size 24576 Oct 25 01:28:02 Using GB pages for direct mapping Oct 25 01:28:02 BRK [0x117001000, 0x117001fff] PGTABLE Oct 25 01:28:02 BRK [0x117002000, 0x117002fff] PGTABLE Oct 25 01:28:02 BRK [0x117003000, 0x117003fff] PGTABLE Oct 25 01:28:02 BRK [0x117004000, 0x117004fff] PGTABLE Oct 25 01:28:02 BRK [0x117005000, 0x117005fff] PGTABLE Oct 25 01:28:02 BRK [0x117006000, 0x117006fff] PGTABLE Oct 25 01:28:02 BRK [0x117007000, 0x117007fff] PGTABLE Oct 25 01:28:02 BRK [0x117008000, 0x117008fff] PGTABLE Oct 25 01:28:02 BRK [0x117009000, 0x117009fff] PGTABLE Oct 25 01:28:02 BRK [0x11700a000, 0x11700afff] PGTABLE Oct 25 01:28:02 BRK [0x11700b000, 0x11700bfff] PGTABLE Oct 25 01:28:02 BRK [0x11700c000, 0x11700cfff] PGTABLE Oct 25 01:28:02 Secure boot disabled Oct 25 01:28:02 RAMDISK: [mem 0x3beda000-0x3cfd1fff] Oct 25 01:28:02 ACPI: Early table checksum verification disabled Oct 25 01:28:02 ACPI: RSDP 0x000000007AFFE014 000024 (v02 APPLE ) Oct 25 01:28:02 ACPI: XSDT 0x000000007AFC6188 0000D4 (v01 APPLE Apple00 00000000 01000013) Oct 25 01:28:02 ACPI: FACP 0x000000007AFF8000 0000F4 (v05 APPLE Apple00 00000000 Loki 0000005F) Oct 25 01:28:02 ACPI: DSDT 0x000000007AFEB000 00869F (v02 APPLE MacBookP 00150001 INTL 20140424) Oct 25 01:28:02 ACPI: FACS 0x000000007AF9B000 000040 Oct 25 01:28:02 ACPI: UEFI 0x000000007AF9D000 000042 (v01 INTEL EDK2 00000002 01000013) Oct 25 01:28:02 ACPI: ECDT 0x000000007AFFA000 000053 (v01 APPLE Apple00 00000001 Loki 0000005F) Oct 25 01:28:02 ACPI: HPET 0x000000007AFF7000 000038 (v01 APPLE Apple00 00000001 Loki 0000005F) Oct 25 01:28:02 ACPI: APIC 0x000000007AFF6000 0000BC (v02 APPLE Apple00 00000001 Loki 0000005F) Oct 25 01:28:02 ACPI: MCFG 0x000000007AFF5000 00003C (v01 APPLE Apple00 00000001 Loki 0000005F) Oct 25 01:28:02 ACPI: SBST 0x000000007AFF4000 000030 (v01 APPLE Apple00 00000001 Loki 0000005F) Oct 25 01:28:02 ACPI: SSDT 0x000000007AFEA000 000024 (v01 APPLE SmcDppt 00001000 INTL 20140424) Oct 25 01:28:02 ACPI: SSDT 0x000000007AFE9000 0007FD (v02 APPLE PEG0GFX0 00001000 INTL 20140424) Oct 25 01:28:02 ACPI: SSDT 0x000000007AFE8000 000024 (v01 APPLE PEG0SSD0 00001000 INTL 20140424) Oct 25 01:28:02 ACPI: SSDT 0x000000007AFE5000 000031 (v01 APPLE SsdtS3 00001000 INTL 20140424) Oct 25 01:28:02 ACPI: SSDT 0x000000007AFE4000 0000DD (v01 APPLE SataAhci 00001000 INTL 20140424) Oct 25 01:28:02 ACPI: SSDT 0x000000007AFE3000 0000B8 (v01 APPLE Sdxc 00001000 INTL 20140424) Oct 25 01:28:02 ACPI: SSDT 0x000000007AFCE000 00996E (v02 APPLE TbtPEG12 00001000 INTL 20140424) Oct 25 01:28:02 ACPI: SSDT 0x000000007AFCD000 000C32 (v02 APPLE Xhci 00001000 INTL 20140424) Oct 25 01:28:02 ACPI: SSDT 0x000000007AFCC000 000612 (v02 PmRef Cpu0Ist 00003000 INTL 20140424) Oct 25 01:28:02 ACPI: SSDT 0x000000007AFCB000 0005AA (v02 PmRef ApIst 00003000 INTL 20140424) Oct 25 01:28:02 ACPI: SSDT 0x000000007AFCA000 000295 (v02 PmRef Cpu0Cst 00003001 INTL 20140424) Oct 25 01:28:02 ACPI: SSDT 0x000000007AFC9000 000119 (v02 PmRef ApCst 00003000 INTL 20140424) Oct 25 01:28:02 ACPI: SSDT 0x000000007AFC8000 000EEF (v02 CpuRef CpuSsdt 00003000 INTL 20140424) Oct 25 01:28:02 ACPI: DMAR 0x000000007AFC7000 000160 (v01 APPLE SKL 00000001 INTL 00000001) Oct 25 01:28:02 ACPI: VFCT 0x000000007AFB7000 00EC84 (v01 APPLE Apple00 00000001 AMD 31504F47) Oct 25 01:28:02 ACPI: DMI detected to setup _OSI("Darwin"): Apple hardware Oct 25 01:28:02 ACPI: Local APIC address 0xfee00000 Oct 25 01:28:02 No NUMA configuration found Oct 25 01:28:02 Faking a node at [mem 0x0000000000000000-0x000000047effffff] Oct 25 01:28:02 NODE_DATA(0) allocated [mem 0x47efd5000-0x47effffff] Oct 25 01:28:02 Zone ranges: Oct 25 01:28:02 DMA [mem 0x0000000000001000-0x0000000000ffffff] Oct 25 01:28:02 DMA32 [mem 0x0000000001000000-0x00000000ffffffff] Oct 25 01:28:02 Normal [mem 0x0000000100000000-0x000000047effffff] Oct 25 01:28:02 Device empty Oct 25 01:28:02 Movable zone start for each node Oct 25 01:28:02 Early memory node ranges Oct 25 01:28:02 node 0: [mem 0x0000000000001000-0x0000000000057fff] Oct 25 01:28:02 node 0: [mem 0x0000000000059000-0x000000000009dfff] Oct 25 01:28:02 node 0: [mem 0x0000000000100000-0x0000000074024fff] Oct 25 01:28:02 node 0: [mem 0x0000000074377000-0x0000000074e07fff] Oct 25 01:28:02 node 0: [mem 0x0000000074e53000-0x000000007507dfff] Oct 25 01:28:02 node 0: [mem 0x000000007507f000-0x000000007ac7efff] Oct 25 01:28:02 node 0: [mem 0x000000007afff000-0x000000007affffff] Oct 25 01:28:02 node 0: [mem 0x0000000100000000-0x000000047effffff] Oct 25 01:28:02 Reserved but unavailable: 22402 pages Oct 25 01:28:02 Initmem setup node 0 [mem 0x0000000000001000-0x000000047effffff] Oct 25 01:28:02 On node 0 totalpages: 4167806 Oct 25 01:28:02 DMA zone: 64 pages used for memmap Oct 25 01:28:02 DMA zone: 21 pages reserved Oct 25 01:28:02 DMA zone: 3996 pages, LIFO batch:0 Oct 25 01:28:02 DMA32 zone: 7780 pages used for memmap Oct 25 01:28:02 DMA32 zone: 497890 pages, LIFO batch:63 Oct 25 01:28:02 Normal zone: 57280 pages used for memmap Oct 25 01:28:02 Normal zone: 3665920 pages, LIFO batch:63 Oct 25 01:28:02 Reserving Intel graphics memory at [mem 0x7c000000-0x7fffffff] Oct 25 01:28:02 ACPI: PM-Timer IO Port: 0x1808 Oct 25 01:28:02 ACPI: Local APIC address 0xfee00000 Oct 25 01:28:02 ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) Oct 25 01:28:02 ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1]) Oct 25 01:28:02 ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1]) Oct 25 01:28:02 ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1]) Oct 25 01:28:02 ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1]) Oct 25 01:28:02 ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1]) Oct 25 01:28:02 ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1]) Oct 25 01:28:02 ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1]) Oct 25 01:28:02 IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23 Oct 25 01:28:02 ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) Oct 25 01:28:02 ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) Oct 25 01:28:02 ACPI: IRQ0 used by override. Oct 25 01:28:02 ACPI: IRQ9 used by override. Oct 25 01:28:02 Using ACPI (MADT) for SMP configuration information Oct 25 01:28:02 ACPI: HPET id: 0x8086a201 base: 0xfed00000 Oct 25 01:28:02 smpboot: Allowing 8 CPUs, 0 hotplug CPUs Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x00000000-0x00000fff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x00058000-0x00058fff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x0009e000-0x000fffff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x72413000-0x72413fff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x72424000-0x72424fff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x72425000-0x72425fff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x72433000-0x72433fff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x74025000-0x74376fff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x74e08000-0x74e08fff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x74e09000-0x74e52fff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x7507e000-0x7507efff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x7ac7f000-0x7af4efff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x7af4f000-0x7af9efff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x7af9f000-0x7affefff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x7b000000-0x7fffffff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0x80000000-0xe00f9fff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0xe00fa000-0xe00fafff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0xe00fb000-0xe00fcfff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0xe00fd000-0xe00fdfff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0xe00fe000-0xfdffffff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0xfe000000-0xfe010fff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0xfe011000-0xff938fff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0xff939000-0xff968fff] Oct 25 01:28:02 PM: Registered nosave memory: [mem 0xff969000-0xffffffff] Oct 25 01:28:02 [mem 0x80000000-0xe00f9fff] available for PCI devices Oct 25 01:28:02 Booting paravirtualized kernel on bare hardware Oct 25 01:28:02 clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns Oct 25 01:28:02 random: get_random_bytes called from start_kernel+0x98/0x54e with crng_init=0 Oct 25 01:28:02 setup_percpu: NR_CPUS:64 nr_cpumask_bits:64 nr_cpu_ids:8 nr_node_ids:1 Oct 25 01:28:02 percpu: Embedded 494 pages/cpu @(____ptrval____) s1982680 r8192 d32552 u2097152 Oct 25 01:28:02 pcpu-alloc: s1982680 r8192 d32552 u2097152 alloc=1*2097152 Oct 25 01:28:02 pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [0] 7 Oct 25 01:28:02 Built 1 zonelists, mobility grouping on. Total pages: 4102661 Oct 25 01:28:02 Policy zone: Normal Oct 25 01:28:02 Kernel command line: BOOT_IMAGE=/vmlinuz-4.19.0-rc8-drm root=/dev/mapper/luks-7d238e07-c0ca-40f5-b0b8-5272c02bd87b ro rd.luks.uuid=luks-7d238e07-c0ca-40f5-b0b8-5272c02bd87b rhgb quiet intel_iommu=on LANG=en_US.UTF-8 i915.fastboot=1 drm.debug=0x1e Oct 25 01:28:02 DMAR: IOMMU enabled Oct 25 01:28:02 Memory: 16142468K/16671224K available (14348K kernel code, 1739K rwdata, 4156K rodata, 3936K init, 17016K bss, 528756K reserved, 0K cma-reserved) Oct 25 01:28:02 SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 Oct 25 01:28:02 Kernel/User page tables isolation: enabled Oct 25 01:28:02 ftrace: allocating 38572 entries in 151 pages Oct 25 01:28:02 Running RCU self tests Oct 25 01:28:02 rcu: Hierarchical RCU implementation. Oct 25 01:28:02 rcu: RCU lockdep checking is enabled. Oct 25 01:28:02 rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=8. Oct 25 01:28:02 Tasks RCU enabled. Oct 25 01:28:02 rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8 Oct 25 01:28:02 NR_IRQS: 4352, nr_irqs: 488, preallocated irqs: 16 Oct 25 01:28:02 rcu: Offload RCU callbacks from CPUs: (none). Oct 25 01:28:02 Console: colour dummy device 80x25 Oct 25 01:28:02 console [tty0] enabled Oct 25 01:28:02 Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar Oct 25 01:28:02 ... MAX_LOCKDEP_SUBCLASSES: 8 Oct 25 01:28:02 ... MAX_LOCK_DEPTH: 48 Oct 25 01:28:02 ... MAX_LOCKDEP_KEYS: 8191 Oct 25 01:28:02 ... CLASSHASH_SIZE: 4096 Oct 25 01:28:02 ... MAX_LOCKDEP_ENTRIES: 32768 Oct 25 01:28:02 ... MAX_LOCKDEP_CHAINS: 131072 Oct 25 01:28:02 ... CHAINHASH_SIZE: 65536 Oct 25 01:28:02 memory used by lock dependency info: 10463 kB Oct 25 01:28:02 per task-struct memory footprint: 2688 bytes Oct 25 01:28:02 ACPI: Core revision 20180810 Oct 25 01:28:02 clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635855245 ns Oct 25 01:28:02 hpet clockevent registered Oct 25 01:28:02 APIC: Switch to symmetric I/O mode setup Oct 25 01:28:02 DMAR: Host address width 39 Oct 25 01:28:02 DMAR: DRHD base: 0x000000fed90000 flags: 0x0 Oct 25 01:28:02 DMAR: dmar0: reg_base_addr fed90000 ver 1:0 cap 1c0000c40660462 ecap 7e3ff0501e Oct 25 01:28:02 DMAR: DRHD base: 0x000000fed91000 flags: 0x1 Oct 25 01:28:02 DMAR: dmar1: reg_base_addr fed91000 ver 1:0 cap d2008c40660462 ecap f050da Oct 25 01:28:02 DMAR: RMRR base: 0x0000007b800000 end: 0x0000007fffffff Oct 25 01:28:02 DMAR: ANDD device: 1 name: \_SB.PCI0.I2C0 Oct 25 01:28:02 DMAR: ANDD device: 7 name: \_SB.PCI0.SPI0 Oct 25 01:28:02 DMAR: ANDD device: 8 name: \_SB.PCI0.SPI1 Oct 25 01:28:02 DMAR: ANDD device: 9 name: \_SB.PCI0.UA00 Oct 25 01:28:02 DMAR: ANDD device: a name: \_SB.PCI0.UA01 Oct 25 01:28:02 DMAR: ANDD device: b name: \_SB.PCI0.UA02 Oct 25 01:28:02 DMAR-IR: IOAPIC id 2 under DRHD base 0xfed91000 IOMMU 1 Oct 25 01:28:02 DMAR-IR: HPET id 0 under DRHD base 0xfed91000 Oct 25 01:28:02 DMAR-IR: Queued invalidation will be enabled to support x2apic and Intr-remapping. Oct 25 01:28:02 DMAR-IR: Enabled IRQ remapping in x2apic mode Oct 25 01:28:02 x2apic enabled Oct 25 01:28:02 Switched APIC routing to cluster x2apic. Oct 25 01:28:02 ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 Oct 25 01:28:02 clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x29dc05e54fc, max_idle_ns: 440795291716 ns Oct 25 01:28:02 Calibrating delay loop (skipped), value calculated using timer frequency.. 5808.00 BogoMIPS (lpj=2904000) Oct 25 01:28:02 pid_max: default: 32768 minimum: 301 Oct 25 01:28:02 Security Framework initialized Oct 25 01:28:02 Yama: becoming mindful. Oct 25 01:28:02 SELinux: Initializing. Oct 25 01:28:02 Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes) Oct 25 01:28:02 Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes) Oct 25 01:28:02 Mount-cache hash table entries: 32768 (order: 6, 262144 bytes) Oct 25 01:28:02 Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes) Oct 25 01:28:02 ENERGY_PERF_BIAS: Set to 'normal', was 'performance' Oct 25 01:28:02 ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8) Oct 25 01:28:02 mce: CPU supports 10 MCE banks Oct 25 01:28:02 CPU0: Thermal monitoring enabled (TM1) Oct 25 01:28:02 process: using mwait in idle threads Oct 25 01:28:02 Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8 Oct 25 01:28:02 Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4 Oct 25 01:28:02 Spectre V2 : Mitigation: Full generic retpoline Oct 25 01:28:02 Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch Oct 25 01:28:02 Spectre V2 : Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier Oct 25 01:28:02 Spectre V2 : Enabling Restricted Speculation for firmware calls Oct 25 01:28:02 Speculative Store Bypass: Mitigation: Speculative Store Bypass disabled via prctl and seccomp Oct 25 01:28:02 Freeing SMP alternatives memory: 36K Oct 25 01:28:02 TSC deadline timer enabled Oct 25 01:28:02 smpboot: CPU0: Intel(R) Core(TM) i7-6920HQ CPU @ 2.90GHz (family: 0x6, model: 0x5e, stepping: 0x3) Oct 25 01:28:02 Performance Events: PEBS fmt3+, Skylake events, 32-deep LBR, full-width counters, Intel PMU driver. Oct 25 01:28:02 ... version: 4 Oct 25 01:28:02 ... bit width: 48 Oct 25 01:28:02 ... generic registers: 4 Oct 25 01:28:02 ... value mask: 0000ffffffffffff Oct 25 01:28:02 ... max period: 00007fffffffffff Oct 25 01:28:02 ... fixed-purpose events: 3 Oct 25 01:28:02 ... event mask: 000000070000000f Oct 25 01:28:02 rcu: Hierarchical SRCU implementation. Oct 25 01:28:02 NMI watchdog: Enabled. Permanently consumes one hw-PMU counter. Oct 25 01:28:02 smp: Bringing up secondary CPUs ... Oct 25 01:28:02 x86: Booting SMP configuration: Oct 25 01:28:02 .... node #0, CPUs: #1 #2 #3 #4 #5 #6 #7 Oct 25 01:28:02 smp: Brought up 1 node, 8 CPUs Oct 25 01:28:02 smpboot: Max logical packages: 1 Oct 25 01:28:02 smpboot: Total of 8 processors activated (46464.00 BogoMIPS) Oct 25 01:28:02 devtmpfs: initialized Oct 25 01:28:02 x86/mm: Memory block size: 128MB Oct 25 01:28:02 PM: Registering ACPI NVS region [mem 0x74e08000-0x74e08fff] (4096 bytes) Oct 25 01:28:02 PM: Registering ACPI NVS region [mem 0x7af4f000-0x7af9efff] (327680 bytes) Oct 25 01:28:02 clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns Oct 25 01:28:02 futex hash table entries: 2048 (order: 6, 262144 bytes) Oct 25 01:28:02 pinctrl core: initialized pinctrl subsystem Oct 25 01:28:02 RTC time: 8:27:59, date: 10/25/18 Oct 25 01:28:02 NET: Registered protocol family 16 Oct 25 01:28:02 audit: initializing netlink subsys (disabled) Oct 25 01:28:02 audit: type=2000 audit(1540456078.043:1): state=initialized audit_enabled=0 res=1 Oct 25 01:28:02 cpuidle: using governor menu Oct 25 01:28:02 ACPI FADT declares the system doesn't support PCIe ASPM, so disable it Oct 25 01:28:02 ACPI: bus type PCI registered Oct 25 01:28:02 acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 Oct 25 01:28:02 PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) Oct 25 01:28:02 PCI: not using MMCONFIG Oct 25 01:28:02 PCI: Using configuration type 1 for base access Oct 25 01:28:02 HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages Oct 25 01:28:02 HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages Oct 25 01:28:02 cryptd: max_cpu_qlen set to 1000 Oct 25 01:28:02 ACPI: Disabled all _OSI OS vendors Oct 25 01:28:02 ACPI: Added _OSI(Module Device) Oct 25 01:28:02 ACPI: Added _OSI(Processor Device) Oct 25 01:28:02 ACPI: Added _OSI(3.0 _SCP Extensions) Oct 25 01:28:02 ACPI: Added _OSI(Processor Aggregator Device) Oct 25 01:28:02 ACPI: Added _OSI(Linux-Dell-Video) Oct 25 01:28:02 ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio) Oct 25 01:28:02 ACPI: Added _OSI(Darwin) Oct 25 01:28:02 ACPI: EC: EC started Oct 25 01:28:02 ACPI: EC: interrupt blocked Oct 25 01:28:02 ACPI: \: Used as first EC Oct 25 01:28:02 ACPI: \: GPE=0x7, EC_CMD/EC_SC=0x66, EC_DATA=0x62 Oct 25 01:28:02 ACPI: \: Used as boot ECDT EC to handle transactions Oct 25 01:28:02 ACPI: 14 ACPI AML tables successfully acquired and loaded Oct 25 01:28:02 ACPI: BIOS _OSI(Darwin) query honored via DMI Oct 25 01:28:02 ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored Oct 25 01:28:02 ACPI: Dynamic OEM Table Load: Oct 25 01:28:02 ACPI Error: AE_ALREADY_EXISTS, SSDT 0xFFFF93DFEB119000 Table is already loaded (20180810/tbdata-528) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU0.GCAP, AE_ALREADY_EXISTS (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU0._OSC, AE_ALREADY_EXISTS (20180810/psparse-516) Oct 25 01:28:02 ACPI: Marking method _OSC as Serialized because of AE_ALREADY_EXISTS error Oct 25 01:28:02 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU1.GCAP, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU1._OSC, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU2.GCAP, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU2._OSC, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU3.GCAP, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU3._OSC, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU4.GCAP, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU4._OSC, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU5.GCAP, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU5._OSC, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU6.GCAP, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU6._OSC, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU7.GCAP, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU7._OSC, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI: Dynamic OEM Table Load: Oct 25 01:28:02 ACPI Error: AE_ALREADY_EXISTS, SSDT 0xFFFF93DFEB7CA800 Table is already loaded (20180810/tbdata-528) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU0.GCAP, AE_ALREADY_EXISTS (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU0._PDC, AE_ALREADY_EXISTS (20180810/psparse-516) Oct 25 01:28:02 ACPI: Marking method _PDC as Serialized because of AE_ALREADY_EXISTS error Oct 25 01:28:02 ACPI: Dynamic OEM Table Load: Oct 25 01:28:02 ACPI Error: AE_ALREADY_EXISTS, SSDT 0xFFFF93DFEB119000 Table is already loaded (20180810/tbdata-528) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU1.APPT, AE_ALREADY_EXISTS (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU1.GCAP, AE_ALREADY_EXISTS (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU1._PDC, AE_ALREADY_EXISTS (20180810/psparse-516) Oct 25 01:28:02 ACPI: Marking method _PDC as Serialized because of AE_ALREADY_EXISTS error Oct 25 01:28:02 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU2.GCAP, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU2._PDC, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU3.GCAP, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU3._PDC, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU4.GCAP, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU4._PDC, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU5.GCAP, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU5._PDC, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU6.GCAP, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU6._PDC, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU7.GCAP, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI Error: Method parse/execution failed \_PR.CPU7._PDC, AE_NOT_FOUND (20180810/psparse-516) Oct 25 01:28:02 ACPI: Interpreter enabled Oct 25 01:28:02 ACPI: (supports S0 S3 S4 S5) Oct 25 01:28:02 ACPI: Using IOAPIC for interrupt routing Oct 25 01:28:02 PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) Oct 25 01:28:02 PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in ACPI motherboard resources Oct 25 01:28:02 PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug Oct 25 01:28:02 ACPI: Enabled 11 GPEs in block 00 to 7F Oct 25 01:28:02 ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) Oct 25 01:28:02 acpi PNP0A08:00: _OSC: OS assumes control of [PCIeHotplug SHPCHotplug AER PCIeCapability LTR] Oct 25 01:28:02 PCI host bridge to bus 0000:00 Oct 25 01:28:02 pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000c3fff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000c4000-0x000c7fff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000c8000-0x000cbfff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000cc000-0x000cffff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000e3fff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000e4000-0x000e7fff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000e8000-0x000ebfff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000ec000-0x000effff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x000f0000-0x000fffff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [mem 0x80000000-0xfeafffff window] Oct 25 01:28:02 pci_bus 0000:00: root bus resource [bus 00-ff] Oct 25 01:28:02 pci 0000:00:00.0: [8086:1910] type 00 class 0x060000 Oct 25 01:28:02 pci 0000:00:01.0: [8086:1901] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:00:01.0: PME# supported from D0 D3hot D3cold Oct 25 01:28:02 pci 0000:00:01.1: [8086:1905] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:00:01.1: PME# supported from D0 D3hot D3cold Oct 25 01:28:02 pci 0000:00:01.2: [8086:1909] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:00:01.2: PME# supported from D0 D3hot D3cold Oct 25 01:28:02 pci 0000:00:02.0: [8086:191b] type 00 class 0x030000 Oct 25 01:28:02 pci 0000:00:02.0: reg 0x10: [mem 0x81000000-0x81ffffff 64bit] Oct 25 01:28:02 pci 0000:00:02.0: reg 0x18: [mem 0xa0000000-0xafffffff 64bit pref] Oct 25 01:28:02 pci 0000:00:02.0: reg 0x20: [io 0x5000-0x503f] Oct 25 01:28:02 pci 0000:00:02.0: BAR 2: assigned to efifb Oct 25 01:28:02 pci 0000:00:14.0: [8086:a12f] type 00 class 0x0c0330 Oct 25 01:28:02 pci 0000:00:14.0: reg 0x10: [mem 0x82700000-0x8270ffff 64bit] Oct 25 01:28:02 pci 0000:00:14.0: PME# supported from D3hot D3cold Oct 25 01:28:02 pci 0000:00:15.0: [8086:a160] type 00 class 0x118000 Oct 25 01:28:02 pci 0000:00:15.0: reg 0x10: [mem 0x82728000-0x82728fff 64bit] Oct 25 01:28:02 pci 0000:00:16.0: [8086:a13a] type 00 class 0x078000 Oct 25 01:28:02 pci 0000:00:16.0: reg 0x10: [mem 0x82729000-0x82729fff 64bit] Oct 25 01:28:02 pci 0000:00:16.0: PME# supported from D3hot Oct 25 01:28:02 pci 0000:00:19.0: [8086:a166] type 00 class 0x118000 Oct 25 01:28:02 pci 0000:00:19.0: reg 0x10: [mem 0x8272a000-0x8272afff 64bit] Oct 25 01:28:02 pci 0000:00:1b.0: [8086:a167] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold Oct 25 01:28:02 pci 0000:00:1b.0: Intel SPT PCH root port ACS workaround enabled Oct 25 01:28:02 pci 0000:00:1c.0: [8086:a110] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold Oct 25 01:28:02 pci 0000:00:1c.0: Intel SPT PCH root port ACS workaround enabled Oct 25 01:28:02 pci 0000:00:1e.0: [8086:a127] type 00 class 0x118000 Oct 25 01:28:02 pci 0000:00:1e.0: reg 0x10: [mem 0x8272b000-0x8272bfff 64bit] Oct 25 01:28:02 pci 0000:00:1e.1: [8086:a128] type 00 class 0x118000 Oct 25 01:28:02 pci 0000:00:1e.1: reg 0x10: [mem 0x8272c000-0x8272cfff 64bit] Oct 25 01:28:02 pci 0000:00:1e.2: [8086:a129] type 00 class 0x118000 Oct 25 01:28:02 pci 0000:00:1e.2: reg 0x10: [mem 0x8272d000-0x8272dfff 64bit] Oct 25 01:28:02 pci 0000:00:1e.3: [8086:a12a] type 00 class 0x118000 Oct 25 01:28:02 pci 0000:00:1e.3: reg 0x10: [mem 0x8272e000-0x8272efff 64bit] Oct 25 01:28:02 pci 0000:00:1f.0: [8086:a151] type 00 class 0x060100 Oct 25 01:28:02 pci 0000:00:1f.2: [8086:a121] type 00 class 0x058000 Oct 25 01:28:02 pci 0000:00:1f.2: reg 0x10: [mem 0x82724000-0x82727fff] Oct 25 01:28:02 pci 0000:00:1f.3: [8086:a170] type 00 class 0x040300 Oct 25 01:28:02 pci 0000:00:1f.3: reg 0x10: [mem 0x82720000-0x82723fff 64bit] Oct 25 01:28:02 pci 0000:00:1f.3: reg 0x20: [mem 0x00000000-0x0000ffff 64bit] Oct 25 01:28:02 pci 0000:00:1f.3: PME# supported from D3hot D3cold Oct 25 01:28:02 pci 0000:00:1f.4: [8086:a123] type 00 class 0x0c0500 Oct 25 01:28:02 pci 0000:00:1f.4: reg 0x10: [mem 0x8272f000-0x8272f0ff 64bit] Oct 25 01:28:02 pci 0000:00:1f.4: reg 0x20: [io 0x5040-0x505f] Oct 25 01:28:02 pci 0000:01:00.0: [1002:67ef] type 00 class 0x030000 Oct 25 01:28:02 pci 0000:01:00.0: reg 0x10: [mem 0xb0000000-0xbfffffff 64bit pref] Oct 25 01:28:02 pci 0000:01:00.0: reg 0x18: [mem 0xc0000000-0xc01fffff 64bit pref] Oct 25 01:28:02 pci 0000:01:00.0: reg 0x20: [io 0x4000-0x40ff] Oct 25 01:28:02 pci 0000:01:00.0: reg 0x24: [mem 0x82600000-0x8263ffff] Oct 25 01:28:02 pci 0000:01:00.0: reg 0x30: [mem 0x82640000-0x8265ffff pref] Oct 25 01:28:02 pci 0000:01:00.0: supports D1 D2 Oct 25 01:28:02 pci 0000:01:00.1: [1002:aae0] type 00 class 0x040300 Oct 25 01:28:02 pci 0000:01:00.1: reg 0x10: [mem 0x82660000-0x82663fff 64bit] Oct 25 01:28:02 pci 0000:01:00.1: supports D1 D2 Oct 25 01:28:02 pci 0000:00:01.0: PCI bridge to [bus 01] Oct 25 01:28:02 pci 0000:00:01.0: bridge window [io 0x4000-0x4fff] Oct 25 01:28:02 pci 0000:00:01.0: bridge window [mem 0x82600000-0x826fffff] Oct 25 01:28:02 pci 0000:00:01.0: bridge window [mem 0xb0000000-0xc01fffff 64bit pref] Oct 25 01:28:02 pci 0000:04:00.0: [8086:1578] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:04:00.0: supports D1 D2 Oct 25 01:28:02 pci 0000:04:00.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:00:01.1: PCI bridge to [bus 04-79] Oct 25 01:28:02 pci 0000:00:01.1: bridge window [io 0x6000-0x9fff] Oct 25 01:28:02 pci 0000:00:01.1: bridge window [mem 0x82800000-0x909fffff] Oct 25 01:28:02 pci 0000:00:01.1: bridge window [mem 0xc0200000-0xce1fffff 64bit pref] Oct 25 01:28:02 pci 0000:05:00.0: [8086:15d3] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:05:00.0: supports D1 D2 Oct 25 01:28:02 pci 0000:05:00.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:05:01.0: [8086:15d3] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:05:01.0: supports D1 D2 Oct 25 01:28:02 pci 0000:05:01.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:05:02.0: [8086:15d3] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:05:02.0: supports D1 D2 Oct 25 01:28:02 pci 0000:05:02.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:05:04.0: [8086:15d3] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:05:04.0: supports D1 D2 Oct 25 01:28:02 pci 0000:05:04.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:04:00.0: PCI bridge to [bus 05-79] Oct 25 01:28:02 pci 0000:04:00.0: bridge window [io 0x6000-0x9fff] Oct 25 01:28:02 pci 0000:04:00.0: bridge window [mem 0x82800000-0x909fffff] Oct 25 01:28:02 pci 0000:04:00.0: bridge window [mem 0xc0200000-0xce1fffff 64bit pref] Oct 25 01:28:02 pci 0000:06:00.0: [8086:15d2] type 00 class 0x088000 Oct 25 01:28:02 pci 0000:06:00.0: reg 0x10: [mem 0x82900000-0x8293ffff] Oct 25 01:28:02 pci 0000:06:00.0: reg 0x14: [mem 0x82940000-0x82940fff] Oct 25 01:28:02 pci 0000:06:00.0: supports D1 D2 Oct 25 01:28:02 pci 0000:06:00.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:06:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x4 link at 0000:05:00.0 (capable of 31.504 Gb/s with 8 GT/s x4 link) Oct 25 01:28:02 pci 0000:05:00.0: PCI bridge to [bus 06] Oct 25 01:28:02 pci 0000:05:00.0: bridge window [mem 0x82900000-0x829fffff] Oct 25 01:28:02 pci 0000:05:01.0: PCI bridge to [bus 08-40] Oct 25 01:28:02 pci 0000:05:01.0: bridge window [io 0x6000-0x7fff] Oct 25 01:28:02 pci 0000:05:01.0: bridge window [mem 0x82a00000-0x899fffff] Oct 25 01:28:02 pci 0000:05:01.0: bridge window [mem 0xc0200000-0xc71fffff 64bit pref] Oct 25 01:28:02 pci 0000:07:00.0: [8086:15d4] type 00 class 0x0c0330 Oct 25 01:28:02 pci 0000:07:00.0: reg 0x10: [mem 0x82800000-0x8280ffff] Oct 25 01:28:02 pci 0000:07:00.0: supports D1 D2 Oct 25 01:28:02 pci 0000:07:00.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:07:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x4 link at 0000:05:02.0 (capable of 31.504 Gb/s with 8 GT/s x4 link) Oct 25 01:28:02 pci 0000:05:02.0: PCI bridge to [bus 07] Oct 25 01:28:02 pci 0000:05:02.0: bridge window [mem 0x82800000-0x828fffff] Oct 25 01:28:02 pci 0000:05:04.0: PCI bridge to [bus 41-79] Oct 25 01:28:02 pci 0000:05:04.0: bridge window [io 0x8000-0x9fff] Oct 25 01:28:02 pci 0000:05:04.0: bridge window [mem 0x89a00000-0x909fffff] Oct 25 01:28:02 pci 0000:05:04.0: bridge window [mem 0xc7200000-0xce1fffff 64bit pref] Oct 25 01:28:02 pci 0000:7a:00.0: [8086:1578] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:7a:00.0: supports D1 D2 Oct 25 01:28:02 pci 0000:7a:00.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:00:01.2: PCI bridge to [bus 7a-ef] Oct 25 01:28:02 pci 0000:00:01.2: bridge window [io 0xa000-0xdfff] Oct 25 01:28:02 pci 0000:00:01.2: bridge window [mem 0x90a00000-0x9ebfffff] Oct 25 01:28:02 pci 0000:00:01.2: bridge window [mem 0xce200000-0xdc1fffff 64bit pref] Oct 25 01:28:02 pci 0000:7b:00.0: [8086:15d3] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:7b:00.0: supports D1 D2 Oct 25 01:28:02 pci 0000:7b:00.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:7b:01.0: [8086:15d3] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:7b:01.0: supports D1 D2 Oct 25 01:28:02 pci 0000:7b:01.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:7b:02.0: [8086:15d3] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:7b:02.0: supports D1 D2 Oct 25 01:28:02 pci 0000:7b:02.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:7b:04.0: [8086:15d3] type 01 class 0x060400 Oct 25 01:28:02 pci 0000:7b:04.0: supports D1 D2 Oct 25 01:28:02 pci 0000:7b:04.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:7a:00.0: PCI bridge to [bus 7b-ef] Oct 25 01:28:02 pci 0000:7a:00.0: bridge window [io 0xa000-0xdfff] Oct 25 01:28:02 pci 0000:7a:00.0: bridge window [mem 0x90a00000-0x9ebfffff] Oct 25 01:28:02 pci 0000:7a:00.0: bridge window [mem 0xce200000-0xdc1fffff 64bit pref] Oct 25 01:28:02 pci 0000:7c:00.0: [8086:15d2] type 00 class 0x088000 Oct 25 01:28:02 pci 0000:7c:00.0: reg 0x10: [mem 0x90b00000-0x90b3ffff] Oct 25 01:28:02 pci 0000:7c:00.0: reg 0x14: [mem 0x90b40000-0x90b40fff] Oct 25 01:28:02 pci 0000:7c:00.0: supports D1 D2 Oct 25 01:28:02 pci 0000:7c:00.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:7c:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x4 link at 0000:7b:00.0 (capable of 31.504 Gb/s with 8 GT/s x4 link) Oct 25 01:28:02 pci 0000:7b:00.0: PCI bridge to [bus 7c] Oct 25 01:28:02 pci 0000:7b:00.0: bridge window [mem 0x90b00000-0x90bfffff] Oct 25 01:28:02 pci 0000:7b:01.0: PCI bridge to [bus 7e-b6] Oct 25 01:28:02 pci 0000:7b:01.0: bridge window [io 0xa000-0xbfff] Oct 25 01:28:02 pci 0000:7b:01.0: bridge window [mem 0x90c00000-0x97bfffff] Oct 25 01:28:02 pci 0000:7b:01.0: bridge window [mem 0xce200000-0xd51fffff 64bit pref] Oct 25 01:28:02 pci 0000:7d:00.0: [8086:15d4] type 00 class 0x0c0330 Oct 25 01:28:02 pci 0000:7d:00.0: reg 0x10: [mem 0x90a00000-0x90a0ffff] Oct 25 01:28:02 pci 0000:7d:00.0: supports D1 D2 Oct 25 01:28:02 pci 0000:7d:00.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:7d:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x4 link at 0000:7b:02.0 (capable of 31.504 Gb/s with 8 GT/s x4 link) Oct 25 01:28:02 pci 0000:7b:02.0: PCI bridge to [bus 7d] Oct 25 01:28:02 pci 0000:7b:02.0: bridge window [mem 0x90a00000-0x90afffff] Oct 25 01:28:02 pci 0000:7b:04.0: PCI bridge to [bus b7-ef] Oct 25 01:28:02 pci 0000:7b:04.0: bridge window [io 0xc000-0xdfff] Oct 25 01:28:02 pci 0000:7b:04.0: bridge window [mem 0x97c00000-0x9ebfffff] Oct 25 01:28:02 pci 0000:7b:04.0: bridge window [mem 0xd5200000-0xdc1fffff 64bit pref] Oct 25 01:28:02 pci 0000:02:00.0: [144d:a804] type 00 class 0x010802 Oct 25 01:28:02 pci 0000:02:00.0: reg 0x10: [mem 0x82500000-0x82503fff 64bit] Oct 25 01:28:02 pci 0000:02:00.0: reg 0x18: [io 0x3000-0x30ff] Oct 25 01:28:02 pci 0000:00:1b.0: PCI bridge to [bus 02] Oct 25 01:28:02 pci 0000:00:1b.0: bridge window [io 0x3000-0x3fff] Oct 25 01:28:02 pci 0000:00:1b.0: bridge window [mem 0x82500000-0x825fffff] Oct 25 01:28:02 pci 0000:03:00.0: [14e4:43ba] type 00 class 0x028000 Oct 25 01:28:02 pci 0000:03:00.0: reg 0x10: [mem 0x82400000-0x82407fff 64bit] Oct 25 01:28:02 pci 0000:03:00.0: reg 0x18: [mem 0x82000000-0x823fffff 64bit] Oct 25 01:28:02 pci 0000:03:00.0: supports D1 D2 Oct 25 01:28:02 pci 0000:03:00.0: PME# supported from D0 D1 D2 D3hot D3cold Oct 25 01:28:02 pci 0000:03:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:1c.0 (capable of 7.876 Gb/s with 8 GT/s x1 link) Oct 25 01:28:02 pci 0000:00:1c.0: PCI bridge to [bus 03] Oct 25 01:28:02 pci 0000:00:1c.0: bridge window [mem 0x82000000-0x824fffff] Oct 25 01:28:02 ACPI: PCI Interrupt Link [LNKA] (IRQs 1 3 4 5 6 7 10 12 14 15) *0 Oct 25 01:28:02 ACPI: PCI Interrupt Link [LNKB] (IRQs 1 3 4 5 6 7 11 12 14 15) *0 Oct 25 01:28:02 ACPI: PCI Interrupt Link [LNKC] (IRQs 1 3 4 5 6 7 10 12 14 15) *0 Oct 25 01:28:02 ACPI: PCI Interrupt Link [LNKD] (IRQs 1 3 4 5 6 7 11 12 14 15) *0 Oct 25 01:28:02 ACPI: PCI Interrupt Link [LNKE] (IRQs 1 3 4 5 6 7 10 12 14 15) *0 Oct 25 01:28:02 ACPI: PCI Interrupt Link [LNKF] (IRQs 1 3 4 5 6 7 11 12 14 15) *0 Oct 25 01:28:02 ACPI: PCI Interrupt Link [LNKG] (IRQs 1 3 4 5 6 7 10 12 14 15) *0 Oct 25 01:28:02 ACPI: PCI Interrupt Link [LNKH] (IRQs 1 3 4 5 6 7 11 12 14 15) *0 Oct 25 01:28:02 ACPI: EC: interrupt unblocked Oct 25 01:28:02 ACPI: EC: event unblocked Oct 25 01:28:02 ACPI: \_SB_.PCI0.LPCB.EC__: GPE=0x7, EC_CMD/EC_SC=0x66, EC_DATA=0x62 Oct 25 01:28:02 ACPI: \_SB_.PCI0.LPCB.EC__: Used as boot DSDT EC to handle transactions and events Oct 25 01:28:02 pci 0000:00:02.0: vgaarb: setting as boot VGA device Oct 25 01:28:02 pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none Oct 25 01:28:02 pci 0000:01:00.0: vgaarb: VGA device added: decodes=io+mem,owns=none,locks=none Oct 25 01:28:02 pci 0000:00:02.0: vgaarb: no bridge control possible Oct 25 01:28:02 pci 0000:01:00.0: vgaarb: bridge control possible Oct 25 01:28:02 vgaarb: loaded Oct 25 01:28:02 SCSI subsystem initialized Oct 25 01:28:02 libata version 3.00 loaded. Oct 25 01:28:02 ACPI: bus type USB registered Oct 25 01:28:02 usbcore: registered new interface driver usbfs Oct 25 01:28:02 usbcore: registered new interface driver hub Oct 25 01:28:02 usbcore: registered new device driver usb Oct 25 01:28:02 pps_core: LinuxPPS API ver. 1 registered Oct 25 01:28:02 pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti Oct 25 01:28:02 PTP clock support registered Oct 25 01:28:02 EDAC MC: Ver: 3.0.0 Oct 25 01:28:02 Registered efivars operations Oct 25 01:28:02 PCI: Using ACPI for IRQ routing Oct 25 01:28:02 PCI: pci_cache_line_size set to 64 bytes Oct 25 01:28:02 e820: reserve RAM buffer [mem 0x00058000-0x0005ffff] Oct 25 01:28:02 e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff] Oct 25 01:28:02 e820: reserve RAM buffer [mem 0x72413018-0x73ffffff] Oct 25 01:28:02 e820: reserve RAM buffer [mem 0x72425018-0x73ffffff] Oct 25 01:28:02 e820: reserve RAM buffer [mem 0x74025000-0x77ffffff] Oct 25 01:28:02 e820: reserve RAM buffer [mem 0x74e08000-0x77ffffff] Oct 25 01:28:02 e820: reserve RAM buffer [mem 0x7507e000-0x77ffffff] Oct 25 01:28:02 e820: reserve RAM buffer [mem 0x7ac7f000-0x7bffffff] Oct 25 01:28:02 e820: reserve RAM buffer [mem 0x7b000000-0x7bffffff] Oct 25 01:28:02 e820: reserve RAM buffer [mem 0x47f000000-0x47fffffff] Oct 25 01:28:02 NetLabel: Initializing Oct 25 01:28:02 NetLabel: domain hash size = 128 Oct 25 01:28:02 NetLabel: protocols = UNLABELED CIPSOv4 CALIPSO Oct 25 01:28:02 NetLabel: unlabeled traffic allowed by default Oct 25 01:28:02 hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 Oct 25 01:28:02 hpet0: 8 comparators, 64-bit 24.000000 MHz counter Oct 25 01:28:02 clocksource: Switched to clocksource tsc-early Oct 25 01:28:02 VFS: Disk quotas dquot_6.6.0 Oct 25 01:28:02 VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) Oct 25 01:28:02 pnp: PnP ACPI init Oct 25 01:28:02 system 00:00: [io 0xffff] has been reserved Oct 25 01:28:02 system 00:00: [io 0x1800-0x18fe] has been reserved Oct 25 01:28:02 system 00:00: [io 0x0800-0x087f] has been reserved Oct 25 01:28:02 system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active) Oct 25 01:28:02 pnp 00:01: Plug and Play ACPI device, IDs PNP0b00 (active) Oct 25 01:28:02 pnp 00:02: Plug and Play ACPI device, IDs APP000b (active) Oct 25 01:28:02 system 00:03: [mem 0xfed10000-0xfed17fff] has been reserved Oct 25 01:28:02 system 00:03: [mem 0xfed18000-0xfed18fff] has been reserved Oct 25 01:28:02 system 00:03: [mem 0xfed19000-0xfed19fff] has been reserved Oct 25 01:28:02 system 00:03: [mem 0xe0000000-0xefffffff] could not be reserved Oct 25 01:28:02 system 00:03: [mem 0xfd000000-0xfe7fffff] could not be reserved Oct 25 01:28:02 system 00:03: [mem 0xfed20000-0xfed3ffff] has been reserved Oct 25 01:28:02 system 00:03: [mem 0xfed90000-0xfed93fff] could not be reserved Oct 25 01:28:02 system 00:03: [mem 0xfed45000-0xfed8ffff] has been reserved Oct 25 01:28:02 system 00:03: [mem 0xff000000-0xffffffff] could not be reserved Oct 25 01:28:02 system 00:03: [mem 0xfee00000-0xfeefffff] has been reserved Oct 25 01:28:02 system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active) Oct 25 01:28:02 system 00:04: [mem 0x20000000-0x201fffff] could not be reserved Oct 25 01:28:02 system 00:04: [mem 0x40000000-0x401fffff] could not be reserved Oct 25 01:28:02 system 00:04: Plug and Play ACPI device, IDs PNP0c01 (active) Oct 25 01:28:02 pnp: PnP ACPI: found 5 devices Oct 25 01:28:02 pci 0000:00:02.0: assigning 5 device properties Oct 25 01:28:02 pci 0000:01:00.0: assigning 44 device properties Oct 25 01:28:02 pci 0000:06:00.0: assigning 8 device properties Oct 25 01:28:02 pci 0000:7c:00.0: assigning 8 device properties Oct 25 01:28:02 pci 0000:00:1f.3: assigning 5 device properties Oct 25 01:28:02 clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns Oct 25 01:28:02 pci 0000:05:02.0: bridge window [io 0x1000-0x0fff] to [bus 07] add_size 1000 Oct 25 01:28:02 pci 0000:05:02.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 07] add_size 200000 add_align 100000 Oct 25 01:28:02 pci 0000:7b:02.0: bridge window [io 0x1000-0x0fff] to [bus 7d] add_size 1000 Oct 25 01:28:02 pci 0000:7b:02.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 7d] add_size 200000 add_align 100000 Oct 25 01:28:02 pci 0000:00:1f.3: BAR 4: assigned [mem 0x80000000-0x8000ffff 64bit] Oct 25 01:28:02 pci 0000:00:01.0: PCI bridge to [bus 01] Oct 25 01:28:02 pci 0000:00:01.0: bridge window [io 0x4000-0x4fff] Oct 25 01:28:02 pci 0000:00:01.0: bridge window [mem 0x82600000-0x826fffff] Oct 25 01:28:02 pci 0000:00:01.0: bridge window [mem 0xb0000000-0xc01fffff 64bit pref] Oct 25 01:28:02 pci 0000:05:02.0: BAR 15: no space for [mem size 0x00200000 64bit pref] Oct 25 01:28:02 pci 0000:05:02.0: BAR 15: failed to assign [mem size 0x00200000 64bit pref] Oct 25 01:28:02 pci 0000:05:02.0: BAR 13: no space for [io size 0x1000] Oct 25 01:28:02 pci 0000:05:02.0: BAR 13: failed to assign [io size 0x1000] Oct 25 01:28:02 pci 0000:05:02.0: BAR 15: no space for [mem size 0x00200000 64bit pref] Oct 25 01:28:02 pci 0000:05:02.0: BAR 15: failed to assign [mem size 0x00200000 64bit pref] Oct 25 01:28:02 pci 0000:05:02.0: BAR 13: no space for [io size 0x1000] Oct 25 01:28:02 pci 0000:05:02.0: BAR 13: failed to assign [io size 0x1000] Oct 25 01:28:02 pci 0000:05:00.0: PCI bridge to [bus 06] Oct 25 01:28:02 pci 0000:05:00.0: bridge window [mem 0x82900000-0x829fffff] Oct 25 01:28:02 pci 0000:05:01.0: PCI bridge to [bus 08-40] Oct 25 01:28:02 pci 0000:05:01.0: bridge window [io 0x6000-0x7fff] Oct 25 01:28:02 pci 0000:05:01.0: bridge window [mem 0x82a00000-0x899fffff] Oct 25 01:28:02 pci 0000:05:01.0: bridge window [mem 0xc0200000-0xc71fffff 64bit pref] Oct 25 01:28:02 pci 0000:05:02.0: PCI bridge to [bus 07] Oct 25 01:28:02 pci 0000:05:02.0: bridge window [mem 0x82800000-0x828fffff] Oct 25 01:28:02 pci 0000:05:04.0: PCI bridge to [bus 41-79] Oct 25 01:28:02 pci 0000:05:04.0: bridge window [io 0x8000-0x9fff] Oct 25 01:28:02 pci 0000:05:04.0: bridge window [mem 0x89a00000-0x909fffff] Oct 25 01:28:02 pci 0000:05:04.0: bridge window [mem 0xc7200000-0xce1fffff 64bit pref] Oct 25 01:28:02 pci 0000:04:00.0: PCI bridge to [bus 05-79] Oct 25 01:28:02 pci 0000:04:00.0: bridge window [io 0x6000-0x9fff] Oct 25 01:28:02 pci 0000:04:00.0: bridge window [mem 0x82800000-0x909fffff] Oct 25 01:28:02 pci 0000:04:00.0: bridge window [mem 0xc0200000-0xce1fffff 64bit pref] Oct 25 01:28:02 pci 0000:00:01.1: PCI bridge to [bus 04-79] Oct 25 01:28:02 pci 0000:00:01.1: bridge window [io 0x6000-0x9fff] Oct 25 01:28:02 pci 0000:00:01.1: bridge window [mem 0x82800000-0x909fffff] Oct 25 01:28:02 pci 0000:00:01.1: bridge window [mem 0xc0200000-0xce1fffff 64bit pref] Oct 25 01:28:02 pci 0000:7b:02.0: BAR 15: no space for [mem size 0x00200000 64bit pref] Oct 25 01:28:02 pci 0000:7b:02.0: BAR 15: failed to assign [mem size 0x00200000 64bit pref] Oct 25 01:28:02 pci 0000:7b:02.0: BAR 13: no space for [io size 0x1000] Oct 25 01:28:02 pci 0000:7b:02.0: BAR 13: failed to assign [io size 0x1000] Oct 25 01:28:02 pci 0000:7b:02.0: BAR 15: no space for [mem size 0x00200000 64bit pref] Oct 25 01:28:02 pci 0000:7b:02.0: BAR 15: failed to assign [mem size 0x00200000 64bit pref] Oct 25 01:28:02 pci 0000:7b:02.0: BAR 13: no space for [io size 0x1000] Oct 25 01:28:02 pci 0000:7b:02.0: BAR 13: failed to assign [io size 0x1000] Oct 25 01:28:02 pci 0000:7b:00.0: PCI bridge to [bus 7c] Oct 25 01:28:02 pci 0000:7b:00.0: bridge window [mem 0x90b00000-0x90bfffff] Oct 25 01:28:02 pci 0000:7b:01.0: PCI bridge to [bus 7e-b6] Oct 25 01:28:02 pci 0000:7b:01.0: bridge window [io 0xa000-0xbfff] Oct 25 01:28:02 pci 0000:7b:01.0: bridge window [mem 0x90c00000-0x97bfffff] Oct 25 01:28:02 pci 0000:7b:01.0: bridge window [mem 0xce200000-0xd51fffff 64bit pref] Oct 25 01:28:02 pci 0000:7b:02.0: PCI bridge to [bus 7d] Oct 25 01:28:02 pci 0000:7b:02.0: bridge window [mem 0x90a00000-0x90afffff] Oct 25 01:28:02 pci 0000:7b:04.0: PCI bridge to [bus b7-ef] Oct 25 01:28:02 pci 0000:7b:04.0: bridge window [io 0xc000-0xdfff] Oct 25 01:28:02 pci 0000:7b:04.0: bridge window [mem 0x97c00000-0x9ebfffff] Oct 25 01:28:02 pci 0000:7b:04.0: bridge window [mem 0xd5200000-0xdc1fffff 64bit pref] Oct 25 01:28:02 pci 0000:7a:00.0: PCI bridge to [bus 7b-ef] Oct 25 01:28:02 pci 0000:7a:00.0: bridge window [io 0xa000-0xdfff] Oct 25 01:28:02 pci 0000:7a:00.0: bridge window [mem 0x90a00000-0x9ebfffff] Oct 25 01:28:02 pci 0000:7a:00.0: bridge window [mem 0xce200000-0xdc1fffff 64bit pref] Oct 25 01:28:02 pci 0000:00:01.2: PCI bridge to [bus 7a-ef] Oct 25 01:28:02 pci 0000:00:01.2: bridge window [io 0xa000-0xdfff] Oct 25 01:28:02 pci 0000:00:01.2: bridge window [mem 0x90a00000-0x9ebfffff] Oct 25 01:28:02 pci 0000:00:01.2: bridge window [mem 0xce200000-0xdc1fffff 64bit pref] Oct 25 01:28:02 pci 0000:00:1b.0: PCI bridge to [bus 02] Oct 25 01:28:02 pci 0000:00:1b.0: bridge window [io 0x3000-0x3fff] Oct 25 01:28:02 pci 0000:00:1b.0: bridge window [mem 0x82500000-0x825fffff] Oct 25 01:28:02 pci 0000:00:1c.0: PCI bridge to [bus 03] Oct 25 01:28:02 pci 0000:00:1c.0: bridge window [mem 0x82000000-0x824fffff] Oct 25 01:28:02 pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7 window] Oct 25 01:28:02 pci_bus 0000:00: resource 5 [io 0x0d00-0xffff window] Oct 25 01:28:02 pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window] Oct 25 01:28:02 pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000c3fff window] Oct 25 01:28:02 pci_bus 0000:00: resource 8 [mem 0x000c4000-0x000c7fff window] Oct 25 01:28:02 pci_bus 0000:00: resource 9 [mem 0x000c8000-0x000cbfff window] Oct 25 01:28:02 pci_bus 0000:00: resource 10 [mem 0x000cc000-0x000cffff window] Oct 25 01:28:02 pci_bus 0000:00: resource 11 [mem 0x000d0000-0x000d3fff window] Oct 25 01:28:02 pci_bus 0000:00: resource 12 [mem 0x000d4000-0x000d7fff window] Oct 25 01:28:02 pci_bus 0000:00: resource 13 [mem 0x000d8000-0x000dbfff window] Oct 25 01:28:02 pci_bus 0000:00: resource 14 [mem 0x000dc000-0x000dffff window] Oct 25 01:28:02 pci_bus 0000:00: resource 15 [mem 0x000e0000-0x000e3fff window] Oct 25 01:28:02 pci_bus 0000:00: resource 16 [mem 0x000e4000-0x000e7fff window] Oct 25 01:28:02 pci_bus 0000:00: resource 17 [mem 0x000e8000-0x000ebfff window] Oct 25 01:28:02 pci_bus 0000:00: resource 18 [mem 0x000ec000-0x000effff window] Oct 25 01:28:02 pci_bus 0000:00: resource 19 [mem 0x000f0000-0x000fffff window] Oct 25 01:28:02 pci_bus 0000:00: resource 20 [mem 0x80000000-0xfeafffff window] Oct 25 01:28:02 pci_bus 0000:01: resource 0 [io 0x4000-0x4fff] Oct 25 01:28:02 pci_bus 0000:01: resource 1 [mem 0x82600000-0x826fffff] Oct 25 01:28:02 pci_bus 0000:01: resource 2 [mem 0xb0000000-0xc01fffff 64bit pref] Oct 25 01:28:02 pci_bus 0000:04: resource 0 [io 0x6000-0x9fff] Oct 25 01:28:02 pci_bus 0000:04: resource 1 [mem 0x82800000-0x909fffff] Oct 25 01:28:02 pci_bus 0000:04: resource 2 [mem 0xc0200000-0xce1fffff 64bit pref] Oct 25 01:28:02 pci_bus 0000:05: resource 0 [io 0x6000-0x9fff] Oct 25 01:28:02 pci_bus 0000:05: resource 1 [mem 0x82800000-0x909fffff] Oct 25 01:28:02 pci_bus 0000:05: resource 2 [mem 0xc0200000-0xce1fffff 64bit pref] Oct 25 01:28:02 pci_bus 0000:06: resource 1 [mem 0x82900000-0x829fffff] Oct 25 01:28:02 pci_bus 0000:08: resource 0 [io 0x6000-0x7fff] Oct 25 01:28:02 pci_bus 0000:08: resource 1 [mem 0x82a00000-0x899fffff] Oct 25 01:28:02 pci_bus 0000:08: resource 2 [mem 0xc0200000-0xc71fffff 64bit pref] Oct 25 01:28:02 pci_bus 0000:07: resource 1 [mem 0x82800000-0x828fffff] Oct 25 01:28:02 pci_bus 0000:41: resource 0 [io 0x8000-0x9fff] Oct 25 01:28:02 pci_bus 0000:41: resource 1 [mem 0x89a00000-0x909fffff] Oct 25 01:28:02 pci_bus 0000:41: resource 2 [mem 0xc7200000-0xce1fffff 64bit pref] Oct 25 01:28:02 pci_bus 0000:7a: resource 0 [io 0xa000-0xdfff] Oct 25 01:28:02 pci_bus 0000:7a: resource 1 [mem 0x90a00000-0x9ebfffff] Oct 25 01:28:02 pci_bus 0000:7a: resource 2 [mem 0xce200000-0xdc1fffff 64bit pref] Oct 25 01:28:02 pci_bus 0000:7b: resource 0 [io 0xa000-0xdfff] Oct 25 01:28:02 pci_bus 0000:7b: resource 1 [mem 0x90a00000-0x9ebfffff] Oct 25 01:28:02 pci_bus 0000:7b: resource 2 [mem 0xce200000-0xdc1fffff 64bit pref] Oct 25 01:28:02 pci_bus 0000:7c: resource 1 [mem 0x90b00000-0x90bfffff] Oct 25 01:28:02 pci_bus 0000:7e: resource 0 [io 0xa000-0xbfff] Oct 25 01:28:02 pci_bus 0000:7e: resource 1 [mem 0x90c00000-0x97bfffff] Oct 25 01:28:02 pci_bus 0000:7e: resource 2 [mem 0xce200000-0xd51fffff 64bit pref] Oct 25 01:28:02 pci_bus 0000:7d: resource 1 [mem 0x90a00000-0x90afffff] Oct 25 01:28:02 pci_bus 0000:b7: resource 0 [io 0xc000-0xdfff] Oct 25 01:28:02 pci_bus 0000:b7: resource 1 [mem 0x97c00000-0x9ebfffff] Oct 25 01:28:02 pci_bus 0000:b7: resource 2 [mem 0xd5200000-0xdc1fffff 64bit pref] Oct 25 01:28:02 pci_bus 0000:02: resource 0 [io 0x3000-0x3fff] Oct 25 01:28:02 pci_bus 0000:02: resource 1 [mem 0x82500000-0x825fffff] Oct 25 01:28:02 pci_bus 0000:03: resource 1 [mem 0x82000000-0x824fffff] Oct 25 01:28:02 NET: Registered protocol family 2 Oct 25 01:28:02 tcp_listen_portaddr_hash hash table entries: 8192 (order: 7, 720896 bytes) Oct 25 01:28:02 TCP established hash table entries: 131072 (order: 8, 1048576 bytes) Oct 25 01:28:02 TCP bind hash table entries: 65536 (order: 10, 5242880 bytes) Oct 25 01:28:02 TCP: Hash tables configured (established 131072 bind 65536) Oct 25 01:28:02 UDP hash table entries: 8192 (order: 8, 1572864 bytes) Oct 25 01:28:02 UDP-Lite hash table entries: 8192 (order: 8, 1572864 bytes) Oct 25 01:28:02 NET: Registered protocol family 1 Oct 25 01:28:02 pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff] Oct 25 01:28:02 pci 0000:01:00.1: Linked as a consumer to 0000:01:00.0 Oct 25 01:28:02 PCI: CLS 256 bytes, default 64 Oct 25 01:28:02 Unpacking initramfs... Oct 25 01:28:02 Freeing initrd memory: 17376K Oct 25 01:28:02 DMAR: ACPI device "device:91" under DMAR at fed91000 as 00:15.0 Oct 25 01:28:02 DMAR: ACPI device "device:92" under DMAR at fed91000 as 00:1e.2 Oct 25 01:28:02 DMAR: ACPI device "device:93" under DMAR at fed91000 as 00:1e.3 Oct 25 01:28:02 DMAR: Failed to find handle for ACPI object \_SB.PCI0.UA00 Oct 25 01:28:02 DMAR: Failed to find handle for ACPI object \_SB.PCI0.UA01 Oct 25 01:28:02 DMAR: Failed to find handle for ACPI object \_SB.PCI0.UA02 Oct 25 01:28:02 DMAR: No ATSR found Oct 25 01:28:02 DMAR: dmar0: Using Queued invalidation Oct 25 01:28:02 DMAR: dmar1: Using Queued invalidation Oct 25 01:28:02 DMAR: Setting RMRR: Oct 25 01:28:02 DMAR: Setting identity map for device 0000:00:02.0 [0x7b800000 - 0x7fffffff] Oct 25 01:28:02 DMAR: Prepare 0-16MiB unity mapping for LPC Oct 25 01:28:02 DMAR: Setting identity map for device 0000:00:1f.0 [0x0 - 0xffffff] Oct 25 01:28:02 DMAR: Intel(R) Virtualization Technology for Directed I/O Oct 25 01:28:02 iommu: Adding device 0000:00:00.0 to group 0 Oct 25 01:28:02 iommu: Adding device 0000:00:01.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:00:01.1 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:00:01.2 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:00:02.0 to group 2 Oct 25 01:28:02 iommu: Adding device 0000:00:14.0 to group 3 Oct 25 01:28:02 iommu: Adding device 0000:00:15.0 to group 4 Oct 25 01:28:02 iommu: Adding device 0000:00:16.0 to group 5 Oct 25 01:28:02 iommu: Adding device 0000:00:19.0 to group 6 Oct 25 01:28:02 iommu: Adding device 0000:00:1b.0 to group 7 Oct 25 01:28:02 iommu: Adding device 0000:00:1c.0 to group 8 Oct 25 01:28:02 iommu: Adding device 0000:00:1e.0 to group 9 Oct 25 01:28:02 iommu: Adding device 0000:00:1e.1 to group 9 Oct 25 01:28:02 iommu: Adding device 0000:00:1e.2 to group 9 Oct 25 01:28:02 iommu: Adding device 0000:00:1e.3 to group 9 Oct 25 01:28:02 iommu: Adding device 0000:00:1f.0 to group 10 Oct 25 01:28:02 iommu: Adding device 0000:00:1f.2 to group 10 Oct 25 01:28:02 iommu: Adding device 0000:00:1f.3 to group 10 Oct 25 01:28:02 iommu: Adding device 0000:00:1f.4 to group 10 Oct 25 01:28:02 iommu: Adding device 0000:01:00.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:01:00.1 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:04:00.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:05:00.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:05:01.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:05:02.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:05:04.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:06:00.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:07:00.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:7a:00.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:7b:00.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:7b:01.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:7b:02.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:7b:04.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:7c:00.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:7d:00.0 to group 1 Oct 25 01:28:02 iommu: Adding device 0000:02:00.0 to group 11 Oct 25 01:28:02 iommu: Adding device 0000:03:00.0 to group 12 Oct 25 01:28:02 clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x29dc05e54fc, max_idle_ns: 440795291716 ns Oct 25 01:28:02 clocksource: Switched to clocksource tsc Oct 25 01:28:02 Initialise system trusted keyrings Oct 25 01:28:02 Key type blacklist registered Oct 25 01:28:02 workingset: timestamp_bits=36 max_order=22 bucket_order=0 Oct 25 01:28:02 zbud: loaded Oct 25 01:28:02 pstore: using deflate compression Oct 25 01:28:02 alg: No test for 842 (842-generic) Oct 25 01:28:02 alg: No test for 842 (842-scomp) Oct 25 01:28:02 NET: Registered protocol family 38 Oct 25 01:28:02 Key type asymmetric registered Oct 25 01:28:02 Asymmetric key parser 'x509' registered Oct 25 01:28:02 Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243) Oct 25 01:28:02 io scheduler noop registered Oct 25 01:28:02 io scheduler deadline registered Oct 25 01:28:02 io scheduler cfq registered (default) Oct 25 01:28:02 io scheduler mq-deadline registered Oct 25 01:28:02 atomic64_test: passed for x86-64 platform with CX8 and with SSE Oct 25 01:28:02 pciehp 0000:05:01.0:pcie204: Slot #1 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ LLActRep+ Oct 25 01:28:02 pciehp 0000:05:02.0:pcie204: Slot #0 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ LLActRep+ Oct 25 01:28:02 pciehp 0000:05:04.0:pcie204: Slot #4 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ LLActRep+ Oct 25 01:28:02 pciehp 0000:7b:01.0:pcie204: Slot #1 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ LLActRep+ Oct 25 01:28:02 pciehp 0000:7b:02.0:pcie204: Slot #0 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ LLActRep+ Oct 25 01:28:02 pciehp 0000:7b:04.0:pcie204: Slot #4 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ LLActRep+ Oct 25 01:28:02 efifb: probing for efifb Oct 25 01:28:02 efifb: framebuffer at 0xa0000000, using 27564k, total 27562k Oct 25 01:28:02 efifb: mode is 3360x2100x32, linelength=13440, pages=1 Oct 25 01:28:02 efifb: scrolling: redraw Oct 25 01:28:02 efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0 Oct 25 01:28:02 Console: switching to colour frame buffer device 420x131 Oct 25 01:28:02 fb0: EFI VGA frame buffer device Oct 25 01:28:02 intel_idle: MWAIT substates: 0x11142120 Oct 25 01:28:02 intel_idle: v0.4.1 model 0x5E Oct 25 01:28:02 intel_idle: state C8 is disabled Oct 25 01:28:02 intel_idle: state C9 is disabled Oct 25 01:28:02 intel_idle: lapic_timer_reliable_states 0xffffffff Oct 25 01:28:02 ACPI: AC Adapter [ADP1] (off-line) Oct 25 01:28:02 input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input0 Oct 25 01:28:02 ACPI: Lid Switch [LID0] Oct 25 01:28:02 input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1 Oct 25 01:28:02 ACPI: Power Button [PWRB] Oct 25 01:28:02 input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input2 Oct 25 01:28:02 ACPI: Sleep Button [SLPB] Oct 25 01:28:02 input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input3 Oct 25 01:28:02 ACPI: Power Button [PWRF] Oct 25 01:28:02 Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled Oct 25 01:28:02 Non-volatile memory driver v1.3 Oct 25 01:28:02 Linux agpgart interface v0.103 Oct 25 01:28:02 libphy: Fixed MDIO Bus: probed Oct 25 01:28:02 ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver Oct 25 01:28:02 ehci-pci: EHCI PCI platform driver Oct 25 01:28:02 ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver Oct 25 01:28:02 ohci-pci: OHCI PCI platform driver Oct 25 01:28:02 uhci_hcd: USB Universal Host Controller Interface driver Oct 25 01:28:02 xhci_hcd 0000:00:14.0: xHCI Host Controller Oct 25 01:28:02 xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1 Oct 25 01:28:02 xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x0000000001109810 Oct 25 01:28:02 xhci_hcd 0000:00:14.0: cache line size of 256 is not supported Oct 25 01:28:02 usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19 Oct 25 01:28:02 usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 Oct 25 01:28:02 usb usb1: Product: xHCI Host Controller Oct 25 01:28:02 usb usb1: Manufacturer: Linux 4.19.0-rc8-drm xhci-hcd Oct 25 01:28:02 usb usb1: SerialNumber: 0000:00:14.0 Oct 25 01:28:02 hub 1-0:1.0: USB hub found Oct 25 01:28:02 hub 1-0:1.0: 16 ports detected Oct 25 01:28:02 xhci_hcd 0000:00:14.0: xHCI Host Controller Oct 25 01:28:02 xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2 Oct 25 01:28:02 xhci_hcd 0000:00:14.0: Host supports USB 3.0 SuperSpeed Oct 25 01:28:02 usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 4.19 Oct 25 01:28:02 usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 Oct 25 01:28:02 usb usb2: Product: xHCI Host Controller Oct 25 01:28:02 usb usb2: Manufacturer: Linux 4.19.0-rc8-drm xhci-hcd Oct 25 01:28:02 usb usb2: SerialNumber: 0000:00:14.0 Oct 25 01:28:02 hub 2-0:1.0: USB hub found Oct 25 01:28:02 hub 2-0:1.0: 8 ports detected Oct 25 01:28:02 xhci_hcd 0000:07:00.0: xHCI Host Controller Oct 25 01:28:02 xhci_hcd 0000:07:00.0: new USB bus registered, assigned bus number 3 Oct 25 01:28:02 xhci_hcd 0000:07:00.0: hcc params 0x200077c1 hci version 0x110 quirks 0x0000000000009810 Oct 25 01:28:02 usb usb3: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19 Oct 25 01:28:02 usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1 Oct 25 01:28:02 usb usb3: Product: xHCI Host Controller Oct 25 01:28:02 usb usb3: Manufacturer: Linux 4.19.0-rc8-drm xhci-hcd Oct 25 01:28:02 usb usb3: SerialNumber: 0000:07:00.0 Oct 25 01:28:02 hub 3-0:1.0: USB hub found Oct 25 01:28:02 hub 3-0:1.0: 2 ports detected Oct 25 01:28:02 xhci_hcd 0000:07:00.0: xHCI Host Controller Oct 25 01:28:02 xhci_hcd 0000:07:00.0: new USB bus registered, assigned bus number 4 Oct 25 01:28:02 xhci_hcd 0000:07:00.0: Host supports USB 3.1 Enhanced SuperSpeed Oct 25 01:28:02 usb usb4: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 4.19 Oct 25 01:28:02 usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1 Oct 25 01:28:02 usb usb4: Product: xHCI Host Controller Oct 25 01:28:02 usb usb4: Manufacturer: Linux 4.19.0-rc8-drm xhci-hcd Oct 25 01:28:02 usb usb4: SerialNumber: 0000:07:00.0 Oct 25 01:28:02 hub 4-0:1.0: USB hub found Oct 25 01:28:02 hub 4-0:1.0: 2 ports detected Oct 25 01:28:02 xhci_hcd 0000:7d:00.0: xHCI Host Controller Oct 25 01:28:02 xhci_hcd 0000:7d:00.0: new USB bus registered, assigned bus number 5 Oct 25 01:28:02 xhci_hcd 0000:7d:00.0: hcc params 0x200077c1 hci version 0x110 quirks 0x0000000000009810 Oct 25 01:28:02 usb usb5: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19 Oct 25 01:28:02 usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1 Oct 25 01:28:02 usb usb5: Product: xHCI Host Controller Oct 25 01:28:02 usb usb5: Manufacturer: Linux 4.19.0-rc8-drm xhci-hcd Oct 25 01:28:02 usb usb5: SerialNumber: 0000:7d:00.0 Oct 25 01:28:02 hub 5-0:1.0: USB hub found Oct 25 01:28:02 hub 5-0:1.0: 2 ports detected Oct 25 01:28:02 xhci_hcd 0000:7d:00.0: xHCI Host Controller Oct 25 01:28:02 xhci_hcd 0000:7d:00.0: new USB bus registered, assigned bus number 6 Oct 25 01:28:02 xhci_hcd 0000:7d:00.0: Host supports USB 3.1 Enhanced SuperSpeed Oct 25 01:28:02 usb usb6: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 4.19 Oct 25 01:28:02 usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1 Oct 25 01:28:02 usb usb6: Product: xHCI Host Controller Oct 25 01:28:02 usb usb6: Manufacturer: Linux 4.19.0-rc8-drm xhci-hcd Oct 25 01:28:02 usb usb6: SerialNumber: 0000:7d:00.0 Oct 25 01:28:02 hub 6-0:1.0: USB hub found Oct 25 01:28:02 hub 6-0:1.0: 2 ports detected Oct 25 01:28:02 usbcore: registered new interface driver usbserial_generic Oct 25 01:28:02 usbserial: USB Serial support registered for generic Oct 25 01:28:02 i8042: PNP: No PS/2 controller found. Oct 25 01:28:02 mousedev: PS/2 mouse device common for all mice Oct 25 01:28:02 rtc_cmos 00:01: RTC can wake from S4 Oct 25 01:28:02 rtc_cmos 00:01: registered as rtc0 Oct 25 01:28:02 rtc_cmos 00:01: alarms up to one month, y3k, 242 bytes nvram, hpet irqs Oct 25 01:28:02 device-mapper: uevent: version 1.0.3 Oct 25 01:28:02 device-mapper: ioctl: 4.39.0-ioctl (2018-04-03) initialised: dm-devel@redhat.com Oct 25 01:28:02 intel_pstate: Intel P-state driver initializing Oct 25 01:28:02 intel_pstate: HWP enabled Oct 25 01:28:02 hidraw: raw HID events driver (C) Jiri Kosina Oct 25 01:28:02 usbcore: registered new interface driver usbhid Oct 25 01:28:02 usbhid: USB HID core driver Oct 25 01:28:02 intel_pmc_core: initialized Oct 25 01:28:02 drop_monitor: Initializing network drop monitor service Oct 25 01:28:02 Initializing XFRM netlink socket Oct 25 01:28:02 NET: Registered protocol family 10 Oct 25 01:28:02 Segment Routing with IPv6 Oct 25 01:28:02 mip6: Mobile IPv6 Oct 25 01:28:02 NET: Registered protocol family 17 Oct 25 01:28:02 RAS: Correctable Errors collector initialized. Oct 25 01:28:02 microcode: sig=0x506e3, pf=0x20, revision=0xc6 Oct 25 01:28:02 microcode: Microcode Update Driver: v2.2. Oct 25 01:28:02 AVX2 version of gcm_enc/dec engaged. Oct 25 01:28:02 AES CTR mode by8 optimization enabled Oct 25 01:28:02 sched_clock: Marking stable (2362895414, -383343)->(2371493307, -8981236) Oct 25 01:28:02 registered taskstats version 1 Oct 25 01:28:02 Loading compiled-in X.509 certificates Oct 25 01:28:02 Loaded X.509 cert 'Build time autogenerated kernel key: 78b553e7189bfc0d00f92073c01cf4efb3fd886d' Oct 25 01:28:02 zswap: loaded using pool lzo/zbud Oct 25 01:28:02 Key type big_key registered Oct 25 01:28:02 Key type encrypted registered Oct 25 01:28:02 ima: No TPM chip found, activating TPM-bypass! Oct 25 01:28:02 ima: Allocated hash algorithm: sha1 Oct 25 01:28:02 Magic number: 6:676:473 Oct 25 01:28:02 rtc_cmos 00:01: setting system clock to 2018-10-25 08:28:01 UTC (1540456081) Oct 25 01:28:02 Freeing unused kernel image memory: 3936K Oct 25 01:28:02 Write protecting the kernel read-only data: 22528k Oct 25 01:28:02 Freeing unused kernel image memory: 2012K Oct 25 01:28:02 Freeing unused kernel image memory: 1988K Oct 25 01:28:02 x86/mm: Checked W+X mappings: passed, no W+X pages found. Oct 25 01:28:02 rodata_test: all tests were successful Oct 25 01:28:02 x86/mm: Checking user space page tables Oct 25 01:28:02 x86/mm: Checked W+X mappings: passed, no W+X pages found. Oct 25 01:28:02 Run /init as init process Oct 25 01:28:02 usb 1-5: new high-speed USB device number 2 using xhci_hcd Oct 25 01:28:02 usb 1-5: New USB device found, idVendor=13b1, idProduct=003f, bcdDevice= 0.00 Oct 25 01:28:02 usb 1-5: New USB device strings: Mfr=1, Product=2, SerialNumber=3 Oct 25 01:28:02 usb 1-5: Product: WUSB6300 Oct 25 01:28:02 usb 1-5: Manufacturer: Linksys Oct 25 01:28:02 usb 1-5: SerialNumber: 34 Oct 25 01:28:02 random: systemd: uninitialized urandom read (16 bytes read) Oct 25 01:28:02 random: systemd: uninitialized urandom read (16 bytes read) Oct 25 01:28:02 random: systemd: uninitialized urandom read (16 bytes read) Oct 25 01:28:02 audit: type=1130 audit(1540456082.257:2): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-sysctl comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:02 audit: type=1130 audit(1540456082.260:3): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=kmod-static-nodes comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:02 audit: type=1130 audit(1540456082.266:4): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-tmpfiles-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:02 audit: type=1130 audit(1540456082.273:5): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-tmpfiles-setup-dev comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:02 audit: type=1130 audit(1540456082.342:6): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-vconsole-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:02 audit: type=1131 audit(1540456082.342:7): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-vconsole-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:02 audit: type=1130 audit(1540456082.359:8): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-cmdline comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:02 audit: type=1130 audit(1540456082.373:9): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-udevd comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:02 audit: type=1130 audit(1540456082.380:10): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-journald comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:02 video: module verification failed: signature and/or required key missing - tainting kernel Oct 25 01:28:02 applespi: loading out-of-tree module taints kernel. Oct 25 01:28:02 intel-lpss 0000:00:15.0: enabling device (0000 -> 0002) Oct 25 01:28:02 nvme nvme0: pci function 0000:02:00.0 Oct 25 01:28:02 intel-lpss 0000:00:19.0: enabling device (0000 -> 0002) Oct 25 01:28:02 dw-apb-uart.1: ttyS4 at MMIO 0x8272a000 (irq = 21, base_baud = 115200) is a 16550A Oct 25 01:28:02 serial serial0: tty port ttyS4 registered Oct 25 01:28:02 kvmgt: Unknown symbol gfn_to_memslot (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol vfio_pin_pages (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol vfio_info_cap_shift (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol vfio_set_irqs_validate_and_prepare (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol vfio_device_put (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol gfn_to_pfn (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol mdev_from_dev (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol kvm_put_kvm (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol kvm_write_guest (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol kvm_slot_page_track_remove_page (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol kvm_page_track_register_notifier (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol mdev_parent_dev (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol vfio_unpin_pages (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol kvm_is_visible_gfn (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol kvm_page_track_unregister_notifier (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol vfio_device_get_from_dev (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol kvm_slot_page_track_add_page (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol vfio_register_notifier (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol vfio_info_add_capability (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol mdev_get_drvdata (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol mdev_register_device (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol mdev_dev (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol mdev_unregister_device (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol vfio_unregister_notifier (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol kvm_read_guest (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol mdev_set_drvdata (err -2) Oct 25 01:28:02 kvmgt: Unknown symbol kvm_get_kvm (err -2) Oct 25 01:28:02 intel-lpss 0000:00:1e.0: enabling device (0000 -> 0002) Oct 25 01:28:02 dw-apb-uart.2: ttyS5 at MMIO 0x8272b000 (irq = 20, base_baud = 3000000) is a 16550A Oct 25 01:28:02 serial serial1: tty port ttyS5 registered Oct 25 01:28:02 intel-lpss 0000:00:1e.1: enabling device (0000 -> 0002) Oct 25 01:28:02 dw-apb-uart.3: ttyS6 at MMIO 0x8272c000 (irq = 21, base_baud = 115200) is a 16550A Oct 25 01:28:02 serial serial2: tty port ttyS6 registered Oct 25 01:28:02 apple-ibridge: registered driver 'apple-ib-touchbar' Oct 25 01:28:02 intel-lpss 0000:00:1e.2: enabling device (0000 -> 0002) Oct 25 01:28:02 intel-lpss 0000:00:1e.3: enabling device (0000 -> 0002) Oct 25 01:28:02 input: Apple SPI Keyboard as /devices/pci0000:00/0000:00:1e.3/pxa2xx-spi.5/spi_master/spi2/spi-APP000D:00/input/input4 Oct 25 01:28:02 applespi: spi-device probe done: spi-APP000D:00 Oct 25 01:28:02 input: Apple SPI Touchpad as /devices/pci0000:00/0000:00:1e.3/pxa2xx-spi.5/spi_master/spi2/spi-APP000D:00/input/input5 Oct 25 01:28:02 [drm:intel_pch_type [i915]] Found SunrisePoint PCH Oct 25 01:28:02 [drm:i915_driver_load [i915]] WOPCM size: 1024KiB Oct 25 01:28:02 [drm:intel_uc_init_early [i915]] enable_guc=0 (submission:no huc:no) Oct 25 01:28:02 [drm:i915_driver_load [i915]] guc_log_level=0 (enabled:no, verbose:no, verbosity:0) Oct 25 01:28:02 [drm:intel_power_domains_init [i915]] Allowed DC state mask 03 Oct 25 01:28:02 applespi: modeswitch done. Oct 25 01:28:02 [drm:i915_ggtt_probe_hw [i915]] GGTT size = 4096M Oct 25 01:28:02 [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M Oct 25 01:28:02 [drm:i915_ggtt_probe_hw [i915]] DSM size = 64M Oct 25 01:28:02 [drm] VT-d active for gfx access Oct 25 01:28:02 checking generic (a0000000 1aeb000) vs hw (a0000000 10000000) Oct 25 01:28:02 fb0: switching to inteldrmfb from EFI VGA Oct 25 01:28:02 Console: switching to colour dummy device 80x25 Oct 25 01:28:02 [drm] Replacing VGA console driver Oct 25 01:28:02 [drm:i915_gem_init_stolen [i915]] GEN6_STOLEN_RESERVED = 7ff00017 Oct 25 01:28:02 [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K Oct 25 01:28:02 [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params Oct 25 01:28:02 [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x7af97018 Oct 25 01:28:02 [drm:intel_opregion_setup [i915]] Public ACPI methods supported Oct 25 01:28:02 [drm:intel_opregion_setup [i915]] SWSCI supported Oct 25 01:28:02 [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00040001, SBCB callbacks 00200001 Oct 25 01:28:02 [drm:intel_opregion_setup [i915]] ASLE supported Oct 25 01:28:02 [drm:intel_opregion_setup [i915]] ASLE extension supported Oct 25 01:28:02 [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4) Oct 25 01:28:02 [drm:skl_dram_get_channel_info [i915]] (size:width:rank) L(8GB:X16:dual) S(0GB:X8:single) Oct 25 01:28:02 [drm:skl_dram_get_channel_info [i915]] (size:width:rank) L(8GB:X16:dual) S(0GB:X8:single) Oct 25 01:28:02 [drm:skl_dram_get_channels_info [i915]] memory configuration is Symmetric memory Oct 25 01:28:02 [drm:i915_driver_load.cold.17 [i915]] DRAM bandwidth:34133344 KBps, total-channels: 2 Oct 25 01:28:02 [drm:i915_driver_load.cold.17 [i915]] DRAM rank: dual rank 16GB-dimm:no Oct 25 01:28:02 [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). Oct 25 01:28:02 [drm] Driver supports precise vblank timestamp query. Oct 25 01:28:02 [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz Oct 25 01:28:02 [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE ", BDB version 196 Oct 25 01:28:02 [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0 Oct 25 01:28:02 [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2 Oct 25 01:28:02 [drm:intel_opregion_get_panel_type [i915]] Failed to get panel details from OpRegion (-22) Oct 25 01:28:02 [drm:intel_bios_init [i915]] Panel type: 2 (VBT) Oct 25 01:28:02 [drm:intel_bios_init [i915]] DRRS supported mode is static Oct 25 01:28:02 [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables: Oct 25 01:28:02 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa Oct 25 01:28:02 [drm:intel_bios_init [i915]] VBT initial LVDS value 300 Oct 25 01:28:02 [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0 Oct 25 01:28:02 [drm:intel_bios_init [i915]] DRRS State Enabled:1 Oct 25 01:28:02 [drm:intel_bios_init [i915]] Skipping SDVO device mapping Oct 25 01:28:02 [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0 Oct 25 01:28:02 [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0 Oct 25 01:28:02 [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0 Oct 25 01:28:02 [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8 Oct 25 01:28:02 [drm:intel_bios_init [i915]] Port D VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0 Oct 25 01:28:02 [drm:intel_bios_init [i915]] VBT HDMI level shift for port D: 8 Oct 25 01:28:02 [drm:intel_dsm_detect [i915]] no _DSM method for intel device Oct 25 01:28:02 [drm:intel_dsm_detect [i915]] no _DSM method for intel device Oct 25 01:28:02 [drm:i915_driver_load [i915]] rawclk rate: 24000 kHz Oct 25 01:28:02 [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 Oct 25 01:28:02 [drm:intel_power_well_enable [i915]] enabling power well 1 Oct 25 01:28:02 [drm:intel_power_well_enable [i915]] enabling MISC IO power well Oct 25 01:28:02 [drm:intel_dump_cdclk_state [i915]] Current CDCLK 675000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 3 Oct 25 01:28:02 [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz Oct 25 01:28:02 [drm:skl_init_cdclk [i915]] Max dotclock rate: 675000 kHz Oct 25 01:28:02 [drm:intel_power_well_enable [i915]] enabling always-on Oct 25 01:28:02 [drm:intel_power_well_enable [i915]] enabling DC off Oct 25 01:28:02 [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 Oct 25 01:28:02 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:02 i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=none:owns=io+mem Oct 25 01:28:02 [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well Oct 25 01:28:02 [drm:intel_power_well_enable [i915]] enabling DDI B IO power well Oct 25 01:28:02 [drm:intel_power_well_enable [i915]] enabling DDI C IO power well Oct 25 01:28:02 [drm:intel_power_well_enable [i915]] enabling DDI D IO power well Oct 25 01:28:02 [drm:intel_csr_ucode_init [i915]] Loading i915/skl_dmc_ver1_27.bin Oct 25 01:28:02 [drm] Finished loading DMC firmware i915/skl_dmc_ver1_27.bin (v1.27) Oct 25 01:28:02 [drm] Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled Oct 25 01:28:02 [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 0 Oct 25 01:28:02 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec) Oct 25 01:28:02 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec) Oct 25 01:28:02 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec) Oct 25 01:28:02 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec) Oct 25 01:28:02 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec) Oct 25 01:28:02 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec) Oct 25 01:28:02 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec) Oct 25 01:28:02 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec) Oct 25 01:28:02 [drm:intel_modeset_init [i915]] 3 display pipes available. Oct 25 01:28:02 [drm:intel_dump_cdclk_state [i915]] Current CDCLK 675000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 3 Oct 25 01:28:02 [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A Oct 25 01:28:02 [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT) Oct 25 01:28:02 [drm:intel_pps_dump_state [i915]] cur t1_t3 125 t8 2100 t9 2500 t10 740 t11_t12 6000 Oct 25 01:28:02 [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 6000 Oct 25 01:28:02 [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 74, power cycle delay 600 Oct 25 01:28:02 [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 210, off delay 250 Oct 25 01:28:02 [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x2e40001, PP_DIV 0x4af06 Oct 25 01:28:02 [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Oct 25 01:28:02 [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f Oct 25 01:28:02 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:02 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:02 [drm:intel_dp_init_connector [i915]] eDP DPCD: 02 83 97 Oct 25 01:28:02 [drm:intel_psr_init_dpcd [i915]] eDP panel supports PSR version 1 Oct 25 01:28:02 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Oct 25 01:28:02 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:02 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:02 [drm:intel_dp_init_connector [i915]] VBT doesn't support DRRS Oct 25 01:28:02 [drm:intel_panel_setup_backlight [i915]] Connector eDP-1 backlight initialized, enabled, brightness 2082/2777 Oct 25 01:28:02 [drm:intel_modeset_init [i915]] VBT says port B is not DVI/HDMI/DP compatible, respect it Oct 25 01:28:02 [drm:intel_dp_init_connector [i915]] Adding DP connector on port C Oct 25 01:28:02 [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT) Oct 25 01:28:02 [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C Oct 25 01:28:02 [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT) Oct 25 01:28:02 [drm:intel_dp_init_connector [i915]] Adding DP connector on port D Oct 25 01:28:02 [drm:intel_dp_init_connector [i915]] using AUX D for port D (VBT) Oct 25 01:28:02 [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port D Oct 25 01:28:02 [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x6 for port D (VBT) Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [CRTC:45:pipe A] hw state readout: enabled Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [CRTC:63:pipe B] hw state readout: disabled Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [CRTC:81:pipe C] hw state readout: disabled Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:28:plane 1A] hw state readout: enabled, pipe A Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:35:plane 2A] hw state readout: disabled, pipe A Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:42:cursor A] hw state readout: disabled, pipe A Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:46:plane 1B] hw state readout: disabled, pipe B Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:53:plane 2B] hw state readout: disabled, pipe B Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:cursor B] hw state readout: disabled, pipe B Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:64:plane 1C] hw state readout: disabled, pipe C Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:71:plane 2C] hw state readout: disabled, pipe C Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:78:cursor C] hw state readout: disabled, pipe C Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000001, on 1 Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0 Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0 Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0 Oct 25 01:28:02 [drm:intel_ddi_get_config [i915]] pipe has 30 bpp for eDP panel, overriding BIOS-provided max 18 bpp Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:82:DDI A] hw state readout: enabled, pipe A Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:89:DDI C] hw state readout: disabled, pipe A Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:91:DP-MST A] hw state readout: disabled, pipe A Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:92:DP-MST B] hw state readout: disabled, pipe B Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:93:DP-MST C] hw state readout: disabled, pipe C Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:100:DDI D] hw state readout: disabled, pipe A Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:102:DP-MST A] hw state readout: disabled, pipe A Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:103:DP-MST B] hw state readout: disabled, pipe B Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:104:DP-MST C] hw state readout: disabled, pipe C Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:83:eDP-1] hw state readout: enabled Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:90:DP-1] hw state readout: disabled Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:96:HDMI-A-1] hw state readout: disabled Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:101:DP-2] hw state readout: disabled Oct 25 01:28:02 [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:106:HDMI-A-2] hw state readout: disabled Oct 25 01:28:02 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 000000007705ab21 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe A][setup_hw_state] Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] output format: RGB Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 30, dithering: 0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 7983741, gmch_n: 8388608, link_m: 532249, link_n: 524288, tu: 64 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] requested mode: Oct 25 01:28:02 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"2880x1800" 60 328919 3360 2888 2920 2960 2100 1838 1846 1852 0x40 0x9 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] adjusted mode: Oct 25 01:28:02 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"2880x1800" 60 328919 2880 2888 2920 2960 1800 1838 1846 1852 0x40 0x9 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] crtc timings: 328919 2880 2888 2920 2960 1800 1838 1846 1852, type: 0x40 flags: 0x9 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] port clock: 324000, pipe src size: 3360x2100, pixel rate 447695 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x0b400708, enabled Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x7, cfgcr1: 0x0, cfgcr2: 0x0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] planes on this crtc Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2A] disabled, scaler_id = -1 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] [PLANE:42:cursor A] disabled, scaler_id = -1 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] [CRTC:63:pipe B][setup_hw_state] Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] output_types: (0x0) Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] output format: Invalid Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] requested mode: Oct 25 01:28:02 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] adjusted mode: Oct 25 01:28:02 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] planes on this crtc Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 1B] disabled, scaler_id = -1 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 2B] disabled, scaler_id = -1 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] [PLANE:60:cursor B] disabled, scaler_id = -1 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] [CRTC:81:pipe C][setup_hw_state] Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] output_types: (0x0) Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] output format: Invalid Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] requested mode: Oct 25 01:28:02 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] adjusted mode: Oct 25 01:28:02 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] planes on this crtc Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] [PLANE:64:plane 1C] disabled, scaler_id = -1 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] [PLANE:71:plane 2C] disabled, scaler_id = -1 Oct 25 01:28:02 [drm:intel_dump_pipe_config [i915]] [PLANE:78:cursor C] disabled, scaler_id = -1 Oct 25 01:28:02 [drm:skylake_get_initial_plane_config [i915]] pipe A/plane 1A with fb: size=3360x2100@32, offset=0, pitch 13440, size 0x1b12000 Oct 25 01:28:02 [drm:i915_gem_object_create_stolen_for_preallocated [i915]] creating preallocated stolen object: stolen_offset=0x0000000000000000, gtt_offset=0x0000000000000000, size=0x0000000001b12000 Oct 25 01:28:02 [drm:intel_alloc_initial_plane_obj.isra.148 [i915]] initial plane fb obj 00000000bcf34bcf Oct 25 01:28:02 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000056d9e878 state to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:45:pipe A] to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003016fdc3 state to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 00000000e231690a state to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e231690a state to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:45:pipe A] to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003016fdc3 state to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 0000000056d9e878 state to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 00000000bc2800d5 state to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_check_only [drm]] checking 000000003ba3a505 Oct 25 01:28:02 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109 Oct 25 01:28:02 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:02 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:02 [drm:drm_atomic_check_only [drm]] atomic driver check for 000000003ba3a505 failed: -35 Oct 25 01:28:02 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000bc2800d5 state to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:45:pipe A] to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003016fdc3 state to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 0000000056d9e878 state to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 00000000e231690a state to 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_check_only [drm]] checking 000000003ba3a505 Oct 25 01:28:02 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109 Oct 25 01:28:02 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:02 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:02 [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (25 - 881) -> (0 - 860) Oct 25 01:28:02 [drm:skl_compute_wm [i915]] [PLANE:42:cursor A] ddb (0 - 0) -> (860 - 892) Oct 25 01:28:02 [drm:drm_atomic_commit [drm]] committing 000000003ba3a505 Oct 25 01:28:02 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003ba3a505 Oct 25 01:28:02 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003ba3a505 Oct 25 01:28:02 [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1b13000, 100000000] Oct 25 01:28:02 [drm:intel_ctx_workarounds_init [i915]] Number of context specific w/a: 9 Oct 25 01:28:02 [drm:i915_gem_contexts_init [i915]] logical context support initialized Oct 25 01:28:02 [drm:intel_fbdev_init [i915]] found possible fb from plane A Oct 25 01:28:02 [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping Oct 25 01:28:02 [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping Oct 25 01:28:02 [drm:intel_fbdev_init [i915]] checking plane A for BIOS fb Oct 25 01:28:02 [drm:intel_fbdev_init [i915]] pipe A area: 2880x1800, bpp: 32, size: 24514560 Oct 25 01:28:02 [drm:intel_fbdev_init [i915]] fb big enough for plane A (28385280 >= 24514560) Oct 25 01:28:02 [drm:intel_fbdev_init [i915]] pipe B not active, skipping Oct 25 01:28:02 [drm:intel_fbdev_init [i915]] pipe C not active, skipping Oct 25 01:28:02 [drm:intel_fbdev_init [i915]] using BIOS fb for initial console Oct 25 01:28:02 [drm:intel_backlight_device_register [i915]] Connector eDP-1 backlight sysfs interface registered Oct 25 01:28:02 [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-eDP-1 Oct 25 01:28:02 [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-1 Oct 25 01:28:02 [drm:intel_dp_connector_register [i915]] registering DPDDC-D bus for card0-DP-2 Oct 25 01:28:02 [drm] Initialized i915 1.6.0 20180921 for 0000:00:02.0 on minor 0 Oct 25 01:28:02 [drm:intel_opregion_register [i915]] 5 outputs detected Oct 25 01:28:02 [Firmware Bug]: ACPI(GFX0) defines _DOD but not _DOS Oct 25 01:28:02 ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) Oct 25 01:28:02 acpi device:02: registered as cooling_device8 Oct 25 01:28:02 input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:01/LNXVIDEO:00/input/input6 Oct 25 01:28:02 ACPI: Video Device [IGPU] (multi-head: yes rom: no post: no) Oct 25 01:28:02 [drm:asle_work [i915]] bclp = 0x80000002 Oct 25 01:28:02 [drm:asle_work [i915]] updating opregion backlight 2/255 Oct 25 01:28:02 [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 22 Oct 25 01:28:02 [drm:asle_work [i915]] No request on ASLC interrupt 0x00000000 Oct 25 01:28:02 acpi device:7e: registered as cooling_device9 Oct 25 01:28:02 input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:01/input/input7 Oct 25 01:28:02 [drm:intel_power_well_disable [i915]] disabling DDI D IO power well Oct 25 01:28:02 [drm:intel_power_well_disable [i915]] disabling DDI C IO power well Oct 25 01:28:02 [drm:drm_setup_crtcs [drm_kms_helper]] Oct 25 01:28:02 [drm:intel_power_well_disable [i915]] disabling DDI B IO power well Oct 25 01:28:02 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:02 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] Oct 25 01:28:02 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:02 i915 device info: pciid=0x191b rev=0x06 platform=SKYLAKE gen=9 Oct 25 01:28:02 i915 device info: is_mobile: no Oct 25 01:28:02 i915 device info: is_lp: no Oct 25 01:28:02 i915 device info: is_alpha_support: no Oct 25 01:28:02 i915 device info: has_64bit_reloc: yes Oct 25 01:28:02 i915 device info: has_csr: yes Oct 25 01:28:02 i915 device info: has_ddi: yes Oct 25 01:28:02 i915 device info: has_dp_mst: yes Oct 25 01:28:02 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:02 i915 device info: has_reset_engine: yes Oct 25 01:28:02 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:02 i915 device info: has_fbc: no Oct 25 01:28:02 i915 device info: has_fpga_dbg: yes Oct 25 01:28:02 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:02 i915 device info: has_gmch_display: no Oct 25 01:28:02 i915 device info: has_guc: yes Oct 25 01:28:02 i915 device info: has_guc_ct: no Oct 25 01:28:02 i915 device info: has_hotplug: yes Oct 25 01:28:02 i915 device info: has_l3_dpf: no Oct 25 01:28:02 i915 device info: has_llc: yes Oct 25 01:28:02 i915 device info: has_logical_ring_contexts: yes Oct 25 01:28:02 i915 device info: has_logical_ring_elsq: no Oct 25 01:28:02 i915 device info: has_logical_ring_preemption: yes Oct 25 01:28:02 i915 device info: has_overlay: no Oct 25 01:28:02 i915 device info: has_pooled_eu: no Oct 25 01:28:02 i915 device info: has_psr: yes Oct 25 01:28:02 i915 device info: has_rc6: yes Oct 25 01:28:02 i915 device info: has_rc6p: no Oct 25 01:28:02 i915 device info: has_runtime_pm: yes Oct 25 01:28:02 i915 device info: has_snoop: no Oct 25 01:28:02 i915 device info: has_coherent_ggtt: yes Oct 25 01:28:02 i915 device info: unfenced_needs_alignment: no Oct 25 01:28:02 i915 device info: cursor_needs_physical: no Oct 25 01:28:02 i915 device info: hws_needs_physical: no Oct 25 01:28:02 i915 device info: overlay_needs_physical: no Oct 25 01:28:02 i915 device info: supports_tv: no Oct 25 01:28:02 i915 device info: has_ipc: no Oct 25 01:28:02 i915 device info: slice total: 1, mask=0001 Oct 25 01:28:02 i915 device info: subslice total: 3 Oct 25 01:28:02 i915 device info: slice0: 3 subslices, mask=0007 Oct 25 01:28:02 i915 device info: slice1: 0 subslices, mask=0000 Oct 25 01:28:02 i915 device info: slice2: 0 subslices, mask=0000 Oct 25 01:28:02 i915 device info: EU total: 24 Oct 25 01:28:02 i915 device info: EU per subslice: 8 Oct 25 01:28:02 i915 device info: has slice power gating: no Oct 25 01:28:02 i915 device info: has subslice power gating: no Oct 25 01:28:02 i915 device info: has EU power gating: yes Oct 25 01:28:02 i915 device info: CS timestamp frequency: 12000 kHz Oct 25 01:28:02 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:02 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:02 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] status updated from unknown to connected Oct 25 01:28:02 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:02 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Oct 25 01:28:02 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:02 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes : Oct 25 01:28:02 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9 Oct 25 01:28:02 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] Oct 25 01:28:02 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1] Oct 25 01:28:02 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:02 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:02 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] status updated from unknown to disconnected Oct 25 01:28:02 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected Oct 25 01:28:02 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:02 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:02 WARNING: CPU: 7 PID: 73 at drivers/pci/msi.c:1259 pci_irq_get_affinity+0x66/0x80 Oct 25 01:28:02 Modules linked in: i915(E) spi_pxa2xx_platform(E) apple_ib_tb(OE) i2c_algo_bit(E) drm_kms_helper(E) crct10dif_pclmul(E) crc32_pclmul(E) crc32c_intel(E) ghash_clmulni_intel(E) drm(E) nvme(E) nvme_core(E) intel_lpss_pci(E) intel_lpss(E) apple_ibridge(OE) applespi(OE) video(E) Oct 25 01:28:02 CPU: 7 PID: 73 Comm: kworker/u16:1 Tainted: G OE 4.19.0-rc8-drm #14 Oct 25 01:28:02 Hardware name: Apple Inc. MacBookPro13,3/Mac-A5C67F76ED83108C, BIOS MBP133.88Z.0247.B00.1806261159 06/26/2018 Oct 25 01:28:02 Workqueue: nvme-reset-wq nvme_reset_work [nvme] Oct 25 01:28:02 RIP: 0010:pci_irq_get_affinity+0x66/0x80 Oct 25 01:28:02 Code: 0b 31 c0 c3 83 e2 02 48 c7 c0 30 76 7a ac 74 26 48 8b 87 48 04 00 00 48 85 c0 74 0e 48 8b 50 30 48 85 d2 74 05 39 70 14 77 05 <0f> 0b 31 c0 c3 48 63 f6 48 8d 04 f2 c3 48 8b 40 30 c3 0f 1f 84 00 Oct 25 01:28:02 RSP: 0018:ffffb7dc81ba3ce8 EFLAGS: 00010246 Oct 25 01:28:02 RAX: ffff93dfe4e63d80 RBX: 0000000000000000 RCX: 0000000000000040 Oct 25 01:28:02 RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffff93dfeb2cf000 Oct 25 01:28:02 RBP: ffff93dfe2e64000 R08: ffff93dfeebe6160 R09: ffff93dfed807800 Oct 25 01:28:02 R10: 0000000000000001 R11: 0000000000000000 R12: ffff93dfe2e64008 Oct 25 01:28:02 R13: 0000000000000000 R14: ffff93dfeb2cf000 R15: 00000000ffffffff Oct 25 01:28:02 FS: 0000000000000000(0000) GS:ffff93dfeea00000(0000) knlGS:0000000000000000 Oct 25 01:28:02 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 Oct 25 01:28:02 CR2: 00007ff2d905fb10 CR3: 0000000115612005 CR4: 00000000003606e0 Oct 25 01:28:02 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 Oct 25 01:28:02 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Oct 25 01:28:02 Call Trace: Oct 25 01:28:02 blk_mq_pci_map_queues+0x37/0xc0 Oct 25 01:28:02 blk_mq_alloc_tag_set+0xe3/0x220 Oct 25 01:28:02 nvme_reset_work+0x113e/0x18e1 [nvme] Oct 25 01:28:02 process_one_work+0x24c/0x5a0 Oct 25 01:28:02 worker_thread+0x1d5/0x390 Oct 25 01:28:02 ? rescuer_thread+0x360/0x360 Oct 25 01:28:02 kthread+0x120/0x140 Oct 25 01:28:02 ? kthread_create_worker_on_cpu+0x70/0x70 Oct 25 01:28:02 ret_from_fork+0x3a/0x50 Oct 25 01:28:02 irq event stamp: 14346 Oct 25 01:28:02 hardirqs last enabled at (14345): [] _raw_spin_unlock_irqrestore+0x4b/0x60 Oct 25 01:28:02 hardirqs last disabled at (14346): [] trace_hardirqs_off_thunk+0x1a/0x1c Oct 25 01:28:02 softirqs last enabled at (14236): [] __do_softirq+0x342/0x437 Oct 25 01:28:02 softirqs last disabled at (14221): [] irq_exit+0x10d/0x120 Oct 25 01:28:02 WARNING: CPU: 7 PID: 73 at drivers/pci/msi.c:1259 pci_irq_get_affinity+0x66/0x80 Oct 25 01:28:02 ---[ end trace 533802152e0a7254 ]--- Oct 25 01:28:02 nvme0n1: p1 p2 p3 p4 p5 Oct 25 01:28:02 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:02 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:02 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:02 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 Oct 25 01:28:02 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:02 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 Oct 25 01:28:02 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:02 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:02 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] status updated from unknown to disconnected Oct 25 01:28:02 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected Oct 25 01:28:02 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] Oct 25 01:28:02 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2] Oct 25 01:28:02 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:02 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:02 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] status updated from unknown to disconnected Oct 25 01:28:02 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected Oct 25 01:28:02 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:02 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:03 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:03 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:03 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:03 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 Oct 25 01:28:03 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:03 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 Oct 25 01:28:03 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:03 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:03 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] status updated from unknown to disconnected Oct 25 01:28:03 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected Oct 25 01:28:03 [drm:drm_setup_crtcs [drm_kms_helper]] connector 83 enabled? yes Oct 25 01:28:03 [drm:drm_setup_crtcs [drm_kms_helper]] connector 90 enabled? no Oct 25 01:28:03 [drm:drm_setup_crtcs [drm_kms_helper]] connector 96 enabled? no Oct 25 01:28:03 [drm:drm_setup_crtcs [drm_kms_helper]] connector 101 enabled? no Oct 25 01:28:03 [drm:drm_setup_crtcs [drm_kms_helper]] connector 106 enabled? no Oct 25 01:28:03 [drm:intel_fb_initial_config [i915]] Not using firmware configuration Oct 25 01:28:03 [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 83 Oct 25 01:28:03 [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 83 0 Oct 25 01:28:03 [drm:drm_setup_crtcs [drm_kms_helper]] found mode 2880x1800 Oct 25 01:28:03 [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 8192x8192 config Oct 25 01:28:03 [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 2880x1800 set on crtc 45 (0,0) Oct 25 01:28:03 [drm:intelfb_create [i915]] re-using BIOS fb Oct 25 01:28:03 [drm:intelfb_create [i915]] allocated 3360x2100 fb: 0x00000000 Oct 25 01:28:03 fbcon: inteldrmfb (fb0) is primary device Oct 25 01:28:03 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005c0264a2 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b394fcfc state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000d9bb526d state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000d9bb526d Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000e5d05083 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000e5d05083 Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000ebd10755 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000438de680 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000438de680 Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 0000000051124701 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 0000000051124701 Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 000000001f4a1b4f state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 000000009e9ecc4c state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 000000009e9ecc4c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 000000007ea723ed state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 000000007ea723ed Oct 25 01:28:03 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 00000000b394fcfc Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 000000005c0264a2 Oct 25 01:28:03 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007ea723ed state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b394fcfc state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000009e9ecc4c state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000009e9ecc4c Oct 25 01:28:03 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009e9ecc4c state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b394fcfc state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000007ea723ed state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000007ea723ed Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000001f4a1b4f state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000001f4a1b4f Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 0000000051124701 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000438de680 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000438de680 Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000ebd10755 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000ebd10755 Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 00000000e5d05083 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000d9bb526d state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000d9bb526d Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 00000000608564d6 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 00000000608564d6 Oct 25 01:28:03 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 00000000b394fcfc Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 000000009e9ecc4c Oct 25 01:28:03 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000946eb70e state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000946eb70e to [NOCRTC] Oct 25 01:28:03 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000946eb70e to [CRTC:45:pipe A] Oct 25 01:28:03 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000608564d6 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b394fcfc state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000d9bb526d state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000d9bb526d Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000e5d05083 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000e5d05083 Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000ebd10755 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000438de680 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000438de680 Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 0000000051124701 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 0000000051124701 Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 000000001f4a1b4f state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 000000007ea723ed state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 000000007ea723ed Oct 25 01:28:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 000000009e9ecc4c state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 000000009e9ecc4c Oct 25 01:28:03 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 00000000b394fcfc Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 00000000608564d6 Oct 25 01:28:03 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000946eb70e state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000946eb70e to [NOCRTC] Oct 25 01:28:03 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000946eb70e to [CRTC:45:pipe A] Oct 25 01:28:03 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 0000000020c8ad84 state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 0000000020c8ad84 Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 00000000ebd10755 Oct 25 01:28:03 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 00000000a943ec5d state to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 00000000a943ec5d Oct 25 01:28:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 000000001f4a1b4f Oct 25 01:28:03 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_check_only [drm]] checking 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:45:pipe A] mode changed Oct 25 01:28:03 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1] Oct 25 01:28:03 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A] Oct 25 01:28:03 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:45:pipe A] needs all connectors, enable: y, active: y Oct 25 01:28:03 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000d3c1a41c Oct 25 01:28:03 [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:45:pipe A] to 00000000d3c1a41c Oct 25 01:28:03 [drm:intel_atomic_check [i915]] [CONNECTOR:83:eDP-1] checking for sink bpp constrains Oct 25 01:28:03 [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 Oct 25 01:28:03 [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0 Oct 25 01:28:03 [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 270000 max bpp 30 pixel clock 328920KHz Oct 25 01:28:03 [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 270000 bpp 24 Oct 25 01:28:03 [drm:intel_dp_compute_config [i915]] DP link rate required 986760 available 1080000 Oct 25 01:28:03 [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Oct 25 01:28:03 [drm:pipe_config_err [i915]] mismatch in dp_m_n (expected tu 64 gmch 7983741/8388608 link 532249/524288, or tu 0 gmch 0/0 link 0/0, found tu 64, gmch 7664391/8388608 link 638699/524288) Oct 25 01:28:03 [drm:pipe_config_err [i915]] mismatch in pipe_bpp (expected 30, found 24) Oct 25 01:28:03 [drm:pipe_config_err [i915]] mismatch in port_clock (expected 324000, found 270000) Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe A][modeset] Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] output format: RGB Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 7664391, gmch_n: 8388608, link_m: 638699, link_n: 524288, tu: 64 Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] requested mode: Oct 25 01:28:03 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9 Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] adjusted mode: Oct 25 01:28:03 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9 Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] crtc timings: 328920 2880 2888 2920 2960 1800 1838 1846 1852, type: 0x48 flags: 0x9 Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 2880x1800, pixel rate 328920 Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x7, cfgcr1: 0x0, cfgcr2: 0x0 Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] planes on this crtc Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:109, fb = 3360x2100 format = XR24 little-endian (0x34325258) Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+3360+2100 dst 0x0+3360+2100 Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2A] disabled, scaler_id = -1 Oct 25 01:28:03 [drm:intel_dump_pipe_config [i915]] [PLANE:42:cursor A] disabled, scaler_id = -1 Oct 25 01:28:03 [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz Oct 25 01:28:03 [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0 Oct 25 01:28:03 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109 Oct 25 01:28:03 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 1, on 1, ms 1 Oct 25 01:28:03 [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe A] allocated DPLL 0 Oct 25 01:28:03 [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A Oct 25 01:28:03 [drm:drm_atomic_commit [drm]] committing 00000000d3c1a41c Oct 25 01:28:03 [drm:intel_edp_backlight_off [i915]] Oct 25 01:28:03 [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0 Oct 25 01:28:03 [drm:lpt_disable_backlight [i915]] cpu backlight was enabled, disabling Oct 25 01:28:03 [drm:intel_disable_pipe [i915]] disabling pipe A Oct 25 01:28:03 [drm:intel_edp_panel_off.part.42 [i915]] Turn eDP port A panel power off Oct 25 01:28:03 [drm:intel_edp_panel_off.part.42 [i915]] Wait for panel power off time Oct 25 01:28:03 [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000000 Oct 25 01:28:03 [drm:wait_panel_status [i915]] Wait complete Oct 25 01:28:03 [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well Oct 25 01:28:03 [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 45 Oct 25 01:28:03 [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0 Oct 25 01:28:03 [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0 Oct 25 01:28:03 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010, long 0x00000010 Oct 25 01:28:03 [drm:intel_atomic_commit_tail [i915]] [ENCODER:82:DDI A] Oct 25 01:28:03 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Oct 25 01:28:03 [drm:intel_atomic_commit_tail [i915]] [ENCODER:89:DDI C] Oct 25 01:28:03 [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0 Oct 25 01:28:03 [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DP-MST A] Oct 25 01:28:03 [drm:intel_atomic_commit_tail [i915]] [ENCODER:92:DP-MST B] Oct 25 01:28:03 [drm:intel_atomic_commit_tail [i915]] [ENCODER:93:DP-MST C] Oct 25 01:28:03 [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Oct 25 01:28:03 [drm:intel_atomic_commit_tail [i915]] [ENCODER:100:DDI D] Oct 25 01:28:03 [drm:intel_atomic_commit_tail [i915]] [ENCODER:102:DP-MST A] Oct 25 01:28:03 [drm:intel_atomic_commit_tail [i915]] [ENCODER:103:DP-MST B] Oct 25 01:28:03 [drm:intel_atomic_commit_tail [i915]] [ENCODER:104:DP-MST C] Oct 25 01:28:03 [drm:verify_single_dpll_state.isra.85 [i915]] DPLL 0 Oct 25 01:28:03 [drm:verify_single_dpll_state.isra.85 [i915]] DPLL 1 Oct 25 01:28:03 [drm:verify_single_dpll_state.isra.85 [i915]] DPLL 2 Oct 25 01:28:03 [drm:verify_single_dpll_state.isra.85 [i915]] DPLL 3 Oct 25 01:28:03 [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 45 Oct 25 01:28:03 [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0 Oct 25 01:28:03 [drm:edp_panel_on [i915]] Turn eDP port A panel power on Oct 25 01:28:03 [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle Oct 25 01:28:03 usb 1-3: new high-speed USB device number 3 using xhci_hcd Oct 25 01:28:03 usb 1-3: New USB device found, idVendor=05ac, idProduct=8600, bcdDevice= 1.01 Oct 25 01:28:03 usb 1-3: New USB device strings: Mfr=1, Product=2, SerialNumber=0 Oct 25 01:28:03 usb 1-3: Product: iBridge Oct 25 01:28:03 usb 1-3: Manufacturer: Apple Inc. Oct 25 01:28:03 apple-ibridge-hid 0003:05AC:8600.0001: tb: device probe done. Oct 25 01:28:03 input: Apple Inc. iBridge as /devices/pci0000:00/0000:00:14.0/usb1/1-3/1-3:1.2/0003:05AC:8600.0001/input/input8 Oct 25 01:28:03 apple-ibridge-hid 0003:05AC:8600.0001: input,hidraw0: USB HID v1.01 Keyboard [Apple Inc. iBridge] on usb-0000:00:14.0-3/input2 Oct 25 01:28:03 apple-ibridge-hid 0003:05AC:8600.0001: ib: device probe done. Oct 25 01:28:03 apple-ib-tb: Connected to keyboard input device Oct 25 01:28:03 apple-ib-tb: Connected to touchpad input device Oct 25 01:28:03 apple-ibridge-hid 0003:05AC:8600.0002: tb: device probe done. Oct 25 01:28:03 apple-ibridge-hid 0003:05AC:8600.0002: hiddev96,hidraw1: USB HID v1.01 Device [Apple Inc. iBridge] on usb-0000:00:14.0-3/input3 Oct 25 01:28:03 apple-ibridge-hid 0003:05AC:8600.0002: ib: device probe done. Oct 25 01:28:04 [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000000 Oct 25 01:28:04 [drm:wait_panel_status [i915]] Wait complete Oct 25 01:28:04 [drm:edp_panel_on [i915]] Wait for panel power on Oct 25 01:28:04 [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000003 Oct 25 01:28:04 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010, long 0x00000010 Oct 25 01:28:04 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long Oct 25 01:28:04 [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 Oct 25 01:28:04 [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A Oct 25 01:28:04 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:04 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:04 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:04 [drm:wait_panel_status [i915]] Wait complete Oct 25 01:28:04 [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well Oct 25 01:28:04 [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Oct 25 01:28:04 [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b Oct 25 01:28:04 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:04 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:04 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:04 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:04 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:04 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:04 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:04 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:04 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:04 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:04 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:04 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:04 [drm:intel_enable_pipe [i915]] enabling pipe A Oct 25 01:28:04 [drm:intel_edp_backlight_on [i915]] Oct 25 01:28:04 [drm:intel_panel_enable_backlight [i915]] pipe A Oct 25 01:28:04 [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 22 Oct 25 01:28:04 [drm:intel_psr_enable_locked [i915]] Enabling PSR1 Oct 25 01:28:04 [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS Oct 25 01:28:04 [drm:verify_connector_state.isra.132 [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:04 [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe A] Oct 25 01:28:04 [drm:verify_single_dpll_state.isra.85 [i915]] DPLL 0 Oct 25 01:28:04 [drm:intel_enable_sagv [i915]] Enabling the SAGV Oct 25 01:28:04 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:04 Console: switching to colour frame buffer device 420x131 Oct 25 01:28:04 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:04 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:04 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c1a41c Oct 25 01:28:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c1a41c Oct 25 01:28:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000811dfcb3 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001bab05ef state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000ab3122dd state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000ab3122dd Oct 25 01:28:04 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000006afceba5 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000006afceba5 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000c6bbb041 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000e460bb76 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000e460bb76 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 000000001c2c4f00 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 000000001c2c4f00 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 0000000027dea594 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 000000003ae8139f state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 000000003ae8139f Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 00000000f2791a4d state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 00000000f2791a4d Oct 25 01:28:04 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 000000001bab05ef Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 00000000811dfcb3 Oct 25 01:28:04 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000004eec77c6 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000004eec77c6 to [NOCRTC] Oct 25 01:28:04 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000004eec77c6 to [CRTC:45:pipe A] Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 000000003ad45f9e state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 000000003ad45f9e Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 00000000c6bbb041 Oct 25 01:28:04 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f2791a4d state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003ad45f9e state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000003ae8139f state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000003ae8139f Oct 25 01:28:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003ae8139f state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003ad45f9e state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000f2791a4d state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000f2791a4d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 0000000027dea594 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 0000000027dea594 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 000000001c2c4f00 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000e460bb76 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000e460bb76 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000c6bbb041 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000c6bbb041 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 000000006afceba5 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000ab3122dd state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000ab3122dd Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 00000000811dfcb3 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 00000000811dfcb3 Oct 25 01:28:04 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 000000003ad45f9e Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 000000003ae8139f Oct 25 01:28:04 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000004eec77c6 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000004eec77c6 to [NOCRTC] Oct 25 01:28:04 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000004eec77c6 to [CRTC:45:pipe A] Oct 25 01:28:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000811dfcb3 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003ad45f9e state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000ab3122dd state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000ab3122dd Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000006afceba5 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000006afceba5 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000c6bbb041 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000e460bb76 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000e460bb76 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 000000001c2c4f00 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 000000001c2c4f00 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 0000000027dea594 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000f2791a4d state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000f2791a4d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 000000003ae8139f state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 000000003ae8139f Oct 25 01:28:04 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 000000003ad45f9e Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 00000000811dfcb3 Oct 25 01:28:04 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000004eec77c6 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000004eec77c6 to [NOCRTC] Oct 25 01:28:04 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000004eec77c6 to [CRTC:45:pipe A] Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 00000000d41a3ff1 state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 00000000d41a3ff1 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 00000000c6bbb041 Oct 25 01:28:04 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 0000000013b906bf state to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 0000000013b906bf Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 0000000027dea594 Oct 25 01:28:04 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_check_only [drm]] checking 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1] Oct 25 01:28:04 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A] Oct 25 01:28:04 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109 Oct 25 01:28:04 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:04 [drm:drm_atomic_commit [drm]] committing 00000000e7d7a34d Oct 25 01:28:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7d7a34d Oct 25 01:28:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7d7a34d Oct 25 01:28:04 i915 0000:00:02.0: fb0: inteldrmfb frame buffer device Oct 25 01:28:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000226def62 state to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000c34b1b76 state to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000007c6e968e state to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000007c6e968e Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000008f906659 state to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000008f906659 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000a661e9a7 state to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000ae6efa3a state to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000ae6efa3a Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 0000000072ba062a state to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 0000000072ba062a Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 0000000064c353c6 state to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000027a1005 state to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000027a1005 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 00000000976ba9d7 state to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 00000000976ba9d7 Oct 25 01:28:04 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 00000000c34b1b76 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 00000000226def62 Oct 25 01:28:04 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 0000000062da1d07 state to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 0000000062da1d07 to [NOCRTC] Oct 25 01:28:04 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 0000000062da1d07 to [CRTC:45:pipe A] Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 0000000041f03b49 state to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 0000000041f03b49 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 00000000a661e9a7 Oct 25 01:28:04 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 00000000a19cb17a state to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 00000000a19cb17a Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 0000000064c353c6 Oct 25 01:28:04 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_check_only [drm]] checking 0000000088d7b300 Oct 25 01:28:04 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1] Oct 25 01:28:04 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A] Oct 25 01:28:04 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109 Oct 25 01:28:04 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:04 [drm:drm_atomic_commit [drm]] committing 0000000088d7b300 Oct 25 01:28:04 [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] Oct 25 01:28:04 [drm:drm_setup_crtcs [drm_kms_helper]] Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] Oct 25 01:28:04 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000088d7b300 Oct 25 01:28:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000088d7b300 Oct 25 01:28:04 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:04 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:04 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:04 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:04 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:04 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:04 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Oct 25 01:28:04 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes : Oct 25 01:28:04 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9 Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] Oct 25 01:28:04 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1] Oct 25 01:28:04 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:04 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:04 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:04 random: fast init done Oct 25 01:28:04 kauditd_printk_skb: 2 callbacks suppressed Oct 25 01:28:04 audit: type=1130 audit(1540456084.575:13): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-ask-password-plymouth comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:04 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:04 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:04 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:04 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 Oct 25 01:28:04 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:04 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 Oct 25 01:28:04 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:04 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] Oct 25 01:28:04 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2] Oct 25 01:28:04 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:04 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:04 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:04 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:04 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:04 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:04 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 Oct 25 01:28:04 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:04 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 Oct 25 01:28:04 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:04 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected Oct 25 01:28:04 [drm:drm_setup_crtcs [drm_kms_helper]] connector 83 enabled? yes Oct 25 01:28:04 [drm:drm_setup_crtcs [drm_kms_helper]] connector 90 enabled? no Oct 25 01:28:04 [drm:drm_setup_crtcs [drm_kms_helper]] connector 96 enabled? no Oct 25 01:28:04 [drm:drm_setup_crtcs [drm_kms_helper]] connector 101 enabled? no Oct 25 01:28:04 [drm:drm_setup_crtcs [drm_kms_helper]] connector 106 enabled? no Oct 25 01:28:04 [drm:intel_fb_initial_config [i915]] Not using firmware configuration Oct 25 01:28:04 [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 83 Oct 25 01:28:04 [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 83 0 Oct 25 01:28:04 [drm:drm_setup_crtcs [drm_kms_helper]] found mode 2880x1800 Oct 25 01:28:04 [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 3360x2100 config Oct 25 01:28:04 [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 2880x1800 set on crtc 45 (0,0) Oct 25 01:28:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004100b83b state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000063867f09 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000b2627f67 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000b2627f67 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000dda82541 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000dda82541 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000f8720a28 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f8720a28 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000063867f09 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000dda82541 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000dda82541 Oct 25 01:28:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dda82541 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000063867f09 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000f8720a28 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000f8720a28 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000b2627f67 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000b2627f67 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 000000004100b83b state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 0000000073b3c55a state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 0000000073b3c55a Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000c901a080 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000c901a080 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 000000008853d0d4 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000c819dde2 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000c819dde2 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 000000006d034443 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 000000006d034443 Oct 25 01:28:04 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 0000000063867f09 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 00000000dda82541 Oct 25 01:28:04 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000cbd062b6 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000cbd062b6 to [NOCRTC] Oct 25 01:28:04 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000cbd062b6 to [CRTC:45:pipe A] Oct 25 01:28:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006d034443 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000063867f09 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000c819dde2 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000c819dde2 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000008853d0d4 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000008853d0d4 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000c901a080 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 0000000073b3c55a state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 0000000073b3c55a Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 000000007e10cb20 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 000000007e10cb20 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 00000000000a752a state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000b7f8a38d state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000b7f8a38d Oct 25 01:28:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 00000000a4cc17e0 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 00000000a4cc17e0 Oct 25 01:28:04 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 0000000063867f09 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 000000006d034443 Oct 25 01:28:04 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000cbd062b6 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000cbd062b6 to [NOCRTC] Oct 25 01:28:04 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000cbd062b6 to [CRTC:45:pipe A] Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 00000000ded4f3a4 state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 00000000ded4f3a4 Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 00000000c901a080 Oct 25 01:28:04 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 00000000cdcefe3d state to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 00000000cdcefe3d Oct 25 01:28:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 00000000000a752a Oct 25 01:28:04 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_check_only [drm]] checking 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1] Oct 25 01:28:04 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A] Oct 25 01:28:04 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109 Oct 25 01:28:04 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:04 [drm:drm_atomic_commit [drm]] committing 000000009a9d4502 Oct 25 01:28:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a9d4502 Oct 25 01:28:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a9d4502 Oct 25 01:28:04 [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] Oct 25 01:28:04 [drm:drm_setup_crtcs [drm_kms_helper]] Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] Oct 25 01:28:04 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:04 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:04 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:04 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:04 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:04 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:04 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:04 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Oct 25 01:28:04 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes : Oct 25 01:28:04 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9 Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] Oct 25 01:28:04 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1] Oct 25 01:28:04 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:04 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:04 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:04 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:04 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:04 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:04 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 Oct 25 01:28:04 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:04 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 Oct 25 01:28:04 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:04 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] Oct 25 01:28:04 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2] Oct 25 01:28:04 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:04 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected Oct 25 01:28:04 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:04 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:04 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:04 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:04 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:04 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 Oct 25 01:28:04 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:04 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 Oct 25 01:28:04 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:04 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:04 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:04 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:05 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:05 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected Oct 25 01:28:05 [drm:drm_setup_crtcs [drm_kms_helper]] connector 83 enabled? yes Oct 25 01:28:05 [drm:drm_setup_crtcs [drm_kms_helper]] connector 90 enabled? no Oct 25 01:28:05 [drm:drm_setup_crtcs [drm_kms_helper]] connector 96 enabled? no Oct 25 01:28:05 [drm:drm_setup_crtcs [drm_kms_helper]] connector 101 enabled? no Oct 25 01:28:05 [drm:drm_setup_crtcs [drm_kms_helper]] connector 106 enabled? no Oct 25 01:28:05 [drm:intel_fb_initial_config [i915]] Not using firmware configuration Oct 25 01:28:05 [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 83 Oct 25 01:28:05 [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 83 0 Oct 25 01:28:05 [drm:drm_setup_crtcs [drm_kms_helper]] found mode 2880x1800 Oct 25 01:28:05 [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 3360x2100 config Oct 25 01:28:05 [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 2880x1800 set on crtc 45 (0,0) Oct 25 01:28:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] Oct 25 01:28:05 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:05 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:05 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:05 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:05 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Oct 25 01:28:05 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes : Oct 25 01:28:05 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9 Oct 25 01:28:05 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:05 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:05 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:05 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:05 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:05 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:05 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:05 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:05 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:05 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fdfe8048 state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000085ba4f7a state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000f67a256e state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000f67a256e Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 0000000021f13594 state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 0000000021f13594 Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000e4615e91 state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 000000003c977655 state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 000000003c977655 Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 000000000ea2083b state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 000000000ea2083b Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 00000000f6011129 state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000d9306151 state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000d9306151 Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 00000000ccb23637 state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 00000000ccb23637 Oct 25 01:28:05 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 0000000085ba4f7a Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 00000000fdfe8048 Oct 25 01:28:05 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 0000000062da1d07 state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 0000000062da1d07 to [NOCRTC] Oct 25 01:28:05 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 0000000062da1d07 to [CRTC:45:pipe A] Oct 25 01:28:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 00000000203c25dc state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 00000000203c25dc Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 00000000e4615e91 Oct 25 01:28:05 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 000000008af53c5a state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 000000008af53c5a Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 00000000f6011129 Oct 25 01:28:05 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_check_only [drm]] checking 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1] Oct 25 01:28:05 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A] Oct 25 01:28:05 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109 Oct 25 01:28:05 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:05 [drm:drm_atomic_commit [drm]] committing 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fd9c1bdc Oct 25 01:28:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000031740a82 state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005b535329 state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000811dfcb3 state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000811dfcb3 Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000005b2c3bf0 state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000005b2c3bf0 Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000879a9656 state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 000000002a584df7 state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 000000002a584df7 Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 000000004e6df67a state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 000000004e6df67a Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 0000000067b22faf state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000274085b5 state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000274085b5 Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 00000000cb5f6008 state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 00000000cb5f6008 Oct 25 01:28:05 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 000000005b535329 Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 0000000031740a82 Oct 25 01:28:05 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000000642812a state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000000642812a to [NOCRTC] Oct 25 01:28:05 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000000642812a to [CRTC:45:pipe A] Oct 25 01:28:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 0000000014f0d2e1 state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 0000000014f0d2e1 Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 00000000879a9656 Oct 25 01:28:05 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 00000000ed8854a5 state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 00000000ed8854a5 Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 0000000067b22faf Oct 25 01:28:05 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_check_only [drm]] checking 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1] Oct 25 01:28:05 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A] Oct 25 01:28:05 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109 Oct 25 01:28:05 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:05 [drm:drm_atomic_commit [drm]] committing 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fd9c1bdc Oct 25 01:28:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] Oct 25 01:28:05 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1] Oct 25 01:28:05 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:05 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected Oct 25 01:28:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:05 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:05 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:05 audit: type=1130 audit(1540456085.142:14): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-vconsole-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:05 audit: type=1131 audit(1540456085.142:15): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-vconsole-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:05 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:05 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:05 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 Oct 25 01:28:05 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:05 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 Oct 25 01:28:05 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:05 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected Oct 25 01:28:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] Oct 25 01:28:05 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2] Oct 25 01:28:05 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:05 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected Oct 25 01:28:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:05 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:05 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:05 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:05 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:05 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 Oct 25 01:28:05 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:05 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 Oct 25 01:28:05 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:05 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected Oct 25 01:28:05 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:05 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:05 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:05 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:05 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:05 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:05 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:05 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:05 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:05 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:05 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:05 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:05 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:05 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:05 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:05 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:05 [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe A] Oct 25 01:28:05 [drm:drm_mode_setcrtc [drm]] [CONNECTOR:83:eDP-1] Oct 25 01:28:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cdcefe3d state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d9e8bfae state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 00000000cdcefe3d Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000d9e8bfae Oct 25 01:28:05 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 0000000009721da3 state to 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 0000000009721da3 to [NOCRTC] Oct 25 01:28:05 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 0000000009721da3 to [CRTC:45:pipe A] Oct 25 01:28:05 [drm:drm_atomic_check_only [drm]] checking 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1] Oct 25 01:28:05 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A] Oct 25 01:28:05 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:05 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:05 [drm:drm_atomic_commit [drm]] committing 000000009a9d4502 Oct 25 01:28:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a9d4502 Oct 25 01:28:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a9d4502 Oct 25 01:28:05 [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe A] Oct 25 01:28:05 [drm:drm_mode_setcrtc [drm]] [CONNECTOR:83:eDP-1] Oct 25 01:28:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008f392724 state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005a51c4ab state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 000000008f392724 Oct 25 01:28:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000005a51c4ab Oct 25 01:28:05 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000006e7f6206 state to 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000006e7f6206 to [NOCRTC] Oct 25 01:28:05 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000006e7f6206 to [CRTC:45:pipe A] Oct 25 01:28:05 [drm:drm_atomic_check_only [drm]] checking 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1] Oct 25 01:28:05 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A] Oct 25 01:28:05 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:05 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:05 [drm:drm_atomic_commit [drm]] committing 00000000fd9c1bdc Oct 25 01:28:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fd9c1bdc Oct 25 01:28:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fd9c1bdc Oct 25 01:28:05 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:05 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:05 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:05 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:05 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:05 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:05 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:05 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:05 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:05 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:05 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:05 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:05 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:05 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:05 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:05 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:05 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:05 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:05 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:05 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:05 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:05 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:05 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:05 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:05 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:05 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:05 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:05 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:05 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:05 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:06 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:06 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:06 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:06 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:06 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:06 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:06 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:06 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:06 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:06 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:06 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:06 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:06 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:06 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:06 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:06 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:06 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:06 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:06 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:06 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:06 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:06 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:06 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:06 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:06 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:06 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:06 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:06 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:06 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:06 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:06 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:06 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:06 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:06 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:06 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:06 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:06 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:06 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:06 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:06 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:06 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:06 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:06 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:06 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:06 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:06 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:06 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:06 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:06 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:06 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:06 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:06 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:06 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:06 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:06 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:06 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:06 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:06 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:06 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:06 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:06 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:06 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:06 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:06 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:06 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:06 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:06 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:07 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:07 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:07 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:07 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:07 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:07 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:07 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:07 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:07 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:07 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:07 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:07 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:07 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:07 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:07 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:07 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:07 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:07 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:07 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:07 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:07 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:07 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:07 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:07 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:07 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:07 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:07 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:07 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:07 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:07 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:07 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:07 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:07 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:07 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:07 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:07 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:07 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:07 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:07 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:07 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:07 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:07 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:07 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:07 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:07 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:07 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:07 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:07 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:07 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:07 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:07 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:07 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:07 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:07 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:07 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:07 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:07 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:07 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:07 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:07 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:08 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:08 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:08 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:08 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:08 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:08 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:08 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:08 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:08 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:08 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:08 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:08 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:08 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:08 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:08 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:08 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:08 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:08 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:08 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:08 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:08 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:08 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:08 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:08 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:08 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:08 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:08 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:08 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:08 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:08 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:08 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:08 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:08 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:08 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:08 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:08 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:08 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:08 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:08 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:08 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:08 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:08 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:08 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:08 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:08 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:08 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:08 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:08 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:08 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:08 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:08 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:08 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:08 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:08 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:08 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:08 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:08 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:08 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:08 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:08 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:08 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:08 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:08 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:08 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:08 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:08 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:08 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:08 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:08 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:09 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:09 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:09 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:09 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:09 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:09 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:09 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:09 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:09 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:09 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:09 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:09 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:09 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:09 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:09 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:09 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:09 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:09 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:09 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:09 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:09 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:09 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:09 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:09 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:09 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:09 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:09 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:09 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:09 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:09 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:09 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:09 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:09 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:09 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:09 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:09 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:09 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:09 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:09 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:09 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:09 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:09 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:09 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:09 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:09 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:09 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:09 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:09 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:09 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:09 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:09 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:09 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:09 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:09 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:09 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:09 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:09 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:09 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:09 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:09 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:09 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:09 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:09 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:09 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:09 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:09 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:09 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:10 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:10 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:10 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:10 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:10 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:10 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:10 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:10 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:10 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:10 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:10 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:10 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:10 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:10 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:10 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:10 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:10 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:10 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:10 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:10 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:10 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:10 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:10 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:10 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:10 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:10 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:10 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:10 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:10 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:10 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:10 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:10 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:10 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:10 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:10 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:10 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:10 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:10 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:10 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:10 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:10 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:10 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:10 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:10 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:10 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:10 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:10 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:10 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:10 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:10 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:10 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:10 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:10 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:10 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:10 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:10 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:10 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:10 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:10 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:10 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:11 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:11 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:11 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:11 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:11 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:11 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:11 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:11 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:11 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:11 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:11 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:11 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:11 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:11 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:11 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:11 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:11 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:11 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:11 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:11 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:11 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:11 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:11 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:11 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:11 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:11 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:11 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:11 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:11 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:11 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:11 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:11 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:11 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:11 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:11 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:11 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:11 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:11 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:11 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:11 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:11 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:11 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:11 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:11 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:11 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:11 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:11 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:11 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:11 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:11 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:11 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:11 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:11 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:11 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:11 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:11 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:11 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:11 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:11 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:11 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:11 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:11 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:11 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:11 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:11 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:11 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:11 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:11 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:11 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:12 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:12 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:12 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:12 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:12 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:12 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:12 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:12 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:12 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:12 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:12 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:12 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:12 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:12 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:12 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:12 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:12 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:12 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:12 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:12 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:12 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:12 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:12 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:12 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:12 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:13 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:13 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:13 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:13 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:13 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:13 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:13 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:13 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:13 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:13 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:13 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:13 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:13 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:13 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:13 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:13 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:13 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:13 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:13 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:13 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:13 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:13 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:13 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:13 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:13 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:13 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:13 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:13 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:13 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:13 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:13 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:13 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:13 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:13 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:13 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:13 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:13 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:13 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:13 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:13 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:13 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:13 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:13 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:13 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:13 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:13 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:13 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:13 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:13 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:13 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:13 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:13 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:13 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:13 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:14 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:14 audit: type=1130 audit(1540456094.081:16): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-cryptsetup@luks\x2d7d238e07\x2dc0ca\x2d40f5\x2db0b8\x2d5272c02bd87b comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:14 audit: type=1130 audit(1540456094.321:17): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-initqueue comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:14 audit: type=1130 audit(1540456094.382:18): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-fsck-root comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:14 EXT4-fs (dm-0): mounted filesystem with ordered data mode. Opts: (null) Oct 25 01:28:14 audit: type=1130 audit(1540456094.542:19): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=initrd-parse-etc comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:14 audit: type=1131 audit(1540456094.542:20): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=initrd-parse-etc comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:14 audit: type=1130 audit(1540456094.554:21): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-cmdline comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:14 audit: type=1131 audit(1540456094.554:22): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-cmdline comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:14 audit: type=1130 audit(1540456094.555:23): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-initqueue comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:14 audit: type=1131 audit(1540456094.555:24): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-initqueue comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:14 audit: type=1130 audit(1540456094.561:25): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-tmpfiles-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:15 journald[242]: Received SIGTERM from PID 1 (systemd). Oct 25 01:28:15 systemd: 22 output lines suppressed due to ratelimiting Oct 25 01:28:15 SELinux: Class bpf not defined in policy. Oct 25 01:28:15 SELinux: Class xdp_socket not defined in policy. Oct 25 01:28:15 SELinux: the above unknown classes and permissions will be allowed Oct 25 01:28:15 SELinux: policy capability network_peer_controls=1 Oct 25 01:28:15 SELinux: policy capability open_perms=1 Oct 25 01:28:15 SELinux: policy capability extended_socket_class=1 Oct 25 01:28:15 SELinux: policy capability always_check_network=0 Oct 25 01:28:15 SELinux: policy capability cgroup_seclabel=1 Oct 25 01:28:15 SELinux: policy capability nnp_nosuid_transition=1 Oct 25 01:28:15 random: crng init done Oct 25 01:28:15 EXT4-fs (dm-0): re-mounted. Opts: (null) Oct 25 01:28:16 apple_gmux: Found gmux version 4.0.29 [indexed] Oct 25 01:28:16 smbus_hc ACPI0001:00: SBS HC: offset = 0x20, query_bit = 0x10 Oct 25 01:28:16 ACPI: Smart Battery System [SBS0]: AC Adapter [AC0] (on-line) Oct 25 01:28:16 thunderbolt 0000:06:00.0: NHI initialized, starting thunderbolt Oct 25 01:28:16 thunderbolt 0000:06:00.0: allocating TX ring 0 of size 10 Oct 25 01:28:16 thunderbolt 0000:06:00.0: allocating RX ring 0 of size 10 Oct 25 01:28:16 thunderbolt 0000:06:00.0: control channel created Oct 25 01:28:16 thunderbolt 0000:06:00.0: control channel starting... Oct 25 01:28:16 thunderbolt 0000:06:00.0: starting TX ring 0 Oct 25 01:28:16 thunderbolt 0000:06:00.0: enabling interrupt at register 0x38200 bit 0 (0x0 -> 0x1) Oct 25 01:28:16 thunderbolt 0000:06:00.0: starting RX ring 0 Oct 25 01:28:16 thunderbolt 0000:06:00.0: enabling interrupt at register 0x38200 bit 12 (0x1 -> 0x1001) Oct 25 01:28:16 thunderbolt 0000:06:00.0: starting ICM firmware Oct 25 01:28:16 [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off Oct 25 01:28:16 [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007 Oct 25 01:28:16 [drm:intel_power_well_disable [i915]] disabling DC off Oct 25 01:28:16 [drm:gen9_dc_off_power_well_disable [i915]] Enabling DC6 Oct 25 01:28:16 [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 Oct 25 01:28:16 Bluetooth: Core ver 2.22 Oct 25 01:28:16 NET: Registered protocol family 31 Oct 25 01:28:16 Bluetooth: HCI device and connection manager initialized Oct 25 01:28:16 Bluetooth: HCI socket layer initialized Oct 25 01:28:16 Bluetooth: L2CAP socket layer initialized Oct 25 01:28:16 Bluetooth: SCO socket layer initialized Oct 25 01:28:16 [drm:intel_backlight_device_update_status [i915]] updating intel_backlight, brightness=1388/2777 Oct 25 01:28:16 [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 1388 Oct 25 01:28:16 [drm:intel_power_well_enable [i915]] enabling DC off Oct 25 01:28:16 [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 Oct 25 01:28:16 [drm:intel_power_well_disable [i915]] disabling DC off Oct 25 01:28:16 [drm:gen9_dc_off_power_well_disable [i915]] Enabling DC6 Oct 25 01:28:16 [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 Oct 25 01:28:16 ACPI: Smart Battery System [SBS0]: Battery Slot [BAT0] (battery present) Oct 25 01:28:16 input: Apple Inc. iBridge as /devices/pci0000:00/0000:00:14.0/usb1/1-3/1-3:1.2/0003:05AC:8600.0001/input/input9 Oct 25 01:28:16 apple-ibridge-hid 0003:05AC:8600.0001: input,hidraw0: USB HID v1.01 Keyboard [Apple Inc. iBridge] on usb-0000:00:14.0-3/input2 Oct 25 01:28:16 apple-ib-als: Found ambient light sensor Oct 25 01:28:16 apple-ibridge-hid 0003:05AC:8600.0002: device probe done. Oct 25 01:28:16 apple-ibridge-hid 0003:05AC:8600.0002: hiddev96,hidraw1: USB HID v1.01 Device [Apple Inc. iBridge] on usb-0000:00:14.0-3/input3 Oct 25 01:28:17 apple-ibridge: registered driver 'apple-ib-als' Oct 25 01:28:17 media: Linux media interface: v0.10 Oct 25 01:28:17 Bluetooth: HCI UART driver ver 2.3 Oct 25 01:28:17 Bluetooth: HCI UART protocol H4 registered Oct 25 01:28:17 Bluetooth: HCI UART protocol BCSP registered Oct 25 01:28:17 Bluetooth: HCI UART protocol LL registered Oct 25 01:28:17 Bluetooth: HCI UART protocol ATH3K registered Oct 25 01:28:17 Bluetooth: HCI UART protocol Three-wire (H5) registered Oct 25 01:28:17 Bluetooth: HCI UART protocol Intel registered Oct 25 01:28:17 Bluetooth: HCI UART protocol Broadcom registered Oct 25 01:28:17 Bluetooth: HCI UART protocol QCA registered Oct 25 01:28:17 Bluetooth: HCI UART protocol AG6XX registered Oct 25 01:28:17 Bluetooth: HCI UART protocol Marvell registered Oct 25 01:28:17 mei_me 0000:00:16.0: enabling device (0000 -> 0002) Oct 25 01:28:17 idma64 idma64.0: Found Intel integrated DMA 64-bit Oct 25 01:28:17 idma64 idma64.2: Found Intel integrated DMA 64-bit Oct 25 01:28:17 hci_uart_bcm serial1-0: Unexpected ACPI gpio_int_idx: -1 Oct 25 01:28:17 hci_uart_bcm serial1-0: Unexpected number of ACPI GPIOs: 0 Oct 25 01:28:17 hci_uart_bcm serial1-0: No reset resource, using default baud rate Oct 25 01:28:17 idma64 idma64.3: Found Intel integrated DMA 64-bit Oct 25 01:28:17 DMAR: Allocating domain for idma64.2 failed Oct 25 01:28:17 ttyS5 - failed to request DMA Oct 25 01:28:17 cfg80211: Loading compiled-in X.509 certificates for regulatory database Oct 25 01:28:17 i801_smbus 0000:00:1f.4: enabling device (0000 -> 0003) Oct 25 01:28:17 cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' Oct 25 01:28:17 videodev: Linux video capture interface: v2.00 Oct 25 01:28:17 i801_smbus 0000:00:1f.4: SMBus using PCI interrupt Oct 25 01:28:17 idma64 idma64.4: Found Intel integrated DMA 64-bit Oct 25 01:28:17 idma64 idma64.5: Found Intel integrated DMA 64-bit Oct 25 01:28:17 input: PC Speaker as /devices/platform/pcspkr/input/input10 Oct 25 01:28:17 uvcvideo: Found UVC 1.50 device iBridge (05ac:8600) Oct 25 01:28:17 uvcvideo 1-3:1.0: Entity type for entity Camera 1 was not initialized! Oct 25 01:28:17 usbcore: registered new interface driver uvcvideo Oct 25 01:28:17 USB Video Class driver (1.1.1) Oct 25 01:28:17 RAPL PMU: API unit is 2^-32 Joules, 5 fixed counters, 655360 ms ovfl timer Oct 25 01:28:17 RAPL PMU: hw unit of domain pp0-core 2^-14 Joules Oct 25 01:28:17 RAPL PMU: hw unit of domain package 2^-14 Joules Oct 25 01:28:17 RAPL PMU: hw unit of domain dram 2^-14 Joules Oct 25 01:28:17 RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules Oct 25 01:28:17 RAPL PMU: hw unit of domain psys 2^-14 Joules Oct 25 01:28:17 usbcore: registered new interface driver brcmfmac Oct 25 01:28:17 brcmfmac 0000:03:00.0: enabling device (0000 -> 0002) Oct 25 01:28:17 applesmc: key=858 fan=2 temp=46 index=45 acc=0 lux=0 kbd=0 Oct 25 01:28:17 applesmc applesmc.768: hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info(). Oct 25 01:28:17 Bluetooth: hci0: BCM: failed to write update baudrate (-16) Oct 25 01:28:17 Bluetooth: hci0: Failed to set baudrate Oct 25 01:28:17 usbcore: registered new interface driver rtl8812au Oct 25 01:28:17 brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43602-pcie for chip BCM43602/2 Oct 25 01:28:17 brcmfmac 0000:03:00.0: Direct firmware load for brcm/brcmfmac43602-pcie.txt failed with error -2 Oct 25 01:28:17 RTL871X: module init start Oct 25 01:28:17 RTL871X: rtl8812au v4.3.14_13455.20150212_BTCOEX20150128-51 Oct 25 01:28:17 RTL871X: rtl8812au BT-Coex version = BTCOEX20150128-51 Oct 25 01:28:17 ------------[ cut here ]------------ Oct 25 01:28:17 proc_dir_entry 'net/rtl8812au' already registered Oct 25 01:28:17 WARNING: CPU: 1 PID: 737 at fs/proc/generic.c:360 proc_register+0x104/0x140 Oct 25 01:28:17 Modules linked in: rtl8812au(OE+) acpi_cpufreq(E-) x86_pkg_temp_thermal(E) intel_powerclamp(E) coretemp(E) kvm_intel(E) applesmc(E) input_polldev(E) brcmfmac(E) kvm(E) brcmutil(E) mmc_core(E) irqbypass(E) intel_cstate(E) intel_uncore(E) intel_rapl_perf(E) 8812au(OE) uvcvideo(E) pcspkr(E) videobuf2_vmalloc(E) videobuf2_memops(E) videobuf2_v4l2(E) videobuf2_common(E) i2c_i801(E) videodev(E) mei_me(E) joydev(E) cfg80211(E) media(E) mei(E) idma64(E) hci_uart(E) pcc_cpufreq(E) btqca(E) btrtl(E) btbcm(E) btintel(E) bluetooth(E) thunderbolt(E+) apple_ib_als(OE) industrialio_triggered_buffer(E) kfifo_buf(E) industrialio(E) ecdh_generic(E) sbs(E) rfkill(E) sbshc(E) apple_gmux(E) apple_bl(E) dm_crypt(E) i915(E) spi_pxa2xx_platform(E) apple_ib_tb(OE) i2c_algo_bit(E) drm_kms_helper(E) crct10dif_pclmul(E) Oct 25 01:28:17 crc32_pclmul(E) crc32c_intel(E) ghash_clmulni_intel(E) drm(E) nvme(E) nvme_core(E) intel_lpss_pci(E) intel_lpss(E) apple_ibridge(OE) applespi(OE) video(E) Oct 25 01:28:17 CPU: 1 PID: 737 Comm: systemd-udevd Tainted: G W OE 4.19.0-rc8-drm #14 Oct 25 01:28:17 Hardware name: Apple Inc. MacBookPro13,3/Mac-A5C67F76ED83108C, BIOS MBP133.88Z.0247.B00.1806261159 06/26/2018 Oct 25 01:28:17 RIP: 0010:proc_register+0x104/0x140 Oct 25 01:28:17 Code: 6b ac e8 5f 3c 6c 00 48 89 d8 5b 5d 41 5c 41 5d 41 5e c3 49 8b b4 24 d8 00 00 00 4c 89 f2 48 c7 c7 78 65 30 ac e8 64 93 d2 ff <0f> 0b 48 c7 c7 40 0e 6b ac e8 2e 3c 6c 00 8b 83 94 00 00 00 48 c7 Oct 25 01:28:17 RSP: 0018:ffffb7dc8292fc40 EFLAGS: 00010286 Oct 25 01:28:17 RAX: 0000000000000000 RBX: ffff93dfe46a9a00 RCX: 0000000000000006 Oct 25 01:28:17 RDX: 0000000000000007 RSI: ffff93dfe07548e8 RDI: ffff93dfedfd6c80 Oct 25 01:28:17 RBP: ffff93dfe2f912c0 R08: 000000121f7616c1 R09: 0000000000000000 Oct 25 01:28:17 R10: 0000000000000000 R11: 0000000000000000 R12: ffff93dfeb730900 Oct 25 01:28:17 R13: ffff93dfeb7309b8 R14: ffff93dfe46a9ae3 R15: ffffffffc0e1f140 Oct 25 01:28:17 FS: 00007f140e616180(0000) GS:ffff93dfede00000(0000) knlGS:0000000000000000 Oct 25 01:28:17 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 Oct 25 01:28:17 CR2: 0000559b61851158 CR3: 000000046074a006 CR4: 00000000003606e0 Oct 25 01:28:17 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 Oct 25 01:28:17 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Oct 25 01:28:17 Call Trace: Oct 25 01:28:17 ? 0xffffffffc0999000 Oct 25 01:28:17 proc_mkdir_data+0x63/0x80 Oct 25 01:28:17 rtw_drv_proc_init+0x34/0xa5 [rtl8812au] Oct 25 01:28:17 rtw_drv_entry+0x63/0x1000 [rtl8812au] Oct 25 01:28:17 do_one_initcall+0x5d/0x2be Oct 25 01:28:17 ? do_init_module+0x22/0x210 Oct 25 01:28:17 ? rcu_read_lock_sched_held+0x6b/0x80 Oct 25 01:28:17 ? kmem_cache_alloc_trace+0x24e/0x280 Oct 25 01:28:17 do_init_module+0x5a/0x210 Oct 25 01:28:17 load_module+0x2094/0x2330 Oct 25 01:28:17 ? lockdep_hardirqs_on+0xed/0x180 Oct 25 01:28:17 ? __do_sys_init_module+0x147/0x190 Oct 25 01:28:17 __do_sys_init_module+0x147/0x190 Oct 25 01:28:17 do_syscall_64+0x60/0x1f0 Oct 25 01:28:17 entry_SYSCALL_64_after_hwframe+0x49/0xbe Oct 25 01:28:17 RIP: 0033:0x7f140d24286a Oct 25 01:28:17 Code: 48 8b 0d 39 e6 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 af 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 06 e6 2b 00 f7 d8 64 89 01 48 Oct 25 01:28:17 RSP: 002b:00007fffe745dd08 EFLAGS: 00000246 ORIG_RAX: 00000000000000af Oct 25 01:28:17 RAX: ffffffffffffffda RBX: 0000559b6090e6f0 RCX: 00007f140d24286a Oct 25 01:28:17 RDX: 00007f140dda94cd RSI: 00000000002f87a8 RDI: 0000559b615589b0 Oct 25 01:28:17 RBP: 00007f140dda94cd R08: 0000000000000005 R09: 0000000000000004 Oct 25 01:28:17 R10: 0000559b60898010 R11: 0000000000000246 R12: 0000559b615589b0 Oct 25 01:28:17 R13: 0000559b609097c0 R14: 0000000000020000 R15: 0000000000000000 Oct 25 01:28:17 irq event stamp: 264630 Oct 25 01:28:17 hardirqs last enabled at (264629): [] console_unlock+0x45d/0x600 Oct 25 01:28:17 hardirqs last disabled at (264630): [] trace_hardirqs_off_thunk+0x1a/0x1c Oct 25 01:28:17 softirqs last enabled at (263052): [] peernet2id+0x51/0x80 Oct 25 01:28:17 softirqs last disabled at (263050): [] peernet2id+0x32/0x80 Oct 25 01:28:17 WARNING: CPU: 1 PID: 737 at fs/proc/generic.c:360 proc_register+0x104/0x140 Oct 25 01:28:17 ---[ end trace 533802152e0a7255 ]--- Oct 25 01:28:17 WARNING: CPU: 1 PID: 737 at /var/lib/dkms/rtl8812au/4.3.14/build/os_dep/linux/rtw_proc.c:193 rtw_drv_proc_init+0x99/0xa5 [rtl8812au] Oct 25 01:28:17 Modules linked in: rtl8812au(OE+) acpi_cpufreq(E-) x86_pkg_temp_thermal(E) intel_powerclamp(E) coretemp(E) kvm_intel(E) applesmc(E) input_polldev(E) brcmfmac(E) kvm(E) brcmutil(E) mmc_core(E) irqbypass(E) intel_cstate(E) intel_uncore(E) intel_rapl_perf(E) 8812au(OE) uvcvideo(E) pcspkr(E) videobuf2_vmalloc(E) videobuf2_memops(E) videobuf2_v4l2(E) videobuf2_common(E) i2c_i801(E) videodev(E) mei_me(E) joydev(E) cfg80211(E) media(E) mei(E) idma64(E) hci_uart(E) pcc_cpufreq(E) btqca(E) btrtl(E) btbcm(E) btintel(E) bluetooth(E) thunderbolt(E+) apple_ib_als(OE) industrialio_triggered_buffer(E) kfifo_buf(E) industrialio(E) ecdh_generic(E) sbs(E) rfkill(E) sbshc(E) apple_gmux(E) apple_bl(E) dm_crypt(E) i915(E) spi_pxa2xx_platform(E) apple_ib_tb(OE) i2c_algo_bit(E) drm_kms_helper(E) crct10dif_pclmul(E) Oct 25 01:28:17 crc32_pclmul(E) crc32c_intel(E) ghash_clmulni_intel(E) drm(E) nvme(E) nvme_core(E) intel_lpss_pci(E) intel_lpss(E) apple_ibridge(OE) applespi(OE) video(E) Oct 25 01:28:17 CPU: 1 PID: 737 Comm: systemd-udevd Tainted: G W OE 4.19.0-rc8-drm #14 Oct 25 01:28:17 Hardware name: Apple Inc. MacBookPro13,3/Mac-A5C67F76ED83108C, BIOS MBP133.88Z.0247.B00.1806261159 06/26/2018 Oct 25 01:28:17 RIP: 0010:rtw_drv_proc_init+0x99/0xa5 [rtl8812au] Oct 25 01:28:17 Code: 00 43 d7 c0 48 8b 15 13 ac 0e 00 be b6 81 00 00 48 c7 c7 03 09 d8 c0 e8 22 83 65 ea 48 89 c2 b8 01 00 00 00 48 85 d2 74 04 c3 <0f> 0b c3 0f 0b b8 00 00 00 00 eb f3 0f 1f 44 00 00 48 8b 35 dc ab Oct 25 01:28:17 RSP: 0018:ffffb7dc8292fc88 EFLAGS: 00010246 Oct 25 01:28:17 RAX: 0000000000000000 RBX: 00000000ffffffff RCX: 00000000000000ff Oct 25 01:28:17 RDX: ffff93dfeb730900 RSI: 00000000ffffffff RDI: 0000000000000246 Oct 25 01:28:17 RBP: ffffffffc0999000 R08: 0000000000000001 R09: 0000000000000000 Oct 25 01:28:17 R10: 0000000000000000 R11: 0000000000000000 R12: ffffffffc0e1f340 Oct 25 01:28:17 R13: ffffffffc0e1f158 R14: ffffb7dc8292fe88 R15: ffffffffc0e1f140 Oct 25 01:28:17 FS: 00007f140e616180(0000) GS:ffff93dfede00000(0000) knlGS:0000000000000000 Oct 25 01:28:17 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 Oct 25 01:28:17 CR2: 0000559b61851158 CR3: 000000046074a006 CR4: 00000000003606e0 Oct 25 01:28:17 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 Oct 25 01:28:17 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Oct 25 01:28:17 Call Trace: Oct 25 01:28:17 rtw_drv_entry+0x63/0x1000 [rtl8812au] Oct 25 01:28:17 do_one_initcall+0x5d/0x2be Oct 25 01:28:17 ? do_init_module+0x22/0x210 Oct 25 01:28:17 ? rcu_read_lock_sched_held+0x6b/0x80 Oct 25 01:28:17 ? kmem_cache_alloc_trace+0x24e/0x280 Oct 25 01:28:17 do_init_module+0x5a/0x210 Oct 25 01:28:17 load_module+0x2094/0x2330 Oct 25 01:28:17 ? lockdep_hardirqs_on+0xed/0x180 Oct 25 01:28:17 ? __do_sys_init_module+0x147/0x190 Oct 25 01:28:17 __do_sys_init_module+0x147/0x190 Oct 25 01:28:17 do_syscall_64+0x60/0x1f0 Oct 25 01:28:17 entry_SYSCALL_64_after_hwframe+0x49/0xbe Oct 25 01:28:17 RIP: 0033:0x7f140d24286a Oct 25 01:28:17 Code: 48 8b 0d 39 e6 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 af 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 06 e6 2b 00 f7 d8 64 89 01 48 Oct 25 01:28:17 RSP: 002b:00007fffe745dd08 EFLAGS: 00000246 ORIG_RAX: 00000000000000af Oct 25 01:28:17 RAX: ffffffffffffffda RBX: 0000559b6090e6f0 RCX: 00007f140d24286a Oct 25 01:28:17 RDX: 00007f140dda94cd RSI: 00000000002f87a8 RDI: 0000559b615589b0 Oct 25 01:28:17 RBP: 00007f140dda94cd R08: 0000000000000005 R09: 0000000000000004 Oct 25 01:28:17 R10: 0000559b60898010 R11: 0000000000000246 R12: 0000559b615589b0 Oct 25 01:28:17 R13: 0000559b609097c0 R14: 0000000000020000 R15: 0000000000000000 Oct 25 01:28:17 irq event stamp: 264636 Oct 25 01:28:17 hardirqs last enabled at (264635): [] kmem_cache_free+0xa1/0x2e0 Oct 25 01:28:17 hardirqs last disabled at (264636): [] trace_hardirqs_off_thunk+0x1a/0x1c Oct 25 01:28:17 softirqs last enabled at (263052): [] peernet2id+0x51/0x80 Oct 25 01:28:17 softirqs last disabled at (263050): [] peernet2id+0x32/0x80 Oct 25 01:28:17 WARNING: CPU: 1 PID: 737 at /var/lib/dkms/rtl8812au/4.3.14/build/os_dep/linux/rtw_proc.c:193 rtw_drv_proc_init+0x99/0xa5 [rtl8812au] Oct 25 01:28:17 ---[ end trace 533802152e0a7256 ]--- Oct 25 01:28:17 Error: Driver 'rtl8812au' is already registered, aborting... Oct 25 01:28:17 RTL871X: module init ret=-16 Oct 25 01:28:17 Bluetooth: hci0: BCM: chip id 126 Oct 25 01:28:17 Bluetooth: hci0: BCM: features 0x2f Oct 25 01:28:17 intel_rapl: Found RAPL domain package Oct 25 01:28:17 intel_rapl: Found RAPL domain core Oct 25 01:28:17 intel_rapl: Found RAPL domain uncore Oct 25 01:28:17 intel_rapl: Found RAPL domain dram Oct 25 01:28:17 Bluetooth: hci0: BCM20703A2 Generic UART UHE Apple 40MHz wlcsp_x100 Oct 25 01:28:17 Bluetooth: hci0: BCM (001.002.070) build 0176 Oct 25 01:28:17 bluetooth hci0: Direct firmware load for brcm/BCM.hcd failed with error -2 Oct 25 01:28:17 Bluetooth: hci0: BCM: Patch brcm/BCM.hcd not found Oct 25 01:28:17 Adding 16352652k swap on /var/cache/swapfile. Priority:-2 extents:14 across:17646988k SSDsFS Oct 25 01:28:17 rtl8812au 1-5:1.0 wlp0s20f0u5: renamed from wlan0 Oct 25 01:28:17 brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43602-pcie for chip BCM43602/2 Oct 25 01:28:17 brcmfmac 0000:03:00.0: Direct firmware load for brcm/brcmfmac43602-pcie.clm_blob failed with error -2 Oct 25 01:28:17 brcmfmac: brcmf_c_process_clm_blob: no clm_blob available (err=-2), device may have limited channels available Oct 25 01:28:17 brcmfmac: brcmf_c_preinit_dcmds: Firmware: BCM43602/2 wl0: Nov 10 2015 06:38:10 version 7.35.177.61 (r598657) FWID 01-ea662a8c Oct 25 01:28:17 brcmfmac 0000:03:00.0 wlp3s0: renamed from wlan0 Oct 25 01:28:17 thunderbolt 0000:06:00.0: current switch config: Oct 25 01:28:17 thunderbolt 0000:06:00.0: Switch: 8086:15d3 (Revision: 6, TB Version: 2) Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max Port Number: 11 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Config: Oct 25 01:28:17 thunderbolt 0000:06:00.0: Upstream Port Number: 5 Depth: 0 Route String: 0x0 Enabled: 1, PlugEventsDelay: 254ms Oct 25 01:28:17 thunderbolt 0000:06:00.0: unknown1: 0x0 unknown4: 0x0 Oct 25 01:28:17 thunderbolt 0000:06:00.0: 0: uid: 0x15a4820626a00 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Port 0: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1)) Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max hop id (in/out): 7/7 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max counters: 8 Oct 25 01:28:17 thunderbolt 0000:06:00.0: NFC Credits: 0x800000 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Port 1: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1)) Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max hop id (in/out): 15/15 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max counters: 16 Oct 25 01:28:17 thunderbolt 0000:06:00.0: NFC Credits: 0x3c00000 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Port 2: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1)) Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max hop id (in/out): 15/15 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max counters: 16 Oct 25 01:28:17 thunderbolt 0000:06:00.0: NFC Credits: 0x3c00000 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Port 3: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1)) Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max hop id (in/out): 15/15 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max counters: 16 Oct 25 01:28:17 thunderbolt 0000:06:00.0: NFC Credits: 0x3c00000 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Port 4: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1)) Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max hop id (in/out): 15/15 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max counters: 16 Oct 25 01:28:17 thunderbolt 0000:06:00.0: NFC Credits: 0x3c00000 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Port 5: 8086:15d3 (Revision: 6, TB Version: 1, Type: NHI (0x2)) Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max hop id (in/out): 11/11 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max counters: 16 Oct 25 01:28:17 thunderbolt 0000:06:00.0: NFC Credits: 0x1000000 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Port 6: 8086:15d3 (Revision: 6, TB Version: 1, Type: PCIe (0x100101)) Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max hop id (in/out): 8/8 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max counters: 2 Oct 25 01:28:17 thunderbolt 0000:06:00.0: NFC Credits: 0x800000 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Port 7: 8086:15d3 (Revision: 6, TB Version: 1, Type: PCIe (0x100101)) Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max hop id (in/out): 8/8 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max counters: 2 Oct 25 01:28:17 thunderbolt 0000:06:00.0: NFC Credits: 0x800000 Oct 25 01:28:17 thunderbolt 0000:06:00.0: 0:8: disabled by eeprom Oct 25 01:28:17 thunderbolt 0000:06:00.0: Port 9: 8086:15d3 (Revision: 6, TB Version: 1, Type: DP/HDMI (0xe0101)) Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max hop id (in/out): 9/9 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max counters: 2 Oct 25 01:28:17 thunderbolt 0000:06:00.0: NFC Credits: 0x1000000 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Port 10: 8086:15d3 (Revision: 6, TB Version: 1, Type: DP/HDMI (0xe0101)) Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max hop id (in/out): 9/9 Oct 25 01:28:17 thunderbolt 0000:06:00.0: Max counters: 2 Oct 25 01:28:17 thunderbolt 0000:06:00.0: NFC Credits: 0x1000000 Oct 25 01:28:17 thunderbolt 0000:06:00.0: 0:b: disabled by eeprom Oct 25 01:28:17 thunderbolt 0000:7c:00.0: NHI initialized, starting thunderbolt Oct 25 01:28:17 thunderbolt 0000:7c:00.0: allocating TX ring 0 of size 10 Oct 25 01:28:17 thunderbolt 0000:7c:00.0: allocating RX ring 0 of size 10 Oct 25 01:28:17 thunderbolt 0000:7c:00.0: control channel created Oct 25 01:28:17 thunderbolt 0000:7c:00.0: control channel starting... Oct 25 01:28:17 thunderbolt 0000:7c:00.0: starting TX ring 0 Oct 25 01:28:17 thunderbolt 0000:7c:00.0: enabling interrupt at register 0x38200 bit 0 (0x0 -> 0x1) Oct 25 01:28:17 thunderbolt 0000:7c:00.0: starting RX ring 0 Oct 25 01:28:17 thunderbolt 0000:7c:00.0: enabling interrupt at register 0x38200 bit 12 (0x1 -> 0x1001) Oct 25 01:28:17 thunderbolt 0000:7c:00.0: starting ICM firmware Oct 25 01:28:19 thunderbolt 0000:7c:00.0: current switch config: Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Switch: 8086:15d3 (Revision: 6, TB Version: 2) Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max Port Number: 11 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Config: Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Upstream Port Number: 5 Depth: 0 Route String: 0x0 Enabled: 1, PlugEventsDelay: 254ms Oct 25 01:28:19 thunderbolt 0000:7c:00.0: unknown1: 0x0 unknown4: 0x0 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: 0: uid: 0x15a4820626a01 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Port 0: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1)) Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max hop id (in/out): 7/7 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max counters: 8 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: NFC Credits: 0x800000 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Port 1: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1)) Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max hop id (in/out): 15/15 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max counters: 16 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: NFC Credits: 0x3c00000 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Port 2: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1)) Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max hop id (in/out): 15/15 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max counters: 16 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: NFC Credits: 0x3c00000 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Port 3: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1)) Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max hop id (in/out): 15/15 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max counters: 16 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: NFC Credits: 0x3c00000 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Port 4: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1)) Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max hop id (in/out): 15/15 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max counters: 16 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: NFC Credits: 0x3c00000 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Port 5: 8086:15d3 (Revision: 6, TB Version: 1, Type: NHI (0x2)) Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max hop id (in/out): 11/11 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max counters: 16 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: NFC Credits: 0x1000000 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Port 6: 8086:15d3 (Revision: 6, TB Version: 1, Type: PCIe (0x100101)) Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max hop id (in/out): 8/8 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max counters: 2 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: NFC Credits: 0x800000 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Port 7: 8086:15d3 (Revision: 6, TB Version: 1, Type: PCIe (0x100101)) Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max hop id (in/out): 8/8 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max counters: 2 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: NFC Credits: 0x800000 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: 0:8: disabled by eeprom Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Port 9: 8086:15d3 (Revision: 6, TB Version: 1, Type: DP/HDMI (0xe0101)) Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max hop id (in/out): 9/9 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max counters: 2 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: NFC Credits: 0x1000000 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Port 10: 8086:15d3 (Revision: 6, TB Version: 1, Type: DP/HDMI (0xe0101)) Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max hop id (in/out): 9/9 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: Max counters: 2 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: NFC Credits: 0x1000000 Oct 25 01:28:19 thunderbolt 0000:7c:00.0: 0:b: disabled by eeprom Oct 25 01:28:19 kauditd_printk_skb: 47 callbacks suppressed Oct 25 01:28:19 audit: type=1130 audit(1540456099.155:73): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=systemd-udev-settle comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:19 audit: type=1130 audit(1540456099.158:74): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=lvm2-lvmetad comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:19 audit: type=1130 audit(1540456099.187:75): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=dmraid-activation comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:19 audit: type=1131 audit(1540456099.187:76): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=dmraid-activation comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:19 audit: type=1130 audit(1540456099.196:77): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=lvm2-monitor comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:19 audit: type=1130 audit(1540456099.230:78): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=systemd-fsck@dev-disk-by\x2duuid-c6f4265d\x2dc566\x2d3c5b\x2d9a93\x2dde411b952fac comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:19 audit: type=1130 audit(1540456099.233:79): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=systemd-fsck@dev-disk-by\x2duuid-3823c2c8\x2dd2d3\x2d4174\x2dab59\x2d6bf2019bf2d1 comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:19 EXT4-fs (nvme0n1p4): mounted filesystem with ordered data mode. Opts: (null) Oct 25 01:28:19 audit: type=1130 audit(1540456099.343:80): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=dracut-shutdown comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:19 audit: type=1130 audit(1540456099.348:81): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=nfs-config comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:19 audit: type=1131 audit(1540456099.349:82): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=nfs-config comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' Oct 25 01:28:19 RPC: Registered named UNIX socket transport module. Oct 25 01:28:19 RPC: Registered udp transport module. Oct 25 01:28:19 RPC: Registered tcp transport module. Oct 25 01:28:19 RPC: Registered tcp NFSv4.1 backchannel transport module. Oct 25 01:28:19 Bluetooth: BNEP (Ethernet Emulation) ver 1.3 Oct 25 01:28:19 Bluetooth: BNEP filters: protocol multicast Oct 25 01:28:19 Bluetooth: BNEP socket layer initialized Oct 25 01:28:20 IPv6: ADDRCONF(NETDEV_UP): wlp0s20f0u5: link is not ready Oct 25 01:28:20 Oct 25 01:28:20 ============================================ Oct 25 01:28:20 WARNING: possible recursive locking detected Oct 25 01:28:20 4.19.0-rc8-drm #14 Tainted: G W OE Oct 25 01:28:20 -------------------------------------------- Oct 25 01:28:20 NetworkManager/997 is trying to acquire lock: Oct 25 01:28:20 00000000e7624997 (pmutex){+.+.}, at: usbctrl_vendorreq+0x9b/0x296 [8812au] Oct 25 01:28:20 but task is already holding lock: Oct 25 01:28:20 000000001313a933 (pmutex){+.+.}, at: netdev_open+0x34/0x53 [8812au] Oct 25 01:28:20 other info that might help us debug this: Oct 25 01:28:20 Possible unsafe locking scenario: Oct 25 01:28:20 CPU0 Oct 25 01:28:20 ---- Oct 25 01:28:20 lock(pmutex); Oct 25 01:28:20 lock(pmutex); Oct 25 01:28:20 *** DEADLOCK *** Oct 25 01:28:20 May be due to missing lock nesting notation Oct 25 01:28:20 2 locks held by NetworkManager/997: Oct 25 01:28:20 #0: 00000000d137454a (rtnl_mutex){+.+.}, at: rtnetlink_rcv_msg+0x158/0x4b0 Oct 25 01:28:20 #1: 000000001313a933 (pmutex){+.+.}, at: netdev_open+0x34/0x53 [8812au] Oct 25 01:28:20 stack backtrace: Oct 25 01:28:20 CPU: 3 PID: 997 Comm: NetworkManager Tainted: G W OE 4.19.0-rc8-drm #14 Oct 25 01:28:20 Hardware name: Apple Inc. MacBookPro13,3/Mac-A5C67F76ED83108C, BIOS MBP133.88Z.0247.B00.1806261159 06/26/2018 Oct 25 01:28:20 Call Trace: Oct 25 01:28:20 dump_stack+0x85/0xc0 Oct 25 01:28:20 __lock_acquire.cold.62+0x158/0x227 Oct 25 01:28:20 ? is_bpf_text_address+0x86/0xf0 Oct 25 01:28:20 ? kernel_text_address+0xe5/0xf0 Oct 25 01:28:20 ? __kernel_text_address+0xe/0x30 Oct 25 01:28:20 ? unwind_get_return_address+0x1b/0x30 Oct 25 01:28:20 ? __save_stack_trace+0x92/0x100 Oct 25 01:28:20 lock_acquire+0x9e/0x180 Oct 25 01:28:20 ? usbctrl_vendorreq+0x9b/0x296 [8812au] Oct 25 01:28:20 ? usbctrl_vendorreq+0x9b/0x296 [8812au] Oct 25 01:28:20 __mutex_lock+0x88/0x9c0 Oct 25 01:28:20 ? usbctrl_vendorreq+0x9b/0x296 [8812au] Oct 25 01:28:20 ? usbctrl_vendorreq+0x9b/0x296 [8812au] Oct 25 01:28:20 ? netdev_open+0x34/0x53 [8812au] Oct 25 01:28:20 usbctrl_vendorreq+0x9b/0x296 [8812au] Oct 25 01:28:20 usb_read8+0x3e/0x5d [8812au] Oct 25 01:28:20 _rtw_read8+0x1b/0x1c [8812au] Oct 25 01:28:20 rtl8812au_hal_init+0x78/0x10eb [8812au] Oct 25 01:28:20 rtw_hal_init+0x25/0x96 [8812au] Oct 25 01:28:20 _netdev_open+0x54/0x200 [8812au] Oct 25 01:28:20 netdev_open+0x3c/0x53 [8812au] Oct 25 01:28:20 __dev_open+0xce/0x160 Oct 25 01:28:20 __dev_change_flags+0x1a3/0x210 Oct 25 01:28:20 ? rcu_read_unlock+0x12/0x60 Oct 25 01:28:20 dev_change_flags+0x21/0x60 Oct 25 01:28:20 do_setlink+0x30b/0xf00 Oct 25 01:28:20 ? nla_parse+0xb5/0xe0 Oct 25 01:28:20 ? native_sched_clock+0x3e/0xa0 Oct 25 01:28:20 ? validate_linkmsg+0x19d/0x350 Oct 25 01:28:20 ? native_sched_clock+0x3e/0xa0 Oct 25 01:28:20 rtnl_newlink+0x504/0x810 Oct 25 01:28:20 ? __lock_acquire+0x29a/0x16c0 Oct 25 01:28:20 ? __snmp6_fill_stats64.isra.58+0x6b/0x110 Oct 25 01:28:20 ? native_sched_clock+0x3e/0xa0 Oct 25 01:28:20 ? native_sched_clock+0x3e/0xa0 Oct 25 01:28:20 ? native_sched_clock+0x3e/0xa0 Oct 25 01:28:20 ? native_sched_clock+0x3e/0xa0 Oct 25 01:28:20 ? __lock_acquire+0x29a/0x16c0 Oct 25 01:28:20 ? noop_count+0x10/0x10 Oct 25 01:28:20 ? noop_count+0x10/0x10 Oct 25 01:28:20 ? native_sched_clock+0x3e/0xa0 Oct 25 01:28:20 ? __lock_acquire+0x29a/0x16c0 Oct 25 01:28:20 ? native_sched_clock+0x3e/0xa0 Oct 25 01:28:20 ? __lock_acquire+0x29a/0x16c0 Oct 25 01:28:20 ? find_held_lock+0x60/0xa0 Oct 25 01:28:20 rtnetlink_rcv_msg+0x184/0x4b0 Oct 25 01:28:20 ? netlink_deliver_tap+0x99/0x410 Oct 25 01:28:20 ? native_sched_clock+0x3e/0xa0 Oct 25 01:28:20 ? rtnetlink_put_metrics+0x1b0/0x1b0 Oct 25 01:28:20 netlink_rcv_skb+0x4c/0x120 Oct 25 01:28:20 netlink_unicast+0x196/0x230 Oct 25 01:28:20 netlink_sendmsg+0x218/0x3e0 Oct 25 01:28:20 sock_sendmsg+0x36/0x40 Oct 25 01:28:20 ___sys_sendmsg+0x298/0x2f0 Oct 25 01:28:20 ? __lock_acquire+0x29a/0x16c0 Oct 25 01:28:20 ? native_sched_clock+0x3e/0xa0 Oct 25 01:28:20 ? __fget+0xee/0x1f0 Oct 25 01:28:20 ? __fget+0x10d/0x1f0 Oct 25 01:28:20 __sys_sendmsg+0x57/0xa0 Oct 25 01:28:20 do_syscall_64+0x60/0x1f0 Oct 25 01:28:20 entry_SYSCALL_64_after_hwframe+0x49/0xbe Oct 25 01:28:20 RIP: 0033:0x7f9195984ce7 Oct 25 01:28:20 Code: 44 00 00 41 54 41 89 d4 55 48 89 f5 53 89 fb 48 83 ec 10 e8 0b ea ff ff 44 89 e2 48 89 ee 89 df 41 89 c0 b8 2e 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 35 44 89 c7 48 89 44 24 08 e8 44 ea ff ff 48 Oct 25 01:28:20 RSP: 002b:00007ffc23e46d20 EFLAGS: 00000293 ORIG_RAX: 000000000000002e Oct 25 01:28:20 RAX: ffffffffffffffda RBX: 0000000000000007 RCX: 00007f9195984ce7 Oct 25 01:28:20 RDX: 0000000000000000 RSI: 00007ffc23e46d80 RDI: 0000000000000007 Oct 25 01:28:20 RBP: 00007ffc23e46d80 R08: 0000000000000000 R09: 0000000000000008 Oct 25 01:28:20 R10: 0000561d67c8b010 R11: 0000000000000293 R12: 0000000000000000 Oct 25 01:28:20 R13: 00007ffc23e46d80 R14: 00007ffc23e46f14 R15: 0000000000000000 Oct 25 01:28:20 vboxdrv: Found 8 processor cores Oct 25 01:28:20 vboxdrv: TSC mode is Invariant, tentative frequency 2904008531 Hz Oct 25 01:28:20 vboxdrv: Successfully loaded version 5.2.18 (interface 0x00290001) Oct 25 01:28:20 VBoxNetFlt: Successfully started. Oct 25 01:28:20 VBoxNetAdp: Successfully started. Oct 25 01:28:20 VBoxPciLinuxInit Oct 25 01:28:20 vboxpci: IOMMU found Oct 25 01:28:20 IPv6: ADDRCONF(NETDEV_UP): wlp0s20f0u5: link is not ready Oct 25 01:28:20 IPv6: ADDRCONF(NETDEV_UP): wlp0s20f0u5: link is not ready Oct 25 01:28:20 IPv6: ADDRCONF(NETDEV_UP): wlp3s0: link is not ready Oct 25 01:28:20 IPv6: ADDRCONF(NETDEV_UP): wlp3s0: link is not ready Oct 25 01:28:20 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:20 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:20 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:20 [drm:intel_power_well_enable [i915]] enabling DC off Oct 25 01:28:20 [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 Oct 25 01:28:20 [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on Oct 25 01:28:20 [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f Oct 25 01:28:20 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:20 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:20 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:20 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:20 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:20 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:20 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:20 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:20 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:20 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:20 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:20 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:20 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:20 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:20 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:20 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:20 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:20 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:20 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:20 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:20 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:20 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:20 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:20 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:20 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:20 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:20 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:20 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:20 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:20 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:20 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:20 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:20 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:20 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:20 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:20 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:20 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:20 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:20 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:20 IPv6: ADDRCONF(NETDEV_UP): wlp3s0: link is not ready Oct 25 01:28:21 bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this. Oct 25 01:28:21 tun: Universal TUN/TAP device driver, 1.6 Oct 25 01:28:21 virbr0: port 1(virbr0-nic) entered blocking state Oct 25 01:28:21 virbr0: port 1(virbr0-nic) entered disabled state Oct 25 01:28:21 device virbr0-nic entered promiscuous mode Oct 25 01:28:21 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:21 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:21 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:21 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:21 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:21 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:21 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:21 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:21 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:21 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:21 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:21 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:21 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:21 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:21 IPv6: ADDRCONF(NETDEV_UP): wlp3s0: link is not ready Oct 25 01:28:21 IPv6: ADDRCONF(NETDEV_UP): wlp0s20f0u5: link is not ready Oct 25 01:28:21 virbr0: port 1(virbr0-nic) entered blocking state Oct 25 01:28:21 virbr0: port 1(virbr0-nic) entered listening state Oct 25 01:28:21 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:21 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:21 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:21 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:21 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:21 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:21 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:21 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:21 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:21 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:21 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:21 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:21 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:21 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:21 virbr0: port 1(virbr0-nic) entered disabled state Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] Oct 25 01:28:21 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:21 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:21 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:21 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:21 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Oct 25 01:28:21 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes : Oct 25 01:28:21 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9 Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] Oct 25 01:28:21 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1] Oct 25 01:28:21 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:21 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:21 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:21 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:21 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:21 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:21 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 Oct 25 01:28:21 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:21 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 Oct 25 01:28:21 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:21 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] Oct 25 01:28:21 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2] Oct 25 01:28:21 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:21 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:21 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:21 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:21 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:21 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:21 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 Oct 25 01:28:21 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:21 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 Oct 25 01:28:21 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:21 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:21 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:21 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:21 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:21 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected Oct 25 01:28:21 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:21 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:21 [drm:intel_backlight_device_get_brightness [i915]] get backlight PWM = 1388 Oct 25 01:28:21 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:21 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:21 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:21 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:21 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:21 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:21 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:21 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] Oct 25 01:28:21 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:21 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:21 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:21 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:21 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Oct 25 01:28:21 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes : Oct 25 01:28:21 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9 Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] Oct 25 01:28:21 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1] Oct 25 01:28:21 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:21 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:21 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:21 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:21 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:21 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:21 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 Oct 25 01:28:21 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:21 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 Oct 25 01:28:21 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:21 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:21 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:21 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:21 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:21 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected Oct 25 01:28:21 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:21 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:21 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:21 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:21 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:21 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:21 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:21 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:21 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:21 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:21 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:21 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] Oct 25 01:28:21 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2] Oct 25 01:28:21 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:21 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:21 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:21 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:21 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:21 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:21 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 Oct 25 01:28:21 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:21 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 Oct 25 01:28:21 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:21 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:21 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected Oct 25 01:28:21 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007d6148eb Oct 25 01:28:21 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000986c774a state to 000000007d6148eb Oct 25 01:28:21 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003a2cd35b state to 000000007d6148eb Oct 25 01:28:21 [drm:drm_atomic_check_only [drm]] checking 000000007d6148eb Oct 25 01:28:21 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:21 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:21 [drm:drm_atomic_commit [drm]] committing 000000007d6148eb Oct 25 01:28:21 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007d6148eb Oct 25 01:28:21 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007d6148eb Oct 25 01:28:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007d6148eb Oct 25 01:28:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000009ee05c94 state to 000000007d6148eb Oct 25 01:28:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000009ee05c94 Oct 25 01:28:22 [drm:drm_atomic_check_only [drm]] checking 000000007d6148eb Oct 25 01:28:22 [drm:drm_atomic_commit [drm]] committing 000000007d6148eb Oct 25 01:28:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007d6148eb Oct 25 01:28:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007d6148eb Oct 25 01:28:22 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:22 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:22 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:22 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:22 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:22 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:22 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:22 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:22 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:22 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:22 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:22 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:22 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:22 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:22 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:22 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:22 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:22 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:22 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:22 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:22 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:22 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:22 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:22 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:22 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:22 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:22 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:22 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:22 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:22 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:22 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:22 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:22 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:22 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:22 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:22 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:22 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:22 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:22 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:22 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:22 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:22 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000e506295 Oct 25 01:28:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000c64798db state to 000000000e506295 Oct 25 01:28:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000049a87919 state to 000000000e506295 Oct 25 01:28:22 [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:42:cursor A] state 00000000c64798db to [CRTC:45:pipe A] Oct 25 01:28:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000c64798db Oct 25 01:28:22 [drm:drm_atomic_check_only [drm]] checking 000000000e506295 Oct 25 01:28:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 0 -> 1, off 0, on 1, ms 0 Oct 25 01:28:22 [drm:drm_atomic_commit [drm]] committing 000000000e506295 Oct 25 01:28:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000e506295 Oct 25 01:28:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000e506295 Oct 25 01:28:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e3f0434b Oct 25 01:28:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:22 [drm:intel_backlight_device_get_brightness [i915]] get backlight PWM = 1388 Oct 25 01:28:22 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:22 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:22 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:22 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:22 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:22 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:22 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:22 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:22 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:22 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:22 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:22 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:22 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:22 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:22 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:22 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:22 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:22 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:22 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:22 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:23 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:23 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:23 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:23 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:23 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:23 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:23 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:23 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:23 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:23 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:23 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:23 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:23 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:23 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:23 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:23 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:23 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:23 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:23 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:23 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:23 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:23 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:23 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:23 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:23 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:23 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:23 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:23 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:23 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:23 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:23 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:23 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:23 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:23 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:23 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:23 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:23 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:23 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:23 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:23 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:23 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:23 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:23 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:23 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:23 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:23 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:23 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:23 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:23 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:23 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:23 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:23 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:23 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:23 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:23 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:23 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:23 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:23 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:23 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:23 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:23 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:23 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:23 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:23 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:23 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:23 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:23 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:23 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:23 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000009383b4c1 Oct 25 01:28:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:23 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:23 [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe A] Oct 25 01:28:23 [drm:drm_mode_setcrtc [drm]] [CONNECTOR:83:eDP-1] Oct 25 01:28:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001496f895 Oct 25 01:28:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008039d632 state to 000000001496f895 Oct 25 01:28:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000005005caf state to 000000001496f895 Oct 25 01:28:23 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 000000008039d632 Oct 25 01:28:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000005005caf Oct 25 01:28:23 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 000000001496f895 Oct 25 01:28:23 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000008d456176 state to 000000001496f895 Oct 25 01:28:23 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000008d456176 to [NOCRTC] Oct 25 01:28:23 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000008d456176 to [CRTC:45:pipe A] Oct 25 01:28:23 [drm:drm_atomic_check_only [drm]] checking 000000001496f895 Oct 25 01:28:23 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1] Oct 25 01:28:23 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A] Oct 25 01:28:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:23 [drm:drm_atomic_commit [drm]] committing 000000001496f895 Oct 25 01:28:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001496f895 Oct 25 01:28:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001496f895 Oct 25 01:28:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001496f895 Oct 25 01:28:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cc00d043 state to 000000001496f895 Oct 25 01:28:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d16a261d state to 000000001496f895 Oct 25 01:28:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000d16a261d Oct 25 01:28:23 [drm:drm_atomic_check_only [drm]] checking 000000001496f895 Oct 25 01:28:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:23 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001496f895 nonblocking Oct 25 01:28:23 [drm:drm_mode_setcrtc [drm]] [CRTC:63:pipe B] Oct 25 01:28:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000969433f0 Oct 25 01:28:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 00000000060a8d02 state to 00000000969433f0 Oct 25 01:28:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 000000006ce42cbb state to 00000000969433f0 Oct 25 01:28:23 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 00000000060a8d02 Oct 25 01:28:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 000000006ce42cbb Oct 25 01:28:23 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 00000000969433f0 Oct 25 01:28:23 [drm:drm_atomic_check_only [drm]] checking 00000000969433f0 Oct 25 01:28:23 [drm:drm_atomic_commit [drm]] committing 00000000969433f0 Oct 25 01:28:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000969433f0 Oct 25 01:28:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000969433f0 Oct 25 01:28:23 [drm:drm_mode_setcrtc [drm]] [CRTC:81:pipe C] Oct 25 01:28:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000969433f0 Oct 25 01:28:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 000000000f18f79d state to 00000000969433f0 Oct 25 01:28:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 000000004bccc6b6 state to 00000000969433f0 Oct 25 01:28:23 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 000000000f18f79d Oct 25 01:28:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 000000004bccc6b6 Oct 25 01:28:23 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 00000000969433f0 Oct 25 01:28:23 [drm:drm_atomic_check_only [drm]] checking 00000000969433f0 Oct 25 01:28:23 [drm:drm_atomic_commit [drm]] committing 00000000969433f0 Oct 25 01:28:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000969433f0 Oct 25 01:28:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000969433f0 Oct 25 01:28:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001496f895 Oct 25 01:28:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001496f895 Oct 25 01:28:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000006d7816fb Oct 25 01:28:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:23 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e1be4f37 Oct 25 01:28:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000add214d3 state to 00000000e1be4f37 Oct 25 01:28:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001fd78324 state to 00000000e1be4f37 Oct 25 01:28:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000001fd78324 Oct 25 01:28:23 [drm:drm_atomic_check_only [drm]] checking 00000000e1be4f37 Oct 25 01:28:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:23 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e1be4f37 nonblocking Oct 25 01:28:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e1be4f37 Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004822f60d Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d226ec8f state to 000000004822f60d Oct 25 01:28:24 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 000000004822f60d Oct 25 01:28:24 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000347cf12d state to 000000004822f60d Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000004822f60d Oct 25 01:28:24 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1] Oct 25 01:28:24 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A] Oct 25 01:28:24 [drm:drm_atomic_commit [drm]] committing 000000004822f60d Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004822f60d Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004822f60d Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000831b5c2 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000c4724bbe state to 000000000831b5c2 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000006f660ec state to 000000000831b5c2 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000006f660ec Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000000831b5c2 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000831b5c2 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000831b5c2 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000831b5c2 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007f283f5c Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000015f800ff state to 000000007f283f5c Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005876c064 state to 000000007f283f5c Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000005876c064 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000007f283f5c Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007f283f5c nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007f283f5c Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007f283f5c Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000969330de Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d6652d03 state to 00000000969330de Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000087a85c85 state to 00000000969330de Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000087a85c85 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000969330de Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000969330de nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000969330de Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000969330de Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000030f2f790 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000039db80cd state to 0000000030f2f790 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001425f82f state to 0000000030f2f790 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000001425f82f Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 0000000030f2f790 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000030f2f790 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cc00d043 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009e3b91be state to 00000000cc00d043 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000cc00d043 Oct 25 01:28:24 [drm:drm_atomic_commit [drm]] committing 00000000cc00d043 Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000030f2f790 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000030f2f790 Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cc00d043 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cc00d043 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cc00d043 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000844a48c state to 00000000cc00d043 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009383b4c1 state to 00000000cc00d043 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000009383b4c1 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000cc00d043 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cc00d043 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cc00d043 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cc00d043 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003e63e638 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e8c0f353 state to 000000003e63e638 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000986c774a state to 000000003e63e638 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000986c774a Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000003e63e638 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003e63e638 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003e63e638 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003e63e638 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a200fb25 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000aafb4eb1 state to 00000000a200fb25 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000879a9656 state to 00000000a200fb25 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000879a9656 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000a200fb25 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a200fb25 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a200fb25 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a200fb25 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000a7a25c7 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a200fb25 state to 000000000a7a25c7 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001e400fd3 state to 000000000a7a25c7 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000001e400fd3 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000000a7a25c7 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000a7a25c7 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000a7a25c7 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000a7a25c7 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e8c0f353 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003e63e638 state to 00000000e8c0f353 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000058731de5 state to 00000000e8c0f353 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000058731de5 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000e8c0f353 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e8c0f353 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e8c0f353 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e8c0f353 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000844a48c Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cc00d043 state to 000000000844a48c Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000631131f6 state to 000000000844a48c Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000631131f6 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000000844a48c Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000844a48c nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000844a48c Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000844a48c Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e3b91be Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001496f895 state to 000000009e3b91be Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000011578b22 state to 000000009e3b91be Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000011578b22 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000009e3b91be Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e3b91be nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e3b91be Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e3b91be Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008039d632 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000331ddb82 state to 000000008039d632 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000074c36f87 state to 000000008039d632 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000074c36f87 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000008039d632 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008039d632 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008039d632 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008039d632 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000869f565a Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008039d632 state to 00000000869f565a Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000000a16ea6 state to 00000000869f565a Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000000a16ea6 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000869f565a Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000869f565a nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000869f565a Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000869f565a Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001496f895 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009e3b91be state to 000000001496f895 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000058b402ee state to 000000001496f895 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000058b402ee Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000001496f895 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001496f895 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001496f895 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001496f895 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cc00d043 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000844a48c state to 00000000cc00d043 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c25455d0 state to 00000000cc00d043 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000c25455d0 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000cc00d043 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cc00d043 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cc00d043 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cc00d043 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003e63e638 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e8c0f353 state to 000000003e63e638 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001703c641 state to 000000003e63e638 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000001703c641 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000003e63e638 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003e63e638 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003e63e638 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003e63e638 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a200fb25 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a7a25c7 state to 00000000a200fb25 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008e96a6f3 state to 00000000a200fb25 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000008e96a6f3 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000a200fb25 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a200fb25 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a200fb25 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a200fb25 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000aafb4eb1 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a200fb25 state to 00000000aafb4eb1 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006b0affef state to 00000000aafb4eb1 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000006b0affef Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000aafb4eb1 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000aafb4eb1 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000aafb4eb1 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000aafb4eb1 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e8c0f353 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003e63e638 state to 00000000e8c0f353 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008e96a6f3 state to 00000000e8c0f353 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000008e96a6f3 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000e8c0f353 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e8c0f353 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e8c0f353 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e8c0f353 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000844a48c Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cc00d043 state to 000000000844a48c Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001703c641 state to 000000000844a48c Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000001703c641 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000000844a48c Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000844a48c nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000844a48c Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000844a48c Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e3b91be Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001496f895 state to 000000009e3b91be Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c25455d0 state to 000000009e3b91be Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000c25455d0 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000009e3b91be Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e3b91be nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e3b91be Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e3b91be Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008039d632 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000869f565a state to 000000008039d632 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000058b402ee state to 000000008039d632 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000058b402ee Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000008039d632 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008039d632 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008039d632 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008039d632 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000331ddb82 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008039d632 state to 00000000331ddb82 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000000a16ea6 state to 00000000331ddb82 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000000a16ea6 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000331ddb82 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000331ddb82 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000331ddb82 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000331ddb82 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001496f895 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009e3b91be state to 000000001496f895 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000074c36f87 state to 000000001496f895 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000074c36f87 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000001496f895 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001496f895 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001496f895 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001496f895 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cc00d043 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000844a48c state to 00000000cc00d043 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000011578b22 state to 00000000cc00d043 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000011578b22 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000cc00d043 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cc00d043 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cc00d043 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cc00d043 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003e63e638 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e8c0f353 state to 000000003e63e638 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000631131f6 state to 000000003e63e638 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000631131f6 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000003e63e638 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003e63e638 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003e63e638 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003e63e638 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a200fb25 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000aafb4eb1 state to 00000000a200fb25 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000058731de5 state to 00000000a200fb25 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000058731de5 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000a200fb25 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a200fb25 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a200fb25 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a200fb25 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000a7a25c7 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a200fb25 state to 000000000a7a25c7 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fd5cd84c state to 000000000a7a25c7 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000fd5cd84c Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000000a7a25c7 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000a7a25c7 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000a7a25c7 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000a7a25c7 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e8c0f353 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003e63e638 state to 00000000e8c0f353 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000011578b22 state to 00000000e8c0f353 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000011578b22 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000e8c0f353 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e8c0f353 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e8c0f353 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e8c0f353 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000844a48c Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cc00d043 state to 000000000844a48c Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000074c36f87 state to 000000000844a48c Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000074c36f87 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000000844a48c Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000844a48c nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000844a48c Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000844a48c Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000c12c90dd Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e3b91be Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001496f895 state to 000000009e3b91be Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a55c03f5 state to 000000009e3b91be Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000a55c03f5 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000009e3b91be Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e3b91be nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e3b91be Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e3b91be Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008039d632 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000331ddb82 state to 000000008039d632 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000da464299 state to 000000008039d632 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000da464299 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000008039d632 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008039d632 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008039d632 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008039d632 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000039db80cd Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000030f2f790 state to 0000000039db80cd Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d04b0146 state to 0000000039db80cd Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000d04b0146 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 0000000039db80cd Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000039db80cd nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000039db80cd Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000039db80cd Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d6652d03 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000969330de state to 00000000d6652d03 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003100757a state to 00000000d6652d03 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000003100757a Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000d6652d03 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d6652d03 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d6652d03 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d6652d03 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000039db80cd Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d6652d03 state to 0000000039db80cd Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e8232e79 state to 0000000039db80cd Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000e8232e79 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 0000000039db80cd Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000039db80cd nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000039db80cd Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000039db80cd Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000030f2f790 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000039db80cd state to 0000000030f2f790 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000357240d2 state to 0000000030f2f790 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000357240d2 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 0000000030f2f790 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000030f2f790 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000030f2f790 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000030f2f790 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000969330de Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000030f2f790 state to 00000000969330de Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e8232e79 state to 00000000969330de Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000e8232e79 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000969330de Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000969330de nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000969330de Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000969330de Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d6652d03 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000969330de state to 00000000d6652d03 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000524b7257 state to 00000000d6652d03 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000524b7257 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000d6652d03 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d6652d03 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d6652d03 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d6652d03 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007785f0f0 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005786b141 state to 000000007785f0f0 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e1916ad8 state to 000000007785f0f0 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000e1916ad8 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000007785f0f0 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007785f0f0 nonblocking Oct 25 01:28:24 IPv6: ADDRCONF(NETDEV_UP): wlp0s20f0u5: link is not ready Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007785f0f0 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007785f0f0 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000bd86b03a Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000007785f0f0 state to 00000000bd86b03a Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000cc3c10ef state to 00000000bd86b03a Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000cc3c10ef Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000bd86b03a Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000bd86b03a nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000bd86b03a Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000bd86b03a Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005af30ff1 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000c0ee9fbb state to 000000005af30ff1 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000562d91c1 state to 000000005af30ff1 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000562d91c1 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 000000005af30ff1 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005af30ff1 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005af30ff1 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005af30ff1 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ddb176f8 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000058df4893 state to 00000000ddb176f8 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000cb1be5e state to 00000000ddb176f8 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000000cb1be5e Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000ddb176f8 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ddb176f8 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ddb176f8 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ddb176f8 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000008277b78 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e1be4f37 state to 0000000008277b78 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000204aa780 state to 0000000008277b78 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000204aa780 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 0000000008277b78 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000008277b78 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000add214d3 Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000008277b78 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000008277b78 Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000add214d3 Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000add214d3 Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000add214d3 Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000add214d3 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000add214d3 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000add214d3 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000004822f60d state to 00000000add214d3 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000adaf73d state to 00000000add214d3 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000000adaf73d Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000add214d3 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000add214d3 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d226ec8f Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000add214d3 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000add214d3 Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d226ec8f Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d226ec8f Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d226ec8f Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d226ec8f Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d226ec8f Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d226ec8f Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000add214d3 state to 00000000d226ec8f Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a39bfbd3 state to 00000000d226ec8f Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000a39bfbd3 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000d226ec8f Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d226ec8f nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e1be4f37 Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d226ec8f Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d226ec8f Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e1be4f37 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e1be4f37 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000008277b78 state to 00000000e1be4f37 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001c46f2f5 state to 00000000e1be4f37 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000001c46f2f5 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000e1be4f37 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e1be4f37 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000058df4893 Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e1be4f37 Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000058df4893 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000058df4893 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000058df4893 Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ddb176f8 state to 0000000058df4893 Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000025023314 state to 0000000058df4893 Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000025023314 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 0000000058df4893 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000058df4893 nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000058df4893 Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000058df4893 Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c0ee9fbb Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005af30ff1 state to 00000000c0ee9fbb Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001c46f2f5 state to 00000000c0ee9fbb Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000001c46f2f5 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000c0ee9fbb Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c0ee9fbb nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c0ee9fbb Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c0ee9fbb Oct 25 01:28:24 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c0ee9fbb Oct 25 01:28:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ddb176f8 state to 00000000c0ee9fbb Oct 25 01:28:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a39bfbd3 state to 00000000c0ee9fbb Oct 25 01:28:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000a39bfbd3 Oct 25 01:28:24 [drm:drm_atomic_check_only [drm]] checking 00000000c0ee9fbb Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c0ee9fbb nonblocking Oct 25 01:28:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c0ee9fbb Oct 25 01:28:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c0ee9fbb Oct 25 01:28:25 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000058df4893 Oct 25 01:28:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000008277b78 state to 0000000058df4893 Oct 25 01:28:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000adaf73d state to 0000000058df4893 Oct 25 01:28:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000000adaf73d Oct 25 01:28:25 [drm:drm_atomic_check_only [drm]] checking 0000000058df4893 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000058df4893 nonblocking Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000058df4893 Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000058df4893 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000add214d3 state to 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000204aa780 state to 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000204aa780 Oct 25 01:28:25 [drm:drm_atomic_check_only [drm]] checking 00000000e1be4f37 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e1be4f37 nonblocking Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d226ec8f Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d226ec8f Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d226ec8f Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d226ec8f Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d226ec8f Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d226ec8f Oct 25 01:28:25 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d226ec8f Oct 25 01:28:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000004822f60d state to 00000000d226ec8f Oct 25 01:28:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000cb1be5e state to 00000000d226ec8f Oct 25 01:28:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000000cb1be5e Oct 25 01:28:25 [drm:drm_atomic_check_only [drm]] checking 00000000d226ec8f Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d226ec8f nonblocking Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d226ec8f Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d226ec8f Oct 25 01:28:25 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d226ec8f Oct 25 01:28:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000add214d3 state to 00000000d226ec8f Oct 25 01:28:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000204aa780 state to 00000000d226ec8f Oct 25 01:28:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000204aa780 Oct 25 01:28:25 [drm:drm_atomic_check_only [drm]] checking 00000000d226ec8f Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d226ec8f nonblocking Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d226ec8f Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d226ec8f Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000008277b78 state to 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000adaf73d state to 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000000adaf73d Oct 25 01:28:25 [drm:drm_atomic_check_only [drm]] checking 00000000e1be4f37 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e1be4f37 nonblocking Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d6652d03 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d6652d03 Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d6652d03 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d6652d03 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d6652d03 Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d6652d03 Oct 25 01:28:25 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000058df4893 Oct 25 01:28:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ddb176f8 state to 0000000058df4893 Oct 25 01:28:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d9e31013 state to 0000000058df4893 Oct 25 01:28:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000d9e31013 Oct 25 01:28:25 [drm:drm_atomic_check_only [drm]] checking 0000000058df4893 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000058df4893 nonblocking Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c0ee9fbb Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000058df4893 Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000058df4893 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c0ee9fbb Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c0ee9fbb Oct 25 01:28:25 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c0ee9fbb Oct 25 01:28:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005af30ff1 state to 00000000c0ee9fbb Oct 25 01:28:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000009960203 state to 00000000c0ee9fbb Oct 25 01:28:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000009960203 Oct 25 01:28:25 [drm:drm_atomic_check_only [drm]] checking 00000000c0ee9fbb Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c0ee9fbb nonblocking Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c0ee9fbb Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c0ee9fbb Oct 25 01:28:25 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c0ee9fbb Oct 25 01:28:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ddb176f8 state to 00000000c0ee9fbb Oct 25 01:28:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ea83e0fd state to 00000000c0ee9fbb Oct 25 01:28:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000ea83e0fd Oct 25 01:28:25 [drm:drm_atomic_check_only [drm]] checking 00000000c0ee9fbb Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c0ee9fbb nonblocking Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c0ee9fbb Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c0ee9fbb Oct 25 01:28:25 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000058df4893 Oct 25 01:28:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000008277b78 state to 0000000058df4893 Oct 25 01:28:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001fd78324 state to 0000000058df4893 Oct 25 01:28:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000001fd78324 Oct 25 01:28:25 [drm:drm_atomic_check_only [drm]] checking 0000000058df4893 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000058df4893 nonblocking Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000058df4893 Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000058df4893 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e1be4f37 Oct 25 01:28:25 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:25 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:25 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:25 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:25 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:25 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:25 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:25 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:25 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:25 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:25 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:25 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:25 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:25 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:25 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:25 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:25 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:25 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:25 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:25 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:25 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:25 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:25 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:25 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:25 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:25 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:25 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:25 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:25 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:25 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:25 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:25 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:25 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:25 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:25 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:25 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:25 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:25 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:25 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:25 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:25 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:25 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:25 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:25 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:25 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:25 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:25 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:25 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:25 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:25 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:25 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:25 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:25 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:25 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:25 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:25 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:25 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:25 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:25 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:25 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:25 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:25 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:25 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:25 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000add214d3 Oct 25 01:28:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000058df4893 state to 00000000add214d3 Oct 25 01:28:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000562d91c1 state to 00000000add214d3 Oct 25 01:28:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000562d91c1 Oct 25 01:28:25 [drm:drm_atomic_check_only [drm]] checking 00000000add214d3 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000add214d3 nonblocking Oct 25 01:28:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000add214d3 Oct 25 01:28:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000add214d3 Oct 25 01:28:26 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:26 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:26 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:26 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:26 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:26 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:26 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:26 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:26 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:26 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:26 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:26 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:26 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:26 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:26 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:26 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:26 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:26 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:26 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:26 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:26 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e1be4f37 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d226ec8f state to 00000000e1be4f37 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000f118b63 state to 00000000e1be4f37 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000000f118b63 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 00000000e1be4f37 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e1be4f37 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1be4f37 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e1be4f37 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004822f60d Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ddb176f8 state to 000000004822f60d Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a39bfbd3 state to 000000004822f60d Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000a39bfbd3 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 000000004822f60d Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004822f60d nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004822f60d Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004822f60d Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c0ee9fbb Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005af30ff1 state to 00000000c0ee9fbb Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000feac5093 state to 00000000c0ee9fbb Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000feac5093 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 00000000c0ee9fbb Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c0ee9fbb nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c0ee9fbb Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000bd86b03a Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000bd86b03a Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c0ee9fbb Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000bd86b03a Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f41115d1 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000059d5e964 state to 00000000f41115d1 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000084a4656d state to 00000000f41115d1 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000084a4656d Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 00000000f41115d1 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f41115d1 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f41115d1 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f41115d1 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000039a1beeb Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f41115d1 state to 0000000039a1beeb Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000a1c27a5 state to 0000000039a1beeb Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000000a1c27a5 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 0000000039a1beeb Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000039a1beeb nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000087db4dc8 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000087db4dc8 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000087db4dc8 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000087db4dc8 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000087db4dc8 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000087db4dc8 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000039a1beeb Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000039a1beeb Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000087db4dc8 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000aba455a0 state to 0000000087db4dc8 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f15aa86f state to 0000000087db4dc8 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000f15aa86f Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 0000000087db4dc8 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000087db4dc8 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000087db4dc8 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000087db4dc8 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cc7825d5 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000905507a8 state to 00000000cc7825d5 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000006bc7435 state to 00000000cc7825d5 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000006bc7435 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 00000000cc7825d5 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cc7825d5 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cc7825d5 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cc7825d5 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000058462696 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000097d17608 state to 0000000058462696 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000da40cb10 state to 0000000058462696 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000da40cb10 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 0000000058462696 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000058462696 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002ae9f59 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002ae9f59 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002ae9f59 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002ae9f59 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002ae9f59 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002ae9f59 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000058462696 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002ae9f59 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a659d339 state to 0000000002ae9f59 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000087263725 state to 0000000002ae9f59 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000087263725 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 0000000002ae9f59 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000058462696 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000002ae9f59 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000790ff029 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000790ff029 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000790ff029 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000790ff029 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000790ff029 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000790ff029 Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002ae9f59 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002ae9f59 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000790ff029 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005745e7f0 state to 00000000790ff029 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003a335607 state to 00000000790ff029 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000003a335607 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 00000000790ff029 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000790ff029 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000790ff029 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000790ff029 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005a65e16b Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000790ff029 state to 000000005a65e16b Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f15aa86f state to 000000005a65e16b Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000f15aa86f Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 000000005a65e16b Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005a65e16b nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005a65e16b Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005a65e16b Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a659d339 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000002ae9f59 state to 00000000a659d339 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000a1c27a5 state to 00000000a659d339 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000000a1c27a5 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 00000000a659d339 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a659d339 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a659d339 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a659d339 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000097d17608 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000058462696 state to 0000000097d17608 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000084a4656d state to 0000000097d17608 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000084a4656d Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 0000000097d17608 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000097d17608 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000097d17608 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000097d17608 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000905507a8 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cc7825d5 state to 00000000905507a8 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000194cacd state to 00000000905507a8 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000000194cacd Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 00000000905507a8 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000905507a8 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000905507a8 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000905507a8 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000aba455a0 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000087db4dc8 state to 00000000aba455a0 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000053770765 state to 00000000aba455a0 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000053770765 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 00000000aba455a0 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000aba455a0 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000aba455a0 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000aba455a0 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f41115d1 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000039a1beeb state to 00000000f41115d1 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ca2851d8 state to 00000000f41115d1 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000ca2851d8 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 00000000f41115d1 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f41115d1 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f41115d1 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f41115d1 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059d5e964 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f41115d1 state to 0000000059d5e964 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f4bdc852 state to 0000000059d5e964 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000f4bdc852 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 0000000059d5e964 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000059d5e964 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059d5e964 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059d5e964 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000087db4dc8 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000aba455a0 state to 0000000087db4dc8 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ef59cc08 state to 0000000087db4dc8 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000ef59cc08 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 0000000087db4dc8 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000087db4dc8 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000087db4dc8 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000087db4dc8 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cc7825d5 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000905507a8 state to 00000000cc7825d5 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000014532b6e state to 00000000cc7825d5 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000014532b6e Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 00000000cc7825d5 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cc7825d5 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cc7825d5 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cc7825d5 Oct 25 01:28:26 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000058462696 Oct 25 01:28:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000097d17608 state to 0000000058462696 Oct 25 01:28:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000007ade698 state to 0000000058462696 Oct 25 01:28:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000007ade698 Oct 25 01:28:26 [drm:drm_atomic_check_only [drm]] checking 0000000058462696 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000058462696 nonblocking Oct 25 01:28:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000058462696 Oct 25 01:28:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000058462696 Oct 25 01:28:26 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:26 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:26 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:26 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:26 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:26 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:26 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:26 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:26 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:26 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:26 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:26 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:26 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:26 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:26 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:26 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:26 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:26 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:26 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:26 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:27 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:27 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:27 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:27 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:27 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:27 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:27 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:27 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:27 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:27 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:27 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:27 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:27 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:27 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:27 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:27 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:27 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:27 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:27 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:27 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:27 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:27 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:27 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002ae9f59 Oct 25 01:28:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a659d339 state to 0000000002ae9f59 Oct 25 01:28:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008c57034d state to 0000000002ae9f59 Oct 25 01:28:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000008c57034d Oct 25 01:28:27 [drm:drm_atomic_check_only [drm]] checking 0000000002ae9f59 Oct 25 01:28:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000002ae9f59 nonblocking Oct 25 01:28:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002ae9f59 Oct 25 01:28:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002ae9f59 Oct 25 01:28:27 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:27 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:27 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:27 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:27 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:27 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:27 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:27 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:27 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:27 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:27 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:27 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:27 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:27 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:27 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:27 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:27 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:27 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:27 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:27 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:27 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:27 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000790ff029 Oct 25 01:28:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005a65e16b state to 00000000790ff029 Oct 25 01:28:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000522df7a0 state to 00000000790ff029 Oct 25 01:28:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000522df7a0 Oct 25 01:28:27 [drm:drm_atomic_check_only [drm]] checking 00000000790ff029 Oct 25 01:28:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000790ff029 nonblocking Oct 25 01:28:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000790ff029 Oct 25 01:28:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000790ff029 Oct 25 01:28:27 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:27 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:27 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:27 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:27 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:27 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:27 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:27 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:27 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:27 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:27 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:27 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:27 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:27 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:27 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:27 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:27 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:27 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:27 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:27 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:27 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:27 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005745e7f0 Oct 25 01:28:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000790ff029 state to 000000005745e7f0 Oct 25 01:28:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000069099f8d state to 000000005745e7f0 Oct 25 01:28:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000069099f8d Oct 25 01:28:27 [drm:drm_atomic_check_only [drm]] checking 000000005745e7f0 Oct 25 01:28:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005745e7f0 nonblocking Oct 25 01:28:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005745e7f0 Oct 25 01:28:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005745e7f0 Oct 25 01:28:28 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:28 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a659d339 Oct 25 01:28:28 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000002ae9f59 state to 00000000a659d339 Oct 25 01:28:28 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000091594e1c state to 00000000a659d339 Oct 25 01:28:28 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000091594e1c Oct 25 01:28:28 [drm:drm_atomic_check_only [drm]] checking 00000000a659d339 Oct 25 01:28:28 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:28 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:28 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a659d339 nonblocking Oct 25 01:28:28 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a659d339 Oct 25 01:28:28 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a659d339 Oct 25 01:28:28 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:28 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000097d17608 Oct 25 01:28:28 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000058462696 state to 0000000097d17608 Oct 25 01:28:28 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000076f8a74b state to 0000000097d17608 Oct 25 01:28:28 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000076f8a74b Oct 25 01:28:28 [drm:drm_atomic_check_only [drm]] checking 0000000097d17608 Oct 25 01:28:28 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:28 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:28 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000097d17608 nonblocking Oct 25 01:28:28 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000097d17608 Oct 25 01:28:28 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000097d17608 Oct 25 01:28:28 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:28 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000905507a8 Oct 25 01:28:28 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cc7825d5 state to 00000000905507a8 Oct 25 01:28:28 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000091594e1c state to 00000000905507a8 Oct 25 01:28:28 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000091594e1c Oct 25 01:28:28 [drm:drm_atomic_check_only [drm]] checking 00000000905507a8 Oct 25 01:28:28 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:28 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:28 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000905507a8 nonblocking Oct 25 01:28:28 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000905507a8 Oct 25 01:28:28 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000905507a8 Oct 25 01:28:28 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:28 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000aba455a0 Oct 25 01:28:28 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000087db4dc8 state to 00000000aba455a0 Oct 25 01:28:28 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000087263725 state to 00000000aba455a0 Oct 25 01:28:28 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000087263725 Oct 25 01:28:28 [drm:drm_atomic_check_only [drm]] checking 00000000aba455a0 Oct 25 01:28:28 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:28 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:28 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000aba455a0 nonblocking Oct 25 01:28:28 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000aba455a0 Oct 25 01:28:28 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000aba455a0 Oct 25 01:28:28 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:28 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f41115d1 Oct 25 01:28:28 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000059d5e964 state to 00000000f41115d1 Oct 25 01:28:28 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003a335607 state to 00000000f41115d1 Oct 25 01:28:28 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000003a335607 Oct 25 01:28:28 [drm:drm_atomic_check_only [drm]] checking 00000000f41115d1 Oct 25 01:28:28 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:28 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:28 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f41115d1 nonblocking Oct 25 01:28:28 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f41115d1 Oct 25 01:28:28 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f41115d1 Oct 25 01:28:28 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:28 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:28 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:28 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:28 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:28 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:28 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:28 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:28 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:28 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:28 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:28 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:28 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:28 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:28 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:28 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:28 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:28 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:28 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:28 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:28 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:28 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:28 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000039a1beeb Oct 25 01:28:28 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f41115d1 state to 0000000039a1beeb Oct 25 01:28:28 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f15aa86f state to 0000000039a1beeb Oct 25 01:28:28 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000f15aa86f Oct 25 01:28:28 [drm:drm_atomic_check_only [drm]] checking 0000000039a1beeb Oct 25 01:28:28 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:28 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:28 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000039a1beeb nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000039a1beeb Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000039a1beeb Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000087db4dc8 Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000aba455a0 state to 0000000087db4dc8 Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000a1c27a5 state to 0000000087db4dc8 Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000000a1c27a5 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 0000000087db4dc8 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000087db4dc8 nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000087db4dc8 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000087db4dc8 Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e3b91be Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001496f895 state to 000000009e3b91be Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009bec1484 state to 000000009e3b91be Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000009bec1484 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 000000009e3b91be Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e3b91be nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e3b91be Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e3b91be Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cc00d043 Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000844a48c state to 00000000cc00d043 Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000074c36f87 state to 00000000cc00d043 Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000074c36f87 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 00000000cc00d043 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cc00d043 nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cc00d043 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cc00d043 Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003e63e638 Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e8c0f353 state to 000000003e63e638 Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000acfbe4c3 state to 000000003e63e638 Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000acfbe4c3 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 000000003e63e638 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003e63e638 nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a200fb25 Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a200fb25 Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a200fb25 Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a200fb25 Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a200fb25 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a200fb25 Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003e63e638 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003e63e638 Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a200fb25 Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a7a25c7 state to 00000000a200fb25 Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006bbfe699 state to 00000000a200fb25 Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000006bbfe699 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 00000000a200fb25 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a200fb25 nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a200fb25 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a200fb25 Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000aafb4eb1 Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a200fb25 state to 00000000aafb4eb1 Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e0ecd51a state to 00000000aafb4eb1 Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000e0ecd51a Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 00000000aafb4eb1 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000aafb4eb1 nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000aafb4eb1 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000aafb4eb1 Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e8c0f353 Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003e63e638 state to 00000000e8c0f353 Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009bec1484 state to 00000000e8c0f353 Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000009bec1484 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 00000000e8c0f353 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e8c0f353 nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e8c0f353 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e8c0f353 Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000844a48c Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cc00d043 state to 000000000844a48c Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000000a16ea6 state to 000000000844a48c Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000000a16ea6 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 000000000844a48c Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000844a48c nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000844a48c Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000844a48c Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001496f895 Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009e3b91be state to 000000001496f895 Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009bec1484 state to 000000001496f895 Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000009bec1484 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 000000001496f895 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001496f895 nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001496f895 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001496f895 Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008039d632 Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001496f895 state to 000000008039d632 Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e0ecd51a state to 000000008039d632 Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000e0ecd51a Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 000000008039d632 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008039d632 nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008039d632 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008039d632 Oct 25 01:28:29 IPv6: ADDRCONF(NETDEV_CHANGE): wlp0s20f0u5: link becomes ready Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cc00d043 Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000844a48c state to 00000000cc00d043 Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006bbfe699 state to 00000000cc00d043 Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000006bbfe699 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 00000000cc00d043 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cc00d043 nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cc00d043 Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005af30ff1 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cc00d043 Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005af30ff1 Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005af30ff1 Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005af30ff1 Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005af30ff1 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005af30ff1 Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000482bd66e Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006b40674c state to 00000000482bd66e Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005876c064 state to 00000000482bd66e Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000005876c064 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 00000000482bd66e Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000482bd66e nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000482bd66e Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000482bd66e Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000231b9af0 Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000482bd66e state to 00000000231b9af0 Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000024f78125 state to 00000000231b9af0 Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000024f78125 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 00000000231b9af0 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000231b9af0 nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000231b9af0 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000231b9af0 Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000231b9af0 Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006b40674c state to 00000000231b9af0 Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000aa540bd0 state to 00000000231b9af0 Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000aa540bd0 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 00000000231b9af0 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000231b9af0 nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000231b9af0 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000231b9af0 Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000231b9af0 Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000482bd66e state to 00000000231b9af0 Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000acca50a0 state to 00000000231b9af0 Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000acca50a0 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 00000000231b9af0 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000231b9af0 nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000231b9af0 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000231b9af0 Oct 25 01:28:29 [drm:drm_mode_addfb2 [drm]] [FB:112] Oct 25 01:28:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000231b9af0 Oct 25 01:28:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006b40674c state to 00000000231b9af0 Oct 25 01:28:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000d82a708 state to 00000000231b9af0 Oct 25 01:28:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000000d82a708 Oct 25 01:28:29 [drm:drm_atomic_check_only [drm]] checking 00000000231b9af0 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000231b9af0 nonblocking Oct 25 01:28:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000231b9af0 Oct 25 01:28:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000231b9af0 Oct 25 01:28:29 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:29 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:29 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:29 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:29 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:29 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:29 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:29 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:29 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:29 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:29 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:29 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:29 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:29 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:29 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:29 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:29 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:29 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:29 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:29 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:29 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:29 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] Oct 25 01:28:29 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:29 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:29 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:29 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:29 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:29 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:29 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:29 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Oct 25 01:28:29 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:29 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes : Oct 25 01:28:29 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9 Oct 25 01:28:29 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] Oct 25 01:28:29 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1] Oct 25 01:28:29 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:29 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:29 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected Oct 25 01:28:29 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:29 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:29 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:29 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:29 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:29 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 Oct 25 01:28:29 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:29 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 Oct 25 01:28:29 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:29 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:29 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected Oct 25 01:28:29 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] Oct 25 01:28:29 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2] Oct 25 01:28:29 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:29 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:29 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected Oct 25 01:28:29 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:29 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:29 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:29 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:29 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:29 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:29 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:29 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:29 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 Oct 25 01:28:29 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:29 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:29 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 Oct 25 01:28:29 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:29 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:29 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected Oct 25 01:28:29 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:29 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:29 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:29 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:29 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:29 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:29 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:29 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:29 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:29 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:29 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:29 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:29 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:29 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:29 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:29 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:30 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:30 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] Oct 25 01:28:30 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:30 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:30 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:30 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:30 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:30 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:30 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:30 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found Oct 25 01:28:30 [drm:drm_add_display_info [drm]] non_desktop set to 0 Oct 25 01:28:30 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes : Oct 25 01:28:30 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9 Oct 25 01:28:30 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] Oct 25 01:28:30 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1] Oct 25 01:28:30 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:30 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:30 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected Oct 25 01:28:30 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:30 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1] Oct 25 01:28:30 fuse init (API version 7.27) Oct 25 01:28:30 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:30 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:30 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:30 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 Oct 25 01:28:30 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc Oct 25 01:28:30 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 Oct 25 01:28:30 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:30 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:30 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:30 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:30 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4 Oct 25 01:28:30 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:30 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected Oct 25 01:28:30 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:30 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:30 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:30 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:30 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:30 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:30 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:30 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:30 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:30 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:30 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:30 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:30 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:30 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:30 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:30 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:30 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:30 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] Oct 25 01:28:30 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2] Oct 25 01:28:30 [drm:intel_power_well_enable [i915]] enabling power well 2 Oct 25 01:28:30 [drm:intel_power_well_disable [i915]] disabling power well 2 Oct 25 01:28:30 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected Oct 25 01:28:30 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:30 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2] Oct 25 01:28:30 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:30 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:30 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging Oct 25 01:28:30 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 Oct 25 01:28:30 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd Oct 25 01:28:30 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 Oct 25 01:28:30 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 Oct 25 01:28:30 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) Oct 25 01:28:30 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected Oct 25 01:28:30 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000814a99fc Oct 25 01:28:30 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003250c036 state to 00000000814a99fc Oct 25 01:28:30 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a8f99ed2 state to 00000000814a99fc Oct 25 01:28:30 [drm:drm_atomic_check_only [drm]] checking 00000000814a99fc Oct 25 01:28:30 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112 Oct 25 01:28:30 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:30 [drm:drm_atomic_commit [drm]] committing 00000000814a99fc Oct 25 01:28:30 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000814a99fc Oct 25 01:28:30 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000814a99fc Oct 25 01:28:30 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006534c18e Oct 25 01:28:30 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000c469c9c4 state to 000000006534c18e Oct 25 01:28:30 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000072af666f state to 000000006534c18e Oct 25 01:28:30 [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:42:cursor A] state 00000000c469c9c4 to [NOCRTC] Oct 25 01:28:30 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000c469c9c4 Oct 25 01:28:30 [drm:drm_atomic_check_only [drm]] checking 000000006534c18e Oct 25 01:28:30 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb -1 Oct 25 01:28:30 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 0, off 1, on 0, ms 0 Oct 25 01:28:30 [drm:drm_atomic_commit [drm]] committing 000000006534c18e Oct 25 01:28:30 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006534c18e Oct 25 01:28:30 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006534c18e Oct 25 01:28:30 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:30 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:30 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:30 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:30 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:30 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:30 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:30 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:30 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:30 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:30 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:30 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:30 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:30 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:30 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:30 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:30 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:30 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:30 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:30 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:30 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:30 Bluetooth: RFCOMM TTY layer initialized Oct 25 01:28:30 Bluetooth: RFCOMM socket layer initialized Oct 25 01:28:30 Bluetooth: RFCOMM ver 1.11 Oct 25 01:28:30 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a659d339 Oct 25 01:28:30 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 0000000036e246a1 state to 00000000a659d339 Oct 25 01:28:30 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000790ff029 state to 00000000a659d339 Oct 25 01:28:30 [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:42:cursor A] state 0000000036e246a1 to [CRTC:45:pipe A] Oct 25 01:28:30 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000036e246a1 Oct 25 01:28:30 [drm:drm_atomic_check_only [drm]] checking 00000000a659d339 Oct 25 01:28:30 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:30 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 0 -> 1, off 0, on 1, ms 0 Oct 25 01:28:30 [drm:drm_atomic_commit [drm]] committing 00000000a659d339 Oct 25 01:28:30 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a659d339 Oct 25 01:28:30 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a659d339 Oct 25 01:28:30 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000f4bdc852 Oct 25 01:28:30 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:30 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:30 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:30 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:30 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:30 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:30 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:30 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:30 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:30 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:30 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:30 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:30 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:30 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:30 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:30 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:30 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:30 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:30 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:30 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:30 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:30 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:31 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:31 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:31 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:31 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:31 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:31 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:31 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:31 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:31 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:31 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:31 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:31 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:31 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:31 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:31 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:31 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:31 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:31 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:31 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:31 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:31 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:31 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:31 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:31 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:31 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:31 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:31 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:31 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:31 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:31 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:31 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:31 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:31 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:31 rfkill: input handler disabled Oct 25 01:28:31 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:31 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:31 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:31 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:31 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:31 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:31 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:31 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:31 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:31 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:31 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:31 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:31 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:31 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:31 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:31 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:31 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:31 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:31 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:31 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:31 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:31 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:31 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:31 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:31 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:31 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000cd96d5ee Oct 25 01:28:31 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:31 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:31 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:31 [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe A] Oct 25 01:28:31 [drm:drm_mode_setcrtc [drm]] [CONNECTOR:83:eDP-1] Oct 25 01:28:31 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003f7f2dbc state to 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d70d5e08 state to 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200_60.00] for [CRTC:45:pipe A] state 000000003f7f2dbc Oct 25 01:28:31 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000d70d5e08 Oct 25 01:28:31 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 0000000043fa1ba1 state to 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 0000000043fa1ba1 to [NOCRTC] Oct 25 01:28:31 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 0000000043fa1ba1 to [CRTC:45:pipe A] Oct 25 01:28:31 [drm:drm_atomic_check_only [drm]] checking 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:45:pipe A] mode changed Oct 25 01:28:31 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1] Oct 25 01:28:31 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A] Oct 25 01:28:31 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:45:pipe A] needs all connectors, enable: y, active: y Oct 25 01:28:31 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:45:pipe A] to 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000d2b1eb81 state to 000000003bd68fe3 Oct 25 01:28:31 [drm:intel_atomic_check [i915]] [CONNECTOR:83:eDP-1] checking for sink bpp constrains Oct 25 01:28:31 [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30 Oct 25 01:28:31 [drm:skl_update_scaler [i915]] scaler_user index 0.31: staged scaling request for 1920x1200->2880x1800 scaler_users = 0x80000000 Oct 25 01:28:31 [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 270000 max bpp 30 pixel clock 328920KHz Oct 25 01:28:31 [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 270000 bpp 24 Oct 25 01:28:31 [drm:intel_dp_compute_config [i915]] DP link rate required 986760 available 1080000 Oct 25 01:28:31 [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe A][fastset] Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100) Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] output format: RGB Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 7664391, gmch_n: 8388608, link_m: 638699, link_n: 524288, tu: 64 Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] requested mode: Oct 25 01:28:31 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200_60.00" 0 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6 Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] adjusted mode: Oct 25 01:28:31 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9 Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] crtc timings: 328920 2880 2888 2920 2960 1800 1838 1846 1852, type: 0x48 flags: 0x9 Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1200, pixel rate 328920 Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: -1 Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x0b400708, enabled Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0 Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] planes on this crtc Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:112, fb = 2880x1800 format = XR24 little-endian (0x34325258) Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+2880+1800 dst 0x0+2880+1800 Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2A] disabled, scaler_id = -1 Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] [PLANE:42:cursor A] FB:110, fb = 256x256 format = AR24 little-endian (0x34325241) Oct 25 01:28:31 [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+256+256 dst 1724x1076+256+256 Oct 25 01:28:31 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:31 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:31 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:31 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:31 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:31 [drm:drm_atomic_commit [drm]] committing 000000003bd68fe3 Oct 25 01:28:31 [drm:verify_connector_state.isra.132 [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:31 [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe A] Oct 25 01:28:31 [drm:verify_single_dpll_state.isra.85 [i915]] DPLL 0 Oct 25 01:28:31 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003bd68fe3 Oct 25 01:28:31 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000790ff029 Oct 25 01:28:31 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f41115d1 state to 00000000790ff029 Oct 25 01:28:31 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000be151ce4 state to 00000000790ff029 Oct 25 01:28:31 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000be151ce4 Oct 25 01:28:31 [drm:drm_atomic_check_only [drm]] checking 00000000790ff029 Oct 25 01:28:31 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:31 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:31 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:31 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000790ff029 nonblocking Oct 25 01:28:31 [drm:drm_mode_setcrtc [drm]] [CRTC:63:pipe B] Oct 25 01:28:31 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 0000000072af666f state to 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 000000003d9827b8 state to 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 0000000072af666f Oct 25 01:28:31 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 000000003d9827b8 Oct 25 01:28:31 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_check_only [drm]] checking 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_commit [drm]] committing 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003bd68fe3 Oct 25 01:28:31 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_mode_setcrtc [drm]] [CRTC:81:pipe C] Oct 25 01:28:31 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 00000000ba50238f state to 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 00000000811bd8b7 state to 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 00000000ba50238f Oct 25 01:28:31 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 00000000811bd8b7 Oct 25 01:28:31 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_check_only [drm]] checking 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_commit [drm]] committing 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003bd68fe3 Oct 25 01:28:31 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003bd68fe3 Oct 25 01:28:31 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000790ff029 Oct 25 01:28:31 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000790ff029 Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003f0168ca Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005633a272 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008b6e35ab state to 000000005633a272 Oct 25 01:28:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000038de9638 state to 000000005633a272 Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000038de9638 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 000000005633a272 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005633a272 nonblocking Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d61a6783 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000790ff029 state to 00000000d61a6783 Oct 25 01:28:32 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000d61a6783 Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005633a272 Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005633a272 Oct 25 01:28:32 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 0000000044751341 state to 00000000d61a6783 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 00000000d61a6783 Oct 25 01:28:32 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1] Oct 25 01:28:32 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A] Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_commit [drm]] committing 00000000d61a6783 Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d61a6783 Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d61a6783 Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000000a33420a Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001957e0b0 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003a72aca5 state to 000000001957e0b0 Oct 25 01:28:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000027dea594 state to 000000001957e0b0 Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000027dea594 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 000000001957e0b0 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001957e0b0 nonblocking Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001957e0b0 Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001957e0b0 Oct 25 01:28:32 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:32 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:32 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:32 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:32 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:32 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:32 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:32 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:32 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:32 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:32 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:32 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:32 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:32 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:32 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:32 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:32 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:32 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:32 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:32 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:32 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a66456d4 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000028c5e2d5 state to 00000000a66456d4 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 00000000a66456d4 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_commit [drm]] committing 00000000a66456d4 Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a66456d4 Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a66456d4 Oct 25 01:28:32 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a66456d4 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000007624a57 state to 00000000a66456d4 Oct 25 01:28:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000be140843 state to 00000000a66456d4 Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000be140843 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 00000000a66456d4 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a66456d4 nonblocking Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035564a8c Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000bae0f477 state to 0000000035564a8c Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 0000000035564a8c Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_commit [drm]] committing 0000000035564a8c Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a66456d4 Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a66456d4 Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035564a8c Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035564a8c Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000d16a261d Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035564a8c Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000007624a57 state to 0000000035564a8c Oct 25 01:28:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009383b4c1 state to 0000000035564a8c Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000009383b4c1 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 0000000035564a8c Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000035564a8c nonblocking Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000016d72364 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003b783e31 state to 0000000016d72364 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 0000000016d72364 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_commit [drm]] committing 0000000016d72364 Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035564a8c Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035564a8c Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000016d72364 Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000016d72364 Oct 25 01:28:32 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e3b91be Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000f18f79d state to 000000009e3b91be Oct 25 01:28:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000021fc25ab state to 000000009e3b91be Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000021fc25ab Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 000000009e3b91be Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e3b91be nonblocking Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000060a8d02 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008bf74c8e state to 00000000060a8d02 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 00000000060a8d02 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_commit [drm]] committing 00000000060a8d02 Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e3b91be Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e3b91be Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000060a8d02 Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000060a8d02 Oct 25 01:28:32 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f41115d1 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000790ff029 state to 00000000f41115d1 Oct 25 01:28:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000025023314 state to 00000000f41115d1 Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000025023314 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 00000000f41115d1 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f41115d1 nonblocking Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d90d204a Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d61a6783 state to 00000000d90d204a Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 00000000d90d204a Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_commit [drm]] committing 00000000d90d204a Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f41115d1 Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f41115d1 Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d90d204a Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d90d204a Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000aafe9fca Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d56ea531 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b3b3f2c0 state to 00000000d56ea531 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 00000000d56ea531 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_commit [drm]] committing 00000000d56ea531 Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d56ea531 Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d56ea531 Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000011adf870 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000af1a6f66 state to 0000000011adf870 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 0000000011adf870 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_commit [drm]] committing 0000000011adf870 Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000011adf870 Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000011adf870 Oct 25 01:28:32 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008db0949f Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000039084ed0 state to 000000008db0949f Oct 25 01:28:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c225610c state to 000000008db0949f Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000c225610c Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 000000008db0949f Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008db0949f nonblocking Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008db0949f Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008db0949f Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008db0949f Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005ea07cb0 state to 000000008db0949f Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 000000008db0949f Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_commit [drm]] committing 000000008db0949f Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008db0949f Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008db0949f Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000c3b28bca Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000011adf870 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001422da5e state to 0000000011adf870 Oct 25 01:28:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001c2c4f00 state to 0000000011adf870 Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000001c2c4f00 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 0000000011adf870 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000011adf870 nonblocking Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000011adf870 Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000011adf870 Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000024fcaf13 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a092e2eb Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000807780fd state to 00000000a092e2eb Oct 25 01:28:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a5b3cf65 state to 00000000a092e2eb Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000a5b3cf65 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 00000000a092e2eb Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a092e2eb nonblocking Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c67fb361 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000071a64e40 state to 00000000c67fb361 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 00000000c67fb361 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_commit [drm]] committing 00000000c67fb361 Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a092e2eb Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a092e2eb Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c67fb361 Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c67fb361 Oct 25 01:28:32 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c67fb361 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000807780fd state to 00000000c67fb361 Oct 25 01:28:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000027dea594 state to 00000000c67fb361 Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000027dea594 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 00000000c67fb361 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c67fb361 nonblocking Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000060e8e09d Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006f5741a1 state to 0000000060e8e09d Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 0000000060e8e09d Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_commit [drm]] committing 0000000060e8e09d Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c67fb361 Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c67fb361 Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000060e8e09d Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000060e8e09d Oct 25 01:28:32 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000060e8e09d Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000807780fd state to 0000000060e8e09d Oct 25 01:28:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab3122dd state to 0000000060e8e09d Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000ab3122dd Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 0000000060e8e09d Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000060e8e09d nonblocking Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000060e8e09d Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000060e8e09d Oct 25 01:28:32 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fef8651c Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006776902b state to 00000000fef8651c Oct 25 01:28:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c6bbb041 state to 00000000fef8651c Oct 25 01:28:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000c6bbb041 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 00000000fef8651c Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000fef8651c nonblocking Oct 25 01:28:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c9540416 Oct 25 01:28:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000060e8e09d state to 00000000c9540416 Oct 25 01:28:32 [drm:drm_atomic_check_only [drm]] checking 00000000c9540416 Oct 25 01:28:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:32 [drm:drm_atomic_commit [drm]] committing 00000000c9540416 Oct 25 01:28:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fef8651c Oct 25 01:28:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fef8651c Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c9540416 Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c9540416 Oct 25 01:28:33 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bf74c8e Oct 25 01:28:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006a849dc5 state to 000000008bf74c8e Oct 25 01:28:33 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ac3180e7 state to 000000008bf74c8e Oct 25 01:28:33 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000ac3180e7 Oct 25 01:28:33 [drm:drm_atomic_check_only [drm]] checking 000000008bf74c8e Oct 25 01:28:33 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:33 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:33 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bf74c8e nonblocking Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bf74c8e Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bf74c8e Oct 25 01:28:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b6d6dc91 Oct 25 01:28:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d452265e state to 00000000b6d6dc91 Oct 25 01:28:33 [drm:drm_atomic_check_only [drm]] checking 00000000b6d6dc91 Oct 25 01:28:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:33 [drm:drm_atomic_commit [drm]] committing 00000000b6d6dc91 Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b6d6dc91 Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b6d6dc91 Oct 25 01:28:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7e689bb Oct 25 01:28:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000dd70ae7c state to 00000000a7e689bb Oct 25 01:28:33 [drm:drm_atomic_check_only [drm]] checking 00000000a7e689bb Oct 25 01:28:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:33 [drm:drm_atomic_commit [drm]] committing 00000000a7e689bb Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7e689bb Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7e689bb Oct 25 01:28:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7e689bb Oct 25 01:28:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ba03e858 state to 00000000a7e689bb Oct 25 01:28:33 [drm:drm_atomic_check_only [drm]] checking 00000000a7e689bb Oct 25 01:28:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:33 [drm:drm_atomic_commit [drm]] committing 00000000a7e689bb Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7e689bb Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7e689bb Oct 25 01:28:33 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b6d6dc91 Oct 25 01:28:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003becacd6 state to 00000000b6d6dc91 Oct 25 01:28:33 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e26ae9fc state to 00000000b6d6dc91 Oct 25 01:28:33 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000e26ae9fc Oct 25 01:28:33 [drm:drm_atomic_check_only [drm]] checking 00000000b6d6dc91 Oct 25 01:28:33 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:33 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:33 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b6d6dc91 nonblocking Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b6d6dc91 Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b6d6dc91 Oct 25 01:28:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b3f6da0e Oct 25 01:28:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008bf74c8e state to 00000000b3f6da0e Oct 25 01:28:33 [drm:drm_atomic_check_only [drm]] checking 00000000b3f6da0e Oct 25 01:28:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:33 [drm:drm_atomic_commit [drm]] committing 00000000b3f6da0e Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b3f6da0e Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b3f6da0e Oct 25 01:28:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000517d25c5 Oct 25 01:28:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001030041c state to 00000000517d25c5 Oct 25 01:28:33 [drm:drm_atomic_check_only [drm]] checking 00000000517d25c5 Oct 25 01:28:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:33 [drm:drm_atomic_commit [drm]] committing 00000000517d25c5 Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000517d25c5 Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000517d25c5 Oct 25 01:28:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006f5741a1 Oct 25 01:28:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000c67fb361 state to 000000006f5741a1 Oct 25 01:28:33 [drm:drm_atomic_check_only [drm]] checking 000000006f5741a1 Oct 25 01:28:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:33 [drm:drm_atomic_commit [drm]] committing 000000006f5741a1 Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006f5741a1 Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006f5741a1 Oct 25 01:28:33 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b783e31 Oct 25 01:28:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000016d72364 state to 000000003b783e31 Oct 25 01:28:33 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000080db0e37 state to 000000003b783e31 Oct 25 01:28:33 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000080db0e37 Oct 25 01:28:33 [drm:drm_atomic_check_only [drm]] checking 000000003b783e31 Oct 25 01:28:33 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:33 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:33 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003b783e31 nonblocking Oct 25 01:28:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008b6e35ab Oct 25 01:28:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005633a272 state to 000000008b6e35ab Oct 25 01:28:33 [drm:drm_atomic_check_only [drm]] checking 000000008b6e35ab Oct 25 01:28:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:33 [drm:drm_atomic_commit [drm]] committing 000000008b6e35ab Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b783e31 Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b783e31 Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008b6e35ab Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008b6e35ab Oct 25 01:28:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000020cc3653 Oct 25 01:28:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000af23d265 state to 0000000020cc3653 Oct 25 01:28:33 [drm:drm_atomic_check_only [drm]] checking 0000000020cc3653 Oct 25 01:28:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:33 [drm:drm_atomic_commit [drm]] committing 0000000020cc3653 Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000020cc3653 Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000020cc3653 Oct 25 01:28:33 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c576626d Oct 25 01:28:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000013bc0d9 state to 00000000c576626d Oct 25 01:28:33 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e4c1b762 state to 00000000c576626d Oct 25 01:28:33 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000e4c1b762 Oct 25 01:28:33 [drm:drm_atomic_check_only [drm]] checking 00000000c576626d Oct 25 01:28:33 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:33 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:33 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c576626d nonblocking Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c576626d Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c576626d Oct 25 01:28:33 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:33 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:33 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:33 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:33 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:33 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:33 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:33 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:33 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:33 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:33 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:33 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:33 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:33 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:33 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:33 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:33 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:33 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:33 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:33 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:33 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003cda299d Oct 25 01:28:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000004fc97502 state to 000000003cda299d Oct 25 01:28:33 [drm:drm_atomic_check_only [drm]] checking 000000003cda299d Oct 25 01:28:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:33 [drm:drm_atomic_commit [drm]] committing 000000003cda299d Oct 25 01:28:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003cda299d Oct 25 01:28:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003cda299d Oct 25 01:28:34 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:34 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:34 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:34 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:34 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:34 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:34 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:34 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:34 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:34 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:34 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:34 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:34 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:34 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:34 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:34 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:34 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:34 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:34 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:34 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:34 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:34 [drm:drm_mode_addfb2 [drm]] [FB:113] Oct 25 01:28:34 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000051539640 Oct 25 01:28:34 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002e04aef1 state to 0000000051539640 Oct 25 01:28:34 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001c8f4cb3 state to 0000000051539640 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000001c8f4cb3 Oct 25 01:28:34 [drm:drm_atomic_check_only [drm]] checking 0000000051539640 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:34 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000051539640 nonblocking Oct 25 01:28:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000051539640 Oct 25 01:28:34 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000051539640 Oct 25 01:28:34 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:34 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:34 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:34 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:34 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:34 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:34 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:34 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:34 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:34 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:34 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:34 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:34 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:34 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:34 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:34 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:34 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:34 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:34 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:34 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:34 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e4c1b762 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000008656ef05 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000b98d87a5 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e4c1b762 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000a832fd69 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e4c1b762 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000000b541f79 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000005081b310 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000000b541f79 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000005081b310 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000000b541f79 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000005081b310 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000000b541f79 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:34 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000046fdf367 Oct 25 01:28:34 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001422361a state to 0000000046fdf367 Oct 25 01:28:34 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001eb7efd1 state to 0000000046fdf367 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000001eb7efd1 Oct 25 01:28:34 [drm:drm_atomic_check_only [drm]] checking 0000000046fdf367 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:34 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000046fdf367 nonblocking Oct 25 01:28:34 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e1b44b65 Oct 25 01:28:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000046fdf367 Oct 25 01:28:34 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000046fdf367 Oct 25 01:28:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1b44b65 Oct 25 01:28:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1b44b65 Oct 25 01:28:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1b44b65 Oct 25 01:28:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1b44b65 Oct 25 01:28:34 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e1b44b65 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000667bab60 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000000b541f79 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000667bab60 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000000b541f79 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000667bab60 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005ea07cb0 Oct 25 01:28:34 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003bd68fe3 state to 000000005ea07cb0 Oct 25 01:28:34 [drm:drm_atomic_check_only [drm]] checking 000000005ea07cb0 Oct 25 01:28:34 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:34 [drm:drm_atomic_commit [drm]] committing 000000005ea07cb0 Oct 25 01:28:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005ea07cb0 Oct 25 01:28:34 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005ea07cb0 Oct 25 01:28:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000b6ae1dd4 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:34 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:34 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:34 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:34 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:34 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:34 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:34 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:34 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:34 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:34 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:34 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:34 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:34 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:34 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:34 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:34 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:34 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:34 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:34 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:34 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:35 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000f9f187f8 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fccd1d90 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000f9f187f8 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fccd1d90 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000000b541f79 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000008b74f43c Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003f0168ca Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000008b74f43c Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003f0168ca Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000008b74f43c Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000007b7a9326 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000963b409f Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000009d197ed5 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003f0168ca Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:35 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f41115d1 Oct 25 01:28:35 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000790ff029 state to 00000000f41115d1 Oct 25 01:28:35 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009d9820b6 state to 00000000f41115d1 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000009d9820b6 Oct 25 01:28:35 [drm:drm_atomic_check_only [drm]] checking 00000000f41115d1 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:35 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f41115d1 nonblocking Oct 25 01:28:35 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000011ad9bf8 Oct 25 01:28:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f41115d1 Oct 25 01:28:35 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f41115d1 Oct 25 01:28:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000011ad9bf8 Oct 25 01:28:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000011ad9bf8 Oct 25 01:28:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000011ad9bf8 Oct 25 01:28:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000011ad9bf8 Oct 25 01:28:35 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000011ad9bf8 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000df5b4594 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003f0168ca Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000df5b4594 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003f0168ca Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000006afceba5 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005ea07cb0 Oct 25 01:28:35 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000008b8bd6d1 state to 000000005ea07cb0 Oct 25 01:28:35 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003bd68fe3 state to 000000005ea07cb0 Oct 25 01:28:35 [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:42:cursor A] state 000000008b8bd6d1 to [NOCRTC] Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000008b8bd6d1 Oct 25 01:28:35 [drm:drm_atomic_check_only [drm]] checking 000000005ea07cb0 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb -1 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 0, off 1, on 0, ms 0 Oct 25 01:28:35 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:35 [drm:drm_atomic_commit [drm]] committing 000000005ea07cb0 Oct 25 01:28:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005ea07cb0 Oct 25 01:28:35 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005ea07cb0 Oct 25 01:28:35 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005ea07cb0 Oct 25 01:28:35 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000c3b28bca state to 000000005ea07cb0 Oct 25 01:28:35 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006d2e0ee2 state to 000000005ea07cb0 Oct 25 01:28:35 [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:42:cursor A] state 00000000c3b28bca to [CRTC:45:pipe A] Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000c3b28bca Oct 25 01:28:35 [drm:drm_atomic_check_only [drm]] checking 000000005ea07cb0 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 0 -> 1, off 0, on 1, ms 0 Oct 25 01:28:35 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:35 [drm:drm_atomic_commit [drm]] committing 000000005ea07cb0 Oct 25 01:28:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005ea07cb0 Oct 25 01:28:35 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005ea07cb0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e26ae9fc Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000d394c5a1 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e26ae9fc Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000df5b4594 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000027f3c3c6 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000df5b4594 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000027f3c3c6 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000007311447f Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 0000000027f3c3c6 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000090052b13 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000027f3c3c6 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000090052b13 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000eeeff3b3 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000000782aee9 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000eeeff3b3 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000dc30f2da Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000876c124b Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000dc30f2da Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000876c124b Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000dc30f2da Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000876c124b Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000d394c5a1 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 0000000027f3c3c6 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000000782aee9 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000aafe9fca Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000000782aee9 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000aafe9fca Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000001c2c4f00 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000aafe9fca Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000001c2c4f00 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000aafe9fca Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000001c2c4f00 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:35 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000071a64e40 Oct 25 01:28:35 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a092e2eb state to 0000000071a64e40 Oct 25 01:28:35 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab3122dd state to 0000000071a64e40 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000ab3122dd Oct 25 01:28:35 [drm:drm_atomic_check_only [drm]] checking 0000000071a64e40 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:35 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000071a64e40 nonblocking Oct 25 01:28:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000071a64e40 Oct 25 01:28:35 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000071a64e40 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000001f2f4d18 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000a832fd69 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003a5a36a4 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000a832fd69 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003a5a36a4 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000028d37c7f Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000d394c5a1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000028d37c7f Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000d394c5a1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000028d37c7f Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000d394c5a1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000e26ae9fc Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000c3b28bca Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000b6ae1dd4 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000c3b28bca Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008db0949f state to 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ac247d80 state to 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000ac247d80 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 0000000070037dd2 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000070037dd2 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000070037dd2 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000d394c5a1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 000000003250c036 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000e7cc1ae0 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000070037dd2 state to 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000018bd19e7 state to 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000018bd19e7 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 0000000039084ed0 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000039084ed0 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000039084ed0 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000d7b9ad72 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000039084ed0 state to 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e7cc1ae0 state to 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000e7cc1ae0 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000006d2e0ee2 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006d2e0ee2 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006d2e0ee2 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000c3b256d6 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006d2e0ee2 state to 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008ed11c40 state to 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000008ed11c40 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000008db0949f Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008db0949f nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008db0949f Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 000000005f4424f7 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008db0949f state to 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008caea0d6 state to 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000008caea0d6 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 0000000070037dd2 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000070037dd2 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000070037dd2 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000cff908dc Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000070037dd2 state to 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000deb85f67 state to 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000deb85f67 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 0000000039084ed0 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000039084ed0 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000039084ed0 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000c3b256d6 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000039084ed0 state to 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000030776f7 state to 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000030776f7 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000006d2e0ee2 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006d2e0ee2 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006d2e0ee2 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 000000005f4424f7 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006d2e0ee2 state to 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000006a5fa8 state to 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000006a5fa8 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000008db0949f Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008db0949f nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008db0949f Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000cff908dc Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008db0949f state to 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000011155843 state to 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000011155843 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 0000000070037dd2 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000070037dd2 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000070037dd2 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000c3b256d6 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000070037dd2 state to 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b75185b4 state to 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000b75185b4 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 0000000039084ed0 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000039084ed0 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000039084ed0 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 000000005f4424f7 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000039084ed0 state to 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000fc87309 state to 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000000fc87309 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000006d2e0ee2 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006d2e0ee2 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008db0949f Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008db0949f Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000cff908dc Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006d2e0ee2 state to 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000382c4688 state to 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000382c4688 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000008db0949f Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008db0949f nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008db0949f Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000c3b256d6 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008db0949f state to 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000042c32216 state to 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000042c32216 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 0000000070037dd2 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000070037dd2 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000070037dd2 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000070037dd2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 000000005f4424f7 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000070037dd2 state to 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000015f3cf28 state to 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000015f3cf28 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 0000000039084ed0 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000039084ed0 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000039084ed0 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000039084ed0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000cff908dc Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000039084ed0 state to 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004e16e8eb state to 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000004e16e8eb Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000006d2e0ee2 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006d2e0ee2 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006d2e0ee2 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006d2e0ee2 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000c3b256d6 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006d2e0ee2 state to 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005a006f94 state to 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000005a006f94 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000008db0949f Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008db0949f nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008db0949f Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008db0949f Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000a607ccf Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d11d0143 state to 000000000a607ccf Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000af79579a state to 000000000a607ccf Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000af79579a Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000000a607ccf Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000a607ccf nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000a607ccf Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000a607ccf Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000b72760f1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000790ad3d1 state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000790ad3d1 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000d96413a1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000831b5c2 state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007a7cc8fd state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000007a7cc8fd Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000086b7f1e7 state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000086b7f1e7 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000b72760f1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d11d0143 state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ead0a771 state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000ead0a771 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000d96413a1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000099302014 state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000099302014 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000831b5c2 state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000df7ca577 state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000df7ca577 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000b72760f1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000076404959 state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000076404959 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000d96413a1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d11d0143 state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f9b80281 state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000f9b80281 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000d96413a1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000076404959 state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000076404959 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000b72760f1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000831b5c2 state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000df7ca577 state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000df7ca577 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000099302014 state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000099302014 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000d96413a1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d11d0143 state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ead0a771 state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000ead0a771 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000b72760f1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000086b7f1e7 state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000086b7f1e7 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000831b5c2 state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007a7cc8fd state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000007a7cc8fd Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000d96413a1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000790ad3d1 state to 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000790ad3d1 Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000b72760f1 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d11d0143 state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000af79579a state to 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000af79579a Oct 25 01:28:36 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000b72760f1 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:37 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ce724567 state to 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000ce724567 Oct 25 01:28:37 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:37 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000d96413a1 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:37 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:37 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000831b5c2 state to 000000009209238b Oct 25 01:28:37 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000af79579a state to 000000009209238b Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000af79579a Oct 25 01:28:37 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:37 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:37 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000d96413a1 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000d96413a1 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000d96413a1 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:37 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:37 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000009209238b Oct 25 01:28:37 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000790ad3d1 state to 000000009209238b Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000790ad3d1 Oct 25 01:28:37 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:37 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:37 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000b72760f1 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_mode_addfb2 [drm]] [FB:110] Oct 25 01:28:37 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d11d0143 state to 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007a7cc8fd state to 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000007a7cc8fd Oct 25 01:28:37 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:37 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:37 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000086b7f1e7 state to 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000086b7f1e7 Oct 25 01:28:37 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:37 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 00000000b72760f1 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000069431b6e Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000069431b6e Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:37 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:37 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:37 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000033d45509 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:37 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:37 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000831b5c2 state to 000000009209238b Oct 25 01:28:37 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ca6401d6 state to 000000009209238b Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000ca6401d6 Oct 25 01:28:37 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:37 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:37 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000d96413a1 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110 Oct 25 01:28:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:37 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:37 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:37 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:37 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:37 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:37 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:37 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:37 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:37 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:37 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:37 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:37 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:37 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:37 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:37 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:37 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:37 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:37 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:37 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:37 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:37 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:37 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:37 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:37 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:37 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:37 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:37 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:37 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:37 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:37 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:37 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:37 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:37 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:37 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:37 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:37 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:37 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:37 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:37 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:37 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:37 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:38 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:38 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:38 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:38 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000009209238b Oct 25 01:28:38 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ac3180e7 state to 000000009209238b Oct 25 01:28:38 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000ac3180e7 Oct 25 01:28:38 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:38 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:38 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:38 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:38 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:38 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:38 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:38 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000013bc0d9 Oct 25 01:28:38 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d8b9aa70 state to 00000000013bc0d9 Oct 25 01:28:38 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000062f3bb01 state to 00000000013bc0d9 Oct 25 01:28:38 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000062f3bb01 Oct 25 01:28:38 [drm:drm_atomic_check_only [drm]] checking 00000000013bc0d9 Oct 25 01:28:38 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:38 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:38 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:38 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000013bc0d9 nonblocking Oct 25 01:28:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000013bc0d9 Oct 25 01:28:38 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000013bc0d9 Oct 25 01:28:38 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:38 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c576626d Oct 25 01:28:38 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001030041c state to 00000000c576626d Oct 25 01:28:38 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003ae811e5 state to 00000000c576626d Oct 25 01:28:38 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000003ae811e5 Oct 25 01:28:38 [drm:drm_atomic_check_only [drm]] checking 00000000c576626d Oct 25 01:28:38 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:38 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:38 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:38 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c576626d nonblocking Oct 25 01:28:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c576626d Oct 25 01:28:38 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c576626d Oct 25 01:28:38 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:38 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000011ad9bf8 Oct 25 01:28:38 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000af23d265 state to 0000000011ad9bf8 Oct 25 01:28:38 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000038de9638 state to 0000000011ad9bf8 Oct 25 01:28:38 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000038de9638 Oct 25 01:28:38 [drm:drm_atomic_check_only [drm]] checking 0000000011ad9bf8 Oct 25 01:28:38 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:38 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:38 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:38 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000011ad9bf8 nonblocking Oct 25 01:28:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000011ad9bf8 Oct 25 01:28:38 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000011ad9bf8 Oct 25 01:28:38 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:38 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000016d72364 Oct 25 01:28:38 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000022d35873 state to 0000000016d72364 Oct 25 01:28:38 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001e352911 state to 0000000016d72364 Oct 25 01:28:38 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000001e352911 Oct 25 01:28:38 [drm:drm_atomic_check_only [drm]] checking 0000000016d72364 Oct 25 01:28:38 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:38 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:38 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:38 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000016d72364 nonblocking Oct 25 01:28:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000016d72364 Oct 25 01:28:38 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000016d72364 Oct 25 01:28:38 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:38 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000032e6f96a Oct 25 01:28:38 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000045760692 state to 0000000032e6f96a Oct 25 01:28:38 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000969f2a83 state to 0000000032e6f96a Oct 25 01:28:38 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000969f2a83 Oct 25 01:28:38 [drm:drm_atomic_check_only [drm]] checking 0000000032e6f96a Oct 25 01:28:38 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:38 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:38 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:38 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000032e6f96a nonblocking Oct 25 01:28:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000032e6f96a Oct 25 01:28:38 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000032e6f96a Oct 25 01:28:38 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:38 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:38 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:38 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:38 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:38 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:38 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:38 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:38 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:38 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:38 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:38 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:38 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:38 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:38 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:38 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:38 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:38 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:38 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:38 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:39 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:39 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:39 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:39 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:39 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:39 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:39 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:39 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:39 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:39 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:39 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:39 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:39 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:39 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:39 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:39 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:39 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:39 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:39 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:39 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:39 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:39 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:39 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:39 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:39 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:39 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:39 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:39 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:39 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:39 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:39 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:39 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:39 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:39 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:39 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:39 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003fa0ca8a Oct 25 01:28:39 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b2d7df79 state to 000000003fa0ca8a Oct 25 01:28:39 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dd10b12a state to 000000003fa0ca8a Oct 25 01:28:39 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000dd10b12a Oct 25 01:28:39 [drm:drm_atomic_check_only [drm]] checking 000000003fa0ca8a Oct 25 01:28:39 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:39 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:39 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:39 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003fa0ca8a nonblocking Oct 25 01:28:39 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003fa0ca8a Oct 25 01:28:39 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003fa0ca8a Oct 25 01:28:39 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:39 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:39 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:39 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:39 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:39 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:39 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:39 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:39 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:39 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:39 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:39 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:39 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:39 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:39 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:39 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:39 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:39 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:39 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:39 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:39 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:39 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:39 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:39 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:39 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:39 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:39 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:39 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:39 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:39 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:39 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:39 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:39 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:39 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:39 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:39 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:39 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006f74f076 Oct 25 01:28:39 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000905f1073 state to 000000006f74f076 Oct 25 01:28:39 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000080db0e37 state to 000000006f74f076 Oct 25 01:28:39 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000080db0e37 Oct 25 01:28:39 [drm:drm_atomic_check_only [drm]] checking 000000006f74f076 Oct 25 01:28:39 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:39 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:39 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:39 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006f74f076 nonblocking Oct 25 01:28:39 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006f74f076 Oct 25 01:28:39 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006f74f076 Oct 25 01:28:40 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:40 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:40 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:40 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:40 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:40 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:40 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:40 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:40 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:40 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:40 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:40 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:40 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:40 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:40 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:40 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:40 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:40 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:40 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:40 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:40 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:40 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:40 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:40 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:40 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:40 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:40 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:40 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:40 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:40 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:40 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:40 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:40 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:40 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:40 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:40 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:40 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:40 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:40 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:40 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:40 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:40 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:40 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:40 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:40 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d11d0143 state to 000000006a849dc5 Oct 25 01:28:40 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000085a49d15 state to 000000006a849dc5 Oct 25 01:28:40 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000085a49d15 Oct 25 01:28:40 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:40 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:40 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:40 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:40 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:40 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:40 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:40 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:40 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:40 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000006a849dc5 Oct 25 01:28:40 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f9b80281 state to 000000006a849dc5 Oct 25 01:28:40 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000f9b80281 Oct 25 01:28:40 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:40 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:40 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:40 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:40 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:40 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:40 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:40 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:40 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:40 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000831b5c2 state to 000000009209238b Oct 25 01:28:40 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000085a49d15 state to 000000009209238b Oct 25 01:28:40 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000085a49d15 Oct 25 01:28:40 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:40 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:40 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:40 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:40 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:40 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:40 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:40 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:40 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:40 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000009209238b Oct 25 01:28:40 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000033d45509 state to 000000009209238b Oct 25 01:28:40 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000033d45509 Oct 25 01:28:40 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:40 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:40 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:40 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:40 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:40 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:40 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:41 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:41 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:41 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:41 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:41 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:41 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:41 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:41 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:41 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:41 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:41 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:41 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:41 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:41 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:41 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:41 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:41 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:41 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:41 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:41 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:41 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:41 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:41 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:41 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:41 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:41 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:41 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:41 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:41 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:41 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:41 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:41 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:41 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:41 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:41 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:41 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:41 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d11d0143 state to 000000006a849dc5 Oct 25 01:28:41 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000099302014 state to 000000006a849dc5 Oct 25 01:28:41 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000099302014 Oct 25 01:28:41 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:41 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:41 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:41 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:41 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:41 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:41 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:41 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:41 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000006a849dc5 Oct 25 01:28:41 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ead0a771 state to 000000006a849dc5 Oct 25 01:28:41 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000ead0a771 Oct 25 01:28:41 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:41 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:41 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:41 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:41 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:41 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:41 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:41 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:41 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000831b5c2 state to 000000009209238b Oct 25 01:28:41 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d1297729 state to 000000009209238b Oct 25 01:28:41 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000d1297729 Oct 25 01:28:41 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:41 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:41 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:41 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:41 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:41 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:41 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:41 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:41 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:41 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:41 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:41 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:41 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:41 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:41 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:41 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:41 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:41 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:41 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:41 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:41 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:41 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:41 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:41 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:41 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:41 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:41 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:41 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:41 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:41 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:41 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:41 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:41 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:41 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:41 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:41 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:41 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:41 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:41 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:41 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:41 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:42 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:42 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:42 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:42 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:42 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:42 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:42 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:42 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:42 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:42 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:42 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:42 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:42 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:42 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:42 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:42 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:42 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:42 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:42 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:42 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:42 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:42 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:42 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:42 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009209238b Oct 25 01:28:42 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000009209238b Oct 25 01:28:42 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000024033fa7 state to 000000009209238b Oct 25 01:28:42 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000024033fa7 Oct 25 01:28:42 [drm:drm_atomic_check_only [drm]] checking 000000009209238b Oct 25 01:28:42 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:42 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:42 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:42 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009209238b nonblocking Oct 25 01:28:42 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009209238b Oct 25 01:28:42 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009209238b Oct 25 01:28:42 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:42 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:42 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:42 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:42 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:42 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:42 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:42 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:42 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:42 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:42 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:42 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:42 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:42 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:42 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:42 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:42 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:42 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:42 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:42 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:42 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:42 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:42 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:42 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d11d0143 state to 000000006a849dc5 Oct 25 01:28:42 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008faa8862 state to 000000006a849dc5 Oct 25 01:28:42 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000008faa8862 Oct 25 01:28:42 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:42 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:42 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:42 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:42 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:42 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:42 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:42 [drm:drm_mode_addfb2 [drm]] [FB:111] Oct 25 01:28:42 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a849dc5 Oct 25 01:28:42 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000a607ccf state to 000000006a849dc5 Oct 25 01:28:42 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009296ee49 state to 000000006a849dc5 Oct 25 01:28:42 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000009296ee49 Oct 25 01:28:42 [drm:drm_atomic_check_only [drm]] checking 000000006a849dc5 Oct 25 01:28:42 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111 Oct 25 01:28:42 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:42 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:42 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a849dc5 nonblocking Oct 25 01:28:42 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a849dc5 Oct 25 01:28:42 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a849dc5 Oct 25 01:28:42 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000 Oct 25 01:28:42 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short Oct 25 01:28:42 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short Oct 25 01:28:42 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00 Oct 25 01:28:42 [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions Oct 25 01:28:42 [drm:i915_hotplug_work_func [i915]] Connector eDP-1 (pin 4) received hotplug event. Oct 25 01:28:42 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1] Oct 25 01:28:42 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 Oct 25 01:28:42 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 Oct 25 01:28:42 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 Oct 25 01:28:42 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000 Oct 25 01:28:42 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes Oct 25 01:28:42 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a Oct 25 01:28:42 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 Oct 25 01:28:42 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 Oct 25 01:28:42 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 Oct 25 01:28:42 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 Oct 25 01:28:42 [drm:intel_dp_start_link_train [i915]] clock recovery OK Oct 25 01:28:42 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 Oct 25 01:28:42 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful Oct 25 01:28:42 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4 Oct 25 01:28:42 [drm:drm_mode_addfb2 [drm]] [FB:114] Oct 25 01:28:42 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002fbbb036 Oct 25 01:28:42 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ddb176f8 state to 000000002fbbb036 Oct 25 01:28:42 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004ae98ac9 state to 000000002fbbb036 Oct 25 01:28:42 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000004ae98ac9 Oct 25 01:28:42 [drm:drm_atomic_check_only [drm]] checking 000000002fbbb036 Oct 25 01:28:42 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114 Oct 25 01:28:42 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 Oct 25 01:28:42 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45 Oct 25 01:28:42 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002fbbb036 nonblocking Oct 25 01:28:42 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002fbbb036 Oct 25 01:28:42 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002fbbb036