Command: ./roles -1 1 Driver vendor: X.Org Device vendor: AMD Device name: AMD Radeon (TM) RX 460 Graphics (POLARIS11, DRM 3.27.0, 4.19.2, LLVM 7.0.0) pipe = 0x138d0b0 time before (API call) = 330.791039s time after (driver done) = 328.142314s flush_resource: resource: {target = 2d, format = PIPE_FORMAT_B8G8R8X8_UNORM, width0 = 1920, height0 = 1080, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 1572874, flags = 0, } ***************************************************************************** Driver-specific state: Memory-mapped registers: GRBM_STATUS <- ME0PIPE0_CMDFIFO_AVAIL = 8 SRBM_RQ_PENDING = 1 ME0PIPE0_CF_RQ_PENDING = 0 ME0PIPE0_PF_RQ_PENDING = 0 GDS_DMA_RQ_PENDING = 0 DB_CLEAN = 1 CB_CLEAN = 0 TA_BUSY = 0 GDS_BUSY = 0 WD_BUSY_NO_DMA = 0 VGT_BUSY = 0 IA_BUSY_NO_DMA = 0 IA_BUSY = 0 SX_BUSY = 1 WD_BUSY = 0 SPI_BUSY = 1 BCI_BUSY = 1 SC_BUSY = 1 PA_BUSY = 0 DB_BUSY = 1 CP_COHERENCY_BUSY = 0 CP_BUSY = 1 CB_BUSY = 1 GUI_ACTIVE = 1 GRBM_STATUS2 <- ME0PIPE1_CMDFIFO_AVAIL = 8 ME0PIPE1_CF_RQ_PENDING = 0 ME0PIPE1_PF_RQ_PENDING = 0 ME1PIPE0_RQ_PENDING = 0 ME1PIPE1_RQ_PENDING = 0 ME1PIPE2_RQ_PENDING = 0 ME1PIPE3_RQ_PENDING = 0 ME2PIPE0_RQ_PENDING = 0 ME2PIPE1_RQ_PENDING = 0 ME2PIPE2_RQ_PENDING = 0 ME2PIPE3_RQ_PENDING = 0 RLC_RQ_PENDING = 0 RLC_BUSY = 0 TC_BUSY = 1 TCC_CC_RESIDENT = 0 CPF_BUSY = 1 CPC_BUSY = 0 CPG_BUSY = 1 GRBM_STATUS_SE0 <- DB_CLEAN = 1 CB_CLEAN = 1 BCI_BUSY = 1 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 1 SPI_BUSY = 1 SC_BUSY = 1 DB_BUSY = 1 CB_BUSY = 1 GRBM_STATUS_SE1 <- DB_CLEAN = 1 CB_CLEAN = 0 BCI_BUSY = 1 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 1 SPI_BUSY = 1 SC_BUSY = 1 DB_BUSY = 1 CB_BUSY = 1 GRBM_STATUS_SE2 <- DB_CLEAN = 1 CB_CLEAN = 1 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 0 SC_BUSY = 0 DB_BUSY = 0 CB_BUSY = 0 GRBM_STATUS_SE3 <- DB_CLEAN = 1 CB_CLEAN = 1 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 0 SC_BUSY = 0 DB_BUSY = 0 CB_BUSY = 0 SDMA0_STATUS_REG <- IDLE = 0 REG_IDLE = 1 RB_EMPTY = 0 RB_FULL = 0 RB_CMD_IDLE = 0 RB_CMD_FULL = 0 IB_CMD_IDLE = 1 IB_CMD_FULL = 0 BLOCK_IDLE = 0 INSIDE_IB = 0 EX_IDLE = 1 EX_IDLE_POLL_TIMER_EXPIRE = 0 PACKET_READY = 0 MC_WR_IDLE = 1 SRBM_IDLE = 1 CONTEXT_EMPTY = 0 DELTA_RPTR_FULL = 0 RB_MC_RREQ_IDLE = 0 IB_MC_RREQ_IDLE = 1 MC_RD_IDLE = 1 DELTA_RPTR_EMPTY = 1 MC_RD_RET_STALL = 0 MC_RD_NO_POLL_IDLE = 1 PREV_CMD_IDLE = 1 SEM_IDLE = 1 SEM_REQ_STALL = 0 SEM_RESP_STATE = 0 INT_IDLE = 1 INT_REQ_STALL = 0 SDMA1_STATUS_REG <- IDLE = 1 REG_IDLE = 1 RB_EMPTY = 1 RB_FULL = 0 RB_CMD_IDLE = 1 RB_CMD_FULL = 0 IB_CMD_IDLE = 1 IB_CMD_FULL = 0 BLOCK_IDLE = 1 INSIDE_IB = 0 EX_IDLE = 1 EX_IDLE_POLL_TIMER_EXPIRE = 1 PACKET_READY = 0 MC_WR_IDLE = 1 SRBM_IDLE = 1 CONTEXT_EMPTY = 1 DELTA_RPTR_FULL = 0 RB_MC_RREQ_IDLE = 1 IB_MC_RREQ_IDLE = 1 MC_RD_IDLE = 1 DELTA_RPTR_EMPTY = 1 MC_RD_RET_STALL = 0 MC_RD_NO_POLL_IDLE = 1 PREV_CMD_IDLE = 1 SEM_IDLE = 1 SEM_REQ_STALL = 0 SEM_RESP_STATE = 0 INT_IDLE = 1 INT_REQ_STALL = 0 SRBM_STATUS <- UVD_RQ_PENDING = 0 SAMMSP_RQ_PENDING = 0 ACP_RQ_PENDING = 0 SMU_RQ_PENDING = 0 GRBM_RQ_PENDING = 0 HI_RQ_PENDING = 1 VMC_BUSY = 0 MCB_BUSY = 1 MCB_NON_DISPLAY_BUSY = 1 MCC_BUSY = 1 MCD_BUSY = 0 VMC1_BUSY = 0 SEM_BUSY = 0 ACP_BUSY = 0 IH_BUSY = 0 UVD_BUSY = 0 SAMMSP_BUSY = 0 GCATCL2_BUSY = 0 OSATCL2_BUSY = 0 BIF_BUSY = 1 SRBM_STATUS2 <- SDMA_RQ_PENDING = 0 TST_RQ_PENDING = 0 SDMA1_RQ_PENDING = 0 VCE0_RQ_PENDING = 0 VP8_BUSY = 0 SDMA_BUSY = 1 SDMA1_BUSY = 0 VCE0_BUSY = 0 XDMA_BUSY = 0 CHUB_BUSY = 0 SDMA2_BUSY = 0 SDMA3_BUSY = 0 SAMSCP_BUSY = 0 ISP_BUSY = 0 VCE1_BUSY = 0 ODE_BUSY = 0 SDMA2_RQ_PENDING = 0 SDMA3_RQ_PENDING = 0 SAMSCP_RQ_PENDING = 0 ISP_RQ_PENDING = 0 VCE1_RQ_PENDING = 0 SRBM_STATUS3 <- MCC0_BUSY = 1 MCC1_BUSY = 0 MCC2_BUSY = 0 MCC3_BUSY = 0 MCC4_BUSY = 0 MCC5_BUSY = 0 MCC6_BUSY = 0 MCC7_BUSY = 0 MCD0_BUSY = 0 MCD1_BUSY = 0 MCD2_BUSY = 0 MCD3_BUSY = 0 MCD4_BUSY = 0 MCD5_BUSY = 0 MCD6_BUSY = 0 MCD7_BUSY = 0 CP_STAT <- ROQ_RING_BUSY = 1 ROQ_INDIRECT1_BUSY = 1 ROQ_INDIRECT2_BUSY = 0 ROQ_STATE_BUSY = 0 DC_BUSY = 0 ATCL2IU_BUSY = 0 PFP_BUSY = 1 MEQ_BUSY = 1 ME_BUSY = 1 QUERY_BUSY = 1 SEMAPHORE_BUSY = 0 INTERRUPT_BUSY = 0 SURFACE_SYNC_BUSY = 0 DMA_BUSY = 0 RCIU_BUSY = 0 SCRATCH_RAM_BUSY = 0 CPC_CPG_BUSY = 0 CE_BUSY = 0 TCIU_BUSY = 0 ROQ_CE_RING_BUSY = 0 ROQ_CE_INDIRECT1_BUSY = 0 ROQ_CE_INDIRECT2_BUSY = 0 CP_BUSY = 1 CP_STALLED_STAT1 <- RBIU_TO_DMA_NOT_RDY_TO_RCV = 0 RBIU_TO_SEM_NOT_RDY_TO_RCV = 0 RBIU_TO_MEMWR_NOT_RDY_TO_RCV = 0 ME_HAS_ACTIVE_CE_BUFFER_FLAG = 1 ME_HAS_ACTIVE_DE_BUFFER_FLAG = 1 ME_STALLED_ON_TC_WR_CONFIRM = 0 ME_STALLED_ON_ATOMIC_RTN_DATA = 0 ME_WAITING_ON_TC_READ_DATA = 0 ME_WAITING_ON_REG_READ_DATA = 0 RCIU_WAITING_ON_GDS_FREE = 0 RCIU_WAITING_ON_GRBM_FREE = 0 RCIU_WAITING_ON_VGT_FREE = 0 RCIU_STALLED_ON_ME_READ = 0 RCIU_STALLED_ON_DMA_READ = 0 RCIU_STALLED_ON_APPEND_READ = 0 RCIU_HALTED_BY_REG_VIOLATION = 0 CP_STALLED_STAT2 <- PFP_TO_CSF_NOT_RDY_TO_RCV = 0 PFP_TO_MEQ_NOT_RDY_TO_RCV = 0 PFP_TO_RCIU_NOT_RDY_TO_RCV = 0 PFP_TO_VGT_WRITES_PENDING = 0 PFP_RCIU_READ_PENDING = 0 PFP_WAITING_ON_BUFFER_DATA = 0 ME_WAIT_ON_CE_COUNTER = 0 ME_WAIT_ON_AVAIL_BUFFER = 0 GFX_CNTX_NOT_AVAIL_TO_ME = 0 ME_RCIU_NOT_RDY_TO_RCV = 0 ME_TO_CONST_NOT_RDY_TO_RCV = 0 ME_WAITING_DATA_FROM_PFP = 0 ME_WAITING_ON_PARTIAL_FLUSH = 1 MEQ_TO_ME_NOT_RDY_TO_RCV = 1 STQ_TO_ME_NOT_RDY_TO_RCV = 0 ME_WAITING_DATA_FROM_STQ = 0 PFP_STALLED_ON_TC_WR_CONFIRM = 0 PFP_STALLED_ON_ATOMIC_RTN_DATA = 0 EOPD_FIFO_NEEDS_SC_EOP_DONE = 1 EOPD_FIFO_NEEDS_WR_CONFIRM = 0 STRMO_WR_OF_PRIM_DATA_PENDING = 0 PIPE_STATS_WR_DATA_PENDING = 0 APPEND_RDY_WAIT_ON_CS_DONE = 0 APPEND_RDY_WAIT_ON_PS_DONE = 0 APPEND_WAIT_ON_WR_CONFIRM = 0 APPEND_ACTIVE_PARTITION = 0 APPEND_WAITING_TO_SEND_MEMWRITE = 0 SURF_SYNC_NEEDS_IDLE_CNTXS = 0 SURF_SYNC_NEEDS_ALL_CLEAN = 0 CP_STALLED_STAT3 <- CE_TO_CSF_NOT_RDY_TO_RCV = 0 CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV = 0 CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER = 0 CE_TO_RAM_INIT_NOT_RDY = 0 CE_TO_RAM_DUMP_NOT_RDY = 0 CE_TO_RAM_WRITE_NOT_RDY = 0 CE_TO_INC_FIFO_NOT_RDY_TO_RCV = 0 CE_TO_WR_FIFO_NOT_RDY_TO_RCV = 0 CE_WAITING_ON_BUFFER_DATA = 0 CE_WAITING_ON_CE_BUFFER_FLAG = 0 CE_WAITING_ON_DE_COUNTER = 0 CE_WAITING_ON_DE_COUNTER_UNDERFLOW = 0 TCIU_WAITING_ON_FREE = 0 TCIU_WAITING_ON_TAGS = 0 CE_STALLED_ON_TC_WR_CONFIRM = 0 CE_STALLED_ON_ATOMIC_RTN_DATA = 0 ATCL2IU_WAITING_ON_FREE = 0 ATCL2IU_WAITING_ON_TAGS = 0 ATCL1_WAITING_ON_TRANS = 0 CP_CPC_STATUS <- MEC1_BUSY = 0 MEC2_BUSY = 0 DC0_BUSY = 0 DC1_BUSY = 0 RCIU1_BUSY = 0 RCIU2_BUSY = 0 ROQ1_BUSY = 0 ROQ2_BUSY = 0 TCIU_BUSY = 0 SCRATCH_RAM_BUSY = 0 QU_BUSY = 0 ATCL2IU_BUSY = 0 CPG_CPC_BUSY = 0 CPF_CPC_BUSY = 0 CPC_BUSY = 0 CP_CPC_BUSY_STAT <- MEC1_LOAD_BUSY = 0 MEC1_SEMAPOHRE_BUSY = 0 MEC1_MUTEX_BUSY = 0 MEC1_MESSAGE_BUSY = 0 MEC1_EOP_QUEUE_BUSY = 0 MEC1_IQ_QUEUE_BUSY = 0 MEC1_IB_QUEUE_BUSY = 0 MEC1_TC_BUSY = 0 MEC1_DMA_BUSY = 0 MEC1_PARTIAL_FLUSH_BUSY = 0 MEC1_PIPE0_BUSY = 0 MEC1_PIPE1_BUSY = 0 MEC1_PIPE2_BUSY = 0 MEC1_PIPE3_BUSY = 0 MEC2_LOAD_BUSY = 0 MEC2_SEMAPOHRE_BUSY = 0 MEC2_MUTEX_BUSY = 0 MEC2_MESSAGE_BUSY = 0 MEC2_EOP_QUEUE_BUSY = 0 MEC2_IQ_QUEUE_BUSY = 0 MEC2_IB_QUEUE_BUSY = 0 MEC2_TC_BUSY = 0 MEC2_DMA_BUSY = 0 MEC2_PARTIAL_FLUSH_BUSY = 0 MEC2_PIPE0_BUSY = 0 MEC2_PIPE1_BUSY = 0 MEC2_PIPE2_BUSY = 0 MEC2_PIPE3_BUSY = 0 CP_CPC_STALLED_STAT1 <- RCIU_TX_FREE_STALL = 0 RCIU_PRIV_VIOLATION = 0 TCIU_TX_FREE_STALL = 0 MEC1_DECODING_PACKET = 0 MEC1_WAIT_ON_RCIU = 0 MEC1_WAIT_ON_RCIU_READ = 0 MEC1_WAIT_ON_ROQ_DATA = 0 MEC2_DECODING_PACKET = 0 MEC2_WAIT_ON_RCIU = 0 MEC2_WAIT_ON_RCIU_READ = 0 MEC2_WAIT_ON_ROQ_DATA = 0