Command: /root/roles -1 1 Driver vendor: X.Org Device vendor: AMD Device name: AMD RAVEN (DRM 3.27.0, 4.20.0-rc1+, LLVM 7.0.0) pipe = 0x12cb900 time before (API call) = 189.996315s time after (driver done) = 189.998462s draw_info: {index_size = 0, has_user_indices = 0, mode = triangle_strip, start = 0, count = 0, start_instance = 0, instance_count = 1, drawid = 0, vertices_per_patch = 3, index_bias = 0, min_index = 0, max_index = 4294967295, primitive_restart = 0, count_from_stream_output = NULL, indirect->offset = 0, indirect->stride = 16, indirect->draw_count = 1, indirect->indirect_draw_count_offset = 0, indirect->buffer = 0x7f8fbc023800, indirect->indirect_draw_count = NULL, } indirect->buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 1536, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 0, flags = 3, } vertex_buffer 0: {stride = 16, is_user_buffer = 0, buffer_offset = 0, buffer.resource = 0x7f8fbc02c650, } buffer.resource: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 1536, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 0, flags = 3, } num vertex elements = 3 vertex_element 0: {src_offset = 0, instance_divisor = 1, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_FLOAT, } vertex_element 1: {src_offset = 8, instance_divisor = 1, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, } vertex_element 2: {src_offset = 12, instance_divisor = 1, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, } num stream output targets = 0 begin shader: VERTEX shader_state: {tokens = " VERT PROPERTY NEXT_SHADER FRAG DCL IN[0] DCL IN[1] DCL IN[2] DCL SV[0], VERTEXID DCL OUT[0], POSITION DCL OUT[1].xy, GENERIC[0] DCL OUT[2].x, GENERIC[1] DCL BUFFER[8] DCL CONST[0][0] DCL CONST[1][0..260] DCL TEMP[0..50], LOCAL IMM[0] INT32 {1, 0, 0, 0} IMM[1] UINT32 {0, 192, 4, 64} IMM[2] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} IMM[3] UINT32 {80, 96, 112, 128} IMM[4] UINT32 {16, 32, 48, 0} 0: UADD OUT[2].x, CONST[0][0].xxxx, IN[1].xxxx 1: ISHR TEMP[0].x, SV[0].xxxx, IMM[0].xxxx 2: I2F TEMP[1].x, TEMP[0].xxxx 3: AND TEMP[2].x, SV[0].xxxx, IMM[0].xxxx 4: I2F TEMP[3].x, TEMP[2].xxxx 5: MOV TEMP[1].y, TEMP[3].xxxx 6: USLT TEMP[4].x, IMM[1].xxxx, IN[2].xxxx 7: UCMP TEMP[5].x, TEMP[4].xxxx, TEMP[3].xxxx, TEMP[5] 8: NOT TEMP[6].x, TEMP[4].xxxx 9: ADD TEMP[7].x, IMM[2].xxxx, -TEMP[3].xxxx 10: UCMP TEMP[5].x, TEMP[6].xxxx, TEMP[7].xxxx, TEMP[5] 11: MOV TEMP[8].x, TEMP[1].xxxx 12: MOV TEMP[8].y, TEMP[5].xxxx 13: MOV OUT[1].xy, TEMP[8].xyxx 14: MUL TEMP[9].xy, TEMP[1].xyyy, IN[0].xyyy 15: LOAD TEMP[10].x, CONSTBUF[1], IMM[1].xxxx 16: LOAD TEMP[11].x, CONSTBUF[1], IMM[1].zzzz 17: UMUL TEMP[12].x, TEMP[11].xxxx, IMM[1].wwww 18: UMAD TEMP[13].x, TEMP[10].xxxx, IMM[1].yyyy, TEMP[12].xxxx 19: UADD TEMP[14].x, TEMP[13].xxxx, IMM[3].xxxx 20: LOAD TEMP[15], CONSTBUF[1], TEMP[14].xxxx 21: UADD TEMP[16].x, TEMP[13].xxxx, IMM[3].yyyy 22: LOAD TEMP[17], CONSTBUF[1], TEMP[16].xxxx 23: UADD TEMP[18].x, TEMP[13].xxxx, IMM[3].zzzz 24: LOAD TEMP[19], CONSTBUF[1], TEMP[18].xxxx 25: UADD TEMP[20].x, TEMP[13].xxxx, IMM[3].wwww 26: LOAD TEMP[21], CONSTBUF[1], TEMP[20].xxxx 27: LOAD TEMP[22].x, CONSTBUF[1], IMM[1].xxxx 28: UMUL TEMP[23].x, TEMP[22].xxxx, IMM[1].yyyy 29: UADD TEMP[24].x, TEMP[23].xxxx, IMM[4].xxxx 30: LOAD TEMP[25], CONSTBUF[1], TEMP[24].xxxx 31: UADD TEMP[26].x, TEMP[23].xxxx, IMM[4].yyyy 32: LOAD TEMP[27], CONSTBUF[1], TEMP[26].xxxx 33: UADD TEMP[28].x, TEMP[23].xxxx, IMM[4].zzzz 34: LOAD TEMP[29], CONSTBUF[1], TEMP[28].xxxx 35: UADD TEMP[30].x, TEMP[23].xxxx, IMM[1].wwww 36: LOAD TEMP[31], CONSTBUF[1], TEMP[30].xxxx 37: UMUL TEMP[32].x, OUT[2].xxxx, IMM[3].yyyy 38: LOAD TEMP[33], BUFFER[8], TEMP[32].xxxx, RESTRICT 39: UADD TEMP[34].x, TEMP[32].xxxx, IMM[4].xxxx 40: LOAD TEMP[35], BUFFER[8], TEMP[34].xxxx, RESTRICT 41: UADD TEMP[36].x, TEMP[32].xxxx, IMM[4].yyyy 42: LOAD TEMP[37], BUFFER[8], TEMP[36].xxxx, RESTRICT 43: UADD TEMP[38].x, TEMP[32].xxxx, IMM[4].zzzz 44: LOAD TEMP[39], BUFFER[8], TEMP[38].xxxx, RESTRICT 45: MUL TEMP[40], TEMP[33], TEMP[9].xxxx 46: MAD TEMP[41], TEMP[35], TEMP[9].yyyy, TEMP[40] 47: MAD TEMP[42], TEMP[37], IMM[2].yyyy, TEMP[41] 48: MAD TEMP[43], TEMP[39], IMM[2].xxxx, TEMP[42] 49: MUL TEMP[44], TEMP[25], TEMP[43].xxxx 50: MAD TEMP[45], TEMP[27], TEMP[43].yyyy, TEMP[44] 51: MAD TEMP[46], TEMP[29], TEMP[43].zzzz, TEMP[45] 52: MAD TEMP[47], TEMP[31], TEMP[43].wwww, TEMP[46] 53: MUL TEMP[48], TEMP[15], TEMP[47].xxxx 54: MAD TEMP[49], TEMP[17], TEMP[47].yyyy, TEMP[48] 55: MAD TEMP[50], TEMP[19], TEMP[47].zzzz, TEMP[49] 56: MAD OUT[0], TEMP[21], TEMP[47].wwww, TEMP[50] 57: END ", } constant_buffer 0: {buffer = NULL, buffer_offset = 0, buffer_size = 16, user_buffer = 0x7f8fbc592a40, } constant_buffer 1: {buffer = 0x7f8fbc7e7840, buffer_offset = 0, buffer_size = 4016, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 4016, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 0, flags = 0, } shader_buffer 8: {buffer = 0x7f8fbc0505e0, buffer_offset = 0, buffer_size = 9216, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 9216, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 0, flags = 3, } end shader: VERTEX viewport_state 0: {scale = {960, 540, 0.5, }, translate = {960, 540, 0.5, }, } rasterizer_state: {flatshade = 0, light_twoside = 0, clamp_vertex_color = 0, clamp_fragment_color = 0, front_ccw = 0, cull_face = 2, fill_front = 0, fill_back = 0, offset_point = 0, offset_line = 0, offset_tri = 0, scissor = 0, poly_smooth = 0, poly_stipple_enable = 0, point_smooth = 0, sprite_coord_enable = 0, sprite_coord_mode = 1, point_quad_rasterization = 1, point_tri_clip = 0, point_size_per_vertex = 0, multisample = 0, line_smooth = 0, line_stipple_enable = 0, line_stipple_factor = 0, line_stipple_pattern = 65535, line_last_pixel = 0, flatshade_first = 0, half_pixel_center = 1, bottom_edge_rule = 0, rasterizer_discard = 0, depth_clip = 1, clip_halfz = 0, clip_plane_enable = 0, line_width = 1, point_size = 1, offset_units = 0, offset_scale = 0, offset_clamp = 0, } begin shader: FRAGMENT shader_state: {tokens = " FRAG DCL IN[0].xy, GENERIC[0], PERSPECTIVE DCL IN[1].x, GENERIC[1], CONSTANT DCL SV[0], POSITION DCL OUT[0], COLOR DCL BUFFER[8] DCL CONST[0][0] DCL CONST[1][0..260] DCL TEMP[0] DCL TEMP[1..16], LOCAL IMM[0] UINT32 {96, 80, 64, 0} IMM[1] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} IMM[2] UINT32 {16, 3856, 88, 0} 0: MOV TEMP[0], SV[0] 1: MAD TEMP[0].y, SV[0], CONST[0][0].xxxx, CONST[0][0].yyyy 2: UMAD TEMP[1].x, IN[1].xxxx, IMM[0].xxxx, IMM[0].yyyy 3: LOAD TEMP[2].xy, BUFFER[8], TEMP[1].xxxx, RESTRICT 4: MOV TEMP[3].xy, TEMP[2].xyxy 5: UMAD TEMP[4].x, IN[1].xxxx, IMM[0].xxxx, IMM[0].zzzz 6: LOAD TEMP[5], BUFFER[8], TEMP[4].xxxx, RESTRICT 7: MOV TEMP[6].xy, IN[0].xyyy 8: TEX TEMP[7], TEMP[6], TEMP[3].xyxy, 2D 9: MUL OUT[0], TEMP[7], TEMP[5] 10: MUL OUT[0].xyz, OUT[0].xyzz, OUT[0].wwww 11: FSLT TEMP[8].x, IMM[1].xxxx, OUT[0].wwww 12: UIF TEMP[8].xxxx 13: LOAD TEMP[9].x, CONSTBUF[1], IMM[0].wwww 14: UMAD TEMP[10].x, TEMP[9].xxxx, IMM[2].xxxx, IMM[2].yyyy 15: LOAD TEMP[11].xy, CONSTBUF[1], TEMP[10].xxxx 16: MOV TEMP[12].xy, TEMP[11].xyxy 17: UMAD TEMP[13].x, IN[1].xxxx, IMM[0].xxxx, IMM[2].zzzz 18: LOAD TEMP[14].x, BUFFER[8], TEMP[13].xxxx, RESTRICT 19: F2I TEMP[15].xy, TEMP[0].xyyy 20: ATOMUMAX TEMP[16].x, TEMP[12].xyxy, TEMP[15].xyxx, TEMP[14].xxxx, 2D 21: ENDIF 22: END ", } constant_buffer 0: {buffer = NULL, buffer_offset = 0, buffer_size = 16, user_buffer = 0x7f8fbc629b30, } constant_buffer 1: {buffer = 0x7f8fbc7e7840, buffer_offset = 0, buffer_size = 4016, user_buffer = NULL, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 4016, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 0, flags = 0, } shader_buffer 8: {buffer = 0x7f8fbc0505e0, buffer_offset = 0, buffer_size = 9216, } buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 9216, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 0, flags = 3, } end shader: FRAGMENT depth_stencil_alpha_state: {depth = {enabled = 0, }, stencil = {{enabled = 0, }, {enabled = 0, }, }, alpha = {enabled = 0, }, } stencil_ref: {ref_value = {0, 0, }, } blend_state: {dither = 1, alpha_to_coverage = 0, alpha_to_one = 0, logicop_enable = 0, independent_blend_enable = 0, rt = {{blend_enable = 1, rgb_func = add, rgb_src_factor = one, rgb_dst_factor = inv_src_alpha, alpha_func = add, alpha_src_factor = one, alpha_dst_factor = inv_src_alpha, colormask = 15, }, }, } blend_color: {color = {0, 0, 0, 0, }, } min_samples = 1 sample_mask = 0xffffffff framebuffer_state: {width = 232, height = 238, samples = 0, layers = 0, nr_cbufs = 1, cbufs = {0x7f8fbfa73980, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, zsbuf = NULL, } cbufs[0]: surface: {format = PIPE_FORMAT_R8G8B8A8_UNORM, width = 232, height = 238, texture = 0x7f8fbe0366c0, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, } resource: {target = 2d, format = PIPE_FORMAT_R8G8B8A8_UNORM, width0 = 232, height0 = 238, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 10, flags = 4, } ***************************************************************************** Context Log: ------------------ IB begin ------------------ c0024600 EVENT_WRITE: 00000115 VGT_EVENT_INITIATOR <- EVENT_TYPE = ZPASS_DONE EVENT_INDEX <- 1 INV_L2 <- 0 00000600 ADDRESS_LO <- 1536 (0x00000600) ffff8001 ADDRESS_HI <- 0xffff8001 c0064900 RELEASE_MEM: 00000528 VGT_EVENT_INITIATOR <- EVENT_TYPE = BOTTOM_OF_PIPE_TS EVENT_INDEX <- 5 TCL1_VOL_ACTION_ENA <- 0 TC_VOL_ACTION_ENA <- 0 TC_WB_ACTION_ENA <- 0 TCL1_ACTION_ENA <- 0 TC_ACTION_ENA <- 0 TC_NC_ACTION_ENA <- 0 TC_WC_ACTION_ENA <- 0 TC_MD_ACTION_ENA <- 0 23000000 DST_SEL <- 0 INT_SEL <- 3 DATA_SEL <- 1 0016125c ADDRESS_LO <- 0x0016125c ffff8001 ADDRESS_HI <- 0xffff8001 80000000 DATA_LO <- -0.0f (0x80000000) 00000000 DATA_HI <- 0 00000000 CTXID <- 0 c0055000 DMA_DATA: 80200000 DMA_DATA_WORD0 <- CP_SYNC = 1 SRC_SEL = SRC_ADDR DST_SEL = NOWHERE ENGINE = ME 00000000 SRC_ADDR_LO <- 0 00000000 SRC_ADDR_HI <- 0 00000000 DST_ADDR_LO <- 0 00000000 DST_ADDR_HI <- 0 00000000 COMMAND <- BYTE_COUNT_GFX6 = 0 BYTE_COUNT_GFX9 = 0 DISABLE_WR_CONFIRM_GFX6 = 0 SRC_SWAP = NONE DST_SWAP = NONE SAS = MEMORY DAS = MEMORY SAIC = INCREMENT DAIC = INCREMENT RAW_WAIT = 0 DISABLE_WR_CONFIRM_GFX9 = 0 c0004600 EVENT_WRITE: 00000410 VGT_EVENT_INITIATOR <- EVENT_TYPE = PS_PARTIAL_FLUSH EVENT_INDEX <- 4 INV_L2 <- 0 c0004200 PFP_SYNC_ME: 00000000 c0033700 WRITE_DATA: 00100100 CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC 00066600 DST_ADDR_LO <- 0x00066600 ffff8001 DST_ADDR_HI <- 0xffff8001 00000003 c0001000 NOP: Trace point ID: 3 !!!!! This is the last trace point that was reached by the CP !!!!! cafe0003 ------------------- IB end ------------------- Flushing. Time: 189.996259s Buffer list (in units of pages = 4kB):  Size VM start page VM end page Usage 32 0xFFFF800000000 0xFFFF800000020 SHADER_RINGS 7840 -- hole -- 32 0xFFFF800001EC0 0xFFFF800001EE0 DESCRIPTORS 32 0xFFFF800001EE0 0xFFFF800001F00 CONST_BUFFER 32 0xFFFF800001F00 0xFFFF800001F20 DESCRIPTORS, SHADER_RINGS 1040608 -- hole -- 32 0xFFFF800100000 0xFFFF800100020 QUERY, IB2 32 0xFFFF800100020 0xFFFF800100040 IB1 32 0xFFFF800100040 0xFFFF800100060 BORDER_COLORS 32 0xFFFF800100060 0xFFFF800100080 TRACE 96 -- hole -- 32 0xFFFF8001000E0 0xFFFF800100100 SHADER_BINARY 19 0xFFFF800100100 0xFFFF800100113 SAMPLER_TEXTURE 20 -- hole -- 19 0xFFFF800100127 0xFFFF80010013A SAMPLER_TEXTURE 6 -- hole -- 32 0xFFFF800100140 0xFFFF800100160 SHADER_BINARY 32 0xFFFF800100160 0xFFFF800100180 QUERY 95 0xFFFF800100180 0xFFFF8001001DF DRAW_INDIRECT 801 -- hole -- 190 0xFFFF800100500 0xFFFF8001005BE VERTEX_BUFFER 4198 -- hole -- 19 0xFFFF800101624 0xFFFF800101637 SAMPLER_TEXTURE 20 -- hole -- 19 0xFFFF80010164B 0xFFFF80010165E SAMPLER_TEXTURE 20 -- hole -- 19 0xFFFF800101672 0xFFFF800101685 SAMPLER_TEXTURE 20 -- hole -- 19 0xFFFF800101699 0xFFFF8001016AC SAMPLER_TEXTURE 20 -- hole -- 19 0xFFFF8001016C0 0xFFFF8001016D3 SAMPLER_TEXTURE 29 -- hole -- 80 0xFFFF8001016F0 0xFFFF800101740 SAMPLER_TEXTURE 96 -- hole -- 32 0xFFFF8001017A0 0xFFFF8001017C0 CONST_BUFFER 1088 -- hole -- 450 0xFFFF800101C00 0xFFFF800101DC2 SAMPLER_TEXTURE 22 0xFFFF800101DC2 0xFFFF800101DD8 SAMPLER_TEXTURE 8 -- hole -- 80 0xFFFF800101DE0 0xFFFF800101E30 SAMPLER_TEXTURE 80 0xFFFF800101E30 0xFFFF800101E80 SAMPLER_TEXTURE, COLOR_BUFFER 80 0xFFFF800101E80 0xFFFF800101ED0 SAMPLER_TEXTURE 80 0xFFFF800101ED0 0xFFFF800101F20 SAMPLER_TEXTURE 80 0xFFFF800101F20 0xFFFF800101F70 SAMPLER_TEXTURE 656 -- hole -- 450 0xFFFF800102200 0xFFFF8001023C2 SAMPLER_TEXTURE 22 0xFFFF8001023C2 0xFFFF8001023D8 SAMPLER_TEXTURE 5664 -- hole -- 450 0xFFFF8001039F8 0xFFFF800103BBA SAMPLER_TEXTURE 1446 -- hole -- 144 0xFFFF800104160 0xFFFF8001041F0 SAMPLER_TEXTURE 112 -- hole -- 144 0xFFFF800104260 0xFFFF8001042F0 SAMPLER_TEXTURE 144 -- hole -- 32 0xFFFF800104380 0xFFFF8001043A0 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF8001043C0 0xFFFF8001043E0 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF800104400 0xFFFF800104420 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF800104440 0xFFFF800104460 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF800104480 0xFFFF8001044A0 SAMPLER_TEXTURE 64 -- hole -- 32 0xFFFF8001044E0 0xFFFF800104500 SAMPLER_TEXTURE 32 0xFFFF800104500 0xFFFF800104520 SAMPLER_TEXTURE 416 0xFFFF800104520 0xFFFF8001046C0 SAMPLER_TEXTURE 325 -- hole -- 22 0xFFFF800104805 0xFFFF80010481B SAMPLER_TEXTURE 5 -- hole -- 32 0xFFFF800104820 0xFFFF800104840 SAMPLER_TEXTURE 32 -- hole -- 336 0xFFFF800104860 0xFFFF8001049B0 SAMPLER_TEXTURE 259 -- hole -- 81 0xFFFF800104AB3 0xFFFF800104B04 SAMPLER_TEXTURE 38652 -- hole -- 570 0xFFFF80010E200 0xFFFF80010E43A SHADER_RW_BUFFER 3382 -- hole -- 32 0xFFFF80010F170 0xFFFF80010F190 SAMPLER_TEXTURE 48 -- hole -- 32 0xFFFF80010F1C0 0xFFFF80010F1E0 SAMPLER_TEXTURE 880 -- hole -- 80 0xFFFF80010F550 0xFFFF80010F5A0 SAMPLER_TEXTURE 2448 -- hole -- 32 0xFFFF80010FF30 0xFFFF80010FF50 SAMPLER_TEXTURE 80 -- hole -- 96 0xFFFF80010FFA0 0xFFFF800110000 SAMPLER_TEXTURE 4032 -- hole -- 32 0xFFFF800110FC0 0xFFFF800110FE0 SAMPLER_TEXTURE 2560 -- hole -- 32 0xFFFF8001119E0 0xFFFF800111A00 SAMPLER_TEXTURE 2176 0xFFFF800111A00 0xFFFF800112280 SAMPLER_TEXTURE 272 0xFFFF800112280 0xFFFF800112390 SAMPLER_TEXTURE 85 0xFFFF800112390 0xFFFF8001123E5 SAMPLER_TEXTURE 22 0xFFFF8001123E5 0xFFFF8001123FB SAMPLER_TEXTURE 2537 -- hole -- 22 0xFFFF800112DE4 0xFFFF800112DFA SAMPLER_TEXTURE 2031 -- hole -- 22 0xFFFF8001135E9 0xFFFF8001135FF SAMPLER_TEXTURE 902 -- hole -- 81 0xFFFF800113985 0xFFFF8001139D6 SAMPLER_TEXTURE 42 -- hole -- 656 0xFFFF800113A00 0xFFFF800113C90 SAMPLER_TEXTURE 272 -- hole -- 96 0xFFFF800113DA0 0xFFFF800113E00 SAMPLER_TEXTURE 1168 -- hole -- 272 0xFFFF800114290 0xFFFF8001143A0 SAMPLER_TEXTURE 64 0xFFFF8001143A0 0xFFFF8001143E0 SAMPLER_TEXTURE 32 0xFFFF8001143E0 0xFFFF800114400 SAMPLER_TEXTURE 2560 -- hole -- 2176 0xFFFF800114E00 0xFFFF800115680 SAMPLER_TEXTURE 256 -- hole -- 64 0xFFFF800115780 0xFFFF8001157C0 SAMPLER_TEXTURE 40 0xFFFF8001157C0 0xFFFF8001157E8 SAMPLER_TEXTURE 19 0xFFFF8001157E8 0xFFFF8001157FB SAMPLER_TEXTURE 5269 -- hole -- 208 0xFFFF800116C90 0xFFFF800116D60 SAMPLER_TEXTURE 160 0xFFFF800116D60 0xFFFF800116E00 SAMPLER_TEXTURE 656 0xFFFF800116E00 0xFFFF800117090 SAMPLER_TEXTURE 208 -- hole -- 160 0xFFFF800117160 0xFFFF800117200 SAMPLER_TEXTURE 1168 -- hole -- 256 0xFFFF800117690 0xFFFF800117790 SAMPLER_TEXTURE 112 0xFFFF800117790 0xFFFF800117800 SAMPLER_TEXTURE 1216 -- hole -- 256 0xFFFF800117CC0 0xFFFF800117DC0 SAMPLER_TEXTURE 64 0xFFFF800117DC0 0xFFFF800117E00 SAMPLER_TEXTURE 1040 0xFFFF800117E00 0xFFFF800118210 SAMPLER_TEXTURE 176 -- hole -- 256 0xFFFF8001182C0 0xFFFF8001183C0 SAMPLER_TEXTURE 42 -- hole -- 19 0xFFFF8001183EA 0xFFFF8001183FD SAMPLER_TEXTURE 1043 -- hole -- 416 0xFFFF800118810 0xFFFF8001189B0 SAMPLER_TEXTURE 1057 -- hole -- 40 0xFFFF800118DD1 0xFFFF800118DF9 SAMPLER_TEXTURE 1383 -- hole -- 112 0xFFFF800119360 0xFFFF8001193D0 SAMPLER_TEXTURE 48 -- hole -- 1040 0xFFFF800119400 0xFFFF800119810 SAMPLER_TEXTURE 336 0xFFFF800119810 0xFFFF800119960 SAMPLER_TEXTURE 160 0xFFFF800119960 0xFFFF800119A00 SAMPLER_TEXTURE 1040 -- hole -- 256 0xFFFF800119E10 0xFFFF800119F10 SAMPLER_TEXTURE 2288 -- hole -- 784 0xFFFF80011A800 0xFFFF80011AB10 SAMPLER_TEXTURE 160 0xFFFF80011AB10 0xFFFF80011ABB0 SAMPLER_TEXTURE 864 -- hole -- 112 0xFFFF80011AF10 0xFFFF80011AF80 SAMPLER_TEXTURE 112 0xFFFF80011AF80 0xFFFF80011AFF0 SAMPLER_TEXTURE 704 -- hole -- 256 0xFFFF80011B2B0 0xFFFF80011B3B0 SAMPLER_TEXTURE 1120 -- hole -- 256 0xFFFF80011B810 0xFFFF80011B910 SAMPLER_TEXTURE 219 -- hole -- 19 0xFFFF80011B9EB 0xFFFF80011B9FE SAMPLER_TEXTURE 2 -- hole -- 656 0xFFFF80011BA00 0xFFFF80011BC90 SAMPLER_TEXTURE 160 0xFFFF80011BC90 0xFFFF80011BD30 SAMPLER_TEXTURE 128 -- hole -- 64 0xFFFF80011BDB0 0xFFFF80011BDF0 SAMPLER_TEXTURE 16 -- hole -- 656 0xFFFF80011BE00 0xFFFF80011C090 SAMPLER_TEXTURE 160 0xFFFF80011C090 0xFFFF80011C130 SAMPLER_TEXTURE 111 -- hole -- 40 0xFFFF80011C19F 0xFFFF80011C1C7 SAMPLER_TEXTURE 57 -- hole -- 112 0xFFFF80011C200 0xFFFF80011C270 SAMPLER_TEXTURE 80 -- hole -- 112 0xFFFF80011C2C0 0xFFFF80011C330 SAMPLER_TEXTURE 80 -- hole -- 256 0xFFFF80011C380 0xFFFF80011C480 SAMPLER_TEXTURE 224 -- hole -- 160 0xFFFF80011C560 0xFFFF80011C600 SAMPLER_TEXTURE 128 -- hole -- 160 0xFFFF80011C680 0xFFFF80011C720 SAMPLER_TEXTURE 112 -- hole -- 64 0xFFFF80011C790 0xFFFF80011C7D0 SAMPLER_TEXTURE 42 -- hole -- 40 0xFFFF80011C7FA 0xFFFF80011C822 SAMPLER_TEXTURE 46 -- hole -- 112 0xFFFF80011C850 0xFFFF80011C8C0 SAMPLER_TEXTURE 80 -- hole -- 112 0xFFFF80011C910 0xFFFF80011C980 SAMPLER_TEXTURE 80 -- hole -- 256 0xFFFF80011C9D0 0xFFFF80011CAD0 SAMPLER_TEXTURE 224 -- hole -- 160 0xFFFF80011CBB0 0xFFFF80011CC50 SAMPLER_TEXTURE 128 -- hole -- 160 0xFFFF80011CCD0 0xFFFF80011CD70 SAMPLER_TEXTURE 112 -- hole -- 64 0xFFFF80011CDE0 0xFFFF80011CE20 SAMPLER_TEXTURE 42 -- hole -- 40 0xFFFF80011CE4A 0xFFFF80011CE72 SAMPLER_TEXTURE 46 -- hole -- 112 0xFFFF80011CEA0 0xFFFF80011CF10 SAMPLER_TEXTURE 80 -- hole -- 112 0xFFFF80011CF60 0xFFFF80011CFD0 SAMPLER_TEXTURE 80 -- hole -- 256 0xFFFF80011D020 0xFFFF80011D120 SAMPLER_TEXTURE 224 -- hole -- 160 0xFFFF80011D200 0xFFFF80011D2A0 SAMPLER_TEXTURE 128 -- hole -- 32 0xFFFF80011D320 0xFFFF80011D340 SAMPLER_TEXTURE 160 0xFFFF80011D340 0xFFFF80011D3E0 SAMPLER_TEXTURE 112 -- hole -- 64 0xFFFF80011D450 0xFFFF80011D490 SAMPLER_TEXTURE 42 -- hole -- 40 0xFFFF80011D4BA 0xFFFF80011D4E2 SAMPLER_TEXTURE 46 -- hole -- 112 0xFFFF80011D510 0xFFFF80011D580 SAMPLER_TEXTURE 80 -- hole -- 112 0xFFFF80011D5D0 0xFFFF80011D640 SAMPLER_TEXTURE 80 -- hole -- 256 0xFFFF80011D690 0xFFFF80011D790 SAMPLER_TEXTURE 272 -- hole -- 32 0xFFFF80011D8A0 0xFFFF80011D8C0 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF80011D8E0 0xFFFF80011D900 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF80011D920 0xFFFF80011D940 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF80011D960 0xFFFF80011D980 SAMPLER_TEXTURE 53 0xFFFF80011D980 0xFFFF80011D9B5 SAMPLER_TEXTURE 75 -- hole -- 2176 0xFFFF80011DA00 0xFFFF80011E280 SAMPLER_TEXTURE 96 0xFFFF80011E280 0xFFFF80011E2E0 SAMPLER_TEXTURE 64 -- hole -- 96 0xFFFF80011E320 0xFFFF80011E380 SAMPLER_TEXTURE 2153 -- hole -- 19 0xFFFF80011EBE9 0xFFFF80011EBFC SAMPLER_TEXTURE 4 -- hole -- 736 0xFFFF80011EC00 0xFFFF80011EEE0 SAMPLER_TEXTURE 96 0xFFFF80011EEE0 0xFFFF80011EF40 SAMPLER_TEXTURE 96 0xFFFF80011EF40 0xFFFF80011EFA0 SAMPLER_TEXTURE 57 -- hole -- 37 0xFFFF80011EFD9 0xFFFF80011EFFE SAMPLER_TEXTURE 610 -- hole -- 96 0xFFFF80011F260 0xFFFF80011F2C0 SAMPLER_TEXTURE 64 -- hole -- 96 0xFFFF80011F300 0xFFFF80011F360 SAMPLER_TEXTURE 64 -- hole -- 96 0xFFFF80011F3A0 0xFFFF80011F400 SAMPLER_TEXTURE 64 -- hole -- 96 0xFFFF80011F440 0xFFFF80011F4A0 SAMPLER_TEXTURE 64 -- hole -- 176 0xFFFF80011F4E0 0xFFFF80011F590 SAMPLER_TEXTURE 112 -- hole -- 176 0xFFFF80011F600 0xFFFF80011F6B0 SAMPLER_TEXTURE 112 -- hole -- 80 0xFFFF80011F720 0xFFFF80011F770 SAMPLER_TEXTURE 94 -- hole -- 37 0xFFFF80011F7CE 0xFFFF80011F7F3 SAMPLER_TEXTURE 45 -- hole -- 32 0xFFFF80011F820 0xFFFF80011F840 SAMPLER_TEXTURE 32 -- hole -- 64 0xFFFF80011F860 0xFFFF80011F8A0 SAMPLER_TEXTURE 48 -- hole -- 48 0xFFFF80011F8D0 0xFFFF80011F900 SAMPLER_TEXTURE 48 0xFFFF80011F900 0xFFFF80011F930 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF80011F950 0xFFFF80011F980 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF80011F9A0 0xFFFF80011F9D0 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF80011F9F0 0xFFFF80011FA20 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF80011FA40 0xFFFF80011FA70 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF80011FA90 0xFFFF80011FAC0 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF80011FAE0 0xFFFF80011FB10 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF80011FB30 0xFFFF80011FB60 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF80011FB80 0xFFFF80011FBB0 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF80011FBD0 0xFFFF80011FC00 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF80011FC20 0xFFFF80011FC50 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF80011FC70 0xFFFF80011FCA0 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF80011FCC0 0xFFFF80011FCF0 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF80011FD10 0xFFFF80011FD30 SAMPLER_TEXTURE 32 0xFFFF80011FD30 0xFFFF80011FD50 SAMPLER_TEXTURE 48 -- hole -- 32 0xFFFF80011FD80 0xFFFF80011FDA0 SAMPLER_TEXTURE 32 0xFFFF80011FDA0 0xFFFF80011FDC0 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF80011FDE0 0xFFFF80011FE00 SAMPLER_TEXTURE 32 0xFFFF80011FE00 0xFFFF80011FE20 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF80011FE40 0xFFFF80011FE60 SAMPLER_TEXTURE 32 0xFFFF80011FE60 0xFFFF80011FE80 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF80011FEA0 0xFFFF80011FEC0 SAMPLER_TEXTURE 32 0xFFFF80011FEC0 0xFFFF80011FEE0 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF80011FF00 0xFFFF80011FF20 SAMPLER_TEXTURE 32 0xFFFF80011FF20 0xFFFF80011FF40 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF80011FF60 0xFFFF80011FF80 SAMPLER_TEXTURE 32 0xFFFF80011FF80 0xFFFF80011FFA0 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF80011FFC0 0xFFFF80011FFE0 SAMPLER_TEXTURE 416 0xFFFF80011FFE0 0xFFFF800120180 SAMPLER_TEXTURE 400 -- hole -- 48 0xFFFF800120310 0xFFFF800120340 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF800120360 0xFFFF800120390 SAMPLER_TEXTURE 32 -- hole -- 48 0xFFFF8001203B0 0xFFFF8001203E0 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF800120400 0xFFFF800120420 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF800120440 0xFFFF800120460 SAMPLER_TEXTURE 32 0xFFFF800120460 0xFFFF800120480 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF8001204A0 0xFFFF8001204C0 SAMPLER_TEXTURE 32 0xFFFF8001204C0 0xFFFF8001204E0 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF800120500 0xFFFF800120520 SAMPLER_TEXTURE 32 0xFFFF800120520 0xFFFF800120540 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF800120560 0xFFFF800120580 SAMPLER_TEXTURE 32 0xFFFF800120580 0xFFFF8001205A0 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF8001205C0 0xFFFF8001205E0 SAMPLER_TEXTURE 32 0xFFFF8001205E0 0xFFFF800120600 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF800120620 0xFFFF800120640 SAMPLER_TEXTURE 32 0xFFFF800120640 0xFFFF800120660 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF800120680 0xFFFF8001206A0 SAMPLER_TEXTURE 32 0xFFFF8001206A0 0xFFFF8001206C0 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF8001206E0 0xFFFF800120700 SAMPLER_TEXTURE 32 0xFFFF800120700 0xFFFF800120720 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF800120740 0xFFFF800120760 SAMPLER_TEXTURE 160 0xFFFF800120760 0xFFFF800120800 SAMPLER_TEXTURE 160 -- hole -- 168 0xFFFF8001208A0 0xFFFF800120948 SAMPLER_TEXTURE 146 -- hole -- 142 0xFFFF8001209DA 0xFFFF800120A68 SAMPLER_TEXTURE 120 -- hole -- 32 0xFFFF800120AE0 0xFFFF800120B00 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF800120B20 0xFFFF800120B40 SAMPLER_TEXTURE 32 0xFFFF800120B40 0xFFFF800120B60 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF800120B80 0xFFFF800120BA0 SAMPLER_TEXTURE 32 -- hole -- 32 0xFFFF800120BC0 0xFFFF800120BE0 SAMPLER_TEXTURE 32 -- hole -- 912 0xFFFF800120C00 0xFFFF800120F90 SAMPLER_TEXTURE 20 -- hole -- 19 0xFFFF800120FA4 0xFFFF800120FB7 SAMPLER_TEXTURE 20 -- hole -- 19 0xFFFF800120FCB 0xFFFF800120FDE SAMPLER_TEXTURE 823 -- hole -- 19 0xFFFF800121315 0xFFFF800121328 SAMPLER_TEXTURE 20 -- hole -- 19 0xFFFF80012133C 0xFFFF80012134F SAMPLER_TEXTURE 20 -- hole -- 19 0xFFFF800121363 0xFFFF800121376 SAMPLER_TEXTURE 20 -- hole -- 19 0xFFFF80012138A 0xFFFF80012139D SAMPLER_TEXTURE 20 -- hole -- 19 0xFFFF8001213B1 0xFFFF8001213C4 SAMPLER_TEXTURE 60 -- hole -- 528 0xFFFF800121400 0xFFFF800121610 SAMPLER_TEXTURE 432 -- hole -- 448 0xFFFF8001217C0 0xFFFF800121980 SAMPLER_TEXTURE 640 -- hole -- 592 0xFFFF800121C00 0xFFFF800121E50 SAMPLER_TEXTURE 1456 -- hole -- 2176 0xFFFF800122400 0xFFFF800122C80 SAMPLER_TEXTURE 2432 -- hole -- 2176 0xFFFF800123600 0xFFFF800123E80 SAMPLER_TEXTURE 2432 -- hole -- 2176 0xFFFF800124800 0xFFFF800125080 SAMPLER_TEXTURE 2432 -- hole -- 2176 0xFFFF800125A00 0xFFFF800126280 SAMPLER_TEXTURE 2432 -- hole -- 2176 0xFFFF800126C00 0xFFFF800127480 SAMPLER_TEXTURE 2432 -- hole -- 2176 0xFFFF800127E00 0xFFFF800128680 SAMPLER_TEXTURE Note: The holes represent memory not used by the IB. Other buffers can still be allocated there. ------------------ IB2: Init config begin ------------------ c0012800 CONTEXT_CONTROL: 80000000 80000000 c0001200 CLEAR_STATE: 00000000 c0016900 SET_CONTEXT_REG: 00000286 42800000 VGT_HOS_MAX_TESS_LEVEL <- 64.0f (0x42800000) c0016900 SET_CONTEXT_REG: 000002a8 00000001 VGT_INSTANCE_STEP_RATE_0 <- 1 c0037900 SET_UCONFIG_REG: 00000248 ffffffff VGT_MAX_VTX_INDX <- 0xffffffff 00000000 VGT_MIN_VTX_INDX <- 0 00000000 VGT_INDX_OFFSET <- 0 c0017600 SET_SH_REG: 00000107 ffff003f SPI_SHADER_PGM_RSRC3_HS <- WAVE_LIMIT = 63 (0x3f) LOCK_LOW_THRESHOLD = 0 SIMD_DISABLE = 0 CU_EN = 0xffff c0017600 SET_SH_REG: 00000087 003fffff SPI_SHADER_PGM_RSRC3_GS <- CU_EN = 0xffff WAVE_LIMIT = 63 (0x3f) LOCK_LOW_THRESHOLD = 0 SIMD_DISABLE = 0 c0027600 SET_SH_REG: 00000046 003fffff SPI_SHADER_PGM_RSRC3_VS <- CU_EN = 0xffff WAVE_LIMIT = 63 (0x3f) LOCK_LOW_THRESHOLD = 0 SIMD_DISABLE = 0 00000002 SPI_SHADER_LATE_ALLOC_VS <- LIMIT = 2 c0017600 SET_SH_REG: 00000007 003fffff SPI_SHADER_PGM_RSRC3_PS <- CU_EN = 0xffff WAVE_LIMIT = 63 (0x3f) LOCK_LOW_THRESHOLD = 0 SIMD_DISABLE = 0 c0016900 SET_CONTEXT_REG: 000002d4 700b0b20 VGT_TESS_DISTRIBUTION <- ACCUM_ISOLINE = 32 (0x20) ACCUM_TRI = 11 (0x0b) ACCUM_QUAD = 11 (0x0b) DONUT_SPLIT = 16 (0x10) TRAP_SPLIT = 3 c0026900 SET_CONTEXT_REG: 00000020 01000500 TA_BC_BASE_ADDR <- 0x01000500 00000080 TA_BC_BASE_ADDR_HI <- ADDRESS = 128 (0x80) c0026900 SET_CONTEXT_REG: 00000312 03ff0080 PA_SC_BINNER_CNTL_1 <- MAX_ALLOC_COUNT = 128 (0x0080) MAX_PRIM_PER_BATCH = 1023 (0x03ff) 00100000 PA_SC_CONSERVATIVE_RASTERIZATION_CNTL <- OVER_RAST_ENABLE = 0 OVER_RAST_SAMPLE_SELECT = 0 UNDER_RAST_ENABLE = 0 UNDER_RAST_SAMPLE_SELECT = 0 PBB_UNCERTAINTY_REGION_ENABLE = 0 ZMM_TRI_EXTENT = 0 ZMM_TRI_OFFSET = 0 OVERRIDE_OVER_RAST_INNER_TO_NORMAL = 0 OVERRIDE_UNDER_RAST_INNER_TO_NORMAL = 0 DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE = 0 UNCERTAINTY_REGION_MODE = 0 OUTER_UNCERTAINTY_EDGERULE_OVERRIDE = 0 INNER_UNCERTAINTY_EDGERULE_OVERRIDE = 0 NULL_SQUAD_AA_MASK_ENABLE = 1 COVERAGE_AA_MASK_ENABLE = 0 PREZ_AA_MASK_ENABLE = 0 POSTZ_AA_MASK_ENABLE = 0 CENTROID_SAMPLE_OVERRIDE = 0 c0017900 SET_UCONFIG_REG: 0000025a 00000000 VGT_INSTANCE_BASE_ID <- 0 ------------------- IB2: Init config end ------------------- ------------------ IB begin ------------------ c0033700 WRITE_DATA: 00100100 CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC 00066800 DST_ADDR_LO <- 0x00066800 ffff8001 DST_ADDR_HI <- 0xffff8001 00000001 c0001000 NOP: Trace point ID: 1 !!!!! This is the last trace point that was reached by the CP !!!!! cafe0001 ------------------- IB end ------------------- ------------------ IB begin ------------------ c0023f00 INDIRECT_BUFFER_CIK: 00000800 IB_BASE_LO <- 2048 (0x00000800) ffff8001 IB_BASE_HI <- 0xffff8001 00000030 CONTROL <- IB_SIZE = 48 (0x00030) CHAIN = 0 VALID = 0 c0024600 EVENT_WRITE: 00000115 VGT_EVENT_INITIATOR <- EVENT_TYPE = ZPASS_DONE EVENT_INDEX <- 1 INV_L2 <- 0 00000600 ADDRESS_LO <- 1536 (0x00000600) ffff8001 ADDRESS_HI <- 0xffff8001 c0064900 RELEASE_MEM: 00000528 VGT_EVENT_INITIATOR <- EVENT_TYPE = BOTTOM_OF_PIPE_TS EVENT_INDEX <- 5 TCL1_VOL_ACTION_ENA <- 0 TC_VOL_ACTION_ENA <- 0 TC_WB_ACTION_ENA <- 0 TCL1_ACTION_ENA <- 0 TC_ACTION_ENA <- 0 TC_NC_ACTION_ENA <- 0 TC_WC_ACTION_ENA <- 0 TC_MD_ACTION_ENA <- 0 23000000 DST_SEL <- 0 INT_SEL <- 3 DATA_SEL <- 1 00161260 ADDRESS_LO <- 0x00161260 ffff8001 ADDRESS_HI <- 0xffff8001 80000000 DATA_LO <- -0.0f (0x80000000) 00000000 DATA_HI <- 0 00000000 CTXID <- 0 c0033700 WRITE_DATA: 40100500 CONTROL <- ENGINE_SEL = PFP WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEM_ASYNC 00161264 DST_ADDR_LO <- 0x00161264 ffff8001 DST_ADDR_HI <- 0xffff8001 80000000 c0004600 EVENT_WRITE: 0000002e VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 c0024600 EVENT_WRITE: 00000115 VGT_EVENT_INITIATOR <- EVENT_TYPE = ZPASS_DONE EVENT_INDEX <- 1 INV_L2 <- 0 00000600 ADDRESS_LO <- 1536 (0x00000600) ffff8001 ADDRESS_HI <- 0xffff8001 c0064900 RELEASE_MEM: 0002852d VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_DATA_TS EVENT_INDEX <- 5 TCL1_VOL_ACTION_ENA <- 0 TC_VOL_ACTION_ENA <- 0 TC_WB_ACTION_ENA <- 1 TCL1_ACTION_ENA <- 0 TC_ACTION_ENA <- 1 TC_NC_ACTION_ENA <- 0 TC_WC_ACTION_ENA <- 0 TC_MD_ACTION_ENA <- 0 23000000 DST_SEL <- 0 INT_SEL <- 3 DATA_SEL <- 1 00000a00 ADDRESS_LO <- 2560 (0x00000a00) ffff8001 ADDRESS_HI <- 0xffff8001 00000242 DATA_LO <- 578 (0x00000242) 00000000 DATA_HI <- 0 00000000 CTXID <- 0 c0053c00 WAIT_REG_MEM: 00000013 OP <- 19 (0x00000013) 00000a00 ADDRESS_LO <- 2560 (0x00000a00) ffff8001 ADDRESS_HI <- 0xffff8001 00000242 REF <- 578 (0x00000242) ffffffff MASK <- 0xffffffff 00000004 POLL_INTERVAL <- 4 c0004200 PFP_SYNC_ME: 00000000 c0055800 ACQUIRE_MEM: 28000000 CP_COHER_CNTL <- TC_NC_ACTION_ENA = 0 TC_WC_ACTION_ENA = 0 TC_INV_METADATA_ACTION_ENA = 0 TCL1_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 TCL1_ACTION_ENA = 0 TC_ACTION_ENA = 0 CB_ACTION_ENA = 0 DB_ACTION_ENA = 0 SH_KCACHE_ACTION_ENA = 1 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 1 SH_KCACHE_WB_ACTION_ENA = 0 ffffffff CP_COHER_SIZE <- 0xffffffff 00ffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) 00000000 CP_COHER_BASE <- 0 00000000 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 0000000a POLL_INTERVAL <- 10 (0x000a) c0004600 EVENT_WRITE: 00000019 VGT_EVENT_INITIATOR <- EVENT_TYPE = PIPELINESTAT_START EVENT_INDEX <- 0 INV_L2 <- 0 c0123700 WRITE_DATA: 00100200 CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = TC_L2 01ed4180 DST_ADDR_LO <- 0x01ed4180 ffff8000 DST_ADDR_HI <- 0xffff8000 0101e300 00a00080 403b40e7 91900fac 001fe000 00000000 00400000 00000000 00000000 00000000 00000000 80000200 90000012 00f00000 c0500000 00000000 c0004200 PFP_SYNC_ME: 00000000 c0055800 ACQUIRE_MEM: 08000000 CP_COHER_CNTL <- TC_NC_ACTION_ENA = 0 TC_WC_ACTION_ENA = 0 TC_INV_METADATA_ACTION_ENA = 0 TCL1_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 TCL1_ACTION_ENA = 0 TC_ACTION_ENA = 0 CB_ACTION_ENA = 0 DB_ACTION_ENA = 0 SH_KCACHE_ACTION_ENA = 1 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 ffffffff CP_COHER_SIZE <- 0xffffffff 00ffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) 00000000 CP_COHER_BASE <- 0 00000000 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 0000000a POLL_INTERVAL <- 10 (0x000a) c0055000 DMA_DATA: 60200000 DMA_DATA_WORD0 <- CP_SYNC = 0 SRC_SEL = SRC_ADDR_TC_L2 DST_SEL = NOWHERE ENGINE = ME 020a0000 SRC_ADDR_LO <- 0x020a0000 ffff8001 SRC_ADDR_HI <- 0xffff8001 020a0000 DST_ADDR_LO <- 0x020a0000 ffff8001 DST_ADDR_HI <- 0xffff8001 80000400 COMMAND <- BYTE_COUNT_GFX6 = 1024 (0x00400) BYTE_COUNT_GFX9 = 1024 (0x000400) DISABLE_WR_CONFIRM_GFX6 = 0 SRC_SWAP = NONE DST_SWAP = NONE SAS = MEMORY DAS = MEMORY SAIC = INCREMENT DAIC = INCREMENT RAW_WAIT = 0 DISABLE_WR_CONFIRM_GFX9 = 1 c0055000 DMA_DATA: 60200000 DMA_DATA_WORD0 <- CP_SYNC = 0 SRC_SEL = SRC_ADDR_TC_L2 DST_SEL = NOWHERE ENGINE = ME 01f08bc0 SRC_ADDR_LO <- 0x01f08bc0 ffff8000 SRC_ADDR_HI <- 0xffff8000 01f08bc0 DST_ADDR_LO <- 0x01f08bc0 ffff8000 DST_ADDR_HI <- 0xffff8000 80000040 COMMAND <- BYTE_COUNT_GFX6 = 64 (0x00040) BYTE_COUNT_GFX9 = 64 (0x000040) DISABLE_WR_CONFIRM_GFX6 = 0 SRC_SWAP = NONE DST_SWAP = NONE SAS = MEMORY DAS = MEMORY SAIC = INCREMENT DAIC = INCREMENT RAW_WAIT = 0 DISABLE_WR_CONFIRM_GFX9 = 1 c0026900 SET_CONTEXT_REG: 000002e5 00000000 VGT_STRMOUT_CONFIG <- STREAMOUT_0_EN = 0 STREAMOUT_1_EN = 0 STREAMOUT_2_EN = 0 STREAMOUT_3_EN = 0 RAST_STREAM = 0 EN_PRIMS_NEEDED_CNT = 0 RAST_STREAM_MASK = 0 USE_RAST_STREAM_MASK = 0 00000000 VGT_STRMOUT_BUFFER_CONFIG <- STREAM_0_BUFFER_EN = 0 STREAM_1_BUFFER_EN = 0 STREAM_2_BUFFER_EN = 0 STREAM_3_BUFFER_EN = 0 c00f6900 SET_CONTEXT_REG: 00000318 0101e300 CB_COLOR0_BASE <- 0x0101e300 00000080 CB_COLOR0_BASE_EXT <- BASE_256B = 128 (0x80) 0039c0ed CB_COLOR0_ATTRIB2 <- MIP0_HEIGHT = 237 (0x0ed) MIP0_WIDTH = 231 (0x0e7) MAX_MIP = 0 00000000 CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 MIP_LEVEL = 0 00028028 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_8_8_8_8 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 1 BLEND_BYPASS = 0 SIMPLE_FLOAT = 1 ROUND_MODE = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 dc640000 CB_COLOR0_ATTRIB <- MIP0_DEPTH = 0 META_LINEAR = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 COLOR_SW_MODE = 25 (0x19) FMASK_SW_MODE = 24 (0x18) RESOURCE_TYPE = 2D RB_ALIGNED = 1 PIPE_ALIGNED = 1 00000218 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = MAX_BLOCK_SIZE_256B MIN_COMPRESSED_BLOCK_SIZE = MIN_BLOCK_SIZE_64B MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 1 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 0101e300 CB_COLOR0_CMASK <- 0x0101e300 00000080 CB_COLOR0_CMASK_BASE_EXT <- BASE_256B = 128 (0x80) 0101e300 CB_COLOR0_FMASK <- 0x0101e300 00000080 CB_COLOR0_FMASK_BASE_EXT <- BASE_256B = 128 (0x80) 00000000 CB_COLOR0_CLEAR_WORD0 <- 0 00000000 CB_COLOR0_CLEAR_WORD1 <- 0 00000000 CB_COLOR0_DCC_BASE <- 0 00000000 CB_COLOR0_DCC_BASE_EXT <- BASE_256B = 0 c0016900 SET_CONTEXT_REG: 000001e8 000000ff CB_MRT0_EPITCH <- EPITCH = 255 (0x00ff) c0026900 SET_CONTEXT_REG: 0000000e 00000000 DB_Z_INFO <- FORMAT = Z_INVALID NUM_SAMPLES = 0 SW_MODE = 0 PARTIALLY_RESIDENT = 0 FAULT_BEHAVIOR = 0 ITERATE_FLUSH = 0 MAXMIP = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 0 READ_SIZE = 0 TILE_SURFACE_ENABLE = 0 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 00000000 DB_STENCIL_INFO <- FORMAT = STENCIL_INVALID SW_MODE = 0 PARTIALLY_RESIDENT = 0 FAULT_BEHAVIOR = 0 ITERATE_FLUSH = 0 ALLOW_EXPCLEAR = 0 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 c0016900 SET_CONTEXT_REG: 00000082 00ee00e8 PA_SC_WINDOW_SCISSOR_BR <- BR_X = 232 (0x0e8) BR_Y = 238 (0x0ee) c0004600 EVENT_WRITE: 0000000e VGT_EVENT_INITIATOR <- EVENT_TYPE = BREAK_BATCH EVENT_INDEX <- 0 INV_L2 <- 0 c0026900 SET_CONTEXT_REG: 000002f5 00000000 PA_SC_CENTROID_PRIORITY_0 <- DISTANCE_0 = 0 DISTANCE_1 = 0 DISTANCE_2 = 0 DISTANCE_3 = 0 DISTANCE_4 = 0 DISTANCE_5 = 0 DISTANCE_6 = 0 DISTANCE_7 = 0 00000000 PA_SC_CENTROID_PRIORITY_1 <- DISTANCE_8 = 0 DISTANCE_9 = 0 DISTANCE_10 = 0 DISTANCE_11 = 0 DISTANCE_12 = 0 DISTANCE_13 = 0 DISTANCE_14 = 0 DISTANCE_15 = 0 c0016900 SET_CONTEXT_REG: 000002fe 00000000 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 <- S0_X = 0 S0_Y = 0 S1_X = 0 S1_Y = 0 S2_X = 0 S2_Y = 0 S3_X = 0 S3_Y = 0 c0016900 SET_CONTEXT_REG: 00000302 00000000 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 <- S0_X = 0 S0_Y = 0 S1_X = 0 S1_Y = 0 S2_X = 0 S2_Y = 0 S3_X = 0 S3_Y = 0 c0016900 SET_CONTEXT_REG: 00000306 00000000 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 <- S0_X = 0 S0_Y = 0 S1_X = 0 S1_Y = 0 S2_X = 0 S2_Y = 0 S3_X = 0 S3_Y = 0 c0016900 SET_CONTEXT_REG: 0000030a 00000000 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 <- S0_X = 0 S0_Y = 0 S1_X = 0 S1_Y = 0 S2_X = 0 S2_Y = 0 S3_X = 0 S3_Y = 0 c0016900 SET_CONTEXT_REG: 0000020c 00000001 PA_SU_SMALL_PRIM_FILTER_CNTL <- SMALL_PRIM_FILTER_ENABLE = 1 TRIANGLE_FILTER_DISABLE = 0 LINE_FILTER_DISABLE = 0 POINT_FILTER_DISABLE = 0 RECTANGLE_FILTER_DISABLE = 0 c0016900 SET_CONTEXT_REG: 00000203 00000010 DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 PRIMITIVE_ORDERED_PIXEL_SHADER = 0 EXEC_IF_OVERLAPPED = 0 POPS_OVERLAP_NUM_SAMPLES = 0 c0016900 SET_CONTEXT_REG: 00000311 09fff500 PA_SC_BINNER_CNTL_0 <- BINNING_MODE = BINNING_ALLOWED BIN_SIZE_X = 0 BIN_SIZE_Y = 0 BIN_SIZE_X_EXTEND = 0 BIN_SIZE_Y_EXTEND = 2 CONTEXT_STATES_PER_BIN = 5 PERSISTENT_STATES_PER_BIN = 31 (0x1f) DISABLE_START_OF_PRIM = 1 FPOVS_PER_BATCH = 63 (0x3f) OPTIMAL_BIN_SELECTION = 1 c0016900 SET_CONTEXT_REG: 00000018 00000004 DB_DFSM_CONTROL <- PUNCHOUT_MODE = AUTO POPS_DRAIN_PS_ON_OVERLAP = 1 DISALLOW_OVERFLOW = 0 c0016900 SET_CONTEXT_REG: 00000201 00170000 DB_EQAA <- MAX_ANCHOR_SAMPLES = 0 PS_ITER_SAMPLES = 0 MASK_EXPORT_NUM_SAMPLES = 0 ALPHA_TO_MASK_NUM_SAMPLES = 0 HIGH_QUALITY_INTERSECTIONS = 1 INCOHERENT_EQAA_READS = 1 INTERPOLATE_COMP_Z = 1 INTERPOLATE_SRC_Z = 0 STATIC_ANCHOR_ASSOCIATIONS = 1 ALPHA_TO_MASK_EQAA_DISABLE = 0 OVERRASTERIZATION_AMOUNT = 0 ENABLE_POSTZ_OVERRASTERIZATION = 0 c0016900 SET_CONTEXT_REG: 00000293 760201bc PA_SC_MODE_CNTL_1 <- WALK_SIZE = 0 WALK_ALIGNMENT = 0 WALK_ALIGN8_PRIM_FITS_ST = 1 WALK_FENCE_ENABLE = 1 WALK_FENCE_SIZE = 3 SUPERTILE_WALK_ORDER_ENABLE = 1 TILE_WALK_ORDER_ENABLE = 1 TILE_COVER_DISABLE = 0 TILE_COVER_NO_SCISSOR = 0 ZMM_LINE_EXTENT = 0 ZMM_LINE_OFFSET = 0 ZMM_RECT_EXTENT = 0 KILL_PIX_POST_HI_Z = 0 KILL_PIX_POST_DETAIL_MASK = 0 PS_ITER_SAMPLE = 0 MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 1 MULTI_GPU_SUPERTILE_ENABLE = 0 GPU_ID_OVERRIDE_ENABLE = 0 GPU_ID_OVERRIDE = 0 MULTI_GPU_PRIM_DISCARD_ENABLE = 0 FORCE_EOV_CNTDWN_ENABLE = 1 FORCE_EOV_REZ_ENABLE = 1 OUT_OF_ORDER_PRIMITIVE_ENABLE = 0 OUT_OF_ORDER_WATER_MARK = 7 c0004600 EVENT_WRITE: 00000012 VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_DFSM EVENT_INDEX <- 0 INV_L2 <- 0 c0016900 SET_CONTEXT_REG: 0000008e 0000000f CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 c0016900 SET_CONTEXT_REG: 00000109 00000012 CB_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 OVERWRITE_COMBINER_MRT_SHARING_DISABLE = 1 OVERWRITE_COMBINER_WATERMARK = 4 c0036900 SET_CONTEXT_REG: 000001d5 00000005 SX_PS_DOWNCONVERT <- MRT0 = SX_RT_EXPORT_8_8_8_8 MRT1 = 0 MRT2 = 0 MRT3 = 0 MRT4 = 0 MRT5 = 0 MRT6 = 0 MRT7 = 0 00000007 SX_BLEND_OPT_EPSILON <- MRT0_EPSILON = 8BIT_FORMAT MRT1_EPSILON = 0 MRT2_EPSILON = 0 MRT3_EPSILON = 0 MRT4_EPSILON = 0 MRT5_EPSILON = 0 MRT6_EPSILON = 0 MRT7_EPSILON = 0 00000000 SX_BLEND_OPT_CONTROL <- MRT0_COLOR_OPT_DISABLE = 0 MRT0_ALPHA_OPT_DISABLE = 0 MRT1_COLOR_OPT_DISABLE = 0 MRT1_ALPHA_OPT_DISABLE = 0 MRT2_COLOR_OPT_DISABLE = 0 MRT2_ALPHA_OPT_DISABLE = 0 MRT3_COLOR_OPT_DISABLE = 0 MRT3_ALPHA_OPT_DISABLE = 0 MRT4_COLOR_OPT_DISABLE = 0 MRT4_ALPHA_OPT_DISABLE = 0 MRT5_COLOR_OPT_DISABLE = 0 MRT5_ALPHA_OPT_DISABLE = 0 MRT6_COLOR_OPT_DISABLE = 0 MRT6_ALPHA_OPT_DISABLE = 0 MRT7_COLOR_OPT_DISABLE = 0 MRT7_ALPHA_OPT_DISABLE = 0 PIXEN_ZERO_OPT_DISABLE = 0 c0016900 SET_CONTEXT_REG: 00000204 01000000 PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 0 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 c0017600 SET_SH_REG: 0000014c 01f08ac0 SPI_SHADER_USER_DATA_COMMON_0 <- 0x01f08ac0 c0027600 SET_SH_REG: 0000004e 01f08b90 SPI_SHADER_USER_DATA_VS_2 <- 0x01f08b90 00000000 SPI_SHADER_USER_DATA_VS_3 <- 0 c0027600 SET_SH_REG: 0000000e 01f08c50 SPI_SHADER_USER_DATA_PS_2 <- 0x01f08c50 01f00000 SPI_SHADER_USER_DATA_PS_3 <- 0x01f00000 c0027600 SET_SH_REG: 00000102 00000000 SPI_SHADER_USER_DATA_ADDR_LO_HS <- 0 00000000 SPI_SHADER_USER_DATA_ADDR_HI_HS <- 0 c0027600 SET_SH_REG: 00000082 00000000 SPI_SHADER_USER_DATA_ADDR_LO_GS <- 0 00000000 SPI_SHADER_USER_DATA_ADDR_HI_GS <- 0 c0017600 SET_SH_REG: 00000054 01f08bc0 SPI_SHADER_USER_DATA_VS_8 <- 0x01f08bc0 c0017600 SET_SH_REG: 0000014d 01ed0000 SPI_SHADER_USER_DATA_COMMON_1 <- 0x01ed0000 c0046900 SET_CONTEXT_REG: 000002fa 426eb7f1 PA_CL_GB_VERT_CLIP_ADJ <- 0x426eb7f1 3f800000 PA_CL_GB_VERT_DISC_ADJ <- 1.0f (0x3f800000) 42048777 PA_CL_GB_HORZ_CLIP_ADJ <- 0x42048777 3f800000 PA_CL_GB_HORZ_DISC_ADJ <- 1.0f (0x3f800000) c0026900 SET_CONTEXT_REG: 00000094 80000000 PA_SC_VPORT_SCISSOR_0_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 04380780 PA_SC_VPORT_SCISSOR_0_BR <- BR_X = 1920 (0x780) BR_Y = 1080 (0x438) c0066900 SET_CONTEXT_REG: 0000010f 44700000 PA_CL_VPORT_XSCALE <- 960.0f (0x44700000) 44700000 PA_CL_VPORT_XOFFSET <- 960.0f (0x44700000) 44070000 PA_CL_VPORT_YSCALE <- 540.0f (0x44070000) 44070000 PA_CL_VPORT_YOFFSET <- 540.0f (0x44070000) 3f000000 PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) 3f000000 PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) c0026900 SET_CONTEXT_REG: 000000b4 00000000 PA_SC_VPORT_ZMIN_0 <- 0 3f800000 PA_SC_VPORT_ZMAX_0 <- 1.0f (0x3f800000) c0026900 SET_CONTEXT_REG: 0000010c 01000000 DB_STENCILREFMASK <- STENCILTESTVAL = 0 STENCILMASK = 0 STENCILWRITEMASK = 0 STENCILOPVAL = 1 01000000 DB_STENCILREFMASK_BF <- STENCILTESTVAL_BF = 0 STENCILMASK_BF = 0 STENCILWRITEMASK_BF = 0 STENCILOPVAL_BF = 1 c0026900 SET_CONTEXT_REG: 00000191 00000000 SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 00000401 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 1 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 c0016900 SET_CONTEXT_REG: 000001ba 00000060 SPI_TMPRING_SIZE <- WAVES = 96 (0x060) WAVESIZE = 0 c0016900 SET_CONTEXT_REG: 000002dc 0000aa00 DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 c0086900 SET_CONTEXT_REG: 000001e0 40000501 CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 1 DISABLE_ROP3 = 0 40000501 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 1 DISABLE_ROP3 = 0 40000501 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 1 DISABLE_ROP3 = 0 40000501 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 1 DISABLE_ROP3 = 0 40000501 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 1 DISABLE_ROP3 = 0 40000501 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 1 DISABLE_ROP3 = 0 40000501 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 1 DISABLE_ROP3 = 0 40000501 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 1 DISABLE_ROP3 = 0 c0086900 SET_CONTEXT_REG: 000001d8 01510151 SX_MRT0_BLEND_OPT <- COLOR_SRC_OPT = BLEND_OPT_PRESERVE_ALL_IGNORE_NONE COLOR_DST_OPT = 5 COLOR_COMB_FCN = OPT_COMB_ADD ALPHA_SRC_OPT = 1 ALPHA_DST_OPT = 5 ALPHA_COMB_FCN = 1 01510151 SX_MRT1_BLEND_OPT <- COLOR_SRC_OPT = 1 COLOR_DST_OPT = 5 COLOR_COMB_FCN = 1 ALPHA_SRC_OPT = 1 ALPHA_DST_OPT = 5 ALPHA_COMB_FCN = 1 01510151 SX_MRT2_BLEND_OPT <- COLOR_SRC_OPT = 1 COLOR_DST_OPT = 5 COLOR_COMB_FCN = 1 ALPHA_SRC_OPT = 1 ALPHA_DST_OPT = 5 ALPHA_COMB_FCN = 1 01510151 SX_MRT3_BLEND_OPT <- COLOR_SRC_OPT = 1 COLOR_DST_OPT = 5 COLOR_COMB_FCN = 1 ALPHA_SRC_OPT = 1 ALPHA_DST_OPT = 5 ALPHA_COMB_FCN = 1 01510151 SX_MRT4_BLEND_OPT <- COLOR_SRC_OPT = 1 COLOR_DST_OPT = 5 COLOR_COMB_FCN = 1 ALPHA_SRC_OPT = 1 ALPHA_DST_OPT = 5 ALPHA_COMB_FCN = 1 01510151 SX_MRT5_BLEND_OPT <- COLOR_SRC_OPT = 1 COLOR_DST_OPT = 5 COLOR_COMB_FCN = 1 ALPHA_SRC_OPT = 1 ALPHA_DST_OPT = 5 ALPHA_COMB_FCN = 1 01510151 SX_MRT6_BLEND_OPT <- COLOR_SRC_OPT = 1 COLOR_DST_OPT = 5 COLOR_COMB_FCN = 1 ALPHA_SRC_OPT = 1 ALPHA_DST_OPT = 5 ALPHA_COMB_FCN = 1 01510151 SX_MRT7_BLEND_OPT <- COLOR_SRC_OPT = 1 COLOR_DST_OPT = 5 COLOR_COMB_FCN = 1 ALPHA_SRC_OPT = 1 ALPHA_DST_OPT = 5 ALPHA_COMB_FCN = 1 c0016900 SET_CONTEXT_REG: 00000202 00cc0010 CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = ROP3_COPY c0016900 SET_CONTEXT_REG: 000001b5 0000486b SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 c0036900 SET_CONTEXT_REG: 00000280 00080008 PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 00080008 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 00000008 PA_SU_LINE_CNTL <- WIDTH = 8 c0016900 SET_CONTEXT_REG: 00000292 00000022 PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 1 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SCALE_LINE_WIDTH_PAD = 0 ALTERNATE_RBS_PER_TILE = 1 COARSE_TILE_STARTS_ON_EVEN_RB = 0 c0016900 SET_CONTEXT_REG: 000002f9 00000029 PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH c0016900 SET_CONTEXT_REG: 000002df 00000000 PA_SU_POLY_OFFSET_CLAMP <- 0 c0016900 SET_CONTEXT_REG: 00000205 00080246 PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 1 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF = 0 NEW_QUAD_DECOMPOSITION = 0 c0016900 SET_CONTEXT_REG: 00000200 00000000 DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 c0016900 SET_CONTEXT_REG: 000002d5 00010000 VGT_SHADER_STAGES_EN <- LS_EN = LS_STAGE_OFF HS_EN = 0 ES_EN = ES_STAGE_OFF GS_EN = 0 VS_EN = VS_STAGE_REAL DISPATCH_DRAW_EN = 0 DIS_DEALLOC_ACCUM_0 = 0 DIS_DEALLOC_ACCUM_1 = 0 VS_WAVE_ID_EN = 0 PRIMGEN_EN = 0 ORDERED_ID_MODE = 0 MAX_PRIMGRP_IN_WAVE = 2 GS_FAST_LAUNCH = 0 c0016900 SET_CONTEXT_REG: 00000290 00000000 VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 RESERVED_3 = 0 RESERVED_4 = 0 RESERVED_5 = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS c0016900 SET_CONTEXT_REG: 000002a1 00000000 VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 NGG_DISABLE_PROVOK_REUSE = 0 c0016900 SET_CONTEXT_REG: 000001b1 00000002 SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 1 VS_HALF_PACK = 0 c0016900 SET_CONTEXT_REG: 000001c3 00000004 SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE c0047600 SET_SH_REG: 00000048 01020a00 SPI_SHADER_PGM_LO_VS <- 0x01020a00 00000080 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 128 (0x80) 012c0185 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 5 SGPRS = 6 PRIORITY = 0 FLOAT_MODE = 192 (0xc0) PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 1 CU_GROUP_ENABLE = 0 CDBG_USER = 0 FP16_OVFL = 0 00000012 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 9 TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 PC_BASE_EN = 0 DISPATCH_DRAW_EN = 0 SKIP_USGPR0 = 0 USER_SGPR_MSB = 0 c0016900 SET_CONTEXT_REG: 00000206 0000043f PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 PERFCOUNTER_REF = 0 c0016900 SET_CONTEXT_REG: 00000316 0000001e VGT_VERTEX_REUSE_BLOCK_CNTL <- VTX_REUSE_DEPTH = 30 (0x1e) c0026900 SET_CONTEXT_REG: 000001b3 00000302 SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 1 POS_Y_FLOAT_ENA = 1 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 0000f377 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 1 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 1 LINEAR_CENTER_ENA = 1 LINEAR_CENTROID_ENA = 1 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 1 POS_Y_FLOAT_ENA = 1 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 1 ANCILLARY_ENA = 1 SAMPLE_COVERAGE_ENA = 1 POS_FIXED_PT_ENA = 1 c0016900 SET_CONTEXT_REG: 000001b8 01020000 SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = 2 POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 1 c0016900 SET_CONTEXT_REG: 000001b6 00000002 SPI_PS_IN_CONTROL <- NUM_INTERP = 2 PARAM_GEN = 0 OFFCHIP_PARAM_EN = 0 LATE_PC_DEALLOC = 0 BC_OPTIMIZE_DISABLE = 0 c0026900 SET_CONTEXT_REG: 000001c4 00000000 SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO 00000004 SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO c0016900 SET_CONTEXT_REG: 0000008f 0000000f CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 c0047600 SET_SH_REG: 00000008 01000e1c SPI_SHADER_PGM_LO_PS <- 0x01000e1c 00000080 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 128 (0x80) 002c0105 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 5 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = FP_64_DENORMS PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CDBG_USER = 0 FP16_OVFL = 0 0000000a SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 5 TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 LOAD_COLLISION_WAVEID = 0 LOAD_INTRAWAVE_COLLISION = 0 SKIP_USGPR0 = 0 USER_SGPR_MSB = 0 c0017600 SET_SH_REG: 00000050 00000000 SPI_SHADER_USER_DATA_VS_4 <- 0 c0017900 SET_UCONFIG_REG: 40000258 INDEX = 4 0070007f IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 EN_INST_OPT_BASIC = 1 EN_INST_OPT_ADV = 1 HW_USE_ONLY = 0 c0017900 SET_UCONFIG_REG: 10000242 INDEX = 1 00000006 VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRISTRIP c0017900 SET_UCONFIG_REG: 0000024b 00000000 VGT_MULTI_PRIM_IB_RESET_EN <- RESET_EN = 0 MATCH_ALL_BITS = 0 c0021100 SET_BASE: 00000001 005e3000 ffff8001 c0082c00 DRAW_INDIRECT_MULTI: 00000000 00000051 00000052 80000053 00000001 00000000 00000000 00000010 00000002 c0055000 DMA_DATA: 60200000 DMA_DATA_WORD0 <- CP_SYNC = 0 SRC_SEL = SRC_ADDR_TC_L2 DST_SEL = NOWHERE ENGINE = ME 000e1c00 SRC_ADDR_LO <- 0x000e1c00 ffff8001 SRC_ADDR_HI <- 0xffff8001 000e1c00 DST_ADDR_LO <- 0x000e1c00 ffff8001 DST_ADDR_HI <- 0xffff8001 800001c0 COMMAND <- BYTE_COUNT_GFX6 = 448 (0x001c0) BYTE_COUNT_GFX9 = 448 (0x0001c0) DISABLE_WR_CONFIRM_GFX6 = 0 SRC_SWAP = NONE DST_SWAP = NONE SAS = MEMORY DAS = MEMORY SAIC = INCREMENT DAIC = INCREMENT RAW_WAIT = 0 DISABLE_WR_CONFIRM_GFX9 = 1 c0033700 WRITE_DATA: 00100100 CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC 00066800 DST_ADDR_LO <- 0x00066800 ffff8001 DST_ADDR_HI <- 0xffff8001 00000002 c0001000 NOP: Trace point ID: 2 !!!!! This trace point was NOT reached by the CP !!!!! cafe0002 ------------------- IB end ------------------- Color buffer 0: Info: npix_x=232, npix_y=238, npix_z=1, blk_w=1, blk_h=1, array_size=1, last_level=0, bpe=4, nsamples=0, flags=0x2000000, r8g8b8a8_unorm Surf: size=262144, slice_size=262144, alignment=65536, swmode=25, epitch=255, pitch=256 SHADER KEY part.vs.prolog.instance_divisor_is_one = 7 part.vs.prolog.instance_divisor_is_fetched = 0 part.vs.prolog.ls_vgpr_fix = 0 mono.vs.fix_fetch = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 mono.u.vs_export_prim_id = 0 opt.kill_outputs = 0x0 opt.clip_disable = 0 Vertex Shader as VS - main shader part - LLVM IR: ; ModuleID = 'mesa-shader' source_filename = "mesa-shader" target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" target triple = "amdgcn--" define amdgpu_vs void @main([0 x <4 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), [0 x <4 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, [0 x <4 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), i32, i32, i32, i32, i32, i32, i32) #0 { main_body: %16 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %8, i32 0, i32 0, !amdgpu.uniform !0 %17 = load <4 x i32>, <4 x i32> addrspace(6)* %16, align 16, !invariant.load !0 %18 = call nsz <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> %17, i32 %13, i32 0, i1 false, i1 false) #2 %19 = extractelement <2 x float> %18, i32 0 %20 = extractelement <2 x float> %18, i32 1 %21 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %8, i32 0, i32 1, !amdgpu.uniform !0 %22 = load <4 x i32>, <4 x i32> addrspace(6)* %21, align 16, !invariant.load !0 %23 = call nsz float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %22, i32 %14, i32 0, i1 false, i1 false) #2 %24 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %8, i32 0, i32 2, !amdgpu.uniform !0 %25 = load <4 x i32>, <4 x i32> addrspace(6)* %24, align 16, !invariant.load !0 %26 = call nsz float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %25, i32 %15, i32 0, i1 false, i1 false) #2 %27 = add i32 %9, %5 %28 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %2, i32 0, i32 16, !amdgpu.uniform !0 %29 = load <4 x i32>, <4 x i32> addrspace(6)* %28, align 16, !invariant.load !0 %30 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 0) %31 = bitcast float %30 to i32 %32 = bitcast float %23 to i32 %33 = add i32 %31, %32 %34 = bitcast i32 %33 to float %35 = ashr i32 %27, 1 %36 = sitofp i32 %35 to float %37 = and i32 %27, 1 %38 = sitofp i32 %37 to float %39 = bitcast float %26 to i32 %40 = icmp eq i32 %39, 0 %41 = fsub nsz float 1.000000e+00, %38 %42 = select i1 %40, float %41, float %38 %43 = fmul nsz float %19, %36 %44 = fmul nsz float %20, %38 %45 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %2, i32 0, i32 17, !amdgpu.uniform !0 %46 = load <4 x i32>, <4 x i32> addrspace(6)* %45, align 16, !invariant.load !0 %47 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 0) %48 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 4) %49 = bitcast float %48 to i32 %50 = shl i32 %49, 6 %51 = bitcast float %47 to i32 %52 = mul i32 %51, 192 %53 = add i32 %52, %50 %54 = add i32 %53, 80 %55 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %54) %56 = add i32 %53, 84 %57 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %56) %58 = add i32 %53, 88 %59 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %58) %60 = add i32 %53, 92 %61 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %60) %62 = add i32 %53, 96 %63 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %62) %64 = add i32 %53, 100 %65 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %64) %66 = add i32 %53, 104 %67 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %66) %68 = add i32 %53, 108 %69 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %68) %70 = add i32 %53, 112 %71 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %70) %72 = add i32 %53, 116 %73 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %72) %74 = add i32 %53, 120 %75 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %74) %76 = add i32 %53, 124 %77 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %76) %78 = add i32 %53, 128 %79 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %78) %80 = add i32 %53, 132 %81 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %80) %82 = add i32 %53, 136 %83 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %82) %84 = add i32 %53, 140 %85 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %84) %86 = or i32 %52, 16 %87 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %86) %88 = or i32 %52, 20 %89 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %88) %90 = add nsw i32 %88, 4 %91 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %90) %92 = or i32 %52, 28 %93 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %92) %94 = or i32 %52, 32 %95 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %94) %96 = or i32 %52, 36 %97 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %96) %98 = add nsw i32 %96, 4 %99 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %98) %100 = or i32 %52, 44 %101 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %100) %102 = or i32 %52, 48 %103 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %102) %104 = or i32 %52, 52 %105 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %104) %106 = add nsw i32 %104, 4 %107 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %106) %108 = or i32 %52, 60 %109 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %108) %110 = add i32 %52, 64 %111 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %110) %112 = add i32 %52, 68 %113 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %112) %114 = add i32 %52, 72 %115 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %114) %116 = add i32 %52, 76 %117 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %46, i32 %116) %118 = mul i32 %33, 96 %119 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %2, i32 0, i32 7, !amdgpu.uniform !0 %120 = load <4 x i32>, <4 x i32> addrspace(6)* %119, align 16, !invariant.load !0 %121 = call nsz <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %120, i32 0, i32 %118, i1 false, i1 false) #2 %122 = extractelement <4 x float> %121, i32 0 %123 = extractelement <4 x float> %121, i32 1 %124 = extractelement <4 x float> %121, i32 2 %125 = extractelement <4 x float> %121, i32 3 %126 = or i32 %118, 16 %127 = call nsz <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %120, i32 0, i32 %126, i1 false, i1 false) #2 %128 = extractelement <4 x float> %127, i32 0 %129 = extractelement <4 x float> %127, i32 1 %130 = extractelement <4 x float> %127, i32 2 %131 = extractelement <4 x float> %127, i32 3 %132 = add i32 %118, 32 %133 = call nsz <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %120, i32 0, i32 %132, i1 false, i1 false) #2 %134 = extractelement <4 x float> %133, i32 0 %135 = extractelement <4 x float> %133, i32 1 %136 = extractelement <4 x float> %133, i32 2 %137 = extractelement <4 x float> %133, i32 3 %138 = add i32 %118, 48 %139 = call nsz <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %120, i32 0, i32 %138, i1 false, i1 false) #2 %140 = extractelement <4 x float> %139, i32 0 %141 = extractelement <4 x float> %139, i32 1 %142 = extractelement <4 x float> %139, i32 2 %143 = extractelement <4 x float> %139, i32 3 %144 = fmul nsz float %122, %43 %145 = fmul nsz float %123, %43 %146 = fmul nsz float %124, %43 %147 = fmul nsz float %125, %43 %148 = fmul nsz float %128, %44 %149 = fadd nsz float %148, %144 %150 = fmul nsz float %129, %44 %151 = fadd nsz float %150, %145 %152 = fmul nsz float %130, %44 %153 = fadd nsz float %152, %146 %154 = fmul nsz float %131, %44 %155 = fadd nsz float %154, %147 %156 = fmul nsz float %134, 0.000000e+00 %157 = fadd nsz float %156, %149 %158 = fmul nsz float %135, 0.000000e+00 %159 = fadd nsz float %158, %151 %160 = fmul nsz float %136, 0.000000e+00 %161 = fadd nsz float %160, %153 %162 = fmul nsz float %137, 0.000000e+00 %163 = fadd nsz float %162, %155 %164 = fadd nsz float %140, %157 %165 = fadd nsz float %141, %159 %166 = fadd nsz float %142, %161 %167 = fadd nsz float %143, %163 %168 = fmul nsz float %87, %164 %169 = fmul nsz float %89, %164 %170 = fmul nsz float %91, %164 %171 = fmul nsz float %93, %164 %172 = fmul nsz float %95, %165 %173 = fadd nsz float %172, %168 %174 = fmul nsz float %97, %165 %175 = fadd nsz float %174, %169 %176 = fmul nsz float %99, %165 %177 = fadd nsz float %176, %170 %178 = fmul nsz float %101, %165 %179 = fadd nsz float %178, %171 %180 = fmul nsz float %103, %166 %181 = fadd nsz float %180, %173 %182 = fmul nsz float %105, %166 %183 = fadd nsz float %182, %175 %184 = fmul nsz float %107, %166 %185 = fadd nsz float %184, %177 %186 = fmul nsz float %109, %166 %187 = fadd nsz float %186, %179 %188 = fmul nsz float %111, %167 %189 = fadd nsz float %188, %181 %190 = fmul nsz float %113, %167 %191 = fadd nsz float %190, %183 %192 = fmul nsz float %115, %167 %193 = fadd nsz float %192, %185 %194 = fmul nsz float %117, %167 %195 = fadd nsz float %194, %187 %196 = fmul nsz float %55, %189 %197 = fmul nsz float %57, %189 %198 = fmul nsz float %59, %189 %199 = fmul nsz float %61, %189 %200 = fmul nsz float %63, %191 %201 = fadd nsz float %200, %196 %202 = fmul nsz float %65, %191 %203 = fadd nsz float %202, %197 %204 = fmul nsz float %67, %191 %205 = fadd nsz float %204, %198 %206 = fmul nsz float %69, %191 %207 = fadd nsz float %206, %199 %208 = fmul nsz float %71, %193 %209 = fadd nsz float %208, %201 %210 = fmul nsz float %73, %193 %211 = fadd nsz float %210, %203 %212 = fmul nsz float %75, %193 %213 = fadd nsz float %212, %205 %214 = fmul nsz float %77, %193 %215 = fadd nsz float %214, %207 %216 = fmul nsz float %79, %195 %217 = fadd nsz float %216, %209 %218 = fmul nsz float %81, %195 %219 = fadd nsz float %218, %211 %220 = fmul nsz float %83, %195 %221 = fadd nsz float %220, %213 %222 = fmul nsz float %85, %195 %223 = fadd nsz float %222, %215 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %217, float %219, float %221, float %223, i1 true, i1 false) #3 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %36, float %42, float undef, float undef, i1 false, i1 false) #3 call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %34, float undef, float undef, float undef, i1 false, i1 false) #3 ret void } ; Function Attrs: nounwind readonly declare <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32>, i32, i32, i1, i1) #1 ; Function Attrs: nounwind readonly declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2 ; Function Attrs: nounwind readonly declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #1 ; Function Attrs: nounwind declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #3 attributes #0 = { "amdgpu-32bit-address-high-bits"="0xffff8000" "no-signed-zeros-fp-math"="true" } attributes #1 = { nounwind readonly } attributes #2 = { nounwind readnone } attributes #3 = { nounwind } !0 = !{} Vertex Shader as VS: Shader prolog disassembly: vs_prolog: BB4_0: v_add_u32_e32 v4, s6, v1 ; 68080206 v_mov_b32_e32 v5, v4 ; 7E0A0304 v_mov_b32_e32 v6, v4 ; 7E0C0304 Shader main disassembly: main: BB9_0: s_movk_i32 s9, 0x8000 ; B0098000 s_add_i32 s0, s8, 16 ; 81009008 s_mov_b32 s1, s9 ; BE810009 s_load_dwordx4 s[12:15], s[0:1], 0x0 ; C00A0300 00000000 s_load_dwordx4 s[16:19], s[8:9], 0x0 ; C00A0404 00000000 s_add_i32 s8, s8, 32 ; 8108A008 s_load_dwordx4 s[20:23], s[8:9], 0x0 ; C00A0504 00000000 s_add_i32 s8, s2, 0x100 ; 8108FF02 00000100 s_waitcnt lgkmcnt(0) ; BF8CC07F buffer_load_format_x v3, v5, s[12:15], 0 idxen ; E0002000 80030305 buffer_load_format_xy v[1:2], v4, s[16:19], 0 idxen ; E0042000 80040104 s_load_dwordx4 s[24:27], s[8:9], 0x0 ; C00A0604 00000000 buffer_load_format_x v5, v6, s[20:23], 0 idxen ; E0002000 80050506 s_add_i32 s8, s2, 0x110 ; 8108FF02 00000110 s_load_dwordx4 s[12:15], s[8:9], 0x0 ; C00A0304 00000000 v_add_u32_e32 v0, s5, v0 ; 68000005 s_waitcnt lgkmcnt(0) ; BF8CC07F s_buffer_load_dword s4, s[24:27], 0x0 ; C022010C 00000000 s_movk_i32 s10, 0x70 ; B00A0070 s_add_i32 s8, s2, s10 ; 81080A02 v_ashrrev_i32_e32 v4, 1, v0 ; 22080081 v_and_b32_e32 v0, 1, v0 ; 26000081 v_cvt_f32_ubyte0_e32 v0, v0 ; 7E002300 s_movk_i32 s11, 0x60 ; B00B0060 s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C00A0004 00000000 v_cvt_f32_i32_e32 v12, v4 ; 7E180B04 v_sub_f32_e32 v4, 1.0, v0 ; 040800F2 s_buffer_load_dwordx2 s[6:7], s[12:15], 0x0 ; C0260186 00000000 s_waitcnt lgkmcnt(0) ; BF8CC07F s_mul_i32 s5, s6, 0xc0 ; 9205FF06 000000C0 s_lshl_b32 s7, s7, 6 ; 8E078607 s_add_i32 s7, s5, s7 ; 81070705 s_or_b32 s6, s5, 16 ; 87069005 s_or_b32 s8, s5, 20 ; 87089405 s_or_b32 s9, s5, 32 ; 8709A005 s_or_b32 s16, s5, 36 ; 8710A405 s_or_b32 s17, s5, 28 ; 87119C05 s_buffer_load_dword s33, s[12:15], s6 ; C0200846 00000006 s_buffer_load_dword s34, s[12:15], s8 ; C0200886 00000008 s_add_i32 s19, s7, 0x50 ; 8113FF07 00000050 s_buffer_load_dword s6, s[12:15], s17 ; C0200186 00000011 s_buffer_load_dword s35, s[12:15], s9 ; C02008C6 00000009 s_buffer_load_dword s36, s[12:15], s16 ; C0200906 00000010 s_add_i32 s20, s7, 0x54 ; 8114FF07 00000054 s_add_i32 s21, s7, 0x58 ; 8115FF07 00000058 s_add_i32 s22, s7, 0x5c ; 8116FF07 0000005C s_add_i32 s23, s7, s11 ; 81170B07 s_add_i32 s24, s7, 0x64 ; 8118FF07 00000064 s_add_i32 s25, s7, 0x68 ; 8119FF07 00000068 s_add_i32 s26, s7, 0x6c ; 811AFF07 0000006C s_add_i32 s10, s7, s10 ; 810A0A07 s_add_i32 s27, s7, 0x74 ; 811BFF07 00000074 s_add_i32 s28, s7, 0x78 ; 811CFF07 00000078 s_add_i32 s29, s7, 0x7c ; 811DFF07 0000007C s_add_i32 s30, s7, 0x80 ; 811EFF07 00000080 s_add_i32 s31, s7, 0x84 ; 811FFF07 00000084 s_add_i32 s32, s7, 0x88 ; 8120FF07 00000088 s_addk_i32 s7, 0x8c ; B707008C s_add_i32 s8, s8, 4 ; 81088408 s_add_i32 s16, s16, 4 ; 81108410 s_buffer_load_dword s9, s[12:15], s19 ; C0200246 00000013 s_buffer_load_dword s17, s[12:15], s20 ; C0200446 00000014 s_buffer_load_dword s37, s[12:15], s21 ; C0200946 00000015 s_buffer_load_dword s38, s[12:15], s22 ; C0200986 00000016 s_buffer_load_dword s39, s[12:15], s23 ; C02009C6 00000017 s_buffer_load_dword s40, s[12:15], s24 ; C0200A06 00000018 s_buffer_load_dword s41, s[12:15], s25 ; C0200A46 00000019 s_buffer_load_dword s42, s[12:15], s26 ; C0200A86 0000001A s_buffer_load_dword s43, s[12:15], s10 ; C0200AC6 0000000A s_buffer_load_dword s44, s[12:15], s27 ; C0200B06 0000001B s_buffer_load_dword s45, s[12:15], s28 ; C0200B46 0000001C s_buffer_load_dword s46, s[12:15], s29 ; C0200B86 0000001D s_buffer_load_dword s47, s[12:15], s30 ; C0200BC6 0000001E s_buffer_load_dword s48, s[12:15], s31 ; C0200C06 0000001F s_buffer_load_dword s49, s[12:15], s32 ; C0200C46 00000020 s_buffer_load_dword s10, s[12:15], s7 ; C0200286 00000007 s_buffer_load_dword s19, s[12:15], s8 ; C02004C6 00000008 s_buffer_load_dword s20, s[12:15], s16 ; C0200506 00000010 s_or_b32 s7, s5, 48 ; 8707B005 s_or_b32 s8, s5, 52 ; 8708B405 s_or_b32 s18, s5, 44 ; 8712AC05 s_add_i32 s21, s5, 64 ; 8115C005 s_buffer_load_dword s16, s[12:15], s8 ; C0200406 00000008 s_add_i32 s8, s8, 4 ; 81088408 s_buffer_load_dword s7, s[12:15], s7 ; C02001C6 00000007 s_add_i32 s22, s5, 0x44 ; 8116FF05 00000044 s_buffer_load_dword s8, s[12:15], s8 ; C0200206 00000008 s_waitcnt vmcnt(2) ; BF8C0F72 v_add_u32_e32 v14, s4, v3 ; 681C0604 v_mul_lo_i32 v16, v14, s11 ; D2850010 0000170E s_waitcnt vmcnt(1) ; BF8C0F71 v_mul_f32_e32 v8, v1, v12 ; 0A101901 s_waitcnt vmcnt(0) ; BF8C0F70 v_cmp_eq_u32_e32 vcc, 0, v5 ; 7D940A80 v_mul_f32_e32 v13, v2, v0 ; 0A1A0102 v_cndmask_b32_e32 v15, v0, v4, vcc ; 001E0900 s_buffer_load_dword s4, s[12:15], s18 ; C0200106 00000012 buffer_load_dwordx4 v[0:3], v16, s[0:3], 0 offen ; E05C1000 80000010 buffer_load_dwordx4 v[4:7], v16, s[0:3], 0 offen offset:16 ; E05C1010 80000410 s_or_b32 s18, s5, 60 ; 8712BC05 s_add_i32 s23, s5, 0x48 ; 8117FF05 00000048 s_addk_i32 s5, 0x4c ; B705004C s_buffer_load_dword s18, s[12:15], s18 ; C0200486 00000012 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], s21 ; C0200546 00000015 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], s22 ; C0200586 00000016 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[12:15], s23 ; C02002C6 00000017 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[12:15], s5 ; C0200146 00000005 s_waitcnt vmcnt(1) ; BF8C0F71 v_mul_f32_e32 v17, v0, v8 ; 0A221100 v_mul_f32_e32 v18, v1, v8 ; 0A241101 v_mul_f32_e32 v19, v2, v8 ; 0A261102 v_mul_f32_e32 v20, v3, v8 ; 0A281103 s_waitcnt vmcnt(0) ; BF8C0F70 v_mac_f32_e32 v17, v4, v13 ; 2C221B04 v_mac_f32_e32 v18, v5, v13 ; 2C241B05 v_mac_f32_e32 v19, v6, v13 ; 2C261B06 v_mac_f32_e32 v20, v7, v13 ; 2C281B07 s_nop 0 ; BF800000 s_nop 0 ; BF800000 buffer_load_dwordx4 v[0:3], v16, s[0:3], 0 offen offset:32 ; E05C1020 80000010 buffer_load_dwordx4 v[8:11], v16, s[0:3], 0 offen offset:48 ; E05C1030 80000810 s_waitcnt vmcnt(1) ; BF8C0F71 v_mac_f32_e32 v17, 0, v0 ; 2C220080 s_waitcnt vmcnt(0) ; BF8C0F70 v_add_f32_e32 v0, v8, v17 ; 02002308 v_mac_f32_e32 v18, 0, v1 ; 2C240280 v_mac_f32_e32 v19, 0, v2 ; 2C260480 v_add_f32_e32 v1, v9, v18 ; 02022509 s_waitcnt lgkmcnt(0) ; BF8CC07F v_mul_f32_e32 v4, s33, v0 ; 0A080021 v_mac_f32_e32 v20, 0, v3 ; 2C280680 v_mul_f32_e32 v5, s34, v0 ; 0A0A0022 v_mul_f32_e32 v6, s19, v0 ; 0A0C0013 v_mul_f32_e32 v0, s6, v0 ; 0A000006 v_add_f32_e32 v2, v10, v19 ; 0204270A v_mac_f32_e32 v4, s35, v1 ; 2C080223 v_mac_f32_e32 v5, s36, v1 ; 2C0A0224 v_mac_f32_e32 v6, s20, v1 ; 2C0C0214 v_mac_f32_e32 v0, s4, v1 ; 2C000204 v_add_f32_e32 v3, v11, v20 ; 0206290B v_mac_f32_e32 v4, s7, v2 ; 2C080407 v_mac_f32_e32 v5, s16, v2 ; 2C0A0410 v_mac_f32_e32 v6, s8, v2 ; 2C0C0408 v_mac_f32_e32 v0, s18, v2 ; 2C000412 v_mac_f32_e32 v4, s21, v3 ; 2C080615 v_mac_f32_e32 v5, s22, v3 ; 2C0A0616 v_mul_f32_e32 v1, s9, v4 ; 0A020809 v_mul_f32_e32 v2, s17, v4 ; 0A040811 v_mac_f32_e32 v6, s11, v3 ; 2C0C060B v_mac_f32_e32 v0, s5, v3 ; 2C000605 v_mul_f32_e32 v3, s37, v4 ; 0A060825 v_mul_f32_e32 v4, s38, v4 ; 0A080826 v_mac_f32_e32 v1, s39, v5 ; 2C020A27 v_mac_f32_e32 v2, s40, v5 ; 2C040A28 v_mac_f32_e32 v3, s41, v5 ; 2C060A29 v_mac_f32_e32 v4, s42, v5 ; 2C080A2A v_mac_f32_e32 v1, s43, v6 ; 2C020C2B v_mac_f32_e32 v2, s44, v6 ; 2C040C2C v_mac_f32_e32 v3, s45, v6 ; 2C060C2D v_mac_f32_e32 v4, s46, v6 ; 2C080C2E v_mac_f32_e32 v1, s47, v0 ; 2C02002F v_mac_f32_e32 v2, s48, v0 ; 2C040030 v_mac_f32_e32 v3, s49, v0 ; 2C060031 v_mac_f32_e32 v4, s10, v0 ; 2C08000A exp pos0 v1, v2, v3, v4 done ; C40008CF 04030201 exp param0 v12, v15, v0, v0 ; C400020F 00000F0C exp param1 v14, v0, v0, v0 ; C400021F 0000000E s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 56 VGPRS: 24 Spilled SGPRs: 0 Spilled VGPRs: 0 Private memory VGPRs: 0 Code Size: 996 bytes LDS: 0 blocks Scratch: 0 bytes per wave Max Waves: 10 ******************** SHADER KEY part.ps.prolog.color_two_side = 0 part.ps.prolog.flatshade_colors = 0 part.ps.prolog.poly_stipple = 0 part.ps.prolog.force_persp_sample_interp = 0 part.ps.prolog.force_linear_sample_interp = 0 part.ps.prolog.force_persp_center_interp = 0 part.ps.prolog.force_linear_center_interp = 0 part.ps.prolog.bc_optimize_for_persp = 0 part.ps.prolog.bc_optimize_for_linear = 0 part.ps.epilog.spi_shader_col_format = 0x4 part.ps.epilog.color_is_int8 = 0x0 part.ps.epilog.color_is_int10 = 0x0 part.ps.epilog.last_cbuf = 0 part.ps.epilog.alpha_func = 7 part.ps.epilog.alpha_to_one = 0 part.ps.epilog.poly_line_smoothing = 0 part.ps.epilog.clamp_color = 0 Pixel Shader - main shader part - LLVM IR: ; ModuleID = 'mesa-shader' source_filename = "mesa-shader" target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" target triple = "amdgcn--" define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([0 x <4 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), [0 x <4 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 { main_body: %22 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %2, i32 0, i32 16, !amdgpu.uniform !0 %23 = load <4 x i32>, <4 x i32> addrspace(6)* %22, align 16, !invariant.load !0 %24 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 1, i32 %5) #1 %25 = bitcast float %24 to i32 %26 = mul i32 %25, 96 %27 = add i32 %26, 80 %28 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %2, i32 0, i32 7, !amdgpu.uniform !0 %29 = load <4 x i32>, <4 x i32> addrspace(6)* %28, align 16, !invariant.load !0 %30 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %29, i32 0, i32 %27, i1 false, i1 false) %31 = add i32 %26, 64 %32 = call nsz <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %29, i32 0, i32 %31, i1 false, i1 false) #1 %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = extractelement <4 x float> %32, i32 2 %36 = extractelement <4 x float> %32, i32 3 %37 = bitcast <2 x i32> %7 to <2 x float> %38 = extractelement <2 x float> %37, i32 0 %39 = extractelement <2 x float> %37, i32 1 %40 = call nsz float @llvm.amdgcn.interp.p1(float %38, i32 0, i32 0, i32 %5) #1 %41 = call nsz float @llvm.amdgcn.interp.p2(float %40, float %39, i32 0, i32 0, i32 %5) #1 %42 = call nsz float @llvm.amdgcn.interp.p1(float %38, i32 1, i32 0, i32 %5) #1 %43 = call nsz float @llvm.amdgcn.interp.p2(float %42, float %39, i32 1, i32 0, i32 %5) #1 %44 = bitcast float %30 to i32 %45 = shl i32 %44, 1 %46 = getelementptr [0 x <8 x i32>], [0 x <8 x i32>] addrspace(6)* %1, i32 0, i32 %45, !amdgpu.uniform !0 %47 = load <8 x i32>, <8 x i32> addrspace(6)* %46, align 32, !invariant.load !0 %48 = shl i32 %44, 2 %49 = or i32 %48, 3 %50 = bitcast [0 x <8 x i32>] addrspace(6)* %1 to [0 x <4 x i32>] addrspace(6)* %51 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %50, i32 0, i32 %49, !amdgpu.uniform !0 %52 = load <4 x i32>, <4 x i32> addrspace(6)* %51, align 16, !invariant.load !0 %53 = call nsz <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %41, float %43, <8 x i32> %47, <4 x i32> %52, i1 false, i32 0, i32 0) #1 %54 = extractelement <4 x float> %53, i32 0 %55 = extractelement <4 x float> %53, i32 1 %56 = extractelement <4 x float> %53, i32 2 %57 = extractelement <4 x float> %53, i32 3 %58 = fmul nsz float %54, %33 %59 = fmul nsz float %55, %34 %60 = fmul nsz float %56, %35 %61 = fmul nsz float %57, %36 %62 = fmul nsz float %58, %61 %63 = fmul nsz float %59, %61 %64 = fmul nsz float %60, %61 %65 = fcmp nsz ogt float %61, 0.000000e+00 br i1 %65, label %if12, label %endif21 if12: ; preds = %main_body %66 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %23, i32 0) %67 = fmul nsz float %66, %15 %68 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %23, i32 4) %69 = fadd nsz float %67, %68 %70 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %2, i32 0, i32 17, !amdgpu.uniform !0 %71 = load <4 x i32>, <4 x i32> addrspace(6)* %70, align 16, !invariant.load !0 %72 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %71, i32 0) %73 = bitcast float %72 to i32 %74 = shl i32 %73, 4 %75 = add i32 %74, 3856 %76 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %71, i32 %75) %77 = add i32 %26, 88 %78 = call nsz float @llvm.amdgcn.buffer.load.f32(<4 x i32> %29, i32 0, i32 %77, i1 false, i1 false) #1 %79 = fptosi float %14 to i32 %80 = fptosi float %69 to i32 %81 = bitcast float %78 to i32 %82 = bitcast float %76 to i32 %83 = shl i32 %82, 1 %84 = getelementptr [0 x <8 x i32>], [0 x <8 x i32>] addrspace(6)* %1, i32 0, i32 %83, !amdgpu.uniform !0 %85 = load <8 x i32>, <8 x i32> addrspace(6)* %84, align 32, !invariant.load !0 %86 = extractelement <8 x i32> %85, i32 6 %87 = and i32 %86, -2097153 %88 = insertelement <8 x i32> %85, i32 %87, i32 6 %89 = extractelement <8 x i32> %85, i32 5 %90 = and i32 %89, 8191 %91 = call i32 @llvm.amdgcn.image.atomic.umax.3d.i32.i32(i32 %81, i32 %79, i32 %80, i32 %90, <8 x i32> %88, i32 0, i32 0) #4 br label %endif21 endif21: ; preds = %if12, %main_body %92 = bitcast float %4 to i32 %93 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %92, 4 %94 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %93, float %62, 5 %95 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %94, float %63, 6 %96 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %95, float %64, 7 %97 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %96, float %61, 8 %98 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %97, float %20, 19 ret <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %98 } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1 ; Function Attrs: nounwind readnone speculatable declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #2 ; Function Attrs: nounwind readonly declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #3 ; Function Attrs: nounwind readonly declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #3 ; Function Attrs: nounwind readnone speculatable declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2 ; Function Attrs: nounwind readnone speculatable declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2 ; Function Attrs: nounwind readonly declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #3 ; Function Attrs: nounwind readonly declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #3 ; Function Attrs: nounwind declare i32 @llvm.amdgcn.image.atomic.umax.3d.i32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #4 attributes #0 = { "InitialPSInputAddr"="0xb077" "amdgpu-32bit-address-high-bits"="0xffff8000" "no-signed-zeros-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind readnone speculatable } attributes #3 = { nounwind readonly } attributes #4 = { nounwind } !0 = !{} Pixel Shader: Shader main disassembly: main: BB12_0: v_mov_b32_e32 v14, v16 ; 7E1C0310 s_mov_b64 s[24:25], exec ; BE98017E s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s5 ; BEFC0005 s_add_i32 s6, s2, 0x70 ; 8106FF02 00000070 s_movk_i32 s7, 0x8000 ; B0078000 v_interp_mov_f32_e32 v0, p0, attr1.x ; D4020402 s_movk_i32 s0, 0x60 ; B0000060 s_load_dwordx4 s[8:11], s[6:7], 0x0 ; C00A0203 00000000 v_mul_lo_i32 v0, v0, s0 ; D2850000 00000100 v_interp_p1_f32_e32 v1, v2, attr0.x ; D4040002 v_interp_p1_f32_e32 v2, v2, attr0.y ; D4080102 v_interp_p2_f32_e32 v1, v3, attr0.x ; D4050003 v_interp_p2_f32_e32 v2, v3, attr0.y ; D4090103 v_mov_b32_e32 v3, s7 ; 7E060207 v_readfirstlane_b32 s27, v3 ; 7E360503 v_readfirstlane_b32 s29, v3 ; 7E3A0503 s_nop 0 ; BF800000 s_waitcnt lgkmcnt(0) ; BF8CC07F s_nop 0 ; BF800000 buffer_load_dwordx4 v[4:7], v0, s[8:11], 0 offen offset:64 ; E05C1040 80020400 buffer_load_dword v3, v0, s[8:11], 0 offen offset:80 ; E0501050 80020300 s_waitcnt vmcnt(0) ; BF8C0F70 v_lshlrev_b32_e32 v3, 6, v3 ; 24060686 v_add_u32_e32 v3, s1, v3 ; 68060601 v_readfirstlane_b32 s26, v3 ; 7E340503 v_add_u32_e32 v3, 48, v3 ; 680606B0 v_readfirstlane_b32 s28, v3 ; 7E380503 s_load_dwordx4 s[20:23], s[28:29], 0x0 ; C00A050E 00000000 s_load_dwordx8 s[12:19], s[26:27], 0x0 ; C00E030D 00000000 s_and_b64 exec, exec, s[24:25] ; 86FE187E s_waitcnt lgkmcnt(0) ; BF8CC07F s_nop 0 ; BF800000 image_sample v[8:11], v[1:2], s[12:19], s[20:23] dmask:0xf ; F0800F00 00A30801 s_waitcnt vmcnt(0) ; BF8C0F70 v_mul_f32_e32 v3, v11, v7 ; 0A060F0B v_cmp_lt_f32_e32 vcc, 0, v3 ; 7C820680 s_and_saveexec_b64 s[12:13], vcc ; BE8C206A s_cbranch_execz BB12_2 ; BF880000 BB12_1: s_nop 0 ; BF800000 buffer_load_dword v7, v0, s[8:11], 0 offen offset:88 ; E0501058 80020700 s_add_i32 s6, s2, 0x100 ; 8106FF02 00000100 s_load_dwordx4 s[16:19], s[6:7], 0x0 ; C00A0403 00000000 s_add_i32 s6, s2, 0x110 ; 8106FF02 00000110 s_load_dwordx4 s[20:23], s[6:7], 0x0 ; C00A0503 00000000 v_cvt_i32_f32_e32 v0, v12 ; 7E00110C s_waitcnt lgkmcnt(0) ; BF8CC07F s_buffer_load_dwordx2 s[2:3], s[16:19], 0x0 ; C0260088 00000000 s_buffer_load_dword s0, s[20:23], 0x0 ; C022000A 00000000 s_waitcnt lgkmcnt(0) ; BF8CC07F v_mov_b32_e32 v1, s3 ; 7E020203 v_mad_f32 v1, s2, v13, v1 ; D1C10001 04061A02 s_lshl_b32 s0, s0, 4 ; 8E008400 s_addk_i32 s0, 0xf10 ; B7000F10 s_buffer_load_dword s0, s[20:23], s0 ; C020000A 00000000 v_cvt_i32_f32_e32 v1, v1 ; 7E021101 s_waitcnt lgkmcnt(0) ; BF8CC07F s_lshl_b32 s0, s0, 6 ; 8E008600 s_add_i32 s6, s1, s0 ; 81060001 s_load_dwordx8 s[16:23], s[6:7], 0x0 ; C00E0403 00000000 s_waitcnt lgkmcnt(0) ; BF8CC07F s_and_b32 s0, s21, 0x1fff ; 8600FF15 00001FFF s_and_b32 s22, s22, 0xffdfffff ; 8616FF16 FFDFFFFF v_mov_b32_e32 v2, s0 ; 7E040200 s_nop 0 ; BF800000 s_waitcnt vmcnt(0) ; BF8C0F70 s_nop 0 ; BF800000 image_atomic_umax v7, v[0:3], s[16:23] dmask:0x1 unorm glc ; F05C3100 00040700 BB12_2: s_or_b64 exec, exec, s[12:13] ; 87FE0C7E v_mul_f32_e32 v0, v8, v4 ; 0A000908 v_mul_f32_e32 v1, v9, v5 ; 0A020B09 v_mul_f32_e32 v2, v10, v6 ; 0A040D0A v_mul_f32_e32 v0, v0, v3 ; 0A000700 v_mul_f32_e32 v1, v1, v3 ; 0A020701 v_mul_f32_e32 v2, v2, v3 ; 0A040702 s_waitcnt vmcnt(0) ; BF8C0F70 Shader epilog disassembly: ps_epilog: BB0_0: v_cvt_pkrtz_f16_f32 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32 v1, v2, v3 ; D2960001 00020702 exp mrt0 v0, v0, v1, v1 done compr vm ; C4001C0F 00000100 s_endpgm ; BF810000 *** SHADER CONFIG *** SPI_PS_INPUT_ADDR = 0xf377 SPI_PS_INPUT_ENA = 0x0302 *** SHADER STATS *** SGPRS: 40 VGPRS: 24 Spilled SGPRs: 0 Spilled VGPRs: 0 Private memory VGPRs: 0 Code Size: 436 bytes LDS: 0 blocks Scratch: 0 bytes per wave Max Waves: 10 ******************** RW buffers slot 0 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 1 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 2 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 3 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 4 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 5 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 6 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 7 (GPU list): SQ_BUF_RSRC_WORD0 <- 0x01f005c0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 32768 (0x8000) STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 32 (0x00000020) SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_Y DST_SEL_Z = SQ_SEL_Z DST_SEL_W = SQ_SEL_W NUM_FORMAT = BUF_NUM_FORMAT_FLOAT DATA_FORMAT = BUF_DATA_FORMAT_32 USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 8 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 9 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 10 (GPU list): SQ_BUF_RSRC_WORD0 <- 0x01f00540 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 32768 (0x8000) STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 128 (0x00000080) SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_Y DST_SEL_Z = SQ_SEL_Z DST_SEL_W = SQ_SEL_W NUM_FORMAT = BUF_NUM_FORMAT_FLOAT DATA_FORMAT = BUF_DATA_FORMAT_32 USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 11 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 32768 (0x8000) STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 8 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_Y DST_SEL_Z = SQ_SEL_Z DST_SEL_W = SQ_SEL_W NUM_FORMAT = BUF_NUM_FORMAT_FLOAT DATA_FORMAT = BUF_DATA_FORMAT_32 USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 12 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 13 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 14 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF RW buffers slot 15 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Vertex buffer slot 0 (GPU list): SQ_BUF_RSRC_WORD0 <- 0x005e2800 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0x8001 STRIDE = 16 (0x010) CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 96 (0x00000060) SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_Y DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_1 NUM_FORMAT = BUF_NUM_FORMAT_FLOAT DATA_FORMAT = BUF_DATA_FORMAT_32_32 USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Vertex buffer slot 1 (GPU list): SQ_BUF_RSRC_WORD0 <- 0x005e2808 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0x8001 STRIDE = 16 (0x010) CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 96 (0x00000060) SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_1 NUM_FORMAT = BUF_NUM_FORMAT_UINT DATA_FORMAT = BUF_DATA_FORMAT_32 USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Vertex buffer slot 2 (GPU list): SQ_BUF_RSRC_WORD0 <- 0x005e280c SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0x8001 STRIDE = 16 (0x010) CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 96 (0x00000060) SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_1 NUM_FORMAT = BUF_NUM_FORMAT_UINT DATA_FORMAT = BUF_DATA_FORMAT_32 USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Constant buffer slot 0 (GPU list): SQ_BUF_RSRC_WORD0 <- 0x01ee1dc0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 32768 (0x8000) STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 16 (0x00000010) SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_Y DST_SEL_Z = SQ_SEL_Z DST_SEL_W = SQ_SEL_W NUM_FORMAT = BUF_NUM_FORMAT_FLOAT DATA_FORMAT = BUF_DATA_FORMAT_32 USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Constant buffer slot 1 (GPU list): SQ_BUF_RSRC_WORD0 <- 0x017a2000 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0x8001 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 4016 (0x00000fb0) SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_Y DST_SEL_Z = SQ_SEL_Z DST_SEL_W = SQ_SEL_W NUM_FORMAT = BUF_NUM_FORMAT_FLOAT DATA_FORMAT = BUF_DATA_FORMAT_32 USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Shader buffer slot 0 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Shader buffer slot 1 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Shader buffer slot 2 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Shader buffer slot 3 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Shader buffer slot 4 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Shader buffer slot 5 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Shader buffer slot 6 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Shader buffer slot 7 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF VS - Shader buffer slot 8 (GPU list): SQ_BUF_RSRC_WORD0 <- 0x005cc000 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0x8001 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 9216 (0x00002400) SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_Y DST_SEL_Z = SQ_SEL_Z DST_SEL_W = SQ_SEL_W NUM_FORMAT = BUF_NUM_FORMAT_FLOAT DATA_FORMAT = BUF_DATA_FORMAT_32 USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF PS - Constant buffer slot 0 (GPU list): SQ_BUF_RSRC_WORD0 <- 0x01ee1e00 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 32768 (0x8000) STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 16 (0x00000010) SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_Y DST_SEL_Z = SQ_SEL_Z DST_SEL_W = SQ_SEL_W NUM_FORMAT = BUF_NUM_FORMAT_FLOAT DATA_FORMAT = BUF_DATA_FORMAT_32 USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF PS - Constant buffer slot 1 (GPU list): SQ_BUF_RSRC_WORD0 <- 0x017a2000 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0x8001 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 4016 (0x00000fb0) SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_Y DST_SEL_Z = SQ_SEL_Z DST_SEL_W = SQ_SEL_W NUM_FORMAT = BUF_NUM_FORMAT_FLOAT DATA_FORMAT = BUF_DATA_FORMAT_32 USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF PS - Shader buffer slot 0 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF PS - Shader buffer slot 1 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF PS - Shader buffer slot 2 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF PS - Shader buffer slot 3 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF PS - Shader buffer slot 4 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF PS - Shader buffer slot 5 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF PS - Shader buffer slot 6 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF PS - Shader buffer slot 7 (GPU list): SQ_BUF_RSRC_WORD0 <- 0 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 0 SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_0 DST_SEL_Y = SQ_SEL_0 DST_SEL_Z = SQ_SEL_0 DST_SEL_W = SQ_SEL_0 NUM_FORMAT = BUF_NUM_FORMAT_UNORM DATA_FORMAT = BUF_DATA_FORMAT_INVALID USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF PS - Shader buffer slot 8 (GPU list): SQ_BUF_RSRC_WORD0 <- 0x005cc000 SQ_BUF_RSRC_WORD1 <- BASE_ADDRESS_HI = 0x8001 STRIDE = 0 CACHE_SWIZZLE = 0 SWIZZLE_ENABLE = 0 SQ_BUF_RSRC_WORD2 <- 9216 (0x00002400) SQ_BUF_RSRC_WORD3 <- DST_SEL_X = SQ_SEL_X DST_SEL_Y = SQ_SEL_Y DST_SEL_Z = SQ_SEL_Z DST_SEL_W = SQ_SEL_W NUM_FORMAT = BUF_NUM_FORMAT_FLOAT DATA_FORMAT = BUF_DATA_FORMAT_32 USER_VM_ENABLE = 0 USER_VM_MODE = 0 INDEX_STRIDE = 0 ADD_TID_ENABLE = 0 NV = 0 TYPE = SQ_RSRC_BUF ***************************************************************************** Driver-specific state: Memory-mapped registers: GRBM_STATUS <- ME0PIPE0_CMDFIFO_AVAIL = 8 RSMU_RQ_PENDING = 1 ME0PIPE0_CF_RQ_PENDING = 0 ME0PIPE0_PF_RQ_PENDING = 0 GDS_DMA_RQ_PENDING = 0 DB_CLEAN = 1 CB_CLEAN = 1 TA_BUSY = 0 GDS_BUSY = 0 WD_BUSY_NO_DMA = 0 VGT_BUSY = 0 IA_BUSY_NO_DMA = 0 IA_BUSY = 0 SX_BUSY = 0 WD_BUSY = 0 SPI_BUSY = 0 BCI_BUSY = 0 SC_BUSY = 0 PA_BUSY = 0 DB_BUSY = 0 CP_COHERENCY_BUSY = 0 CP_BUSY = 1 CB_BUSY = 0 GUI_ACTIVE = 1 GRBM_STATUS2 <- ME0PIPE1_CMDFIFO_AVAIL = 8 ME0PIPE1_CF_RQ_PENDING = 0 ME0PIPE1_PF_RQ_PENDING = 0 ME1PIPE0_RQ_PENDING = 0 ME1PIPE1_RQ_PENDING = 0 ME1PIPE2_RQ_PENDING = 0 ME1PIPE3_RQ_PENDING = 0 ME2PIPE0_RQ_PENDING = 0 ME2PIPE1_RQ_PENDING = 0 ME2PIPE2_RQ_PENDING = 0 ME2PIPE3_RQ_PENDING = 0 RLC_RQ_PENDING = 0 UTCL2_BUSY = 0 EA_BUSY = 0 RMI_BUSY = 0 UTCL2_RQ_PENDING = 0 CPF_RQ_PENDING = 0 EA_LINK_BUSY = 0 RLC_BUSY = 0 TC_BUSY = 0 TCC_CC_RESIDENT = 0 CPF_BUSY = 1 CPC_BUSY = 0 CPG_BUSY = 1 CPAXI_BUSY = 0 GRBM_STATUS_SE0 <- DB_CLEAN = 1 CB_CLEAN = 1 RMI_BUSY = 0 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 0 SC_BUSY = 0 DB_BUSY = 0 CB_BUSY = 0 GRBM_STATUS_SE1 <- DB_CLEAN = 1 CB_CLEAN = 1 RMI_BUSY = 0 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 0 SC_BUSY = 0 DB_BUSY = 0 CB_BUSY = 0 GRBM_STATUS_SE2 <- DB_CLEAN = 1 CB_CLEAN = 1 RMI_BUSY = 0 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 0 SC_BUSY = 0 DB_BUSY = 0 CB_BUSY = 0 GRBM_STATUS_SE3 <- DB_CLEAN = 1 CB_CLEAN = 1 RMI_BUSY = 0 BCI_BUSY = 0 VGT_BUSY = 0 PA_BUSY = 0 TA_BUSY = 0 SX_BUSY = 0 SPI_BUSY = 0 SC_BUSY = 0 DB_BUSY = 0 CB_BUSY = 0 CP_STAT <- ROQ_RING_BUSY = 1 ROQ_INDIRECT1_BUSY = 1 ROQ_INDIRECT2_BUSY = 0 ROQ_STATE_BUSY = 0 DC_BUSY = 0 UTCL2IU_BUSY = 1 PFP_BUSY = 1 MEQ_BUSY = 1 ME_BUSY = 1 QUERY_BUSY = 0 SEMAPHORE_BUSY = 0 INTERRUPT_BUSY = 0 SURFACE_SYNC_BUSY = 0 DMA_BUSY = 0 RCIU_BUSY = 0 SCRATCH_RAM_BUSY = 1 CE_BUSY = 0 TCIU_BUSY = 0 ROQ_CE_RING_BUSY = 0 ROQ_CE_INDIRECT1_BUSY = 0 ROQ_CE_INDIRECT2_BUSY = 0 CP_BUSY = 1 CP_STALLED_STAT1 <- RBIU_TO_DMA_NOT_RDY_TO_RCV = 0 RBIU_TO_SEM_NOT_RDY_TO_RCV = 0 RBIU_TO_MEMWR_NOT_RDY_TO_RCV = 0 ME_HAS_ACTIVE_CE_BUFFER_FLAG = 1 ME_HAS_ACTIVE_DE_BUFFER_FLAG = 1 ME_STALLED_ON_TC_WR_CONFIRM = 0 ME_STALLED_ON_ATOMIC_RTN_DATA = 0 ME_WAITING_ON_TC_READ_DATA = 0 ME_WAITING_ON_REG_READ_DATA = 0 RCIU_WAITING_ON_GDS_FREE = 0 RCIU_WAITING_ON_GRBM_FREE = 0 RCIU_WAITING_ON_VGT_FREE = 0 RCIU_STALLED_ON_ME_READ = 0 RCIU_STALLED_ON_DMA_READ = 0 RCIU_STALLED_ON_APPEND_READ = 0 RCIU_HALTED_BY_REG_VIOLATION = 0 CP_STALLED_STAT2 <- PFP_TO_CSF_NOT_RDY_TO_RCV = 0 PFP_TO_MEQ_NOT_RDY_TO_RCV = 0 PFP_TO_RCIU_NOT_RDY_TO_RCV = 0 PFP_TO_VGT_WRITES_PENDING = 0 PFP_RCIU_READ_PENDING = 0 PFP_WAITING_ON_BUFFER_DATA = 0 ME_WAIT_ON_CE_COUNTER = 0 ME_WAIT_ON_AVAIL_BUFFER = 0 GFX_CNTX_NOT_AVAIL_TO_ME = 0 ME_RCIU_NOT_RDY_TO_RCV = 0 ME_TO_CONST_NOT_RDY_TO_RCV = 0 ME_WAITING_DATA_FROM_PFP = 0 ME_WAITING_ON_PARTIAL_FLUSH = 0 MEQ_TO_ME_NOT_RDY_TO_RCV = 1 STQ_TO_ME_NOT_RDY_TO_RCV = 0 ME_WAITING_DATA_FROM_STQ = 0 PFP_STALLED_ON_TC_WR_CONFIRM = 0 PFP_STALLED_ON_ATOMIC_RTN_DATA = 0 EOPD_FIFO_NEEDS_SC_EOP_DONE = 0 EOPD_FIFO_NEEDS_WR_CONFIRM = 0 STRMO_WR_OF_PRIM_DATA_PENDING = 0 PIPE_STATS_WR_DATA_PENDING = 0 APPEND_RDY_WAIT_ON_CS_DONE = 0 APPEND_RDY_WAIT_ON_PS_DONE = 0 APPEND_WAIT_ON_WR_CONFIRM = 0 APPEND_ACTIVE_PARTITION = 0 APPEND_WAITING_TO_SEND_MEMWRITE = 0 SURF_SYNC_NEEDS_IDLE_CNTXS = 0 SURF_SYNC_NEEDS_ALL_CLEAN = 0 CP_STALLED_STAT3 <- CE_TO_CSF_NOT_RDY_TO_RCV = 0 CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV = 0 CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER = 0 CE_TO_RAM_INIT_NOT_RDY = 0 CE_TO_RAM_DUMP_NOT_RDY = 0 CE_TO_RAM_WRITE_NOT_RDY = 0 CE_TO_INC_FIFO_NOT_RDY_TO_RCV = 0 CE_TO_WR_FIFO_NOT_RDY_TO_RCV = 0 CE_WAITING_ON_BUFFER_DATA = 0 CE_WAITING_ON_CE_BUFFER_FLAG = 0 CE_WAITING_ON_DE_COUNTER = 0 CE_WAITING_ON_DE_COUNTER_UNDERFLOW = 0 TCIU_WAITING_ON_FREE = 0 TCIU_WAITING_ON_TAGS = 0 CE_STALLED_ON_TC_WR_CONFIRM = 0 CE_STALLED_ON_ATOMIC_RTN_DATA = 0 UTCL2IU_WAITING_ON_FREE = 0 UTCL2IU_WAITING_ON_TAGS = 0 UTCL1_WAITING_ON_TRANS = 1 CP_CPC_STATUS <- MEC1_BUSY = 0 MEC2_BUSY = 0 DC0_BUSY = 0 DC1_BUSY = 0 RCIU1_BUSY = 0 RCIU2_BUSY = 0 ROQ1_BUSY = 0 ROQ2_BUSY = 0 TCIU_BUSY = 0 SCRATCH_RAM_BUSY = 0 QU_BUSY = 0 UTCL2IU_BUSY = 0 SAVE_RESTORE_BUSY = 0 CPG_CPC_BUSY = 0 CPF_CPC_BUSY = 0 CPC_BUSY = 0 CP_CPC_STALLED_STAT1 <- RCIU_TX_FREE_STALL = 0 RCIU_PRIV_VIOLATION = 0 TCIU_TX_FREE_STALL = 0 MEC1_DECODING_PACKET = 0 MEC1_WAIT_ON_RCIU = 0 MEC1_WAIT_ON_RCIU_READ = 0 MEC1_WAIT_ON_ROQ_DATA = 0 MEC2_DECODING_PACKET = 0 MEC2_WAIT_ON_RCIU = 0 MEC2_WAIT_ON_RCIU_READ = 0 MEC2_WAIT_ON_ROQ_DATA = 0 UTCL2IU_WAITING_ON_FREE = 0 UTCL2IU_WAITING_ON_TAGS = 0 UTCL1_WAITING_ON_TRANS = 0 CP_CPF_STATUS <- POST_WPTR_GFX_BUSY = 1 CSF_BUSY = 1 ROQ_ALIGN_BUSY = 0 ROQ_RING_BUSY = 1 ROQ_INDIRECT1_BUSY = 1 ROQ_INDIRECT2_BUSY = 0 ROQ_STATE_BUSY = 0 ROQ_CE_RING_BUSY = 0 ROQ_CE_INDIRECT1_BUSY = 0 ROQ_CE_INDIRECT2_BUSY = 0 SEMAPHORE_BUSY = 0 INTERRUPT_BUSY = 0 TCIU_BUSY = 0 HQD_BUSY = 0 PRT_BUSY = 0 UTCL2IU_BUSY = 0 CPF_GFX_BUSY = 1 CPF_CMP_BUSY = 0 GRBM_CPF_STAT_BUSY = 3 CPC_CPF_BUSY = 0 CPF_BUSY = 1 CP_CPF_BUSY_STAT <- REG_BUS_FIFO_BUSY = 0 CSF_RING_BUSY = 1 CSF_INDIRECT1_BUSY = 1 CSF_INDIRECT2_BUSY = 0 CSF_STATE_BUSY = 0 CSF_CE_INDR1_BUSY = 0 CSF_CE_INDR2_BUSY = 0 CSF_ARBITER_BUSY = 0 CSF_INPUT_BUSY = 0 OUTSTANDING_READ_TAGS = 0 HPD_PROCESSING_EOP_BUSY = 0 HQD_DISPATCH_BUSY = 0 HQD_IQ_TIMER_BUSY = 0 HQD_DMA_OFFLOAD_BUSY = 0 HQD_WAIT_SEMAPHORE_BUSY = 0 HQD_SIGNAL_SEMAPHORE_BUSY = 0 HQD_MESSAGE_BUSY = 0 HQD_PQ_FETCHER_BUSY = 0 HQD_IB_FETCHER_BUSY = 0 HQD_IQ_FETCHER_BUSY = 0 HQD_EOP_FETCHER_BUSY = 0 HQD_CONSUMED_RPTR_BUSY = 0 HQD_FETCHER_ARB_BUSY = 0 HQD_ROQ_ALIGN_BUSY = 0 HQD_ROQ_EOP_BUSY = 0 HQD_ROQ_IQ_BUSY = 0 HQD_ROQ_PQ_BUSY = 0 HQD_ROQ_IB_BUSY = 0 HQD_WPTR_POLL_BUSY = 0 HQD_PQ_BUSY = 0 HQD_IB_BUSY = 0 CP_CPF_STALLED_STAT1